1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774e1 SoC 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774e1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774e1-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a774e1"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 /* 21 * The external audio clocks are configured as 0 Hz fixed frequency 22 * clocks by default. 23 * Boards that provide audio clocks should override them. 24 */ 25 audio_clk_a: audio_clk_a { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <0>; 29 }; 30 31 audio_clk_c: audio_clk_c { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 cluster0_opp: opp_table0 { 38 compatible = "operating-points-v2"; 39 opp-shared; 40 41 opp-500000000 { 42 opp-hz = /bits/ 64 <500000000>; 43 opp-microvolt = <820000>; 44 clock-latency-ns = <300000>; 45 }; 46 opp-1000000000 { 47 opp-hz = /bits/ 64 <1000000000>; 48 opp-microvolt = <820000>; 49 clock-latency-ns = <300000>; 50 }; 51 opp-1500000000 { 52 opp-hz = /bits/ 64 <1500000000>; 53 opp-microvolt = <820000>; 54 clock-latency-ns = <300000>; 55 opp-suspend; 56 }; 57 }; 58 59 cluster1_opp: opp_table1 { 60 compatible = "operating-points-v2"; 61 opp-shared; 62 63 opp-800000000 { 64 opp-hz = /bits/ 64 <800000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1000000000 { 69 opp-hz = /bits/ 64 <1000000000>; 70 opp-microvolt = <820000>; 71 clock-latency-ns = <300000>; 72 }; 73 opp-1200000000 { 74 opp-hz = /bits/ 64 <1200000000>; 75 opp-microvolt = <820000>; 76 clock-latency-ns = <300000>; 77 }; 78 }; 79 80 cpus { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 84 cpu-map { 85 cluster0 { 86 core0 { 87 cpu = <&a57_0>; 88 }; 89 core1 { 90 cpu = <&a57_1>; 91 }; 92 core2 { 93 cpu = <&a57_2>; 94 }; 95 core3 { 96 cpu = <&a57_3>; 97 }; 98 }; 99 100 cluster1 { 101 core0 { 102 cpu = <&a53_0>; 103 }; 104 core1 { 105 cpu = <&a53_1>; 106 }; 107 core2 { 108 cpu = <&a53_2>; 109 }; 110 core3 { 111 cpu = <&a53_3>; 112 }; 113 }; 114 }; 115 116 a57_0: cpu@0 { 117 compatible = "arm,cortex-a57"; 118 reg = <0x0>; 119 device_type = "cpu"; 120 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; 121 next-level-cache = <&L2_CA57>; 122 enable-method = "psci"; 123 dynamic-power-coefficient = <854>; 124 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 125 operating-points-v2 = <&cluster0_opp>; 126 capacity-dmips-mhz = <1024>; 127 #cooling-cells = <2>; 128 }; 129 130 a57_1: cpu@1 { 131 compatible = "arm,cortex-a57"; 132 reg = <0x1>; 133 device_type = "cpu"; 134 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; 135 next-level-cache = <&L2_CA57>; 136 enable-method = "psci"; 137 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 138 operating-points-v2 = <&cluster0_opp>; 139 capacity-dmips-mhz = <1024>; 140 #cooling-cells = <2>; 141 }; 142 143 a57_2: cpu@2 { 144 compatible = "arm,cortex-a57"; 145 reg = <0x2>; 146 device_type = "cpu"; 147 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; 148 next-level-cache = <&L2_CA57>; 149 enable-method = "psci"; 150 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 151 operating-points-v2 = <&cluster0_opp>; 152 capacity-dmips-mhz = <1024>; 153 #cooling-cells = <2>; 154 }; 155 156 a57_3: cpu@3 { 157 compatible = "arm,cortex-a57"; 158 reg = <0x3>; 159 device_type = "cpu"; 160 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; 161 next-level-cache = <&L2_CA57>; 162 enable-method = "psci"; 163 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 164 operating-points-v2 = <&cluster0_opp>; 165 capacity-dmips-mhz = <1024>; 166 #cooling-cells = <2>; 167 }; 168 169 a53_0: cpu@100 { 170 compatible = "arm,cortex-a53"; 171 reg = <0x100>; 172 device_type = "cpu"; 173 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; 174 next-level-cache = <&L2_CA53>; 175 enable-method = "psci"; 176 #cooling-cells = <2>; 177 dynamic-power-coefficient = <277>; 178 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 179 operating-points-v2 = <&cluster1_opp>; 180 capacity-dmips-mhz = <535>; 181 }; 182 183 a53_1: cpu@101 { 184 compatible = "arm,cortex-a53"; 185 reg = <0x101>; 186 device_type = "cpu"; 187 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; 188 next-level-cache = <&L2_CA53>; 189 enable-method = "psci"; 190 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 191 operating-points-v2 = <&cluster1_opp>; 192 capacity-dmips-mhz = <535>; 193 }; 194 195 a53_2: cpu@102 { 196 compatible = "arm,cortex-a53"; 197 reg = <0x102>; 198 device_type = "cpu"; 199 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; 200 next-level-cache = <&L2_CA53>; 201 enable-method = "psci"; 202 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 203 operating-points-v2 = <&cluster1_opp>; 204 capacity-dmips-mhz = <535>; 205 }; 206 207 a53_3: cpu@103 { 208 compatible = "arm,cortex-a53"; 209 reg = <0x103>; 210 device_type = "cpu"; 211 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; 212 next-level-cache = <&L2_CA53>; 213 enable-method = "psci"; 214 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 215 operating-points-v2 = <&cluster1_opp>; 216 capacity-dmips-mhz = <535>; 217 }; 218 219 L2_CA57: cache-controller-0 { 220 compatible = "cache"; 221 power-domains = <&sysc R8A774E1_PD_CA57_SCU>; 222 cache-unified; 223 cache-level = <2>; 224 }; 225 226 L2_CA53: cache-controller-1 { 227 compatible = "cache"; 228 power-domains = <&sysc R8A774E1_PD_CA53_SCU>; 229 cache-unified; 230 cache-level = <2>; 231 }; 232 }; 233 234 extal_clk: extal { 235 compatible = "fixed-clock"; 236 #clock-cells = <0>; 237 /* This value must be overridden by the board */ 238 clock-frequency = <0>; 239 }; 240 241 extalr_clk: extalr { 242 compatible = "fixed-clock"; 243 #clock-cells = <0>; 244 /* This value must be overridden by the board */ 245 clock-frequency = <0>; 246 }; 247 248 /* External PCIe clock - can be overridden by the board */ 249 pcie_bus_clk: pcie_bus { 250 compatible = "fixed-clock"; 251 #clock-cells = <0>; 252 clock-frequency = <0>; 253 }; 254 255 pmu_a53 { 256 compatible = "arm,cortex-a53-pmu"; 257 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 258 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 259 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 260 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 261 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 262 }; 263 264 pmu_a57 { 265 compatible = "arm,cortex-a57-pmu"; 266 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 267 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 268 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 269 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 270 interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; 271 }; 272 273 psci { 274 compatible = "arm,psci-1.0", "arm,psci-0.2"; 275 method = "smc"; 276 }; 277 278 /* External SCIF clock - to be overridden by boards that provide it */ 279 scif_clk: scif { 280 compatible = "fixed-clock"; 281 #clock-cells = <0>; 282 clock-frequency = <0>; 283 }; 284 285 soc { 286 compatible = "simple-bus"; 287 interrupt-parent = <&gic>; 288 #address-cells = <2>; 289 #size-cells = <2>; 290 ranges; 291 292 rwdt: watchdog@e6020000 { 293 reg = <0 0xe6020000 0 0x0c>; 294 status = "disabled"; 295 296 /* placeholder */ 297 }; 298 299 gpio0: gpio@e6050000 { 300 compatible = "renesas,gpio-r8a774e1", 301 "renesas,rcar-gen3-gpio"; 302 reg = <0 0xe6050000 0 0x50>; 303 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 304 #gpio-cells = <2>; 305 gpio-controller; 306 gpio-ranges = <&pfc 0 0 16>; 307 #interrupt-cells = <2>; 308 interrupt-controller; 309 clocks = <&cpg CPG_MOD 912>; 310 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 311 resets = <&cpg 912>; 312 }; 313 314 gpio1: gpio@e6051000 { 315 compatible = "renesas,gpio-r8a774e1", 316 "renesas,rcar-gen3-gpio"; 317 reg = <0 0xe6051000 0 0x50>; 318 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 319 #gpio-cells = <2>; 320 gpio-controller; 321 gpio-ranges = <&pfc 0 32 29>; 322 #interrupt-cells = <2>; 323 interrupt-controller; 324 clocks = <&cpg CPG_MOD 911>; 325 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 326 resets = <&cpg 911>; 327 }; 328 329 gpio2: gpio@e6052000 { 330 compatible = "renesas,gpio-r8a774e1", 331 "renesas,rcar-gen3-gpio"; 332 reg = <0 0xe6052000 0 0x50>; 333 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 334 #gpio-cells = <2>; 335 gpio-controller; 336 gpio-ranges = <&pfc 0 64 15>; 337 #interrupt-cells = <2>; 338 interrupt-controller; 339 clocks = <&cpg CPG_MOD 910>; 340 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 341 resets = <&cpg 910>; 342 }; 343 344 gpio3: gpio@e6053000 { 345 compatible = "renesas,gpio-r8a774e1", 346 "renesas,rcar-gen3-gpio"; 347 reg = <0 0xe6053000 0 0x50>; 348 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 349 #gpio-cells = <2>; 350 gpio-controller; 351 gpio-ranges = <&pfc 0 96 16>; 352 #interrupt-cells = <2>; 353 interrupt-controller; 354 clocks = <&cpg CPG_MOD 909>; 355 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 356 resets = <&cpg 909>; 357 }; 358 359 gpio4: gpio@e6054000 { 360 compatible = "renesas,gpio-r8a774e1", 361 "renesas,rcar-gen3-gpio"; 362 reg = <0 0xe6054000 0 0x50>; 363 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 364 #gpio-cells = <2>; 365 gpio-controller; 366 gpio-ranges = <&pfc 0 128 18>; 367 #interrupt-cells = <2>; 368 interrupt-controller; 369 clocks = <&cpg CPG_MOD 908>; 370 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 371 resets = <&cpg 908>; 372 }; 373 374 gpio5: gpio@e6055000 { 375 compatible = "renesas,gpio-r8a774e1", 376 "renesas,rcar-gen3-gpio"; 377 reg = <0 0xe6055000 0 0x50>; 378 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 379 #gpio-cells = <2>; 380 gpio-controller; 381 gpio-ranges = <&pfc 0 160 26>; 382 #interrupt-cells = <2>; 383 interrupt-controller; 384 clocks = <&cpg CPG_MOD 907>; 385 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 386 resets = <&cpg 907>; 387 }; 388 389 gpio6: gpio@e6055400 { 390 compatible = "renesas,gpio-r8a774e1", 391 "renesas,rcar-gen3-gpio"; 392 reg = <0 0xe6055400 0 0x50>; 393 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 394 #gpio-cells = <2>; 395 gpio-controller; 396 gpio-ranges = <&pfc 0 192 32>; 397 #interrupt-cells = <2>; 398 interrupt-controller; 399 clocks = <&cpg CPG_MOD 906>; 400 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 401 resets = <&cpg 906>; 402 }; 403 404 gpio7: gpio@e6055800 { 405 compatible = "renesas,gpio-r8a774e1", 406 "renesas,rcar-gen3-gpio"; 407 reg = <0 0xe6055800 0 0x50>; 408 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 409 #gpio-cells = <2>; 410 gpio-controller; 411 gpio-ranges = <&pfc 0 224 4>; 412 #interrupt-cells = <2>; 413 interrupt-controller; 414 clocks = <&cpg CPG_MOD 905>; 415 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 416 resets = <&cpg 905>; 417 }; 418 419 pfc: pin-controller@e6060000 { 420 compatible = "renesas,pfc-r8a774e1"; 421 reg = <0 0xe6060000 0 0x50c>; 422 }; 423 424 cmt0: timer@e60f0000 { 425 compatible = "renesas,r8a774e1-cmt0", 426 "renesas,rcar-gen3-cmt0"; 427 reg = <0 0xe60f0000 0 0x1004>; 428 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&cpg CPG_MOD 303>; 431 clock-names = "fck"; 432 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 433 resets = <&cpg 303>; 434 status = "disabled"; 435 }; 436 437 cmt1: timer@e6130000 { 438 compatible = "renesas,r8a774e1-cmt1", 439 "renesas,rcar-gen3-cmt1"; 440 reg = <0 0xe6130000 0 0x1004>; 441 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&cpg CPG_MOD 302>; 450 clock-names = "fck"; 451 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 452 resets = <&cpg 302>; 453 status = "disabled"; 454 }; 455 456 cmt2: timer@e6140000 { 457 compatible = "renesas,r8a774e1-cmt1", 458 "renesas,rcar-gen3-cmt1"; 459 reg = <0 0xe6140000 0 0x1004>; 460 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&cpg CPG_MOD 301>; 469 clock-names = "fck"; 470 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 471 resets = <&cpg 301>; 472 status = "disabled"; 473 }; 474 475 cmt3: timer@e6148000 { 476 compatible = "renesas,r8a774e1-cmt1", 477 "renesas,rcar-gen3-cmt1"; 478 reg = <0 0xe6148000 0 0x1004>; 479 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cpg CPG_MOD 300>; 488 clock-names = "fck"; 489 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 490 resets = <&cpg 300>; 491 status = "disabled"; 492 }; 493 494 cpg: clock-controller@e6150000 { 495 compatible = "renesas,r8a774e1-cpg-mssr"; 496 reg = <0 0xe6150000 0 0x1000>; 497 clocks = <&extal_clk>, <&extalr_clk>; 498 clock-names = "extal", "extalr"; 499 #clock-cells = <2>; 500 #power-domain-cells = <0>; 501 #reset-cells = <1>; 502 }; 503 504 rst: reset-controller@e6160000 { 505 compatible = "renesas,r8a774e1-rst"; 506 reg = <0 0xe6160000 0 0x0200>; 507 }; 508 509 sysc: system-controller@e6180000 { 510 compatible = "renesas,r8a774e1-sysc"; 511 reg = <0 0xe6180000 0 0x0400>; 512 #power-domain-cells = <1>; 513 }; 514 515 tsc: thermal@e6198000 { 516 compatible = "renesas,r8a774e1-thermal"; 517 reg = <0 0xe6198000 0 0x100>, 518 <0 0xe61a0000 0 0x100>, 519 <0 0xe61a8000 0 0x100>; 520 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&cpg CPG_MOD 522>; 524 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 525 resets = <&cpg 522>; 526 #thermal-sensor-cells = <1>; 527 }; 528 529 intc_ex: interrupt-controller@e61c0000 { 530 compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; 531 #interrupt-cells = <2>; 532 interrupt-controller; 533 reg = <0 0xe61c0000 0 0x200>; 534 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&cpg CPG_MOD 407>; 541 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 542 resets = <&cpg 407>; 543 }; 544 545 tmu0: timer@e61e0000 { 546 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 547 reg = <0 0xe61e0000 0 0x30>; 548 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&cpg CPG_MOD 125>; 552 clock-names = "fck"; 553 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 554 resets = <&cpg 125>; 555 status = "disabled"; 556 }; 557 558 tmu1: timer@e6fc0000 { 559 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 560 reg = <0 0xe6fc0000 0 0x30>; 561 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&cpg CPG_MOD 124>; 565 clock-names = "fck"; 566 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 567 resets = <&cpg 124>; 568 status = "disabled"; 569 }; 570 571 tmu2: timer@e6fd0000 { 572 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 573 reg = <0 0xe6fd0000 0 0x30>; 574 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&cpg CPG_MOD 123>; 578 clock-names = "fck"; 579 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 580 resets = <&cpg 123>; 581 status = "disabled"; 582 }; 583 584 tmu3: timer@e6fe0000 { 585 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 586 reg = <0 0xe6fe0000 0 0x30>; 587 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&cpg CPG_MOD 122>; 591 clock-names = "fck"; 592 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 593 resets = <&cpg 122>; 594 status = "disabled"; 595 }; 596 597 tmu4: timer@ffc00000 { 598 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 599 reg = <0 0xffc00000 0 0x30>; 600 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&cpg CPG_MOD 121>; 604 clock-names = "fck"; 605 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 606 resets = <&cpg 121>; 607 status = "disabled"; 608 }; 609 610 i2c0: i2c@e6500000 { 611 #address-cells = <1>; 612 #size-cells = <0>; 613 compatible = "renesas,i2c-r8a774e1", 614 "renesas,rcar-gen3-i2c"; 615 reg = <0 0xe6500000 0 0x40>; 616 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&cpg CPG_MOD 931>; 618 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 619 resets = <&cpg 931>; 620 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 621 <&dmac2 0x91>, <&dmac2 0x90>; 622 dma-names = "tx", "rx", "tx", "rx"; 623 i2c-scl-internal-delay-ns = <110>; 624 status = "disabled"; 625 }; 626 627 i2c1: i2c@e6508000 { 628 #address-cells = <1>; 629 #size-cells = <0>; 630 compatible = "renesas,i2c-r8a774e1", 631 "renesas,rcar-gen3-i2c"; 632 reg = <0 0xe6508000 0 0x40>; 633 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&cpg CPG_MOD 930>; 635 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 636 resets = <&cpg 930>; 637 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 638 <&dmac2 0x93>, <&dmac2 0x92>; 639 dma-names = "tx", "rx", "tx", "rx"; 640 i2c-scl-internal-delay-ns = <6>; 641 status = "disabled"; 642 }; 643 644 i2c2: i2c@e6510000 { 645 #address-cells = <1>; 646 #size-cells = <0>; 647 compatible = "renesas,i2c-r8a774e1", 648 "renesas,rcar-gen3-i2c"; 649 reg = <0 0xe6510000 0 0x40>; 650 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&cpg CPG_MOD 929>; 652 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 653 resets = <&cpg 929>; 654 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 655 <&dmac2 0x95>, <&dmac2 0x94>; 656 dma-names = "tx", "rx", "tx", "rx"; 657 i2c-scl-internal-delay-ns = <6>; 658 status = "disabled"; 659 }; 660 661 i2c3: i2c@e66d0000 { 662 #address-cells = <1>; 663 #size-cells = <0>; 664 compatible = "renesas,i2c-r8a774e1", 665 "renesas,rcar-gen3-i2c"; 666 reg = <0 0xe66d0000 0 0x40>; 667 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 668 clocks = <&cpg CPG_MOD 928>; 669 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 670 resets = <&cpg 928>; 671 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 672 dma-names = "tx", "rx"; 673 i2c-scl-internal-delay-ns = <110>; 674 status = "disabled"; 675 }; 676 677 i2c4: i2c@e66d8000 { 678 #address-cells = <1>; 679 #size-cells = <0>; 680 compatible = "renesas,i2c-r8a774e1", 681 "renesas,rcar-gen3-i2c"; 682 reg = <0 0xe66d8000 0 0x40>; 683 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&cpg CPG_MOD 927>; 685 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 686 resets = <&cpg 927>; 687 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 688 dma-names = "tx", "rx"; 689 i2c-scl-internal-delay-ns = <110>; 690 status = "disabled"; 691 }; 692 693 i2c5: i2c@e66e0000 { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 compatible = "renesas,i2c-r8a774e1", 697 "renesas,rcar-gen3-i2c"; 698 reg = <0 0xe66e0000 0 0x40>; 699 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&cpg CPG_MOD 919>; 701 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 702 resets = <&cpg 919>; 703 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 704 dma-names = "tx", "rx"; 705 i2c-scl-internal-delay-ns = <110>; 706 status = "disabled"; 707 }; 708 709 i2c6: i2c@e66e8000 { 710 #address-cells = <1>; 711 #size-cells = <0>; 712 compatible = "renesas,i2c-r8a774e1", 713 "renesas,rcar-gen3-i2c"; 714 reg = <0 0xe66e8000 0 0x40>; 715 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&cpg CPG_MOD 918>; 717 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 718 resets = <&cpg 918>; 719 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 720 dma-names = "tx", "rx"; 721 i2c-scl-internal-delay-ns = <6>; 722 status = "disabled"; 723 }; 724 725 i2c_dvfs: i2c@e60b0000 { 726 #address-cells = <1>; 727 #size-cells = <0>; 728 compatible = "renesas,iic-r8a774e1", 729 "renesas,rcar-gen3-iic", 730 "renesas,rmobile-iic"; 731 reg = <0 0xe60b0000 0 0x425>; 732 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&cpg CPG_MOD 926>; 734 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 735 resets = <&cpg 926>; 736 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 737 dma-names = "tx", "rx"; 738 status = "disabled"; 739 }; 740 741 hscif0: serial@e6540000 { 742 compatible = "renesas,hscif-r8a774e1", 743 "renesas,rcar-gen3-hscif", 744 "renesas,hscif"; 745 reg = <0 0xe6540000 0 0x60>; 746 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&cpg CPG_MOD 520>, 748 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 749 <&scif_clk>; 750 clock-names = "fck", "brg_int", "scif_clk"; 751 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 752 <&dmac2 0x31>, <&dmac2 0x30>; 753 dma-names = "tx", "rx", "tx", "rx"; 754 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 755 resets = <&cpg 520>; 756 status = "disabled"; 757 }; 758 759 hscif1: serial@e6550000 { 760 compatible = "renesas,hscif-r8a774e1", 761 "renesas,rcar-gen3-hscif", 762 "renesas,hscif"; 763 reg = <0 0xe6550000 0 0x60>; 764 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&cpg CPG_MOD 519>, 766 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 767 <&scif_clk>; 768 clock-names = "fck", "brg_int", "scif_clk"; 769 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 770 <&dmac2 0x33>, <&dmac2 0x32>; 771 dma-names = "tx", "rx", "tx", "rx"; 772 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 773 resets = <&cpg 519>; 774 status = "disabled"; 775 }; 776 777 hscif2: serial@e6560000 { 778 compatible = "renesas,hscif-r8a774e1", 779 "renesas,rcar-gen3-hscif", 780 "renesas,hscif"; 781 reg = <0 0xe6560000 0 0x60>; 782 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&cpg CPG_MOD 518>, 784 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 785 <&scif_clk>; 786 clock-names = "fck", "brg_int", "scif_clk"; 787 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 788 <&dmac2 0x35>, <&dmac2 0x34>; 789 dma-names = "tx", "rx", "tx", "rx"; 790 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 791 resets = <&cpg 518>; 792 status = "disabled"; 793 }; 794 795 hscif3: serial@e66a0000 { 796 compatible = "renesas,hscif-r8a774e1", 797 "renesas,rcar-gen3-hscif", 798 "renesas,hscif"; 799 reg = <0 0xe66a0000 0 0x60>; 800 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&cpg CPG_MOD 517>, 802 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 803 <&scif_clk>; 804 clock-names = "fck", "brg_int", "scif_clk"; 805 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 806 dma-names = "tx", "rx"; 807 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 808 resets = <&cpg 517>; 809 status = "disabled"; 810 }; 811 812 hscif4: serial@e66b0000 { 813 compatible = "renesas,hscif-r8a774e1", 814 "renesas,rcar-gen3-hscif", 815 "renesas,hscif"; 816 reg = <0 0xe66b0000 0 0x60>; 817 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&cpg CPG_MOD 516>, 819 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 820 <&scif_clk>; 821 clock-names = "fck", "brg_int", "scif_clk"; 822 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 823 dma-names = "tx", "rx"; 824 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 825 resets = <&cpg 516>; 826 status = "disabled"; 827 }; 828 829 hsusb: usb@e6590000 { 830 reg = <0 0xe6590000 0 0x200>; 831 status = "disabled"; 832 833 /* placeholder */ 834 }; 835 836 usb3_phy0: usb-phy@e65ee000 { 837 reg = <0 0xe65ee000 0 0x90>; 838 #phy-cells = <0>; 839 status = "disabled"; 840 841 /* placeholder */ 842 }; 843 844 dmac0: dma-controller@e6700000 { 845 compatible = "renesas,dmac-r8a774e1", 846 "renesas,rcar-dmac"; 847 reg = <0 0xe6700000 0 0x10000>; 848 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 865 interrupt-names = "error", 866 "ch0", "ch1", "ch2", "ch3", 867 "ch4", "ch5", "ch6", "ch7", 868 "ch8", "ch9", "ch10", "ch11", 869 "ch12", "ch13", "ch14", "ch15"; 870 clocks = <&cpg CPG_MOD 219>; 871 clock-names = "fck"; 872 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 873 resets = <&cpg 219>; 874 #dma-cells = <1>; 875 dma-channels = <16>; 876 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 877 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 878 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 879 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 880 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 881 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 882 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 883 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 884 }; 885 886 dmac1: dma-controller@e7300000 { 887 compatible = "renesas,dmac-r8a774e1", 888 "renesas,rcar-dmac"; 889 reg = <0 0xe7300000 0 0x10000>; 890 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 907 interrupt-names = "error", 908 "ch0", "ch1", "ch2", "ch3", 909 "ch4", "ch5", "ch6", "ch7", 910 "ch8", "ch9", "ch10", "ch11", 911 "ch12", "ch13", "ch14", "ch15"; 912 clocks = <&cpg CPG_MOD 218>; 913 clock-names = "fck"; 914 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 915 resets = <&cpg 218>; 916 #dma-cells = <1>; 917 dma-channels = <16>; 918 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 919 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 920 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 921 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 922 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 923 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 924 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 925 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 926 }; 927 928 dmac2: dma-controller@e7310000 { 929 compatible = "renesas,dmac-r8a774e1", 930 "renesas,rcar-dmac"; 931 reg = <0 0xe7310000 0 0x10000>; 932 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 949 interrupt-names = "error", 950 "ch0", "ch1", "ch2", "ch3", 951 "ch4", "ch5", "ch6", "ch7", 952 "ch8", "ch9", "ch10", "ch11", 953 "ch12", "ch13", "ch14", "ch15"; 954 clocks = <&cpg CPG_MOD 217>; 955 clock-names = "fck"; 956 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 957 resets = <&cpg 217>; 958 #dma-cells = <1>; 959 dma-channels = <16>; 960 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 961 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 962 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 963 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 964 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 965 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 966 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 967 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 968 }; 969 970 ipmmu_ds0: iommu@e6740000 { 971 compatible = "renesas,ipmmu-r8a774e1"; 972 reg = <0 0xe6740000 0 0x1000>; 973 renesas,ipmmu-main = <&ipmmu_mm 0>; 974 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 975 #iommu-cells = <1>; 976 }; 977 978 ipmmu_ds1: iommu@e7740000 { 979 compatible = "renesas,ipmmu-r8a774e1"; 980 reg = <0 0xe7740000 0 0x1000>; 981 renesas,ipmmu-main = <&ipmmu_mm 1>; 982 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 983 #iommu-cells = <1>; 984 }; 985 986 ipmmu_hc: iommu@e6570000 { 987 compatible = "renesas,ipmmu-r8a774e1"; 988 reg = <0 0xe6570000 0 0x1000>; 989 renesas,ipmmu-main = <&ipmmu_mm 2>; 990 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 991 #iommu-cells = <1>; 992 }; 993 994 ipmmu_mm: iommu@e67b0000 { 995 compatible = "renesas,ipmmu-r8a774e1"; 996 reg = <0 0xe67b0000 0 0x1000>; 997 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 999 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1000 #iommu-cells = <1>; 1001 }; 1002 1003 ipmmu_mp0: iommu@ec670000 { 1004 compatible = "renesas,ipmmu-r8a774e1"; 1005 reg = <0 0xec670000 0 0x1000>; 1006 renesas,ipmmu-main = <&ipmmu_mm 4>; 1007 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1008 #iommu-cells = <1>; 1009 }; 1010 1011 ipmmu_pv0: iommu@fd800000 { 1012 compatible = "renesas,ipmmu-r8a774e1"; 1013 reg = <0 0xfd800000 0 0x1000>; 1014 renesas,ipmmu-main = <&ipmmu_mm 6>; 1015 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1016 #iommu-cells = <1>; 1017 }; 1018 1019 ipmmu_pv1: iommu@fd950000 { 1020 compatible = "renesas,ipmmu-r8a774e1"; 1021 reg = <0 0xfd950000 0 0x1000>; 1022 renesas,ipmmu-main = <&ipmmu_mm 7>; 1023 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1024 #iommu-cells = <1>; 1025 }; 1026 1027 ipmmu_pv2: iommu@fd960000 { 1028 compatible = "renesas,ipmmu-r8a774e1"; 1029 reg = <0 0xfd960000 0 0x1000>; 1030 renesas,ipmmu-main = <&ipmmu_mm 8>; 1031 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1032 #iommu-cells = <1>; 1033 }; 1034 1035 ipmmu_pv3: iommu@fd970000 { 1036 compatible = "renesas,ipmmu-r8a774e1"; 1037 reg = <0 0xfd970000 0 0x1000>; 1038 renesas,ipmmu-main = <&ipmmu_mm 9>; 1039 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1040 #iommu-cells = <1>; 1041 }; 1042 1043 ipmmu_vc0: iommu@fe6b0000 { 1044 compatible = "renesas,ipmmu-r8a774e1"; 1045 reg = <0 0xfe6b0000 0 0x1000>; 1046 renesas,ipmmu-main = <&ipmmu_mm 12>; 1047 power-domains = <&sysc R8A774E1_PD_A3VC>; 1048 #iommu-cells = <1>; 1049 }; 1050 1051 ipmmu_vc1: iommu@fe6f0000 { 1052 compatible = "renesas,ipmmu-r8a774e1"; 1053 reg = <0 0xfe6f0000 0 0x1000>; 1054 renesas,ipmmu-main = <&ipmmu_mm 13>; 1055 power-domains = <&sysc R8A774E1_PD_A3VC>; 1056 #iommu-cells = <1>; 1057 }; 1058 1059 ipmmu_vi0: iommu@febd0000 { 1060 compatible = "renesas,ipmmu-r8a774e1"; 1061 reg = <0 0xfebd0000 0 0x1000>; 1062 renesas,ipmmu-main = <&ipmmu_mm 14>; 1063 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1064 #iommu-cells = <1>; 1065 }; 1066 1067 ipmmu_vi1: iommu@febe0000 { 1068 compatible = "renesas,ipmmu-r8a774e1"; 1069 reg = <0 0xfebe0000 0 0x1000>; 1070 renesas,ipmmu-main = <&ipmmu_mm 15>; 1071 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1072 #iommu-cells = <1>; 1073 }; 1074 1075 ipmmu_vp0: iommu@fe990000 { 1076 compatible = "renesas,ipmmu-r8a774e1"; 1077 reg = <0 0xfe990000 0 0x1000>; 1078 renesas,ipmmu-main = <&ipmmu_mm 16>; 1079 power-domains = <&sysc R8A774E1_PD_A3VP>; 1080 #iommu-cells = <1>; 1081 }; 1082 1083 ipmmu_vp1: iommu@fe980000 { 1084 compatible = "renesas,ipmmu-r8a774e1"; 1085 reg = <0 0xfe980000 0 0x1000>; 1086 renesas,ipmmu-main = <&ipmmu_mm 17>; 1087 power-domains = <&sysc R8A774E1_PD_A3VP>; 1088 #iommu-cells = <1>; 1089 }; 1090 1091 avb: ethernet@e6800000 { 1092 compatible = "renesas,etheravb-r8a774e1", 1093 "renesas,etheravb-rcar-gen3"; 1094 reg = <0 0xe6800000 0 0x800>; 1095 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1120 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1121 "ch4", "ch5", "ch6", "ch7", 1122 "ch8", "ch9", "ch10", "ch11", 1123 "ch12", "ch13", "ch14", "ch15", 1124 "ch16", "ch17", "ch18", "ch19", 1125 "ch20", "ch21", "ch22", "ch23", 1126 "ch24"; 1127 clocks = <&cpg CPG_MOD 812>; 1128 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1129 resets = <&cpg 812>; 1130 phy-mode = "rgmii"; 1131 iommus = <&ipmmu_ds0 16>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 status = "disabled"; 1135 }; 1136 1137 can0: can@e6c30000 { 1138 reg = <0 0xe6c30000 0 0x1000>; 1139 status = "disabled"; 1140 1141 /* placeholder */ 1142 }; 1143 1144 can1: can@e6c38000 { 1145 reg = <0 0xe6c38000 0 0x1000>; 1146 status = "disabled"; 1147 1148 /* placeholder */ 1149 }; 1150 1151 pwm0: pwm@e6e30000 { 1152 reg = <0 0xe6e30000 0 0x8>; 1153 #pwm-cells = <2>; 1154 status = "disabled"; 1155 1156 /* placeholder */ 1157 }; 1158 1159 scif0: serial@e6e60000 { 1160 compatible = "renesas,scif-r8a774e1", 1161 "renesas,rcar-gen3-scif", "renesas,scif"; 1162 reg = <0 0xe6e60000 0 0x40>; 1163 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1164 clocks = <&cpg CPG_MOD 207>, 1165 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1166 <&scif_clk>; 1167 clock-names = "fck", "brg_int", "scif_clk"; 1168 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1169 <&dmac2 0x51>, <&dmac2 0x50>; 1170 dma-names = "tx", "rx", "tx", "rx"; 1171 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1172 resets = <&cpg 207>; 1173 status = "disabled"; 1174 }; 1175 1176 scif1: serial@e6e68000 { 1177 compatible = "renesas,scif-r8a774e1", 1178 "renesas,rcar-gen3-scif", "renesas,scif"; 1179 reg = <0 0xe6e68000 0 0x40>; 1180 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1181 clocks = <&cpg CPG_MOD 206>, 1182 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1183 <&scif_clk>; 1184 clock-names = "fck", "brg_int", "scif_clk"; 1185 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1186 <&dmac2 0x53>, <&dmac2 0x52>; 1187 dma-names = "tx", "rx", "tx", "rx"; 1188 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1189 resets = <&cpg 206>; 1190 status = "disabled"; 1191 }; 1192 1193 scif2: serial@e6e88000 { 1194 compatible = "renesas,scif-r8a774e1", 1195 "renesas,rcar-gen3-scif", "renesas,scif"; 1196 reg = <0 0xe6e88000 0 0x40>; 1197 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&cpg CPG_MOD 310>, 1199 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1200 <&scif_clk>; 1201 clock-names = "fck", "brg_int", "scif_clk"; 1202 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1203 <&dmac2 0x13>, <&dmac2 0x12>; 1204 dma-names = "tx", "rx", "tx", "rx"; 1205 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1206 resets = <&cpg 310>; 1207 status = "disabled"; 1208 }; 1209 1210 scif3: serial@e6c50000 { 1211 compatible = "renesas,scif-r8a774e1", 1212 "renesas,rcar-gen3-scif", "renesas,scif"; 1213 reg = <0 0xe6c50000 0 0x40>; 1214 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1215 clocks = <&cpg CPG_MOD 204>, 1216 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1217 <&scif_clk>; 1218 clock-names = "fck", "brg_int", "scif_clk"; 1219 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1220 dma-names = "tx", "rx"; 1221 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1222 resets = <&cpg 204>; 1223 status = "disabled"; 1224 }; 1225 1226 scif4: serial@e6c40000 { 1227 compatible = "renesas,scif-r8a774e1", 1228 "renesas,rcar-gen3-scif", "renesas,scif"; 1229 reg = <0 0xe6c40000 0 0x40>; 1230 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&cpg CPG_MOD 203>, 1232 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1233 <&scif_clk>; 1234 clock-names = "fck", "brg_int", "scif_clk"; 1235 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1236 dma-names = "tx", "rx"; 1237 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1238 resets = <&cpg 203>; 1239 status = "disabled"; 1240 }; 1241 1242 scif5: serial@e6f30000 { 1243 compatible = "renesas,scif-r8a774e1", 1244 "renesas,rcar-gen3-scif", "renesas,scif"; 1245 reg = <0 0xe6f30000 0 0x40>; 1246 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1247 clocks = <&cpg CPG_MOD 202>, 1248 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1249 <&scif_clk>; 1250 clock-names = "fck", "brg_int", "scif_clk"; 1251 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1252 <&dmac2 0x5b>, <&dmac2 0x5a>; 1253 dma-names = "tx", "rx", "tx", "rx"; 1254 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1255 resets = <&cpg 202>; 1256 status = "disabled"; 1257 }; 1258 1259 rcar_sound: sound@ec500000 { 1260 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1261 <0 0xec5a0000 0 0x100>, /* ADG */ 1262 <0 0xec540000 0 0x1000>, /* SSIU */ 1263 <0 0xec541000 0 0x280>, /* SSI */ 1264 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1265 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1266 1267 status = "disabled"; 1268 1269 /* placeholder */ 1270 1271 rcar_sound,ssi { 1272 ssi2: ssi-2 { 1273 /* placeholder */ 1274 }; 1275 }; 1276 }; 1277 1278 xhci0: usb@ee000000 { 1279 reg = <0 0xee000000 0 0xc00>; 1280 status = "disabled"; 1281 1282 /* placeholder */ 1283 }; 1284 1285 usb3_peri0: usb@ee020000 { 1286 reg = <0 0xee020000 0 0x400>; 1287 status = "disabled"; 1288 1289 /* placeholder */ 1290 }; 1291 1292 ohci0: usb@ee080000 { 1293 reg = <0 0xee080000 0 0x100>; 1294 status = "disabled"; 1295 1296 /* placeholder */ 1297 }; 1298 1299 ohci1: usb@ee0a0000 { 1300 reg = <0 0xee0a0000 0 0x100>; 1301 status = "disabled"; 1302 1303 /* placeholder */ 1304 }; 1305 1306 ehci0: usb@ee080100 { 1307 reg = <0 0xee080100 0 0x100>; 1308 status = "disabled"; 1309 1310 /* placeholder */ 1311 }; 1312 1313 ehci1: usb@ee0a0100 { 1314 reg = <0 0xee0a0100 0 0x100>; 1315 status = "disabled"; 1316 1317 /* placeholder */ 1318 }; 1319 1320 usb2_phy0: usb-phy@ee080200 { 1321 reg = <0 0xee080200 0 0x700>; 1322 status = "disabled"; 1323 1324 /* placeholder */ 1325 }; 1326 1327 usb2_phy1: usb-phy@ee0a0200 { 1328 reg = <0 0xee0a0200 0 0x700>; 1329 status = "disabled"; 1330 1331 /* placeholder */ 1332 }; 1333 1334 sdhi0: mmc@ee100000 { 1335 compatible = "renesas,sdhi-r8a774e1", 1336 "renesas,rcar-gen3-sdhi"; 1337 reg = <0 0xee100000 0 0x2000>; 1338 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1339 clocks = <&cpg CPG_MOD 314>; 1340 max-frequency = <200000000>; 1341 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1342 resets = <&cpg 314>; 1343 iommus = <&ipmmu_ds1 32>; 1344 status = "disabled"; 1345 }; 1346 1347 sdhi1: mmc@ee120000 { 1348 compatible = "renesas,sdhi-r8a774e1", 1349 "renesas,rcar-gen3-sdhi"; 1350 reg = <0 0xee120000 0 0x2000>; 1351 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1352 clocks = <&cpg CPG_MOD 313>; 1353 max-frequency = <200000000>; 1354 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1355 resets = <&cpg 313>; 1356 iommus = <&ipmmu_ds1 33>; 1357 status = "disabled"; 1358 }; 1359 1360 sdhi2: mmc@ee140000 { 1361 compatible = "renesas,sdhi-r8a774e1", 1362 "renesas,rcar-gen3-sdhi"; 1363 reg = <0 0xee140000 0 0x2000>; 1364 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1365 clocks = <&cpg CPG_MOD 312>; 1366 max-frequency = <200000000>; 1367 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1368 resets = <&cpg 312>; 1369 iommus = <&ipmmu_ds1 34>; 1370 status = "disabled"; 1371 }; 1372 1373 sdhi3: mmc@ee160000 { 1374 compatible = "renesas,sdhi-r8a774e1", 1375 "renesas,rcar-gen3-sdhi"; 1376 reg = <0 0xee160000 0 0x2000>; 1377 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1378 clocks = <&cpg CPG_MOD 311>; 1379 max-frequency = <200000000>; 1380 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1381 resets = <&cpg 311>; 1382 iommus = <&ipmmu_ds1 35>; 1383 status = "disabled"; 1384 }; 1385 1386 gic: interrupt-controller@f1010000 { 1387 compatible = "arm,gic-400"; 1388 #interrupt-cells = <3>; 1389 #address-cells = <0>; 1390 interrupt-controller; 1391 reg = <0x0 0xf1010000 0 0x1000>, 1392 <0x0 0xf1020000 0 0x20000>, 1393 <0x0 0xf1040000 0 0x20000>, 1394 <0x0 0xf1060000 0 0x20000>; 1395 interrupts = <GIC_PPI 9 1396 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1397 clocks = <&cpg CPG_MOD 408>; 1398 clock-names = "clk"; 1399 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1400 resets = <&cpg 408>; 1401 }; 1402 1403 pciec0: pcie@fe000000 { 1404 reg = <0 0xfe000000 0 0x80000>; 1405 #address-cells = <3>; 1406 #size-cells = <2>; 1407 status = "disabled"; 1408 1409 /* placeholder */ 1410 }; 1411 1412 hdmi0: hdmi@fead0000 { 1413 reg = <0 0xfead0000 0 0x10000>; 1414 status = "disabled"; 1415 1416 /* placeholder */ 1417 1418 ports { 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 1422 port@0 { 1423 reg = <0>; 1424 }; 1425 port@1 { 1426 reg = <1>; 1427 }; 1428 port@2 { 1429 reg = <2>; 1430 }; 1431 }; 1432 }; 1433 1434 du: display@feb00000 { 1435 reg = <0 0xfeb00000 0 0x80000>; 1436 status = "disabled"; 1437 1438 /* placeholder */ 1439 ports { 1440 #address-cells = <1>; 1441 #size-cells = <0>; 1442 1443 port@0 { 1444 reg = <0>; 1445 }; 1446 port@1 { 1447 reg = <1>; 1448 }; 1449 port@2 { 1450 reg = <2>; 1451 }; 1452 }; 1453 }; 1454 1455 prr: chipid@fff00044 { 1456 compatible = "renesas,prr"; 1457 reg = <0 0xfff00044 0 4>; 1458 }; 1459 }; 1460 1461 thermal-zones { 1462 sensor_thermal1: sensor-thermal1 { 1463 polling-delay-passive = <250>; 1464 polling-delay = <1000>; 1465 thermal-sensors = <&tsc 0>; 1466 sustainable-power = <6313>; 1467 1468 trips { 1469 sensor1_crit: sensor1-crit { 1470 temperature = <120000>; 1471 hysteresis = <1000>; 1472 type = "critical"; 1473 }; 1474 }; 1475 }; 1476 1477 sensor_thermal2: sensor-thermal2 { 1478 polling-delay-passive = <250>; 1479 polling-delay = <1000>; 1480 thermal-sensors = <&tsc 1>; 1481 sustainable-power = <6313>; 1482 1483 trips { 1484 sensor2_crit: sensor2-crit { 1485 temperature = <120000>; 1486 hysteresis = <1000>; 1487 type = "critical"; 1488 }; 1489 }; 1490 }; 1491 1492 sensor_thermal3: sensor-thermal3 { 1493 polling-delay-passive = <250>; 1494 polling-delay = <1000>; 1495 thermal-sensors = <&tsc 2>; 1496 sustainable-power = <6313>; 1497 1498 trips { 1499 target: trip-point1 { 1500 temperature = <100000>; 1501 hysteresis = <1000>; 1502 type = "passive"; 1503 }; 1504 1505 sensor3_crit: sensor3-crit { 1506 temperature = <120000>; 1507 hysteresis = <1000>; 1508 type = "critical"; 1509 }; 1510 }; 1511 1512 cooling-maps { 1513 map0 { 1514 trip = <&target>; 1515 cooling-device = <&a57_0 0 2>; 1516 contribution = <1024>; 1517 }; 1518 1519 map1 { 1520 trip = <&target>; 1521 cooling-device = <&a53_0 0 2>; 1522 contribution = <1024>; 1523 }; 1524 }; 1525 }; 1526 }; 1527 1528 timer { 1529 compatible = "arm,armv8-timer"; 1530 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1531 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1532 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1533 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1534 }; 1535 1536 /* External USB clocks - can be overridden by the board */ 1537 usb3s0_clk: usb3s0 { 1538 compatible = "fixed-clock"; 1539 #clock-cells = <0>; 1540 clock-frequency = <0>; 1541 }; 1542 1543 usb_extal_clk: usb_extal { 1544 compatible = "fixed-clock"; 1545 #clock-cells = <0>; 1546 clock-frequency = <0>; 1547 }; 1548}; 1549