1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774e1 SoC 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774e1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774e1-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a774e1"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 /* 21 * The external audio clocks are configured as 0 Hz fixed frequency 22 * clocks by default. 23 * Boards that provide audio clocks should override them. 24 */ 25 audio_clk_a: audio_clk_a { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <0>; 29 }; 30 31 audio_clk_c: audio_clk_c { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* External CAN clock - to be overridden by boards that provide it */ 38 can_clk: can { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <0>; 42 }; 43 44 cluster0_opp: opp_table0 { 45 compatible = "operating-points-v2"; 46 opp-shared; 47 48 opp-500000000 { 49 opp-hz = /bits/ 64 <500000000>; 50 opp-microvolt = <820000>; 51 clock-latency-ns = <300000>; 52 }; 53 opp-1000000000 { 54 opp-hz = /bits/ 64 <1000000000>; 55 opp-microvolt = <820000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1500000000 { 59 opp-hz = /bits/ 64 <1500000000>; 60 opp-microvolt = <820000>; 61 clock-latency-ns = <300000>; 62 opp-suspend; 63 }; 64 }; 65 66 cluster1_opp: opp_table1 { 67 compatible = "operating-points-v2"; 68 opp-shared; 69 70 opp-800000000 { 71 opp-hz = /bits/ 64 <800000000>; 72 opp-microvolt = <820000>; 73 clock-latency-ns = <300000>; 74 }; 75 opp-1000000000 { 76 opp-hz = /bits/ 64 <1000000000>; 77 opp-microvolt = <820000>; 78 clock-latency-ns = <300000>; 79 }; 80 opp-1200000000 { 81 opp-hz = /bits/ 64 <1200000000>; 82 opp-microvolt = <820000>; 83 clock-latency-ns = <300000>; 84 }; 85 }; 86 87 cpus { 88 #address-cells = <1>; 89 #size-cells = <0>; 90 91 cpu-map { 92 cluster0 { 93 core0 { 94 cpu = <&a57_0>; 95 }; 96 core1 { 97 cpu = <&a57_1>; 98 }; 99 core2 { 100 cpu = <&a57_2>; 101 }; 102 core3 { 103 cpu = <&a57_3>; 104 }; 105 }; 106 107 cluster1 { 108 core0 { 109 cpu = <&a53_0>; 110 }; 111 core1 { 112 cpu = <&a53_1>; 113 }; 114 core2 { 115 cpu = <&a53_2>; 116 }; 117 core3 { 118 cpu = <&a53_3>; 119 }; 120 }; 121 }; 122 123 a57_0: cpu@0 { 124 compatible = "arm,cortex-a57"; 125 reg = <0x0>; 126 device_type = "cpu"; 127 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; 128 next-level-cache = <&L2_CA57>; 129 enable-method = "psci"; 130 cpu-idle-states = <&CPU_SLEEP_0>; 131 dynamic-power-coefficient = <854>; 132 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 133 operating-points-v2 = <&cluster0_opp>; 134 capacity-dmips-mhz = <1024>; 135 #cooling-cells = <2>; 136 }; 137 138 a57_1: cpu@1 { 139 compatible = "arm,cortex-a57"; 140 reg = <0x1>; 141 device_type = "cpu"; 142 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; 143 next-level-cache = <&L2_CA57>; 144 enable-method = "psci"; 145 cpu-idle-states = <&CPU_SLEEP_0>; 146 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 147 operating-points-v2 = <&cluster0_opp>; 148 capacity-dmips-mhz = <1024>; 149 #cooling-cells = <2>; 150 }; 151 152 a57_2: cpu@2 { 153 compatible = "arm,cortex-a57"; 154 reg = <0x2>; 155 device_type = "cpu"; 156 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; 157 next-level-cache = <&L2_CA57>; 158 enable-method = "psci"; 159 cpu-idle-states = <&CPU_SLEEP_0>; 160 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 161 operating-points-v2 = <&cluster0_opp>; 162 capacity-dmips-mhz = <1024>; 163 #cooling-cells = <2>; 164 }; 165 166 a57_3: cpu@3 { 167 compatible = "arm,cortex-a57"; 168 reg = <0x3>; 169 device_type = "cpu"; 170 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; 171 next-level-cache = <&L2_CA57>; 172 enable-method = "psci"; 173 cpu-idle-states = <&CPU_SLEEP_0>; 174 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 175 operating-points-v2 = <&cluster0_opp>; 176 capacity-dmips-mhz = <1024>; 177 #cooling-cells = <2>; 178 }; 179 180 a53_0: cpu@100 { 181 compatible = "arm,cortex-a53"; 182 reg = <0x100>; 183 device_type = "cpu"; 184 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; 185 next-level-cache = <&L2_CA53>; 186 enable-method = "psci"; 187 cpu-idle-states = <&CPU_SLEEP_1>; 188 #cooling-cells = <2>; 189 dynamic-power-coefficient = <277>; 190 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 191 operating-points-v2 = <&cluster1_opp>; 192 capacity-dmips-mhz = <535>; 193 }; 194 195 a53_1: cpu@101 { 196 compatible = "arm,cortex-a53"; 197 reg = <0x101>; 198 device_type = "cpu"; 199 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; 200 next-level-cache = <&L2_CA53>; 201 enable-method = "psci"; 202 cpu-idle-states = <&CPU_SLEEP_1>; 203 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 204 operating-points-v2 = <&cluster1_opp>; 205 capacity-dmips-mhz = <535>; 206 }; 207 208 a53_2: cpu@102 { 209 compatible = "arm,cortex-a53"; 210 reg = <0x102>; 211 device_type = "cpu"; 212 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; 213 next-level-cache = <&L2_CA53>; 214 enable-method = "psci"; 215 cpu-idle-states = <&CPU_SLEEP_1>; 216 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 217 operating-points-v2 = <&cluster1_opp>; 218 capacity-dmips-mhz = <535>; 219 }; 220 221 a53_3: cpu@103 { 222 compatible = "arm,cortex-a53"; 223 reg = <0x103>; 224 device_type = "cpu"; 225 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; 226 next-level-cache = <&L2_CA53>; 227 enable-method = "psci"; 228 cpu-idle-states = <&CPU_SLEEP_1>; 229 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 230 operating-points-v2 = <&cluster1_opp>; 231 capacity-dmips-mhz = <535>; 232 }; 233 234 L2_CA57: cache-controller-0 { 235 compatible = "cache"; 236 power-domains = <&sysc R8A774E1_PD_CA57_SCU>; 237 cache-unified; 238 cache-level = <2>; 239 }; 240 241 L2_CA53: cache-controller-1 { 242 compatible = "cache"; 243 power-domains = <&sysc R8A774E1_PD_CA53_SCU>; 244 cache-unified; 245 cache-level = <2>; 246 }; 247 248 idle-states { 249 entry-method = "psci"; 250 251 CPU_SLEEP_0: cpu-sleep-0 { 252 compatible = "arm,idle-state"; 253 arm,psci-suspend-param = <0x0010000>; 254 local-timer-stop; 255 entry-latency-us = <400>; 256 exit-latency-us = <500>; 257 min-residency-us = <4000>; 258 }; 259 260 CPU_SLEEP_1: cpu-sleep-1 { 261 compatible = "arm,idle-state"; 262 arm,psci-suspend-param = <0x0010000>; 263 local-timer-stop; 264 entry-latency-us = <700>; 265 exit-latency-us = <700>; 266 min-residency-us = <5000>; 267 }; 268 }; 269 }; 270 271 extal_clk: extal { 272 compatible = "fixed-clock"; 273 #clock-cells = <0>; 274 /* This value must be overridden by the board */ 275 clock-frequency = <0>; 276 }; 277 278 extalr_clk: extalr { 279 compatible = "fixed-clock"; 280 #clock-cells = <0>; 281 /* This value must be overridden by the board */ 282 clock-frequency = <0>; 283 }; 284 285 /* External PCIe clock - can be overridden by the board */ 286 pcie_bus_clk: pcie_bus { 287 compatible = "fixed-clock"; 288 #clock-cells = <0>; 289 clock-frequency = <0>; 290 }; 291 292 pmu_a53 { 293 compatible = "arm,cortex-a53-pmu"; 294 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 295 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 296 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 297 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 298 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 299 }; 300 301 pmu_a57 { 302 compatible = "arm,cortex-a57-pmu"; 303 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 304 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 305 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 306 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 307 interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; 308 }; 309 310 psci { 311 compatible = "arm,psci-1.0", "arm,psci-0.2"; 312 method = "smc"; 313 }; 314 315 /* External SCIF clock - to be overridden by boards that provide it */ 316 scif_clk: scif { 317 compatible = "fixed-clock"; 318 #clock-cells = <0>; 319 clock-frequency = <0>; 320 }; 321 322 soc { 323 compatible = "simple-bus"; 324 interrupt-parent = <&gic>; 325 #address-cells = <2>; 326 #size-cells = <2>; 327 ranges; 328 329 rwdt: watchdog@e6020000 { 330 compatible = "renesas,r8a774e1-wdt", 331 "renesas,rcar-gen3-wdt"; 332 reg = <0 0xe6020000 0 0x0c>; 333 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&cpg CPG_MOD 402>; 335 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 336 resets = <&cpg 402>; 337 status = "disabled"; 338 }; 339 340 gpio0: gpio@e6050000 { 341 compatible = "renesas,gpio-r8a774e1", 342 "renesas,rcar-gen3-gpio"; 343 reg = <0 0xe6050000 0 0x50>; 344 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 345 #gpio-cells = <2>; 346 gpio-controller; 347 gpio-ranges = <&pfc 0 0 16>; 348 #interrupt-cells = <2>; 349 interrupt-controller; 350 clocks = <&cpg CPG_MOD 912>; 351 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 352 resets = <&cpg 912>; 353 }; 354 355 gpio1: gpio@e6051000 { 356 compatible = "renesas,gpio-r8a774e1", 357 "renesas,rcar-gen3-gpio"; 358 reg = <0 0xe6051000 0 0x50>; 359 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 360 #gpio-cells = <2>; 361 gpio-controller; 362 gpio-ranges = <&pfc 0 32 29>; 363 #interrupt-cells = <2>; 364 interrupt-controller; 365 clocks = <&cpg CPG_MOD 911>; 366 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 367 resets = <&cpg 911>; 368 }; 369 370 gpio2: gpio@e6052000 { 371 compatible = "renesas,gpio-r8a774e1", 372 "renesas,rcar-gen3-gpio"; 373 reg = <0 0xe6052000 0 0x50>; 374 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 375 #gpio-cells = <2>; 376 gpio-controller; 377 gpio-ranges = <&pfc 0 64 15>; 378 #interrupt-cells = <2>; 379 interrupt-controller; 380 clocks = <&cpg CPG_MOD 910>; 381 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 382 resets = <&cpg 910>; 383 }; 384 385 gpio3: gpio@e6053000 { 386 compatible = "renesas,gpio-r8a774e1", 387 "renesas,rcar-gen3-gpio"; 388 reg = <0 0xe6053000 0 0x50>; 389 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 390 #gpio-cells = <2>; 391 gpio-controller; 392 gpio-ranges = <&pfc 0 96 16>; 393 #interrupt-cells = <2>; 394 interrupt-controller; 395 clocks = <&cpg CPG_MOD 909>; 396 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 397 resets = <&cpg 909>; 398 }; 399 400 gpio4: gpio@e6054000 { 401 compatible = "renesas,gpio-r8a774e1", 402 "renesas,rcar-gen3-gpio"; 403 reg = <0 0xe6054000 0 0x50>; 404 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 405 #gpio-cells = <2>; 406 gpio-controller; 407 gpio-ranges = <&pfc 0 128 18>; 408 #interrupt-cells = <2>; 409 interrupt-controller; 410 clocks = <&cpg CPG_MOD 908>; 411 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 412 resets = <&cpg 908>; 413 }; 414 415 gpio5: gpio@e6055000 { 416 compatible = "renesas,gpio-r8a774e1", 417 "renesas,rcar-gen3-gpio"; 418 reg = <0 0xe6055000 0 0x50>; 419 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 420 #gpio-cells = <2>; 421 gpio-controller; 422 gpio-ranges = <&pfc 0 160 26>; 423 #interrupt-cells = <2>; 424 interrupt-controller; 425 clocks = <&cpg CPG_MOD 907>; 426 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 427 resets = <&cpg 907>; 428 }; 429 430 gpio6: gpio@e6055400 { 431 compatible = "renesas,gpio-r8a774e1", 432 "renesas,rcar-gen3-gpio"; 433 reg = <0 0xe6055400 0 0x50>; 434 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 435 #gpio-cells = <2>; 436 gpio-controller; 437 gpio-ranges = <&pfc 0 192 32>; 438 #interrupt-cells = <2>; 439 interrupt-controller; 440 clocks = <&cpg CPG_MOD 906>; 441 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 442 resets = <&cpg 906>; 443 }; 444 445 gpio7: gpio@e6055800 { 446 compatible = "renesas,gpio-r8a774e1", 447 "renesas,rcar-gen3-gpio"; 448 reg = <0 0xe6055800 0 0x50>; 449 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 450 #gpio-cells = <2>; 451 gpio-controller; 452 gpio-ranges = <&pfc 0 224 4>; 453 #interrupt-cells = <2>; 454 interrupt-controller; 455 clocks = <&cpg CPG_MOD 905>; 456 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 457 resets = <&cpg 905>; 458 }; 459 460 pfc: pin-controller@e6060000 { 461 compatible = "renesas,pfc-r8a774e1"; 462 reg = <0 0xe6060000 0 0x50c>; 463 }; 464 465 cmt0: timer@e60f0000 { 466 compatible = "renesas,r8a774e1-cmt0", 467 "renesas,rcar-gen3-cmt0"; 468 reg = <0 0xe60f0000 0 0x1004>; 469 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&cpg CPG_MOD 303>; 472 clock-names = "fck"; 473 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 474 resets = <&cpg 303>; 475 status = "disabled"; 476 }; 477 478 cmt1: timer@e6130000 { 479 compatible = "renesas,r8a774e1-cmt1", 480 "renesas,rcar-gen3-cmt1"; 481 reg = <0 0xe6130000 0 0x1004>; 482 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&cpg CPG_MOD 302>; 491 clock-names = "fck"; 492 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 493 resets = <&cpg 302>; 494 status = "disabled"; 495 }; 496 497 cmt2: timer@e6140000 { 498 compatible = "renesas,r8a774e1-cmt1", 499 "renesas,rcar-gen3-cmt1"; 500 reg = <0 0xe6140000 0 0x1004>; 501 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&cpg CPG_MOD 301>; 510 clock-names = "fck"; 511 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 512 resets = <&cpg 301>; 513 status = "disabled"; 514 }; 515 516 cmt3: timer@e6148000 { 517 compatible = "renesas,r8a774e1-cmt1", 518 "renesas,rcar-gen3-cmt1"; 519 reg = <0 0xe6148000 0 0x1004>; 520 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&cpg CPG_MOD 300>; 529 clock-names = "fck"; 530 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 531 resets = <&cpg 300>; 532 status = "disabled"; 533 }; 534 535 cpg: clock-controller@e6150000 { 536 compatible = "renesas,r8a774e1-cpg-mssr"; 537 reg = <0 0xe6150000 0 0x1000>; 538 clocks = <&extal_clk>, <&extalr_clk>; 539 clock-names = "extal", "extalr"; 540 #clock-cells = <2>; 541 #power-domain-cells = <0>; 542 #reset-cells = <1>; 543 }; 544 545 rst: reset-controller@e6160000 { 546 compatible = "renesas,r8a774e1-rst"; 547 reg = <0 0xe6160000 0 0x0200>; 548 }; 549 550 sysc: system-controller@e6180000 { 551 compatible = "renesas,r8a774e1-sysc"; 552 reg = <0 0xe6180000 0 0x0400>; 553 #power-domain-cells = <1>; 554 }; 555 556 tsc: thermal@e6198000 { 557 compatible = "renesas,r8a774e1-thermal"; 558 reg = <0 0xe6198000 0 0x100>, 559 <0 0xe61a0000 0 0x100>, 560 <0 0xe61a8000 0 0x100>; 561 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&cpg CPG_MOD 522>; 565 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 566 resets = <&cpg 522>; 567 #thermal-sensor-cells = <1>; 568 }; 569 570 intc_ex: interrupt-controller@e61c0000 { 571 compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; 572 #interrupt-cells = <2>; 573 interrupt-controller; 574 reg = <0 0xe61c0000 0 0x200>; 575 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&cpg CPG_MOD 407>; 582 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 583 resets = <&cpg 407>; 584 }; 585 586 tmu0: timer@e61e0000 { 587 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 588 reg = <0 0xe61e0000 0 0x30>; 589 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&cpg CPG_MOD 125>; 593 clock-names = "fck"; 594 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 595 resets = <&cpg 125>; 596 status = "disabled"; 597 }; 598 599 tmu1: timer@e6fc0000 { 600 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 601 reg = <0 0xe6fc0000 0 0x30>; 602 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&cpg CPG_MOD 124>; 606 clock-names = "fck"; 607 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 608 resets = <&cpg 124>; 609 status = "disabled"; 610 }; 611 612 tmu2: timer@e6fd0000 { 613 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 614 reg = <0 0xe6fd0000 0 0x30>; 615 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&cpg CPG_MOD 123>; 619 clock-names = "fck"; 620 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 621 resets = <&cpg 123>; 622 status = "disabled"; 623 }; 624 625 tmu3: timer@e6fe0000 { 626 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 627 reg = <0 0xe6fe0000 0 0x30>; 628 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&cpg CPG_MOD 122>; 632 clock-names = "fck"; 633 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 634 resets = <&cpg 122>; 635 status = "disabled"; 636 }; 637 638 tmu4: timer@ffc00000 { 639 compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; 640 reg = <0 0xffc00000 0 0x30>; 641 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&cpg CPG_MOD 121>; 645 clock-names = "fck"; 646 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 647 resets = <&cpg 121>; 648 status = "disabled"; 649 }; 650 651 i2c0: i2c@e6500000 { 652 #address-cells = <1>; 653 #size-cells = <0>; 654 compatible = "renesas,i2c-r8a774e1", 655 "renesas,rcar-gen3-i2c"; 656 reg = <0 0xe6500000 0 0x40>; 657 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&cpg CPG_MOD 931>; 659 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 660 resets = <&cpg 931>; 661 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 662 <&dmac2 0x91>, <&dmac2 0x90>; 663 dma-names = "tx", "rx", "tx", "rx"; 664 i2c-scl-internal-delay-ns = <110>; 665 status = "disabled"; 666 }; 667 668 i2c1: i2c@e6508000 { 669 #address-cells = <1>; 670 #size-cells = <0>; 671 compatible = "renesas,i2c-r8a774e1", 672 "renesas,rcar-gen3-i2c"; 673 reg = <0 0xe6508000 0 0x40>; 674 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&cpg CPG_MOD 930>; 676 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 677 resets = <&cpg 930>; 678 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 679 <&dmac2 0x93>, <&dmac2 0x92>; 680 dma-names = "tx", "rx", "tx", "rx"; 681 i2c-scl-internal-delay-ns = <6>; 682 status = "disabled"; 683 }; 684 685 i2c2: i2c@e6510000 { 686 #address-cells = <1>; 687 #size-cells = <0>; 688 compatible = "renesas,i2c-r8a774e1", 689 "renesas,rcar-gen3-i2c"; 690 reg = <0 0xe6510000 0 0x40>; 691 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&cpg CPG_MOD 929>; 693 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 694 resets = <&cpg 929>; 695 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 696 <&dmac2 0x95>, <&dmac2 0x94>; 697 dma-names = "tx", "rx", "tx", "rx"; 698 i2c-scl-internal-delay-ns = <6>; 699 status = "disabled"; 700 }; 701 702 i2c3: i2c@e66d0000 { 703 #address-cells = <1>; 704 #size-cells = <0>; 705 compatible = "renesas,i2c-r8a774e1", 706 "renesas,rcar-gen3-i2c"; 707 reg = <0 0xe66d0000 0 0x40>; 708 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&cpg CPG_MOD 928>; 710 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 711 resets = <&cpg 928>; 712 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 713 dma-names = "tx", "rx"; 714 i2c-scl-internal-delay-ns = <110>; 715 status = "disabled"; 716 }; 717 718 i2c4: i2c@e66d8000 { 719 #address-cells = <1>; 720 #size-cells = <0>; 721 compatible = "renesas,i2c-r8a774e1", 722 "renesas,rcar-gen3-i2c"; 723 reg = <0 0xe66d8000 0 0x40>; 724 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&cpg CPG_MOD 927>; 726 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 727 resets = <&cpg 927>; 728 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 729 dma-names = "tx", "rx"; 730 i2c-scl-internal-delay-ns = <110>; 731 status = "disabled"; 732 }; 733 734 i2c5: i2c@e66e0000 { 735 #address-cells = <1>; 736 #size-cells = <0>; 737 compatible = "renesas,i2c-r8a774e1", 738 "renesas,rcar-gen3-i2c"; 739 reg = <0 0xe66e0000 0 0x40>; 740 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&cpg CPG_MOD 919>; 742 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 743 resets = <&cpg 919>; 744 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 745 dma-names = "tx", "rx"; 746 i2c-scl-internal-delay-ns = <110>; 747 status = "disabled"; 748 }; 749 750 i2c6: i2c@e66e8000 { 751 #address-cells = <1>; 752 #size-cells = <0>; 753 compatible = "renesas,i2c-r8a774e1", 754 "renesas,rcar-gen3-i2c"; 755 reg = <0 0xe66e8000 0 0x40>; 756 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&cpg CPG_MOD 918>; 758 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 759 resets = <&cpg 918>; 760 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 761 dma-names = "tx", "rx"; 762 i2c-scl-internal-delay-ns = <6>; 763 status = "disabled"; 764 }; 765 766 i2c_dvfs: i2c@e60b0000 { 767 #address-cells = <1>; 768 #size-cells = <0>; 769 compatible = "renesas,iic-r8a774e1", 770 "renesas,rcar-gen3-iic", 771 "renesas,rmobile-iic"; 772 reg = <0 0xe60b0000 0 0x425>; 773 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 774 clocks = <&cpg CPG_MOD 926>; 775 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 776 resets = <&cpg 926>; 777 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 778 dma-names = "tx", "rx"; 779 status = "disabled"; 780 }; 781 782 hscif0: serial@e6540000 { 783 compatible = "renesas,hscif-r8a774e1", 784 "renesas,rcar-gen3-hscif", 785 "renesas,hscif"; 786 reg = <0 0xe6540000 0 0x60>; 787 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&cpg CPG_MOD 520>, 789 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 790 <&scif_clk>; 791 clock-names = "fck", "brg_int", "scif_clk"; 792 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 793 <&dmac2 0x31>, <&dmac2 0x30>; 794 dma-names = "tx", "rx", "tx", "rx"; 795 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 796 resets = <&cpg 520>; 797 status = "disabled"; 798 }; 799 800 hscif1: serial@e6550000 { 801 compatible = "renesas,hscif-r8a774e1", 802 "renesas,rcar-gen3-hscif", 803 "renesas,hscif"; 804 reg = <0 0xe6550000 0 0x60>; 805 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&cpg CPG_MOD 519>, 807 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 808 <&scif_clk>; 809 clock-names = "fck", "brg_int", "scif_clk"; 810 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 811 <&dmac2 0x33>, <&dmac2 0x32>; 812 dma-names = "tx", "rx", "tx", "rx"; 813 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 814 resets = <&cpg 519>; 815 status = "disabled"; 816 }; 817 818 hscif2: serial@e6560000 { 819 compatible = "renesas,hscif-r8a774e1", 820 "renesas,rcar-gen3-hscif", 821 "renesas,hscif"; 822 reg = <0 0xe6560000 0 0x60>; 823 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&cpg CPG_MOD 518>, 825 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 826 <&scif_clk>; 827 clock-names = "fck", "brg_int", "scif_clk"; 828 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 829 <&dmac2 0x35>, <&dmac2 0x34>; 830 dma-names = "tx", "rx", "tx", "rx"; 831 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 832 resets = <&cpg 518>; 833 status = "disabled"; 834 }; 835 836 hscif3: serial@e66a0000 { 837 compatible = "renesas,hscif-r8a774e1", 838 "renesas,rcar-gen3-hscif", 839 "renesas,hscif"; 840 reg = <0 0xe66a0000 0 0x60>; 841 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&cpg CPG_MOD 517>, 843 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 844 <&scif_clk>; 845 clock-names = "fck", "brg_int", "scif_clk"; 846 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 847 dma-names = "tx", "rx"; 848 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 849 resets = <&cpg 517>; 850 status = "disabled"; 851 }; 852 853 hscif4: serial@e66b0000 { 854 compatible = "renesas,hscif-r8a774e1", 855 "renesas,rcar-gen3-hscif", 856 "renesas,hscif"; 857 reg = <0 0xe66b0000 0 0x60>; 858 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&cpg CPG_MOD 516>, 860 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 861 <&scif_clk>; 862 clock-names = "fck", "brg_int", "scif_clk"; 863 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 864 dma-names = "tx", "rx"; 865 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 866 resets = <&cpg 516>; 867 status = "disabled"; 868 }; 869 870 hsusb: usb@e6590000 { 871 compatible = "renesas,usbhs-r8a774e1", 872 "renesas,rcar-gen3-usbhs"; 873 reg = <0 0xe6590000 0 0x200>; 874 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 876 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 877 <&usb_dmac1 0>, <&usb_dmac1 1>; 878 dma-names = "ch0", "ch1", "ch2", "ch3"; 879 renesas,buswait = <11>; 880 phys = <&usb2_phy0 3>; 881 phy-names = "usb"; 882 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 883 resets = <&cpg 704>, <&cpg 703>; 884 status = "disabled"; 885 }; 886 887 usb_dmac0: dma-controller@e65a0000 { 888 compatible = "renesas,r8a774e1-usb-dmac", 889 "renesas,usb-dmac"; 890 reg = <0 0xe65a0000 0 0x100>; 891 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 893 interrupt-names = "ch0", "ch1"; 894 clocks = <&cpg CPG_MOD 330>; 895 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 896 resets = <&cpg 330>; 897 #dma-cells = <1>; 898 dma-channels = <2>; 899 }; 900 901 usb_dmac1: dma-controller@e65b0000 { 902 compatible = "renesas,r8a774e1-usb-dmac", 903 "renesas,usb-dmac"; 904 reg = <0 0xe65b0000 0 0x100>; 905 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 907 interrupt-names = "ch0", "ch1"; 908 clocks = <&cpg CPG_MOD 331>; 909 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 910 resets = <&cpg 331>; 911 #dma-cells = <1>; 912 dma-channels = <2>; 913 }; 914 915 usb3_phy0: usb-phy@e65ee000 { 916 compatible = "renesas,r8a774e1-usb3-phy", 917 "renesas,rcar-gen3-usb3-phy"; 918 reg = <0 0xe65ee000 0 0x90>; 919 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 920 <&usb_extal_clk>; 921 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 922 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 923 resets = <&cpg 328>; 924 #phy-cells = <0>; 925 status = "disabled"; 926 }; 927 928 dmac0: dma-controller@e6700000 { 929 compatible = "renesas,dmac-r8a774e1", 930 "renesas,rcar-dmac"; 931 reg = <0 0xe6700000 0 0x10000>; 932 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 949 interrupt-names = "error", 950 "ch0", "ch1", "ch2", "ch3", 951 "ch4", "ch5", "ch6", "ch7", 952 "ch8", "ch9", "ch10", "ch11", 953 "ch12", "ch13", "ch14", "ch15"; 954 clocks = <&cpg CPG_MOD 219>; 955 clock-names = "fck"; 956 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 957 resets = <&cpg 219>; 958 #dma-cells = <1>; 959 dma-channels = <16>; 960 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 961 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 962 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 963 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 964 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 965 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 966 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 967 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 968 }; 969 970 dmac1: dma-controller@e7300000 { 971 compatible = "renesas,dmac-r8a774e1", 972 "renesas,rcar-dmac"; 973 reg = <0 0xe7300000 0 0x10000>; 974 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 991 interrupt-names = "error", 992 "ch0", "ch1", "ch2", "ch3", 993 "ch4", "ch5", "ch6", "ch7", 994 "ch8", "ch9", "ch10", "ch11", 995 "ch12", "ch13", "ch14", "ch15"; 996 clocks = <&cpg CPG_MOD 218>; 997 clock-names = "fck"; 998 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 999 resets = <&cpg 218>; 1000 #dma-cells = <1>; 1001 dma-channels = <16>; 1002 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 1003 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 1004 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 1005 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 1006 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 1007 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 1008 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 1009 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 1010 }; 1011 1012 dmac2: dma-controller@e7310000 { 1013 compatible = "renesas,dmac-r8a774e1", 1014 "renesas,rcar-dmac"; 1015 reg = <0 0xe7310000 0 0x10000>; 1016 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1033 interrupt-names = "error", 1034 "ch0", "ch1", "ch2", "ch3", 1035 "ch4", "ch5", "ch6", "ch7", 1036 "ch8", "ch9", "ch10", "ch11", 1037 "ch12", "ch13", "ch14", "ch15"; 1038 clocks = <&cpg CPG_MOD 217>; 1039 clock-names = "fck"; 1040 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1041 resets = <&cpg 217>; 1042 #dma-cells = <1>; 1043 dma-channels = <16>; 1044 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1045 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1046 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1047 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1048 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1049 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1050 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1051 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1052 }; 1053 1054 ipmmu_ds0: iommu@e6740000 { 1055 compatible = "renesas,ipmmu-r8a774e1"; 1056 reg = <0 0xe6740000 0 0x1000>; 1057 renesas,ipmmu-main = <&ipmmu_mm 0>; 1058 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1059 #iommu-cells = <1>; 1060 }; 1061 1062 ipmmu_ds1: iommu@e7740000 { 1063 compatible = "renesas,ipmmu-r8a774e1"; 1064 reg = <0 0xe7740000 0 0x1000>; 1065 renesas,ipmmu-main = <&ipmmu_mm 1>; 1066 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1067 #iommu-cells = <1>; 1068 }; 1069 1070 ipmmu_hc: iommu@e6570000 { 1071 compatible = "renesas,ipmmu-r8a774e1"; 1072 reg = <0 0xe6570000 0 0x1000>; 1073 renesas,ipmmu-main = <&ipmmu_mm 2>; 1074 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1075 #iommu-cells = <1>; 1076 }; 1077 1078 ipmmu_mm: iommu@e67b0000 { 1079 compatible = "renesas,ipmmu-r8a774e1"; 1080 reg = <0 0xe67b0000 0 0x1000>; 1081 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1083 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1084 #iommu-cells = <1>; 1085 }; 1086 1087 ipmmu_mp0: iommu@ec670000 { 1088 compatible = "renesas,ipmmu-r8a774e1"; 1089 reg = <0 0xec670000 0 0x1000>; 1090 renesas,ipmmu-main = <&ipmmu_mm 4>; 1091 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1092 #iommu-cells = <1>; 1093 }; 1094 1095 ipmmu_pv0: iommu@fd800000 { 1096 compatible = "renesas,ipmmu-r8a774e1"; 1097 reg = <0 0xfd800000 0 0x1000>; 1098 renesas,ipmmu-main = <&ipmmu_mm 6>; 1099 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1100 #iommu-cells = <1>; 1101 }; 1102 1103 ipmmu_pv1: iommu@fd950000 { 1104 compatible = "renesas,ipmmu-r8a774e1"; 1105 reg = <0 0xfd950000 0 0x1000>; 1106 renesas,ipmmu-main = <&ipmmu_mm 7>; 1107 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1108 #iommu-cells = <1>; 1109 }; 1110 1111 ipmmu_pv2: iommu@fd960000 { 1112 compatible = "renesas,ipmmu-r8a774e1"; 1113 reg = <0 0xfd960000 0 0x1000>; 1114 renesas,ipmmu-main = <&ipmmu_mm 8>; 1115 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1116 #iommu-cells = <1>; 1117 }; 1118 1119 ipmmu_pv3: iommu@fd970000 { 1120 compatible = "renesas,ipmmu-r8a774e1"; 1121 reg = <0 0xfd970000 0 0x1000>; 1122 renesas,ipmmu-main = <&ipmmu_mm 9>; 1123 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1124 #iommu-cells = <1>; 1125 }; 1126 1127 ipmmu_vc0: iommu@fe6b0000 { 1128 compatible = "renesas,ipmmu-r8a774e1"; 1129 reg = <0 0xfe6b0000 0 0x1000>; 1130 renesas,ipmmu-main = <&ipmmu_mm 12>; 1131 power-domains = <&sysc R8A774E1_PD_A3VC>; 1132 #iommu-cells = <1>; 1133 }; 1134 1135 ipmmu_vc1: iommu@fe6f0000 { 1136 compatible = "renesas,ipmmu-r8a774e1"; 1137 reg = <0 0xfe6f0000 0 0x1000>; 1138 renesas,ipmmu-main = <&ipmmu_mm 13>; 1139 power-domains = <&sysc R8A774E1_PD_A3VC>; 1140 #iommu-cells = <1>; 1141 }; 1142 1143 ipmmu_vi0: iommu@febd0000 { 1144 compatible = "renesas,ipmmu-r8a774e1"; 1145 reg = <0 0xfebd0000 0 0x1000>; 1146 renesas,ipmmu-main = <&ipmmu_mm 14>; 1147 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1148 #iommu-cells = <1>; 1149 }; 1150 1151 ipmmu_vi1: iommu@febe0000 { 1152 compatible = "renesas,ipmmu-r8a774e1"; 1153 reg = <0 0xfebe0000 0 0x1000>; 1154 renesas,ipmmu-main = <&ipmmu_mm 15>; 1155 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1156 #iommu-cells = <1>; 1157 }; 1158 1159 ipmmu_vp0: iommu@fe990000 { 1160 compatible = "renesas,ipmmu-r8a774e1"; 1161 reg = <0 0xfe990000 0 0x1000>; 1162 renesas,ipmmu-main = <&ipmmu_mm 16>; 1163 power-domains = <&sysc R8A774E1_PD_A3VP>; 1164 #iommu-cells = <1>; 1165 }; 1166 1167 ipmmu_vp1: iommu@fe980000 { 1168 compatible = "renesas,ipmmu-r8a774e1"; 1169 reg = <0 0xfe980000 0 0x1000>; 1170 renesas,ipmmu-main = <&ipmmu_mm 17>; 1171 power-domains = <&sysc R8A774E1_PD_A3VP>; 1172 #iommu-cells = <1>; 1173 }; 1174 1175 avb: ethernet@e6800000 { 1176 compatible = "renesas,etheravb-r8a774e1", 1177 "renesas,etheravb-rcar-gen3"; 1178 reg = <0 0xe6800000 0 0x800>; 1179 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1204 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1205 "ch4", "ch5", "ch6", "ch7", 1206 "ch8", "ch9", "ch10", "ch11", 1207 "ch12", "ch13", "ch14", "ch15", 1208 "ch16", "ch17", "ch18", "ch19", 1209 "ch20", "ch21", "ch22", "ch23", 1210 "ch24"; 1211 clocks = <&cpg CPG_MOD 812>; 1212 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1213 resets = <&cpg 812>; 1214 phy-mode = "rgmii"; 1215 iommus = <&ipmmu_ds0 16>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 status = "disabled"; 1219 }; 1220 1221 can0: can@e6c30000 { 1222 compatible = "renesas,can-r8a774e1", 1223 "renesas,rcar-gen3-can"; 1224 reg = <0 0xe6c30000 0 0x1000>; 1225 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1226 clocks = <&cpg CPG_MOD 916>, 1227 <&cpg CPG_CORE R8A774E1_CLK_CANFD>, 1228 <&can_clk>; 1229 clock-names = "clkp1", "clkp2", "can_clk"; 1230 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; 1231 assigned-clock-rates = <40000000>; 1232 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1233 resets = <&cpg 916>; 1234 status = "disabled"; 1235 }; 1236 1237 can1: can@e6c38000 { 1238 compatible = "renesas,can-r8a774e1", 1239 "renesas,rcar-gen3-can"; 1240 reg = <0 0xe6c38000 0 0x1000>; 1241 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1242 clocks = <&cpg CPG_MOD 915>, 1243 <&cpg CPG_CORE R8A774E1_CLK_CANFD>, 1244 <&can_clk>; 1245 clock-names = "clkp1", "clkp2", "can_clk"; 1246 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; 1247 assigned-clock-rates = <40000000>; 1248 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1249 resets = <&cpg 915>; 1250 status = "disabled"; 1251 }; 1252 1253 canfd: can@e66c0000 { 1254 compatible = "renesas,r8a774e1-canfd", 1255 "renesas,rcar-gen3-canfd"; 1256 reg = <0 0xe66c0000 0 0x8000>; 1257 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1259 clocks = <&cpg CPG_MOD 914>, 1260 <&cpg CPG_CORE R8A774E1_CLK_CANFD>, 1261 <&can_clk>; 1262 clock-names = "fck", "canfd", "can_clk"; 1263 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; 1264 assigned-clock-rates = <40000000>; 1265 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1266 resets = <&cpg 914>; 1267 status = "disabled"; 1268 1269 channel0 { 1270 status = "disabled"; 1271 }; 1272 1273 channel1 { 1274 status = "disabled"; 1275 }; 1276 }; 1277 1278 pwm0: pwm@e6e30000 { 1279 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1280 reg = <0 0xe6e30000 0 0x8>; 1281 clocks = <&cpg CPG_MOD 523>; 1282 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1283 resets = <&cpg 523>; 1284 #pwm-cells = <2>; 1285 status = "disabled"; 1286 }; 1287 1288 pwm1: pwm@e6e31000 { 1289 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1290 reg = <0 0xe6e31000 0 0x8>; 1291 clocks = <&cpg CPG_MOD 523>; 1292 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1293 resets = <&cpg 523>; 1294 #pwm-cells = <2>; 1295 status = "disabled"; 1296 }; 1297 1298 pwm2: pwm@e6e32000 { 1299 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1300 reg = <0 0xe6e32000 0 0x8>; 1301 clocks = <&cpg CPG_MOD 523>; 1302 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1303 resets = <&cpg 523>; 1304 #pwm-cells = <2>; 1305 status = "disabled"; 1306 }; 1307 1308 pwm3: pwm@e6e33000 { 1309 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1310 reg = <0 0xe6e33000 0 0x8>; 1311 clocks = <&cpg CPG_MOD 523>; 1312 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1313 resets = <&cpg 523>; 1314 #pwm-cells = <2>; 1315 status = "disabled"; 1316 }; 1317 1318 pwm4: pwm@e6e34000 { 1319 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1320 reg = <0 0xe6e34000 0 0x8>; 1321 clocks = <&cpg CPG_MOD 523>; 1322 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1323 resets = <&cpg 523>; 1324 #pwm-cells = <2>; 1325 status = "disabled"; 1326 }; 1327 1328 pwm5: pwm@e6e35000 { 1329 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1330 reg = <0 0xe6e35000 0 0x8>; 1331 clocks = <&cpg CPG_MOD 523>; 1332 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1333 resets = <&cpg 523>; 1334 #pwm-cells = <2>; 1335 status = "disabled"; 1336 }; 1337 1338 pwm6: pwm@e6e36000 { 1339 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar"; 1340 reg = <0 0xe6e36000 0 0x8>; 1341 clocks = <&cpg CPG_MOD 523>; 1342 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1343 resets = <&cpg 523>; 1344 #pwm-cells = <2>; 1345 status = "disabled"; 1346 }; 1347 1348 scif0: serial@e6e60000 { 1349 compatible = "renesas,scif-r8a774e1", 1350 "renesas,rcar-gen3-scif", "renesas,scif"; 1351 reg = <0 0xe6e60000 0 0x40>; 1352 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1353 clocks = <&cpg CPG_MOD 207>, 1354 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1355 <&scif_clk>; 1356 clock-names = "fck", "brg_int", "scif_clk"; 1357 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1358 <&dmac2 0x51>, <&dmac2 0x50>; 1359 dma-names = "tx", "rx", "tx", "rx"; 1360 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1361 resets = <&cpg 207>; 1362 status = "disabled"; 1363 }; 1364 1365 scif1: serial@e6e68000 { 1366 compatible = "renesas,scif-r8a774e1", 1367 "renesas,rcar-gen3-scif", "renesas,scif"; 1368 reg = <0 0xe6e68000 0 0x40>; 1369 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1370 clocks = <&cpg CPG_MOD 206>, 1371 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1372 <&scif_clk>; 1373 clock-names = "fck", "brg_int", "scif_clk"; 1374 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1375 <&dmac2 0x53>, <&dmac2 0x52>; 1376 dma-names = "tx", "rx", "tx", "rx"; 1377 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1378 resets = <&cpg 206>; 1379 status = "disabled"; 1380 }; 1381 1382 scif2: serial@e6e88000 { 1383 compatible = "renesas,scif-r8a774e1", 1384 "renesas,rcar-gen3-scif", "renesas,scif"; 1385 reg = <0 0xe6e88000 0 0x40>; 1386 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1387 clocks = <&cpg CPG_MOD 310>, 1388 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1389 <&scif_clk>; 1390 clock-names = "fck", "brg_int", "scif_clk"; 1391 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1392 <&dmac2 0x13>, <&dmac2 0x12>; 1393 dma-names = "tx", "rx", "tx", "rx"; 1394 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1395 resets = <&cpg 310>; 1396 status = "disabled"; 1397 }; 1398 1399 scif3: serial@e6c50000 { 1400 compatible = "renesas,scif-r8a774e1", 1401 "renesas,rcar-gen3-scif", "renesas,scif"; 1402 reg = <0 0xe6c50000 0 0x40>; 1403 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1404 clocks = <&cpg CPG_MOD 204>, 1405 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1406 <&scif_clk>; 1407 clock-names = "fck", "brg_int", "scif_clk"; 1408 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1409 dma-names = "tx", "rx"; 1410 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1411 resets = <&cpg 204>; 1412 status = "disabled"; 1413 }; 1414 1415 scif4: serial@e6c40000 { 1416 compatible = "renesas,scif-r8a774e1", 1417 "renesas,rcar-gen3-scif", "renesas,scif"; 1418 reg = <0 0xe6c40000 0 0x40>; 1419 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1420 clocks = <&cpg CPG_MOD 203>, 1421 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1422 <&scif_clk>; 1423 clock-names = "fck", "brg_int", "scif_clk"; 1424 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1425 dma-names = "tx", "rx"; 1426 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1427 resets = <&cpg 203>; 1428 status = "disabled"; 1429 }; 1430 1431 scif5: serial@e6f30000 { 1432 compatible = "renesas,scif-r8a774e1", 1433 "renesas,rcar-gen3-scif", "renesas,scif"; 1434 reg = <0 0xe6f30000 0 0x40>; 1435 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1436 clocks = <&cpg CPG_MOD 202>, 1437 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 1438 <&scif_clk>; 1439 clock-names = "fck", "brg_int", "scif_clk"; 1440 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1441 <&dmac2 0x5b>, <&dmac2 0x5a>; 1442 dma-names = "tx", "rx", "tx", "rx"; 1443 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1444 resets = <&cpg 202>; 1445 status = "disabled"; 1446 }; 1447 1448 msiof0: spi@e6e90000 { 1449 compatible = "renesas,msiof-r8a774e1", 1450 "renesas,rcar-gen3-msiof"; 1451 reg = <0 0xe6e90000 0 0x0064>; 1452 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1453 clocks = <&cpg CPG_MOD 211>; 1454 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1455 <&dmac2 0x41>, <&dmac2 0x40>; 1456 dma-names = "tx", "rx", "tx", "rx"; 1457 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1458 resets = <&cpg 211>; 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 status = "disabled"; 1462 }; 1463 1464 msiof1: spi@e6ea0000 { 1465 compatible = "renesas,msiof-r8a774e1", 1466 "renesas,rcar-gen3-msiof"; 1467 reg = <0 0xe6ea0000 0 0x0064>; 1468 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1469 clocks = <&cpg CPG_MOD 210>; 1470 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1471 <&dmac2 0x43>, <&dmac2 0x42>; 1472 dma-names = "tx", "rx", "tx", "rx"; 1473 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1474 resets = <&cpg 210>; 1475 #address-cells = <1>; 1476 #size-cells = <0>; 1477 status = "disabled"; 1478 }; 1479 1480 msiof2: spi@e6c00000 { 1481 compatible = "renesas,msiof-r8a774e1", 1482 "renesas,rcar-gen3-msiof"; 1483 reg = <0 0xe6c00000 0 0x0064>; 1484 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1485 clocks = <&cpg CPG_MOD 209>; 1486 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1487 dma-names = "tx", "rx"; 1488 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1489 resets = <&cpg 209>; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 status = "disabled"; 1493 }; 1494 1495 msiof3: spi@e6c10000 { 1496 compatible = "renesas,msiof-r8a774e1", 1497 "renesas,rcar-gen3-msiof"; 1498 reg = <0 0xe6c10000 0 0x0064>; 1499 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1500 clocks = <&cpg CPG_MOD 208>; 1501 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1502 dma-names = "tx", "rx"; 1503 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1504 resets = <&cpg 208>; 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 status = "disabled"; 1508 }; 1509 1510 vin0: video@e6ef0000 { 1511 compatible = "renesas,vin-r8a774e1"; 1512 reg = <0 0xe6ef0000 0 0x1000>; 1513 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1514 clocks = <&cpg CPG_MOD 811>; 1515 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1516 resets = <&cpg 811>; 1517 renesas,id = <0>; 1518 status = "disabled"; 1519 1520 ports { 1521 #address-cells = <1>; 1522 #size-cells = <0>; 1523 1524 port@1 { 1525 #address-cells = <1>; 1526 #size-cells = <0>; 1527 1528 reg = <1>; 1529 1530 vin0csi20: endpoint@0 { 1531 reg = <0>; 1532 remote-endpoint = <&csi20vin0>; 1533 }; 1534 vin0csi40: endpoint@2 { 1535 reg = <2>; 1536 remote-endpoint = <&csi40vin0>; 1537 }; 1538 }; 1539 }; 1540 }; 1541 1542 vin1: video@e6ef1000 { 1543 compatible = "renesas,vin-r8a774e1"; 1544 reg = <0 0xe6ef1000 0 0x1000>; 1545 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1546 clocks = <&cpg CPG_MOD 810>; 1547 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1548 resets = <&cpg 810>; 1549 renesas,id = <1>; 1550 status = "disabled"; 1551 1552 ports { 1553 #address-cells = <1>; 1554 #size-cells = <0>; 1555 1556 port@1 { 1557 #address-cells = <1>; 1558 #size-cells = <0>; 1559 1560 reg = <1>; 1561 1562 vin1csi20: endpoint@0 { 1563 reg = <0>; 1564 remote-endpoint = <&csi20vin1>; 1565 }; 1566 vin1csi40: endpoint@2 { 1567 reg = <2>; 1568 remote-endpoint = <&csi40vin1>; 1569 }; 1570 }; 1571 }; 1572 }; 1573 1574 vin2: video@e6ef2000 { 1575 compatible = "renesas,vin-r8a774e1"; 1576 reg = <0 0xe6ef2000 0 0x1000>; 1577 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1578 clocks = <&cpg CPG_MOD 809>; 1579 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1580 resets = <&cpg 809>; 1581 renesas,id = <2>; 1582 status = "disabled"; 1583 1584 ports { 1585 #address-cells = <1>; 1586 #size-cells = <0>; 1587 1588 port@1 { 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 1592 reg = <1>; 1593 1594 vin2csi20: endpoint@0 { 1595 reg = <0>; 1596 remote-endpoint = <&csi20vin2>; 1597 }; 1598 vin2csi40: endpoint@2 { 1599 reg = <2>; 1600 remote-endpoint = <&csi40vin2>; 1601 }; 1602 }; 1603 }; 1604 }; 1605 1606 vin3: video@e6ef3000 { 1607 compatible = "renesas,vin-r8a774e1"; 1608 reg = <0 0xe6ef3000 0 0x1000>; 1609 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1610 clocks = <&cpg CPG_MOD 808>; 1611 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1612 resets = <&cpg 808>; 1613 renesas,id = <3>; 1614 status = "disabled"; 1615 1616 ports { 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 1620 port@1 { 1621 #address-cells = <1>; 1622 #size-cells = <0>; 1623 1624 reg = <1>; 1625 1626 vin3csi20: endpoint@0 { 1627 reg = <0>; 1628 remote-endpoint = <&csi20vin3>; 1629 }; 1630 vin3csi40: endpoint@2 { 1631 reg = <2>; 1632 remote-endpoint = <&csi40vin3>; 1633 }; 1634 }; 1635 }; 1636 }; 1637 1638 vin4: video@e6ef4000 { 1639 compatible = "renesas,vin-r8a774e1"; 1640 reg = <0 0xe6ef4000 0 0x1000>; 1641 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1642 clocks = <&cpg CPG_MOD 807>; 1643 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1644 resets = <&cpg 807>; 1645 renesas,id = <4>; 1646 status = "disabled"; 1647 1648 ports { 1649 #address-cells = <1>; 1650 #size-cells = <0>; 1651 1652 port@1 { 1653 #address-cells = <1>; 1654 #size-cells = <0>; 1655 1656 reg = <1>; 1657 1658 vin4csi20: endpoint@0 { 1659 reg = <0>; 1660 remote-endpoint = <&csi20vin4>; 1661 }; 1662 }; 1663 }; 1664 }; 1665 1666 vin5: video@e6ef5000 { 1667 compatible = "renesas,vin-r8a774e1"; 1668 reg = <0 0xe6ef5000 0 0x1000>; 1669 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1670 clocks = <&cpg CPG_MOD 806>; 1671 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1672 resets = <&cpg 806>; 1673 renesas,id = <5>; 1674 status = "disabled"; 1675 1676 ports { 1677 #address-cells = <1>; 1678 #size-cells = <0>; 1679 1680 port@1 { 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 1684 reg = <1>; 1685 1686 vin5csi20: endpoint@0 { 1687 reg = <0>; 1688 remote-endpoint = <&csi20vin5>; 1689 }; 1690 }; 1691 }; 1692 }; 1693 1694 vin6: video@e6ef6000 { 1695 compatible = "renesas,vin-r8a774e1"; 1696 reg = <0 0xe6ef6000 0 0x1000>; 1697 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1698 clocks = <&cpg CPG_MOD 805>; 1699 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1700 resets = <&cpg 805>; 1701 renesas,id = <6>; 1702 status = "disabled"; 1703 1704 ports { 1705 #address-cells = <1>; 1706 #size-cells = <0>; 1707 1708 port@1 { 1709 #address-cells = <1>; 1710 #size-cells = <0>; 1711 1712 reg = <1>; 1713 1714 vin6csi20: endpoint@0 { 1715 reg = <0>; 1716 remote-endpoint = <&csi20vin6>; 1717 }; 1718 }; 1719 }; 1720 }; 1721 1722 vin7: video@e6ef7000 { 1723 compatible = "renesas,vin-r8a774e1"; 1724 reg = <0 0xe6ef7000 0 0x1000>; 1725 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1726 clocks = <&cpg CPG_MOD 804>; 1727 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1728 resets = <&cpg 804>; 1729 renesas,id = <7>; 1730 status = "disabled"; 1731 1732 ports { 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 1736 port@1 { 1737 #address-cells = <1>; 1738 #size-cells = <0>; 1739 1740 reg = <1>; 1741 1742 vin7csi20: endpoint@0 { 1743 reg = <0>; 1744 remote-endpoint = <&csi20vin7>; 1745 }; 1746 }; 1747 }; 1748 }; 1749 1750 rcar_sound: sound@ec500000 { 1751 /* 1752 * #sound-dai-cells is required 1753 * 1754 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1755 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1756 */ 1757 /* 1758 * #clock-cells is required for audio_clkout0/1/2/3 1759 * 1760 * clkout : #clock-cells = <0>; <&rcar_sound>; 1761 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1762 */ 1763 compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3"; 1764 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1765 <0 0xec5a0000 0 0x100>, /* ADG */ 1766 <0 0xec540000 0 0x1000>, /* SSIU */ 1767 <0 0xec541000 0 0x280>, /* SSI */ 1768 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1769 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1770 1771 clocks = <&cpg CPG_MOD 1005>, 1772 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1773 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1774 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1775 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1776 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1777 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1778 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1779 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1780 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1781 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1782 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1783 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1784 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1785 <&audio_clk_a>, <&audio_clk_b>, 1786 <&audio_clk_c>, 1787 <&cpg CPG_CORE R8A774E1_CLK_S0D4>; 1788 clock-names = "ssi-all", 1789 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1790 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1791 "ssi.1", "ssi.0", 1792 "src.9", "src.8", "src.7", "src.6", 1793 "src.5", "src.4", "src.3", "src.2", 1794 "src.1", "src.0", 1795 "mix.1", "mix.0", 1796 "ctu.1", "ctu.0", 1797 "dvc.0", "dvc.1", 1798 "clk_a", "clk_b", "clk_c", "clk_i"; 1799 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 1800 resets = <&cpg 1005>, 1801 <&cpg 1006>, <&cpg 1007>, 1802 <&cpg 1008>, <&cpg 1009>, 1803 <&cpg 1010>, <&cpg 1011>, 1804 <&cpg 1012>, <&cpg 1013>, 1805 <&cpg 1014>, <&cpg 1015>; 1806 reset-names = "ssi-all", 1807 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1808 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1809 "ssi.1", "ssi.0"; 1810 status = "disabled"; 1811 1812 rcar_sound,dvc { 1813 dvc0: dvc-0 { 1814 dmas = <&audma1 0xbc>; 1815 dma-names = "tx"; 1816 }; 1817 dvc1: dvc-1 { 1818 dmas = <&audma1 0xbe>; 1819 dma-names = "tx"; 1820 }; 1821 }; 1822 1823 rcar_sound,mix { 1824 mix0: mix-0 { }; 1825 mix1: mix-1 { }; 1826 }; 1827 1828 rcar_sound,ctu { 1829 ctu00: ctu-0 { }; 1830 ctu01: ctu-1 { }; 1831 ctu02: ctu-2 { }; 1832 ctu03: ctu-3 { }; 1833 ctu10: ctu-4 { }; 1834 ctu11: ctu-5 { }; 1835 ctu12: ctu-6 { }; 1836 ctu13: ctu-7 { }; 1837 }; 1838 1839 rcar_sound,src { 1840 src0: src-0 { 1841 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1842 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1843 dma-names = "rx", "tx"; 1844 }; 1845 src1: src-1 { 1846 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1847 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1848 dma-names = "rx", "tx"; 1849 }; 1850 src2: src-2 { 1851 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1852 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1853 dma-names = "rx", "tx"; 1854 }; 1855 src3: src-3 { 1856 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1857 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1858 dma-names = "rx", "tx"; 1859 }; 1860 src4: src-4 { 1861 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1862 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1863 dma-names = "rx", "tx"; 1864 }; 1865 src5: src-5 { 1866 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1867 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1868 dma-names = "rx", "tx"; 1869 }; 1870 src6: src-6 { 1871 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1872 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1873 dma-names = "rx", "tx"; 1874 }; 1875 src7: src-7 { 1876 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1877 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1878 dma-names = "rx", "tx"; 1879 }; 1880 src8: src-8 { 1881 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1882 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1883 dma-names = "rx", "tx"; 1884 }; 1885 src9: src-9 { 1886 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1887 dmas = <&audma0 0x97>, <&audma1 0xba>; 1888 dma-names = "rx", "tx"; 1889 }; 1890 }; 1891 1892 rcar_sound,ssiu { 1893 ssiu00: ssiu-0 { 1894 dmas = <&audma0 0x15>, <&audma1 0x16>; 1895 dma-names = "rx", "tx"; 1896 }; 1897 ssiu01: ssiu-1 { 1898 dmas = <&audma0 0x35>, <&audma1 0x36>; 1899 dma-names = "rx", "tx"; 1900 }; 1901 ssiu02: ssiu-2 { 1902 dmas = <&audma0 0x37>, <&audma1 0x38>; 1903 dma-names = "rx", "tx"; 1904 }; 1905 ssiu03: ssiu-3 { 1906 dmas = <&audma0 0x47>, <&audma1 0x48>; 1907 dma-names = "rx", "tx"; 1908 }; 1909 ssiu04: ssiu-4 { 1910 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1911 dma-names = "rx", "tx"; 1912 }; 1913 ssiu05: ssiu-5 { 1914 dmas = <&audma0 0x43>, <&audma1 0x44>; 1915 dma-names = "rx", "tx"; 1916 }; 1917 ssiu06: ssiu-6 { 1918 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1919 dma-names = "rx", "tx"; 1920 }; 1921 ssiu07: ssiu-7 { 1922 dmas = <&audma0 0x53>, <&audma1 0x54>; 1923 dma-names = "rx", "tx"; 1924 }; 1925 ssiu10: ssiu-8 { 1926 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1927 dma-names = "rx", "tx"; 1928 }; 1929 ssiu11: ssiu-9 { 1930 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1931 dma-names = "rx", "tx"; 1932 }; 1933 ssiu12: ssiu-10 { 1934 dmas = <&audma0 0x57>, <&audma1 0x58>; 1935 dma-names = "rx", "tx"; 1936 }; 1937 ssiu13: ssiu-11 { 1938 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1939 dma-names = "rx", "tx"; 1940 }; 1941 ssiu14: ssiu-12 { 1942 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1943 dma-names = "rx", "tx"; 1944 }; 1945 ssiu15: ssiu-13 { 1946 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1947 dma-names = "rx", "tx"; 1948 }; 1949 ssiu16: ssiu-14 { 1950 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1951 dma-names = "rx", "tx"; 1952 }; 1953 ssiu17: ssiu-15 { 1954 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1955 dma-names = "rx", "tx"; 1956 }; 1957 ssiu20: ssiu-16 { 1958 dmas = <&audma0 0x63>, <&audma1 0x64>; 1959 dma-names = "rx", "tx"; 1960 }; 1961 ssiu21: ssiu-17 { 1962 dmas = <&audma0 0x67>, <&audma1 0x68>; 1963 dma-names = "rx", "tx"; 1964 }; 1965 ssiu22: ssiu-18 { 1966 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1967 dma-names = "rx", "tx"; 1968 }; 1969 ssiu23: ssiu-19 { 1970 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1971 dma-names = "rx", "tx"; 1972 }; 1973 ssiu24: ssiu-20 { 1974 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1975 dma-names = "rx", "tx"; 1976 }; 1977 ssiu25: ssiu-21 { 1978 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1979 dma-names = "rx", "tx"; 1980 }; 1981 ssiu26: ssiu-22 { 1982 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1983 dma-names = "rx", "tx"; 1984 }; 1985 ssiu27: ssiu-23 { 1986 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1987 dma-names = "rx", "tx"; 1988 }; 1989 ssiu30: ssiu-24 { 1990 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1991 dma-names = "rx", "tx"; 1992 }; 1993 ssiu31: ssiu-25 { 1994 dmas = <&audma0 0x21>, <&audma1 0x22>; 1995 dma-names = "rx", "tx"; 1996 }; 1997 ssiu32: ssiu-26 { 1998 dmas = <&audma0 0x23>, <&audma1 0x24>; 1999 dma-names = "rx", "tx"; 2000 }; 2001 ssiu33: ssiu-27 { 2002 dmas = <&audma0 0x25>, <&audma1 0x26>; 2003 dma-names = "rx", "tx"; 2004 }; 2005 ssiu34: ssiu-28 { 2006 dmas = <&audma0 0x27>, <&audma1 0x28>; 2007 dma-names = "rx", "tx"; 2008 }; 2009 ssiu35: ssiu-29 { 2010 dmas = <&audma0 0x29>, <&audma1 0x2A>; 2011 dma-names = "rx", "tx"; 2012 }; 2013 ssiu36: ssiu-30 { 2014 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 2015 dma-names = "rx", "tx"; 2016 }; 2017 ssiu37: ssiu-31 { 2018 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 2019 dma-names = "rx", "tx"; 2020 }; 2021 ssiu40: ssiu-32 { 2022 dmas = <&audma0 0x71>, <&audma1 0x72>; 2023 dma-names = "rx", "tx"; 2024 }; 2025 ssiu41: ssiu-33 { 2026 dmas = <&audma0 0x17>, <&audma1 0x18>; 2027 dma-names = "rx", "tx"; 2028 }; 2029 ssiu42: ssiu-34 { 2030 dmas = <&audma0 0x19>, <&audma1 0x1A>; 2031 dma-names = "rx", "tx"; 2032 }; 2033 ssiu43: ssiu-35 { 2034 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 2035 dma-names = "rx", "tx"; 2036 }; 2037 ssiu44: ssiu-36 { 2038 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 2039 dma-names = "rx", "tx"; 2040 }; 2041 ssiu45: ssiu-37 { 2042 dmas = <&audma0 0x1F>, <&audma1 0x20>; 2043 dma-names = "rx", "tx"; 2044 }; 2045 ssiu46: ssiu-38 { 2046 dmas = <&audma0 0x31>, <&audma1 0x32>; 2047 dma-names = "rx", "tx"; 2048 }; 2049 ssiu47: ssiu-39 { 2050 dmas = <&audma0 0x33>, <&audma1 0x34>; 2051 dma-names = "rx", "tx"; 2052 }; 2053 ssiu50: ssiu-40 { 2054 dmas = <&audma0 0x73>, <&audma1 0x74>; 2055 dma-names = "rx", "tx"; 2056 }; 2057 ssiu60: ssiu-41 { 2058 dmas = <&audma0 0x75>, <&audma1 0x76>; 2059 dma-names = "rx", "tx"; 2060 }; 2061 ssiu70: ssiu-42 { 2062 dmas = <&audma0 0x79>, <&audma1 0x7a>; 2063 dma-names = "rx", "tx"; 2064 }; 2065 ssiu80: ssiu-43 { 2066 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 2067 dma-names = "rx", "tx"; 2068 }; 2069 ssiu90: ssiu-44 { 2070 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 2071 dma-names = "rx", "tx"; 2072 }; 2073 ssiu91: ssiu-45 { 2074 dmas = <&audma0 0x7F>, <&audma1 0x80>; 2075 dma-names = "rx", "tx"; 2076 }; 2077 ssiu92: ssiu-46 { 2078 dmas = <&audma0 0x81>, <&audma1 0x82>; 2079 dma-names = "rx", "tx"; 2080 }; 2081 ssiu93: ssiu-47 { 2082 dmas = <&audma0 0x83>, <&audma1 0x84>; 2083 dma-names = "rx", "tx"; 2084 }; 2085 ssiu94: ssiu-48 { 2086 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 2087 dma-names = "rx", "tx"; 2088 }; 2089 ssiu95: ssiu-49 { 2090 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 2091 dma-names = "rx", "tx"; 2092 }; 2093 ssiu96: ssiu-50 { 2094 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2095 dma-names = "rx", "tx"; 2096 }; 2097 ssiu97: ssiu-51 { 2098 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2099 dma-names = "rx", "tx"; 2100 }; 2101 }; 2102 2103 rcar_sound,ssi { 2104 ssi0: ssi-0 { 2105 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 2106 dmas = <&audma0 0x01>, <&audma1 0x02>; 2107 dma-names = "rx", "tx"; 2108 }; 2109 ssi1: ssi-1 { 2110 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 2111 dmas = <&audma0 0x03>, <&audma1 0x04>; 2112 dma-names = "rx", "tx"; 2113 }; 2114 ssi2: ssi-2 { 2115 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 2116 dmas = <&audma0 0x05>, <&audma1 0x06>; 2117 dma-names = "rx", "tx"; 2118 }; 2119 ssi3: ssi-3 { 2120 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2121 dmas = <&audma0 0x07>, <&audma1 0x08>; 2122 dma-names = "rx", "tx"; 2123 }; 2124 ssi4: ssi-4 { 2125 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 2126 dmas = <&audma0 0x09>, <&audma1 0x0a>; 2127 dma-names = "rx", "tx"; 2128 }; 2129 ssi5: ssi-5 { 2130 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2131 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 2132 dma-names = "rx", "tx"; 2133 }; 2134 ssi6: ssi-6 { 2135 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 2136 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 2137 dma-names = "rx", "tx"; 2138 }; 2139 ssi7: ssi-7 { 2140 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 2141 dmas = <&audma0 0x0f>, <&audma1 0x10>; 2142 dma-names = "rx", "tx"; 2143 }; 2144 ssi8: ssi-8 { 2145 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 2146 dmas = <&audma0 0x11>, <&audma1 0x12>; 2147 dma-names = "rx", "tx"; 2148 }; 2149 ssi9: ssi-9 { 2150 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 2151 dmas = <&audma0 0x13>, <&audma1 0x14>; 2152 dma-names = "rx", "tx"; 2153 }; 2154 }; 2155 }; 2156 2157 audma0: dma-controller@ec700000 { 2158 compatible = "renesas,dmac-r8a774e1", 2159 "renesas,rcar-dmac"; 2160 reg = <0 0xec700000 0 0x10000>; 2161 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2162 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2165 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2178 interrupt-names = "error", 2179 "ch0", "ch1", "ch2", "ch3", 2180 "ch4", "ch5", "ch6", "ch7", 2181 "ch8", "ch9", "ch10", "ch11", 2182 "ch12", "ch13", "ch14", "ch15"; 2183 clocks = <&cpg CPG_MOD 502>; 2184 clock-names = "fck"; 2185 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2186 resets = <&cpg 502>; 2187 #dma-cells = <1>; 2188 dma-channels = <16>; 2189 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, 2190 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, 2191 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, 2192 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, 2193 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, 2194 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, 2195 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, 2196 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; 2197 }; 2198 2199 audma1: dma-controller@ec720000 { 2200 compatible = "renesas,dmac-r8a774e1", 2201 "renesas,rcar-dmac"; 2202 reg = <0 0xec720000 0 0x10000>; 2203 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2205 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2206 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2207 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2208 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2209 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2210 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2211 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2212 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2214 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2215 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2219 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2220 interrupt-names = "error", 2221 "ch0", "ch1", "ch2", "ch3", 2222 "ch4", "ch5", "ch6", "ch7", 2223 "ch8", "ch9", "ch10", "ch11", 2224 "ch12", "ch13", "ch14", "ch15"; 2225 clocks = <&cpg CPG_MOD 501>; 2226 clock-names = "fck"; 2227 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2228 resets = <&cpg 501>; 2229 #dma-cells = <1>; 2230 dma-channels = <16>; 2231 iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, 2232 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, 2233 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, 2234 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, 2235 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, 2236 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, 2237 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, 2238 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; 2239 }; 2240 2241 xhci0: usb@ee000000 { 2242 compatible = "renesas,xhci-r8a774e1", 2243 "renesas,rcar-gen3-xhci"; 2244 reg = <0 0xee000000 0 0xc00>; 2245 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2246 clocks = <&cpg CPG_MOD 328>; 2247 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2248 resets = <&cpg 328>; 2249 status = "disabled"; 2250 }; 2251 2252 usb3_peri0: usb@ee020000 { 2253 compatible = "renesas,r8a774e1-usb3-peri", 2254 "renesas,rcar-gen3-usb3-peri"; 2255 reg = <0 0xee020000 0 0x400>; 2256 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2257 clocks = <&cpg CPG_MOD 328>; 2258 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2259 resets = <&cpg 328>; 2260 status = "disabled"; 2261 }; 2262 2263 ohci0: usb@ee080000 { 2264 compatible = "generic-ohci"; 2265 reg = <0 0xee080000 0 0x100>; 2266 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2267 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2268 phys = <&usb2_phy0 1>; 2269 phy-names = "usb"; 2270 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2271 resets = <&cpg 703>, <&cpg 704>; 2272 status = "disabled"; 2273 }; 2274 2275 ohci1: usb@ee0a0000 { 2276 compatible = "generic-ohci"; 2277 reg = <0 0xee0a0000 0 0x100>; 2278 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2279 clocks = <&cpg CPG_MOD 702>; 2280 phys = <&usb2_phy1 1>; 2281 phy-names = "usb"; 2282 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2283 resets = <&cpg 702>; 2284 status = "disabled"; 2285 }; 2286 2287 ehci0: usb@ee080100 { 2288 compatible = "generic-ehci"; 2289 reg = <0 0xee080100 0 0x100>; 2290 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2291 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2292 phys = <&usb2_phy0 2>; 2293 phy-names = "usb"; 2294 companion = <&ohci0>; 2295 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2296 resets = <&cpg 703>, <&cpg 704>; 2297 status = "disabled"; 2298 }; 2299 2300 ehci1: usb@ee0a0100 { 2301 compatible = "generic-ehci"; 2302 reg = <0 0xee0a0100 0 0x100>; 2303 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2304 clocks = <&cpg CPG_MOD 702>; 2305 phys = <&usb2_phy1 2>; 2306 phy-names = "usb"; 2307 companion = <&ohci1>; 2308 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2309 resets = <&cpg 702>; 2310 status = "disabled"; 2311 }; 2312 2313 usb2_phy0: usb-phy@ee080200 { 2314 compatible = "renesas,usb2-phy-r8a774e1", 2315 "renesas,rcar-gen3-usb2-phy"; 2316 reg = <0 0xee080200 0 0x700>; 2317 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2318 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2319 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2320 resets = <&cpg 703>, <&cpg 704>; 2321 #phy-cells = <1>; 2322 status = "disabled"; 2323 }; 2324 2325 usb2_phy1: usb-phy@ee0a0200 { 2326 compatible = "renesas,usb2-phy-r8a774e1", 2327 "renesas,rcar-gen3-usb2-phy"; 2328 reg = <0 0xee0a0200 0 0x700>; 2329 clocks = <&cpg CPG_MOD 702>; 2330 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2331 resets = <&cpg 702>; 2332 #phy-cells = <1>; 2333 status = "disabled"; 2334 }; 2335 2336 sdhi0: mmc@ee100000 { 2337 compatible = "renesas,sdhi-r8a774e1", 2338 "renesas,rcar-gen3-sdhi"; 2339 reg = <0 0xee100000 0 0x2000>; 2340 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2341 clocks = <&cpg CPG_MOD 314>; 2342 max-frequency = <200000000>; 2343 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2344 resets = <&cpg 314>; 2345 iommus = <&ipmmu_ds1 32>; 2346 status = "disabled"; 2347 }; 2348 2349 sdhi1: mmc@ee120000 { 2350 compatible = "renesas,sdhi-r8a774e1", 2351 "renesas,rcar-gen3-sdhi"; 2352 reg = <0 0xee120000 0 0x2000>; 2353 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2354 clocks = <&cpg CPG_MOD 313>; 2355 max-frequency = <200000000>; 2356 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2357 resets = <&cpg 313>; 2358 iommus = <&ipmmu_ds1 33>; 2359 status = "disabled"; 2360 }; 2361 2362 sdhi2: mmc@ee140000 { 2363 compatible = "renesas,sdhi-r8a774e1", 2364 "renesas,rcar-gen3-sdhi"; 2365 reg = <0 0xee140000 0 0x2000>; 2366 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2367 clocks = <&cpg CPG_MOD 312>; 2368 max-frequency = <200000000>; 2369 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2370 resets = <&cpg 312>; 2371 iommus = <&ipmmu_ds1 34>; 2372 status = "disabled"; 2373 }; 2374 2375 sdhi3: mmc@ee160000 { 2376 compatible = "renesas,sdhi-r8a774e1", 2377 "renesas,rcar-gen3-sdhi"; 2378 reg = <0 0xee160000 0 0x2000>; 2379 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2380 clocks = <&cpg CPG_MOD 311>; 2381 max-frequency = <200000000>; 2382 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2383 resets = <&cpg 311>; 2384 iommus = <&ipmmu_ds1 35>; 2385 status = "disabled"; 2386 }; 2387 2388 sata: sata@ee300000 { 2389 compatible = "renesas,sata-r8a774e1", 2390 "renesas,rcar-gen3-sata"; 2391 reg = <0 0xee300000 0 0x200000>; 2392 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2393 clocks = <&cpg CPG_MOD 815>; 2394 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2395 resets = <&cpg 815>; 2396 iommus = <&ipmmu_hc 2>; 2397 status = "disabled"; 2398 }; 2399 2400 gic: interrupt-controller@f1010000 { 2401 compatible = "arm,gic-400"; 2402 #interrupt-cells = <3>; 2403 #address-cells = <0>; 2404 interrupt-controller; 2405 reg = <0x0 0xf1010000 0 0x1000>, 2406 <0x0 0xf1020000 0 0x20000>, 2407 <0x0 0xf1040000 0 0x20000>, 2408 <0x0 0xf1060000 0 0x20000>; 2409 interrupts = <GIC_PPI 9 2410 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2411 clocks = <&cpg CPG_MOD 408>; 2412 clock-names = "clk"; 2413 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2414 resets = <&cpg 408>; 2415 }; 2416 2417 pciec0: pcie@fe000000 { 2418 compatible = "renesas,pcie-r8a774e1", 2419 "renesas,pcie-rcar-gen3"; 2420 reg = <0 0xfe000000 0 0x80000>; 2421 #address-cells = <3>; 2422 #size-cells = <2>; 2423 bus-range = <0x00 0xff>; 2424 device_type = "pci"; 2425 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2426 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2427 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2428 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2429 /* Map all possible DDR as inbound ranges */ 2430 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2431 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2434 #interrupt-cells = <1>; 2435 interrupt-map-mask = <0 0 0 0>; 2436 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2437 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2438 clock-names = "pcie", "pcie_bus"; 2439 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2440 resets = <&cpg 319>; 2441 status = "disabled"; 2442 }; 2443 2444 pciec1: pcie@ee800000 { 2445 compatible = "renesas,pcie-r8a774e1", 2446 "renesas,pcie-rcar-gen3"; 2447 reg = <0 0xee800000 0 0x80000>; 2448 #address-cells = <3>; 2449 #size-cells = <2>; 2450 bus-range = <0x00 0xff>; 2451 device_type = "pci"; 2452 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2453 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2454 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2455 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2456 /* Map all possible DDR as inbound ranges */ 2457 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2458 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2459 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2460 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2461 #interrupt-cells = <1>; 2462 interrupt-map-mask = <0 0 0 0>; 2463 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2464 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2465 clock-names = "pcie", "pcie_bus"; 2466 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2467 resets = <&cpg 318>; 2468 status = "disabled"; 2469 }; 2470 2471 vspbc: vsp@fe920000 { 2472 compatible = "renesas,vsp2"; 2473 reg = <0 0xfe920000 0 0x8000>; 2474 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 2475 clocks = <&cpg CPG_MOD 624>; 2476 power-domains = <&sysc R8A774E1_PD_A3VP>; 2477 resets = <&cpg 624>; 2478 2479 renesas,fcp = <&fcpvb1>; 2480 }; 2481 2482 vspbd: vsp@fe960000 { 2483 compatible = "renesas,vsp2"; 2484 reg = <0 0xfe960000 0 0x8000>; 2485 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2486 clocks = <&cpg CPG_MOD 626>; 2487 power-domains = <&sysc R8A774E1_PD_A3VP>; 2488 resets = <&cpg 626>; 2489 2490 renesas,fcp = <&fcpvb0>; 2491 }; 2492 2493 vspd0: vsp@fea20000 { 2494 compatible = "renesas,vsp2"; 2495 reg = <0 0xfea20000 0 0x5000>; 2496 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2497 clocks = <&cpg CPG_MOD 623>; 2498 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2499 resets = <&cpg 623>; 2500 2501 renesas,fcp = <&fcpvd0>; 2502 }; 2503 2504 vspd1: vsp@fea28000 { 2505 compatible = "renesas,vsp2"; 2506 reg = <0 0xfea28000 0 0x5000>; 2507 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2508 clocks = <&cpg CPG_MOD 622>; 2509 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2510 resets = <&cpg 622>; 2511 2512 renesas,fcp = <&fcpvd1>; 2513 }; 2514 2515 vspi0: vsp@fe9a0000 { 2516 compatible = "renesas,vsp2"; 2517 reg = <0 0xfe9a0000 0 0x8000>; 2518 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2519 clocks = <&cpg CPG_MOD 631>; 2520 power-domains = <&sysc R8A774E1_PD_A3VP>; 2521 resets = <&cpg 631>; 2522 2523 renesas,fcp = <&fcpvi0>; 2524 }; 2525 2526 vspi1: vsp@fe9b0000 { 2527 compatible = "renesas,vsp2"; 2528 reg = <0 0xfe9b0000 0 0x8000>; 2529 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 2530 clocks = <&cpg CPG_MOD 630>; 2531 power-domains = <&sysc R8A774E1_PD_A3VP>; 2532 resets = <&cpg 630>; 2533 2534 renesas,fcp = <&fcpvi1>; 2535 }; 2536 2537 fdp1@fe940000 { 2538 compatible = "renesas,fdp1"; 2539 reg = <0 0xfe940000 0 0x2400>; 2540 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2541 clocks = <&cpg CPG_MOD 119>; 2542 power-domains = <&sysc R8A774E1_PD_A3VP>; 2543 resets = <&cpg 119>; 2544 renesas,fcp = <&fcpf0>; 2545 }; 2546 2547 fdp1@fe944000 { 2548 compatible = "renesas,fdp1"; 2549 reg = <0 0xfe944000 0 0x2400>; 2550 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2551 clocks = <&cpg CPG_MOD 118>; 2552 power-domains = <&sysc R8A774E1_PD_A3VP>; 2553 resets = <&cpg 118>; 2554 renesas,fcp = <&fcpf1>; 2555 }; 2556 2557 fcpf0: fcp@fe950000 { 2558 compatible = "renesas,fcpf"; 2559 reg = <0 0xfe950000 0 0x200>; 2560 clocks = <&cpg CPG_MOD 615>; 2561 power-domains = <&sysc R8A774E1_PD_A3VP>; 2562 resets = <&cpg 615>; 2563 }; 2564 2565 fcpf1: fcp@fe951000 { 2566 compatible = "renesas,fcpf"; 2567 reg = <0 0xfe951000 0 0x200>; 2568 clocks = <&cpg CPG_MOD 614>; 2569 power-domains = <&sysc R8A774E1_PD_A3VP>; 2570 resets = <&cpg 614>; 2571 }; 2572 2573 fcpvb0: fcp@fe96f000 { 2574 compatible = "renesas,fcpv"; 2575 reg = <0 0xfe96f000 0 0x200>; 2576 clocks = <&cpg CPG_MOD 607>; 2577 power-domains = <&sysc R8A774E1_PD_A3VP>; 2578 resets = <&cpg 607>; 2579 }; 2580 2581 fcpvb1: fcp@fe92f000 { 2582 compatible = "renesas,fcpv"; 2583 reg = <0 0xfe92f000 0 0x200>; 2584 clocks = <&cpg CPG_MOD 606>; 2585 power-domains = <&sysc R8A774E1_PD_A3VP>; 2586 resets = <&cpg 606>; 2587 }; 2588 2589 fcpvi0: fcp@fe9af000 { 2590 compatible = "renesas,fcpv"; 2591 reg = <0 0xfe9af000 0 0x200>; 2592 clocks = <&cpg CPG_MOD 611>; 2593 power-domains = <&sysc R8A774E1_PD_A3VP>; 2594 resets = <&cpg 611>; 2595 }; 2596 2597 fcpvi1: fcp@fe9bf000 { 2598 compatible = "renesas,fcpv"; 2599 reg = <0 0xfe9bf000 0 0x200>; 2600 clocks = <&cpg CPG_MOD 610>; 2601 power-domains = <&sysc R8A774E1_PD_A3VP>; 2602 resets = <&cpg 610>; 2603 }; 2604 2605 fcpvd0: fcp@fea27000 { 2606 compatible = "renesas,fcpv"; 2607 reg = <0 0xfea27000 0 0x200>; 2608 clocks = <&cpg CPG_MOD 603>; 2609 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2610 resets = <&cpg 603>; 2611 }; 2612 2613 fcpvd1: fcp@fea2f000 { 2614 compatible = "renesas,fcpv"; 2615 reg = <0 0xfea2f000 0 0x200>; 2616 clocks = <&cpg CPG_MOD 602>; 2617 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2618 resets = <&cpg 602>; 2619 }; 2620 2621 csi20: csi2@fea80000 { 2622 compatible = "renesas,r8a774e1-csi2"; 2623 reg = <0 0xfea80000 0 0x10000>; 2624 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2625 clocks = <&cpg CPG_MOD 714>; 2626 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2627 resets = <&cpg 714>; 2628 status = "disabled"; 2629 2630 ports { 2631 #address-cells = <1>; 2632 #size-cells = <0>; 2633 2634 port@1 { 2635 #address-cells = <1>; 2636 #size-cells = <0>; 2637 2638 reg = <1>; 2639 2640 csi20vin0: endpoint@0 { 2641 reg = <0>; 2642 remote-endpoint = <&vin0csi20>; 2643 }; 2644 csi20vin1: endpoint@1 { 2645 reg = <1>; 2646 remote-endpoint = <&vin1csi20>; 2647 }; 2648 csi20vin2: endpoint@2 { 2649 reg = <2>; 2650 remote-endpoint = <&vin2csi20>; 2651 }; 2652 csi20vin3: endpoint@3 { 2653 reg = <3>; 2654 remote-endpoint = <&vin3csi20>; 2655 }; 2656 csi20vin4: endpoint@4 { 2657 reg = <4>; 2658 remote-endpoint = <&vin4csi20>; 2659 }; 2660 csi20vin5: endpoint@5 { 2661 reg = <5>; 2662 remote-endpoint = <&vin5csi20>; 2663 }; 2664 csi20vin6: endpoint@6 { 2665 reg = <6>; 2666 remote-endpoint = <&vin6csi20>; 2667 }; 2668 csi20vin7: endpoint@7 { 2669 reg = <7>; 2670 remote-endpoint = <&vin7csi20>; 2671 }; 2672 }; 2673 }; 2674 }; 2675 2676 csi40: csi2@feaa0000 { 2677 compatible = "renesas,r8a774e1-csi2"; 2678 reg = <0 0xfeaa0000 0 0x10000>; 2679 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2680 clocks = <&cpg CPG_MOD 716>; 2681 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2682 resets = <&cpg 716>; 2683 status = "disabled"; 2684 2685 ports { 2686 #address-cells = <1>; 2687 #size-cells = <0>; 2688 2689 port@1 { 2690 #address-cells = <1>; 2691 #size-cells = <0>; 2692 2693 reg = <1>; 2694 2695 csi40vin0: endpoint@0 { 2696 reg = <0>; 2697 remote-endpoint = <&vin0csi40>; 2698 }; 2699 csi40vin1: endpoint@1 { 2700 reg = <1>; 2701 remote-endpoint = <&vin1csi40>; 2702 }; 2703 csi40vin2: endpoint@2 { 2704 reg = <2>; 2705 remote-endpoint = <&vin2csi40>; 2706 }; 2707 csi40vin3: endpoint@3 { 2708 reg = <3>; 2709 remote-endpoint = <&vin3csi40>; 2710 }; 2711 }; 2712 }; 2713 }; 2714 2715 hdmi0: hdmi@fead0000 { 2716 compatible = "renesas,r8a774e1-hdmi", 2717 "renesas,rcar-gen3-hdmi"; 2718 reg = <0 0xfead0000 0 0x10000>; 2719 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2720 clocks = <&cpg CPG_MOD 729>, 2721 <&cpg CPG_CORE R8A774E1_CLK_HDMI>; 2722 clock-names = "iahb", "isfr"; 2723 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2724 resets = <&cpg 729>; 2725 status = "disabled"; 2726 2727 ports { 2728 #address-cells = <1>; 2729 #size-cells = <0>; 2730 2731 port@0 { 2732 reg = <0>; 2733 dw_hdmi0_in: endpoint { 2734 remote-endpoint = <&du_out_hdmi0>; 2735 }; 2736 }; 2737 port@1 { 2738 reg = <1>; 2739 }; 2740 port@2 { 2741 /* HDMI sound */ 2742 reg = <2>; 2743 }; 2744 }; 2745 }; 2746 2747 du: display@feb00000 { 2748 compatible = "renesas,du-r8a774e1"; 2749 reg = <0 0xfeb00000 0 0x80000>; 2750 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2751 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2752 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 2753 clocks = <&cpg CPG_MOD 724>, 2754 <&cpg CPG_MOD 723>, 2755 <&cpg CPG_MOD 721>; 2756 clock-names = "du.0", "du.1", "du.3"; 2757 resets = <&cpg 724>, <&cpg 722>; 2758 reset-names = "du.0", "du.3"; 2759 status = "disabled"; 2760 2761 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; 2762 2763 ports { 2764 #address-cells = <1>; 2765 #size-cells = <0>; 2766 2767 port@0 { 2768 reg = <0>; 2769 du_out_rgb: endpoint { 2770 }; 2771 }; 2772 port@1 { 2773 reg = <1>; 2774 du_out_hdmi0: endpoint { 2775 remote-endpoint = <&dw_hdmi0_in>; 2776 }; 2777 }; 2778 port@2 { 2779 reg = <2>; 2780 du_out_lvds0: endpoint { 2781 remote-endpoint = <&lvds0_in>; 2782 }; 2783 }; 2784 }; 2785 }; 2786 2787 lvds0: lvds@feb90000 { 2788 compatible = "renesas,r8a774e1-lvds"; 2789 reg = <0 0xfeb90000 0 0x14>; 2790 clocks = <&cpg CPG_MOD 727>; 2791 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 2792 resets = <&cpg 727>; 2793 status = "disabled"; 2794 2795 ports { 2796 #address-cells = <1>; 2797 #size-cells = <0>; 2798 2799 port@0 { 2800 reg = <0>; 2801 lvds0_in: endpoint { 2802 remote-endpoint = <&du_out_lvds0>; 2803 }; 2804 }; 2805 port@1 { 2806 reg = <1>; 2807 lvds0_out: endpoint { 2808 }; 2809 }; 2810 }; 2811 }; 2812 2813 prr: chipid@fff00044 { 2814 compatible = "renesas,prr"; 2815 reg = <0 0xfff00044 0 4>; 2816 }; 2817 }; 2818 2819 thermal-zones { 2820 sensor_thermal1: sensor-thermal1 { 2821 polling-delay-passive = <250>; 2822 polling-delay = <1000>; 2823 thermal-sensors = <&tsc 0>; 2824 sustainable-power = <6313>; 2825 2826 trips { 2827 sensor1_crit: sensor1-crit { 2828 temperature = <120000>; 2829 hysteresis = <1000>; 2830 type = "critical"; 2831 }; 2832 }; 2833 }; 2834 2835 sensor_thermal2: sensor-thermal2 { 2836 polling-delay-passive = <250>; 2837 polling-delay = <1000>; 2838 thermal-sensors = <&tsc 1>; 2839 sustainable-power = <6313>; 2840 2841 trips { 2842 sensor2_crit: sensor2-crit { 2843 temperature = <120000>; 2844 hysteresis = <1000>; 2845 type = "critical"; 2846 }; 2847 }; 2848 }; 2849 2850 sensor_thermal3: sensor-thermal3 { 2851 polling-delay-passive = <250>; 2852 polling-delay = <1000>; 2853 thermal-sensors = <&tsc 2>; 2854 sustainable-power = <6313>; 2855 2856 trips { 2857 target: trip-point1 { 2858 temperature = <100000>; 2859 hysteresis = <1000>; 2860 type = "passive"; 2861 }; 2862 2863 sensor3_crit: sensor3-crit { 2864 temperature = <120000>; 2865 hysteresis = <1000>; 2866 type = "critical"; 2867 }; 2868 }; 2869 2870 cooling-maps { 2871 map0 { 2872 trip = <&target>; 2873 cooling-device = <&a57_0 0 2>; 2874 contribution = <1024>; 2875 }; 2876 2877 map1 { 2878 trip = <&target>; 2879 cooling-device = <&a53_0 0 2>; 2880 contribution = <1024>; 2881 }; 2882 }; 2883 }; 2884 }; 2885 2886 timer { 2887 compatible = "arm,armv8-timer"; 2888 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2889 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2890 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2891 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2892 }; 2893 2894 /* External USB clocks - can be overridden by the board */ 2895 usb3s0_clk: usb3s0 { 2896 compatible = "fixed-clock"; 2897 #clock-cells = <0>; 2898 clock-frequency = <0>; 2899 }; 2900 2901 usb_extal_clk: usb_extal { 2902 compatible = "fixed-clock"; 2903 #clock-cells = <0>; 2904 clock-frequency = <0>; 2905 }; 2906}; 2907