1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774e1 SoC 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774e1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774e1-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a774e1"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 /* 21 * The external audio clocks are configured as 0 Hz fixed frequency 22 * clocks by default. 23 * Boards that provide audio clocks should override them. 24 */ 25 audio_clk_a: audio_clk_a { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <0>; 29 }; 30 31 audio_clk_c: audio_clk_c { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 cpus { 38 #address-cells = <1>; 39 #size-cells = <0>; 40 41 cpu-map { 42 cluster0 { 43 core0 { 44 cpu = <&a57_0>; 45 }; 46 core1 { 47 cpu = <&a57_1>; 48 }; 49 core2 { 50 cpu = <&a57_2>; 51 }; 52 core3 { 53 cpu = <&a57_3>; 54 }; 55 }; 56 57 cluster1 { 58 core0 { 59 cpu = <&a53_0>; 60 }; 61 core1 { 62 cpu = <&a53_1>; 63 }; 64 core2 { 65 cpu = <&a53_2>; 66 }; 67 core3 { 68 cpu = <&a53_3>; 69 }; 70 }; 71 }; 72 73 a57_0: cpu@0 { 74 compatible = "arm,cortex-a57"; 75 reg = <0x0>; 76 device_type = "cpu"; 77 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; 78 next-level-cache = <&L2_CA57>; 79 enable-method = "psci"; 80 dynamic-power-coefficient = <854>; 81 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 82 capacity-dmips-mhz = <1024>; 83 #cooling-cells = <2>; 84 }; 85 86 a57_1: cpu@1 { 87 compatible = "arm,cortex-a57"; 88 reg = <0x1>; 89 device_type = "cpu"; 90 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; 91 next-level-cache = <&L2_CA57>; 92 enable-method = "psci"; 93 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 94 capacity-dmips-mhz = <1024>; 95 #cooling-cells = <2>; 96 }; 97 98 a57_2: cpu@2 { 99 compatible = "arm,cortex-a57"; 100 reg = <0x2>; 101 device_type = "cpu"; 102 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; 103 next-level-cache = <&L2_CA57>; 104 enable-method = "psci"; 105 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 106 capacity-dmips-mhz = <1024>; 107 #cooling-cells = <2>; 108 }; 109 110 a57_3: cpu@3 { 111 compatible = "arm,cortex-a57"; 112 reg = <0x3>; 113 device_type = "cpu"; 114 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; 115 next-level-cache = <&L2_CA57>; 116 enable-method = "psci"; 117 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; 118 capacity-dmips-mhz = <1024>; 119 #cooling-cells = <2>; 120 }; 121 122 a53_0: cpu@100 { 123 compatible = "arm,cortex-a53"; 124 reg = <0x100>; 125 device_type = "cpu"; 126 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; 127 next-level-cache = <&L2_CA53>; 128 enable-method = "psci"; 129 #cooling-cells = <2>; 130 dynamic-power-coefficient = <277>; 131 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 132 capacity-dmips-mhz = <535>; 133 }; 134 135 a53_1: cpu@101 { 136 compatible = "arm,cortex-a53"; 137 reg = <0x101>; 138 device_type = "cpu"; 139 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; 140 next-level-cache = <&L2_CA53>; 141 enable-method = "psci"; 142 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 143 capacity-dmips-mhz = <535>; 144 }; 145 146 a53_2: cpu@102 { 147 compatible = "arm,cortex-a53"; 148 reg = <0x102>; 149 device_type = "cpu"; 150 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; 151 next-level-cache = <&L2_CA53>; 152 enable-method = "psci"; 153 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 154 capacity-dmips-mhz = <535>; 155 }; 156 157 a53_3: cpu@103 { 158 compatible = "arm,cortex-a53"; 159 reg = <0x103>; 160 device_type = "cpu"; 161 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; 162 next-level-cache = <&L2_CA53>; 163 enable-method = "psci"; 164 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; 165 capacity-dmips-mhz = <535>; 166 }; 167 168 L2_CA57: cache-controller-0 { 169 compatible = "cache"; 170 power-domains = <&sysc R8A774E1_PD_CA57_SCU>; 171 cache-unified; 172 cache-level = <2>; 173 }; 174 175 L2_CA53: cache-controller-1 { 176 compatible = "cache"; 177 power-domains = <&sysc R8A774E1_PD_CA53_SCU>; 178 cache-unified; 179 cache-level = <2>; 180 }; 181 }; 182 183 extal_clk: extal { 184 compatible = "fixed-clock"; 185 #clock-cells = <0>; 186 /* This value must be overridden by the board */ 187 clock-frequency = <0>; 188 }; 189 190 extalr_clk: extalr { 191 compatible = "fixed-clock"; 192 #clock-cells = <0>; 193 /* This value must be overridden by the board */ 194 clock-frequency = <0>; 195 }; 196 197 /* External PCIe clock - can be overridden by the board */ 198 pcie_bus_clk: pcie_bus { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <0>; 202 }; 203 204 pmu_a53 { 205 compatible = "arm,cortex-a53-pmu"; 206 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 207 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 208 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 209 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 210 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 211 }; 212 213 pmu_a57 { 214 compatible = "arm,cortex-a57-pmu"; 215 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 216 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 217 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 218 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 219 interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0", "arm,psci-0.2"; 224 method = "smc"; 225 }; 226 227 /* External SCIF clock - to be overridden by boards that provide it */ 228 scif_clk: scif { 229 compatible = "fixed-clock"; 230 #clock-cells = <0>; 231 clock-frequency = <0>; 232 }; 233 234 soc { 235 compatible = "simple-bus"; 236 interrupt-parent = <&gic>; 237 #address-cells = <2>; 238 #size-cells = <2>; 239 ranges; 240 241 rwdt: watchdog@e6020000 { 242 reg = <0 0xe6020000 0 0x0c>; 243 status = "disabled"; 244 245 /* placeholder */ 246 }; 247 248 gpio0: gpio@e6050000 { 249 reg = <0 0xe6050000 0 0x50>; 250 #gpio-cells = <2>; 251 gpio-controller; 252 #interrupt-cells = <2>; 253 interrupt-controller; 254 255 /* placeholder */ 256 }; 257 258 gpio1: gpio@e6051000 { 259 reg = <0 0xe6051000 0 0x50>; 260 #gpio-cells = <2>; 261 gpio-controller; 262 #interrupt-cells = <2>; 263 interrupt-controller; 264 265 /* placeholder */ 266 }; 267 268 gpio2: gpio@e6052000 { 269 reg = <0 0xe6052000 0 0x50>; 270 #gpio-cells = <2>; 271 gpio-controller; 272 #interrupt-cells = <2>; 273 interrupt-controller; 274 275 /* placeholder */ 276 }; 277 278 gpio3: gpio@e6053000 { 279 /* placeholder */ 280 reg = <0 0xe6053000 0 0x50>; 281 #gpio-cells = <2>; 282 gpio-controller; 283 #interrupt-cells = <2>; 284 interrupt-controller; 285 286 /* placeholder */ 287 }; 288 289 gpio4: gpio@e6054000 { 290 reg = <0 0xe6054000 0 0x50>; 291 #gpio-cells = <2>; 292 gpio-controller; 293 #interrupt-cells = <2>; 294 interrupt-controller; 295 296 /* placeholder */ 297 }; 298 299 gpio5: gpio@e6055000 { 300 reg = <0 0xe6055000 0 0x50>; 301 #gpio-cells = <2>; 302 gpio-controller; 303 #interrupt-cells = <2>; 304 interrupt-controller; 305 306 /* placeholder */ 307 }; 308 309 gpio6: gpio@e6055400 { 310 reg = <0 0xe6055400 0 0x50>; 311 #gpio-cells = <2>; 312 gpio-controller; 313 #interrupt-cells = <2>; 314 interrupt-controller; 315 316 /* placeholder */ 317 }; 318 319 gpio7: gpio@e6055800 { 320 reg = <0 0xe6055800 0 0x50>; 321 #gpio-cells = <2>; 322 gpio-controller; 323 #interrupt-cells = <2>; 324 interrupt-controller; 325 326 /* placeholder */ 327 }; 328 329 pfc: pin-controller@e6060000 { 330 compatible = "renesas,pfc-r8a774e1"; 331 reg = <0 0xe6060000 0 0x50c>; 332 }; 333 334 cpg: clock-controller@e6150000 { 335 compatible = "renesas,r8a774e1-cpg-mssr"; 336 reg = <0 0xe6150000 0 0x1000>; 337 clocks = <&extal_clk>, <&extalr_clk>; 338 clock-names = "extal", "extalr"; 339 #clock-cells = <2>; 340 #power-domain-cells = <0>; 341 #reset-cells = <1>; 342 }; 343 344 rst: reset-controller@e6160000 { 345 compatible = "renesas,r8a774e1-rst"; 346 reg = <0 0xe6160000 0 0x0200>; 347 }; 348 349 sysc: system-controller@e6180000 { 350 compatible = "renesas,r8a774e1-sysc"; 351 reg = <0 0xe6180000 0 0x0400>; 352 #power-domain-cells = <1>; 353 }; 354 355 intc_ex: interrupt-controller@e61c0000 { 356 compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; 357 #interrupt-cells = <2>; 358 interrupt-controller; 359 reg = <0 0xe61c0000 0 0x200>; 360 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&cpg CPG_MOD 407>; 367 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 368 resets = <&cpg 407>; 369 }; 370 371 i2c2: i2c@e6510000 { 372 reg = <0 0xe6510000 0 0x40>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 status = "disabled"; 376 377 /* placeholder */ 378 }; 379 380 i2c4: i2c@e66d8000 { 381 #address-cells = <1>; 382 #size-cells = <0>; 383 reg = <0 0xe66d8000 0 0x40>; 384 status = "disabled"; 385 386 /* placeholder */ 387 }; 388 389 hscif0: serial@e6540000 { 390 reg = <0 0xe6540000 0 0x60>; 391 status = "disabled"; 392 393 /* placeholder */ 394 }; 395 396 hsusb: usb@e6590000 { 397 reg = <0 0xe6590000 0 0x200>; 398 status = "disabled"; 399 400 /* placeholder */ 401 }; 402 403 usb3_phy0: usb-phy@e65ee000 { 404 reg = <0 0xe65ee000 0 0x90>; 405 #phy-cells = <0>; 406 status = "disabled"; 407 408 /* placeholder */ 409 }; 410 411 ipmmu_ds0: iommu@e6740000 { 412 compatible = "renesas,ipmmu-r8a774e1"; 413 reg = <0 0xe6740000 0 0x1000>; 414 renesas,ipmmu-main = <&ipmmu_mm 0>; 415 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 416 #iommu-cells = <1>; 417 }; 418 419 ipmmu_ds1: iommu@e7740000 { 420 compatible = "renesas,ipmmu-r8a774e1"; 421 reg = <0 0xe7740000 0 0x1000>; 422 renesas,ipmmu-main = <&ipmmu_mm 1>; 423 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 424 #iommu-cells = <1>; 425 }; 426 427 ipmmu_hc: iommu@e6570000 { 428 compatible = "renesas,ipmmu-r8a774e1"; 429 reg = <0 0xe6570000 0 0x1000>; 430 renesas,ipmmu-main = <&ipmmu_mm 2>; 431 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 432 #iommu-cells = <1>; 433 }; 434 435 ipmmu_mm: iommu@e67b0000 { 436 compatible = "renesas,ipmmu-r8a774e1"; 437 reg = <0 0xe67b0000 0 0x1000>; 438 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 440 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 441 #iommu-cells = <1>; 442 }; 443 444 ipmmu_mp0: iommu@ec670000 { 445 compatible = "renesas,ipmmu-r8a774e1"; 446 reg = <0 0xec670000 0 0x1000>; 447 renesas,ipmmu-main = <&ipmmu_mm 4>; 448 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 449 #iommu-cells = <1>; 450 }; 451 452 ipmmu_pv0: iommu@fd800000 { 453 compatible = "renesas,ipmmu-r8a774e1"; 454 reg = <0 0xfd800000 0 0x1000>; 455 renesas,ipmmu-main = <&ipmmu_mm 6>; 456 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 457 #iommu-cells = <1>; 458 }; 459 460 ipmmu_pv1: iommu@fd950000 { 461 compatible = "renesas,ipmmu-r8a774e1"; 462 reg = <0 0xfd950000 0 0x1000>; 463 renesas,ipmmu-main = <&ipmmu_mm 7>; 464 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 465 #iommu-cells = <1>; 466 }; 467 468 ipmmu_pv2: iommu@fd960000 { 469 compatible = "renesas,ipmmu-r8a774e1"; 470 reg = <0 0xfd960000 0 0x1000>; 471 renesas,ipmmu-main = <&ipmmu_mm 8>; 472 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 473 #iommu-cells = <1>; 474 }; 475 476 ipmmu_pv3: iommu@fd970000 { 477 compatible = "renesas,ipmmu-r8a774e1"; 478 reg = <0 0xfd970000 0 0x1000>; 479 renesas,ipmmu-main = <&ipmmu_mm 9>; 480 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 481 #iommu-cells = <1>; 482 }; 483 484 ipmmu_vc0: iommu@fe6b0000 { 485 compatible = "renesas,ipmmu-r8a774e1"; 486 reg = <0 0xfe6b0000 0 0x1000>; 487 renesas,ipmmu-main = <&ipmmu_mm 12>; 488 power-domains = <&sysc R8A774E1_PD_A3VC>; 489 #iommu-cells = <1>; 490 }; 491 492 ipmmu_vc1: iommu@fe6f0000 { 493 compatible = "renesas,ipmmu-r8a774e1"; 494 reg = <0 0xfe6f0000 0 0x1000>; 495 renesas,ipmmu-main = <&ipmmu_mm 13>; 496 power-domains = <&sysc R8A774E1_PD_A3VC>; 497 #iommu-cells = <1>; 498 }; 499 500 ipmmu_vi0: iommu@febd0000 { 501 compatible = "renesas,ipmmu-r8a774e1"; 502 reg = <0 0xfebd0000 0 0x1000>; 503 renesas,ipmmu-main = <&ipmmu_mm 14>; 504 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 505 #iommu-cells = <1>; 506 }; 507 508 ipmmu_vi1: iommu@febe0000 { 509 compatible = "renesas,ipmmu-r8a774e1"; 510 reg = <0 0xfebe0000 0 0x1000>; 511 renesas,ipmmu-main = <&ipmmu_mm 15>; 512 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 513 #iommu-cells = <1>; 514 }; 515 516 ipmmu_vp0: iommu@fe990000 { 517 compatible = "renesas,ipmmu-r8a774e1"; 518 reg = <0 0xfe990000 0 0x1000>; 519 renesas,ipmmu-main = <&ipmmu_mm 16>; 520 power-domains = <&sysc R8A774E1_PD_A3VP>; 521 #iommu-cells = <1>; 522 }; 523 524 ipmmu_vp1: iommu@fe980000 { 525 compatible = "renesas,ipmmu-r8a774e1"; 526 reg = <0 0xfe980000 0 0x1000>; 527 renesas,ipmmu-main = <&ipmmu_mm 17>; 528 power-domains = <&sysc R8A774E1_PD_A3VP>; 529 #iommu-cells = <1>; 530 }; 531 532 avb: ethernet@e6800000 { 533 reg = <0 0xe6800000 0 0x800>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 status = "disabled"; 537 538 /* placeholder */ 539 }; 540 541 can0: can@e6c30000 { 542 reg = <0 0xe6c30000 0 0x1000>; 543 status = "disabled"; 544 545 /* placeholder */ 546 }; 547 548 can1: can@e6c38000 { 549 reg = <0 0xe6c38000 0 0x1000>; 550 status = "disabled"; 551 552 /* placeholder */ 553 }; 554 555 pwm0: pwm@e6e30000 { 556 reg = <0 0xe6e30000 0 0x8>; 557 #pwm-cells = <2>; 558 status = "disabled"; 559 560 /* placeholder */ 561 }; 562 563 scif2: serial@e6e88000 { 564 compatible = "renesas,scif-r8a774e1", 565 "renesas,rcar-gen3-scif", "renesas,scif"; 566 reg = <0 0xe6e88000 0 0x40>; 567 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&cpg CPG_MOD 310>, 569 <&cpg CPG_CORE R8A774E1_CLK_S3D1>, 570 <&scif_clk>; 571 clock-names = "fck", "brg_int", "scif_clk"; 572 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 573 resets = <&cpg 310>; 574 status = "disabled"; 575 }; 576 577 rcar_sound: sound@ec500000 { 578 reg = <0 0xec500000 0 0x1000>, /* SCU */ 579 <0 0xec5a0000 0 0x100>, /* ADG */ 580 <0 0xec540000 0 0x1000>, /* SSIU */ 581 <0 0xec541000 0 0x280>, /* SSI */ 582 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 583 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 584 585 status = "disabled"; 586 587 /* placeholder */ 588 589 rcar_sound,ssi { 590 ssi2: ssi-2 { 591 /* placeholder */ 592 }; 593 }; 594 }; 595 596 xhci0: usb@ee000000 { 597 reg = <0 0xee000000 0 0xc00>; 598 status = "disabled"; 599 600 /* placeholder */ 601 }; 602 603 usb3_peri0: usb@ee020000 { 604 reg = <0 0xee020000 0 0x400>; 605 status = "disabled"; 606 607 /* placeholder */ 608 }; 609 610 ohci0: usb@ee080000 { 611 reg = <0 0xee080000 0 0x100>; 612 status = "disabled"; 613 614 /* placeholder */ 615 }; 616 617 ohci1: usb@ee0a0000 { 618 reg = <0 0xee0a0000 0 0x100>; 619 status = "disabled"; 620 621 /* placeholder */ 622 }; 623 624 ehci0: usb@ee080100 { 625 reg = <0 0xee080100 0 0x100>; 626 status = "disabled"; 627 628 /* placeholder */ 629 }; 630 631 ehci1: usb@ee0a0100 { 632 reg = <0 0xee0a0100 0 0x100>; 633 status = "disabled"; 634 635 /* placeholder */ 636 }; 637 638 usb2_phy0: usb-phy@ee080200 { 639 reg = <0 0xee080200 0 0x700>; 640 status = "disabled"; 641 642 /* placeholder */ 643 }; 644 645 usb2_phy1: usb-phy@ee0a0200 { 646 reg = <0 0xee0a0200 0 0x700>; 647 status = "disabled"; 648 649 /* placeholder */ 650 }; 651 652 sdhi0: mmc@ee100000 { 653 reg = <0 0xee100000 0 0x2000>; 654 status = "disabled"; 655 656 /* placeholder */ 657 }; 658 659 sdhi2: mmc@ee140000 { 660 reg = <0 0xee140000 0 0x2000>; 661 status = "disabled"; 662 663 /* placeholder */ 664 }; 665 666 sdhi3: mmc@ee160000 { 667 compatible = "renesas,sdhi-r8a774e1", 668 "renesas,rcar-gen3-sdhi"; 669 reg = <0 0xee160000 0 0x2000>; 670 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&cpg CPG_MOD 311>; 672 max-frequency = <200000000>; 673 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 674 resets = <&cpg 311>; 675 status = "disabled"; 676 }; 677 678 gic: interrupt-controller@f1010000 { 679 compatible = "arm,gic-400"; 680 #interrupt-cells = <3>; 681 #address-cells = <0>; 682 interrupt-controller; 683 reg = <0x0 0xf1010000 0 0x1000>, 684 <0x0 0xf1020000 0 0x20000>, 685 <0x0 0xf1040000 0 0x20000>, 686 <0x0 0xf1060000 0 0x20000>; 687 interrupts = <GIC_PPI 9 688 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 689 clocks = <&cpg CPG_MOD 408>; 690 clock-names = "clk"; 691 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; 692 resets = <&cpg 408>; 693 }; 694 695 pciec0: pcie@fe000000 { 696 reg = <0 0xfe000000 0 0x80000>; 697 #address-cells = <3>; 698 #size-cells = <2>; 699 status = "disabled"; 700 701 /* placeholder */ 702 }; 703 704 hdmi0: hdmi@fead0000 { 705 reg = <0 0xfead0000 0 0x10000>; 706 status = "disabled"; 707 708 /* placeholder */ 709 710 ports { 711 #address-cells = <1>; 712 #size-cells = <0>; 713 714 port@0 { 715 reg = <0>; 716 }; 717 port@1 { 718 reg = <1>; 719 }; 720 port@2 { 721 reg = <2>; 722 }; 723 }; 724 }; 725 726 du: display@feb00000 { 727 reg = <0 0xfeb00000 0 0x80000>; 728 status = "disabled"; 729 730 /* placeholder */ 731 ports { 732 #address-cells = <1>; 733 #size-cells = <0>; 734 735 port@0 { 736 reg = <0>; 737 }; 738 port@1 { 739 reg = <1>; 740 }; 741 port@2 { 742 reg = <2>; 743 }; 744 }; 745 }; 746 747 prr: chipid@fff00044 { 748 compatible = "renesas,prr"; 749 reg = <0 0xfff00044 0 4>; 750 }; 751 }; 752 753 timer { 754 compatible = "arm,armv8-timer"; 755 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 756 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 757 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 758 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 759 }; 760 761 /* External USB clocks - can be overridden by the board */ 762 usb3s0_clk: usb3s0 { 763 compatible = "fixed-clock"; 764 #clock-cells = <0>; 765 clock-frequency = <0>; 766 }; 767 768 usb_extal_clk: usb_extal { 769 compatible = "fixed-clock"; 770 #clock-cells = <0>; 771 clock-frequency = <0>; 772 }; 773}; 774