1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774b1 SoC 4 * 5 * Copyright (C) 2019 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774b1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774b1-sysc.h> 12 13/ { 14 compatible = "renesas,r8a774b1"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* 19 * The external audio clocks are configured as 0 Hz fixed frequency 20 * clocks by default. 21 * Boards that provide audio clocks should override them. 22 */ 23 audio_clk_a: audio_clk_a { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <0>; 27 }; 28 29 audio_clk_b: audio_clk_b { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 33 }; 34 35 audio_clk_c: audio_clk_c { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <0>; 39 }; 40 41 /* External CAN clock - to be overridden by boards that provide it */ 42 can_clk: can { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <0>; 46 }; 47 48 cluster0_opp: opp_table0 { 49 compatible = "operating-points-v2"; 50 opp-shared; 51 52 opp-500000000 { 53 opp-hz = /bits/ 64 <500000000>; 54 opp-microvolt = <830000>; 55 clock-latency-ns = <300000>; 56 }; 57 opp-1000000000 { 58 opp-hz = /bits/ 64 <1000000000>; 59 opp-microvolt = <830000>; 60 clock-latency-ns = <300000>; 61 }; 62 opp-1500000000 { 63 opp-hz = /bits/ 64 <1500000000>; 64 opp-microvolt = <830000>; 65 clock-latency-ns = <300000>; 66 opp-suspend; 67 }; 68 }; 69 70 cpus { 71 #address-cells = <1>; 72 #size-cells = <0>; 73 74 a57_0: cpu@0 { 75 compatible = "arm,cortex-a57"; 76 reg = <0x0>; 77 device_type = "cpu"; 78 power-domains = <&sysc R8A774B1_PD_CA57_CPU0>; 79 next-level-cache = <&L2_CA57>; 80 enable-method = "psci"; 81 #cooling-cells = <2>; 82 dynamic-power-coefficient = <854>; 83 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; 84 operating-points-v2 = <&cluster0_opp>; 85 }; 86 87 a57_1: cpu@1 { 88 compatible = "arm,cortex-a57"; 89 reg = <0x1>; 90 device_type = "cpu"; 91 power-domains = <&sysc R8A774B1_PD_CA57_CPU1>; 92 next-level-cache = <&L2_CA57>; 93 enable-method = "psci"; 94 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; 95 operating-points-v2 = <&cluster0_opp>; 96 }; 97 98 L2_CA57: cache-controller-0 { 99 compatible = "cache"; 100 power-domains = <&sysc R8A774B1_PD_CA57_SCU>; 101 cache-unified; 102 cache-level = <2>; 103 }; 104 }; 105 106 extal_clk: extal { 107 compatible = "fixed-clock"; 108 #clock-cells = <0>; 109 /* This value must be overridden by the board */ 110 clock-frequency = <0>; 111 }; 112 113 extalr_clk: extalr { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 /* This value must be overridden by the board */ 117 clock-frequency = <0>; 118 }; 119 120 /* External PCIe clock - can be overridden by the board */ 121 pcie_bus_clk: pcie_bus { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <0>; 125 }; 126 127 pmu_a57 { 128 compatible = "arm,cortex-a57-pmu"; 129 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 130 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-affinity = <&a57_0>, <&a57_1>; 132 }; 133 134 psci { 135 compatible = "arm,psci-1.0", "arm,psci-0.2"; 136 method = "smc"; 137 }; 138 139 /* External SCIF clock - to be overridden by boards that provide it */ 140 scif_clk: scif { 141 compatible = "fixed-clock"; 142 #clock-cells = <0>; 143 clock-frequency = <0>; 144 }; 145 146 soc { 147 compatible = "simple-bus"; 148 interrupt-parent = <&gic>; 149 #address-cells = <2>; 150 #size-cells = <2>; 151 ranges; 152 153 rwdt: watchdog@e6020000 { 154 reg = <0 0xe6020000 0 0x0c>; 155 /* placeholder */ 156 }; 157 158 gpio0: gpio@e6050000 { 159 compatible = "renesas,gpio-r8a774b1", 160 "renesas,rcar-gen3-gpio"; 161 reg = <0 0xe6050000 0 0x50>; 162 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 163 #gpio-cells = <2>; 164 gpio-controller; 165 gpio-ranges = <&pfc 0 0 16>; 166 #interrupt-cells = <2>; 167 interrupt-controller; 168 clocks = <&cpg CPG_MOD 912>; 169 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 170 resets = <&cpg 912>; 171 }; 172 173 gpio1: gpio@e6051000 { 174 compatible = "renesas,gpio-r8a774b1", 175 "renesas,rcar-gen3-gpio"; 176 reg = <0 0xe6051000 0 0x50>; 177 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 178 #gpio-cells = <2>; 179 gpio-controller; 180 gpio-ranges = <&pfc 0 32 29>; 181 #interrupt-cells = <2>; 182 interrupt-controller; 183 clocks = <&cpg CPG_MOD 911>; 184 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 185 resets = <&cpg 911>; 186 }; 187 188 gpio2: gpio@e6052000 { 189 compatible = "renesas,gpio-r8a774b1", 190 "renesas,rcar-gen3-gpio"; 191 reg = <0 0xe6052000 0 0x50>; 192 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 193 #gpio-cells = <2>; 194 gpio-controller; 195 gpio-ranges = <&pfc 0 64 15>; 196 #interrupt-cells = <2>; 197 interrupt-controller; 198 clocks = <&cpg CPG_MOD 910>; 199 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 200 resets = <&cpg 910>; 201 }; 202 203 gpio3: gpio@e6053000 { 204 compatible = "renesas,gpio-r8a774b1", 205 "renesas,rcar-gen3-gpio"; 206 reg = <0 0xe6053000 0 0x50>; 207 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 208 #gpio-cells = <2>; 209 gpio-controller; 210 gpio-ranges = <&pfc 0 96 16>; 211 #interrupt-cells = <2>; 212 interrupt-controller; 213 clocks = <&cpg CPG_MOD 909>; 214 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 215 resets = <&cpg 909>; 216 }; 217 218 gpio4: gpio@e6054000 { 219 compatible = "renesas,gpio-r8a774b1", 220 "renesas,rcar-gen3-gpio"; 221 reg = <0 0xe6054000 0 0x50>; 222 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 223 #gpio-cells = <2>; 224 gpio-controller; 225 gpio-ranges = <&pfc 0 128 18>; 226 #interrupt-cells = <2>; 227 interrupt-controller; 228 clocks = <&cpg CPG_MOD 908>; 229 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 230 resets = <&cpg 908>; 231 }; 232 233 gpio5: gpio@e6055000 { 234 compatible = "renesas,gpio-r8a774b1", 235 "renesas,rcar-gen3-gpio"; 236 reg = <0 0xe6055000 0 0x50>; 237 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 238 #gpio-cells = <2>; 239 gpio-controller; 240 gpio-ranges = <&pfc 0 160 26>; 241 #interrupt-cells = <2>; 242 interrupt-controller; 243 clocks = <&cpg CPG_MOD 907>; 244 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 245 resets = <&cpg 907>; 246 }; 247 248 gpio6: gpio@e6055400 { 249 compatible = "renesas,gpio-r8a774b1", 250 "renesas,rcar-gen3-gpio"; 251 reg = <0 0xe6055400 0 0x50>; 252 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 253 #gpio-cells = <2>; 254 gpio-controller; 255 gpio-ranges = <&pfc 0 192 32>; 256 #interrupt-cells = <2>; 257 interrupt-controller; 258 clocks = <&cpg CPG_MOD 906>; 259 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 260 resets = <&cpg 906>; 261 }; 262 263 gpio7: gpio@e6055800 { 264 compatible = "renesas,gpio-r8a774b1", 265 "renesas,rcar-gen3-gpio"; 266 reg = <0 0xe6055800 0 0x50>; 267 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 268 #gpio-cells = <2>; 269 gpio-controller; 270 gpio-ranges = <&pfc 0 224 4>; 271 #interrupt-cells = <2>; 272 interrupt-controller; 273 clocks = <&cpg CPG_MOD 905>; 274 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 275 resets = <&cpg 905>; 276 }; 277 278 pfc: pin-controller@e6060000 { 279 compatible = "renesas,pfc-r8a774b1"; 280 reg = <0 0xe6060000 0 0x50c>; 281 }; 282 283 cmt0: timer@e60f0000 { 284 compatible = "renesas,r8a774b1-cmt0", 285 "renesas,rcar-gen3-cmt0"; 286 reg = <0 0xe60f0000 0 0x1004>; 287 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&cpg CPG_MOD 303>; 290 clock-names = "fck"; 291 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 292 resets = <&cpg 303>; 293 status = "disabled"; 294 }; 295 296 cmt1: timer@e6130000 { 297 compatible = "renesas,r8a774b1-cmt1", 298 "renesas,rcar-gen3-cmt1"; 299 reg = <0 0xe6130000 0 0x1004>; 300 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&cpg CPG_MOD 302>; 309 clock-names = "fck"; 310 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 311 resets = <&cpg 302>; 312 status = "disabled"; 313 }; 314 315 cmt2: timer@e6140000 { 316 compatible = "renesas,r8a774b1-cmt1", 317 "renesas,rcar-gen3-cmt1"; 318 reg = <0 0xe6140000 0 0x1004>; 319 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&cpg CPG_MOD 301>; 328 clock-names = "fck"; 329 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 330 resets = <&cpg 301>; 331 status = "disabled"; 332 }; 333 334 cmt3: timer@e6148000 { 335 compatible = "renesas,r8a774b1-cmt1", 336 "renesas,rcar-gen3-cmt1"; 337 reg = <0 0xe6148000 0 0x1004>; 338 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&cpg CPG_MOD 300>; 347 clock-names = "fck"; 348 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 349 resets = <&cpg 300>; 350 status = "disabled"; 351 }; 352 353 cpg: clock-controller@e6150000 { 354 compatible = "renesas,r8a774b1-cpg-mssr"; 355 reg = <0 0xe6150000 0 0x1000>; 356 clocks = <&extal_clk>, <&extalr_clk>; 357 clock-names = "extal", "extalr"; 358 #clock-cells = <2>; 359 #power-domain-cells = <0>; 360 #reset-cells = <1>; 361 }; 362 363 rst: reset-controller@e6160000 { 364 compatible = "renesas,r8a774b1-rst"; 365 reg = <0 0xe6160000 0 0x0200>; 366 }; 367 368 sysc: system-controller@e6180000 { 369 compatible = "renesas,r8a774b1-sysc"; 370 reg = <0 0xe6180000 0 0x0400>; 371 #power-domain-cells = <1>; 372 }; 373 374 tsc: thermal@e6198000 { 375 compatible = "renesas,r8a774b1-thermal"; 376 reg = <0 0xe6198000 0 0x100>, 377 <0 0xe61a0000 0 0x100>, 378 <0 0xe61a8000 0 0x100>; 379 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&cpg CPG_MOD 522>; 383 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 384 resets = <&cpg 522>; 385 #thermal-sensor-cells = <1>; 386 }; 387 388 tmu0: timer@e61e0000 { 389 compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; 390 reg = <0 0xe61e0000 0 0x30>; 391 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&cpg CPG_MOD 125>; 395 clock-names = "fck"; 396 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 397 resets = <&cpg 125>; 398 status = "disabled"; 399 }; 400 401 tmu1: timer@e6fc0000 { 402 compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; 403 reg = <0 0xe6fc0000 0 0x30>; 404 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&cpg CPG_MOD 124>; 408 clock-names = "fck"; 409 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 410 resets = <&cpg 124>; 411 status = "disabled"; 412 }; 413 414 tmu2: timer@e6fd0000 { 415 compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; 416 reg = <0 0xe6fd0000 0 0x30>; 417 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&cpg CPG_MOD 123>; 421 clock-names = "fck"; 422 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 423 resets = <&cpg 123>; 424 status = "disabled"; 425 }; 426 427 tmu3: timer@e6fe0000 { 428 compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; 429 reg = <0 0xe6fe0000 0 0x30>; 430 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&cpg CPG_MOD 122>; 434 clock-names = "fck"; 435 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 436 resets = <&cpg 122>; 437 status = "disabled"; 438 }; 439 440 tmu4: timer@ffc00000 { 441 compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; 442 reg = <0 0xffc00000 0 0x30>; 443 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&cpg CPG_MOD 121>; 447 clock-names = "fck"; 448 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 449 resets = <&cpg 121>; 450 status = "disabled"; 451 }; 452 453 i2c0: i2c@e6500000 { 454 #address-cells = <1>; 455 #size-cells = <0>; 456 compatible = "renesas,i2c-r8a774b1", 457 "renesas,rcar-gen3-i2c"; 458 reg = <0 0xe6500000 0 0x40>; 459 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&cpg CPG_MOD 931>; 461 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 462 resets = <&cpg 931>; 463 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 464 <&dmac2 0x91>, <&dmac2 0x90>; 465 dma-names = "tx", "rx", "tx", "rx"; 466 i2c-scl-internal-delay-ns = <110>; 467 status = "disabled"; 468 }; 469 470 i2c1: i2c@e6508000 { 471 #address-cells = <1>; 472 #size-cells = <0>; 473 compatible = "renesas,i2c-r8a774b1", 474 "renesas,rcar-gen3-i2c"; 475 reg = <0 0xe6508000 0 0x40>; 476 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&cpg CPG_MOD 930>; 478 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 479 resets = <&cpg 930>; 480 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 481 <&dmac2 0x93>, <&dmac2 0x92>; 482 dma-names = "tx", "rx", "tx", "rx"; 483 i2c-scl-internal-delay-ns = <6>; 484 status = "disabled"; 485 }; 486 487 i2c2: i2c@e6510000 { 488 #address-cells = <1>; 489 #size-cells = <0>; 490 compatible = "renesas,i2c-r8a774b1", 491 "renesas,rcar-gen3-i2c"; 492 reg = <0 0xe6510000 0 0x40>; 493 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&cpg CPG_MOD 929>; 495 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 496 resets = <&cpg 929>; 497 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 498 <&dmac2 0x95>, <&dmac2 0x94>; 499 dma-names = "tx", "rx", "tx", "rx"; 500 i2c-scl-internal-delay-ns = <6>; 501 status = "disabled"; 502 }; 503 504 i2c3: i2c@e66d0000 { 505 #address-cells = <1>; 506 #size-cells = <0>; 507 compatible = "renesas,i2c-r8a774b1", 508 "renesas,rcar-gen3-i2c"; 509 reg = <0 0xe66d0000 0 0x40>; 510 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&cpg CPG_MOD 928>; 512 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 513 resets = <&cpg 928>; 514 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 515 dma-names = "tx", "rx"; 516 i2c-scl-internal-delay-ns = <110>; 517 status = "disabled"; 518 }; 519 520 i2c4: i2c@e66d8000 { 521 #address-cells = <1>; 522 #size-cells = <0>; 523 compatible = "renesas,i2c-r8a774b1", 524 "renesas,rcar-gen3-i2c"; 525 reg = <0 0xe66d8000 0 0x40>; 526 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&cpg CPG_MOD 927>; 528 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 529 resets = <&cpg 927>; 530 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 531 dma-names = "tx", "rx"; 532 i2c-scl-internal-delay-ns = <110>; 533 status = "disabled"; 534 }; 535 536 i2c5: i2c@e66e0000 { 537 #address-cells = <1>; 538 #size-cells = <0>; 539 compatible = "renesas,i2c-r8a774b1", 540 "renesas,rcar-gen3-i2c"; 541 reg = <0 0xe66e0000 0 0x40>; 542 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&cpg CPG_MOD 919>; 544 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 545 resets = <&cpg 919>; 546 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 547 dma-names = "tx", "rx"; 548 i2c-scl-internal-delay-ns = <110>; 549 status = "disabled"; 550 }; 551 552 i2c6: i2c@e66e8000 { 553 #address-cells = <1>; 554 #size-cells = <0>; 555 compatible = "renesas,i2c-r8a774b1", 556 "renesas,rcar-gen3-i2c"; 557 reg = <0 0xe66e8000 0 0x40>; 558 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&cpg CPG_MOD 918>; 560 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 561 resets = <&cpg 918>; 562 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 563 dma-names = "tx", "rx"; 564 i2c-scl-internal-delay-ns = <6>; 565 status = "disabled"; 566 }; 567 568 i2c_dvfs: i2c@e60b0000 { 569 #address-cells = <1>; 570 #size-cells = <0>; 571 compatible = "renesas,iic-r8a774b1", 572 "renesas,rcar-gen3-iic", 573 "renesas,rmobile-iic"; 574 reg = <0 0xe60b0000 0 0x425>; 575 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&cpg CPG_MOD 926>; 577 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 578 resets = <&cpg 926>; 579 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 580 dma-names = "tx", "rx"; 581 status = "disabled"; 582 }; 583 584 hscif0: serial@e6540000 { 585 compatible = "renesas,hscif-r8a774b1", 586 "renesas,rcar-gen3-hscif", 587 "renesas,hscif"; 588 reg = <0 0xe6540000 0 0x60>; 589 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&cpg CPG_MOD 520>, 591 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 592 <&scif_clk>; 593 clock-names = "fck", "brg_int", "scif_clk"; 594 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 595 <&dmac2 0x31>, <&dmac2 0x30>; 596 dma-names = "tx", "rx", "tx", "rx"; 597 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 598 resets = <&cpg 520>; 599 status = "disabled"; 600 }; 601 602 hscif1: serial@e6550000 { 603 compatible = "renesas,hscif-r8a774b1", 604 "renesas,rcar-gen3-hscif", 605 "renesas,hscif"; 606 reg = <0 0xe6550000 0 0x60>; 607 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&cpg CPG_MOD 519>, 609 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 610 <&scif_clk>; 611 clock-names = "fck", "brg_int", "scif_clk"; 612 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 613 <&dmac2 0x33>, <&dmac2 0x32>; 614 dma-names = "tx", "rx", "tx", "rx"; 615 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 616 resets = <&cpg 519>; 617 status = "disabled"; 618 }; 619 620 hscif2: serial@e6560000 { 621 compatible = "renesas,hscif-r8a774b1", 622 "renesas,rcar-gen3-hscif", 623 "renesas,hscif"; 624 reg = <0 0xe6560000 0 0x60>; 625 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&cpg CPG_MOD 518>, 627 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 628 <&scif_clk>; 629 clock-names = "fck", "brg_int", "scif_clk"; 630 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 631 <&dmac2 0x35>, <&dmac2 0x34>; 632 dma-names = "tx", "rx", "tx", "rx"; 633 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 634 resets = <&cpg 518>; 635 status = "disabled"; 636 }; 637 638 hscif3: serial@e66a0000 { 639 compatible = "renesas,hscif-r8a774b1", 640 "renesas,rcar-gen3-hscif", 641 "renesas,hscif"; 642 reg = <0 0xe66a0000 0 0x60>; 643 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&cpg CPG_MOD 517>, 645 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 646 <&scif_clk>; 647 clock-names = "fck", "brg_int", "scif_clk"; 648 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 649 dma-names = "tx", "rx"; 650 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 651 resets = <&cpg 517>; 652 status = "disabled"; 653 }; 654 655 hscif4: serial@e66b0000 { 656 compatible = "renesas,hscif-r8a774b1", 657 "renesas,rcar-gen3-hscif", 658 "renesas,hscif"; 659 reg = <0 0xe66b0000 0 0x60>; 660 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&cpg CPG_MOD 516>, 662 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 663 <&scif_clk>; 664 clock-names = "fck", "brg_int", "scif_clk"; 665 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 666 dma-names = "tx", "rx"; 667 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 668 resets = <&cpg 516>; 669 status = "disabled"; 670 }; 671 672 hsusb: usb@e6590000 { 673 reg = <0 0xe6590000 0 0x200>; 674 /* placeholder */ 675 }; 676 677 usb3_phy0: usb-phy@e65ee000 { 678 reg = <0 0xe65ee000 0 0x90>; 679 #phy-cells = <0>; 680 /* placeholder */ 681 }; 682 683 dmac0: dma-controller@e6700000 { 684 compatible = "renesas,dmac-r8a774b1", 685 "renesas,rcar-dmac"; 686 reg = <0 0xe6700000 0 0x10000>; 687 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 688 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 689 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 690 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 691 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 692 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 693 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 694 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 695 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 696 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 697 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 698 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 699 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 700 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 701 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 702 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 703 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 704 interrupt-names = "error", 705 "ch0", "ch1", "ch2", "ch3", 706 "ch4", "ch5", "ch6", "ch7", 707 "ch8", "ch9", "ch10", "ch11", 708 "ch12", "ch13", "ch14", "ch15"; 709 clocks = <&cpg CPG_MOD 219>; 710 clock-names = "fck"; 711 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 712 resets = <&cpg 219>; 713 #dma-cells = <1>; 714 dma-channels = <16>; 715 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 716 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 717 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 718 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 719 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 720 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 721 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 722 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 723 }; 724 725 dmac1: dma-controller@e7300000 { 726 compatible = "renesas,dmac-r8a774b1", 727 "renesas,rcar-dmac"; 728 reg = <0 0xe7300000 0 0x10000>; 729 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 730 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 731 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 732 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 733 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 734 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 735 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 736 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 737 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 738 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 739 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 740 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 741 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 742 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 743 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 744 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 745 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 746 interrupt-names = "error", 747 "ch0", "ch1", "ch2", "ch3", 748 "ch4", "ch5", "ch6", "ch7", 749 "ch8", "ch9", "ch10", "ch11", 750 "ch12", "ch13", "ch14", "ch15"; 751 clocks = <&cpg CPG_MOD 218>; 752 clock-names = "fck"; 753 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 754 resets = <&cpg 218>; 755 #dma-cells = <1>; 756 dma-channels = <16>; 757 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 758 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 759 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 760 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 761 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 762 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 763 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 764 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 765 }; 766 767 dmac2: dma-controller@e7310000 { 768 compatible = "renesas,dmac-r8a774b1", 769 "renesas,rcar-dmac"; 770 reg = <0 0xe7310000 0 0x10000>; 771 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 772 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 773 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 774 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 775 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 776 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 777 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 778 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 779 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 780 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 781 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 782 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 783 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 784 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 785 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 786 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 787 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 788 interrupt-names = "error", 789 "ch0", "ch1", "ch2", "ch3", 790 "ch4", "ch5", "ch6", "ch7", 791 "ch8", "ch9", "ch10", "ch11", 792 "ch12", "ch13", "ch14", "ch15"; 793 clocks = <&cpg CPG_MOD 217>; 794 clock-names = "fck"; 795 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 796 resets = <&cpg 217>; 797 #dma-cells = <1>; 798 dma-channels = <16>; 799 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 800 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 801 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 802 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 803 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 804 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 805 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 806 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 807 }; 808 809 ipmmu_ds0: mmu@e6740000 { 810 compatible = "renesas,ipmmu-r8a774b1"; 811 reg = <0 0xe6740000 0 0x1000>; 812 renesas,ipmmu-main = <&ipmmu_mm 0>; 813 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 814 #iommu-cells = <1>; 815 }; 816 817 ipmmu_ds1: mmu@e7740000 { 818 compatible = "renesas,ipmmu-r8a774b1"; 819 reg = <0 0xe7740000 0 0x1000>; 820 renesas,ipmmu-main = <&ipmmu_mm 1>; 821 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 822 #iommu-cells = <1>; 823 }; 824 825 ipmmu_hc: mmu@e6570000 { 826 compatible = "renesas,ipmmu-r8a774b1"; 827 reg = <0 0xe6570000 0 0x1000>; 828 renesas,ipmmu-main = <&ipmmu_mm 2>; 829 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 830 #iommu-cells = <1>; 831 }; 832 833 ipmmu_mm: mmu@e67b0000 { 834 compatible = "renesas,ipmmu-r8a774b1"; 835 reg = <0 0xe67b0000 0 0x1000>; 836 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 838 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 839 #iommu-cells = <1>; 840 }; 841 842 ipmmu_mp: mmu@ec670000 { 843 compatible = "renesas,ipmmu-r8a774b1"; 844 reg = <0 0xec670000 0 0x1000>; 845 renesas,ipmmu-main = <&ipmmu_mm 4>; 846 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 847 #iommu-cells = <1>; 848 }; 849 850 ipmmu_pv0: mmu@fd800000 { 851 compatible = "renesas,ipmmu-r8a774b1"; 852 reg = <0 0xfd800000 0 0x1000>; 853 renesas,ipmmu-main = <&ipmmu_mm 6>; 854 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 855 #iommu-cells = <1>; 856 }; 857 858 ipmmu_vc0: mmu@fe6b0000 { 859 compatible = "renesas,ipmmu-r8a774b1"; 860 reg = <0 0xfe6b0000 0 0x1000>; 861 renesas,ipmmu-main = <&ipmmu_mm 12>; 862 power-domains = <&sysc R8A774B1_PD_A3VC>; 863 #iommu-cells = <1>; 864 }; 865 866 ipmmu_vi0: mmu@febd0000 { 867 compatible = "renesas,ipmmu-r8a774b1"; 868 reg = <0 0xfebd0000 0 0x1000>; 869 renesas,ipmmu-main = <&ipmmu_mm 14>; 870 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 871 #iommu-cells = <1>; 872 }; 873 874 ipmmu_vp0: mmu@fe990000 { 875 compatible = "renesas,ipmmu-r8a774b1"; 876 reg = <0 0xfe990000 0 0x1000>; 877 renesas,ipmmu-main = <&ipmmu_mm 16>; 878 power-domains = <&sysc R8A774B1_PD_A3VP>; 879 #iommu-cells = <1>; 880 }; 881 882 avb: ethernet@e6800000 { 883 compatible = "renesas,etheravb-r8a774b1", 884 "renesas,etheravb-rcar-gen3"; 885 reg = <0 0xe6800000 0 0x800>; 886 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 911 interrupt-names = "ch0", "ch1", "ch2", "ch3", 912 "ch4", "ch5", "ch6", "ch7", 913 "ch8", "ch9", "ch10", "ch11", 914 "ch12", "ch13", "ch14", "ch15", 915 "ch16", "ch17", "ch18", "ch19", 916 "ch20", "ch21", "ch22", "ch23", 917 "ch24"; 918 clocks = <&cpg CPG_MOD 812>; 919 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 920 resets = <&cpg 812>; 921 phy-mode = "rgmii"; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 status = "disabled"; 925 }; 926 927 can0: can@e6c30000 { 928 reg = <0 0xe6c30000 0 0x1000>; 929 /* placeholder */ 930 }; 931 932 can1: can@e6c38000 { 933 reg = <0 0xe6c38000 0 0x1000>; 934 /* placeholder */ 935 }; 936 937 canfd: can@e66c0000 { 938 reg = <0 0xe66c0000 0 0x8000>; 939 /* placeholder */ 940 }; 941 942 scif0: serial@e6e60000 { 943 compatible = "renesas,scif-r8a774b1", 944 "renesas,rcar-gen3-scif", "renesas,scif"; 945 reg = <0 0xe6e60000 0 0x40>; 946 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&cpg CPG_MOD 207>, 948 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 949 <&scif_clk>; 950 clock-names = "fck", "brg_int", "scif_clk"; 951 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 952 <&dmac2 0x51>, <&dmac2 0x50>; 953 dma-names = "tx", "rx", "tx", "rx"; 954 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 955 resets = <&cpg 207>; 956 status = "disabled"; 957 }; 958 959 scif1: serial@e6e68000 { 960 compatible = "renesas,scif-r8a774b1", 961 "renesas,rcar-gen3-scif", "renesas,scif"; 962 reg = <0 0xe6e68000 0 0x40>; 963 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&cpg CPG_MOD 206>, 965 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 966 <&scif_clk>; 967 clock-names = "fck", "brg_int", "scif_clk"; 968 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 969 <&dmac2 0x53>, <&dmac2 0x52>; 970 dma-names = "tx", "rx", "tx", "rx"; 971 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 972 resets = <&cpg 206>; 973 status = "disabled"; 974 }; 975 976 scif2: serial@e6e88000 { 977 compatible = "renesas,scif-r8a774b1", 978 "renesas,rcar-gen3-scif", "renesas,scif"; 979 reg = <0 0xe6e88000 0 0x40>; 980 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&cpg CPG_MOD 310>, 982 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 983 <&scif_clk>; 984 clock-names = "fck", "brg_int", "scif_clk"; 985 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 986 <&dmac2 0x13>, <&dmac2 0x12>; 987 dma-names = "tx", "rx", "tx", "rx"; 988 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 989 resets = <&cpg 310>; 990 status = "disabled"; 991 }; 992 993 scif3: serial@e6c50000 { 994 compatible = "renesas,scif-r8a774b1", 995 "renesas,rcar-gen3-scif", "renesas,scif"; 996 reg = <0 0xe6c50000 0 0x40>; 997 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&cpg CPG_MOD 204>, 999 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 1000 <&scif_clk>; 1001 clock-names = "fck", "brg_int", "scif_clk"; 1002 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1003 dma-names = "tx", "rx"; 1004 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1005 resets = <&cpg 204>; 1006 status = "disabled"; 1007 }; 1008 1009 scif4: serial@e6c40000 { 1010 compatible = "renesas,scif-r8a774b1", 1011 "renesas,rcar-gen3-scif", "renesas,scif"; 1012 reg = <0 0xe6c40000 0 0x40>; 1013 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&cpg CPG_MOD 203>, 1015 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 1016 <&scif_clk>; 1017 clock-names = "fck", "brg_int", "scif_clk"; 1018 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1019 dma-names = "tx", "rx"; 1020 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1021 resets = <&cpg 203>; 1022 status = "disabled"; 1023 }; 1024 1025 scif5: serial@e6f30000 { 1026 compatible = "renesas,scif-r8a774b1", 1027 "renesas,rcar-gen3-scif", "renesas,scif"; 1028 reg = <0 0xe6f30000 0 0x40>; 1029 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1030 clocks = <&cpg CPG_MOD 202>, 1031 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 1032 <&scif_clk>; 1033 clock-names = "fck", "brg_int", "scif_clk"; 1034 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1035 <&dmac2 0x5b>, <&dmac2 0x5a>; 1036 dma-names = "tx", "rx", "tx", "rx"; 1037 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1038 resets = <&cpg 202>; 1039 status = "disabled"; 1040 }; 1041 1042 rcar_sound: sound@ec500000 { 1043 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1044 <0 0xec5a0000 0 0x100>, /* ADG */ 1045 <0 0xec540000 0 0x1000>, /* SSIU */ 1046 <0 0xec541000 0 0x280>, /* SSI */ 1047 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1048 1049 rcar_sound,ssi { 1050 ssi0: ssi-0 { }; 1051 ssi1: ssi-1 { }; 1052 ssi2: ssi-2 { }; 1053 ssi3: ssi-3 { }; 1054 ssi4: ssi-4 { }; 1055 ssi5: ssi-5 { }; 1056 ssi6: ssi-6 { }; 1057 ssi7: ssi-7 { }; 1058 ssi8: ssi-8 { }; 1059 ssi9: ssi-9 { }; 1060 }; 1061 }; 1062 1063 xhci0: usb@ee000000 { 1064 reg = <0 0xee000000 0 0xc00>; 1065 /* placeholder */ 1066 }; 1067 1068 usb3_peri0: usb@ee020000 { 1069 reg = <0 0xee020000 0 0x400>; 1070 /* placeholder */ 1071 }; 1072 1073 ohci0: usb@ee080000 { 1074 reg = <0 0xee080000 0 0x100>; 1075 /* placeholder */ 1076 }; 1077 1078 ohci1: usb@ee0a0000 { 1079 reg = <0 0xee0a0000 0 0x100>; 1080 /* placeholder */ 1081 }; 1082 1083 ehci0: usb@ee080100 { 1084 reg = <0 0xee080100 0 0x100>; 1085 /* placeholder */ 1086 }; 1087 1088 ehci1: usb@ee0a0100 { 1089 reg = <0 0xee0a0100 0 0x100>; 1090 /* placeholder */ 1091 }; 1092 1093 usb2_phy0: usb-phy@ee080200 { 1094 reg = <0 0xee080200 0 0x700>; 1095 /* placeholder */ 1096 }; 1097 1098 usb2_phy1: usb-phy@ee0a0200 { 1099 reg = <0 0xee0a0200 0 0x700>; 1100 /* placeholder */ 1101 }; 1102 1103 sdhi0: sd@ee100000 { 1104 compatible = "renesas,sdhi-r8a774b1", 1105 "renesas,rcar-gen3-sdhi"; 1106 reg = <0 0xee100000 0 0x2000>; 1107 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1108 clocks = <&cpg CPG_MOD 314>; 1109 max-frequency = <200000000>; 1110 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1111 resets = <&cpg 314>; 1112 status = "disabled"; 1113 }; 1114 1115 sdhi1: sd@ee120000 { 1116 compatible = "renesas,sdhi-r8a774b1", 1117 "renesas,rcar-gen3-sdhi"; 1118 reg = <0 0xee120000 0 0x2000>; 1119 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1120 clocks = <&cpg CPG_MOD 313>; 1121 max-frequency = <200000000>; 1122 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1123 resets = <&cpg 313>; 1124 status = "disabled"; 1125 }; 1126 1127 sdhi2: sd@ee140000 { 1128 compatible = "renesas,sdhi-r8a774b1", 1129 "renesas,rcar-gen3-sdhi"; 1130 reg = <0 0xee140000 0 0x2000>; 1131 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&cpg CPG_MOD 312>; 1133 max-frequency = <200000000>; 1134 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1135 resets = <&cpg 312>; 1136 status = "disabled"; 1137 }; 1138 1139 sdhi3: sd@ee160000 { 1140 compatible = "renesas,sdhi-r8a774b1", 1141 "renesas,rcar-gen3-sdhi"; 1142 reg = <0 0xee160000 0 0x2000>; 1143 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1144 clocks = <&cpg CPG_MOD 311>; 1145 max-frequency = <200000000>; 1146 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1147 resets = <&cpg 311>; 1148 status = "disabled"; 1149 }; 1150 1151 gic: interrupt-controller@f1010000 { 1152 compatible = "arm,gic-400"; 1153 #interrupt-cells = <3>; 1154 #address-cells = <0>; 1155 interrupt-controller; 1156 reg = <0x0 0xf1010000 0 0x1000>, 1157 <0x0 0xf1020000 0 0x20000>, 1158 <0x0 0xf1040000 0 0x20000>, 1159 <0x0 0xf1060000 0 0x20000>; 1160 interrupts = <GIC_PPI 9 1161 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1162 clocks = <&cpg CPG_MOD 408>; 1163 clock-names = "clk"; 1164 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1165 resets = <&cpg 408>; 1166 }; 1167 1168 pciec0: pcie@fe000000 { 1169 reg = <0 0xfe000000 0 0x80000>; 1170 #address-cells = <3>; 1171 #size-cells = <2>; 1172 bus-range = <0x00 0xff>; 1173 /* placeholder */ 1174 }; 1175 1176 pciec1: pcie@ee800000 { 1177 reg = <0 0xee800000 0 0x80000>; 1178 #address-cells = <3>; 1179 #size-cells = <2>; 1180 bus-range = <0x00 0xff>; 1181 /* placeholder */ 1182 }; 1183 1184 fcpf0: fcp@fe950000 { 1185 compatible = "renesas,fcpf"; 1186 reg = <0 0xfe950000 0 0x200>; 1187 clocks = <&cpg CPG_MOD 615>; 1188 power-domains = <&sysc R8A774B1_PD_A3VP>; 1189 resets = <&cpg 615>; 1190 }; 1191 1192 vspb: vsp@fe960000 { 1193 compatible = "renesas,vsp2"; 1194 reg = <0 0xfe960000 0 0x8000>; 1195 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1196 clocks = <&cpg CPG_MOD 626>; 1197 power-domains = <&sysc R8A774B1_PD_A3VP>; 1198 resets = <&cpg 626>; 1199 1200 renesas,fcp = <&fcpvb0>; 1201 }; 1202 1203 vspi0: vsp@fe9a0000 { 1204 compatible = "renesas,vsp2"; 1205 reg = <0 0xfe9a0000 0 0x8000>; 1206 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1207 clocks = <&cpg CPG_MOD 631>; 1208 power-domains = <&sysc R8A774B1_PD_A3VP>; 1209 resets = <&cpg 631>; 1210 1211 renesas,fcp = <&fcpvi0>; 1212 }; 1213 1214 vspd0: vsp@fea20000 { 1215 compatible = "renesas,vsp2"; 1216 reg = <0 0xfea20000 0 0x5000>; 1217 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1218 clocks = <&cpg CPG_MOD 623>; 1219 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1220 resets = <&cpg 623>; 1221 1222 renesas,fcp = <&fcpvd0>; 1223 }; 1224 1225 vspd1: vsp@fea28000 { 1226 compatible = "renesas,vsp2"; 1227 reg = <0 0xfea28000 0 0x5000>; 1228 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1229 clocks = <&cpg CPG_MOD 622>; 1230 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1231 resets = <&cpg 622>; 1232 1233 renesas,fcp = <&fcpvd1>; 1234 }; 1235 1236 fcpvb0: fcp@fe96f000 { 1237 compatible = "renesas,fcpv"; 1238 reg = <0 0xfe96f000 0 0x200>; 1239 clocks = <&cpg CPG_MOD 607>; 1240 power-domains = <&sysc R8A774B1_PD_A3VP>; 1241 resets = <&cpg 607>; 1242 }; 1243 1244 fcpvd0: fcp@fea27000 { 1245 compatible = "renesas,fcpv"; 1246 reg = <0 0xfea27000 0 0x200>; 1247 clocks = <&cpg CPG_MOD 603>; 1248 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1249 resets = <&cpg 603>; 1250 }; 1251 1252 fcpvd1: fcp@fea2f000 { 1253 compatible = "renesas,fcpv"; 1254 reg = <0 0xfea2f000 0 0x200>; 1255 clocks = <&cpg CPG_MOD 602>; 1256 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1257 resets = <&cpg 602>; 1258 }; 1259 1260 fcpvi0: fcp@fe9af000 { 1261 compatible = "renesas,fcpv"; 1262 reg = <0 0xfe9af000 0 0x200>; 1263 clocks = <&cpg CPG_MOD 611>; 1264 power-domains = <&sysc R8A774B1_PD_A3VP>; 1265 resets = <&cpg 611>; 1266 }; 1267 1268 hdmi0: hdmi@fead0000 { 1269 reg = <0 0xfead0000 0 0x10000>; 1270 1271 ports { 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 1275 port@0 { 1276 reg = <0>; 1277 dw_hdmi0_in: endpoint { 1278 }; 1279 }; 1280 port@1 { 1281 reg = <1>; 1282 }; 1283 }; 1284 }; 1285 1286 du: display@feb00000 { 1287 reg = <0 0xfeb00000 0 0x80000>; 1288 1289 ports { 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 1293 port@0 { 1294 reg = <0>; 1295 du_out_rgb: endpoint { 1296 }; 1297 }; 1298 port@1 { 1299 reg = <1>; 1300 du_out_hdmi0: endpoint { 1301 }; 1302 }; 1303 port@2 { 1304 reg = <2>; 1305 du_out_lvds0: endpoint { 1306 }; 1307 }; 1308 }; 1309 }; 1310 1311 prr: chipid@fff00044 { 1312 compatible = "renesas,prr"; 1313 reg = <0 0xfff00044 0 4>; 1314 }; 1315 }; 1316 1317 thermal-zones { 1318 sensor_thermal1: sensor-thermal1 { 1319 polling-delay-passive = <250>; 1320 polling-delay = <1000>; 1321 thermal-sensors = <&tsc 0>; 1322 sustainable-power = <2439>; 1323 1324 trips { 1325 sensor1_crit: sensor1-crit { 1326 temperature = <120000>; 1327 hysteresis = <1000>; 1328 type = "critical"; 1329 }; 1330 }; 1331 }; 1332 1333 sensor_thermal2: sensor-thermal2 { 1334 polling-delay-passive = <250>; 1335 polling-delay = <1000>; 1336 thermal-sensors = <&tsc 1>; 1337 sustainable-power = <2439>; 1338 1339 trips { 1340 sensor2_crit: sensor2-crit { 1341 temperature = <120000>; 1342 hysteresis = <1000>; 1343 type = "critical"; 1344 }; 1345 }; 1346 }; 1347 1348 sensor_thermal3: sensor-thermal3 { 1349 polling-delay-passive = <250>; 1350 polling-delay = <1000>; 1351 thermal-sensors = <&tsc 2>; 1352 sustainable-power = <2439>; 1353 1354 cooling-maps { 1355 map0 { 1356 trip = <&target>; 1357 cooling-device = <&a57_0 0 2>; 1358 contribution = <1024>; 1359 }; 1360 }; 1361 trips { 1362 target: trip-point1 { 1363 temperature = <100000>; 1364 hysteresis = <1000>; 1365 type = "passive"; 1366 }; 1367 1368 sensor3_crit: sensor3-crit { 1369 temperature = <120000>; 1370 hysteresis = <1000>; 1371 type = "critical"; 1372 }; 1373 }; 1374 }; 1375 }; 1376 1377 timer { 1378 compatible = "arm,armv8-timer"; 1379 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1380 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1381 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1382 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1383 }; 1384 1385 /* External USB clocks - can be overridden by the board */ 1386 usb3s0_clk: usb3s0 { 1387 compatible = "fixed-clock"; 1388 #clock-cells = <0>; 1389 clock-frequency = <0>; 1390 }; 1391 1392 usb_extal_clk: usb_extal { 1393 compatible = "fixed-clock"; 1394 #clock-cells = <0>; 1395 clock-frequency = <0>; 1396 }; 1397}; 1398