1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774b1 SoC 4 * 5 * Copyright (C) 2019 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774b1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774b1-sysc.h> 12 13/ { 14 compatible = "renesas,r8a774b1"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* 19 * The external audio clocks are configured as 0 Hz fixed frequency 20 * clocks by default. 21 * Boards that provide audio clocks should override them. 22 */ 23 audio_clk_a: audio_clk_a { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <0>; 27 }; 28 29 audio_clk_b: audio_clk_b { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 33 }; 34 35 audio_clk_c: audio_clk_c { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <0>; 39 }; 40 41 /* External CAN clock - to be overridden by boards that provide it */ 42 can_clk: can { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <0>; 46 }; 47 48 cluster0_opp: opp_table0 { 49 compatible = "operating-points-v2"; 50 opp-shared; 51 52 opp-500000000 { 53 opp-hz = /bits/ 64 <500000000>; 54 opp-microvolt = <830000>; 55 clock-latency-ns = <300000>; 56 }; 57 opp-1000000000 { 58 opp-hz = /bits/ 64 <1000000000>; 59 opp-microvolt = <830000>; 60 clock-latency-ns = <300000>; 61 }; 62 opp-1500000000 { 63 opp-hz = /bits/ 64 <1500000000>; 64 opp-microvolt = <830000>; 65 clock-latency-ns = <300000>; 66 opp-suspend; 67 }; 68 }; 69 70 cpus { 71 #address-cells = <1>; 72 #size-cells = <0>; 73 74 a57_0: cpu@0 { 75 compatible = "arm,cortex-a57"; 76 reg = <0x0>; 77 device_type = "cpu"; 78 power-domains = <&sysc R8A774B1_PD_CA57_CPU0>; 79 next-level-cache = <&L2_CA57>; 80 enable-method = "psci"; 81 #cooling-cells = <2>; 82 dynamic-power-coefficient = <854>; 83 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; 84 operating-points-v2 = <&cluster0_opp>; 85 }; 86 87 a57_1: cpu@1 { 88 compatible = "arm,cortex-a57"; 89 reg = <0x1>; 90 device_type = "cpu"; 91 power-domains = <&sysc R8A774B1_PD_CA57_CPU1>; 92 next-level-cache = <&L2_CA57>; 93 enable-method = "psci"; 94 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; 95 operating-points-v2 = <&cluster0_opp>; 96 }; 97 98 L2_CA57: cache-controller-0 { 99 compatible = "cache"; 100 power-domains = <&sysc R8A774B1_PD_CA57_SCU>; 101 cache-unified; 102 cache-level = <2>; 103 }; 104 }; 105 106 extal_clk: extal { 107 compatible = "fixed-clock"; 108 #clock-cells = <0>; 109 /* This value must be overridden by the board */ 110 clock-frequency = <0>; 111 }; 112 113 extalr_clk: extalr { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 /* This value must be overridden by the board */ 117 clock-frequency = <0>; 118 }; 119 120 /* External PCIe clock - can be overridden by the board */ 121 pcie_bus_clk: pcie_bus { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <0>; 125 }; 126 127 pmu_a57 { 128 compatible = "arm,cortex-a57-pmu"; 129 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 130 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-affinity = <&a57_0>, <&a57_1>; 132 }; 133 134 psci { 135 compatible = "arm,psci-1.0", "arm,psci-0.2"; 136 method = "smc"; 137 }; 138 139 /* External SCIF clock - to be overridden by boards that provide it */ 140 scif_clk: scif { 141 compatible = "fixed-clock"; 142 #clock-cells = <0>; 143 clock-frequency = <0>; 144 }; 145 146 soc { 147 compatible = "simple-bus"; 148 interrupt-parent = <&gic>; 149 #address-cells = <2>; 150 #size-cells = <2>; 151 ranges; 152 153 rwdt: watchdog@e6020000 { 154 compatible = "renesas,r8a774b1-wdt", 155 "renesas,rcar-gen3-wdt"; 156 reg = <0 0xe6020000 0 0x0c>; 157 clocks = <&cpg CPG_MOD 402>; 158 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 159 resets = <&cpg 402>; 160 status = "disabled"; 161 }; 162 163 gpio0: gpio@e6050000 { 164 compatible = "renesas,gpio-r8a774b1", 165 "renesas,rcar-gen3-gpio"; 166 reg = <0 0xe6050000 0 0x50>; 167 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 168 #gpio-cells = <2>; 169 gpio-controller; 170 gpio-ranges = <&pfc 0 0 16>; 171 #interrupt-cells = <2>; 172 interrupt-controller; 173 clocks = <&cpg CPG_MOD 912>; 174 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 175 resets = <&cpg 912>; 176 }; 177 178 gpio1: gpio@e6051000 { 179 compatible = "renesas,gpio-r8a774b1", 180 "renesas,rcar-gen3-gpio"; 181 reg = <0 0xe6051000 0 0x50>; 182 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 183 #gpio-cells = <2>; 184 gpio-controller; 185 gpio-ranges = <&pfc 0 32 29>; 186 #interrupt-cells = <2>; 187 interrupt-controller; 188 clocks = <&cpg CPG_MOD 911>; 189 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 190 resets = <&cpg 911>; 191 }; 192 193 gpio2: gpio@e6052000 { 194 compatible = "renesas,gpio-r8a774b1", 195 "renesas,rcar-gen3-gpio"; 196 reg = <0 0xe6052000 0 0x50>; 197 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 198 #gpio-cells = <2>; 199 gpio-controller; 200 gpio-ranges = <&pfc 0 64 15>; 201 #interrupt-cells = <2>; 202 interrupt-controller; 203 clocks = <&cpg CPG_MOD 910>; 204 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 205 resets = <&cpg 910>; 206 }; 207 208 gpio3: gpio@e6053000 { 209 compatible = "renesas,gpio-r8a774b1", 210 "renesas,rcar-gen3-gpio"; 211 reg = <0 0xe6053000 0 0x50>; 212 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 213 #gpio-cells = <2>; 214 gpio-controller; 215 gpio-ranges = <&pfc 0 96 16>; 216 #interrupt-cells = <2>; 217 interrupt-controller; 218 clocks = <&cpg CPG_MOD 909>; 219 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 220 resets = <&cpg 909>; 221 }; 222 223 gpio4: gpio@e6054000 { 224 compatible = "renesas,gpio-r8a774b1", 225 "renesas,rcar-gen3-gpio"; 226 reg = <0 0xe6054000 0 0x50>; 227 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 228 #gpio-cells = <2>; 229 gpio-controller; 230 gpio-ranges = <&pfc 0 128 18>; 231 #interrupt-cells = <2>; 232 interrupt-controller; 233 clocks = <&cpg CPG_MOD 908>; 234 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 235 resets = <&cpg 908>; 236 }; 237 238 gpio5: gpio@e6055000 { 239 compatible = "renesas,gpio-r8a774b1", 240 "renesas,rcar-gen3-gpio"; 241 reg = <0 0xe6055000 0 0x50>; 242 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 243 #gpio-cells = <2>; 244 gpio-controller; 245 gpio-ranges = <&pfc 0 160 26>; 246 #interrupt-cells = <2>; 247 interrupt-controller; 248 clocks = <&cpg CPG_MOD 907>; 249 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 250 resets = <&cpg 907>; 251 }; 252 253 gpio6: gpio@e6055400 { 254 compatible = "renesas,gpio-r8a774b1", 255 "renesas,rcar-gen3-gpio"; 256 reg = <0 0xe6055400 0 0x50>; 257 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 258 #gpio-cells = <2>; 259 gpio-controller; 260 gpio-ranges = <&pfc 0 192 32>; 261 #interrupt-cells = <2>; 262 interrupt-controller; 263 clocks = <&cpg CPG_MOD 906>; 264 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 265 resets = <&cpg 906>; 266 }; 267 268 gpio7: gpio@e6055800 { 269 compatible = "renesas,gpio-r8a774b1", 270 "renesas,rcar-gen3-gpio"; 271 reg = <0 0xe6055800 0 0x50>; 272 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 273 #gpio-cells = <2>; 274 gpio-controller; 275 gpio-ranges = <&pfc 0 224 4>; 276 #interrupt-cells = <2>; 277 interrupt-controller; 278 clocks = <&cpg CPG_MOD 905>; 279 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 280 resets = <&cpg 905>; 281 }; 282 283 pfc: pin-controller@e6060000 { 284 compatible = "renesas,pfc-r8a774b1"; 285 reg = <0 0xe6060000 0 0x50c>; 286 }; 287 288 cmt0: timer@e60f0000 { 289 compatible = "renesas,r8a774b1-cmt0", 290 "renesas,rcar-gen3-cmt0"; 291 reg = <0 0xe60f0000 0 0x1004>; 292 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&cpg CPG_MOD 303>; 295 clock-names = "fck"; 296 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 297 resets = <&cpg 303>; 298 status = "disabled"; 299 }; 300 301 cmt1: timer@e6130000 { 302 compatible = "renesas,r8a774b1-cmt1", 303 "renesas,rcar-gen3-cmt1"; 304 reg = <0 0xe6130000 0 0x1004>; 305 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&cpg CPG_MOD 302>; 314 clock-names = "fck"; 315 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 316 resets = <&cpg 302>; 317 status = "disabled"; 318 }; 319 320 cmt2: timer@e6140000 { 321 compatible = "renesas,r8a774b1-cmt1", 322 "renesas,rcar-gen3-cmt1"; 323 reg = <0 0xe6140000 0 0x1004>; 324 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&cpg CPG_MOD 301>; 333 clock-names = "fck"; 334 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 335 resets = <&cpg 301>; 336 status = "disabled"; 337 }; 338 339 cmt3: timer@e6148000 { 340 compatible = "renesas,r8a774b1-cmt1", 341 "renesas,rcar-gen3-cmt1"; 342 reg = <0 0xe6148000 0 0x1004>; 343 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&cpg CPG_MOD 300>; 352 clock-names = "fck"; 353 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 354 resets = <&cpg 300>; 355 status = "disabled"; 356 }; 357 358 cpg: clock-controller@e6150000 { 359 compatible = "renesas,r8a774b1-cpg-mssr"; 360 reg = <0 0xe6150000 0 0x1000>; 361 clocks = <&extal_clk>, <&extalr_clk>; 362 clock-names = "extal", "extalr"; 363 #clock-cells = <2>; 364 #power-domain-cells = <0>; 365 #reset-cells = <1>; 366 }; 367 368 rst: reset-controller@e6160000 { 369 compatible = "renesas,r8a774b1-rst"; 370 reg = <0 0xe6160000 0 0x0200>; 371 }; 372 373 sysc: system-controller@e6180000 { 374 compatible = "renesas,r8a774b1-sysc"; 375 reg = <0 0xe6180000 0 0x0400>; 376 #power-domain-cells = <1>; 377 }; 378 379 tsc: thermal@e6198000 { 380 compatible = "renesas,r8a774b1-thermal"; 381 reg = <0 0xe6198000 0 0x100>, 382 <0 0xe61a0000 0 0x100>, 383 <0 0xe61a8000 0 0x100>; 384 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&cpg CPG_MOD 522>; 388 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 389 resets = <&cpg 522>; 390 #thermal-sensor-cells = <1>; 391 }; 392 393 tmu0: timer@e61e0000 { 394 compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; 395 reg = <0 0xe61e0000 0 0x30>; 396 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&cpg CPG_MOD 125>; 400 clock-names = "fck"; 401 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 402 resets = <&cpg 125>; 403 status = "disabled"; 404 }; 405 406 tmu1: timer@e6fc0000 { 407 compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; 408 reg = <0 0xe6fc0000 0 0x30>; 409 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&cpg CPG_MOD 124>; 413 clock-names = "fck"; 414 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 415 resets = <&cpg 124>; 416 status = "disabled"; 417 }; 418 419 tmu2: timer@e6fd0000 { 420 compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; 421 reg = <0 0xe6fd0000 0 0x30>; 422 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&cpg CPG_MOD 123>; 426 clock-names = "fck"; 427 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 428 resets = <&cpg 123>; 429 status = "disabled"; 430 }; 431 432 tmu3: timer@e6fe0000 { 433 compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; 434 reg = <0 0xe6fe0000 0 0x30>; 435 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&cpg CPG_MOD 122>; 439 clock-names = "fck"; 440 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 441 resets = <&cpg 122>; 442 status = "disabled"; 443 }; 444 445 tmu4: timer@ffc00000 { 446 compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; 447 reg = <0 0xffc00000 0 0x30>; 448 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&cpg CPG_MOD 121>; 452 clock-names = "fck"; 453 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 454 resets = <&cpg 121>; 455 status = "disabled"; 456 }; 457 458 i2c0: i2c@e6500000 { 459 #address-cells = <1>; 460 #size-cells = <0>; 461 compatible = "renesas,i2c-r8a774b1", 462 "renesas,rcar-gen3-i2c"; 463 reg = <0 0xe6500000 0 0x40>; 464 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&cpg CPG_MOD 931>; 466 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 467 resets = <&cpg 931>; 468 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 469 <&dmac2 0x91>, <&dmac2 0x90>; 470 dma-names = "tx", "rx", "tx", "rx"; 471 i2c-scl-internal-delay-ns = <110>; 472 status = "disabled"; 473 }; 474 475 i2c1: i2c@e6508000 { 476 #address-cells = <1>; 477 #size-cells = <0>; 478 compatible = "renesas,i2c-r8a774b1", 479 "renesas,rcar-gen3-i2c"; 480 reg = <0 0xe6508000 0 0x40>; 481 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&cpg CPG_MOD 930>; 483 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 484 resets = <&cpg 930>; 485 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 486 <&dmac2 0x93>, <&dmac2 0x92>; 487 dma-names = "tx", "rx", "tx", "rx"; 488 i2c-scl-internal-delay-ns = <6>; 489 status = "disabled"; 490 }; 491 492 i2c2: i2c@e6510000 { 493 #address-cells = <1>; 494 #size-cells = <0>; 495 compatible = "renesas,i2c-r8a774b1", 496 "renesas,rcar-gen3-i2c"; 497 reg = <0 0xe6510000 0 0x40>; 498 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&cpg CPG_MOD 929>; 500 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 501 resets = <&cpg 929>; 502 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 503 <&dmac2 0x95>, <&dmac2 0x94>; 504 dma-names = "tx", "rx", "tx", "rx"; 505 i2c-scl-internal-delay-ns = <6>; 506 status = "disabled"; 507 }; 508 509 i2c3: i2c@e66d0000 { 510 #address-cells = <1>; 511 #size-cells = <0>; 512 compatible = "renesas,i2c-r8a774b1", 513 "renesas,rcar-gen3-i2c"; 514 reg = <0 0xe66d0000 0 0x40>; 515 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&cpg CPG_MOD 928>; 517 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 518 resets = <&cpg 928>; 519 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 520 dma-names = "tx", "rx"; 521 i2c-scl-internal-delay-ns = <110>; 522 status = "disabled"; 523 }; 524 525 i2c4: i2c@e66d8000 { 526 #address-cells = <1>; 527 #size-cells = <0>; 528 compatible = "renesas,i2c-r8a774b1", 529 "renesas,rcar-gen3-i2c"; 530 reg = <0 0xe66d8000 0 0x40>; 531 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&cpg CPG_MOD 927>; 533 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 534 resets = <&cpg 927>; 535 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 536 dma-names = "tx", "rx"; 537 i2c-scl-internal-delay-ns = <110>; 538 status = "disabled"; 539 }; 540 541 i2c5: i2c@e66e0000 { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 compatible = "renesas,i2c-r8a774b1", 545 "renesas,rcar-gen3-i2c"; 546 reg = <0 0xe66e0000 0 0x40>; 547 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&cpg CPG_MOD 919>; 549 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 550 resets = <&cpg 919>; 551 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 552 dma-names = "tx", "rx"; 553 i2c-scl-internal-delay-ns = <110>; 554 status = "disabled"; 555 }; 556 557 i2c6: i2c@e66e8000 { 558 #address-cells = <1>; 559 #size-cells = <0>; 560 compatible = "renesas,i2c-r8a774b1", 561 "renesas,rcar-gen3-i2c"; 562 reg = <0 0xe66e8000 0 0x40>; 563 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&cpg CPG_MOD 918>; 565 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 566 resets = <&cpg 918>; 567 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 568 dma-names = "tx", "rx"; 569 i2c-scl-internal-delay-ns = <6>; 570 status = "disabled"; 571 }; 572 573 i2c_dvfs: i2c@e60b0000 { 574 #address-cells = <1>; 575 #size-cells = <0>; 576 compatible = "renesas,iic-r8a774b1", 577 "renesas,rcar-gen3-iic", 578 "renesas,rmobile-iic"; 579 reg = <0 0xe60b0000 0 0x425>; 580 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&cpg CPG_MOD 926>; 582 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 583 resets = <&cpg 926>; 584 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 585 dma-names = "tx", "rx"; 586 status = "disabled"; 587 }; 588 589 hscif0: serial@e6540000 { 590 compatible = "renesas,hscif-r8a774b1", 591 "renesas,rcar-gen3-hscif", 592 "renesas,hscif"; 593 reg = <0 0xe6540000 0 0x60>; 594 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&cpg CPG_MOD 520>, 596 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 597 <&scif_clk>; 598 clock-names = "fck", "brg_int", "scif_clk"; 599 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 600 <&dmac2 0x31>, <&dmac2 0x30>; 601 dma-names = "tx", "rx", "tx", "rx"; 602 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 603 resets = <&cpg 520>; 604 status = "disabled"; 605 }; 606 607 hscif1: serial@e6550000 { 608 compatible = "renesas,hscif-r8a774b1", 609 "renesas,rcar-gen3-hscif", 610 "renesas,hscif"; 611 reg = <0 0xe6550000 0 0x60>; 612 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&cpg CPG_MOD 519>, 614 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 615 <&scif_clk>; 616 clock-names = "fck", "brg_int", "scif_clk"; 617 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 618 <&dmac2 0x33>, <&dmac2 0x32>; 619 dma-names = "tx", "rx", "tx", "rx"; 620 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 621 resets = <&cpg 519>; 622 status = "disabled"; 623 }; 624 625 hscif2: serial@e6560000 { 626 compatible = "renesas,hscif-r8a774b1", 627 "renesas,rcar-gen3-hscif", 628 "renesas,hscif"; 629 reg = <0 0xe6560000 0 0x60>; 630 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&cpg CPG_MOD 518>, 632 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 633 <&scif_clk>; 634 clock-names = "fck", "brg_int", "scif_clk"; 635 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 636 <&dmac2 0x35>, <&dmac2 0x34>; 637 dma-names = "tx", "rx", "tx", "rx"; 638 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 639 resets = <&cpg 518>; 640 status = "disabled"; 641 }; 642 643 hscif3: serial@e66a0000 { 644 compatible = "renesas,hscif-r8a774b1", 645 "renesas,rcar-gen3-hscif", 646 "renesas,hscif"; 647 reg = <0 0xe66a0000 0 0x60>; 648 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&cpg CPG_MOD 517>, 650 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 651 <&scif_clk>; 652 clock-names = "fck", "brg_int", "scif_clk"; 653 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 654 dma-names = "tx", "rx"; 655 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 656 resets = <&cpg 517>; 657 status = "disabled"; 658 }; 659 660 hscif4: serial@e66b0000 { 661 compatible = "renesas,hscif-r8a774b1", 662 "renesas,rcar-gen3-hscif", 663 "renesas,hscif"; 664 reg = <0 0xe66b0000 0 0x60>; 665 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&cpg CPG_MOD 516>, 667 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 668 <&scif_clk>; 669 clock-names = "fck", "brg_int", "scif_clk"; 670 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 671 dma-names = "tx", "rx"; 672 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 673 resets = <&cpg 516>; 674 status = "disabled"; 675 }; 676 677 hsusb: usb@e6590000 { 678 compatible = "renesas,usbhs-r8a774b1", 679 "renesas,rcar-gen3-usbhs"; 680 reg = <0 0xe6590000 0 0x200>; 681 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 683 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 684 <&usb_dmac1 0>, <&usb_dmac1 1>; 685 dma-names = "ch0", "ch1", "ch2", "ch3"; 686 renesas,buswait = <11>; 687 phys = <&usb2_phy0 3>; 688 phy-names = "usb"; 689 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 690 resets = <&cpg 704>, <&cpg 703>; 691 status = "disabled"; 692 }; 693 694 usb_dmac0: dma-controller@e65a0000 { 695 compatible = "renesas,r8a774b1-usb-dmac", 696 "renesas,usb-dmac"; 697 reg = <0 0xe65a0000 0 0x100>; 698 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 699 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 700 interrupt-names = "ch0", "ch1"; 701 clocks = <&cpg CPG_MOD 330>; 702 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 703 resets = <&cpg 330>; 704 #dma-cells = <1>; 705 dma-channels = <2>; 706 }; 707 708 usb_dmac1: dma-controller@e65b0000 { 709 compatible = "renesas,r8a774b1-usb-dmac", 710 "renesas,usb-dmac"; 711 reg = <0 0xe65b0000 0 0x100>; 712 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 713 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 714 interrupt-names = "ch0", "ch1"; 715 clocks = <&cpg CPG_MOD 331>; 716 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 717 resets = <&cpg 331>; 718 #dma-cells = <1>; 719 dma-channels = <2>; 720 }; 721 722 usb3_phy0: usb-phy@e65ee000 { 723 reg = <0 0xe65ee000 0 0x90>; 724 #phy-cells = <0>; 725 /* placeholder */ 726 }; 727 728 dmac0: dma-controller@e6700000 { 729 compatible = "renesas,dmac-r8a774b1", 730 "renesas,rcar-dmac"; 731 reg = <0 0xe6700000 0 0x10000>; 732 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 733 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 734 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 735 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 736 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 737 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 738 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 739 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 740 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 741 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 742 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 743 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 744 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 745 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 746 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 747 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 748 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 749 interrupt-names = "error", 750 "ch0", "ch1", "ch2", "ch3", 751 "ch4", "ch5", "ch6", "ch7", 752 "ch8", "ch9", "ch10", "ch11", 753 "ch12", "ch13", "ch14", "ch15"; 754 clocks = <&cpg CPG_MOD 219>; 755 clock-names = "fck"; 756 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 757 resets = <&cpg 219>; 758 #dma-cells = <1>; 759 dma-channels = <16>; 760 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 761 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 762 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 763 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 764 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 765 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 766 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 767 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 768 }; 769 770 dmac1: dma-controller@e7300000 { 771 compatible = "renesas,dmac-r8a774b1", 772 "renesas,rcar-dmac"; 773 reg = <0 0xe7300000 0 0x10000>; 774 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 775 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 776 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 777 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 778 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 779 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 780 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 781 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 782 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 783 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 784 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 785 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 786 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 787 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 788 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 789 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 790 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 791 interrupt-names = "error", 792 "ch0", "ch1", "ch2", "ch3", 793 "ch4", "ch5", "ch6", "ch7", 794 "ch8", "ch9", "ch10", "ch11", 795 "ch12", "ch13", "ch14", "ch15"; 796 clocks = <&cpg CPG_MOD 218>; 797 clock-names = "fck"; 798 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 799 resets = <&cpg 218>; 800 #dma-cells = <1>; 801 dma-channels = <16>; 802 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 803 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 804 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 805 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 806 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 807 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 808 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 809 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 810 }; 811 812 dmac2: dma-controller@e7310000 { 813 compatible = "renesas,dmac-r8a774b1", 814 "renesas,rcar-dmac"; 815 reg = <0 0xe7310000 0 0x10000>; 816 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 817 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 818 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 819 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 820 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 821 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 822 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 823 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 824 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 825 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 826 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 827 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 828 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 829 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 830 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 831 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 832 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 833 interrupt-names = "error", 834 "ch0", "ch1", "ch2", "ch3", 835 "ch4", "ch5", "ch6", "ch7", 836 "ch8", "ch9", "ch10", "ch11", 837 "ch12", "ch13", "ch14", "ch15"; 838 clocks = <&cpg CPG_MOD 217>; 839 clock-names = "fck"; 840 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 841 resets = <&cpg 217>; 842 #dma-cells = <1>; 843 dma-channels = <16>; 844 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 845 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 846 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 847 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 848 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 849 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 850 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 851 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 852 }; 853 854 ipmmu_ds0: mmu@e6740000 { 855 compatible = "renesas,ipmmu-r8a774b1"; 856 reg = <0 0xe6740000 0 0x1000>; 857 renesas,ipmmu-main = <&ipmmu_mm 0>; 858 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 859 #iommu-cells = <1>; 860 }; 861 862 ipmmu_ds1: mmu@e7740000 { 863 compatible = "renesas,ipmmu-r8a774b1"; 864 reg = <0 0xe7740000 0 0x1000>; 865 renesas,ipmmu-main = <&ipmmu_mm 1>; 866 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 867 #iommu-cells = <1>; 868 }; 869 870 ipmmu_hc: mmu@e6570000 { 871 compatible = "renesas,ipmmu-r8a774b1"; 872 reg = <0 0xe6570000 0 0x1000>; 873 renesas,ipmmu-main = <&ipmmu_mm 2>; 874 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 875 #iommu-cells = <1>; 876 }; 877 878 ipmmu_mm: mmu@e67b0000 { 879 compatible = "renesas,ipmmu-r8a774b1"; 880 reg = <0 0xe67b0000 0 0x1000>; 881 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 883 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 884 #iommu-cells = <1>; 885 }; 886 887 ipmmu_mp: mmu@ec670000 { 888 compatible = "renesas,ipmmu-r8a774b1"; 889 reg = <0 0xec670000 0 0x1000>; 890 renesas,ipmmu-main = <&ipmmu_mm 4>; 891 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 892 #iommu-cells = <1>; 893 }; 894 895 ipmmu_pv0: mmu@fd800000 { 896 compatible = "renesas,ipmmu-r8a774b1"; 897 reg = <0 0xfd800000 0 0x1000>; 898 renesas,ipmmu-main = <&ipmmu_mm 6>; 899 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 900 #iommu-cells = <1>; 901 }; 902 903 ipmmu_vc0: mmu@fe6b0000 { 904 compatible = "renesas,ipmmu-r8a774b1"; 905 reg = <0 0xfe6b0000 0 0x1000>; 906 renesas,ipmmu-main = <&ipmmu_mm 12>; 907 power-domains = <&sysc R8A774B1_PD_A3VC>; 908 #iommu-cells = <1>; 909 }; 910 911 ipmmu_vi0: mmu@febd0000 { 912 compatible = "renesas,ipmmu-r8a774b1"; 913 reg = <0 0xfebd0000 0 0x1000>; 914 renesas,ipmmu-main = <&ipmmu_mm 14>; 915 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 916 #iommu-cells = <1>; 917 }; 918 919 ipmmu_vp0: mmu@fe990000 { 920 compatible = "renesas,ipmmu-r8a774b1"; 921 reg = <0 0xfe990000 0 0x1000>; 922 renesas,ipmmu-main = <&ipmmu_mm 16>; 923 power-domains = <&sysc R8A774B1_PD_A3VP>; 924 #iommu-cells = <1>; 925 }; 926 927 avb: ethernet@e6800000 { 928 compatible = "renesas,etheravb-r8a774b1", 929 "renesas,etheravb-rcar-gen3"; 930 reg = <0 0xe6800000 0 0x800>; 931 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 956 interrupt-names = "ch0", "ch1", "ch2", "ch3", 957 "ch4", "ch5", "ch6", "ch7", 958 "ch8", "ch9", "ch10", "ch11", 959 "ch12", "ch13", "ch14", "ch15", 960 "ch16", "ch17", "ch18", "ch19", 961 "ch20", "ch21", "ch22", "ch23", 962 "ch24"; 963 clocks = <&cpg CPG_MOD 812>; 964 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 965 resets = <&cpg 812>; 966 phy-mode = "rgmii"; 967 iommus = <&ipmmu_ds0 16>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 status = "disabled"; 971 }; 972 973 can0: can@e6c30000 { 974 reg = <0 0xe6c30000 0 0x1000>; 975 /* placeholder */ 976 }; 977 978 can1: can@e6c38000 { 979 reg = <0 0xe6c38000 0 0x1000>; 980 /* placeholder */ 981 }; 982 983 canfd: can@e66c0000 { 984 reg = <0 0xe66c0000 0 0x8000>; 985 /* placeholder */ 986 }; 987 988 pwm0: pwm@e6e30000 { 989 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; 990 reg = <0 0xe6e30000 0 0x8>; 991 #pwm-cells = <2>; 992 clocks = <&cpg CPG_MOD 523>; 993 resets = <&cpg 523>; 994 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 995 status = "disabled"; 996 }; 997 998 pwm1: pwm@e6e31000 { 999 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; 1000 reg = <0 0xe6e31000 0 0x8>; 1001 #pwm-cells = <2>; 1002 clocks = <&cpg CPG_MOD 523>; 1003 resets = <&cpg 523>; 1004 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1005 status = "disabled"; 1006 }; 1007 1008 pwm2: pwm@e6e32000 { 1009 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; 1010 reg = <0 0xe6e32000 0 0x8>; 1011 #pwm-cells = <2>; 1012 clocks = <&cpg CPG_MOD 523>; 1013 resets = <&cpg 523>; 1014 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1015 status = "disabled"; 1016 }; 1017 1018 pwm3: pwm@e6e33000 { 1019 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; 1020 reg = <0 0xe6e33000 0 0x8>; 1021 #pwm-cells = <2>; 1022 clocks = <&cpg CPG_MOD 523>; 1023 resets = <&cpg 523>; 1024 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1025 status = "disabled"; 1026 }; 1027 1028 pwm4: pwm@e6e34000 { 1029 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; 1030 reg = <0 0xe6e34000 0 0x8>; 1031 #pwm-cells = <2>; 1032 clocks = <&cpg CPG_MOD 523>; 1033 resets = <&cpg 523>; 1034 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1035 status = "disabled"; 1036 }; 1037 1038 pwm5: pwm@e6e35000 { 1039 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; 1040 reg = <0 0xe6e35000 0 0x8>; 1041 #pwm-cells = <2>; 1042 clocks = <&cpg CPG_MOD 523>; 1043 resets = <&cpg 523>; 1044 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1045 status = "disabled"; 1046 }; 1047 1048 pwm6: pwm@e6e36000 { 1049 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; 1050 reg = <0 0xe6e36000 0 0x8>; 1051 #pwm-cells = <2>; 1052 clocks = <&cpg CPG_MOD 523>; 1053 resets = <&cpg 523>; 1054 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1055 status = "disabled"; 1056 }; 1057 1058 scif0: serial@e6e60000 { 1059 compatible = "renesas,scif-r8a774b1", 1060 "renesas,rcar-gen3-scif", "renesas,scif"; 1061 reg = <0 0xe6e60000 0 0x40>; 1062 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&cpg CPG_MOD 207>, 1064 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 1065 <&scif_clk>; 1066 clock-names = "fck", "brg_int", "scif_clk"; 1067 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1068 <&dmac2 0x51>, <&dmac2 0x50>; 1069 dma-names = "tx", "rx", "tx", "rx"; 1070 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1071 resets = <&cpg 207>; 1072 status = "disabled"; 1073 }; 1074 1075 scif1: serial@e6e68000 { 1076 compatible = "renesas,scif-r8a774b1", 1077 "renesas,rcar-gen3-scif", "renesas,scif"; 1078 reg = <0 0xe6e68000 0 0x40>; 1079 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1080 clocks = <&cpg CPG_MOD 206>, 1081 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 1082 <&scif_clk>; 1083 clock-names = "fck", "brg_int", "scif_clk"; 1084 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1085 <&dmac2 0x53>, <&dmac2 0x52>; 1086 dma-names = "tx", "rx", "tx", "rx"; 1087 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1088 resets = <&cpg 206>; 1089 status = "disabled"; 1090 }; 1091 1092 scif2: serial@e6e88000 { 1093 compatible = "renesas,scif-r8a774b1", 1094 "renesas,rcar-gen3-scif", "renesas,scif"; 1095 reg = <0 0xe6e88000 0 0x40>; 1096 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1097 clocks = <&cpg CPG_MOD 310>, 1098 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 1099 <&scif_clk>; 1100 clock-names = "fck", "brg_int", "scif_clk"; 1101 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1102 <&dmac2 0x13>, <&dmac2 0x12>; 1103 dma-names = "tx", "rx", "tx", "rx"; 1104 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1105 resets = <&cpg 310>; 1106 status = "disabled"; 1107 }; 1108 1109 scif3: serial@e6c50000 { 1110 compatible = "renesas,scif-r8a774b1", 1111 "renesas,rcar-gen3-scif", "renesas,scif"; 1112 reg = <0 0xe6c50000 0 0x40>; 1113 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&cpg CPG_MOD 204>, 1115 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 1116 <&scif_clk>; 1117 clock-names = "fck", "brg_int", "scif_clk"; 1118 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1119 dma-names = "tx", "rx"; 1120 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1121 resets = <&cpg 204>; 1122 status = "disabled"; 1123 }; 1124 1125 scif4: serial@e6c40000 { 1126 compatible = "renesas,scif-r8a774b1", 1127 "renesas,rcar-gen3-scif", "renesas,scif"; 1128 reg = <0 0xe6c40000 0 0x40>; 1129 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&cpg CPG_MOD 203>, 1131 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 1132 <&scif_clk>; 1133 clock-names = "fck", "brg_int", "scif_clk"; 1134 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1135 dma-names = "tx", "rx"; 1136 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1137 resets = <&cpg 203>; 1138 status = "disabled"; 1139 }; 1140 1141 scif5: serial@e6f30000 { 1142 compatible = "renesas,scif-r8a774b1", 1143 "renesas,rcar-gen3-scif", "renesas,scif"; 1144 reg = <0 0xe6f30000 0 0x40>; 1145 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&cpg CPG_MOD 202>, 1147 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 1148 <&scif_clk>; 1149 clock-names = "fck", "brg_int", "scif_clk"; 1150 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1151 <&dmac2 0x5b>, <&dmac2 0x5a>; 1152 dma-names = "tx", "rx", "tx", "rx"; 1153 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1154 resets = <&cpg 202>; 1155 status = "disabled"; 1156 }; 1157 1158 msiof0: spi@e6e90000 { 1159 compatible = "renesas,msiof-r8a774b1", 1160 "renesas,rcar-gen3-msiof"; 1161 reg = <0 0xe6e90000 0 0x0064>; 1162 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1163 clocks = <&cpg CPG_MOD 211>; 1164 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1165 <&dmac2 0x41>, <&dmac2 0x40>; 1166 dma-names = "tx", "rx", "tx", "rx"; 1167 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1168 resets = <&cpg 211>; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 status = "disabled"; 1172 }; 1173 1174 msiof1: spi@e6ea0000 { 1175 compatible = "renesas,msiof-r8a774b1", 1176 "renesas,rcar-gen3-msiof"; 1177 reg = <0 0xe6ea0000 0 0x0064>; 1178 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1179 clocks = <&cpg CPG_MOD 210>; 1180 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1181 <&dmac2 0x43>, <&dmac2 0x42>; 1182 dma-names = "tx", "rx", "tx", "rx"; 1183 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1184 resets = <&cpg 210>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 status = "disabled"; 1188 }; 1189 1190 msiof2: spi@e6c00000 { 1191 compatible = "renesas,msiof-r8a774b1", 1192 "renesas,rcar-gen3-msiof"; 1193 reg = <0 0xe6c00000 0 0x0064>; 1194 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1195 clocks = <&cpg CPG_MOD 209>; 1196 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1197 dma-names = "tx", "rx"; 1198 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1199 resets = <&cpg 209>; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 1205 msiof3: spi@e6c10000 { 1206 compatible = "renesas,msiof-r8a774b1", 1207 "renesas,rcar-gen3-msiof"; 1208 reg = <0 0xe6c10000 0 0x0064>; 1209 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1210 clocks = <&cpg CPG_MOD 208>; 1211 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1212 dma-names = "tx", "rx"; 1213 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1214 resets = <&cpg 208>; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 status = "disabled"; 1218 }; 1219 1220 rcar_sound: sound@ec500000 { 1221 /* 1222 * #sound-dai-cells is required 1223 * 1224 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1225 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1226 */ 1227 /* 1228 * #clock-cells is required for audio_clkout0/1/2/3 1229 * 1230 * clkout : #clock-cells = <0>; <&rcar_sound>; 1231 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1232 */ 1233 compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3"; 1234 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1235 <0 0xec5a0000 0 0x100>, /* ADG */ 1236 <0 0xec540000 0 0x1000>, /* SSIU */ 1237 <0 0xec541000 0 0x280>, /* SSI */ 1238 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1239 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1240 1241 clocks = <&cpg CPG_MOD 1005>, 1242 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1243 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1244 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1245 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1246 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1247 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1248 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1249 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1250 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1251 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1252 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1253 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1254 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1255 <&audio_clk_a>, <&audio_clk_b>, 1256 <&audio_clk_c>, 1257 <&cpg CPG_CORE R8A774B1_CLK_S0D4>; 1258 clock-names = "ssi-all", 1259 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1260 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1261 "ssi.1", "ssi.0", 1262 "src.9", "src.8", "src.7", "src.6", 1263 "src.5", "src.4", "src.3", "src.2", 1264 "src.1", "src.0", 1265 "mix.1", "mix.0", 1266 "ctu.1", "ctu.0", 1267 "dvc.0", "dvc.1", 1268 "clk_a", "clk_b", "clk_c", "clk_i"; 1269 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1270 resets = <&cpg 1005>, 1271 <&cpg 1006>, <&cpg 1007>, 1272 <&cpg 1008>, <&cpg 1009>, 1273 <&cpg 1010>, <&cpg 1011>, 1274 <&cpg 1012>, <&cpg 1013>, 1275 <&cpg 1014>, <&cpg 1015>; 1276 reset-names = "ssi-all", 1277 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1278 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1279 "ssi.1", "ssi.0"; 1280 status = "disabled"; 1281 1282 rcar_sound,ctu { 1283 ctu00: ctu-0 { }; 1284 ctu01: ctu-1 { }; 1285 ctu02: ctu-2 { }; 1286 ctu03: ctu-3 { }; 1287 ctu10: ctu-4 { }; 1288 ctu11: ctu-5 { }; 1289 ctu12: ctu-6 { }; 1290 ctu13: ctu-7 { }; 1291 }; 1292 1293 rcar_sound,dvc { 1294 dvc0: dvc-0 { 1295 dmas = <&audma1 0xbc>; 1296 dma-names = "tx"; 1297 }; 1298 dvc1: dvc-1 { 1299 dmas = <&audma1 0xbe>; 1300 dma-names = "tx"; 1301 }; 1302 }; 1303 1304 rcar_sound,mix { 1305 mix0: mix-0 { }; 1306 mix1: mix-1 { }; 1307 }; 1308 1309 rcar_sound,src { 1310 src0: src-0 { 1311 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1312 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1313 dma-names = "rx", "tx"; 1314 }; 1315 src1: src-1 { 1316 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1317 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1318 dma-names = "rx", "tx"; 1319 }; 1320 src2: src-2 { 1321 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1322 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1323 dma-names = "rx", "tx"; 1324 }; 1325 src3: src-3 { 1326 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1327 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1328 dma-names = "rx", "tx"; 1329 }; 1330 src4: src-4 { 1331 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1332 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1333 dma-names = "rx", "tx"; 1334 }; 1335 src5: src-5 { 1336 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1337 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1338 dma-names = "rx", "tx"; 1339 }; 1340 src6: src-6 { 1341 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1342 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1343 dma-names = "rx", "tx"; 1344 }; 1345 src7: src-7 { 1346 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1347 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1348 dma-names = "rx", "tx"; 1349 }; 1350 src8: src-8 { 1351 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1352 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1353 dma-names = "rx", "tx"; 1354 }; 1355 src9: src-9 { 1356 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1357 dmas = <&audma0 0x97>, <&audma1 0xba>; 1358 dma-names = "rx", "tx"; 1359 }; 1360 }; 1361 1362 rcar_sound,ssi { 1363 ssi0: ssi-0 { 1364 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1365 dmas = <&audma0 0x01>, <&audma1 0x02>; 1366 dma-names = "rx", "tx"; 1367 }; 1368 ssi1: ssi-1 { 1369 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1370 dmas = <&audma0 0x03>, <&audma1 0x04>; 1371 dma-names = "rx", "tx"; 1372 }; 1373 ssi2: ssi-2 { 1374 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1375 dmas = <&audma0 0x05>, <&audma1 0x06>; 1376 dma-names = "rx", "tx"; 1377 }; 1378 ssi3: ssi-3 { 1379 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1380 dmas = <&audma0 0x07>, <&audma1 0x08>; 1381 dma-names = "rx", "tx"; 1382 }; 1383 ssi4: ssi-4 { 1384 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1385 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1386 dma-names = "rx", "tx"; 1387 }; 1388 ssi5: ssi-5 { 1389 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1390 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1391 dma-names = "rx", "tx"; 1392 }; 1393 ssi6: ssi-6 { 1394 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1395 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1396 dma-names = "rx", "tx"; 1397 }; 1398 ssi7: ssi-7 { 1399 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1400 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1401 dma-names = "rx", "tx"; 1402 }; 1403 ssi8: ssi-8 { 1404 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1405 dmas = <&audma0 0x11>, <&audma1 0x12>; 1406 dma-names = "rx", "tx"; 1407 }; 1408 ssi9: ssi-9 { 1409 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1410 dmas = <&audma0 0x13>, <&audma1 0x14>; 1411 dma-names = "rx", "tx"; 1412 }; 1413 }; 1414 1415 rcar_sound,ssiu { 1416 ssiu00: ssiu-0 { 1417 dmas = <&audma0 0x15>, <&audma1 0x16>; 1418 dma-names = "rx", "tx"; 1419 }; 1420 ssiu01: ssiu-1 { 1421 dmas = <&audma0 0x35>, <&audma1 0x36>; 1422 dma-names = "rx", "tx"; 1423 }; 1424 ssiu02: ssiu-2 { 1425 dmas = <&audma0 0x37>, <&audma1 0x38>; 1426 dma-names = "rx", "tx"; 1427 }; 1428 ssiu03: ssiu-3 { 1429 dmas = <&audma0 0x47>, <&audma1 0x48>; 1430 dma-names = "rx", "tx"; 1431 }; 1432 ssiu04: ssiu-4 { 1433 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1434 dma-names = "rx", "tx"; 1435 }; 1436 ssiu05: ssiu-5 { 1437 dmas = <&audma0 0x43>, <&audma1 0x44>; 1438 dma-names = "rx", "tx"; 1439 }; 1440 ssiu06: ssiu-6 { 1441 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1442 dma-names = "rx", "tx"; 1443 }; 1444 ssiu07: ssiu-7 { 1445 dmas = <&audma0 0x53>, <&audma1 0x54>; 1446 dma-names = "rx", "tx"; 1447 }; 1448 ssiu10: ssiu-8 { 1449 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1450 dma-names = "rx", "tx"; 1451 }; 1452 ssiu11: ssiu-9 { 1453 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1454 dma-names = "rx", "tx"; 1455 }; 1456 ssiu12: ssiu-10 { 1457 dmas = <&audma0 0x57>, <&audma1 0x58>; 1458 dma-names = "rx", "tx"; 1459 }; 1460 ssiu13: ssiu-11 { 1461 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1462 dma-names = "rx", "tx"; 1463 }; 1464 ssiu14: ssiu-12 { 1465 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1466 dma-names = "rx", "tx"; 1467 }; 1468 ssiu15: ssiu-13 { 1469 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1470 dma-names = "rx", "tx"; 1471 }; 1472 ssiu16: ssiu-14 { 1473 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1474 dma-names = "rx", "tx"; 1475 }; 1476 ssiu17: ssiu-15 { 1477 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1478 dma-names = "rx", "tx"; 1479 }; 1480 ssiu20: ssiu-16 { 1481 dmas = <&audma0 0x63>, <&audma1 0x64>; 1482 dma-names = "rx", "tx"; 1483 }; 1484 ssiu21: ssiu-17 { 1485 dmas = <&audma0 0x67>, <&audma1 0x68>; 1486 dma-names = "rx", "tx"; 1487 }; 1488 ssiu22: ssiu-18 { 1489 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1490 dma-names = "rx", "tx"; 1491 }; 1492 ssiu23: ssiu-19 { 1493 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1494 dma-names = "rx", "tx"; 1495 }; 1496 ssiu24: ssiu-20 { 1497 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1498 dma-names = "rx", "tx"; 1499 }; 1500 ssiu25: ssiu-21 { 1501 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1502 dma-names = "rx", "tx"; 1503 }; 1504 ssiu26: ssiu-22 { 1505 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1506 dma-names = "rx", "tx"; 1507 }; 1508 ssiu27: ssiu-23 { 1509 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1510 dma-names = "rx", "tx"; 1511 }; 1512 ssiu30: ssiu-24 { 1513 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1514 dma-names = "rx", "tx"; 1515 }; 1516 ssiu31: ssiu-25 { 1517 dmas = <&audma0 0x21>, <&audma1 0x22>; 1518 dma-names = "rx", "tx"; 1519 }; 1520 ssiu32: ssiu-26 { 1521 dmas = <&audma0 0x23>, <&audma1 0x24>; 1522 dma-names = "rx", "tx"; 1523 }; 1524 ssiu33: ssiu-27 { 1525 dmas = <&audma0 0x25>, <&audma1 0x26>; 1526 dma-names = "rx", "tx"; 1527 }; 1528 ssiu34: ssiu-28 { 1529 dmas = <&audma0 0x27>, <&audma1 0x28>; 1530 dma-names = "rx", "tx"; 1531 }; 1532 ssiu35: ssiu-29 { 1533 dmas = <&audma0 0x29>, <&audma1 0x2A>; 1534 dma-names = "rx", "tx"; 1535 }; 1536 ssiu36: ssiu-30 { 1537 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 1538 dma-names = "rx", "tx"; 1539 }; 1540 ssiu37: ssiu-31 { 1541 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 1542 dma-names = "rx", "tx"; 1543 }; 1544 ssiu40: ssiu-32 { 1545 dmas = <&audma0 0x71>, <&audma1 0x72>; 1546 dma-names = "rx", "tx"; 1547 }; 1548 ssiu41: ssiu-33 { 1549 dmas = <&audma0 0x17>, <&audma1 0x18>; 1550 dma-names = "rx", "tx"; 1551 }; 1552 ssiu42: ssiu-34 { 1553 dmas = <&audma0 0x19>, <&audma1 0x1A>; 1554 dma-names = "rx", "tx"; 1555 }; 1556 ssiu43: ssiu-35 { 1557 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 1558 dma-names = "rx", "tx"; 1559 }; 1560 ssiu44: ssiu-36 { 1561 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 1562 dma-names = "rx", "tx"; 1563 }; 1564 ssiu45: ssiu-37 { 1565 dmas = <&audma0 0x1F>, <&audma1 0x20>; 1566 dma-names = "rx", "tx"; 1567 }; 1568 ssiu46: ssiu-38 { 1569 dmas = <&audma0 0x31>, <&audma1 0x32>; 1570 dma-names = "rx", "tx"; 1571 }; 1572 ssiu47: ssiu-39 { 1573 dmas = <&audma0 0x33>, <&audma1 0x34>; 1574 dma-names = "rx", "tx"; 1575 }; 1576 ssiu50: ssiu-40 { 1577 dmas = <&audma0 0x73>, <&audma1 0x74>; 1578 dma-names = "rx", "tx"; 1579 }; 1580 ssiu60: ssiu-41 { 1581 dmas = <&audma0 0x75>, <&audma1 0x76>; 1582 dma-names = "rx", "tx"; 1583 }; 1584 ssiu70: ssiu-42 { 1585 dmas = <&audma0 0x79>, <&audma1 0x7a>; 1586 dma-names = "rx", "tx"; 1587 }; 1588 ssiu80: ssiu-43 { 1589 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 1590 dma-names = "rx", "tx"; 1591 }; 1592 ssiu90: ssiu-44 { 1593 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 1594 dma-names = "rx", "tx"; 1595 }; 1596 ssiu91: ssiu-45 { 1597 dmas = <&audma0 0x7F>, <&audma1 0x80>; 1598 dma-names = "rx", "tx"; 1599 }; 1600 ssiu92: ssiu-46 { 1601 dmas = <&audma0 0x81>, <&audma1 0x82>; 1602 dma-names = "rx", "tx"; 1603 }; 1604 ssiu93: ssiu-47 { 1605 dmas = <&audma0 0x83>, <&audma1 0x84>; 1606 dma-names = "rx", "tx"; 1607 }; 1608 ssiu94: ssiu-48 { 1609 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 1610 dma-names = "rx", "tx"; 1611 }; 1612 ssiu95: ssiu-49 { 1613 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 1614 dma-names = "rx", "tx"; 1615 }; 1616 ssiu96: ssiu-50 { 1617 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 1618 dma-names = "rx", "tx"; 1619 }; 1620 ssiu97: ssiu-51 { 1621 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 1622 dma-names = "rx", "tx"; 1623 }; 1624 }; 1625 }; 1626 1627 audma0: dma-controller@ec700000 { 1628 compatible = "renesas,dmac-r8a774b1", 1629 "renesas,rcar-dmac"; 1630 reg = <0 0xec700000 0 0x10000>; 1631 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 1632 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 1633 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 1634 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 1635 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 1636 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 1637 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 1638 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 1639 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 1640 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 1641 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 1642 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 1643 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 1644 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 1645 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 1646 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 1647 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1648 interrupt-names = "error", 1649 "ch0", "ch1", "ch2", "ch3", 1650 "ch4", "ch5", "ch6", "ch7", 1651 "ch8", "ch9", "ch10", "ch11", 1652 "ch12", "ch13", "ch14", "ch15"; 1653 clocks = <&cpg CPG_MOD 502>; 1654 clock-names = "fck"; 1655 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1656 resets = <&cpg 502>; 1657 #dma-cells = <1>; 1658 dma-channels = <16>; 1659 }; 1660 1661 audma1: dma-controller@ec720000 { 1662 compatible = "renesas,dmac-r8a774b1", 1663 "renesas,rcar-dmac"; 1664 reg = <0 0xec720000 0 0x10000>; 1665 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 1666 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 1667 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 1668 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 1669 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 1670 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 1671 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 1672 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 1673 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 1674 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 1675 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 1676 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 1677 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 1678 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 1679 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH 1680 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 1681 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 1682 interrupt-names = "error", 1683 "ch0", "ch1", "ch2", "ch3", 1684 "ch4", "ch5", "ch6", "ch7", 1685 "ch8", "ch9", "ch10", "ch11", 1686 "ch12", "ch13", "ch14", "ch15"; 1687 clocks = <&cpg CPG_MOD 501>; 1688 clock-names = "fck"; 1689 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1690 resets = <&cpg 501>; 1691 #dma-cells = <1>; 1692 dma-channels = <16>; 1693 }; 1694 1695 xhci0: usb@ee000000 { 1696 reg = <0 0xee000000 0 0xc00>; 1697 /* placeholder */ 1698 }; 1699 1700 usb3_peri0: usb@ee020000 { 1701 reg = <0 0xee020000 0 0x400>; 1702 /* placeholder */ 1703 }; 1704 1705 ohci0: usb@ee080000 { 1706 compatible = "generic-ohci"; 1707 reg = <0 0xee080000 0 0x100>; 1708 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1709 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1710 phys = <&usb2_phy0 1>; 1711 phy-names = "usb"; 1712 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1713 resets = <&cpg 703>, <&cpg 704>; 1714 status = "disabled"; 1715 }; 1716 1717 ohci1: usb@ee0a0000 { 1718 compatible = "generic-ohci"; 1719 reg = <0 0xee0a0000 0 0x100>; 1720 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1721 clocks = <&cpg CPG_MOD 702>; 1722 phys = <&usb2_phy1 1>; 1723 phy-names = "usb"; 1724 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1725 resets = <&cpg 702>; 1726 status = "disabled"; 1727 }; 1728 1729 ehci0: usb@ee080100 { 1730 compatible = "generic-ehci"; 1731 reg = <0 0xee080100 0 0x100>; 1732 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1733 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1734 phys = <&usb2_phy0 2>; 1735 phy-names = "usb"; 1736 companion = <&ohci0>; 1737 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1738 resets = <&cpg 703>, <&cpg 704>; 1739 status = "disabled"; 1740 }; 1741 1742 ehci1: usb@ee0a0100 { 1743 compatible = "generic-ehci"; 1744 reg = <0 0xee0a0100 0 0x100>; 1745 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1746 clocks = <&cpg CPG_MOD 702>; 1747 phys = <&usb2_phy1 2>; 1748 phy-names = "usb"; 1749 companion = <&ohci1>; 1750 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1751 resets = <&cpg 702>; 1752 status = "disabled"; 1753 }; 1754 1755 usb2_phy0: usb-phy@ee080200 { 1756 compatible = "renesas,usb2-phy-r8a774b1", 1757 "renesas,rcar-gen3-usb2-phy"; 1758 reg = <0 0xee080200 0 0x700>; 1759 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1760 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1761 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1762 resets = <&cpg 703>, <&cpg 704>; 1763 #phy-cells = <1>; 1764 status = "disabled"; 1765 }; 1766 1767 usb2_phy1: usb-phy@ee0a0200 { 1768 compatible = "renesas,usb2-phy-r8a774b1", 1769 "renesas,rcar-gen3-usb2-phy"; 1770 reg = <0 0xee0a0200 0 0x700>; 1771 clocks = <&cpg CPG_MOD 702>; 1772 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1773 resets = <&cpg 702>; 1774 #phy-cells = <1>; 1775 status = "disabled"; 1776 }; 1777 1778 sdhi0: sd@ee100000 { 1779 compatible = "renesas,sdhi-r8a774b1", 1780 "renesas,rcar-gen3-sdhi"; 1781 reg = <0 0xee100000 0 0x2000>; 1782 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1783 clocks = <&cpg CPG_MOD 314>; 1784 max-frequency = <200000000>; 1785 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1786 resets = <&cpg 314>; 1787 status = "disabled"; 1788 }; 1789 1790 sdhi1: sd@ee120000 { 1791 compatible = "renesas,sdhi-r8a774b1", 1792 "renesas,rcar-gen3-sdhi"; 1793 reg = <0 0xee120000 0 0x2000>; 1794 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1795 clocks = <&cpg CPG_MOD 313>; 1796 max-frequency = <200000000>; 1797 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1798 resets = <&cpg 313>; 1799 status = "disabled"; 1800 }; 1801 1802 sdhi2: sd@ee140000 { 1803 compatible = "renesas,sdhi-r8a774b1", 1804 "renesas,rcar-gen3-sdhi"; 1805 reg = <0 0xee140000 0 0x2000>; 1806 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1807 clocks = <&cpg CPG_MOD 312>; 1808 max-frequency = <200000000>; 1809 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1810 resets = <&cpg 312>; 1811 status = "disabled"; 1812 }; 1813 1814 sdhi3: sd@ee160000 { 1815 compatible = "renesas,sdhi-r8a774b1", 1816 "renesas,rcar-gen3-sdhi"; 1817 reg = <0 0xee160000 0 0x2000>; 1818 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1819 clocks = <&cpg CPG_MOD 311>; 1820 max-frequency = <200000000>; 1821 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1822 resets = <&cpg 311>; 1823 status = "disabled"; 1824 }; 1825 1826 gic: interrupt-controller@f1010000 { 1827 compatible = "arm,gic-400"; 1828 #interrupt-cells = <3>; 1829 #address-cells = <0>; 1830 interrupt-controller; 1831 reg = <0x0 0xf1010000 0 0x1000>, 1832 <0x0 0xf1020000 0 0x20000>, 1833 <0x0 0xf1040000 0 0x20000>, 1834 <0x0 0xf1060000 0 0x20000>; 1835 interrupts = <GIC_PPI 9 1836 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1837 clocks = <&cpg CPG_MOD 408>; 1838 clock-names = "clk"; 1839 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1840 resets = <&cpg 408>; 1841 }; 1842 1843 pciec0: pcie@fe000000 { 1844 compatible = "renesas,pcie-r8a774b1", 1845 "renesas,pcie-rcar-gen3"; 1846 reg = <0 0xfe000000 0 0x80000>; 1847 #address-cells = <3>; 1848 #size-cells = <2>; 1849 bus-range = <0x00 0xff>; 1850 device_type = "pci"; 1851 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 1852 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 1853 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 1854 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1855 /* Map all possible DDR as inbound ranges */ 1856 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 1857 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1860 #interrupt-cells = <1>; 1861 interrupt-map-mask = <0 0 0 0>; 1862 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1863 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1864 clock-names = "pcie", "pcie_bus"; 1865 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1866 resets = <&cpg 319>; 1867 status = "disabled"; 1868 }; 1869 1870 pciec1: pcie@ee800000 { 1871 compatible = "renesas,pcie-r8a774b1", 1872 "renesas,pcie-rcar-gen3"; 1873 reg = <0 0xee800000 0 0x80000>; 1874 #address-cells = <3>; 1875 #size-cells = <2>; 1876 bus-range = <0x00 0xff>; 1877 device_type = "pci"; 1878 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 1879 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 1880 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 1881 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 1882 /* Map all possible DDR as inbound ranges */ 1883 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 1884 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1887 #interrupt-cells = <1>; 1888 interrupt-map-mask = <0 0 0 0>; 1889 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1890 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 1891 clock-names = "pcie", "pcie_bus"; 1892 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1893 resets = <&cpg 318>; 1894 status = "disabled"; 1895 }; 1896 1897 fdp1@fe940000 { 1898 compatible = "renesas,fdp1"; 1899 reg = <0 0xfe940000 0 0x2400>; 1900 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 1901 clocks = <&cpg CPG_MOD 119>; 1902 power-domains = <&sysc R8A774B1_PD_A3VP>; 1903 resets = <&cpg 119>; 1904 renesas,fcp = <&fcpf0>; 1905 }; 1906 1907 fcpf0: fcp@fe950000 { 1908 compatible = "renesas,fcpf"; 1909 reg = <0 0xfe950000 0 0x200>; 1910 clocks = <&cpg CPG_MOD 615>; 1911 power-domains = <&sysc R8A774B1_PD_A3VP>; 1912 resets = <&cpg 615>; 1913 }; 1914 1915 vspb: vsp@fe960000 { 1916 compatible = "renesas,vsp2"; 1917 reg = <0 0xfe960000 0 0x8000>; 1918 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1919 clocks = <&cpg CPG_MOD 626>; 1920 power-domains = <&sysc R8A774B1_PD_A3VP>; 1921 resets = <&cpg 626>; 1922 1923 renesas,fcp = <&fcpvb0>; 1924 }; 1925 1926 vspi0: vsp@fe9a0000 { 1927 compatible = "renesas,vsp2"; 1928 reg = <0 0xfe9a0000 0 0x8000>; 1929 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1930 clocks = <&cpg CPG_MOD 631>; 1931 power-domains = <&sysc R8A774B1_PD_A3VP>; 1932 resets = <&cpg 631>; 1933 1934 renesas,fcp = <&fcpvi0>; 1935 }; 1936 1937 vspd0: vsp@fea20000 { 1938 compatible = "renesas,vsp2"; 1939 reg = <0 0xfea20000 0 0x5000>; 1940 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1941 clocks = <&cpg CPG_MOD 623>; 1942 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1943 resets = <&cpg 623>; 1944 1945 renesas,fcp = <&fcpvd0>; 1946 }; 1947 1948 vspd1: vsp@fea28000 { 1949 compatible = "renesas,vsp2"; 1950 reg = <0 0xfea28000 0 0x5000>; 1951 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1952 clocks = <&cpg CPG_MOD 622>; 1953 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1954 resets = <&cpg 622>; 1955 1956 renesas,fcp = <&fcpvd1>; 1957 }; 1958 1959 fcpvb0: fcp@fe96f000 { 1960 compatible = "renesas,fcpv"; 1961 reg = <0 0xfe96f000 0 0x200>; 1962 clocks = <&cpg CPG_MOD 607>; 1963 power-domains = <&sysc R8A774B1_PD_A3VP>; 1964 resets = <&cpg 607>; 1965 }; 1966 1967 fcpvd0: fcp@fea27000 { 1968 compatible = "renesas,fcpv"; 1969 reg = <0 0xfea27000 0 0x200>; 1970 clocks = <&cpg CPG_MOD 603>; 1971 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1972 resets = <&cpg 603>; 1973 }; 1974 1975 fcpvd1: fcp@fea2f000 { 1976 compatible = "renesas,fcpv"; 1977 reg = <0 0xfea2f000 0 0x200>; 1978 clocks = <&cpg CPG_MOD 602>; 1979 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1980 resets = <&cpg 602>; 1981 }; 1982 1983 fcpvi0: fcp@fe9af000 { 1984 compatible = "renesas,fcpv"; 1985 reg = <0 0xfe9af000 0 0x200>; 1986 clocks = <&cpg CPG_MOD 611>; 1987 power-domains = <&sysc R8A774B1_PD_A3VP>; 1988 resets = <&cpg 611>; 1989 }; 1990 1991 hdmi0: hdmi@fead0000 { 1992 compatible = "renesas,r8a774b1-hdmi", 1993 "renesas,rcar-gen3-hdmi"; 1994 reg = <0 0xfead0000 0 0x10000>; 1995 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 1996 clocks = <&cpg CPG_MOD 729>, 1997 <&cpg CPG_CORE R8A774B1_CLK_HDMI>; 1998 clock-names = "iahb", "isfr"; 1999 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 2000 resets = <&cpg 729>; 2001 status = "disabled"; 2002 2003 ports { 2004 #address-cells = <1>; 2005 #size-cells = <0>; 2006 2007 port@0 { 2008 reg = <0>; 2009 dw_hdmi0_in: endpoint { 2010 remote-endpoint = <&du_out_hdmi0>; 2011 }; 2012 }; 2013 port@1 { 2014 reg = <1>; 2015 }; 2016 port@2 { 2017 /* HDMI sound */ 2018 reg = <2>; 2019 }; 2020 }; 2021 }; 2022 2023 du: display@feb00000 { 2024 compatible = "renesas,du-r8a774b1"; 2025 reg = <0 0xfeb00000 0 0x80000>; 2026 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2027 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2028 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 2029 clocks = <&cpg CPG_MOD 724>, 2030 <&cpg CPG_MOD 723>, 2031 <&cpg CPG_MOD 721>; 2032 clock-names = "du.0", "du.1", "du.3"; 2033 status = "disabled"; 2034 2035 vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; 2036 2037 ports { 2038 #address-cells = <1>; 2039 #size-cells = <0>; 2040 2041 port@0 { 2042 reg = <0>; 2043 du_out_rgb: endpoint { 2044 }; 2045 }; 2046 port@1 { 2047 reg = <1>; 2048 du_out_hdmi0: endpoint { 2049 remote-endpoint = <&dw_hdmi0_in>; 2050 }; 2051 }; 2052 port@2 { 2053 reg = <2>; 2054 du_out_lvds0: endpoint { 2055 remote-endpoint = <&lvds0_in>; 2056 }; 2057 }; 2058 }; 2059 }; 2060 2061 lvds0: lvds@feb90000 { 2062 compatible = "renesas,r8a774b1-lvds"; 2063 reg = <0 0xfeb90000 0 0x14>; 2064 clocks = <&cpg CPG_MOD 727>; 2065 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 2066 resets = <&cpg 727>; 2067 status = "disabled"; 2068 2069 ports { 2070 #address-cells = <1>; 2071 #size-cells = <0>; 2072 2073 port@0 { 2074 reg = <0>; 2075 lvds0_in: endpoint { 2076 remote-endpoint = <&du_out_lvds0>; 2077 }; 2078 }; 2079 port@1 { 2080 reg = <1>; 2081 lvds0_out: endpoint { 2082 }; 2083 }; 2084 }; 2085 }; 2086 2087 prr: chipid@fff00044 { 2088 compatible = "renesas,prr"; 2089 reg = <0 0xfff00044 0 4>; 2090 }; 2091 }; 2092 2093 thermal-zones { 2094 sensor_thermal1: sensor-thermal1 { 2095 polling-delay-passive = <250>; 2096 polling-delay = <1000>; 2097 thermal-sensors = <&tsc 0>; 2098 sustainable-power = <2439>; 2099 2100 trips { 2101 sensor1_crit: sensor1-crit { 2102 temperature = <120000>; 2103 hysteresis = <1000>; 2104 type = "critical"; 2105 }; 2106 }; 2107 }; 2108 2109 sensor_thermal2: sensor-thermal2 { 2110 polling-delay-passive = <250>; 2111 polling-delay = <1000>; 2112 thermal-sensors = <&tsc 1>; 2113 sustainable-power = <2439>; 2114 2115 trips { 2116 sensor2_crit: sensor2-crit { 2117 temperature = <120000>; 2118 hysteresis = <1000>; 2119 type = "critical"; 2120 }; 2121 }; 2122 }; 2123 2124 sensor_thermal3: sensor-thermal3 { 2125 polling-delay-passive = <250>; 2126 polling-delay = <1000>; 2127 thermal-sensors = <&tsc 2>; 2128 sustainable-power = <2439>; 2129 2130 cooling-maps { 2131 map0 { 2132 trip = <&target>; 2133 cooling-device = <&a57_0 0 2>; 2134 contribution = <1024>; 2135 }; 2136 }; 2137 trips { 2138 target: trip-point1 { 2139 temperature = <100000>; 2140 hysteresis = <1000>; 2141 type = "passive"; 2142 }; 2143 2144 sensor3_crit: sensor3-crit { 2145 temperature = <120000>; 2146 hysteresis = <1000>; 2147 type = "critical"; 2148 }; 2149 }; 2150 }; 2151 }; 2152 2153 timer { 2154 compatible = "arm,armv8-timer"; 2155 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 2156 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 2157 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 2158 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 2159 }; 2160 2161 /* External USB clocks - can be overridden by the board */ 2162 usb3s0_clk: usb3s0 { 2163 compatible = "fixed-clock"; 2164 #clock-cells = <0>; 2165 clock-frequency = <0>; 2166 }; 2167 2168 usb_extal_clk: usb_extal { 2169 compatible = "fixed-clock"; 2170 #clock-cells = <0>; 2171 clock-frequency = <0>; 2172 }; 2173}; 2174