1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774b1 SoC 4 * 5 * Copyright (C) 2019 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774b1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774b1-sysc.h> 12 13/ { 14 compatible = "renesas,r8a774b1"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* 19 * The external audio clocks are configured as 0 Hz fixed frequency 20 * clocks by default. 21 * Boards that provide audio clocks should override them. 22 */ 23 audio_clk_a: audio_clk_a { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <0>; 27 }; 28 29 audio_clk_b: audio_clk_b { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 33 }; 34 35 audio_clk_c: audio_clk_c { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <0>; 39 }; 40 41 /* External CAN clock - to be overridden by boards that provide it */ 42 can_clk: can { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <0>; 46 }; 47 48 cluster0_opp: opp_table0 { 49 compatible = "operating-points-v2"; 50 opp-shared; 51 52 opp-500000000 { 53 opp-hz = /bits/ 64 <500000000>; 54 opp-microvolt = <830000>; 55 clock-latency-ns = <300000>; 56 }; 57 opp-1000000000 { 58 opp-hz = /bits/ 64 <1000000000>; 59 opp-microvolt = <830000>; 60 clock-latency-ns = <300000>; 61 }; 62 opp-1500000000 { 63 opp-hz = /bits/ 64 <1500000000>; 64 opp-microvolt = <830000>; 65 clock-latency-ns = <300000>; 66 opp-suspend; 67 }; 68 }; 69 70 cpus { 71 #address-cells = <1>; 72 #size-cells = <0>; 73 74 a57_0: cpu@0 { 75 compatible = "arm,cortex-a57"; 76 reg = <0x0>; 77 device_type = "cpu"; 78 power-domains = <&sysc R8A774B1_PD_CA57_CPU0>; 79 next-level-cache = <&L2_CA57>; 80 enable-method = "psci"; 81 #cooling-cells = <2>; 82 dynamic-power-coefficient = <854>; 83 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; 84 operating-points-v2 = <&cluster0_opp>; 85 }; 86 87 a57_1: cpu@1 { 88 compatible = "arm,cortex-a57"; 89 reg = <0x1>; 90 device_type = "cpu"; 91 power-domains = <&sysc R8A774B1_PD_CA57_CPU1>; 92 next-level-cache = <&L2_CA57>; 93 enable-method = "psci"; 94 clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; 95 operating-points-v2 = <&cluster0_opp>; 96 }; 97 98 L2_CA57: cache-controller-0 { 99 compatible = "cache"; 100 power-domains = <&sysc R8A774B1_PD_CA57_SCU>; 101 cache-unified; 102 cache-level = <2>; 103 }; 104 }; 105 106 extal_clk: extal { 107 compatible = "fixed-clock"; 108 #clock-cells = <0>; 109 /* This value must be overridden by the board */ 110 clock-frequency = <0>; 111 }; 112 113 extalr_clk: extalr { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 /* This value must be overridden by the board */ 117 clock-frequency = <0>; 118 }; 119 120 /* External PCIe clock - can be overridden by the board */ 121 pcie_bus_clk: pcie_bus { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <0>; 125 }; 126 127 pmu_a57 { 128 compatible = "arm,cortex-a57-pmu"; 129 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 130 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-affinity = <&a57_0>, <&a57_1>; 132 }; 133 134 psci { 135 compatible = "arm,psci-1.0", "arm,psci-0.2"; 136 method = "smc"; 137 }; 138 139 /* External SCIF clock - to be overridden by boards that provide it */ 140 scif_clk: scif { 141 compatible = "fixed-clock"; 142 #clock-cells = <0>; 143 clock-frequency = <0>; 144 }; 145 146 soc { 147 compatible = "simple-bus"; 148 interrupt-parent = <&gic>; 149 #address-cells = <2>; 150 #size-cells = <2>; 151 ranges; 152 153 rwdt: watchdog@e6020000 { 154 compatible = "renesas,r8a774b1-wdt", 155 "renesas,rcar-gen3-wdt"; 156 reg = <0 0xe6020000 0 0x0c>; 157 clocks = <&cpg CPG_MOD 402>; 158 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 159 resets = <&cpg 402>; 160 status = "disabled"; 161 }; 162 163 gpio0: gpio@e6050000 { 164 compatible = "renesas,gpio-r8a774b1", 165 "renesas,rcar-gen3-gpio"; 166 reg = <0 0xe6050000 0 0x50>; 167 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 168 #gpio-cells = <2>; 169 gpio-controller; 170 gpio-ranges = <&pfc 0 0 16>; 171 #interrupt-cells = <2>; 172 interrupt-controller; 173 clocks = <&cpg CPG_MOD 912>; 174 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 175 resets = <&cpg 912>; 176 }; 177 178 gpio1: gpio@e6051000 { 179 compatible = "renesas,gpio-r8a774b1", 180 "renesas,rcar-gen3-gpio"; 181 reg = <0 0xe6051000 0 0x50>; 182 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 183 #gpio-cells = <2>; 184 gpio-controller; 185 gpio-ranges = <&pfc 0 32 29>; 186 #interrupt-cells = <2>; 187 interrupt-controller; 188 clocks = <&cpg CPG_MOD 911>; 189 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 190 resets = <&cpg 911>; 191 }; 192 193 gpio2: gpio@e6052000 { 194 compatible = "renesas,gpio-r8a774b1", 195 "renesas,rcar-gen3-gpio"; 196 reg = <0 0xe6052000 0 0x50>; 197 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 198 #gpio-cells = <2>; 199 gpio-controller; 200 gpio-ranges = <&pfc 0 64 15>; 201 #interrupt-cells = <2>; 202 interrupt-controller; 203 clocks = <&cpg CPG_MOD 910>; 204 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 205 resets = <&cpg 910>; 206 }; 207 208 gpio3: gpio@e6053000 { 209 compatible = "renesas,gpio-r8a774b1", 210 "renesas,rcar-gen3-gpio"; 211 reg = <0 0xe6053000 0 0x50>; 212 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 213 #gpio-cells = <2>; 214 gpio-controller; 215 gpio-ranges = <&pfc 0 96 16>; 216 #interrupt-cells = <2>; 217 interrupt-controller; 218 clocks = <&cpg CPG_MOD 909>; 219 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 220 resets = <&cpg 909>; 221 }; 222 223 gpio4: gpio@e6054000 { 224 compatible = "renesas,gpio-r8a774b1", 225 "renesas,rcar-gen3-gpio"; 226 reg = <0 0xe6054000 0 0x50>; 227 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 228 #gpio-cells = <2>; 229 gpio-controller; 230 gpio-ranges = <&pfc 0 128 18>; 231 #interrupt-cells = <2>; 232 interrupt-controller; 233 clocks = <&cpg CPG_MOD 908>; 234 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 235 resets = <&cpg 908>; 236 }; 237 238 gpio5: gpio@e6055000 { 239 compatible = "renesas,gpio-r8a774b1", 240 "renesas,rcar-gen3-gpio"; 241 reg = <0 0xe6055000 0 0x50>; 242 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 243 #gpio-cells = <2>; 244 gpio-controller; 245 gpio-ranges = <&pfc 0 160 26>; 246 #interrupt-cells = <2>; 247 interrupt-controller; 248 clocks = <&cpg CPG_MOD 907>; 249 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 250 resets = <&cpg 907>; 251 }; 252 253 gpio6: gpio@e6055400 { 254 compatible = "renesas,gpio-r8a774b1", 255 "renesas,rcar-gen3-gpio"; 256 reg = <0 0xe6055400 0 0x50>; 257 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 258 #gpio-cells = <2>; 259 gpio-controller; 260 gpio-ranges = <&pfc 0 192 32>; 261 #interrupt-cells = <2>; 262 interrupt-controller; 263 clocks = <&cpg CPG_MOD 906>; 264 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 265 resets = <&cpg 906>; 266 }; 267 268 gpio7: gpio@e6055800 { 269 compatible = "renesas,gpio-r8a774b1", 270 "renesas,rcar-gen3-gpio"; 271 reg = <0 0xe6055800 0 0x50>; 272 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 273 #gpio-cells = <2>; 274 gpio-controller; 275 gpio-ranges = <&pfc 0 224 4>; 276 #interrupt-cells = <2>; 277 interrupt-controller; 278 clocks = <&cpg CPG_MOD 905>; 279 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 280 resets = <&cpg 905>; 281 }; 282 283 pfc: pin-controller@e6060000 { 284 compatible = "renesas,pfc-r8a774b1"; 285 reg = <0 0xe6060000 0 0x50c>; 286 }; 287 288 cmt0: timer@e60f0000 { 289 compatible = "renesas,r8a774b1-cmt0", 290 "renesas,rcar-gen3-cmt0"; 291 reg = <0 0xe60f0000 0 0x1004>; 292 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&cpg CPG_MOD 303>; 295 clock-names = "fck"; 296 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 297 resets = <&cpg 303>; 298 status = "disabled"; 299 }; 300 301 cmt1: timer@e6130000 { 302 compatible = "renesas,r8a774b1-cmt1", 303 "renesas,rcar-gen3-cmt1"; 304 reg = <0 0xe6130000 0 0x1004>; 305 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&cpg CPG_MOD 302>; 314 clock-names = "fck"; 315 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 316 resets = <&cpg 302>; 317 status = "disabled"; 318 }; 319 320 cmt2: timer@e6140000 { 321 compatible = "renesas,r8a774b1-cmt1", 322 "renesas,rcar-gen3-cmt1"; 323 reg = <0 0xe6140000 0 0x1004>; 324 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&cpg CPG_MOD 301>; 333 clock-names = "fck"; 334 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 335 resets = <&cpg 301>; 336 status = "disabled"; 337 }; 338 339 cmt3: timer@e6148000 { 340 compatible = "renesas,r8a774b1-cmt1", 341 "renesas,rcar-gen3-cmt1"; 342 reg = <0 0xe6148000 0 0x1004>; 343 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&cpg CPG_MOD 300>; 352 clock-names = "fck"; 353 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 354 resets = <&cpg 300>; 355 status = "disabled"; 356 }; 357 358 cpg: clock-controller@e6150000 { 359 compatible = "renesas,r8a774b1-cpg-mssr"; 360 reg = <0 0xe6150000 0 0x1000>; 361 clocks = <&extal_clk>, <&extalr_clk>; 362 clock-names = "extal", "extalr"; 363 #clock-cells = <2>; 364 #power-domain-cells = <0>; 365 #reset-cells = <1>; 366 }; 367 368 rst: reset-controller@e6160000 { 369 compatible = "renesas,r8a774b1-rst"; 370 reg = <0 0xe6160000 0 0x0200>; 371 }; 372 373 sysc: system-controller@e6180000 { 374 compatible = "renesas,r8a774b1-sysc"; 375 reg = <0 0xe6180000 0 0x0400>; 376 #power-domain-cells = <1>; 377 }; 378 379 tsc: thermal@e6198000 { 380 compatible = "renesas,r8a774b1-thermal"; 381 reg = <0 0xe6198000 0 0x100>, 382 <0 0xe61a0000 0 0x100>, 383 <0 0xe61a8000 0 0x100>; 384 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&cpg CPG_MOD 522>; 388 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 389 resets = <&cpg 522>; 390 #thermal-sensor-cells = <1>; 391 }; 392 393 tmu0: timer@e61e0000 { 394 compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; 395 reg = <0 0xe61e0000 0 0x30>; 396 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&cpg CPG_MOD 125>; 400 clock-names = "fck"; 401 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 402 resets = <&cpg 125>; 403 status = "disabled"; 404 }; 405 406 tmu1: timer@e6fc0000 { 407 compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; 408 reg = <0 0xe6fc0000 0 0x30>; 409 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&cpg CPG_MOD 124>; 413 clock-names = "fck"; 414 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 415 resets = <&cpg 124>; 416 status = "disabled"; 417 }; 418 419 tmu2: timer@e6fd0000 { 420 compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; 421 reg = <0 0xe6fd0000 0 0x30>; 422 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&cpg CPG_MOD 123>; 426 clock-names = "fck"; 427 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 428 resets = <&cpg 123>; 429 status = "disabled"; 430 }; 431 432 tmu3: timer@e6fe0000 { 433 compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; 434 reg = <0 0xe6fe0000 0 0x30>; 435 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&cpg CPG_MOD 122>; 439 clock-names = "fck"; 440 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 441 resets = <&cpg 122>; 442 status = "disabled"; 443 }; 444 445 tmu4: timer@ffc00000 { 446 compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; 447 reg = <0 0xffc00000 0 0x30>; 448 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&cpg CPG_MOD 121>; 452 clock-names = "fck"; 453 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 454 resets = <&cpg 121>; 455 status = "disabled"; 456 }; 457 458 i2c0: i2c@e6500000 { 459 #address-cells = <1>; 460 #size-cells = <0>; 461 compatible = "renesas,i2c-r8a774b1", 462 "renesas,rcar-gen3-i2c"; 463 reg = <0 0xe6500000 0 0x40>; 464 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&cpg CPG_MOD 931>; 466 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 467 resets = <&cpg 931>; 468 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 469 <&dmac2 0x91>, <&dmac2 0x90>; 470 dma-names = "tx", "rx", "tx", "rx"; 471 i2c-scl-internal-delay-ns = <110>; 472 status = "disabled"; 473 }; 474 475 i2c1: i2c@e6508000 { 476 #address-cells = <1>; 477 #size-cells = <0>; 478 compatible = "renesas,i2c-r8a774b1", 479 "renesas,rcar-gen3-i2c"; 480 reg = <0 0xe6508000 0 0x40>; 481 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&cpg CPG_MOD 930>; 483 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 484 resets = <&cpg 930>; 485 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 486 <&dmac2 0x93>, <&dmac2 0x92>; 487 dma-names = "tx", "rx", "tx", "rx"; 488 i2c-scl-internal-delay-ns = <6>; 489 status = "disabled"; 490 }; 491 492 i2c2: i2c@e6510000 { 493 #address-cells = <1>; 494 #size-cells = <0>; 495 compatible = "renesas,i2c-r8a774b1", 496 "renesas,rcar-gen3-i2c"; 497 reg = <0 0xe6510000 0 0x40>; 498 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&cpg CPG_MOD 929>; 500 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 501 resets = <&cpg 929>; 502 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 503 <&dmac2 0x95>, <&dmac2 0x94>; 504 dma-names = "tx", "rx", "tx", "rx"; 505 i2c-scl-internal-delay-ns = <6>; 506 status = "disabled"; 507 }; 508 509 i2c3: i2c@e66d0000 { 510 #address-cells = <1>; 511 #size-cells = <0>; 512 compatible = "renesas,i2c-r8a774b1", 513 "renesas,rcar-gen3-i2c"; 514 reg = <0 0xe66d0000 0 0x40>; 515 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&cpg CPG_MOD 928>; 517 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 518 resets = <&cpg 928>; 519 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 520 dma-names = "tx", "rx"; 521 i2c-scl-internal-delay-ns = <110>; 522 status = "disabled"; 523 }; 524 525 i2c4: i2c@e66d8000 { 526 #address-cells = <1>; 527 #size-cells = <0>; 528 compatible = "renesas,i2c-r8a774b1", 529 "renesas,rcar-gen3-i2c"; 530 reg = <0 0xe66d8000 0 0x40>; 531 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&cpg CPG_MOD 927>; 533 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 534 resets = <&cpg 927>; 535 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 536 dma-names = "tx", "rx"; 537 i2c-scl-internal-delay-ns = <110>; 538 status = "disabled"; 539 }; 540 541 i2c5: i2c@e66e0000 { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 compatible = "renesas,i2c-r8a774b1", 545 "renesas,rcar-gen3-i2c"; 546 reg = <0 0xe66e0000 0 0x40>; 547 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&cpg CPG_MOD 919>; 549 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 550 resets = <&cpg 919>; 551 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 552 dma-names = "tx", "rx"; 553 i2c-scl-internal-delay-ns = <110>; 554 status = "disabled"; 555 }; 556 557 i2c6: i2c@e66e8000 { 558 #address-cells = <1>; 559 #size-cells = <0>; 560 compatible = "renesas,i2c-r8a774b1", 561 "renesas,rcar-gen3-i2c"; 562 reg = <0 0xe66e8000 0 0x40>; 563 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&cpg CPG_MOD 918>; 565 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 566 resets = <&cpg 918>; 567 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 568 dma-names = "tx", "rx"; 569 i2c-scl-internal-delay-ns = <6>; 570 status = "disabled"; 571 }; 572 573 i2c_dvfs: i2c@e60b0000 { 574 #address-cells = <1>; 575 #size-cells = <0>; 576 compatible = "renesas,iic-r8a774b1", 577 "renesas,rcar-gen3-iic", 578 "renesas,rmobile-iic"; 579 reg = <0 0xe60b0000 0 0x425>; 580 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&cpg CPG_MOD 926>; 582 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 583 resets = <&cpg 926>; 584 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 585 dma-names = "tx", "rx"; 586 status = "disabled"; 587 }; 588 589 hscif0: serial@e6540000 { 590 compatible = "renesas,hscif-r8a774b1", 591 "renesas,rcar-gen3-hscif", 592 "renesas,hscif"; 593 reg = <0 0xe6540000 0 0x60>; 594 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&cpg CPG_MOD 520>, 596 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 597 <&scif_clk>; 598 clock-names = "fck", "brg_int", "scif_clk"; 599 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 600 <&dmac2 0x31>, <&dmac2 0x30>; 601 dma-names = "tx", "rx", "tx", "rx"; 602 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 603 resets = <&cpg 520>; 604 status = "disabled"; 605 }; 606 607 hscif1: serial@e6550000 { 608 compatible = "renesas,hscif-r8a774b1", 609 "renesas,rcar-gen3-hscif", 610 "renesas,hscif"; 611 reg = <0 0xe6550000 0 0x60>; 612 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&cpg CPG_MOD 519>, 614 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 615 <&scif_clk>; 616 clock-names = "fck", "brg_int", "scif_clk"; 617 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 618 <&dmac2 0x33>, <&dmac2 0x32>; 619 dma-names = "tx", "rx", "tx", "rx"; 620 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 621 resets = <&cpg 519>; 622 status = "disabled"; 623 }; 624 625 hscif2: serial@e6560000 { 626 compatible = "renesas,hscif-r8a774b1", 627 "renesas,rcar-gen3-hscif", 628 "renesas,hscif"; 629 reg = <0 0xe6560000 0 0x60>; 630 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&cpg CPG_MOD 518>, 632 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 633 <&scif_clk>; 634 clock-names = "fck", "brg_int", "scif_clk"; 635 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 636 <&dmac2 0x35>, <&dmac2 0x34>; 637 dma-names = "tx", "rx", "tx", "rx"; 638 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 639 resets = <&cpg 518>; 640 status = "disabled"; 641 }; 642 643 hscif3: serial@e66a0000 { 644 compatible = "renesas,hscif-r8a774b1", 645 "renesas,rcar-gen3-hscif", 646 "renesas,hscif"; 647 reg = <0 0xe66a0000 0 0x60>; 648 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&cpg CPG_MOD 517>, 650 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 651 <&scif_clk>; 652 clock-names = "fck", "brg_int", "scif_clk"; 653 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 654 dma-names = "tx", "rx"; 655 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 656 resets = <&cpg 517>; 657 status = "disabled"; 658 }; 659 660 hscif4: serial@e66b0000 { 661 compatible = "renesas,hscif-r8a774b1", 662 "renesas,rcar-gen3-hscif", 663 "renesas,hscif"; 664 reg = <0 0xe66b0000 0 0x60>; 665 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&cpg CPG_MOD 516>, 667 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 668 <&scif_clk>; 669 clock-names = "fck", "brg_int", "scif_clk"; 670 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 671 dma-names = "tx", "rx"; 672 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 673 resets = <&cpg 516>; 674 status = "disabled"; 675 }; 676 677 hsusb: usb@e6590000 { 678 reg = <0 0xe6590000 0 0x200>; 679 /* placeholder */ 680 }; 681 682 usb3_phy0: usb-phy@e65ee000 { 683 reg = <0 0xe65ee000 0 0x90>; 684 #phy-cells = <0>; 685 /* placeholder */ 686 }; 687 688 dmac0: dma-controller@e6700000 { 689 compatible = "renesas,dmac-r8a774b1", 690 "renesas,rcar-dmac"; 691 reg = <0 0xe6700000 0 0x10000>; 692 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 693 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 694 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 695 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 696 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 697 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 698 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 699 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 700 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 701 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 702 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 703 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 704 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 705 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 706 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 707 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 708 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 709 interrupt-names = "error", 710 "ch0", "ch1", "ch2", "ch3", 711 "ch4", "ch5", "ch6", "ch7", 712 "ch8", "ch9", "ch10", "ch11", 713 "ch12", "ch13", "ch14", "ch15"; 714 clocks = <&cpg CPG_MOD 219>; 715 clock-names = "fck"; 716 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 717 resets = <&cpg 219>; 718 #dma-cells = <1>; 719 dma-channels = <16>; 720 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 721 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 722 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 723 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 724 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 725 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 726 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 727 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 728 }; 729 730 dmac1: dma-controller@e7300000 { 731 compatible = "renesas,dmac-r8a774b1", 732 "renesas,rcar-dmac"; 733 reg = <0 0xe7300000 0 0x10000>; 734 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 735 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 736 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 737 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 738 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 739 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 740 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 741 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 742 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 743 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 744 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 745 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 746 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 747 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 748 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 749 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 750 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 751 interrupt-names = "error", 752 "ch0", "ch1", "ch2", "ch3", 753 "ch4", "ch5", "ch6", "ch7", 754 "ch8", "ch9", "ch10", "ch11", 755 "ch12", "ch13", "ch14", "ch15"; 756 clocks = <&cpg CPG_MOD 218>; 757 clock-names = "fck"; 758 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 759 resets = <&cpg 218>; 760 #dma-cells = <1>; 761 dma-channels = <16>; 762 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 763 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 764 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 765 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 766 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 767 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 768 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 769 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 770 }; 771 772 dmac2: dma-controller@e7310000 { 773 compatible = "renesas,dmac-r8a774b1", 774 "renesas,rcar-dmac"; 775 reg = <0 0xe7310000 0 0x10000>; 776 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 777 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 778 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 779 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 780 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 781 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 782 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 783 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 784 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 785 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 786 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 787 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 788 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 789 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 790 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 791 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 792 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 793 interrupt-names = "error", 794 "ch0", "ch1", "ch2", "ch3", 795 "ch4", "ch5", "ch6", "ch7", 796 "ch8", "ch9", "ch10", "ch11", 797 "ch12", "ch13", "ch14", "ch15"; 798 clocks = <&cpg CPG_MOD 217>; 799 clock-names = "fck"; 800 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 801 resets = <&cpg 217>; 802 #dma-cells = <1>; 803 dma-channels = <16>; 804 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 805 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 806 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 807 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 808 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 809 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 810 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 811 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 812 }; 813 814 ipmmu_ds0: mmu@e6740000 { 815 compatible = "renesas,ipmmu-r8a774b1"; 816 reg = <0 0xe6740000 0 0x1000>; 817 renesas,ipmmu-main = <&ipmmu_mm 0>; 818 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 819 #iommu-cells = <1>; 820 }; 821 822 ipmmu_ds1: mmu@e7740000 { 823 compatible = "renesas,ipmmu-r8a774b1"; 824 reg = <0 0xe7740000 0 0x1000>; 825 renesas,ipmmu-main = <&ipmmu_mm 1>; 826 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 827 #iommu-cells = <1>; 828 }; 829 830 ipmmu_hc: mmu@e6570000 { 831 compatible = "renesas,ipmmu-r8a774b1"; 832 reg = <0 0xe6570000 0 0x1000>; 833 renesas,ipmmu-main = <&ipmmu_mm 2>; 834 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 835 #iommu-cells = <1>; 836 }; 837 838 ipmmu_mm: mmu@e67b0000 { 839 compatible = "renesas,ipmmu-r8a774b1"; 840 reg = <0 0xe67b0000 0 0x1000>; 841 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 843 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 844 #iommu-cells = <1>; 845 }; 846 847 ipmmu_mp: mmu@ec670000 { 848 compatible = "renesas,ipmmu-r8a774b1"; 849 reg = <0 0xec670000 0 0x1000>; 850 renesas,ipmmu-main = <&ipmmu_mm 4>; 851 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 852 #iommu-cells = <1>; 853 }; 854 855 ipmmu_pv0: mmu@fd800000 { 856 compatible = "renesas,ipmmu-r8a774b1"; 857 reg = <0 0xfd800000 0 0x1000>; 858 renesas,ipmmu-main = <&ipmmu_mm 6>; 859 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 860 #iommu-cells = <1>; 861 }; 862 863 ipmmu_vc0: mmu@fe6b0000 { 864 compatible = "renesas,ipmmu-r8a774b1"; 865 reg = <0 0xfe6b0000 0 0x1000>; 866 renesas,ipmmu-main = <&ipmmu_mm 12>; 867 power-domains = <&sysc R8A774B1_PD_A3VC>; 868 #iommu-cells = <1>; 869 }; 870 871 ipmmu_vi0: mmu@febd0000 { 872 compatible = "renesas,ipmmu-r8a774b1"; 873 reg = <0 0xfebd0000 0 0x1000>; 874 renesas,ipmmu-main = <&ipmmu_mm 14>; 875 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 876 #iommu-cells = <1>; 877 }; 878 879 ipmmu_vp0: mmu@fe990000 { 880 compatible = "renesas,ipmmu-r8a774b1"; 881 reg = <0 0xfe990000 0 0x1000>; 882 renesas,ipmmu-main = <&ipmmu_mm 16>; 883 power-domains = <&sysc R8A774B1_PD_A3VP>; 884 #iommu-cells = <1>; 885 }; 886 887 avb: ethernet@e6800000 { 888 compatible = "renesas,etheravb-r8a774b1", 889 "renesas,etheravb-rcar-gen3"; 890 reg = <0 0xe6800000 0 0x800>; 891 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 916 interrupt-names = "ch0", "ch1", "ch2", "ch3", 917 "ch4", "ch5", "ch6", "ch7", 918 "ch8", "ch9", "ch10", "ch11", 919 "ch12", "ch13", "ch14", "ch15", 920 "ch16", "ch17", "ch18", "ch19", 921 "ch20", "ch21", "ch22", "ch23", 922 "ch24"; 923 clocks = <&cpg CPG_MOD 812>; 924 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 925 resets = <&cpg 812>; 926 phy-mode = "rgmii"; 927 iommus = <&ipmmu_ds0 16>; 928 #address-cells = <1>; 929 #size-cells = <0>; 930 status = "disabled"; 931 }; 932 933 can0: can@e6c30000 { 934 reg = <0 0xe6c30000 0 0x1000>; 935 /* placeholder */ 936 }; 937 938 can1: can@e6c38000 { 939 reg = <0 0xe6c38000 0 0x1000>; 940 /* placeholder */ 941 }; 942 943 canfd: can@e66c0000 { 944 reg = <0 0xe66c0000 0 0x8000>; 945 /* placeholder */ 946 }; 947 948 pwm0: pwm@e6e30000 { 949 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; 950 reg = <0 0xe6e30000 0 0x8>; 951 #pwm-cells = <2>; 952 clocks = <&cpg CPG_MOD 523>; 953 resets = <&cpg 523>; 954 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 955 status = "disabled"; 956 }; 957 958 pwm1: pwm@e6e31000 { 959 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; 960 reg = <0 0xe6e31000 0 0x8>; 961 #pwm-cells = <2>; 962 clocks = <&cpg CPG_MOD 523>; 963 resets = <&cpg 523>; 964 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 965 status = "disabled"; 966 }; 967 968 pwm2: pwm@e6e32000 { 969 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; 970 reg = <0 0xe6e32000 0 0x8>; 971 #pwm-cells = <2>; 972 clocks = <&cpg CPG_MOD 523>; 973 resets = <&cpg 523>; 974 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 975 status = "disabled"; 976 }; 977 978 pwm3: pwm@e6e33000 { 979 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; 980 reg = <0 0xe6e33000 0 0x8>; 981 #pwm-cells = <2>; 982 clocks = <&cpg CPG_MOD 523>; 983 resets = <&cpg 523>; 984 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 985 status = "disabled"; 986 }; 987 988 pwm4: pwm@e6e34000 { 989 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; 990 reg = <0 0xe6e34000 0 0x8>; 991 #pwm-cells = <2>; 992 clocks = <&cpg CPG_MOD 523>; 993 resets = <&cpg 523>; 994 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 995 status = "disabled"; 996 }; 997 998 pwm5: pwm@e6e35000 { 999 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; 1000 reg = <0 0xe6e35000 0 0x8>; 1001 #pwm-cells = <2>; 1002 clocks = <&cpg CPG_MOD 523>; 1003 resets = <&cpg 523>; 1004 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1005 status = "disabled"; 1006 }; 1007 1008 pwm6: pwm@e6e36000 { 1009 compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; 1010 reg = <0 0xe6e36000 0 0x8>; 1011 #pwm-cells = <2>; 1012 clocks = <&cpg CPG_MOD 523>; 1013 resets = <&cpg 523>; 1014 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1015 status = "disabled"; 1016 }; 1017 1018 scif0: serial@e6e60000 { 1019 compatible = "renesas,scif-r8a774b1", 1020 "renesas,rcar-gen3-scif", "renesas,scif"; 1021 reg = <0 0xe6e60000 0 0x40>; 1022 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&cpg CPG_MOD 207>, 1024 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 1025 <&scif_clk>; 1026 clock-names = "fck", "brg_int", "scif_clk"; 1027 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1028 <&dmac2 0x51>, <&dmac2 0x50>; 1029 dma-names = "tx", "rx", "tx", "rx"; 1030 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1031 resets = <&cpg 207>; 1032 status = "disabled"; 1033 }; 1034 1035 scif1: serial@e6e68000 { 1036 compatible = "renesas,scif-r8a774b1", 1037 "renesas,rcar-gen3-scif", "renesas,scif"; 1038 reg = <0 0xe6e68000 0 0x40>; 1039 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1040 clocks = <&cpg CPG_MOD 206>, 1041 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 1042 <&scif_clk>; 1043 clock-names = "fck", "brg_int", "scif_clk"; 1044 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1045 <&dmac2 0x53>, <&dmac2 0x52>; 1046 dma-names = "tx", "rx", "tx", "rx"; 1047 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1048 resets = <&cpg 206>; 1049 status = "disabled"; 1050 }; 1051 1052 scif2: serial@e6e88000 { 1053 compatible = "renesas,scif-r8a774b1", 1054 "renesas,rcar-gen3-scif", "renesas,scif"; 1055 reg = <0 0xe6e88000 0 0x40>; 1056 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1057 clocks = <&cpg CPG_MOD 310>, 1058 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 1059 <&scif_clk>; 1060 clock-names = "fck", "brg_int", "scif_clk"; 1061 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1062 <&dmac2 0x13>, <&dmac2 0x12>; 1063 dma-names = "tx", "rx", "tx", "rx"; 1064 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1065 resets = <&cpg 310>; 1066 status = "disabled"; 1067 }; 1068 1069 scif3: serial@e6c50000 { 1070 compatible = "renesas,scif-r8a774b1", 1071 "renesas,rcar-gen3-scif", "renesas,scif"; 1072 reg = <0 0xe6c50000 0 0x40>; 1073 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1074 clocks = <&cpg CPG_MOD 204>, 1075 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 1076 <&scif_clk>; 1077 clock-names = "fck", "brg_int", "scif_clk"; 1078 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1079 dma-names = "tx", "rx"; 1080 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1081 resets = <&cpg 204>; 1082 status = "disabled"; 1083 }; 1084 1085 scif4: serial@e6c40000 { 1086 compatible = "renesas,scif-r8a774b1", 1087 "renesas,rcar-gen3-scif", "renesas,scif"; 1088 reg = <0 0xe6c40000 0 0x40>; 1089 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&cpg CPG_MOD 203>, 1091 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 1092 <&scif_clk>; 1093 clock-names = "fck", "brg_int", "scif_clk"; 1094 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1095 dma-names = "tx", "rx"; 1096 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1097 resets = <&cpg 203>; 1098 status = "disabled"; 1099 }; 1100 1101 scif5: serial@e6f30000 { 1102 compatible = "renesas,scif-r8a774b1", 1103 "renesas,rcar-gen3-scif", "renesas,scif"; 1104 reg = <0 0xe6f30000 0 0x40>; 1105 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1106 clocks = <&cpg CPG_MOD 202>, 1107 <&cpg CPG_CORE R8A774B1_CLK_S3D1>, 1108 <&scif_clk>; 1109 clock-names = "fck", "brg_int", "scif_clk"; 1110 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1111 <&dmac2 0x5b>, <&dmac2 0x5a>; 1112 dma-names = "tx", "rx", "tx", "rx"; 1113 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1114 resets = <&cpg 202>; 1115 status = "disabled"; 1116 }; 1117 1118 msiof0: spi@e6e90000 { 1119 compatible = "renesas,msiof-r8a774b1", 1120 "renesas,rcar-gen3-msiof"; 1121 reg = <0 0xe6e90000 0 0x0064>; 1122 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&cpg CPG_MOD 211>; 1124 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1125 <&dmac2 0x41>, <&dmac2 0x40>; 1126 dma-names = "tx", "rx", "tx", "rx"; 1127 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1128 resets = <&cpg 211>; 1129 #address-cells = <1>; 1130 #size-cells = <0>; 1131 status = "disabled"; 1132 }; 1133 1134 msiof1: spi@e6ea0000 { 1135 compatible = "renesas,msiof-r8a774b1", 1136 "renesas,rcar-gen3-msiof"; 1137 reg = <0 0xe6ea0000 0 0x0064>; 1138 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1139 clocks = <&cpg CPG_MOD 210>; 1140 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1141 <&dmac2 0x43>, <&dmac2 0x42>; 1142 dma-names = "tx", "rx", "tx", "rx"; 1143 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1144 resets = <&cpg 210>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 status = "disabled"; 1148 }; 1149 1150 msiof2: spi@e6c00000 { 1151 compatible = "renesas,msiof-r8a774b1", 1152 "renesas,rcar-gen3-msiof"; 1153 reg = <0 0xe6c00000 0 0x0064>; 1154 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1155 clocks = <&cpg CPG_MOD 209>; 1156 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1157 dma-names = "tx", "rx"; 1158 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1159 resets = <&cpg 209>; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 status = "disabled"; 1163 }; 1164 1165 msiof3: spi@e6c10000 { 1166 compatible = "renesas,msiof-r8a774b1", 1167 "renesas,rcar-gen3-msiof"; 1168 reg = <0 0xe6c10000 0 0x0064>; 1169 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1170 clocks = <&cpg CPG_MOD 208>; 1171 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1172 dma-names = "tx", "rx"; 1173 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1174 resets = <&cpg 208>; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 status = "disabled"; 1178 }; 1179 1180 rcar_sound: sound@ec500000 { 1181 /* 1182 * #sound-dai-cells is required 1183 * 1184 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1185 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1186 */ 1187 /* 1188 * #clock-cells is required for audio_clkout0/1/2/3 1189 * 1190 * clkout : #clock-cells = <0>; <&rcar_sound>; 1191 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1192 */ 1193 compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3"; 1194 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1195 <0 0xec5a0000 0 0x100>, /* ADG */ 1196 <0 0xec540000 0 0x1000>, /* SSIU */ 1197 <0 0xec541000 0 0x280>, /* SSI */ 1198 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1199 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1200 1201 clocks = <&cpg CPG_MOD 1005>, 1202 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1203 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1204 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1205 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1206 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1207 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1208 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1209 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1210 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1211 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1212 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1213 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1214 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1215 <&audio_clk_a>, <&audio_clk_b>, 1216 <&audio_clk_c>, 1217 <&cpg CPG_CORE R8A774B1_CLK_S0D4>; 1218 clock-names = "ssi-all", 1219 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1220 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1221 "ssi.1", "ssi.0", 1222 "src.9", "src.8", "src.7", "src.6", 1223 "src.5", "src.4", "src.3", "src.2", 1224 "src.1", "src.0", 1225 "mix.1", "mix.0", 1226 "ctu.1", "ctu.0", 1227 "dvc.0", "dvc.1", 1228 "clk_a", "clk_b", "clk_c", "clk_i"; 1229 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1230 resets = <&cpg 1005>, 1231 <&cpg 1006>, <&cpg 1007>, 1232 <&cpg 1008>, <&cpg 1009>, 1233 <&cpg 1010>, <&cpg 1011>, 1234 <&cpg 1012>, <&cpg 1013>, 1235 <&cpg 1014>, <&cpg 1015>; 1236 reset-names = "ssi-all", 1237 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1238 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1239 "ssi.1", "ssi.0"; 1240 status = "disabled"; 1241 1242 rcar_sound,ctu { 1243 ctu00: ctu-0 { }; 1244 ctu01: ctu-1 { }; 1245 ctu02: ctu-2 { }; 1246 ctu03: ctu-3 { }; 1247 ctu10: ctu-4 { }; 1248 ctu11: ctu-5 { }; 1249 ctu12: ctu-6 { }; 1250 ctu13: ctu-7 { }; 1251 }; 1252 1253 rcar_sound,dvc { 1254 dvc0: dvc-0 { 1255 dmas = <&audma1 0xbc>; 1256 dma-names = "tx"; 1257 }; 1258 dvc1: dvc-1 { 1259 dmas = <&audma1 0xbe>; 1260 dma-names = "tx"; 1261 }; 1262 }; 1263 1264 rcar_sound,mix { 1265 mix0: mix-0 { }; 1266 mix1: mix-1 { }; 1267 }; 1268 1269 rcar_sound,src { 1270 src0: src-0 { 1271 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1272 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1273 dma-names = "rx", "tx"; 1274 }; 1275 src1: src-1 { 1276 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1277 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1278 dma-names = "rx", "tx"; 1279 }; 1280 src2: src-2 { 1281 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1282 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1283 dma-names = "rx", "tx"; 1284 }; 1285 src3: src-3 { 1286 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1287 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1288 dma-names = "rx", "tx"; 1289 }; 1290 src4: src-4 { 1291 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1292 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1293 dma-names = "rx", "tx"; 1294 }; 1295 src5: src-5 { 1296 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1297 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1298 dma-names = "rx", "tx"; 1299 }; 1300 src6: src-6 { 1301 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1302 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1303 dma-names = "rx", "tx"; 1304 }; 1305 src7: src-7 { 1306 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1307 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1308 dma-names = "rx", "tx"; 1309 }; 1310 src8: src-8 { 1311 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1312 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1313 dma-names = "rx", "tx"; 1314 }; 1315 src9: src-9 { 1316 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1317 dmas = <&audma0 0x97>, <&audma1 0xba>; 1318 dma-names = "rx", "tx"; 1319 }; 1320 }; 1321 1322 rcar_sound,ssi { 1323 ssi0: ssi-0 { 1324 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1325 dmas = <&audma0 0x01>, <&audma1 0x02>; 1326 dma-names = "rx", "tx"; 1327 }; 1328 ssi1: ssi-1 { 1329 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1330 dmas = <&audma0 0x03>, <&audma1 0x04>; 1331 dma-names = "rx", "tx"; 1332 }; 1333 ssi2: ssi-2 { 1334 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1335 dmas = <&audma0 0x05>, <&audma1 0x06>; 1336 dma-names = "rx", "tx"; 1337 }; 1338 ssi3: ssi-3 { 1339 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1340 dmas = <&audma0 0x07>, <&audma1 0x08>; 1341 dma-names = "rx", "tx"; 1342 }; 1343 ssi4: ssi-4 { 1344 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1345 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1346 dma-names = "rx", "tx"; 1347 }; 1348 ssi5: ssi-5 { 1349 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1350 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1351 dma-names = "rx", "tx"; 1352 }; 1353 ssi6: ssi-6 { 1354 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1355 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1356 dma-names = "rx", "tx"; 1357 }; 1358 ssi7: ssi-7 { 1359 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1360 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1361 dma-names = "rx", "tx"; 1362 }; 1363 ssi8: ssi-8 { 1364 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1365 dmas = <&audma0 0x11>, <&audma1 0x12>; 1366 dma-names = "rx", "tx"; 1367 }; 1368 ssi9: ssi-9 { 1369 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1370 dmas = <&audma0 0x13>, <&audma1 0x14>; 1371 dma-names = "rx", "tx"; 1372 }; 1373 }; 1374 1375 rcar_sound,ssiu { 1376 ssiu00: ssiu-0 { 1377 dmas = <&audma0 0x15>, <&audma1 0x16>; 1378 dma-names = "rx", "tx"; 1379 }; 1380 ssiu01: ssiu-1 { 1381 dmas = <&audma0 0x35>, <&audma1 0x36>; 1382 dma-names = "rx", "tx"; 1383 }; 1384 ssiu02: ssiu-2 { 1385 dmas = <&audma0 0x37>, <&audma1 0x38>; 1386 dma-names = "rx", "tx"; 1387 }; 1388 ssiu03: ssiu-3 { 1389 dmas = <&audma0 0x47>, <&audma1 0x48>; 1390 dma-names = "rx", "tx"; 1391 }; 1392 ssiu04: ssiu-4 { 1393 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1394 dma-names = "rx", "tx"; 1395 }; 1396 ssiu05: ssiu-5 { 1397 dmas = <&audma0 0x43>, <&audma1 0x44>; 1398 dma-names = "rx", "tx"; 1399 }; 1400 ssiu06: ssiu-6 { 1401 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1402 dma-names = "rx", "tx"; 1403 }; 1404 ssiu07: ssiu-7 { 1405 dmas = <&audma0 0x53>, <&audma1 0x54>; 1406 dma-names = "rx", "tx"; 1407 }; 1408 ssiu10: ssiu-8 { 1409 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1410 dma-names = "rx", "tx"; 1411 }; 1412 ssiu11: ssiu-9 { 1413 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1414 dma-names = "rx", "tx"; 1415 }; 1416 ssiu12: ssiu-10 { 1417 dmas = <&audma0 0x57>, <&audma1 0x58>; 1418 dma-names = "rx", "tx"; 1419 }; 1420 ssiu13: ssiu-11 { 1421 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1422 dma-names = "rx", "tx"; 1423 }; 1424 ssiu14: ssiu-12 { 1425 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1426 dma-names = "rx", "tx"; 1427 }; 1428 ssiu15: ssiu-13 { 1429 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1430 dma-names = "rx", "tx"; 1431 }; 1432 ssiu16: ssiu-14 { 1433 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1434 dma-names = "rx", "tx"; 1435 }; 1436 ssiu17: ssiu-15 { 1437 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1438 dma-names = "rx", "tx"; 1439 }; 1440 ssiu20: ssiu-16 { 1441 dmas = <&audma0 0x63>, <&audma1 0x64>; 1442 dma-names = "rx", "tx"; 1443 }; 1444 ssiu21: ssiu-17 { 1445 dmas = <&audma0 0x67>, <&audma1 0x68>; 1446 dma-names = "rx", "tx"; 1447 }; 1448 ssiu22: ssiu-18 { 1449 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1450 dma-names = "rx", "tx"; 1451 }; 1452 ssiu23: ssiu-19 { 1453 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1454 dma-names = "rx", "tx"; 1455 }; 1456 ssiu24: ssiu-20 { 1457 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1458 dma-names = "rx", "tx"; 1459 }; 1460 ssiu25: ssiu-21 { 1461 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1462 dma-names = "rx", "tx"; 1463 }; 1464 ssiu26: ssiu-22 { 1465 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1466 dma-names = "rx", "tx"; 1467 }; 1468 ssiu27: ssiu-23 { 1469 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1470 dma-names = "rx", "tx"; 1471 }; 1472 ssiu30: ssiu-24 { 1473 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1474 dma-names = "rx", "tx"; 1475 }; 1476 ssiu31: ssiu-25 { 1477 dmas = <&audma0 0x21>, <&audma1 0x22>; 1478 dma-names = "rx", "tx"; 1479 }; 1480 ssiu32: ssiu-26 { 1481 dmas = <&audma0 0x23>, <&audma1 0x24>; 1482 dma-names = "rx", "tx"; 1483 }; 1484 ssiu33: ssiu-27 { 1485 dmas = <&audma0 0x25>, <&audma1 0x26>; 1486 dma-names = "rx", "tx"; 1487 }; 1488 ssiu34: ssiu-28 { 1489 dmas = <&audma0 0x27>, <&audma1 0x28>; 1490 dma-names = "rx", "tx"; 1491 }; 1492 ssiu35: ssiu-29 { 1493 dmas = <&audma0 0x29>, <&audma1 0x2A>; 1494 dma-names = "rx", "tx"; 1495 }; 1496 ssiu36: ssiu-30 { 1497 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 1498 dma-names = "rx", "tx"; 1499 }; 1500 ssiu37: ssiu-31 { 1501 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 1502 dma-names = "rx", "tx"; 1503 }; 1504 ssiu40: ssiu-32 { 1505 dmas = <&audma0 0x71>, <&audma1 0x72>; 1506 dma-names = "rx", "tx"; 1507 }; 1508 ssiu41: ssiu-33 { 1509 dmas = <&audma0 0x17>, <&audma1 0x18>; 1510 dma-names = "rx", "tx"; 1511 }; 1512 ssiu42: ssiu-34 { 1513 dmas = <&audma0 0x19>, <&audma1 0x1A>; 1514 dma-names = "rx", "tx"; 1515 }; 1516 ssiu43: ssiu-35 { 1517 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 1518 dma-names = "rx", "tx"; 1519 }; 1520 ssiu44: ssiu-36 { 1521 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 1522 dma-names = "rx", "tx"; 1523 }; 1524 ssiu45: ssiu-37 { 1525 dmas = <&audma0 0x1F>, <&audma1 0x20>; 1526 dma-names = "rx", "tx"; 1527 }; 1528 ssiu46: ssiu-38 { 1529 dmas = <&audma0 0x31>, <&audma1 0x32>; 1530 dma-names = "rx", "tx"; 1531 }; 1532 ssiu47: ssiu-39 { 1533 dmas = <&audma0 0x33>, <&audma1 0x34>; 1534 dma-names = "rx", "tx"; 1535 }; 1536 ssiu50: ssiu-40 { 1537 dmas = <&audma0 0x73>, <&audma1 0x74>; 1538 dma-names = "rx", "tx"; 1539 }; 1540 ssiu60: ssiu-41 { 1541 dmas = <&audma0 0x75>, <&audma1 0x76>; 1542 dma-names = "rx", "tx"; 1543 }; 1544 ssiu70: ssiu-42 { 1545 dmas = <&audma0 0x79>, <&audma1 0x7a>; 1546 dma-names = "rx", "tx"; 1547 }; 1548 ssiu80: ssiu-43 { 1549 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 1550 dma-names = "rx", "tx"; 1551 }; 1552 ssiu90: ssiu-44 { 1553 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 1554 dma-names = "rx", "tx"; 1555 }; 1556 ssiu91: ssiu-45 { 1557 dmas = <&audma0 0x7F>, <&audma1 0x80>; 1558 dma-names = "rx", "tx"; 1559 }; 1560 ssiu92: ssiu-46 { 1561 dmas = <&audma0 0x81>, <&audma1 0x82>; 1562 dma-names = "rx", "tx"; 1563 }; 1564 ssiu93: ssiu-47 { 1565 dmas = <&audma0 0x83>, <&audma1 0x84>; 1566 dma-names = "rx", "tx"; 1567 }; 1568 ssiu94: ssiu-48 { 1569 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 1570 dma-names = "rx", "tx"; 1571 }; 1572 ssiu95: ssiu-49 { 1573 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 1574 dma-names = "rx", "tx"; 1575 }; 1576 ssiu96: ssiu-50 { 1577 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 1578 dma-names = "rx", "tx"; 1579 }; 1580 ssiu97: ssiu-51 { 1581 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 1582 dma-names = "rx", "tx"; 1583 }; 1584 }; 1585 }; 1586 1587 audma0: dma-controller@ec700000 { 1588 compatible = "renesas,dmac-r8a774b1", 1589 "renesas,rcar-dmac"; 1590 reg = <0 0xec700000 0 0x10000>; 1591 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 1592 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 1593 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 1594 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 1595 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 1596 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 1597 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 1598 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 1599 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 1600 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 1601 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 1602 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 1603 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 1604 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 1605 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 1606 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 1607 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1608 interrupt-names = "error", 1609 "ch0", "ch1", "ch2", "ch3", 1610 "ch4", "ch5", "ch6", "ch7", 1611 "ch8", "ch9", "ch10", "ch11", 1612 "ch12", "ch13", "ch14", "ch15"; 1613 clocks = <&cpg CPG_MOD 502>; 1614 clock-names = "fck"; 1615 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1616 resets = <&cpg 502>; 1617 #dma-cells = <1>; 1618 dma-channels = <16>; 1619 }; 1620 1621 audma1: dma-controller@ec720000 { 1622 compatible = "renesas,dmac-r8a774b1", 1623 "renesas,rcar-dmac"; 1624 reg = <0 0xec720000 0 0x10000>; 1625 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 1626 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 1627 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 1628 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 1629 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 1630 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 1631 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 1632 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 1633 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 1634 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 1635 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 1636 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 1637 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 1638 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 1639 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH 1640 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 1641 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 1642 interrupt-names = "error", 1643 "ch0", "ch1", "ch2", "ch3", 1644 "ch4", "ch5", "ch6", "ch7", 1645 "ch8", "ch9", "ch10", "ch11", 1646 "ch12", "ch13", "ch14", "ch15"; 1647 clocks = <&cpg CPG_MOD 501>; 1648 clock-names = "fck"; 1649 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1650 resets = <&cpg 501>; 1651 #dma-cells = <1>; 1652 dma-channels = <16>; 1653 }; 1654 1655 xhci0: usb@ee000000 { 1656 reg = <0 0xee000000 0 0xc00>; 1657 /* placeholder */ 1658 }; 1659 1660 usb3_peri0: usb@ee020000 { 1661 reg = <0 0xee020000 0 0x400>; 1662 /* placeholder */ 1663 }; 1664 1665 ohci0: usb@ee080000 { 1666 reg = <0 0xee080000 0 0x100>; 1667 /* placeholder */ 1668 }; 1669 1670 ohci1: usb@ee0a0000 { 1671 reg = <0 0xee0a0000 0 0x100>; 1672 /* placeholder */ 1673 }; 1674 1675 ehci0: usb@ee080100 { 1676 reg = <0 0xee080100 0 0x100>; 1677 /* placeholder */ 1678 }; 1679 1680 ehci1: usb@ee0a0100 { 1681 reg = <0 0xee0a0100 0 0x100>; 1682 /* placeholder */ 1683 }; 1684 1685 usb2_phy0: usb-phy@ee080200 { 1686 reg = <0 0xee080200 0 0x700>; 1687 /* placeholder */ 1688 }; 1689 1690 usb2_phy1: usb-phy@ee0a0200 { 1691 reg = <0 0xee0a0200 0 0x700>; 1692 /* placeholder */ 1693 }; 1694 1695 sdhi0: sd@ee100000 { 1696 compatible = "renesas,sdhi-r8a774b1", 1697 "renesas,rcar-gen3-sdhi"; 1698 reg = <0 0xee100000 0 0x2000>; 1699 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1700 clocks = <&cpg CPG_MOD 314>; 1701 max-frequency = <200000000>; 1702 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1703 resets = <&cpg 314>; 1704 status = "disabled"; 1705 }; 1706 1707 sdhi1: sd@ee120000 { 1708 compatible = "renesas,sdhi-r8a774b1", 1709 "renesas,rcar-gen3-sdhi"; 1710 reg = <0 0xee120000 0 0x2000>; 1711 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1712 clocks = <&cpg CPG_MOD 313>; 1713 max-frequency = <200000000>; 1714 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1715 resets = <&cpg 313>; 1716 status = "disabled"; 1717 }; 1718 1719 sdhi2: sd@ee140000 { 1720 compatible = "renesas,sdhi-r8a774b1", 1721 "renesas,rcar-gen3-sdhi"; 1722 reg = <0 0xee140000 0 0x2000>; 1723 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1724 clocks = <&cpg CPG_MOD 312>; 1725 max-frequency = <200000000>; 1726 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1727 resets = <&cpg 312>; 1728 status = "disabled"; 1729 }; 1730 1731 sdhi3: sd@ee160000 { 1732 compatible = "renesas,sdhi-r8a774b1", 1733 "renesas,rcar-gen3-sdhi"; 1734 reg = <0 0xee160000 0 0x2000>; 1735 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1736 clocks = <&cpg CPG_MOD 311>; 1737 max-frequency = <200000000>; 1738 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1739 resets = <&cpg 311>; 1740 status = "disabled"; 1741 }; 1742 1743 gic: interrupt-controller@f1010000 { 1744 compatible = "arm,gic-400"; 1745 #interrupt-cells = <3>; 1746 #address-cells = <0>; 1747 interrupt-controller; 1748 reg = <0x0 0xf1010000 0 0x1000>, 1749 <0x0 0xf1020000 0 0x20000>, 1750 <0x0 0xf1040000 0 0x20000>, 1751 <0x0 0xf1060000 0 0x20000>; 1752 interrupts = <GIC_PPI 9 1753 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1754 clocks = <&cpg CPG_MOD 408>; 1755 clock-names = "clk"; 1756 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1757 resets = <&cpg 408>; 1758 }; 1759 1760 pciec0: pcie@fe000000 { 1761 compatible = "renesas,pcie-r8a774b1", 1762 "renesas,pcie-rcar-gen3"; 1763 reg = <0 0xfe000000 0 0x80000>; 1764 #address-cells = <3>; 1765 #size-cells = <2>; 1766 bus-range = <0x00 0xff>; 1767 device_type = "pci"; 1768 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 1769 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 1770 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 1771 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1772 /* Map all possible DDR as inbound ranges */ 1773 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 1774 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1777 #interrupt-cells = <1>; 1778 interrupt-map-mask = <0 0 0 0>; 1779 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1780 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1781 clock-names = "pcie", "pcie_bus"; 1782 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1783 resets = <&cpg 319>; 1784 status = "disabled"; 1785 }; 1786 1787 pciec1: pcie@ee800000 { 1788 compatible = "renesas,pcie-r8a774b1", 1789 "renesas,pcie-rcar-gen3"; 1790 reg = <0 0xee800000 0 0x80000>; 1791 #address-cells = <3>; 1792 #size-cells = <2>; 1793 bus-range = <0x00 0xff>; 1794 device_type = "pci"; 1795 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 1796 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 1797 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 1798 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 1799 /* Map all possible DDR as inbound ranges */ 1800 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 1801 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1804 #interrupt-cells = <1>; 1805 interrupt-map-mask = <0 0 0 0>; 1806 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1807 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 1808 clock-names = "pcie", "pcie_bus"; 1809 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1810 resets = <&cpg 318>; 1811 status = "disabled"; 1812 }; 1813 1814 fdp1@fe940000 { 1815 compatible = "renesas,fdp1"; 1816 reg = <0 0xfe940000 0 0x2400>; 1817 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 1818 clocks = <&cpg CPG_MOD 119>; 1819 power-domains = <&sysc R8A774B1_PD_A3VP>; 1820 resets = <&cpg 119>; 1821 renesas,fcp = <&fcpf0>; 1822 }; 1823 1824 fcpf0: fcp@fe950000 { 1825 compatible = "renesas,fcpf"; 1826 reg = <0 0xfe950000 0 0x200>; 1827 clocks = <&cpg CPG_MOD 615>; 1828 power-domains = <&sysc R8A774B1_PD_A3VP>; 1829 resets = <&cpg 615>; 1830 }; 1831 1832 vspb: vsp@fe960000 { 1833 compatible = "renesas,vsp2"; 1834 reg = <0 0xfe960000 0 0x8000>; 1835 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1836 clocks = <&cpg CPG_MOD 626>; 1837 power-domains = <&sysc R8A774B1_PD_A3VP>; 1838 resets = <&cpg 626>; 1839 1840 renesas,fcp = <&fcpvb0>; 1841 }; 1842 1843 vspi0: vsp@fe9a0000 { 1844 compatible = "renesas,vsp2"; 1845 reg = <0 0xfe9a0000 0 0x8000>; 1846 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1847 clocks = <&cpg CPG_MOD 631>; 1848 power-domains = <&sysc R8A774B1_PD_A3VP>; 1849 resets = <&cpg 631>; 1850 1851 renesas,fcp = <&fcpvi0>; 1852 }; 1853 1854 vspd0: vsp@fea20000 { 1855 compatible = "renesas,vsp2"; 1856 reg = <0 0xfea20000 0 0x5000>; 1857 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1858 clocks = <&cpg CPG_MOD 623>; 1859 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1860 resets = <&cpg 623>; 1861 1862 renesas,fcp = <&fcpvd0>; 1863 }; 1864 1865 vspd1: vsp@fea28000 { 1866 compatible = "renesas,vsp2"; 1867 reg = <0 0xfea28000 0 0x5000>; 1868 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1869 clocks = <&cpg CPG_MOD 622>; 1870 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1871 resets = <&cpg 622>; 1872 1873 renesas,fcp = <&fcpvd1>; 1874 }; 1875 1876 fcpvb0: fcp@fe96f000 { 1877 compatible = "renesas,fcpv"; 1878 reg = <0 0xfe96f000 0 0x200>; 1879 clocks = <&cpg CPG_MOD 607>; 1880 power-domains = <&sysc R8A774B1_PD_A3VP>; 1881 resets = <&cpg 607>; 1882 }; 1883 1884 fcpvd0: fcp@fea27000 { 1885 compatible = "renesas,fcpv"; 1886 reg = <0 0xfea27000 0 0x200>; 1887 clocks = <&cpg CPG_MOD 603>; 1888 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1889 resets = <&cpg 603>; 1890 }; 1891 1892 fcpvd1: fcp@fea2f000 { 1893 compatible = "renesas,fcpv"; 1894 reg = <0 0xfea2f000 0 0x200>; 1895 clocks = <&cpg CPG_MOD 602>; 1896 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1897 resets = <&cpg 602>; 1898 }; 1899 1900 fcpvi0: fcp@fe9af000 { 1901 compatible = "renesas,fcpv"; 1902 reg = <0 0xfe9af000 0 0x200>; 1903 clocks = <&cpg CPG_MOD 611>; 1904 power-domains = <&sysc R8A774B1_PD_A3VP>; 1905 resets = <&cpg 611>; 1906 }; 1907 1908 hdmi0: hdmi@fead0000 { 1909 compatible = "renesas,r8a774b1-hdmi", 1910 "renesas,rcar-gen3-hdmi"; 1911 reg = <0 0xfead0000 0 0x10000>; 1912 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 1913 clocks = <&cpg CPG_MOD 729>, 1914 <&cpg CPG_CORE R8A774B1_CLK_HDMI>; 1915 clock-names = "iahb", "isfr"; 1916 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1917 resets = <&cpg 729>; 1918 status = "disabled"; 1919 1920 ports { 1921 #address-cells = <1>; 1922 #size-cells = <0>; 1923 1924 port@0 { 1925 reg = <0>; 1926 dw_hdmi0_in: endpoint { 1927 remote-endpoint = <&du_out_hdmi0>; 1928 }; 1929 }; 1930 port@1 { 1931 reg = <1>; 1932 }; 1933 port@2 { 1934 /* HDMI sound */ 1935 reg = <2>; 1936 }; 1937 }; 1938 }; 1939 1940 du: display@feb00000 { 1941 compatible = "renesas,du-r8a774b1"; 1942 reg = <0 0xfeb00000 0 0x80000>; 1943 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 1946 clocks = <&cpg CPG_MOD 724>, 1947 <&cpg CPG_MOD 723>, 1948 <&cpg CPG_MOD 721>; 1949 clock-names = "du.0", "du.1", "du.3"; 1950 status = "disabled"; 1951 1952 vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; 1953 1954 ports { 1955 #address-cells = <1>; 1956 #size-cells = <0>; 1957 1958 port@0 { 1959 reg = <0>; 1960 du_out_rgb: endpoint { 1961 }; 1962 }; 1963 port@1 { 1964 reg = <1>; 1965 du_out_hdmi0: endpoint { 1966 remote-endpoint = <&dw_hdmi0_in>; 1967 }; 1968 }; 1969 port@2 { 1970 reg = <2>; 1971 du_out_lvds0: endpoint { 1972 remote-endpoint = <&lvds0_in>; 1973 }; 1974 }; 1975 }; 1976 }; 1977 1978 lvds0: lvds@feb90000 { 1979 compatible = "renesas,r8a774b1-lvds"; 1980 reg = <0 0xfeb90000 0 0x14>; 1981 clocks = <&cpg CPG_MOD 727>; 1982 power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; 1983 resets = <&cpg 727>; 1984 status = "disabled"; 1985 1986 ports { 1987 #address-cells = <1>; 1988 #size-cells = <0>; 1989 1990 port@0 { 1991 reg = <0>; 1992 lvds0_in: endpoint { 1993 remote-endpoint = <&du_out_lvds0>; 1994 }; 1995 }; 1996 port@1 { 1997 reg = <1>; 1998 lvds0_out: endpoint { 1999 }; 2000 }; 2001 }; 2002 }; 2003 2004 prr: chipid@fff00044 { 2005 compatible = "renesas,prr"; 2006 reg = <0 0xfff00044 0 4>; 2007 }; 2008 }; 2009 2010 thermal-zones { 2011 sensor_thermal1: sensor-thermal1 { 2012 polling-delay-passive = <250>; 2013 polling-delay = <1000>; 2014 thermal-sensors = <&tsc 0>; 2015 sustainable-power = <2439>; 2016 2017 trips { 2018 sensor1_crit: sensor1-crit { 2019 temperature = <120000>; 2020 hysteresis = <1000>; 2021 type = "critical"; 2022 }; 2023 }; 2024 }; 2025 2026 sensor_thermal2: sensor-thermal2 { 2027 polling-delay-passive = <250>; 2028 polling-delay = <1000>; 2029 thermal-sensors = <&tsc 1>; 2030 sustainable-power = <2439>; 2031 2032 trips { 2033 sensor2_crit: sensor2-crit { 2034 temperature = <120000>; 2035 hysteresis = <1000>; 2036 type = "critical"; 2037 }; 2038 }; 2039 }; 2040 2041 sensor_thermal3: sensor-thermal3 { 2042 polling-delay-passive = <250>; 2043 polling-delay = <1000>; 2044 thermal-sensors = <&tsc 2>; 2045 sustainable-power = <2439>; 2046 2047 cooling-maps { 2048 map0 { 2049 trip = <&target>; 2050 cooling-device = <&a57_0 0 2>; 2051 contribution = <1024>; 2052 }; 2053 }; 2054 trips { 2055 target: trip-point1 { 2056 temperature = <100000>; 2057 hysteresis = <1000>; 2058 type = "passive"; 2059 }; 2060 2061 sensor3_crit: sensor3-crit { 2062 temperature = <120000>; 2063 hysteresis = <1000>; 2064 type = "critical"; 2065 }; 2066 }; 2067 }; 2068 }; 2069 2070 timer { 2071 compatible = "arm,armv8-timer"; 2072 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 2073 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 2074 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 2075 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 2076 }; 2077 2078 /* External USB clocks - can be overridden by the board */ 2079 usb3s0_clk: usb3s0 { 2080 compatible = "fixed-clock"; 2081 #clock-cells = <0>; 2082 clock-frequency = <0>; 2083 }; 2084 2085 usb_extal_clk: usb_extal { 2086 compatible = "fixed-clock"; 2087 #clock-cells = <0>; 2088 clock-frequency = <0>; 2089 }; 2090}; 2091