1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774a1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774a1-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a774a1"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &i2c0; 22 i2c1 = &i2c1; 23 i2c2 = &i2c2; 24 i2c3 = &i2c3; 25 i2c4 = &i2c4; 26 i2c5 = &i2c5; 27 i2c6 = &i2c6; 28 i2c7 = &iic_pmic; 29 }; 30 31 /* 32 * The external audio clocks are configured as 0 Hz fixed frequency 33 * clocks by default. 34 * Boards that provide audio clocks should override them. 35 */ 36 audio_clk_a: audio_clk_a { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 audio_clk_b: audio_clk_b { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <0>; 46 }; 47 48 audio_clk_c: audio_clk_c { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <0>; 52 }; 53 54 /* External CAN clock - to be overridden by boards that provide it */ 55 can_clk: can { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 59 }; 60 61 cluster0_opp: opp-table-0 { 62 compatible = "operating-points-v2"; 63 opp-shared; 64 65 opp-500000000 { 66 opp-hz = /bits/ 64 <500000000>; 67 opp-microvolt = <820000>; 68 clock-latency-ns = <300000>; 69 }; 70 opp-1000000000 { 71 opp-hz = /bits/ 64 <1000000000>; 72 opp-microvolt = <820000>; 73 clock-latency-ns = <300000>; 74 }; 75 opp-1500000000 { 76 opp-hz = /bits/ 64 <1500000000>; 77 opp-microvolt = <820000>; 78 clock-latency-ns = <300000>; 79 opp-suspend; 80 }; 81 }; 82 83 cluster1_opp: opp-table-1 { 84 compatible = "operating-points-v2"; 85 opp-shared; 86 87 opp-800000000 { 88 opp-hz = /bits/ 64 <800000000>; 89 opp-microvolt = <820000>; 90 clock-latency-ns = <300000>; 91 }; 92 opp-1000000000 { 93 opp-hz = /bits/ 64 <1000000000>; 94 opp-microvolt = <820000>; 95 clock-latency-ns = <300000>; 96 }; 97 opp-1200000000 { 98 opp-hz = /bits/ 64 <1200000000>; 99 opp-microvolt = <820000>; 100 clock-latency-ns = <300000>; 101 }; 102 }; 103 104 cpus { 105 #address-cells = <1>; 106 #size-cells = <0>; 107 108 cpu-map { 109 cluster0 { 110 core0 { 111 cpu = <&a57_0>; 112 }; 113 core1 { 114 cpu = <&a57_1>; 115 }; 116 }; 117 118 cluster1 { 119 core0 { 120 cpu = <&a53_0>; 121 }; 122 core1 { 123 cpu = <&a53_1>; 124 }; 125 core2 { 126 cpu = <&a53_2>; 127 }; 128 core3 { 129 cpu = <&a53_3>; 130 }; 131 }; 132 }; 133 134 a57_0: cpu@0 { 135 compatible = "arm,cortex-a57"; 136 reg = <0x0>; 137 device_type = "cpu"; 138 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; 139 next-level-cache = <&L2_CA57>; 140 enable-method = "psci"; 141 dynamic-power-coefficient = <854>; 142 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 143 operating-points-v2 = <&cluster0_opp>; 144 capacity-dmips-mhz = <1024>; 145 #cooling-cells = <2>; 146 }; 147 148 a57_1: cpu@1 { 149 compatible = "arm,cortex-a57"; 150 reg = <0x1>; 151 device_type = "cpu"; 152 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; 153 next-level-cache = <&L2_CA57>; 154 enable-method = "psci"; 155 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 156 operating-points-v2 = <&cluster0_opp>; 157 capacity-dmips-mhz = <1024>; 158 #cooling-cells = <2>; 159 }; 160 161 a53_0: cpu@100 { 162 compatible = "arm,cortex-a53"; 163 reg = <0x100>; 164 device_type = "cpu"; 165 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; 166 next-level-cache = <&L2_CA53>; 167 enable-method = "psci"; 168 #cooling-cells = <2>; 169 dynamic-power-coefficient = <277>; 170 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 171 operating-points-v2 = <&cluster1_opp>; 172 capacity-dmips-mhz = <560>; 173 }; 174 175 a53_1: cpu@101 { 176 compatible = "arm,cortex-a53"; 177 reg = <0x101>; 178 device_type = "cpu"; 179 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; 180 next-level-cache = <&L2_CA53>; 181 enable-method = "psci"; 182 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 183 operating-points-v2 = <&cluster1_opp>; 184 capacity-dmips-mhz = <560>; 185 }; 186 187 a53_2: cpu@102 { 188 compatible = "arm,cortex-a53"; 189 reg = <0x102>; 190 device_type = "cpu"; 191 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; 192 next-level-cache = <&L2_CA53>; 193 enable-method = "psci"; 194 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 195 operating-points-v2 = <&cluster1_opp>; 196 capacity-dmips-mhz = <560>; 197 }; 198 199 a53_3: cpu@103 { 200 compatible = "arm,cortex-a53"; 201 reg = <0x103>; 202 device_type = "cpu"; 203 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; 204 next-level-cache = <&L2_CA53>; 205 enable-method = "psci"; 206 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 207 operating-points-v2 = <&cluster1_opp>; 208 capacity-dmips-mhz = <560>; 209 }; 210 211 L2_CA57: cache-controller-0 { 212 compatible = "cache"; 213 power-domains = <&sysc R8A774A1_PD_CA57_SCU>; 214 cache-unified; 215 cache-level = <2>; 216 }; 217 218 L2_CA53: cache-controller-1 { 219 compatible = "cache"; 220 power-domains = <&sysc R8A774A1_PD_CA53_SCU>; 221 cache-unified; 222 cache-level = <2>; 223 }; 224 }; 225 226 extal_clk: extal { 227 compatible = "fixed-clock"; 228 #clock-cells = <0>; 229 /* This value must be overridden by the board */ 230 clock-frequency = <0>; 231 }; 232 233 extalr_clk: extalr { 234 compatible = "fixed-clock"; 235 #clock-cells = <0>; 236 /* This value must be overridden by the board */ 237 clock-frequency = <0>; 238 }; 239 240 /* External PCIe clock - can be overridden by the board */ 241 pcie_bus_clk: pcie_bus { 242 compatible = "fixed-clock"; 243 #clock-cells = <0>; 244 clock-frequency = <0>; 245 }; 246 247 pmu_a53 { 248 compatible = "arm,cortex-a53-pmu"; 249 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 250 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 251 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 252 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 253 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 254 }; 255 256 pmu_a57 { 257 compatible = "arm,cortex-a57-pmu"; 258 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 259 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 260 interrupt-affinity = <&a57_0>, <&a57_1>; 261 }; 262 263 psci { 264 compatible = "arm,psci-1.0", "arm,psci-0.2"; 265 method = "smc"; 266 }; 267 268 /* External SCIF clock - to be overridden by boards that provide it */ 269 scif_clk: scif { 270 compatible = "fixed-clock"; 271 #clock-cells = <0>; 272 clock-frequency = <0>; 273 }; 274 275 soc { 276 compatible = "simple-bus"; 277 interrupt-parent = <&gic>; 278 #address-cells = <2>; 279 #size-cells = <2>; 280 ranges; 281 282 rwdt: watchdog@e6020000 { 283 compatible = "renesas,r8a774a1-wdt", 284 "renesas,rcar-gen3-wdt"; 285 reg = <0 0xe6020000 0 0x0c>; 286 clocks = <&cpg CPG_MOD 402>; 287 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 288 resets = <&cpg 402>; 289 status = "disabled"; 290 }; 291 292 gpio0: gpio@e6050000 { 293 compatible = "renesas,gpio-r8a774a1", 294 "renesas,rcar-gen3-gpio"; 295 reg = <0 0xe6050000 0 0x50>; 296 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 297 #gpio-cells = <2>; 298 gpio-controller; 299 gpio-ranges = <&pfc 0 0 16>; 300 #interrupt-cells = <2>; 301 interrupt-controller; 302 clocks = <&cpg CPG_MOD 912>; 303 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 304 resets = <&cpg 912>; 305 }; 306 307 gpio1: gpio@e6051000 { 308 compatible = "renesas,gpio-r8a774a1", 309 "renesas,rcar-gen3-gpio"; 310 reg = <0 0xe6051000 0 0x50>; 311 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 312 #gpio-cells = <2>; 313 gpio-controller; 314 gpio-ranges = <&pfc 0 32 29>; 315 #interrupt-cells = <2>; 316 interrupt-controller; 317 clocks = <&cpg CPG_MOD 911>; 318 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 319 resets = <&cpg 911>; 320 }; 321 322 gpio2: gpio@e6052000 { 323 compatible = "renesas,gpio-r8a774a1", 324 "renesas,rcar-gen3-gpio"; 325 reg = <0 0xe6052000 0 0x50>; 326 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 327 #gpio-cells = <2>; 328 gpio-controller; 329 gpio-ranges = <&pfc 0 64 15>; 330 #interrupt-cells = <2>; 331 interrupt-controller; 332 clocks = <&cpg CPG_MOD 910>; 333 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 334 resets = <&cpg 910>; 335 }; 336 337 gpio3: gpio@e6053000 { 338 compatible = "renesas,gpio-r8a774a1", 339 "renesas,rcar-gen3-gpio"; 340 reg = <0 0xe6053000 0 0x50>; 341 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 342 #gpio-cells = <2>; 343 gpio-controller; 344 gpio-ranges = <&pfc 0 96 16>; 345 #interrupt-cells = <2>; 346 interrupt-controller; 347 clocks = <&cpg CPG_MOD 909>; 348 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 349 resets = <&cpg 909>; 350 }; 351 352 gpio4: gpio@e6054000 { 353 compatible = "renesas,gpio-r8a774a1", 354 "renesas,rcar-gen3-gpio"; 355 reg = <0 0xe6054000 0 0x50>; 356 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 357 #gpio-cells = <2>; 358 gpio-controller; 359 gpio-ranges = <&pfc 0 128 18>; 360 #interrupt-cells = <2>; 361 interrupt-controller; 362 clocks = <&cpg CPG_MOD 908>; 363 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 364 resets = <&cpg 908>; 365 }; 366 367 gpio5: gpio@e6055000 { 368 compatible = "renesas,gpio-r8a774a1", 369 "renesas,rcar-gen3-gpio"; 370 reg = <0 0xe6055000 0 0x50>; 371 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 372 #gpio-cells = <2>; 373 gpio-controller; 374 gpio-ranges = <&pfc 0 160 26>; 375 #interrupt-cells = <2>; 376 interrupt-controller; 377 clocks = <&cpg CPG_MOD 907>; 378 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 379 resets = <&cpg 907>; 380 }; 381 382 gpio6: gpio@e6055400 { 383 compatible = "renesas,gpio-r8a774a1", 384 "renesas,rcar-gen3-gpio"; 385 reg = <0 0xe6055400 0 0x50>; 386 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 387 #gpio-cells = <2>; 388 gpio-controller; 389 gpio-ranges = <&pfc 0 192 32>; 390 #interrupt-cells = <2>; 391 interrupt-controller; 392 clocks = <&cpg CPG_MOD 906>; 393 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 394 resets = <&cpg 906>; 395 }; 396 397 gpio7: gpio@e6055800 { 398 compatible = "renesas,gpio-r8a774a1", 399 "renesas,rcar-gen3-gpio"; 400 reg = <0 0xe6055800 0 0x50>; 401 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 402 #gpio-cells = <2>; 403 gpio-controller; 404 gpio-ranges = <&pfc 0 224 4>; 405 #interrupt-cells = <2>; 406 interrupt-controller; 407 clocks = <&cpg CPG_MOD 905>; 408 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 409 resets = <&cpg 905>; 410 }; 411 412 pfc: pinctrl@e6060000 { 413 compatible = "renesas,pfc-r8a774a1"; 414 reg = <0 0xe6060000 0 0x50c>; 415 }; 416 417 cmt0: timer@e60f0000 { 418 compatible = "renesas,r8a774a1-cmt0", 419 "renesas,rcar-gen3-cmt0"; 420 reg = <0 0xe60f0000 0 0x1004>; 421 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&cpg CPG_MOD 303>; 424 clock-names = "fck"; 425 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 426 resets = <&cpg 303>; 427 status = "disabled"; 428 }; 429 430 cmt1: timer@e6130000 { 431 compatible = "renesas,r8a774a1-cmt1", 432 "renesas,rcar-gen3-cmt1"; 433 reg = <0 0xe6130000 0 0x1004>; 434 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&cpg CPG_MOD 302>; 443 clock-names = "fck"; 444 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 445 resets = <&cpg 302>; 446 status = "disabled"; 447 }; 448 449 cmt2: timer@e6140000 { 450 compatible = "renesas,r8a774a1-cmt1", 451 "renesas,rcar-gen3-cmt1"; 452 reg = <0 0xe6140000 0 0x1004>; 453 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&cpg CPG_MOD 301>; 462 clock-names = "fck"; 463 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 464 resets = <&cpg 301>; 465 status = "disabled"; 466 }; 467 468 cmt3: timer@e6148000 { 469 compatible = "renesas,r8a774a1-cmt1", 470 "renesas,rcar-gen3-cmt1"; 471 reg = <0 0xe6148000 0 0x1004>; 472 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&cpg CPG_MOD 300>; 481 clock-names = "fck"; 482 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 483 resets = <&cpg 300>; 484 status = "disabled"; 485 }; 486 487 cpg: clock-controller@e6150000 { 488 compatible = "renesas,r8a774a1-cpg-mssr"; 489 reg = <0 0xe6150000 0 0x0bb0>; 490 clocks = <&extal_clk>, <&extalr_clk>; 491 clock-names = "extal", "extalr"; 492 #clock-cells = <2>; 493 #power-domain-cells = <0>; 494 #reset-cells = <1>; 495 }; 496 497 rst: reset-controller@e6160000 { 498 compatible = "renesas,r8a774a1-rst"; 499 reg = <0 0xe6160000 0 0x018c>; 500 }; 501 502 sysc: system-controller@e6180000 { 503 compatible = "renesas,r8a774a1-sysc"; 504 reg = <0 0xe6180000 0 0x0400>; 505 #power-domain-cells = <1>; 506 }; 507 508 tsc: thermal@e6198000 { 509 compatible = "renesas,r8a774a1-thermal"; 510 reg = <0 0xe6198000 0 0x100>, 511 <0 0xe61a0000 0 0x100>, 512 <0 0xe61a8000 0 0x100>; 513 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&cpg CPG_MOD 522>; 517 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 518 resets = <&cpg 522>; 519 #thermal-sensor-cells = <1>; 520 }; 521 522 intc_ex: interrupt-controller@e61c0000 { 523 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; 524 #interrupt-cells = <2>; 525 interrupt-controller; 526 reg = <0 0xe61c0000 0 0x200>; 527 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&cpg CPG_MOD 407>; 534 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 535 resets = <&cpg 407>; 536 }; 537 538 tmu0: timer@e61e0000 { 539 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 540 reg = <0 0xe61e0000 0 0x30>; 541 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&cpg CPG_MOD 125>; 545 clock-names = "fck"; 546 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 547 resets = <&cpg 125>; 548 status = "disabled"; 549 }; 550 551 tmu1: timer@e6fc0000 { 552 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 553 reg = <0 0xe6fc0000 0 0x30>; 554 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&cpg CPG_MOD 124>; 558 clock-names = "fck"; 559 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 560 resets = <&cpg 124>; 561 status = "disabled"; 562 }; 563 564 tmu2: timer@e6fd0000 { 565 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 566 reg = <0 0xe6fd0000 0 0x30>; 567 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&cpg CPG_MOD 123>; 571 clock-names = "fck"; 572 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 573 resets = <&cpg 123>; 574 status = "disabled"; 575 }; 576 577 tmu3: timer@e6fe0000 { 578 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 579 reg = <0 0xe6fe0000 0 0x30>; 580 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&cpg CPG_MOD 122>; 584 clock-names = "fck"; 585 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 586 resets = <&cpg 122>; 587 status = "disabled"; 588 }; 589 590 tmu4: timer@ffc00000 { 591 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 592 reg = <0 0xffc00000 0 0x30>; 593 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&cpg CPG_MOD 121>; 597 clock-names = "fck"; 598 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 599 resets = <&cpg 121>; 600 status = "disabled"; 601 }; 602 603 i2c0: i2c@e6500000 { 604 #address-cells = <1>; 605 #size-cells = <0>; 606 compatible = "renesas,i2c-r8a774a1", 607 "renesas,rcar-gen3-i2c"; 608 reg = <0 0xe6500000 0 0x40>; 609 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&cpg CPG_MOD 931>; 611 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 612 resets = <&cpg 931>; 613 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 614 <&dmac2 0x91>, <&dmac2 0x90>; 615 dma-names = "tx", "rx", "tx", "rx"; 616 i2c-scl-internal-delay-ns = <110>; 617 status = "disabled"; 618 }; 619 620 i2c1: i2c@e6508000 { 621 #address-cells = <1>; 622 #size-cells = <0>; 623 compatible = "renesas,i2c-r8a774a1", 624 "renesas,rcar-gen3-i2c"; 625 reg = <0 0xe6508000 0 0x40>; 626 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&cpg CPG_MOD 930>; 628 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 629 resets = <&cpg 930>; 630 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 631 <&dmac2 0x93>, <&dmac2 0x92>; 632 dma-names = "tx", "rx", "tx", "rx"; 633 i2c-scl-internal-delay-ns = <6>; 634 status = "disabled"; 635 }; 636 637 i2c2: i2c@e6510000 { 638 #address-cells = <1>; 639 #size-cells = <0>; 640 compatible = "renesas,i2c-r8a774a1", 641 "renesas,rcar-gen3-i2c"; 642 reg = <0 0xe6510000 0 0x40>; 643 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&cpg CPG_MOD 929>; 645 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 646 resets = <&cpg 929>; 647 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 648 <&dmac2 0x95>, <&dmac2 0x94>; 649 dma-names = "tx", "rx", "tx", "rx"; 650 i2c-scl-internal-delay-ns = <6>; 651 status = "disabled"; 652 }; 653 654 i2c3: i2c@e66d0000 { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 compatible = "renesas,i2c-r8a774a1", 658 "renesas,rcar-gen3-i2c"; 659 reg = <0 0xe66d0000 0 0x40>; 660 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&cpg CPG_MOD 928>; 662 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 663 resets = <&cpg 928>; 664 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 665 dma-names = "tx", "rx"; 666 i2c-scl-internal-delay-ns = <110>; 667 status = "disabled"; 668 }; 669 670 i2c4: i2c@e66d8000 { 671 #address-cells = <1>; 672 #size-cells = <0>; 673 compatible = "renesas,i2c-r8a774a1", 674 "renesas,rcar-gen3-i2c"; 675 reg = <0 0xe66d8000 0 0x40>; 676 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&cpg CPG_MOD 927>; 678 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 679 resets = <&cpg 927>; 680 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 681 dma-names = "tx", "rx"; 682 i2c-scl-internal-delay-ns = <110>; 683 status = "disabled"; 684 }; 685 686 i2c5: i2c@e66e0000 { 687 #address-cells = <1>; 688 #size-cells = <0>; 689 compatible = "renesas,i2c-r8a774a1", 690 "renesas,rcar-gen3-i2c"; 691 reg = <0 0xe66e0000 0 0x40>; 692 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&cpg CPG_MOD 919>; 694 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 695 resets = <&cpg 919>; 696 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 697 dma-names = "tx", "rx"; 698 i2c-scl-internal-delay-ns = <110>; 699 status = "disabled"; 700 }; 701 702 i2c6: i2c@e66e8000 { 703 #address-cells = <1>; 704 #size-cells = <0>; 705 compatible = "renesas,i2c-r8a774a1", 706 "renesas,rcar-gen3-i2c"; 707 reg = <0 0xe66e8000 0 0x40>; 708 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&cpg CPG_MOD 918>; 710 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 711 resets = <&cpg 918>; 712 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 713 dma-names = "tx", "rx"; 714 i2c-scl-internal-delay-ns = <6>; 715 status = "disabled"; 716 }; 717 718 iic_pmic: i2c@e60b0000 { 719 #address-cells = <1>; 720 #size-cells = <0>; 721 compatible = "renesas,iic-r8a774a1", 722 "renesas,rcar-gen3-iic", 723 "renesas,rmobile-iic"; 724 reg = <0 0xe60b0000 0 0x425>; 725 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&cpg CPG_MOD 926>; 727 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 728 resets = <&cpg 926>; 729 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 730 dma-names = "tx", "rx"; 731 status = "disabled"; 732 }; 733 734 hscif0: serial@e6540000 { 735 compatible = "renesas,hscif-r8a774a1", 736 "renesas,rcar-gen3-hscif", 737 "renesas,hscif"; 738 reg = <0 0xe6540000 0 0x60>; 739 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&cpg CPG_MOD 520>, 741 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 742 <&scif_clk>; 743 clock-names = "fck", "brg_int", "scif_clk"; 744 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 745 <&dmac2 0x31>, <&dmac2 0x30>; 746 dma-names = "tx", "rx", "tx", "rx"; 747 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 748 resets = <&cpg 520>; 749 status = "disabled"; 750 }; 751 752 hscif1: serial@e6550000 { 753 compatible = "renesas,hscif-r8a774a1", 754 "renesas,rcar-gen3-hscif", 755 "renesas,hscif"; 756 reg = <0 0xe6550000 0 0x60>; 757 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&cpg CPG_MOD 519>, 759 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 760 <&scif_clk>; 761 clock-names = "fck", "brg_int", "scif_clk"; 762 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 763 <&dmac2 0x33>, <&dmac2 0x32>; 764 dma-names = "tx", "rx", "tx", "rx"; 765 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 766 resets = <&cpg 519>; 767 status = "disabled"; 768 }; 769 770 hscif2: serial@e6560000 { 771 compatible = "renesas,hscif-r8a774a1", 772 "renesas,rcar-gen3-hscif", 773 "renesas,hscif"; 774 reg = <0 0xe6560000 0 0x60>; 775 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&cpg CPG_MOD 518>, 777 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 778 <&scif_clk>; 779 clock-names = "fck", "brg_int", "scif_clk"; 780 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 781 <&dmac2 0x35>, <&dmac2 0x34>; 782 dma-names = "tx", "rx", "tx", "rx"; 783 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 784 resets = <&cpg 518>; 785 status = "disabled"; 786 }; 787 788 hscif3: serial@e66a0000 { 789 compatible = "renesas,hscif-r8a774a1", 790 "renesas,rcar-gen3-hscif", 791 "renesas,hscif"; 792 reg = <0 0xe66a0000 0 0x60>; 793 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&cpg CPG_MOD 517>, 795 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 796 <&scif_clk>; 797 clock-names = "fck", "brg_int", "scif_clk"; 798 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 799 dma-names = "tx", "rx"; 800 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 801 resets = <&cpg 517>; 802 status = "disabled"; 803 }; 804 805 hscif4: serial@e66b0000 { 806 compatible = "renesas,hscif-r8a774a1", 807 "renesas,rcar-gen3-hscif", 808 "renesas,hscif"; 809 reg = <0 0xe66b0000 0 0x60>; 810 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&cpg CPG_MOD 516>, 812 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 813 <&scif_clk>; 814 clock-names = "fck", "brg_int", "scif_clk"; 815 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 816 dma-names = "tx", "rx"; 817 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 818 resets = <&cpg 516>; 819 status = "disabled"; 820 }; 821 822 hsusb: usb@e6590000 { 823 compatible = "renesas,usbhs-r8a774a1", 824 "renesas,rcar-gen3-usbhs"; 825 reg = <0 0xe6590000 0 0x200>; 826 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 828 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 829 <&usb_dmac1 0>, <&usb_dmac1 1>; 830 dma-names = "ch0", "ch1", "ch2", "ch3"; 831 renesas,buswait = <11>; 832 phys = <&usb2_phy0 3>; 833 phy-names = "usb"; 834 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 835 resets = <&cpg 704>, <&cpg 703>; 836 status = "disabled"; 837 }; 838 839 usb2_clksel: clock-controller@e6590630 { 840 compatible = "renesas,r8a774a1-rcar-usb2-clock-sel", 841 "renesas,rcar-gen3-usb2-clock-sel"; 842 reg = <0 0xe6590630 0 0x02>; 843 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, 844 <&usb_extal_clk>, <&usb3s0_clk>; 845 clock-names = "ehci_ohci", "hs-usb-if", 846 "usb_extal", "usb_xtal"; 847 #clock-cells = <0>; 848 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 849 resets = <&cpg 703>, <&cpg 704>; 850 reset-names = "ehci_ohci", "hs-usb-if"; 851 status = "disabled"; 852 }; 853 854 usb_dmac0: dma-controller@e65a0000 { 855 compatible = "renesas,r8a774a1-usb-dmac", 856 "renesas,usb-dmac"; 857 reg = <0 0xe65a0000 0 0x100>; 858 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 860 interrupt-names = "ch0", "ch1"; 861 clocks = <&cpg CPG_MOD 330>; 862 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 863 resets = <&cpg 330>; 864 #dma-cells = <1>; 865 dma-channels = <2>; 866 }; 867 868 usb_dmac1: dma-controller@e65b0000 { 869 compatible = "renesas,r8a774a1-usb-dmac", 870 "renesas,usb-dmac"; 871 reg = <0 0xe65b0000 0 0x100>; 872 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 874 interrupt-names = "ch0", "ch1"; 875 clocks = <&cpg CPG_MOD 331>; 876 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 877 resets = <&cpg 331>; 878 #dma-cells = <1>; 879 dma-channels = <2>; 880 }; 881 882 usb3_phy0: usb-phy@e65ee000 { 883 compatible = "renesas,r8a774a1-usb3-phy", 884 "renesas,rcar-gen3-usb3-phy"; 885 reg = <0 0xe65ee000 0 0x90>; 886 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 887 <&usb_extal_clk>; 888 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 889 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 890 resets = <&cpg 328>; 891 #phy-cells = <0>; 892 status = "disabled"; 893 }; 894 895 dmac0: dma-controller@e6700000 { 896 compatible = "renesas,dmac-r8a774a1", 897 "renesas,rcar-dmac"; 898 reg = <0 0xe6700000 0 0x10000>; 899 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 916 interrupt-names = "error", 917 "ch0", "ch1", "ch2", "ch3", 918 "ch4", "ch5", "ch6", "ch7", 919 "ch8", "ch9", "ch10", "ch11", 920 "ch12", "ch13", "ch14", "ch15"; 921 clocks = <&cpg CPG_MOD 219>; 922 clock-names = "fck"; 923 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 924 resets = <&cpg 219>; 925 #dma-cells = <1>; 926 dma-channels = <16>; 927 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 928 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 929 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 930 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 931 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 932 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 933 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 934 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 935 }; 936 937 dmac1: dma-controller@e7300000 { 938 compatible = "renesas,dmac-r8a774a1", 939 "renesas,rcar-dmac"; 940 reg = <0 0xe7300000 0 0x10000>; 941 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 958 interrupt-names = "error", 959 "ch0", "ch1", "ch2", "ch3", 960 "ch4", "ch5", "ch6", "ch7", 961 "ch8", "ch9", "ch10", "ch11", 962 "ch12", "ch13", "ch14", "ch15"; 963 clocks = <&cpg CPG_MOD 218>; 964 clock-names = "fck"; 965 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 966 resets = <&cpg 218>; 967 #dma-cells = <1>; 968 dma-channels = <16>; 969 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 970 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 971 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 972 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 973 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 974 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 975 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 976 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 977 }; 978 979 dmac2: dma-controller@e7310000 { 980 compatible = "renesas,dmac-r8a774a1", 981 "renesas,rcar-dmac"; 982 reg = <0 0xe7310000 0 0x10000>; 983 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1000 interrupt-names = "error", 1001 "ch0", "ch1", "ch2", "ch3", 1002 "ch4", "ch5", "ch6", "ch7", 1003 "ch8", "ch9", "ch10", "ch11", 1004 "ch12", "ch13", "ch14", "ch15"; 1005 clocks = <&cpg CPG_MOD 217>; 1006 clock-names = "fck"; 1007 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1008 resets = <&cpg 217>; 1009 #dma-cells = <1>; 1010 dma-channels = <16>; 1011 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1012 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1013 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1014 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1015 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1016 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1017 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1018 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1019 }; 1020 1021 ipmmu_ds0: iommu@e6740000 { 1022 compatible = "renesas,ipmmu-r8a774a1"; 1023 reg = <0 0xe6740000 0 0x1000>; 1024 renesas,ipmmu-main = <&ipmmu_mm 0>; 1025 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1026 #iommu-cells = <1>; 1027 }; 1028 1029 ipmmu_ds1: iommu@e7740000 { 1030 compatible = "renesas,ipmmu-r8a774a1"; 1031 reg = <0 0xe7740000 0 0x1000>; 1032 renesas,ipmmu-main = <&ipmmu_mm 1>; 1033 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1034 #iommu-cells = <1>; 1035 }; 1036 1037 ipmmu_hc: iommu@e6570000 { 1038 compatible = "renesas,ipmmu-r8a774a1"; 1039 reg = <0 0xe6570000 0 0x1000>; 1040 renesas,ipmmu-main = <&ipmmu_mm 2>; 1041 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1042 #iommu-cells = <1>; 1043 }; 1044 1045 ipmmu_mm: iommu@e67b0000 { 1046 compatible = "renesas,ipmmu-r8a774a1"; 1047 reg = <0 0xe67b0000 0 0x1000>; 1048 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1050 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1051 #iommu-cells = <1>; 1052 }; 1053 1054 ipmmu_mp: iommu@ec670000 { 1055 compatible = "renesas,ipmmu-r8a774a1"; 1056 reg = <0 0xec670000 0 0x1000>; 1057 renesas,ipmmu-main = <&ipmmu_mm 4>; 1058 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1059 #iommu-cells = <1>; 1060 }; 1061 1062 ipmmu_pv0: iommu@fd800000 { 1063 compatible = "renesas,ipmmu-r8a774a1"; 1064 reg = <0 0xfd800000 0 0x1000>; 1065 renesas,ipmmu-main = <&ipmmu_mm 5>; 1066 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1067 #iommu-cells = <1>; 1068 }; 1069 1070 ipmmu_pv1: iommu@fd950000 { 1071 compatible = "renesas,ipmmu-r8a774a1"; 1072 reg = <0 0xfd950000 0 0x1000>; 1073 renesas,ipmmu-main = <&ipmmu_mm 6>; 1074 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1075 #iommu-cells = <1>; 1076 }; 1077 1078 ipmmu_vc0: iommu@fe6b0000 { 1079 compatible = "renesas,ipmmu-r8a774a1"; 1080 reg = <0 0xfe6b0000 0 0x1000>; 1081 renesas,ipmmu-main = <&ipmmu_mm 8>; 1082 power-domains = <&sysc R8A774A1_PD_A3VC>; 1083 #iommu-cells = <1>; 1084 }; 1085 1086 ipmmu_vi0: iommu@febd0000 { 1087 compatible = "renesas,ipmmu-r8a774a1"; 1088 reg = <0 0xfebd0000 0 0x1000>; 1089 renesas,ipmmu-main = <&ipmmu_mm 9>; 1090 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1091 #iommu-cells = <1>; 1092 }; 1093 1094 avb: ethernet@e6800000 { 1095 compatible = "renesas,etheravb-r8a774a1", 1096 "renesas,etheravb-rcar-gen3"; 1097 reg = <0 0xe6800000 0 0x800>; 1098 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1123 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1124 "ch4", "ch5", "ch6", "ch7", 1125 "ch8", "ch9", "ch10", "ch11", 1126 "ch12", "ch13", "ch14", "ch15", 1127 "ch16", "ch17", "ch18", "ch19", 1128 "ch20", "ch21", "ch22", "ch23", 1129 "ch24"; 1130 clocks = <&cpg CPG_MOD 812>; 1131 clock-names = "fck"; 1132 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1133 resets = <&cpg 812>; 1134 phy-mode = "rgmii"; 1135 rx-internal-delay-ps = <0>; 1136 tx-internal-delay-ps = <0>; 1137 iommus = <&ipmmu_ds0 16>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 status = "disabled"; 1141 }; 1142 1143 can0: can@e6c30000 { 1144 compatible = "renesas,can-r8a774a1", 1145 "renesas,rcar-gen3-can"; 1146 reg = <0 0xe6c30000 0 0x1000>; 1147 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1148 clocks = <&cpg CPG_MOD 916>, 1149 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1150 <&can_clk>; 1151 clock-names = "clkp1", "clkp2", "can_clk"; 1152 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1153 assigned-clock-rates = <40000000>; 1154 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1155 resets = <&cpg 916>; 1156 status = "disabled"; 1157 }; 1158 1159 can1: can@e6c38000 { 1160 compatible = "renesas,can-r8a774a1", 1161 "renesas,rcar-gen3-can"; 1162 reg = <0 0xe6c38000 0 0x1000>; 1163 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1164 clocks = <&cpg CPG_MOD 915>, 1165 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1166 <&can_clk>; 1167 clock-names = "clkp1", "clkp2", "can_clk"; 1168 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1169 assigned-clock-rates = <40000000>; 1170 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1171 resets = <&cpg 915>; 1172 status = "disabled"; 1173 }; 1174 1175 canfd: can@e66c0000 { 1176 compatible = "renesas,r8a774a1-canfd", 1177 "renesas,rcar-gen3-canfd"; 1178 reg = <0 0xe66c0000 0 0x8000>; 1179 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1181 clocks = <&cpg CPG_MOD 914>, 1182 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1183 <&can_clk>; 1184 clock-names = "fck", "canfd", "can_clk"; 1185 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1186 assigned-clock-rates = <40000000>; 1187 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1188 resets = <&cpg 914>; 1189 status = "disabled"; 1190 1191 channel0 { 1192 status = "disabled"; 1193 }; 1194 1195 channel1 { 1196 status = "disabled"; 1197 }; 1198 }; 1199 1200 pwm0: pwm@e6e30000 { 1201 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1202 reg = <0 0xe6e30000 0 0x8>; 1203 #pwm-cells = <2>; 1204 clocks = <&cpg CPG_MOD 523>; 1205 resets = <&cpg 523>; 1206 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1207 status = "disabled"; 1208 }; 1209 1210 pwm1: pwm@e6e31000 { 1211 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1212 reg = <0 0xe6e31000 0 0x8>; 1213 #pwm-cells = <2>; 1214 clocks = <&cpg CPG_MOD 523>; 1215 resets = <&cpg 523>; 1216 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1217 status = "disabled"; 1218 }; 1219 1220 pwm2: pwm@e6e32000 { 1221 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1222 reg = <0 0xe6e32000 0 0x8>; 1223 #pwm-cells = <2>; 1224 clocks = <&cpg CPG_MOD 523>; 1225 resets = <&cpg 523>; 1226 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1227 status = "disabled"; 1228 }; 1229 1230 pwm3: pwm@e6e33000 { 1231 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1232 reg = <0 0xe6e33000 0 0x8>; 1233 #pwm-cells = <2>; 1234 clocks = <&cpg CPG_MOD 523>; 1235 resets = <&cpg 523>; 1236 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1237 status = "disabled"; 1238 }; 1239 1240 pwm4: pwm@e6e34000 { 1241 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1242 reg = <0 0xe6e34000 0 0x8>; 1243 #pwm-cells = <2>; 1244 clocks = <&cpg CPG_MOD 523>; 1245 resets = <&cpg 523>; 1246 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1247 status = "disabled"; 1248 }; 1249 1250 pwm5: pwm@e6e35000 { 1251 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1252 reg = <0 0xe6e35000 0 0x8>; 1253 #pwm-cells = <2>; 1254 clocks = <&cpg CPG_MOD 523>; 1255 resets = <&cpg 523>; 1256 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1257 status = "disabled"; 1258 }; 1259 1260 pwm6: pwm@e6e36000 { 1261 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1262 reg = <0 0xe6e36000 0 0x8>; 1263 #pwm-cells = <2>; 1264 clocks = <&cpg CPG_MOD 523>; 1265 resets = <&cpg 523>; 1266 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1267 status = "disabled"; 1268 }; 1269 1270 scif0: serial@e6e60000 { 1271 compatible = "renesas,scif-r8a774a1", 1272 "renesas,rcar-gen3-scif", "renesas,scif"; 1273 reg = <0 0xe6e60000 0 0x40>; 1274 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1275 clocks = <&cpg CPG_MOD 207>, 1276 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1277 <&scif_clk>; 1278 clock-names = "fck", "brg_int", "scif_clk"; 1279 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1280 <&dmac2 0x51>, <&dmac2 0x50>; 1281 dma-names = "tx", "rx", "tx", "rx"; 1282 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1283 resets = <&cpg 207>; 1284 status = "disabled"; 1285 }; 1286 1287 scif1: serial@e6e68000 { 1288 compatible = "renesas,scif-r8a774a1", 1289 "renesas,rcar-gen3-scif", "renesas,scif"; 1290 reg = <0 0xe6e68000 0 0x40>; 1291 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1292 clocks = <&cpg CPG_MOD 206>, 1293 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1294 <&scif_clk>; 1295 clock-names = "fck", "brg_int", "scif_clk"; 1296 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1297 <&dmac2 0x53>, <&dmac2 0x52>; 1298 dma-names = "tx", "rx", "tx", "rx"; 1299 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1300 resets = <&cpg 206>; 1301 status = "disabled"; 1302 }; 1303 1304 scif2: serial@e6e88000 { 1305 compatible = "renesas,scif-r8a774a1", 1306 "renesas,rcar-gen3-scif", "renesas,scif"; 1307 reg = <0 0xe6e88000 0 0x40>; 1308 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1309 clocks = <&cpg CPG_MOD 310>, 1310 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1311 <&scif_clk>; 1312 clock-names = "fck", "brg_int", "scif_clk"; 1313 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1314 <&dmac2 0x13>, <&dmac2 0x12>; 1315 dma-names = "tx", "rx", "tx", "rx"; 1316 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1317 resets = <&cpg 310>; 1318 status = "disabled"; 1319 }; 1320 1321 scif3: serial@e6c50000 { 1322 compatible = "renesas,scif-r8a774a1", 1323 "renesas,rcar-gen3-scif", "renesas,scif"; 1324 reg = <0 0xe6c50000 0 0x40>; 1325 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1326 clocks = <&cpg CPG_MOD 204>, 1327 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1328 <&scif_clk>; 1329 clock-names = "fck", "brg_int", "scif_clk"; 1330 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1331 dma-names = "tx", "rx"; 1332 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1333 resets = <&cpg 204>; 1334 status = "disabled"; 1335 }; 1336 1337 scif4: serial@e6c40000 { 1338 compatible = "renesas,scif-r8a774a1", 1339 "renesas,rcar-gen3-scif", "renesas,scif"; 1340 reg = <0 0xe6c40000 0 0x40>; 1341 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1342 clocks = <&cpg CPG_MOD 203>, 1343 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1344 <&scif_clk>; 1345 clock-names = "fck", "brg_int", "scif_clk"; 1346 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1347 dma-names = "tx", "rx"; 1348 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1349 resets = <&cpg 203>; 1350 status = "disabled"; 1351 }; 1352 1353 scif5: serial@e6f30000 { 1354 compatible = "renesas,scif-r8a774a1", 1355 "renesas,rcar-gen3-scif", "renesas,scif"; 1356 reg = <0 0xe6f30000 0 0x40>; 1357 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1358 clocks = <&cpg CPG_MOD 202>, 1359 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1360 <&scif_clk>; 1361 clock-names = "fck", "brg_int", "scif_clk"; 1362 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1363 <&dmac2 0x5b>, <&dmac2 0x5a>; 1364 dma-names = "tx", "rx", "tx", "rx"; 1365 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1366 resets = <&cpg 202>; 1367 status = "disabled"; 1368 }; 1369 1370 msiof0: spi@e6e90000 { 1371 compatible = "renesas,msiof-r8a774a1", 1372 "renesas,rcar-gen3-msiof"; 1373 reg = <0 0xe6e90000 0 0x0064>; 1374 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1375 clocks = <&cpg CPG_MOD 211>; 1376 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1377 <&dmac2 0x41>, <&dmac2 0x40>; 1378 dma-names = "tx", "rx", "tx", "rx"; 1379 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1380 resets = <&cpg 211>; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 status = "disabled"; 1384 }; 1385 1386 msiof1: spi@e6ea0000 { 1387 compatible = "renesas,msiof-r8a774a1", 1388 "renesas,rcar-gen3-msiof"; 1389 reg = <0 0xe6ea0000 0 0x0064>; 1390 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1391 clocks = <&cpg CPG_MOD 210>; 1392 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1393 <&dmac2 0x43>, <&dmac2 0x42>; 1394 dma-names = "tx", "rx", "tx", "rx"; 1395 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1396 resets = <&cpg 210>; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 status = "disabled"; 1400 }; 1401 1402 msiof2: spi@e6c00000 { 1403 compatible = "renesas,msiof-r8a774a1", 1404 "renesas,rcar-gen3-msiof"; 1405 reg = <0 0xe6c00000 0 0x0064>; 1406 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1407 clocks = <&cpg CPG_MOD 209>; 1408 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1409 dma-names = "tx", "rx"; 1410 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1411 resets = <&cpg 209>; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 status = "disabled"; 1415 }; 1416 1417 msiof3: spi@e6c10000 { 1418 compatible = "renesas,msiof-r8a774a1", 1419 "renesas,rcar-gen3-msiof"; 1420 reg = <0 0xe6c10000 0 0x0064>; 1421 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1422 clocks = <&cpg CPG_MOD 208>; 1423 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1424 dma-names = "tx", "rx"; 1425 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1426 resets = <&cpg 208>; 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 status = "disabled"; 1430 }; 1431 1432 vin0: video@e6ef0000 { 1433 compatible = "renesas,vin-r8a774a1"; 1434 reg = <0 0xe6ef0000 0 0x1000>; 1435 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1436 clocks = <&cpg CPG_MOD 811>; 1437 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1438 resets = <&cpg 811>; 1439 renesas,id = <0>; 1440 status = "disabled"; 1441 1442 ports { 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 1446 port@1 { 1447 #address-cells = <1>; 1448 #size-cells = <0>; 1449 1450 reg = <1>; 1451 1452 vin0csi20: endpoint@0 { 1453 reg = <0>; 1454 remote-endpoint = <&csi20vin0>; 1455 }; 1456 vin0csi40: endpoint@2 { 1457 reg = <2>; 1458 remote-endpoint = <&csi40vin0>; 1459 }; 1460 }; 1461 }; 1462 }; 1463 1464 vin1: video@e6ef1000 { 1465 compatible = "renesas,vin-r8a774a1"; 1466 reg = <0 0xe6ef1000 0 0x1000>; 1467 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1468 clocks = <&cpg CPG_MOD 810>; 1469 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1470 resets = <&cpg 810>; 1471 renesas,id = <1>; 1472 status = "disabled"; 1473 1474 ports { 1475 #address-cells = <1>; 1476 #size-cells = <0>; 1477 1478 port@1 { 1479 #address-cells = <1>; 1480 #size-cells = <0>; 1481 1482 reg = <1>; 1483 1484 vin1csi20: endpoint@0 { 1485 reg = <0>; 1486 remote-endpoint = <&csi20vin1>; 1487 }; 1488 vin1csi40: endpoint@2 { 1489 reg = <2>; 1490 remote-endpoint = <&csi40vin1>; 1491 }; 1492 }; 1493 }; 1494 }; 1495 1496 vin2: video@e6ef2000 { 1497 compatible = "renesas,vin-r8a774a1"; 1498 reg = <0 0xe6ef2000 0 0x1000>; 1499 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1500 clocks = <&cpg CPG_MOD 809>; 1501 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1502 resets = <&cpg 809>; 1503 renesas,id = <2>; 1504 status = "disabled"; 1505 1506 ports { 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 1510 port@1 { 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 1514 reg = <1>; 1515 1516 vin2csi20: endpoint@0 { 1517 reg = <0>; 1518 remote-endpoint = <&csi20vin2>; 1519 }; 1520 vin2csi40: endpoint@2 { 1521 reg = <2>; 1522 remote-endpoint = <&csi40vin2>; 1523 }; 1524 }; 1525 }; 1526 }; 1527 1528 vin3: video@e6ef3000 { 1529 compatible = "renesas,vin-r8a774a1"; 1530 reg = <0 0xe6ef3000 0 0x1000>; 1531 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1532 clocks = <&cpg CPG_MOD 808>; 1533 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1534 resets = <&cpg 808>; 1535 renesas,id = <3>; 1536 status = "disabled"; 1537 1538 ports { 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 1542 port@1 { 1543 #address-cells = <1>; 1544 #size-cells = <0>; 1545 1546 reg = <1>; 1547 1548 vin3csi20: endpoint@0 { 1549 reg = <0>; 1550 remote-endpoint = <&csi20vin3>; 1551 }; 1552 vin3csi40: endpoint@2 { 1553 reg = <2>; 1554 remote-endpoint = <&csi40vin3>; 1555 }; 1556 }; 1557 }; 1558 }; 1559 1560 vin4: video@e6ef4000 { 1561 compatible = "renesas,vin-r8a774a1"; 1562 reg = <0 0xe6ef4000 0 0x1000>; 1563 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1564 clocks = <&cpg CPG_MOD 807>; 1565 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1566 resets = <&cpg 807>; 1567 renesas,id = <4>; 1568 status = "disabled"; 1569 1570 ports { 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 1574 port@1 { 1575 #address-cells = <1>; 1576 #size-cells = <0>; 1577 1578 reg = <1>; 1579 1580 vin4csi20: endpoint@0 { 1581 reg = <0>; 1582 remote-endpoint = <&csi20vin4>; 1583 }; 1584 vin4csi40: endpoint@2 { 1585 reg = <2>; 1586 remote-endpoint = <&csi40vin4>; 1587 }; 1588 }; 1589 }; 1590 }; 1591 1592 vin5: video@e6ef5000 { 1593 compatible = "renesas,vin-r8a774a1"; 1594 reg = <0 0xe6ef5000 0 0x1000>; 1595 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1596 clocks = <&cpg CPG_MOD 806>; 1597 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1598 resets = <&cpg 806>; 1599 renesas,id = <5>; 1600 status = "disabled"; 1601 1602 ports { 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 1606 port@1 { 1607 #address-cells = <1>; 1608 #size-cells = <0>; 1609 1610 reg = <1>; 1611 1612 vin5csi20: endpoint@0 { 1613 reg = <0>; 1614 remote-endpoint = <&csi20vin5>; 1615 }; 1616 vin5csi40: endpoint@2 { 1617 reg = <2>; 1618 remote-endpoint = <&csi40vin5>; 1619 }; 1620 }; 1621 }; 1622 }; 1623 1624 vin6: video@e6ef6000 { 1625 compatible = "renesas,vin-r8a774a1"; 1626 reg = <0 0xe6ef6000 0 0x1000>; 1627 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1628 clocks = <&cpg CPG_MOD 805>; 1629 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1630 resets = <&cpg 805>; 1631 renesas,id = <6>; 1632 status = "disabled"; 1633 1634 ports { 1635 #address-cells = <1>; 1636 #size-cells = <0>; 1637 1638 port@1 { 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 1642 reg = <1>; 1643 1644 vin6csi20: endpoint@0 { 1645 reg = <0>; 1646 remote-endpoint = <&csi20vin6>; 1647 }; 1648 vin6csi40: endpoint@2 { 1649 reg = <2>; 1650 remote-endpoint = <&csi40vin6>; 1651 }; 1652 }; 1653 }; 1654 }; 1655 1656 vin7: video@e6ef7000 { 1657 compatible = "renesas,vin-r8a774a1"; 1658 reg = <0 0xe6ef7000 0 0x1000>; 1659 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1660 clocks = <&cpg CPG_MOD 804>; 1661 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1662 resets = <&cpg 804>; 1663 renesas,id = <7>; 1664 status = "disabled"; 1665 1666 ports { 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 1670 port@1 { 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 1674 reg = <1>; 1675 1676 vin7csi20: endpoint@0 { 1677 reg = <0>; 1678 remote-endpoint = <&csi20vin7>; 1679 }; 1680 vin7csi40: endpoint@2 { 1681 reg = <2>; 1682 remote-endpoint = <&csi40vin7>; 1683 }; 1684 }; 1685 }; 1686 }; 1687 1688 rcar_sound: sound@ec500000 { 1689 /* 1690 * #sound-dai-cells is required 1691 * 1692 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1693 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1694 */ 1695 /* 1696 * #clock-cells is required for audio_clkout0/1/2/3 1697 * 1698 * clkout : #clock-cells = <0>; <&rcar_sound>; 1699 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1700 */ 1701 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; 1702 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1703 <0 0xec5a0000 0 0x100>, /* ADG */ 1704 <0 0xec540000 0 0x1000>, /* SSIU */ 1705 <0 0xec541000 0 0x280>, /* SSI */ 1706 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1707 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1708 1709 clocks = <&cpg CPG_MOD 1005>, 1710 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1711 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1712 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1713 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1714 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1715 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1716 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1717 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1718 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1719 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1720 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1721 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1722 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1723 <&audio_clk_a>, <&audio_clk_b>, 1724 <&audio_clk_c>, 1725 <&cpg CPG_CORE R8A774A1_CLK_S0D4>; 1726 clock-names = "ssi-all", 1727 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1728 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1729 "ssi.1", "ssi.0", 1730 "src.9", "src.8", "src.7", "src.6", 1731 "src.5", "src.4", "src.3", "src.2", 1732 "src.1", "src.0", 1733 "mix.1", "mix.0", 1734 "ctu.1", "ctu.0", 1735 "dvc.0", "dvc.1", 1736 "clk_a", "clk_b", "clk_c", "clk_i"; 1737 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1738 resets = <&cpg 1005>, 1739 <&cpg 1006>, <&cpg 1007>, 1740 <&cpg 1008>, <&cpg 1009>, 1741 <&cpg 1010>, <&cpg 1011>, 1742 <&cpg 1012>, <&cpg 1013>, 1743 <&cpg 1014>, <&cpg 1015>; 1744 reset-names = "ssi-all", 1745 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1746 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1747 "ssi.1", "ssi.0"; 1748 status = "disabled"; 1749 1750 rcar_sound,ctu { 1751 ctu00: ctu-0 { }; 1752 ctu01: ctu-1 { }; 1753 ctu02: ctu-2 { }; 1754 ctu03: ctu-3 { }; 1755 ctu10: ctu-4 { }; 1756 ctu11: ctu-5 { }; 1757 ctu12: ctu-6 { }; 1758 ctu13: ctu-7 { }; 1759 }; 1760 1761 rcar_sound,dvc { 1762 dvc0: dvc-0 { 1763 dmas = <&audma1 0xbc>; 1764 dma-names = "tx"; 1765 }; 1766 dvc1: dvc-1 { 1767 dmas = <&audma1 0xbe>; 1768 dma-names = "tx"; 1769 }; 1770 }; 1771 1772 rcar_sound,mix { 1773 mix0: mix-0 { }; 1774 mix1: mix-1 { }; 1775 }; 1776 1777 rcar_sound,src { 1778 src0: src-0 { 1779 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1780 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1781 dma-names = "rx", "tx"; 1782 }; 1783 src1: src-1 { 1784 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1785 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1786 dma-names = "rx", "tx"; 1787 }; 1788 src2: src-2 { 1789 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1790 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1791 dma-names = "rx", "tx"; 1792 }; 1793 src3: src-3 { 1794 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1795 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1796 dma-names = "rx", "tx"; 1797 }; 1798 src4: src-4 { 1799 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1800 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1801 dma-names = "rx", "tx"; 1802 }; 1803 src5: src-5 { 1804 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1805 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1806 dma-names = "rx", "tx"; 1807 }; 1808 src6: src-6 { 1809 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1810 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1811 dma-names = "rx", "tx"; 1812 }; 1813 src7: src-7 { 1814 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1815 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1816 dma-names = "rx", "tx"; 1817 }; 1818 src8: src-8 { 1819 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1820 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1821 dma-names = "rx", "tx"; 1822 }; 1823 src9: src-9 { 1824 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1825 dmas = <&audma0 0x97>, <&audma1 0xba>; 1826 dma-names = "rx", "tx"; 1827 }; 1828 }; 1829 1830 rcar_sound,ssi { 1831 ssi0: ssi-0 { 1832 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1833 dmas = <&audma0 0x01>, <&audma1 0x02>; 1834 dma-names = "rx", "tx"; 1835 }; 1836 ssi1: ssi-1 { 1837 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1838 dmas = <&audma0 0x03>, <&audma1 0x04>; 1839 dma-names = "rx", "tx"; 1840 }; 1841 ssi2: ssi-2 { 1842 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1843 dmas = <&audma0 0x05>, <&audma1 0x06>; 1844 dma-names = "rx", "tx"; 1845 }; 1846 ssi3: ssi-3 { 1847 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1848 dmas = <&audma0 0x07>, <&audma1 0x08>; 1849 dma-names = "rx", "tx"; 1850 }; 1851 ssi4: ssi-4 { 1852 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1853 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1854 dma-names = "rx", "tx"; 1855 }; 1856 ssi5: ssi-5 { 1857 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1858 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1859 dma-names = "rx", "tx"; 1860 }; 1861 ssi6: ssi-6 { 1862 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1863 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1864 dma-names = "rx", "tx"; 1865 }; 1866 ssi7: ssi-7 { 1867 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1868 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1869 dma-names = "rx", "tx"; 1870 }; 1871 ssi8: ssi-8 { 1872 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1873 dmas = <&audma0 0x11>, <&audma1 0x12>; 1874 dma-names = "rx", "tx"; 1875 }; 1876 ssi9: ssi-9 { 1877 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1878 dmas = <&audma0 0x13>, <&audma1 0x14>; 1879 dma-names = "rx", "tx"; 1880 }; 1881 }; 1882 1883 rcar_sound,ssiu { 1884 ssiu00: ssiu-0 { 1885 dmas = <&audma0 0x15>, <&audma1 0x16>; 1886 dma-names = "rx", "tx"; 1887 }; 1888 ssiu01: ssiu-1 { 1889 dmas = <&audma0 0x35>, <&audma1 0x36>; 1890 dma-names = "rx", "tx"; 1891 }; 1892 ssiu02: ssiu-2 { 1893 dmas = <&audma0 0x37>, <&audma1 0x38>; 1894 dma-names = "rx", "tx"; 1895 }; 1896 ssiu03: ssiu-3 { 1897 dmas = <&audma0 0x47>, <&audma1 0x48>; 1898 dma-names = "rx", "tx"; 1899 }; 1900 ssiu04: ssiu-4 { 1901 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1902 dma-names = "rx", "tx"; 1903 }; 1904 ssiu05: ssiu-5 { 1905 dmas = <&audma0 0x43>, <&audma1 0x44>; 1906 dma-names = "rx", "tx"; 1907 }; 1908 ssiu06: ssiu-6 { 1909 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1910 dma-names = "rx", "tx"; 1911 }; 1912 ssiu07: ssiu-7 { 1913 dmas = <&audma0 0x53>, <&audma1 0x54>; 1914 dma-names = "rx", "tx"; 1915 }; 1916 ssiu10: ssiu-8 { 1917 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1918 dma-names = "rx", "tx"; 1919 }; 1920 ssiu11: ssiu-9 { 1921 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1922 dma-names = "rx", "tx"; 1923 }; 1924 ssiu12: ssiu-10 { 1925 dmas = <&audma0 0x57>, <&audma1 0x58>; 1926 dma-names = "rx", "tx"; 1927 }; 1928 ssiu13: ssiu-11 { 1929 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1930 dma-names = "rx", "tx"; 1931 }; 1932 ssiu14: ssiu-12 { 1933 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1934 dma-names = "rx", "tx"; 1935 }; 1936 ssiu15: ssiu-13 { 1937 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1938 dma-names = "rx", "tx"; 1939 }; 1940 ssiu16: ssiu-14 { 1941 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1942 dma-names = "rx", "tx"; 1943 }; 1944 ssiu17: ssiu-15 { 1945 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1946 dma-names = "rx", "tx"; 1947 }; 1948 ssiu20: ssiu-16 { 1949 dmas = <&audma0 0x63>, <&audma1 0x64>; 1950 dma-names = "rx", "tx"; 1951 }; 1952 ssiu21: ssiu-17 { 1953 dmas = <&audma0 0x67>, <&audma1 0x68>; 1954 dma-names = "rx", "tx"; 1955 }; 1956 ssiu22: ssiu-18 { 1957 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1958 dma-names = "rx", "tx"; 1959 }; 1960 ssiu23: ssiu-19 { 1961 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1962 dma-names = "rx", "tx"; 1963 }; 1964 ssiu24: ssiu-20 { 1965 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1966 dma-names = "rx", "tx"; 1967 }; 1968 ssiu25: ssiu-21 { 1969 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1970 dma-names = "rx", "tx"; 1971 }; 1972 ssiu26: ssiu-22 { 1973 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1974 dma-names = "rx", "tx"; 1975 }; 1976 ssiu27: ssiu-23 { 1977 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1978 dma-names = "rx", "tx"; 1979 }; 1980 ssiu30: ssiu-24 { 1981 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1982 dma-names = "rx", "tx"; 1983 }; 1984 ssiu31: ssiu-25 { 1985 dmas = <&audma0 0x21>, <&audma1 0x22>; 1986 dma-names = "rx", "tx"; 1987 }; 1988 ssiu32: ssiu-26 { 1989 dmas = <&audma0 0x23>, <&audma1 0x24>; 1990 dma-names = "rx", "tx"; 1991 }; 1992 ssiu33: ssiu-27 { 1993 dmas = <&audma0 0x25>, <&audma1 0x26>; 1994 dma-names = "rx", "tx"; 1995 }; 1996 ssiu34: ssiu-28 { 1997 dmas = <&audma0 0x27>, <&audma1 0x28>; 1998 dma-names = "rx", "tx"; 1999 }; 2000 ssiu35: ssiu-29 { 2001 dmas = <&audma0 0x29>, <&audma1 0x2A>; 2002 dma-names = "rx", "tx"; 2003 }; 2004 ssiu36: ssiu-30 { 2005 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 2006 dma-names = "rx", "tx"; 2007 }; 2008 ssiu37: ssiu-31 { 2009 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 2010 dma-names = "rx", "tx"; 2011 }; 2012 ssiu40: ssiu-32 { 2013 dmas = <&audma0 0x71>, <&audma1 0x72>; 2014 dma-names = "rx", "tx"; 2015 }; 2016 ssiu41: ssiu-33 { 2017 dmas = <&audma0 0x17>, <&audma1 0x18>; 2018 dma-names = "rx", "tx"; 2019 }; 2020 ssiu42: ssiu-34 { 2021 dmas = <&audma0 0x19>, <&audma1 0x1A>; 2022 dma-names = "rx", "tx"; 2023 }; 2024 ssiu43: ssiu-35 { 2025 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 2026 dma-names = "rx", "tx"; 2027 }; 2028 ssiu44: ssiu-36 { 2029 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 2030 dma-names = "rx", "tx"; 2031 }; 2032 ssiu45: ssiu-37 { 2033 dmas = <&audma0 0x1F>, <&audma1 0x20>; 2034 dma-names = "rx", "tx"; 2035 }; 2036 ssiu46: ssiu-38 { 2037 dmas = <&audma0 0x31>, <&audma1 0x32>; 2038 dma-names = "rx", "tx"; 2039 }; 2040 ssiu47: ssiu-39 { 2041 dmas = <&audma0 0x33>, <&audma1 0x34>; 2042 dma-names = "rx", "tx"; 2043 }; 2044 ssiu50: ssiu-40 { 2045 dmas = <&audma0 0x73>, <&audma1 0x74>; 2046 dma-names = "rx", "tx"; 2047 }; 2048 ssiu60: ssiu-41 { 2049 dmas = <&audma0 0x75>, <&audma1 0x76>; 2050 dma-names = "rx", "tx"; 2051 }; 2052 ssiu70: ssiu-42 { 2053 dmas = <&audma0 0x79>, <&audma1 0x7a>; 2054 dma-names = "rx", "tx"; 2055 }; 2056 ssiu80: ssiu-43 { 2057 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 2058 dma-names = "rx", "tx"; 2059 }; 2060 ssiu90: ssiu-44 { 2061 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 2062 dma-names = "rx", "tx"; 2063 }; 2064 ssiu91: ssiu-45 { 2065 dmas = <&audma0 0x7F>, <&audma1 0x80>; 2066 dma-names = "rx", "tx"; 2067 }; 2068 ssiu92: ssiu-46 { 2069 dmas = <&audma0 0x81>, <&audma1 0x82>; 2070 dma-names = "rx", "tx"; 2071 }; 2072 ssiu93: ssiu-47 { 2073 dmas = <&audma0 0x83>, <&audma1 0x84>; 2074 dma-names = "rx", "tx"; 2075 }; 2076 ssiu94: ssiu-48 { 2077 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 2078 dma-names = "rx", "tx"; 2079 }; 2080 ssiu95: ssiu-49 { 2081 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 2082 dma-names = "rx", "tx"; 2083 }; 2084 ssiu96: ssiu-50 { 2085 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2086 dma-names = "rx", "tx"; 2087 }; 2088 ssiu97: ssiu-51 { 2089 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2090 dma-names = "rx", "tx"; 2091 }; 2092 }; 2093 }; 2094 2095 audma0: dma-controller@ec700000 { 2096 compatible = "renesas,dmac-r8a774a1", 2097 "renesas,rcar-dmac"; 2098 reg = <0 0xec700000 0 0x10000>; 2099 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2116 interrupt-names = "error", 2117 "ch0", "ch1", "ch2", "ch3", 2118 "ch4", "ch5", "ch6", "ch7", 2119 "ch8", "ch9", "ch10", "ch11", 2120 "ch12", "ch13", "ch14", "ch15"; 2121 clocks = <&cpg CPG_MOD 502>; 2122 clock-names = "fck"; 2123 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2124 resets = <&cpg 502>; 2125 #dma-cells = <1>; 2126 dma-channels = <16>; 2127 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 2128 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 2129 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 2130 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 2131 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 2132 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 2133 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 2134 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 2135 }; 2136 2137 audma1: dma-controller@ec720000 { 2138 compatible = "renesas,dmac-r8a774a1", 2139 "renesas,rcar-dmac"; 2140 reg = <0 0xec720000 0 0x10000>; 2141 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2158 interrupt-names = "error", 2159 "ch0", "ch1", "ch2", "ch3", 2160 "ch4", "ch5", "ch6", "ch7", 2161 "ch8", "ch9", "ch10", "ch11", 2162 "ch12", "ch13", "ch14", "ch15"; 2163 clocks = <&cpg CPG_MOD 501>; 2164 clock-names = "fck"; 2165 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2166 resets = <&cpg 501>; 2167 #dma-cells = <1>; 2168 dma-channels = <16>; 2169 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 2170 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 2171 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 2172 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 2173 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 2174 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 2175 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 2176 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 2177 }; 2178 2179 xhci0: usb@ee000000 { 2180 compatible = "renesas,xhci-r8a774a1", 2181 "renesas,rcar-gen3-xhci"; 2182 reg = <0 0xee000000 0 0xc00>; 2183 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2184 clocks = <&cpg CPG_MOD 328>; 2185 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2186 resets = <&cpg 328>; 2187 status = "disabled"; 2188 }; 2189 2190 usb3_peri0: usb@ee020000 { 2191 compatible = "renesas,r8a774a1-usb3-peri", 2192 "renesas,rcar-gen3-usb3-peri"; 2193 reg = <0 0xee020000 0 0x400>; 2194 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2195 clocks = <&cpg CPG_MOD 328>; 2196 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2197 resets = <&cpg 328>; 2198 status = "disabled"; 2199 }; 2200 2201 ohci0: usb@ee080000 { 2202 compatible = "generic-ohci"; 2203 reg = <0 0xee080000 0 0x100>; 2204 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2205 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2206 phys = <&usb2_phy0 1>; 2207 phy-names = "usb"; 2208 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2209 resets = <&cpg 703>, <&cpg 704>; 2210 status = "disabled"; 2211 }; 2212 2213 ohci1: usb@ee0a0000 { 2214 compatible = "generic-ohci"; 2215 reg = <0 0xee0a0000 0 0x100>; 2216 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2217 clocks = <&cpg CPG_MOD 702>; 2218 phys = <&usb2_phy1 1>; 2219 phy-names = "usb"; 2220 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2221 resets = <&cpg 702>; 2222 status = "disabled"; 2223 }; 2224 2225 ehci0: usb@ee080100 { 2226 compatible = "generic-ehci"; 2227 reg = <0 0xee080100 0 0x100>; 2228 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2229 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2230 phys = <&usb2_phy0 2>; 2231 phy-names = "usb"; 2232 companion = <&ohci0>; 2233 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2234 resets = <&cpg 703>, <&cpg 704>; 2235 status = "disabled"; 2236 }; 2237 2238 ehci1: usb@ee0a0100 { 2239 compatible = "generic-ehci"; 2240 reg = <0 0xee0a0100 0 0x100>; 2241 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2242 clocks = <&cpg CPG_MOD 702>; 2243 phys = <&usb2_phy1 2>; 2244 phy-names = "usb"; 2245 companion = <&ohci1>; 2246 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2247 resets = <&cpg 702>; 2248 status = "disabled"; 2249 }; 2250 2251 usb2_phy0: usb-phy@ee080200 { 2252 compatible = "renesas,usb2-phy-r8a774a1", 2253 "renesas,rcar-gen3-usb2-phy"; 2254 reg = <0 0xee080200 0 0x700>; 2255 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2256 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2257 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2258 resets = <&cpg 703>, <&cpg 704>; 2259 #phy-cells = <1>; 2260 status = "disabled"; 2261 }; 2262 2263 usb2_phy1: usb-phy@ee0a0200 { 2264 compatible = "renesas,usb2-phy-r8a774a1", 2265 "renesas,rcar-gen3-usb2-phy"; 2266 reg = <0 0xee0a0200 0 0x700>; 2267 clocks = <&cpg CPG_MOD 702>; 2268 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2269 resets = <&cpg 702>; 2270 #phy-cells = <1>; 2271 status = "disabled"; 2272 }; 2273 2274 sdhi0: mmc@ee100000 { 2275 compatible = "renesas,sdhi-r8a774a1", 2276 "renesas,rcar-gen3-sdhi"; 2277 reg = <0 0xee100000 0 0x2000>; 2278 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2279 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>; 2280 clock-names = "core", "clkh"; 2281 max-frequency = <200000000>; 2282 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2283 resets = <&cpg 314>; 2284 status = "disabled"; 2285 }; 2286 2287 sdhi1: mmc@ee120000 { 2288 compatible = "renesas,sdhi-r8a774a1", 2289 "renesas,rcar-gen3-sdhi"; 2290 reg = <0 0xee120000 0 0x2000>; 2291 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2292 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>; 2293 clock-names = "core", "clkh"; 2294 max-frequency = <200000000>; 2295 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2296 resets = <&cpg 313>; 2297 status = "disabled"; 2298 }; 2299 2300 sdhi2: mmc@ee140000 { 2301 compatible = "renesas,sdhi-r8a774a1", 2302 "renesas,rcar-gen3-sdhi"; 2303 reg = <0 0xee140000 0 0x2000>; 2304 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2305 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>; 2306 clock-names = "core", "clkh"; 2307 max-frequency = <200000000>; 2308 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2309 resets = <&cpg 312>; 2310 status = "disabled"; 2311 }; 2312 2313 sdhi3: mmc@ee160000 { 2314 compatible = "renesas,sdhi-r8a774a1", 2315 "renesas,rcar-gen3-sdhi"; 2316 reg = <0 0xee160000 0 0x2000>; 2317 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2318 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>; 2319 clock-names = "core", "clkh"; 2320 max-frequency = <200000000>; 2321 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2322 resets = <&cpg 311>; 2323 status = "disabled"; 2324 }; 2325 2326 rpc: spi@ee200000 { 2327 compatible = "renesas,r8a774a1-rpc-if", 2328 "renesas,rcar-gen3-rpc-if"; 2329 reg = <0 0xee200000 0 0x200>, 2330 <0 0x08000000 0 0x4000000>, 2331 <0 0xee208000 0 0x100>; 2332 reg-names = "regs", "dirmap", "wbuf"; 2333 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 2334 clocks = <&cpg CPG_MOD 917>; 2335 clock-names = "rpc"; 2336 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2337 resets = <&cpg 917>; 2338 #address-cells = <1>; 2339 #size-cells = <0>; 2340 status = "disabled"; 2341 }; 2342 2343 gic: interrupt-controller@f1010000 { 2344 compatible = "arm,gic-400"; 2345 #interrupt-cells = <3>; 2346 #address-cells = <0>; 2347 interrupt-controller; 2348 reg = <0x0 0xf1010000 0 0x1000>, 2349 <0x0 0xf1020000 0 0x20000>, 2350 <0x0 0xf1040000 0 0x20000>, 2351 <0x0 0xf1060000 0 0x20000>; 2352 interrupts = <GIC_PPI 9 2353 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 2354 clocks = <&cpg CPG_MOD 408>; 2355 clock-names = "clk"; 2356 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2357 resets = <&cpg 408>; 2358 }; 2359 2360 pciec0: pcie@fe000000 { 2361 compatible = "renesas,pcie-r8a774a1", 2362 "renesas,pcie-rcar-gen3"; 2363 reg = <0 0xfe000000 0 0x80000>; 2364 #address-cells = <3>; 2365 #size-cells = <2>; 2366 bus-range = <0x00 0xff>; 2367 device_type = "pci"; 2368 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2369 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2370 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2371 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2372 /* Map all possible DDR as inbound ranges */ 2373 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2374 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2375 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2376 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2377 #interrupt-cells = <1>; 2378 interrupt-map-mask = <0 0 0 0>; 2379 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2380 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2381 clock-names = "pcie", "pcie_bus"; 2382 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2383 resets = <&cpg 319>; 2384 status = "disabled"; 2385 }; 2386 2387 pciec1: pcie@ee800000 { 2388 compatible = "renesas,pcie-r8a774a1", 2389 "renesas,pcie-rcar-gen3"; 2390 reg = <0 0xee800000 0 0x80000>; 2391 #address-cells = <3>; 2392 #size-cells = <2>; 2393 bus-range = <0x00 0xff>; 2394 device_type = "pci"; 2395 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2396 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2397 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2398 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2399 /* Map all possible DDR as inbound ranges */ 2400 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2401 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2404 #interrupt-cells = <1>; 2405 interrupt-map-mask = <0 0 0 0>; 2406 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2407 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2408 clock-names = "pcie", "pcie_bus"; 2409 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2410 resets = <&cpg 318>; 2411 status = "disabled"; 2412 }; 2413 2414 pciec0_ep: pcie-ep@fe000000 { 2415 compatible = "renesas,r8a774a1-pcie-ep", 2416 "renesas,rcar-gen3-pcie-ep"; 2417 reg = <0x0 0xfe000000 0 0x80000>, 2418 <0x0 0xfe100000 0 0x100000>, 2419 <0x0 0xfe200000 0 0x200000>, 2420 <0x0 0x30000000 0 0x8000000>, 2421 <0x0 0x38000000 0 0x8000000>; 2422 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2423 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2424 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2425 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2426 clocks = <&cpg CPG_MOD 319>; 2427 clock-names = "pcie"; 2428 resets = <&cpg 319>; 2429 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2430 status = "disabled"; 2431 }; 2432 2433 pciec1_ep: pcie-ep@ee800000 { 2434 compatible = "renesas,r8a774a1-pcie-ep", 2435 "renesas,rcar-gen3-pcie-ep"; 2436 reg = <0x0 0xee800000 0 0x80000>, 2437 <0x0 0xee900000 0 0x100000>, 2438 <0x0 0xeea00000 0 0x200000>, 2439 <0x0 0xc0000000 0 0x8000000>, 2440 <0x0 0xc8000000 0 0x8000000>; 2441 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2442 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2443 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2445 clocks = <&cpg CPG_MOD 318>; 2446 clock-names = "pcie"; 2447 resets = <&cpg 318>; 2448 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2449 status = "disabled"; 2450 }; 2451 2452 fdp1@fe940000 { 2453 compatible = "renesas,fdp1"; 2454 reg = <0 0xfe940000 0 0x2400>; 2455 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2456 clocks = <&cpg CPG_MOD 119>; 2457 power-domains = <&sysc R8A774A1_PD_A3VC>; 2458 resets = <&cpg 119>; 2459 renesas,fcp = <&fcpf0>; 2460 }; 2461 2462 fcpf0: fcp@fe950000 { 2463 compatible = "renesas,fcpf"; 2464 reg = <0 0xfe950000 0 0x200>; 2465 clocks = <&cpg CPG_MOD 615>; 2466 power-domains = <&sysc R8A774A1_PD_A3VC>; 2467 resets = <&cpg 615>; 2468 }; 2469 2470 fcpvb0: fcp@fe96f000 { 2471 compatible = "renesas,fcpv"; 2472 reg = <0 0xfe96f000 0 0x200>; 2473 clocks = <&cpg CPG_MOD 607>; 2474 power-domains = <&sysc R8A774A1_PD_A3VC>; 2475 resets = <&cpg 607>; 2476 }; 2477 2478 fcpvd0: fcp@fea27000 { 2479 compatible = "renesas,fcpv"; 2480 reg = <0 0xfea27000 0 0x200>; 2481 clocks = <&cpg CPG_MOD 603>; 2482 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2483 resets = <&cpg 603>; 2484 iommus = <&ipmmu_vi0 8>; 2485 }; 2486 2487 fcpvd1: fcp@fea2f000 { 2488 compatible = "renesas,fcpv"; 2489 reg = <0 0xfea2f000 0 0x200>; 2490 clocks = <&cpg CPG_MOD 602>; 2491 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2492 resets = <&cpg 602>; 2493 iommus = <&ipmmu_vi0 9>; 2494 }; 2495 2496 fcpvd2: fcp@fea37000 { 2497 compatible = "renesas,fcpv"; 2498 reg = <0 0xfea37000 0 0x200>; 2499 clocks = <&cpg CPG_MOD 601>; 2500 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2501 resets = <&cpg 601>; 2502 iommus = <&ipmmu_vi0 10>; 2503 }; 2504 2505 fcpvi0: fcp@fe9af000 { 2506 compatible = "renesas,fcpv"; 2507 reg = <0 0xfe9af000 0 0x200>; 2508 clocks = <&cpg CPG_MOD 611>; 2509 power-domains = <&sysc R8A774A1_PD_A3VC>; 2510 resets = <&cpg 611>; 2511 iommus = <&ipmmu_vc0 19>; 2512 }; 2513 2514 vspb: vsp@fe960000 { 2515 compatible = "renesas,vsp2"; 2516 reg = <0 0xfe960000 0 0x8000>; 2517 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2518 clocks = <&cpg CPG_MOD 626>; 2519 power-domains = <&sysc R8A774A1_PD_A3VC>; 2520 resets = <&cpg 626>; 2521 2522 renesas,fcp = <&fcpvb0>; 2523 }; 2524 2525 vspd0: vsp@fea20000 { 2526 compatible = "renesas,vsp2"; 2527 reg = <0 0xfea20000 0 0x5000>; 2528 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2529 clocks = <&cpg CPG_MOD 623>; 2530 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2531 resets = <&cpg 623>; 2532 2533 renesas,fcp = <&fcpvd0>; 2534 }; 2535 2536 vspd1: vsp@fea28000 { 2537 compatible = "renesas,vsp2"; 2538 reg = <0 0xfea28000 0 0x5000>; 2539 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2540 clocks = <&cpg CPG_MOD 622>; 2541 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2542 resets = <&cpg 622>; 2543 2544 renesas,fcp = <&fcpvd1>; 2545 }; 2546 2547 vspd2: vsp@fea30000 { 2548 compatible = "renesas,vsp2"; 2549 reg = <0 0xfea30000 0 0x5000>; 2550 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2551 clocks = <&cpg CPG_MOD 621>; 2552 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2553 resets = <&cpg 621>; 2554 2555 renesas,fcp = <&fcpvd2>; 2556 }; 2557 2558 vspi0: vsp@fe9a0000 { 2559 compatible = "renesas,vsp2"; 2560 reg = <0 0xfe9a0000 0 0x8000>; 2561 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2562 clocks = <&cpg CPG_MOD 631>; 2563 power-domains = <&sysc R8A774A1_PD_A3VC>; 2564 resets = <&cpg 631>; 2565 2566 renesas,fcp = <&fcpvi0>; 2567 }; 2568 2569 csi20: csi2@fea80000 { 2570 compatible = "renesas,r8a774a1-csi2"; 2571 reg = <0 0xfea80000 0 0x10000>; 2572 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2573 clocks = <&cpg CPG_MOD 714>; 2574 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2575 resets = <&cpg 714>; 2576 status = "disabled"; 2577 2578 ports { 2579 #address-cells = <1>; 2580 #size-cells = <0>; 2581 2582 port@0 { 2583 reg = <0>; 2584 }; 2585 2586 port@1 { 2587 #address-cells = <1>; 2588 #size-cells = <0>; 2589 2590 reg = <1>; 2591 2592 csi20vin0: endpoint@0 { 2593 reg = <0>; 2594 remote-endpoint = <&vin0csi20>; 2595 }; 2596 csi20vin1: endpoint@1 { 2597 reg = <1>; 2598 remote-endpoint = <&vin1csi20>; 2599 }; 2600 csi20vin2: endpoint@2 { 2601 reg = <2>; 2602 remote-endpoint = <&vin2csi20>; 2603 }; 2604 csi20vin3: endpoint@3 { 2605 reg = <3>; 2606 remote-endpoint = <&vin3csi20>; 2607 }; 2608 csi20vin4: endpoint@4 { 2609 reg = <4>; 2610 remote-endpoint = <&vin4csi20>; 2611 }; 2612 csi20vin5: endpoint@5 { 2613 reg = <5>; 2614 remote-endpoint = <&vin5csi20>; 2615 }; 2616 csi20vin6: endpoint@6 { 2617 reg = <6>; 2618 remote-endpoint = <&vin6csi20>; 2619 }; 2620 csi20vin7: endpoint@7 { 2621 reg = <7>; 2622 remote-endpoint = <&vin7csi20>; 2623 }; 2624 }; 2625 }; 2626 }; 2627 2628 csi40: csi2@feaa0000 { 2629 compatible = "renesas,r8a774a1-csi2"; 2630 reg = <0 0xfeaa0000 0 0x10000>; 2631 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2632 clocks = <&cpg CPG_MOD 716>; 2633 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2634 resets = <&cpg 716>; 2635 status = "disabled"; 2636 2637 ports { 2638 #address-cells = <1>; 2639 #size-cells = <0>; 2640 2641 port@0 { 2642 reg = <0>; 2643 }; 2644 2645 port@1 { 2646 #address-cells = <1>; 2647 #size-cells = <0>; 2648 2649 reg = <1>; 2650 2651 csi40vin0: endpoint@0 { 2652 reg = <0>; 2653 remote-endpoint = <&vin0csi40>; 2654 }; 2655 csi40vin1: endpoint@1 { 2656 reg = <1>; 2657 remote-endpoint = <&vin1csi40>; 2658 }; 2659 csi40vin2: endpoint@2 { 2660 reg = <2>; 2661 remote-endpoint = <&vin2csi40>; 2662 }; 2663 csi40vin3: endpoint@3 { 2664 reg = <3>; 2665 remote-endpoint = <&vin3csi40>; 2666 }; 2667 csi40vin4: endpoint@4 { 2668 reg = <4>; 2669 remote-endpoint = <&vin4csi40>; 2670 }; 2671 csi40vin5: endpoint@5 { 2672 reg = <5>; 2673 remote-endpoint = <&vin5csi40>; 2674 }; 2675 csi40vin6: endpoint@6 { 2676 reg = <6>; 2677 remote-endpoint = <&vin6csi40>; 2678 }; 2679 csi40vin7: endpoint@7 { 2680 reg = <7>; 2681 remote-endpoint = <&vin7csi40>; 2682 }; 2683 }; 2684 2685 }; 2686 }; 2687 2688 hdmi0: hdmi@fead0000 { 2689 compatible = "renesas,r8a774a1-hdmi", 2690 "renesas,rcar-gen3-hdmi"; 2691 reg = <0 0xfead0000 0 0x10000>; 2692 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2693 clocks = <&cpg CPG_MOD 729>, 2694 <&cpg CPG_CORE R8A774A1_CLK_HDMI>; 2695 clock-names = "iahb", "isfr"; 2696 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2697 resets = <&cpg 729>; 2698 status = "disabled"; 2699 2700 ports { 2701 #address-cells = <1>; 2702 #size-cells = <0>; 2703 port@0 { 2704 reg = <0>; 2705 dw_hdmi0_in: endpoint { 2706 remote-endpoint = <&du_out_hdmi0>; 2707 }; 2708 }; 2709 port@1 { 2710 reg = <1>; 2711 }; 2712 port@2 { 2713 /* HDMI sound */ 2714 reg = <2>; 2715 }; 2716 }; 2717 }; 2718 2719 du: display@feb00000 { 2720 compatible = "renesas,du-r8a774a1"; 2721 reg = <0 0xfeb00000 0 0x70000>; 2722 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2723 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2724 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2725 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 2726 <&cpg CPG_MOD 722>; 2727 clock-names = "du.0", "du.1", "du.2"; 2728 resets = <&cpg 724>, <&cpg 722>; 2729 reset-names = "du.0", "du.2"; 2730 status = "disabled"; 2731 2732 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; 2733 2734 ports { 2735 #address-cells = <1>; 2736 #size-cells = <0>; 2737 2738 port@0 { 2739 reg = <0>; 2740 du_out_rgb: endpoint { 2741 }; 2742 }; 2743 port@1 { 2744 reg = <1>; 2745 du_out_hdmi0: endpoint { 2746 remote-endpoint = <&dw_hdmi0_in>; 2747 }; 2748 }; 2749 port@2 { 2750 reg = <2>; 2751 du_out_lvds0: endpoint { 2752 remote-endpoint = <&lvds0_in>; 2753 }; 2754 }; 2755 }; 2756 }; 2757 2758 lvds0: lvds@feb90000 { 2759 compatible = "renesas,r8a774a1-lvds"; 2760 reg = <0 0xfeb90000 0 0x14>; 2761 clocks = <&cpg CPG_MOD 727>; 2762 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2763 resets = <&cpg 727>; 2764 status = "disabled"; 2765 2766 ports { 2767 #address-cells = <1>; 2768 #size-cells = <0>; 2769 2770 port@0 { 2771 reg = <0>; 2772 lvds0_in: endpoint { 2773 remote-endpoint = <&du_out_lvds0>; 2774 }; 2775 }; 2776 port@1 { 2777 reg = <1>; 2778 lvds0_out: endpoint { 2779 }; 2780 }; 2781 }; 2782 }; 2783 2784 prr: chipid@fff00044 { 2785 compatible = "renesas,prr"; 2786 reg = <0 0xfff00044 0 4>; 2787 }; 2788 }; 2789 2790 thermal-zones { 2791 sensor1_thermal: sensor1-thermal { 2792 polling-delay-passive = <250>; 2793 polling-delay = <1000>; 2794 thermal-sensors = <&tsc 0>; 2795 sustainable-power = <3874>; 2796 2797 trips { 2798 sensor1_crit: sensor1-crit { 2799 temperature = <120000>; 2800 hysteresis = <1000>; 2801 type = "critical"; 2802 }; 2803 }; 2804 }; 2805 2806 sensor2_thermal: sensor2-thermal { 2807 polling-delay-passive = <250>; 2808 polling-delay = <1000>; 2809 thermal-sensors = <&tsc 1>; 2810 sustainable-power = <3874>; 2811 2812 trips { 2813 sensor2_crit: sensor2-crit { 2814 temperature = <120000>; 2815 hysteresis = <1000>; 2816 type = "critical"; 2817 }; 2818 }; 2819 }; 2820 2821 sensor3_thermal: sensor3-thermal { 2822 polling-delay-passive = <250>; 2823 polling-delay = <1000>; 2824 thermal-sensors = <&tsc 2>; 2825 sustainable-power = <3874>; 2826 2827 cooling-maps { 2828 map0 { 2829 trip = <&target>; 2830 cooling-device = <&a57_0 0 2>; 2831 contribution = <1024>; 2832 }; 2833 map1 { 2834 trip = <&target>; 2835 cooling-device = <&a53_0 0 2>; 2836 contribution = <1024>; 2837 }; 2838 }; 2839 trips { 2840 target: trip-point1 { 2841 temperature = <100000>; 2842 hysteresis = <1000>; 2843 type = "passive"; 2844 }; 2845 2846 sensor3_crit: sensor3-crit { 2847 temperature = <120000>; 2848 hysteresis = <1000>; 2849 type = "critical"; 2850 }; 2851 }; 2852 }; 2853 }; 2854 2855 timer { 2856 compatible = "arm,armv8-timer"; 2857 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2858 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2859 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2860 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2861 }; 2862 2863 /* External USB clocks - can be overridden by the board */ 2864 usb3s0_clk: usb3s0 { 2865 compatible = "fixed-clock"; 2866 #clock-cells = <0>; 2867 clock-frequency = <0>; 2868 }; 2869 2870 usb_extal_clk: usb_extal { 2871 compatible = "fixed-clock"; 2872 #clock-cells = <0>; 2873 clock-frequency = <0>; 2874 }; 2875}; 2876