1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774a1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774a1-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a774a1"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 /* 21 * The external audio clocks are configured as 0 Hz fixed frequency 22 * clocks by default. 23 * Boards that provide audio clocks should override them. 24 */ 25 audio_clk_a: audio_clk_a { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <0>; 29 }; 30 31 audio_clk_b: audio_clk_b { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 audio_clk_c: audio_clk_c { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <0>; 41 }; 42 43 /* External CAN clock - to be overridden by boards that provide it */ 44 can_clk: can { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 clock-frequency = <0>; 48 }; 49 50 cluster0_opp: opp-table-0 { 51 compatible = "operating-points-v2"; 52 opp-shared; 53 54 opp-500000000 { 55 opp-hz = /bits/ 64 <500000000>; 56 opp-microvolt = <820000>; 57 clock-latency-ns = <300000>; 58 }; 59 opp-1000000000 { 60 opp-hz = /bits/ 64 <1000000000>; 61 opp-microvolt = <820000>; 62 clock-latency-ns = <300000>; 63 }; 64 opp-1500000000 { 65 opp-hz = /bits/ 64 <1500000000>; 66 opp-microvolt = <820000>; 67 clock-latency-ns = <300000>; 68 opp-suspend; 69 }; 70 }; 71 72 cluster1_opp: opp-table-1 { 73 compatible = "operating-points-v2"; 74 opp-shared; 75 76 opp-800000000 { 77 opp-hz = /bits/ 64 <800000000>; 78 opp-microvolt = <820000>; 79 clock-latency-ns = <300000>; 80 }; 81 opp-1000000000 { 82 opp-hz = /bits/ 64 <1000000000>; 83 opp-microvolt = <820000>; 84 clock-latency-ns = <300000>; 85 }; 86 opp-1200000000 { 87 opp-hz = /bits/ 64 <1200000000>; 88 opp-microvolt = <820000>; 89 clock-latency-ns = <300000>; 90 }; 91 }; 92 93 cpus { 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 cpu-map { 98 cluster0 { 99 core0 { 100 cpu = <&a57_0>; 101 }; 102 core1 { 103 cpu = <&a57_1>; 104 }; 105 }; 106 107 cluster1 { 108 core0 { 109 cpu = <&a53_0>; 110 }; 111 core1 { 112 cpu = <&a53_1>; 113 }; 114 core2 { 115 cpu = <&a53_2>; 116 }; 117 core3 { 118 cpu = <&a53_3>; 119 }; 120 }; 121 }; 122 123 a57_0: cpu@0 { 124 compatible = "arm,cortex-a57"; 125 reg = <0x0>; 126 device_type = "cpu"; 127 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; 128 next-level-cache = <&L2_CA57>; 129 enable-method = "psci"; 130 dynamic-power-coefficient = <854>; 131 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 132 operating-points-v2 = <&cluster0_opp>; 133 capacity-dmips-mhz = <1024>; 134 #cooling-cells = <2>; 135 }; 136 137 a57_1: cpu@1 { 138 compatible = "arm,cortex-a57"; 139 reg = <0x1>; 140 device_type = "cpu"; 141 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; 142 next-level-cache = <&L2_CA57>; 143 enable-method = "psci"; 144 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 145 operating-points-v2 = <&cluster0_opp>; 146 capacity-dmips-mhz = <1024>; 147 #cooling-cells = <2>; 148 }; 149 150 a53_0: cpu@100 { 151 compatible = "arm,cortex-a53"; 152 reg = <0x100>; 153 device_type = "cpu"; 154 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; 155 next-level-cache = <&L2_CA53>; 156 enable-method = "psci"; 157 #cooling-cells = <2>; 158 dynamic-power-coefficient = <277>; 159 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 160 operating-points-v2 = <&cluster1_opp>; 161 capacity-dmips-mhz = <560>; 162 }; 163 164 a53_1: cpu@101 { 165 compatible = "arm,cortex-a53"; 166 reg = <0x101>; 167 device_type = "cpu"; 168 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; 169 next-level-cache = <&L2_CA53>; 170 enable-method = "psci"; 171 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 172 operating-points-v2 = <&cluster1_opp>; 173 capacity-dmips-mhz = <560>; 174 }; 175 176 a53_2: cpu@102 { 177 compatible = "arm,cortex-a53"; 178 reg = <0x102>; 179 device_type = "cpu"; 180 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; 181 next-level-cache = <&L2_CA53>; 182 enable-method = "psci"; 183 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 184 operating-points-v2 = <&cluster1_opp>; 185 capacity-dmips-mhz = <560>; 186 }; 187 188 a53_3: cpu@103 { 189 compatible = "arm,cortex-a53"; 190 reg = <0x103>; 191 device_type = "cpu"; 192 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; 193 next-level-cache = <&L2_CA53>; 194 enable-method = "psci"; 195 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 196 operating-points-v2 = <&cluster1_opp>; 197 capacity-dmips-mhz = <560>; 198 }; 199 200 L2_CA57: cache-controller-0 { 201 compatible = "cache"; 202 power-domains = <&sysc R8A774A1_PD_CA57_SCU>; 203 cache-unified; 204 cache-level = <2>; 205 }; 206 207 L2_CA53: cache-controller-1 { 208 compatible = "cache"; 209 power-domains = <&sysc R8A774A1_PD_CA53_SCU>; 210 cache-unified; 211 cache-level = <2>; 212 }; 213 }; 214 215 extal_clk: extal { 216 compatible = "fixed-clock"; 217 #clock-cells = <0>; 218 /* This value must be overridden by the board */ 219 clock-frequency = <0>; 220 }; 221 222 extalr_clk: extalr { 223 compatible = "fixed-clock"; 224 #clock-cells = <0>; 225 /* This value must be overridden by the board */ 226 clock-frequency = <0>; 227 }; 228 229 /* External PCIe clock - can be overridden by the board */ 230 pcie_bus_clk: pcie_bus { 231 compatible = "fixed-clock"; 232 #clock-cells = <0>; 233 clock-frequency = <0>; 234 }; 235 236 pmu_a53 { 237 compatible = "arm,cortex-a53-pmu"; 238 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 239 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 240 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 241 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 242 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 243 }; 244 245 pmu_a57 { 246 compatible = "arm,cortex-a57-pmu"; 247 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 248 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 249 interrupt-affinity = <&a57_0>, <&a57_1>; 250 }; 251 252 psci { 253 compatible = "arm,psci-1.0", "arm,psci-0.2"; 254 method = "smc"; 255 }; 256 257 /* External SCIF clock - to be overridden by boards that provide it */ 258 scif_clk: scif { 259 compatible = "fixed-clock"; 260 #clock-cells = <0>; 261 clock-frequency = <0>; 262 }; 263 264 soc { 265 compatible = "simple-bus"; 266 interrupt-parent = <&gic>; 267 #address-cells = <2>; 268 #size-cells = <2>; 269 ranges; 270 271 rwdt: watchdog@e6020000 { 272 compatible = "renesas,r8a774a1-wdt", 273 "renesas,rcar-gen3-wdt"; 274 reg = <0 0xe6020000 0 0x0c>; 275 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&cpg CPG_MOD 402>; 277 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 278 resets = <&cpg 402>; 279 status = "disabled"; 280 }; 281 282 gpio0: gpio@e6050000 { 283 compatible = "renesas,gpio-r8a774a1", 284 "renesas,rcar-gen3-gpio"; 285 reg = <0 0xe6050000 0 0x50>; 286 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 287 #gpio-cells = <2>; 288 gpio-controller; 289 gpio-ranges = <&pfc 0 0 16>; 290 #interrupt-cells = <2>; 291 interrupt-controller; 292 clocks = <&cpg CPG_MOD 912>; 293 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 294 resets = <&cpg 912>; 295 }; 296 297 gpio1: gpio@e6051000 { 298 compatible = "renesas,gpio-r8a774a1", 299 "renesas,rcar-gen3-gpio"; 300 reg = <0 0xe6051000 0 0x50>; 301 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 302 #gpio-cells = <2>; 303 gpio-controller; 304 gpio-ranges = <&pfc 0 32 29>; 305 #interrupt-cells = <2>; 306 interrupt-controller; 307 clocks = <&cpg CPG_MOD 911>; 308 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 309 resets = <&cpg 911>; 310 }; 311 312 gpio2: gpio@e6052000 { 313 compatible = "renesas,gpio-r8a774a1", 314 "renesas,rcar-gen3-gpio"; 315 reg = <0 0xe6052000 0 0x50>; 316 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 317 #gpio-cells = <2>; 318 gpio-controller; 319 gpio-ranges = <&pfc 0 64 15>; 320 #interrupt-cells = <2>; 321 interrupt-controller; 322 clocks = <&cpg CPG_MOD 910>; 323 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 324 resets = <&cpg 910>; 325 }; 326 327 gpio3: gpio@e6053000 { 328 compatible = "renesas,gpio-r8a774a1", 329 "renesas,rcar-gen3-gpio"; 330 reg = <0 0xe6053000 0 0x50>; 331 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 332 #gpio-cells = <2>; 333 gpio-controller; 334 gpio-ranges = <&pfc 0 96 16>; 335 #interrupt-cells = <2>; 336 interrupt-controller; 337 clocks = <&cpg CPG_MOD 909>; 338 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 339 resets = <&cpg 909>; 340 }; 341 342 gpio4: gpio@e6054000 { 343 compatible = "renesas,gpio-r8a774a1", 344 "renesas,rcar-gen3-gpio"; 345 reg = <0 0xe6054000 0 0x50>; 346 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 347 #gpio-cells = <2>; 348 gpio-controller; 349 gpio-ranges = <&pfc 0 128 18>; 350 #interrupt-cells = <2>; 351 interrupt-controller; 352 clocks = <&cpg CPG_MOD 908>; 353 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 354 resets = <&cpg 908>; 355 }; 356 357 gpio5: gpio@e6055000 { 358 compatible = "renesas,gpio-r8a774a1", 359 "renesas,rcar-gen3-gpio"; 360 reg = <0 0xe6055000 0 0x50>; 361 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 362 #gpio-cells = <2>; 363 gpio-controller; 364 gpio-ranges = <&pfc 0 160 26>; 365 #interrupt-cells = <2>; 366 interrupt-controller; 367 clocks = <&cpg CPG_MOD 907>; 368 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 369 resets = <&cpg 907>; 370 }; 371 372 gpio6: gpio@e6055400 { 373 compatible = "renesas,gpio-r8a774a1", 374 "renesas,rcar-gen3-gpio"; 375 reg = <0 0xe6055400 0 0x50>; 376 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 377 #gpio-cells = <2>; 378 gpio-controller; 379 gpio-ranges = <&pfc 0 192 32>; 380 #interrupt-cells = <2>; 381 interrupt-controller; 382 clocks = <&cpg CPG_MOD 906>; 383 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 384 resets = <&cpg 906>; 385 }; 386 387 gpio7: gpio@e6055800 { 388 compatible = "renesas,gpio-r8a774a1", 389 "renesas,rcar-gen3-gpio"; 390 reg = <0 0xe6055800 0 0x50>; 391 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 392 #gpio-cells = <2>; 393 gpio-controller; 394 gpio-ranges = <&pfc 0 224 4>; 395 #interrupt-cells = <2>; 396 interrupt-controller; 397 clocks = <&cpg CPG_MOD 905>; 398 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 399 resets = <&cpg 905>; 400 }; 401 402 pfc: pinctrl@e6060000 { 403 compatible = "renesas,pfc-r8a774a1"; 404 reg = <0 0xe6060000 0 0x50c>; 405 }; 406 407 cmt0: timer@e60f0000 { 408 compatible = "renesas,r8a774a1-cmt0", 409 "renesas,rcar-gen3-cmt0"; 410 reg = <0 0xe60f0000 0 0x1004>; 411 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&cpg CPG_MOD 303>; 414 clock-names = "fck"; 415 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 416 resets = <&cpg 303>; 417 status = "disabled"; 418 }; 419 420 cmt1: timer@e6130000 { 421 compatible = "renesas,r8a774a1-cmt1", 422 "renesas,rcar-gen3-cmt1"; 423 reg = <0 0xe6130000 0 0x1004>; 424 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&cpg CPG_MOD 302>; 433 clock-names = "fck"; 434 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 435 resets = <&cpg 302>; 436 status = "disabled"; 437 }; 438 439 cmt2: timer@e6140000 { 440 compatible = "renesas,r8a774a1-cmt1", 441 "renesas,rcar-gen3-cmt1"; 442 reg = <0 0xe6140000 0 0x1004>; 443 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&cpg CPG_MOD 301>; 452 clock-names = "fck"; 453 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 454 resets = <&cpg 301>; 455 status = "disabled"; 456 }; 457 458 cmt3: timer@e6148000 { 459 compatible = "renesas,r8a774a1-cmt1", 460 "renesas,rcar-gen3-cmt1"; 461 reg = <0 0xe6148000 0 0x1004>; 462 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&cpg CPG_MOD 300>; 471 clock-names = "fck"; 472 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 473 resets = <&cpg 300>; 474 status = "disabled"; 475 }; 476 477 cpg: clock-controller@e6150000 { 478 compatible = "renesas,r8a774a1-cpg-mssr"; 479 reg = <0 0xe6150000 0 0x0bb0>; 480 clocks = <&extal_clk>, <&extalr_clk>; 481 clock-names = "extal", "extalr"; 482 #clock-cells = <2>; 483 #power-domain-cells = <0>; 484 #reset-cells = <1>; 485 }; 486 487 rst: reset-controller@e6160000 { 488 compatible = "renesas,r8a774a1-rst"; 489 reg = <0 0xe6160000 0 0x018c>; 490 }; 491 492 sysc: system-controller@e6180000 { 493 compatible = "renesas,r8a774a1-sysc"; 494 reg = <0 0xe6180000 0 0x0400>; 495 #power-domain-cells = <1>; 496 }; 497 498 tsc: thermal@e6198000 { 499 compatible = "renesas,r8a774a1-thermal"; 500 reg = <0 0xe6198000 0 0x100>, 501 <0 0xe61a0000 0 0x100>, 502 <0 0xe61a8000 0 0x100>; 503 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&cpg CPG_MOD 522>; 507 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 508 resets = <&cpg 522>; 509 #thermal-sensor-cells = <1>; 510 }; 511 512 intc_ex: interrupt-controller@e61c0000 { 513 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; 514 #interrupt-cells = <2>; 515 interrupt-controller; 516 reg = <0 0xe61c0000 0 0x200>; 517 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&cpg CPG_MOD 407>; 524 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 525 resets = <&cpg 407>; 526 }; 527 528 tmu0: timer@e61e0000 { 529 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 530 reg = <0 0xe61e0000 0 0x30>; 531 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&cpg CPG_MOD 125>; 535 clock-names = "fck"; 536 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 537 resets = <&cpg 125>; 538 status = "disabled"; 539 }; 540 541 tmu1: timer@e6fc0000 { 542 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 543 reg = <0 0xe6fc0000 0 0x30>; 544 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&cpg CPG_MOD 124>; 548 clock-names = "fck"; 549 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 550 resets = <&cpg 124>; 551 status = "disabled"; 552 }; 553 554 tmu2: timer@e6fd0000 { 555 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 556 reg = <0 0xe6fd0000 0 0x30>; 557 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&cpg CPG_MOD 123>; 561 clock-names = "fck"; 562 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 563 resets = <&cpg 123>; 564 status = "disabled"; 565 }; 566 567 tmu3: timer@e6fe0000 { 568 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 569 reg = <0 0xe6fe0000 0 0x30>; 570 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&cpg CPG_MOD 122>; 574 clock-names = "fck"; 575 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 576 resets = <&cpg 122>; 577 status = "disabled"; 578 }; 579 580 tmu4: timer@ffc00000 { 581 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 582 reg = <0 0xffc00000 0 0x30>; 583 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&cpg CPG_MOD 121>; 587 clock-names = "fck"; 588 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 589 resets = <&cpg 121>; 590 status = "disabled"; 591 }; 592 593 i2c0: i2c@e6500000 { 594 #address-cells = <1>; 595 #size-cells = <0>; 596 compatible = "renesas,i2c-r8a774a1", 597 "renesas,rcar-gen3-i2c"; 598 reg = <0 0xe6500000 0 0x40>; 599 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&cpg CPG_MOD 931>; 601 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 602 resets = <&cpg 931>; 603 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 604 <&dmac2 0x91>, <&dmac2 0x90>; 605 dma-names = "tx", "rx", "tx", "rx"; 606 i2c-scl-internal-delay-ns = <110>; 607 status = "disabled"; 608 }; 609 610 i2c1: i2c@e6508000 { 611 #address-cells = <1>; 612 #size-cells = <0>; 613 compatible = "renesas,i2c-r8a774a1", 614 "renesas,rcar-gen3-i2c"; 615 reg = <0 0xe6508000 0 0x40>; 616 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&cpg CPG_MOD 930>; 618 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 619 resets = <&cpg 930>; 620 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 621 <&dmac2 0x93>, <&dmac2 0x92>; 622 dma-names = "tx", "rx", "tx", "rx"; 623 i2c-scl-internal-delay-ns = <6>; 624 status = "disabled"; 625 }; 626 627 i2c2: i2c@e6510000 { 628 #address-cells = <1>; 629 #size-cells = <0>; 630 compatible = "renesas,i2c-r8a774a1", 631 "renesas,rcar-gen3-i2c"; 632 reg = <0 0xe6510000 0 0x40>; 633 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&cpg CPG_MOD 929>; 635 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 636 resets = <&cpg 929>; 637 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 638 <&dmac2 0x95>, <&dmac2 0x94>; 639 dma-names = "tx", "rx", "tx", "rx"; 640 i2c-scl-internal-delay-ns = <6>; 641 status = "disabled"; 642 }; 643 644 i2c3: i2c@e66d0000 { 645 #address-cells = <1>; 646 #size-cells = <0>; 647 compatible = "renesas,i2c-r8a774a1", 648 "renesas,rcar-gen3-i2c"; 649 reg = <0 0xe66d0000 0 0x40>; 650 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&cpg CPG_MOD 928>; 652 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 653 resets = <&cpg 928>; 654 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 655 dma-names = "tx", "rx"; 656 i2c-scl-internal-delay-ns = <110>; 657 status = "disabled"; 658 }; 659 660 i2c4: i2c@e66d8000 { 661 #address-cells = <1>; 662 #size-cells = <0>; 663 compatible = "renesas,i2c-r8a774a1", 664 "renesas,rcar-gen3-i2c"; 665 reg = <0 0xe66d8000 0 0x40>; 666 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&cpg CPG_MOD 927>; 668 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 669 resets = <&cpg 927>; 670 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 671 dma-names = "tx", "rx"; 672 i2c-scl-internal-delay-ns = <110>; 673 status = "disabled"; 674 }; 675 676 i2c5: i2c@e66e0000 { 677 #address-cells = <1>; 678 #size-cells = <0>; 679 compatible = "renesas,i2c-r8a774a1", 680 "renesas,rcar-gen3-i2c"; 681 reg = <0 0xe66e0000 0 0x40>; 682 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&cpg CPG_MOD 919>; 684 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 685 resets = <&cpg 919>; 686 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 687 dma-names = "tx", "rx"; 688 i2c-scl-internal-delay-ns = <110>; 689 status = "disabled"; 690 }; 691 692 i2c6: i2c@e66e8000 { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 compatible = "renesas,i2c-r8a774a1", 696 "renesas,rcar-gen3-i2c"; 697 reg = <0 0xe66e8000 0 0x40>; 698 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&cpg CPG_MOD 918>; 700 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 701 resets = <&cpg 918>; 702 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 703 dma-names = "tx", "rx"; 704 i2c-scl-internal-delay-ns = <6>; 705 status = "disabled"; 706 }; 707 708 iic_pmic: i2c@e60b0000 { 709 #address-cells = <1>; 710 #size-cells = <0>; 711 compatible = "renesas,iic-r8a774a1", 712 "renesas,rcar-gen3-iic", 713 "renesas,rmobile-iic"; 714 reg = <0 0xe60b0000 0 0x425>; 715 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&cpg CPG_MOD 926>; 717 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 718 resets = <&cpg 926>; 719 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 720 dma-names = "tx", "rx"; 721 status = "disabled"; 722 }; 723 724 hscif0: serial@e6540000 { 725 compatible = "renesas,hscif-r8a774a1", 726 "renesas,rcar-gen3-hscif", 727 "renesas,hscif"; 728 reg = <0 0xe6540000 0 0x60>; 729 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&cpg CPG_MOD 520>, 731 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 732 <&scif_clk>; 733 clock-names = "fck", "brg_int", "scif_clk"; 734 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 735 <&dmac2 0x31>, <&dmac2 0x30>; 736 dma-names = "tx", "rx", "tx", "rx"; 737 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 738 resets = <&cpg 520>; 739 status = "disabled"; 740 }; 741 742 hscif1: serial@e6550000 { 743 compatible = "renesas,hscif-r8a774a1", 744 "renesas,rcar-gen3-hscif", 745 "renesas,hscif"; 746 reg = <0 0xe6550000 0 0x60>; 747 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&cpg CPG_MOD 519>, 749 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 750 <&scif_clk>; 751 clock-names = "fck", "brg_int", "scif_clk"; 752 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 753 <&dmac2 0x33>, <&dmac2 0x32>; 754 dma-names = "tx", "rx", "tx", "rx"; 755 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 756 resets = <&cpg 519>; 757 status = "disabled"; 758 }; 759 760 hscif2: serial@e6560000 { 761 compatible = "renesas,hscif-r8a774a1", 762 "renesas,rcar-gen3-hscif", 763 "renesas,hscif"; 764 reg = <0 0xe6560000 0 0x60>; 765 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&cpg CPG_MOD 518>, 767 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 768 <&scif_clk>; 769 clock-names = "fck", "brg_int", "scif_clk"; 770 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 771 <&dmac2 0x35>, <&dmac2 0x34>; 772 dma-names = "tx", "rx", "tx", "rx"; 773 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 774 resets = <&cpg 518>; 775 status = "disabled"; 776 }; 777 778 hscif3: serial@e66a0000 { 779 compatible = "renesas,hscif-r8a774a1", 780 "renesas,rcar-gen3-hscif", 781 "renesas,hscif"; 782 reg = <0 0xe66a0000 0 0x60>; 783 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 784 clocks = <&cpg CPG_MOD 517>, 785 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 786 <&scif_clk>; 787 clock-names = "fck", "brg_int", "scif_clk"; 788 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 789 dma-names = "tx", "rx"; 790 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 791 resets = <&cpg 517>; 792 status = "disabled"; 793 }; 794 795 hscif4: serial@e66b0000 { 796 compatible = "renesas,hscif-r8a774a1", 797 "renesas,rcar-gen3-hscif", 798 "renesas,hscif"; 799 reg = <0 0xe66b0000 0 0x60>; 800 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&cpg CPG_MOD 516>, 802 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 803 <&scif_clk>; 804 clock-names = "fck", "brg_int", "scif_clk"; 805 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 806 dma-names = "tx", "rx"; 807 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 808 resets = <&cpg 516>; 809 status = "disabled"; 810 }; 811 812 hsusb: usb@e6590000 { 813 compatible = "renesas,usbhs-r8a774a1", 814 "renesas,rcar-gen3-usbhs"; 815 reg = <0 0xe6590000 0 0x200>; 816 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 817 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 818 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 819 <&usb_dmac1 0>, <&usb_dmac1 1>; 820 dma-names = "ch0", "ch1", "ch2", "ch3"; 821 renesas,buswait = <11>; 822 phys = <&usb2_phy0 3>; 823 phy-names = "usb"; 824 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 825 resets = <&cpg 704>, <&cpg 703>; 826 status = "disabled"; 827 }; 828 829 usb2_clksel: clock-controller@e6590630 { 830 compatible = "renesas,r8a774a1-rcar-usb2-clock-sel", 831 "renesas,rcar-gen3-usb2-clock-sel"; 832 reg = <0 0xe6590630 0 0x02>; 833 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, 834 <&usb_extal_clk>, <&usb3s0_clk>; 835 clock-names = "ehci_ohci", "hs-usb-if", 836 "usb_extal", "usb_xtal"; 837 #clock-cells = <0>; 838 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 839 resets = <&cpg 703>, <&cpg 704>; 840 reset-names = "ehci_ohci", "hs-usb-if"; 841 status = "disabled"; 842 }; 843 844 usb_dmac0: dma-controller@e65a0000 { 845 compatible = "renesas,r8a774a1-usb-dmac", 846 "renesas,usb-dmac"; 847 reg = <0 0xe65a0000 0 0x100>; 848 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 850 interrupt-names = "ch0", "ch1"; 851 clocks = <&cpg CPG_MOD 330>; 852 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 853 resets = <&cpg 330>; 854 #dma-cells = <1>; 855 dma-channels = <2>; 856 }; 857 858 usb_dmac1: dma-controller@e65b0000 { 859 compatible = "renesas,r8a774a1-usb-dmac", 860 "renesas,usb-dmac"; 861 reg = <0 0xe65b0000 0 0x100>; 862 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 864 interrupt-names = "ch0", "ch1"; 865 clocks = <&cpg CPG_MOD 331>; 866 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 867 resets = <&cpg 331>; 868 #dma-cells = <1>; 869 dma-channels = <2>; 870 }; 871 872 usb3_phy0: usb-phy@e65ee000 { 873 compatible = "renesas,r8a774a1-usb3-phy", 874 "renesas,rcar-gen3-usb3-phy"; 875 reg = <0 0xe65ee000 0 0x90>; 876 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 877 <&usb_extal_clk>; 878 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 879 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 880 resets = <&cpg 328>; 881 #phy-cells = <0>; 882 status = "disabled"; 883 }; 884 885 dmac0: dma-controller@e6700000 { 886 compatible = "renesas,dmac-r8a774a1", 887 "renesas,rcar-dmac"; 888 reg = <0 0xe6700000 0 0x10000>; 889 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 906 interrupt-names = "error", 907 "ch0", "ch1", "ch2", "ch3", 908 "ch4", "ch5", "ch6", "ch7", 909 "ch8", "ch9", "ch10", "ch11", 910 "ch12", "ch13", "ch14", "ch15"; 911 clocks = <&cpg CPG_MOD 219>; 912 clock-names = "fck"; 913 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 914 resets = <&cpg 219>; 915 #dma-cells = <1>; 916 dma-channels = <16>; 917 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 918 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 919 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 920 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 921 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 922 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 923 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 924 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 925 }; 926 927 dmac1: dma-controller@e7300000 { 928 compatible = "renesas,dmac-r8a774a1", 929 "renesas,rcar-dmac"; 930 reg = <0 0xe7300000 0 0x10000>; 931 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 948 interrupt-names = "error", 949 "ch0", "ch1", "ch2", "ch3", 950 "ch4", "ch5", "ch6", "ch7", 951 "ch8", "ch9", "ch10", "ch11", 952 "ch12", "ch13", "ch14", "ch15"; 953 clocks = <&cpg CPG_MOD 218>; 954 clock-names = "fck"; 955 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 956 resets = <&cpg 218>; 957 #dma-cells = <1>; 958 dma-channels = <16>; 959 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 960 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 961 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 962 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 963 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 964 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 965 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 966 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 967 }; 968 969 dmac2: dma-controller@e7310000 { 970 compatible = "renesas,dmac-r8a774a1", 971 "renesas,rcar-dmac"; 972 reg = <0 0xe7310000 0 0x10000>; 973 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 990 interrupt-names = "error", 991 "ch0", "ch1", "ch2", "ch3", 992 "ch4", "ch5", "ch6", "ch7", 993 "ch8", "ch9", "ch10", "ch11", 994 "ch12", "ch13", "ch14", "ch15"; 995 clocks = <&cpg CPG_MOD 217>; 996 clock-names = "fck"; 997 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 998 resets = <&cpg 217>; 999 #dma-cells = <1>; 1000 dma-channels = <16>; 1001 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1002 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1003 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1004 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1005 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1006 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1007 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1008 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1009 }; 1010 1011 ipmmu_ds0: iommu@e6740000 { 1012 compatible = "renesas,ipmmu-r8a774a1"; 1013 reg = <0 0xe6740000 0 0x1000>; 1014 renesas,ipmmu-main = <&ipmmu_mm 0>; 1015 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1016 #iommu-cells = <1>; 1017 }; 1018 1019 ipmmu_ds1: iommu@e7740000 { 1020 compatible = "renesas,ipmmu-r8a774a1"; 1021 reg = <0 0xe7740000 0 0x1000>; 1022 renesas,ipmmu-main = <&ipmmu_mm 1>; 1023 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1024 #iommu-cells = <1>; 1025 }; 1026 1027 ipmmu_hc: iommu@e6570000 { 1028 compatible = "renesas,ipmmu-r8a774a1"; 1029 reg = <0 0xe6570000 0 0x1000>; 1030 renesas,ipmmu-main = <&ipmmu_mm 2>; 1031 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1032 #iommu-cells = <1>; 1033 }; 1034 1035 ipmmu_mm: iommu@e67b0000 { 1036 compatible = "renesas,ipmmu-r8a774a1"; 1037 reg = <0 0xe67b0000 0 0x1000>; 1038 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1040 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1041 #iommu-cells = <1>; 1042 }; 1043 1044 ipmmu_mp: iommu@ec670000 { 1045 compatible = "renesas,ipmmu-r8a774a1"; 1046 reg = <0 0xec670000 0 0x1000>; 1047 renesas,ipmmu-main = <&ipmmu_mm 4>; 1048 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1049 #iommu-cells = <1>; 1050 }; 1051 1052 ipmmu_pv0: iommu@fd800000 { 1053 compatible = "renesas,ipmmu-r8a774a1"; 1054 reg = <0 0xfd800000 0 0x1000>; 1055 renesas,ipmmu-main = <&ipmmu_mm 5>; 1056 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1057 #iommu-cells = <1>; 1058 }; 1059 1060 ipmmu_pv1: iommu@fd950000 { 1061 compatible = "renesas,ipmmu-r8a774a1"; 1062 reg = <0 0xfd950000 0 0x1000>; 1063 renesas,ipmmu-main = <&ipmmu_mm 6>; 1064 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1065 #iommu-cells = <1>; 1066 }; 1067 1068 ipmmu_vc0: iommu@fe6b0000 { 1069 compatible = "renesas,ipmmu-r8a774a1"; 1070 reg = <0 0xfe6b0000 0 0x1000>; 1071 renesas,ipmmu-main = <&ipmmu_mm 8>; 1072 power-domains = <&sysc R8A774A1_PD_A3VC>; 1073 #iommu-cells = <1>; 1074 }; 1075 1076 ipmmu_vi0: iommu@febd0000 { 1077 compatible = "renesas,ipmmu-r8a774a1"; 1078 reg = <0 0xfebd0000 0 0x1000>; 1079 renesas,ipmmu-main = <&ipmmu_mm 9>; 1080 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1081 #iommu-cells = <1>; 1082 }; 1083 1084 avb: ethernet@e6800000 { 1085 compatible = "renesas,etheravb-r8a774a1", 1086 "renesas,etheravb-rcar-gen3"; 1087 reg = <0 0xe6800000 0 0x800>; 1088 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1113 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1114 "ch4", "ch5", "ch6", "ch7", 1115 "ch8", "ch9", "ch10", "ch11", 1116 "ch12", "ch13", "ch14", "ch15", 1117 "ch16", "ch17", "ch18", "ch19", 1118 "ch20", "ch21", "ch22", "ch23", 1119 "ch24"; 1120 clocks = <&cpg CPG_MOD 812>; 1121 clock-names = "fck"; 1122 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1123 resets = <&cpg 812>; 1124 phy-mode = "rgmii"; 1125 rx-internal-delay-ps = <0>; 1126 tx-internal-delay-ps = <0>; 1127 iommus = <&ipmmu_ds0 16>; 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 status = "disabled"; 1131 }; 1132 1133 can0: can@e6c30000 { 1134 compatible = "renesas,can-r8a774a1", 1135 "renesas,rcar-gen3-can"; 1136 reg = <0 0xe6c30000 0 0x1000>; 1137 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1138 clocks = <&cpg CPG_MOD 916>, 1139 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1140 <&can_clk>; 1141 clock-names = "clkp1", "clkp2", "can_clk"; 1142 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1143 assigned-clock-rates = <40000000>; 1144 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1145 resets = <&cpg 916>; 1146 status = "disabled"; 1147 }; 1148 1149 can1: can@e6c38000 { 1150 compatible = "renesas,can-r8a774a1", 1151 "renesas,rcar-gen3-can"; 1152 reg = <0 0xe6c38000 0 0x1000>; 1153 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1154 clocks = <&cpg CPG_MOD 915>, 1155 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1156 <&can_clk>; 1157 clock-names = "clkp1", "clkp2", "can_clk"; 1158 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1159 assigned-clock-rates = <40000000>; 1160 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1161 resets = <&cpg 915>; 1162 status = "disabled"; 1163 }; 1164 1165 canfd: can@e66c0000 { 1166 compatible = "renesas,r8a774a1-canfd", 1167 "renesas,rcar-gen3-canfd"; 1168 reg = <0 0xe66c0000 0 0x8000>; 1169 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1171 interrupt-names = "ch_int", "g_int"; 1172 clocks = <&cpg CPG_MOD 914>, 1173 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1174 <&can_clk>; 1175 clock-names = "fck", "canfd", "can_clk"; 1176 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1177 assigned-clock-rates = <40000000>; 1178 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1179 resets = <&cpg 914>; 1180 status = "disabled"; 1181 1182 channel0 { 1183 status = "disabled"; 1184 }; 1185 1186 channel1 { 1187 status = "disabled"; 1188 }; 1189 }; 1190 1191 pwm0: pwm@e6e30000 { 1192 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1193 reg = <0 0xe6e30000 0 0x8>; 1194 #pwm-cells = <2>; 1195 clocks = <&cpg CPG_MOD 523>; 1196 resets = <&cpg 523>; 1197 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1198 status = "disabled"; 1199 }; 1200 1201 pwm1: pwm@e6e31000 { 1202 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1203 reg = <0 0xe6e31000 0 0x8>; 1204 #pwm-cells = <2>; 1205 clocks = <&cpg CPG_MOD 523>; 1206 resets = <&cpg 523>; 1207 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1208 status = "disabled"; 1209 }; 1210 1211 pwm2: pwm@e6e32000 { 1212 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1213 reg = <0 0xe6e32000 0 0x8>; 1214 #pwm-cells = <2>; 1215 clocks = <&cpg CPG_MOD 523>; 1216 resets = <&cpg 523>; 1217 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1218 status = "disabled"; 1219 }; 1220 1221 pwm3: pwm@e6e33000 { 1222 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1223 reg = <0 0xe6e33000 0 0x8>; 1224 #pwm-cells = <2>; 1225 clocks = <&cpg CPG_MOD 523>; 1226 resets = <&cpg 523>; 1227 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1228 status = "disabled"; 1229 }; 1230 1231 pwm4: pwm@e6e34000 { 1232 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1233 reg = <0 0xe6e34000 0 0x8>; 1234 #pwm-cells = <2>; 1235 clocks = <&cpg CPG_MOD 523>; 1236 resets = <&cpg 523>; 1237 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1238 status = "disabled"; 1239 }; 1240 1241 pwm5: pwm@e6e35000 { 1242 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1243 reg = <0 0xe6e35000 0 0x8>; 1244 #pwm-cells = <2>; 1245 clocks = <&cpg CPG_MOD 523>; 1246 resets = <&cpg 523>; 1247 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1248 status = "disabled"; 1249 }; 1250 1251 pwm6: pwm@e6e36000 { 1252 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1253 reg = <0 0xe6e36000 0 0x8>; 1254 #pwm-cells = <2>; 1255 clocks = <&cpg CPG_MOD 523>; 1256 resets = <&cpg 523>; 1257 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1258 status = "disabled"; 1259 }; 1260 1261 scif0: serial@e6e60000 { 1262 compatible = "renesas,scif-r8a774a1", 1263 "renesas,rcar-gen3-scif", "renesas,scif"; 1264 reg = <0 0xe6e60000 0 0x40>; 1265 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1266 clocks = <&cpg CPG_MOD 207>, 1267 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1268 <&scif_clk>; 1269 clock-names = "fck", "brg_int", "scif_clk"; 1270 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1271 <&dmac2 0x51>, <&dmac2 0x50>; 1272 dma-names = "tx", "rx", "tx", "rx"; 1273 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1274 resets = <&cpg 207>; 1275 status = "disabled"; 1276 }; 1277 1278 scif1: serial@e6e68000 { 1279 compatible = "renesas,scif-r8a774a1", 1280 "renesas,rcar-gen3-scif", "renesas,scif"; 1281 reg = <0 0xe6e68000 0 0x40>; 1282 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&cpg CPG_MOD 206>, 1284 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1285 <&scif_clk>; 1286 clock-names = "fck", "brg_int", "scif_clk"; 1287 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1288 <&dmac2 0x53>, <&dmac2 0x52>; 1289 dma-names = "tx", "rx", "tx", "rx"; 1290 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1291 resets = <&cpg 206>; 1292 status = "disabled"; 1293 }; 1294 1295 scif2: serial@e6e88000 { 1296 compatible = "renesas,scif-r8a774a1", 1297 "renesas,rcar-gen3-scif", "renesas,scif"; 1298 reg = <0 0xe6e88000 0 0x40>; 1299 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1300 clocks = <&cpg CPG_MOD 310>, 1301 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1302 <&scif_clk>; 1303 clock-names = "fck", "brg_int", "scif_clk"; 1304 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1305 <&dmac2 0x13>, <&dmac2 0x12>; 1306 dma-names = "tx", "rx", "tx", "rx"; 1307 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1308 resets = <&cpg 310>; 1309 status = "disabled"; 1310 }; 1311 1312 scif3: serial@e6c50000 { 1313 compatible = "renesas,scif-r8a774a1", 1314 "renesas,rcar-gen3-scif", "renesas,scif"; 1315 reg = <0 0xe6c50000 0 0x40>; 1316 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1317 clocks = <&cpg CPG_MOD 204>, 1318 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1319 <&scif_clk>; 1320 clock-names = "fck", "brg_int", "scif_clk"; 1321 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1322 dma-names = "tx", "rx"; 1323 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1324 resets = <&cpg 204>; 1325 status = "disabled"; 1326 }; 1327 1328 scif4: serial@e6c40000 { 1329 compatible = "renesas,scif-r8a774a1", 1330 "renesas,rcar-gen3-scif", "renesas,scif"; 1331 reg = <0 0xe6c40000 0 0x40>; 1332 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1333 clocks = <&cpg CPG_MOD 203>, 1334 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1335 <&scif_clk>; 1336 clock-names = "fck", "brg_int", "scif_clk"; 1337 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1338 dma-names = "tx", "rx"; 1339 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1340 resets = <&cpg 203>; 1341 status = "disabled"; 1342 }; 1343 1344 scif5: serial@e6f30000 { 1345 compatible = "renesas,scif-r8a774a1", 1346 "renesas,rcar-gen3-scif", "renesas,scif"; 1347 reg = <0 0xe6f30000 0 0x40>; 1348 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1349 clocks = <&cpg CPG_MOD 202>, 1350 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1351 <&scif_clk>; 1352 clock-names = "fck", "brg_int", "scif_clk"; 1353 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1354 <&dmac2 0x5b>, <&dmac2 0x5a>; 1355 dma-names = "tx", "rx", "tx", "rx"; 1356 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1357 resets = <&cpg 202>; 1358 status = "disabled"; 1359 }; 1360 1361 msiof0: spi@e6e90000 { 1362 compatible = "renesas,msiof-r8a774a1", 1363 "renesas,rcar-gen3-msiof"; 1364 reg = <0 0xe6e90000 0 0x0064>; 1365 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1366 clocks = <&cpg CPG_MOD 211>; 1367 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1368 <&dmac2 0x41>, <&dmac2 0x40>; 1369 dma-names = "tx", "rx", "tx", "rx"; 1370 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1371 resets = <&cpg 211>; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 status = "disabled"; 1375 }; 1376 1377 msiof1: spi@e6ea0000 { 1378 compatible = "renesas,msiof-r8a774a1", 1379 "renesas,rcar-gen3-msiof"; 1380 reg = <0 0xe6ea0000 0 0x0064>; 1381 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1382 clocks = <&cpg CPG_MOD 210>; 1383 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1384 <&dmac2 0x43>, <&dmac2 0x42>; 1385 dma-names = "tx", "rx", "tx", "rx"; 1386 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1387 resets = <&cpg 210>; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 status = "disabled"; 1391 }; 1392 1393 msiof2: spi@e6c00000 { 1394 compatible = "renesas,msiof-r8a774a1", 1395 "renesas,rcar-gen3-msiof"; 1396 reg = <0 0xe6c00000 0 0x0064>; 1397 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1398 clocks = <&cpg CPG_MOD 209>; 1399 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1400 dma-names = "tx", "rx"; 1401 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1402 resets = <&cpg 209>; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 status = "disabled"; 1406 }; 1407 1408 msiof3: spi@e6c10000 { 1409 compatible = "renesas,msiof-r8a774a1", 1410 "renesas,rcar-gen3-msiof"; 1411 reg = <0 0xe6c10000 0 0x0064>; 1412 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1413 clocks = <&cpg CPG_MOD 208>; 1414 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1415 dma-names = "tx", "rx"; 1416 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1417 resets = <&cpg 208>; 1418 #address-cells = <1>; 1419 #size-cells = <0>; 1420 status = "disabled"; 1421 }; 1422 1423 vin0: video@e6ef0000 { 1424 compatible = "renesas,vin-r8a774a1"; 1425 reg = <0 0xe6ef0000 0 0x1000>; 1426 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1427 clocks = <&cpg CPG_MOD 811>; 1428 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1429 resets = <&cpg 811>; 1430 renesas,id = <0>; 1431 status = "disabled"; 1432 1433 ports { 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 1437 port@1 { 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 1441 reg = <1>; 1442 1443 vin0csi20: endpoint@0 { 1444 reg = <0>; 1445 remote-endpoint = <&csi20vin0>; 1446 }; 1447 vin0csi40: endpoint@2 { 1448 reg = <2>; 1449 remote-endpoint = <&csi40vin0>; 1450 }; 1451 }; 1452 }; 1453 }; 1454 1455 vin1: video@e6ef1000 { 1456 compatible = "renesas,vin-r8a774a1"; 1457 reg = <0 0xe6ef1000 0 0x1000>; 1458 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1459 clocks = <&cpg CPG_MOD 810>; 1460 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1461 resets = <&cpg 810>; 1462 renesas,id = <1>; 1463 status = "disabled"; 1464 1465 ports { 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 1469 port@1 { 1470 #address-cells = <1>; 1471 #size-cells = <0>; 1472 1473 reg = <1>; 1474 1475 vin1csi20: endpoint@0 { 1476 reg = <0>; 1477 remote-endpoint = <&csi20vin1>; 1478 }; 1479 vin1csi40: endpoint@2 { 1480 reg = <2>; 1481 remote-endpoint = <&csi40vin1>; 1482 }; 1483 }; 1484 }; 1485 }; 1486 1487 vin2: video@e6ef2000 { 1488 compatible = "renesas,vin-r8a774a1"; 1489 reg = <0 0xe6ef2000 0 0x1000>; 1490 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1491 clocks = <&cpg CPG_MOD 809>; 1492 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1493 resets = <&cpg 809>; 1494 renesas,id = <2>; 1495 status = "disabled"; 1496 1497 ports { 1498 #address-cells = <1>; 1499 #size-cells = <0>; 1500 1501 port@1 { 1502 #address-cells = <1>; 1503 #size-cells = <0>; 1504 1505 reg = <1>; 1506 1507 vin2csi20: endpoint@0 { 1508 reg = <0>; 1509 remote-endpoint = <&csi20vin2>; 1510 }; 1511 vin2csi40: endpoint@2 { 1512 reg = <2>; 1513 remote-endpoint = <&csi40vin2>; 1514 }; 1515 }; 1516 }; 1517 }; 1518 1519 vin3: video@e6ef3000 { 1520 compatible = "renesas,vin-r8a774a1"; 1521 reg = <0 0xe6ef3000 0 0x1000>; 1522 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1523 clocks = <&cpg CPG_MOD 808>; 1524 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1525 resets = <&cpg 808>; 1526 renesas,id = <3>; 1527 status = "disabled"; 1528 1529 ports { 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 1533 port@1 { 1534 #address-cells = <1>; 1535 #size-cells = <0>; 1536 1537 reg = <1>; 1538 1539 vin3csi20: endpoint@0 { 1540 reg = <0>; 1541 remote-endpoint = <&csi20vin3>; 1542 }; 1543 vin3csi40: endpoint@2 { 1544 reg = <2>; 1545 remote-endpoint = <&csi40vin3>; 1546 }; 1547 }; 1548 }; 1549 }; 1550 1551 vin4: video@e6ef4000 { 1552 compatible = "renesas,vin-r8a774a1"; 1553 reg = <0 0xe6ef4000 0 0x1000>; 1554 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1555 clocks = <&cpg CPG_MOD 807>; 1556 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1557 resets = <&cpg 807>; 1558 renesas,id = <4>; 1559 status = "disabled"; 1560 1561 ports { 1562 #address-cells = <1>; 1563 #size-cells = <0>; 1564 1565 port@1 { 1566 #address-cells = <1>; 1567 #size-cells = <0>; 1568 1569 reg = <1>; 1570 1571 vin4csi20: endpoint@0 { 1572 reg = <0>; 1573 remote-endpoint = <&csi20vin4>; 1574 }; 1575 vin4csi40: endpoint@2 { 1576 reg = <2>; 1577 remote-endpoint = <&csi40vin4>; 1578 }; 1579 }; 1580 }; 1581 }; 1582 1583 vin5: video@e6ef5000 { 1584 compatible = "renesas,vin-r8a774a1"; 1585 reg = <0 0xe6ef5000 0 0x1000>; 1586 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1587 clocks = <&cpg CPG_MOD 806>; 1588 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1589 resets = <&cpg 806>; 1590 renesas,id = <5>; 1591 status = "disabled"; 1592 1593 ports { 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 1597 port@1 { 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 1601 reg = <1>; 1602 1603 vin5csi20: endpoint@0 { 1604 reg = <0>; 1605 remote-endpoint = <&csi20vin5>; 1606 }; 1607 vin5csi40: endpoint@2 { 1608 reg = <2>; 1609 remote-endpoint = <&csi40vin5>; 1610 }; 1611 }; 1612 }; 1613 }; 1614 1615 vin6: video@e6ef6000 { 1616 compatible = "renesas,vin-r8a774a1"; 1617 reg = <0 0xe6ef6000 0 0x1000>; 1618 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1619 clocks = <&cpg CPG_MOD 805>; 1620 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1621 resets = <&cpg 805>; 1622 renesas,id = <6>; 1623 status = "disabled"; 1624 1625 ports { 1626 #address-cells = <1>; 1627 #size-cells = <0>; 1628 1629 port@1 { 1630 #address-cells = <1>; 1631 #size-cells = <0>; 1632 1633 reg = <1>; 1634 1635 vin6csi20: endpoint@0 { 1636 reg = <0>; 1637 remote-endpoint = <&csi20vin6>; 1638 }; 1639 vin6csi40: endpoint@2 { 1640 reg = <2>; 1641 remote-endpoint = <&csi40vin6>; 1642 }; 1643 }; 1644 }; 1645 }; 1646 1647 vin7: video@e6ef7000 { 1648 compatible = "renesas,vin-r8a774a1"; 1649 reg = <0 0xe6ef7000 0 0x1000>; 1650 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1651 clocks = <&cpg CPG_MOD 804>; 1652 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1653 resets = <&cpg 804>; 1654 renesas,id = <7>; 1655 status = "disabled"; 1656 1657 ports { 1658 #address-cells = <1>; 1659 #size-cells = <0>; 1660 1661 port@1 { 1662 #address-cells = <1>; 1663 #size-cells = <0>; 1664 1665 reg = <1>; 1666 1667 vin7csi20: endpoint@0 { 1668 reg = <0>; 1669 remote-endpoint = <&csi20vin7>; 1670 }; 1671 vin7csi40: endpoint@2 { 1672 reg = <2>; 1673 remote-endpoint = <&csi40vin7>; 1674 }; 1675 }; 1676 }; 1677 }; 1678 1679 rcar_sound: sound@ec500000 { 1680 /* 1681 * #sound-dai-cells is required 1682 * 1683 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1684 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1685 */ 1686 /* 1687 * #clock-cells is required for audio_clkout0/1/2/3 1688 * 1689 * clkout : #clock-cells = <0>; <&rcar_sound>; 1690 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1691 */ 1692 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; 1693 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1694 <0 0xec5a0000 0 0x100>, /* ADG */ 1695 <0 0xec540000 0 0x1000>, /* SSIU */ 1696 <0 0xec541000 0 0x280>, /* SSI */ 1697 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1698 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1699 1700 clocks = <&cpg CPG_MOD 1005>, 1701 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1702 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1703 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1704 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1705 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1706 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1707 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1708 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1709 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1710 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1711 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1712 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1713 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1714 <&audio_clk_a>, <&audio_clk_b>, 1715 <&audio_clk_c>, 1716 <&cpg CPG_CORE R8A774A1_CLK_S0D4>; 1717 clock-names = "ssi-all", 1718 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1719 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1720 "ssi.1", "ssi.0", 1721 "src.9", "src.8", "src.7", "src.6", 1722 "src.5", "src.4", "src.3", "src.2", 1723 "src.1", "src.0", 1724 "mix.1", "mix.0", 1725 "ctu.1", "ctu.0", 1726 "dvc.0", "dvc.1", 1727 "clk_a", "clk_b", "clk_c", "clk_i"; 1728 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1729 resets = <&cpg 1005>, 1730 <&cpg 1006>, <&cpg 1007>, 1731 <&cpg 1008>, <&cpg 1009>, 1732 <&cpg 1010>, <&cpg 1011>, 1733 <&cpg 1012>, <&cpg 1013>, 1734 <&cpg 1014>, <&cpg 1015>; 1735 reset-names = "ssi-all", 1736 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1737 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1738 "ssi.1", "ssi.0"; 1739 status = "disabled"; 1740 1741 rcar_sound,ctu { 1742 ctu00: ctu-0 { }; 1743 ctu01: ctu-1 { }; 1744 ctu02: ctu-2 { }; 1745 ctu03: ctu-3 { }; 1746 ctu10: ctu-4 { }; 1747 ctu11: ctu-5 { }; 1748 ctu12: ctu-6 { }; 1749 ctu13: ctu-7 { }; 1750 }; 1751 1752 rcar_sound,dvc { 1753 dvc0: dvc-0 { 1754 dmas = <&audma1 0xbc>; 1755 dma-names = "tx"; 1756 }; 1757 dvc1: dvc-1 { 1758 dmas = <&audma1 0xbe>; 1759 dma-names = "tx"; 1760 }; 1761 }; 1762 1763 rcar_sound,mix { 1764 mix0: mix-0 { }; 1765 mix1: mix-1 { }; 1766 }; 1767 1768 rcar_sound,src { 1769 src0: src-0 { 1770 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1771 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1772 dma-names = "rx", "tx"; 1773 }; 1774 src1: src-1 { 1775 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1776 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1777 dma-names = "rx", "tx"; 1778 }; 1779 src2: src-2 { 1780 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1781 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1782 dma-names = "rx", "tx"; 1783 }; 1784 src3: src-3 { 1785 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1786 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1787 dma-names = "rx", "tx"; 1788 }; 1789 src4: src-4 { 1790 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1791 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1792 dma-names = "rx", "tx"; 1793 }; 1794 src5: src-5 { 1795 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1796 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1797 dma-names = "rx", "tx"; 1798 }; 1799 src6: src-6 { 1800 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1801 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1802 dma-names = "rx", "tx"; 1803 }; 1804 src7: src-7 { 1805 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1806 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1807 dma-names = "rx", "tx"; 1808 }; 1809 src8: src-8 { 1810 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1811 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1812 dma-names = "rx", "tx"; 1813 }; 1814 src9: src-9 { 1815 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1816 dmas = <&audma0 0x97>, <&audma1 0xba>; 1817 dma-names = "rx", "tx"; 1818 }; 1819 }; 1820 1821 rcar_sound,ssi { 1822 ssi0: ssi-0 { 1823 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1824 dmas = <&audma0 0x01>, <&audma1 0x02>; 1825 dma-names = "rx", "tx"; 1826 }; 1827 ssi1: ssi-1 { 1828 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1829 dmas = <&audma0 0x03>, <&audma1 0x04>; 1830 dma-names = "rx", "tx"; 1831 }; 1832 ssi2: ssi-2 { 1833 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1834 dmas = <&audma0 0x05>, <&audma1 0x06>; 1835 dma-names = "rx", "tx"; 1836 }; 1837 ssi3: ssi-3 { 1838 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1839 dmas = <&audma0 0x07>, <&audma1 0x08>; 1840 dma-names = "rx", "tx"; 1841 }; 1842 ssi4: ssi-4 { 1843 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1844 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1845 dma-names = "rx", "tx"; 1846 }; 1847 ssi5: ssi-5 { 1848 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1849 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1850 dma-names = "rx", "tx"; 1851 }; 1852 ssi6: ssi-6 { 1853 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1854 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1855 dma-names = "rx", "tx"; 1856 }; 1857 ssi7: ssi-7 { 1858 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1859 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1860 dma-names = "rx", "tx"; 1861 }; 1862 ssi8: ssi-8 { 1863 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1864 dmas = <&audma0 0x11>, <&audma1 0x12>; 1865 dma-names = "rx", "tx"; 1866 }; 1867 ssi9: ssi-9 { 1868 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1869 dmas = <&audma0 0x13>, <&audma1 0x14>; 1870 dma-names = "rx", "tx"; 1871 }; 1872 }; 1873 1874 rcar_sound,ssiu { 1875 ssiu00: ssiu-0 { 1876 dmas = <&audma0 0x15>, <&audma1 0x16>; 1877 dma-names = "rx", "tx"; 1878 }; 1879 ssiu01: ssiu-1 { 1880 dmas = <&audma0 0x35>, <&audma1 0x36>; 1881 dma-names = "rx", "tx"; 1882 }; 1883 ssiu02: ssiu-2 { 1884 dmas = <&audma0 0x37>, <&audma1 0x38>; 1885 dma-names = "rx", "tx"; 1886 }; 1887 ssiu03: ssiu-3 { 1888 dmas = <&audma0 0x47>, <&audma1 0x48>; 1889 dma-names = "rx", "tx"; 1890 }; 1891 ssiu04: ssiu-4 { 1892 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1893 dma-names = "rx", "tx"; 1894 }; 1895 ssiu05: ssiu-5 { 1896 dmas = <&audma0 0x43>, <&audma1 0x44>; 1897 dma-names = "rx", "tx"; 1898 }; 1899 ssiu06: ssiu-6 { 1900 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1901 dma-names = "rx", "tx"; 1902 }; 1903 ssiu07: ssiu-7 { 1904 dmas = <&audma0 0x53>, <&audma1 0x54>; 1905 dma-names = "rx", "tx"; 1906 }; 1907 ssiu10: ssiu-8 { 1908 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1909 dma-names = "rx", "tx"; 1910 }; 1911 ssiu11: ssiu-9 { 1912 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1913 dma-names = "rx", "tx"; 1914 }; 1915 ssiu12: ssiu-10 { 1916 dmas = <&audma0 0x57>, <&audma1 0x58>; 1917 dma-names = "rx", "tx"; 1918 }; 1919 ssiu13: ssiu-11 { 1920 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1921 dma-names = "rx", "tx"; 1922 }; 1923 ssiu14: ssiu-12 { 1924 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1925 dma-names = "rx", "tx"; 1926 }; 1927 ssiu15: ssiu-13 { 1928 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1929 dma-names = "rx", "tx"; 1930 }; 1931 ssiu16: ssiu-14 { 1932 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1933 dma-names = "rx", "tx"; 1934 }; 1935 ssiu17: ssiu-15 { 1936 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1937 dma-names = "rx", "tx"; 1938 }; 1939 ssiu20: ssiu-16 { 1940 dmas = <&audma0 0x63>, <&audma1 0x64>; 1941 dma-names = "rx", "tx"; 1942 }; 1943 ssiu21: ssiu-17 { 1944 dmas = <&audma0 0x67>, <&audma1 0x68>; 1945 dma-names = "rx", "tx"; 1946 }; 1947 ssiu22: ssiu-18 { 1948 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1949 dma-names = "rx", "tx"; 1950 }; 1951 ssiu23: ssiu-19 { 1952 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1953 dma-names = "rx", "tx"; 1954 }; 1955 ssiu24: ssiu-20 { 1956 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1957 dma-names = "rx", "tx"; 1958 }; 1959 ssiu25: ssiu-21 { 1960 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1961 dma-names = "rx", "tx"; 1962 }; 1963 ssiu26: ssiu-22 { 1964 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1965 dma-names = "rx", "tx"; 1966 }; 1967 ssiu27: ssiu-23 { 1968 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1969 dma-names = "rx", "tx"; 1970 }; 1971 ssiu30: ssiu-24 { 1972 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1973 dma-names = "rx", "tx"; 1974 }; 1975 ssiu31: ssiu-25 { 1976 dmas = <&audma0 0x21>, <&audma1 0x22>; 1977 dma-names = "rx", "tx"; 1978 }; 1979 ssiu32: ssiu-26 { 1980 dmas = <&audma0 0x23>, <&audma1 0x24>; 1981 dma-names = "rx", "tx"; 1982 }; 1983 ssiu33: ssiu-27 { 1984 dmas = <&audma0 0x25>, <&audma1 0x26>; 1985 dma-names = "rx", "tx"; 1986 }; 1987 ssiu34: ssiu-28 { 1988 dmas = <&audma0 0x27>, <&audma1 0x28>; 1989 dma-names = "rx", "tx"; 1990 }; 1991 ssiu35: ssiu-29 { 1992 dmas = <&audma0 0x29>, <&audma1 0x2A>; 1993 dma-names = "rx", "tx"; 1994 }; 1995 ssiu36: ssiu-30 { 1996 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 1997 dma-names = "rx", "tx"; 1998 }; 1999 ssiu37: ssiu-31 { 2000 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 2001 dma-names = "rx", "tx"; 2002 }; 2003 ssiu40: ssiu-32 { 2004 dmas = <&audma0 0x71>, <&audma1 0x72>; 2005 dma-names = "rx", "tx"; 2006 }; 2007 ssiu41: ssiu-33 { 2008 dmas = <&audma0 0x17>, <&audma1 0x18>; 2009 dma-names = "rx", "tx"; 2010 }; 2011 ssiu42: ssiu-34 { 2012 dmas = <&audma0 0x19>, <&audma1 0x1A>; 2013 dma-names = "rx", "tx"; 2014 }; 2015 ssiu43: ssiu-35 { 2016 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 2017 dma-names = "rx", "tx"; 2018 }; 2019 ssiu44: ssiu-36 { 2020 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 2021 dma-names = "rx", "tx"; 2022 }; 2023 ssiu45: ssiu-37 { 2024 dmas = <&audma0 0x1F>, <&audma1 0x20>; 2025 dma-names = "rx", "tx"; 2026 }; 2027 ssiu46: ssiu-38 { 2028 dmas = <&audma0 0x31>, <&audma1 0x32>; 2029 dma-names = "rx", "tx"; 2030 }; 2031 ssiu47: ssiu-39 { 2032 dmas = <&audma0 0x33>, <&audma1 0x34>; 2033 dma-names = "rx", "tx"; 2034 }; 2035 ssiu50: ssiu-40 { 2036 dmas = <&audma0 0x73>, <&audma1 0x74>; 2037 dma-names = "rx", "tx"; 2038 }; 2039 ssiu60: ssiu-41 { 2040 dmas = <&audma0 0x75>, <&audma1 0x76>; 2041 dma-names = "rx", "tx"; 2042 }; 2043 ssiu70: ssiu-42 { 2044 dmas = <&audma0 0x79>, <&audma1 0x7a>; 2045 dma-names = "rx", "tx"; 2046 }; 2047 ssiu80: ssiu-43 { 2048 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 2049 dma-names = "rx", "tx"; 2050 }; 2051 ssiu90: ssiu-44 { 2052 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 2053 dma-names = "rx", "tx"; 2054 }; 2055 ssiu91: ssiu-45 { 2056 dmas = <&audma0 0x7F>, <&audma1 0x80>; 2057 dma-names = "rx", "tx"; 2058 }; 2059 ssiu92: ssiu-46 { 2060 dmas = <&audma0 0x81>, <&audma1 0x82>; 2061 dma-names = "rx", "tx"; 2062 }; 2063 ssiu93: ssiu-47 { 2064 dmas = <&audma0 0x83>, <&audma1 0x84>; 2065 dma-names = "rx", "tx"; 2066 }; 2067 ssiu94: ssiu-48 { 2068 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 2069 dma-names = "rx", "tx"; 2070 }; 2071 ssiu95: ssiu-49 { 2072 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 2073 dma-names = "rx", "tx"; 2074 }; 2075 ssiu96: ssiu-50 { 2076 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2077 dma-names = "rx", "tx"; 2078 }; 2079 ssiu97: ssiu-51 { 2080 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2081 dma-names = "rx", "tx"; 2082 }; 2083 }; 2084 }; 2085 2086 audma0: dma-controller@ec700000 { 2087 compatible = "renesas,dmac-r8a774a1", 2088 "renesas,rcar-dmac"; 2089 reg = <0 0xec700000 0 0x10000>; 2090 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2107 interrupt-names = "error", 2108 "ch0", "ch1", "ch2", "ch3", 2109 "ch4", "ch5", "ch6", "ch7", 2110 "ch8", "ch9", "ch10", "ch11", 2111 "ch12", "ch13", "ch14", "ch15"; 2112 clocks = <&cpg CPG_MOD 502>; 2113 clock-names = "fck"; 2114 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2115 resets = <&cpg 502>; 2116 #dma-cells = <1>; 2117 dma-channels = <16>; 2118 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 2119 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 2120 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 2121 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 2122 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 2123 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 2124 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 2125 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 2126 }; 2127 2128 audma1: dma-controller@ec720000 { 2129 compatible = "renesas,dmac-r8a774a1", 2130 "renesas,rcar-dmac"; 2131 reg = <0 0xec720000 0 0x10000>; 2132 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2149 interrupt-names = "error", 2150 "ch0", "ch1", "ch2", "ch3", 2151 "ch4", "ch5", "ch6", "ch7", 2152 "ch8", "ch9", "ch10", "ch11", 2153 "ch12", "ch13", "ch14", "ch15"; 2154 clocks = <&cpg CPG_MOD 501>; 2155 clock-names = "fck"; 2156 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2157 resets = <&cpg 501>; 2158 #dma-cells = <1>; 2159 dma-channels = <16>; 2160 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 2161 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 2162 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 2163 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 2164 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 2165 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 2166 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 2167 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 2168 }; 2169 2170 xhci0: usb@ee000000 { 2171 compatible = "renesas,xhci-r8a774a1", 2172 "renesas,rcar-gen3-xhci"; 2173 reg = <0 0xee000000 0 0xc00>; 2174 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2175 clocks = <&cpg CPG_MOD 328>; 2176 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2177 resets = <&cpg 328>; 2178 status = "disabled"; 2179 }; 2180 2181 usb3_peri0: usb@ee020000 { 2182 compatible = "renesas,r8a774a1-usb3-peri", 2183 "renesas,rcar-gen3-usb3-peri"; 2184 reg = <0 0xee020000 0 0x400>; 2185 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2186 clocks = <&cpg CPG_MOD 328>; 2187 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2188 resets = <&cpg 328>; 2189 status = "disabled"; 2190 }; 2191 2192 ohci0: usb@ee080000 { 2193 compatible = "generic-ohci"; 2194 reg = <0 0xee080000 0 0x100>; 2195 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2196 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2197 phys = <&usb2_phy0 1>; 2198 phy-names = "usb"; 2199 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2200 resets = <&cpg 703>, <&cpg 704>; 2201 status = "disabled"; 2202 }; 2203 2204 ohci1: usb@ee0a0000 { 2205 compatible = "generic-ohci"; 2206 reg = <0 0xee0a0000 0 0x100>; 2207 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2208 clocks = <&cpg CPG_MOD 702>; 2209 phys = <&usb2_phy1 1>; 2210 phy-names = "usb"; 2211 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2212 resets = <&cpg 702>; 2213 status = "disabled"; 2214 }; 2215 2216 ehci0: usb@ee080100 { 2217 compatible = "generic-ehci"; 2218 reg = <0 0xee080100 0 0x100>; 2219 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2220 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2221 phys = <&usb2_phy0 2>; 2222 phy-names = "usb"; 2223 companion = <&ohci0>; 2224 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2225 resets = <&cpg 703>, <&cpg 704>; 2226 status = "disabled"; 2227 }; 2228 2229 ehci1: usb@ee0a0100 { 2230 compatible = "generic-ehci"; 2231 reg = <0 0xee0a0100 0 0x100>; 2232 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2233 clocks = <&cpg CPG_MOD 702>; 2234 phys = <&usb2_phy1 2>; 2235 phy-names = "usb"; 2236 companion = <&ohci1>; 2237 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2238 resets = <&cpg 702>; 2239 status = "disabled"; 2240 }; 2241 2242 usb2_phy0: usb-phy@ee080200 { 2243 compatible = "renesas,usb2-phy-r8a774a1", 2244 "renesas,rcar-gen3-usb2-phy"; 2245 reg = <0 0xee080200 0 0x700>; 2246 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2247 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2248 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2249 resets = <&cpg 703>, <&cpg 704>; 2250 #phy-cells = <1>; 2251 status = "disabled"; 2252 }; 2253 2254 usb2_phy1: usb-phy@ee0a0200 { 2255 compatible = "renesas,usb2-phy-r8a774a1", 2256 "renesas,rcar-gen3-usb2-phy"; 2257 reg = <0 0xee0a0200 0 0x700>; 2258 clocks = <&cpg CPG_MOD 702>; 2259 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2260 resets = <&cpg 702>; 2261 #phy-cells = <1>; 2262 status = "disabled"; 2263 }; 2264 2265 sdhi0: mmc@ee100000 { 2266 compatible = "renesas,sdhi-r8a774a1", 2267 "renesas,rcar-gen3-sdhi"; 2268 reg = <0 0xee100000 0 0x2000>; 2269 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2270 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>; 2271 clock-names = "core", "clkh"; 2272 max-frequency = <200000000>; 2273 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2274 resets = <&cpg 314>; 2275 status = "disabled"; 2276 }; 2277 2278 sdhi1: mmc@ee120000 { 2279 compatible = "renesas,sdhi-r8a774a1", 2280 "renesas,rcar-gen3-sdhi"; 2281 reg = <0 0xee120000 0 0x2000>; 2282 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2283 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>; 2284 clock-names = "core", "clkh"; 2285 max-frequency = <200000000>; 2286 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2287 resets = <&cpg 313>; 2288 status = "disabled"; 2289 }; 2290 2291 sdhi2: mmc@ee140000 { 2292 compatible = "renesas,sdhi-r8a774a1", 2293 "renesas,rcar-gen3-sdhi"; 2294 reg = <0 0xee140000 0 0x2000>; 2295 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2296 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>; 2297 clock-names = "core", "clkh"; 2298 max-frequency = <200000000>; 2299 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2300 resets = <&cpg 312>; 2301 status = "disabled"; 2302 }; 2303 2304 sdhi3: mmc@ee160000 { 2305 compatible = "renesas,sdhi-r8a774a1", 2306 "renesas,rcar-gen3-sdhi"; 2307 reg = <0 0xee160000 0 0x2000>; 2308 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2309 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>; 2310 clock-names = "core", "clkh"; 2311 max-frequency = <200000000>; 2312 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2313 resets = <&cpg 311>; 2314 status = "disabled"; 2315 }; 2316 2317 rpc: spi@ee200000 { 2318 compatible = "renesas,r8a774a1-rpc-if", 2319 "renesas,rcar-gen3-rpc-if"; 2320 reg = <0 0xee200000 0 0x200>, 2321 <0 0x08000000 0 0x4000000>, 2322 <0 0xee208000 0 0x100>; 2323 reg-names = "regs", "dirmap", "wbuf"; 2324 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 2325 clocks = <&cpg CPG_MOD 917>; 2326 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2327 resets = <&cpg 917>; 2328 #address-cells = <1>; 2329 #size-cells = <0>; 2330 status = "disabled"; 2331 }; 2332 2333 gic: interrupt-controller@f1010000 { 2334 compatible = "arm,gic-400"; 2335 #interrupt-cells = <3>; 2336 #address-cells = <0>; 2337 interrupt-controller; 2338 reg = <0x0 0xf1010000 0 0x1000>, 2339 <0x0 0xf1020000 0 0x20000>, 2340 <0x0 0xf1040000 0 0x20000>, 2341 <0x0 0xf1060000 0 0x20000>; 2342 interrupts = <GIC_PPI 9 2343 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 2344 clocks = <&cpg CPG_MOD 408>; 2345 clock-names = "clk"; 2346 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2347 resets = <&cpg 408>; 2348 }; 2349 2350 pciec0: pcie@fe000000 { 2351 compatible = "renesas,pcie-r8a774a1", 2352 "renesas,pcie-rcar-gen3"; 2353 reg = <0 0xfe000000 0 0x80000>; 2354 #address-cells = <3>; 2355 #size-cells = <2>; 2356 bus-range = <0x00 0xff>; 2357 device_type = "pci"; 2358 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2359 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2360 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2361 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2362 /* Map all possible DDR as inbound ranges */ 2363 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2364 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2365 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2366 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2367 #interrupt-cells = <1>; 2368 interrupt-map-mask = <0 0 0 0>; 2369 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2370 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2371 clock-names = "pcie", "pcie_bus"; 2372 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2373 resets = <&cpg 319>; 2374 status = "disabled"; 2375 }; 2376 2377 pciec1: pcie@ee800000 { 2378 compatible = "renesas,pcie-r8a774a1", 2379 "renesas,pcie-rcar-gen3"; 2380 reg = <0 0xee800000 0 0x80000>; 2381 #address-cells = <3>; 2382 #size-cells = <2>; 2383 bus-range = <0x00 0xff>; 2384 device_type = "pci"; 2385 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2386 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2387 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2388 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2389 /* Map all possible DDR as inbound ranges */ 2390 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2391 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2392 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2393 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2394 #interrupt-cells = <1>; 2395 interrupt-map-mask = <0 0 0 0>; 2396 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2397 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2398 clock-names = "pcie", "pcie_bus"; 2399 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2400 resets = <&cpg 318>; 2401 status = "disabled"; 2402 }; 2403 2404 pciec0_ep: pcie-ep@fe000000 { 2405 compatible = "renesas,r8a774a1-pcie-ep", 2406 "renesas,rcar-gen3-pcie-ep"; 2407 reg = <0x0 0xfe000000 0 0x80000>, 2408 <0x0 0xfe100000 0 0x100000>, 2409 <0x0 0xfe200000 0 0x200000>, 2410 <0x0 0x30000000 0 0x8000000>, 2411 <0x0 0x38000000 0 0x8000000>; 2412 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2413 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2414 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2415 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2416 clocks = <&cpg CPG_MOD 319>; 2417 clock-names = "pcie"; 2418 resets = <&cpg 319>; 2419 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2420 status = "disabled"; 2421 }; 2422 2423 pciec1_ep: pcie-ep@ee800000 { 2424 compatible = "renesas,r8a774a1-pcie-ep", 2425 "renesas,rcar-gen3-pcie-ep"; 2426 reg = <0x0 0xee800000 0 0x80000>, 2427 <0x0 0xee900000 0 0x100000>, 2428 <0x0 0xeea00000 0 0x200000>, 2429 <0x0 0xc0000000 0 0x8000000>, 2430 <0x0 0xc8000000 0 0x8000000>; 2431 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2432 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2435 clocks = <&cpg CPG_MOD 318>; 2436 clock-names = "pcie"; 2437 resets = <&cpg 318>; 2438 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2439 status = "disabled"; 2440 }; 2441 2442 fdp1@fe940000 { 2443 compatible = "renesas,fdp1"; 2444 reg = <0 0xfe940000 0 0x2400>; 2445 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2446 clocks = <&cpg CPG_MOD 119>; 2447 power-domains = <&sysc R8A774A1_PD_A3VC>; 2448 resets = <&cpg 119>; 2449 renesas,fcp = <&fcpf0>; 2450 }; 2451 2452 fcpf0: fcp@fe950000 { 2453 compatible = "renesas,fcpf"; 2454 reg = <0 0xfe950000 0 0x200>; 2455 clocks = <&cpg CPG_MOD 615>; 2456 power-domains = <&sysc R8A774A1_PD_A3VC>; 2457 resets = <&cpg 615>; 2458 }; 2459 2460 fcpvb0: fcp@fe96f000 { 2461 compatible = "renesas,fcpv"; 2462 reg = <0 0xfe96f000 0 0x200>; 2463 clocks = <&cpg CPG_MOD 607>; 2464 power-domains = <&sysc R8A774A1_PD_A3VC>; 2465 resets = <&cpg 607>; 2466 }; 2467 2468 fcpvd0: fcp@fea27000 { 2469 compatible = "renesas,fcpv"; 2470 reg = <0 0xfea27000 0 0x200>; 2471 clocks = <&cpg CPG_MOD 603>; 2472 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2473 resets = <&cpg 603>; 2474 iommus = <&ipmmu_vi0 8>; 2475 }; 2476 2477 fcpvd1: fcp@fea2f000 { 2478 compatible = "renesas,fcpv"; 2479 reg = <0 0xfea2f000 0 0x200>; 2480 clocks = <&cpg CPG_MOD 602>; 2481 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2482 resets = <&cpg 602>; 2483 iommus = <&ipmmu_vi0 9>; 2484 }; 2485 2486 fcpvd2: fcp@fea37000 { 2487 compatible = "renesas,fcpv"; 2488 reg = <0 0xfea37000 0 0x200>; 2489 clocks = <&cpg CPG_MOD 601>; 2490 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2491 resets = <&cpg 601>; 2492 iommus = <&ipmmu_vi0 10>; 2493 }; 2494 2495 fcpvi0: fcp@fe9af000 { 2496 compatible = "renesas,fcpv"; 2497 reg = <0 0xfe9af000 0 0x200>; 2498 clocks = <&cpg CPG_MOD 611>; 2499 power-domains = <&sysc R8A774A1_PD_A3VC>; 2500 resets = <&cpg 611>; 2501 iommus = <&ipmmu_vc0 19>; 2502 }; 2503 2504 vspb: vsp@fe960000 { 2505 compatible = "renesas,vsp2"; 2506 reg = <0 0xfe960000 0 0x8000>; 2507 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2508 clocks = <&cpg CPG_MOD 626>; 2509 power-domains = <&sysc R8A774A1_PD_A3VC>; 2510 resets = <&cpg 626>; 2511 2512 renesas,fcp = <&fcpvb0>; 2513 }; 2514 2515 vspd0: vsp@fea20000 { 2516 compatible = "renesas,vsp2"; 2517 reg = <0 0xfea20000 0 0x5000>; 2518 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2519 clocks = <&cpg CPG_MOD 623>; 2520 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2521 resets = <&cpg 623>; 2522 2523 renesas,fcp = <&fcpvd0>; 2524 }; 2525 2526 vspd1: vsp@fea28000 { 2527 compatible = "renesas,vsp2"; 2528 reg = <0 0xfea28000 0 0x5000>; 2529 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2530 clocks = <&cpg CPG_MOD 622>; 2531 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2532 resets = <&cpg 622>; 2533 2534 renesas,fcp = <&fcpvd1>; 2535 }; 2536 2537 vspd2: vsp@fea30000 { 2538 compatible = "renesas,vsp2"; 2539 reg = <0 0xfea30000 0 0x5000>; 2540 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2541 clocks = <&cpg CPG_MOD 621>; 2542 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2543 resets = <&cpg 621>; 2544 2545 renesas,fcp = <&fcpvd2>; 2546 }; 2547 2548 vspi0: vsp@fe9a0000 { 2549 compatible = "renesas,vsp2"; 2550 reg = <0 0xfe9a0000 0 0x8000>; 2551 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2552 clocks = <&cpg CPG_MOD 631>; 2553 power-domains = <&sysc R8A774A1_PD_A3VC>; 2554 resets = <&cpg 631>; 2555 2556 renesas,fcp = <&fcpvi0>; 2557 }; 2558 2559 csi20: csi2@fea80000 { 2560 compatible = "renesas,r8a774a1-csi2"; 2561 reg = <0 0xfea80000 0 0x10000>; 2562 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2563 clocks = <&cpg CPG_MOD 714>; 2564 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2565 resets = <&cpg 714>; 2566 status = "disabled"; 2567 2568 ports { 2569 #address-cells = <1>; 2570 #size-cells = <0>; 2571 2572 port@0 { 2573 reg = <0>; 2574 }; 2575 2576 port@1 { 2577 #address-cells = <1>; 2578 #size-cells = <0>; 2579 2580 reg = <1>; 2581 2582 csi20vin0: endpoint@0 { 2583 reg = <0>; 2584 remote-endpoint = <&vin0csi20>; 2585 }; 2586 csi20vin1: endpoint@1 { 2587 reg = <1>; 2588 remote-endpoint = <&vin1csi20>; 2589 }; 2590 csi20vin2: endpoint@2 { 2591 reg = <2>; 2592 remote-endpoint = <&vin2csi20>; 2593 }; 2594 csi20vin3: endpoint@3 { 2595 reg = <3>; 2596 remote-endpoint = <&vin3csi20>; 2597 }; 2598 csi20vin4: endpoint@4 { 2599 reg = <4>; 2600 remote-endpoint = <&vin4csi20>; 2601 }; 2602 csi20vin5: endpoint@5 { 2603 reg = <5>; 2604 remote-endpoint = <&vin5csi20>; 2605 }; 2606 csi20vin6: endpoint@6 { 2607 reg = <6>; 2608 remote-endpoint = <&vin6csi20>; 2609 }; 2610 csi20vin7: endpoint@7 { 2611 reg = <7>; 2612 remote-endpoint = <&vin7csi20>; 2613 }; 2614 }; 2615 }; 2616 }; 2617 2618 csi40: csi2@feaa0000 { 2619 compatible = "renesas,r8a774a1-csi2"; 2620 reg = <0 0xfeaa0000 0 0x10000>; 2621 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2622 clocks = <&cpg CPG_MOD 716>; 2623 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2624 resets = <&cpg 716>; 2625 status = "disabled"; 2626 2627 ports { 2628 #address-cells = <1>; 2629 #size-cells = <0>; 2630 2631 port@0 { 2632 reg = <0>; 2633 }; 2634 2635 port@1 { 2636 #address-cells = <1>; 2637 #size-cells = <0>; 2638 2639 reg = <1>; 2640 2641 csi40vin0: endpoint@0 { 2642 reg = <0>; 2643 remote-endpoint = <&vin0csi40>; 2644 }; 2645 csi40vin1: endpoint@1 { 2646 reg = <1>; 2647 remote-endpoint = <&vin1csi40>; 2648 }; 2649 csi40vin2: endpoint@2 { 2650 reg = <2>; 2651 remote-endpoint = <&vin2csi40>; 2652 }; 2653 csi40vin3: endpoint@3 { 2654 reg = <3>; 2655 remote-endpoint = <&vin3csi40>; 2656 }; 2657 csi40vin4: endpoint@4 { 2658 reg = <4>; 2659 remote-endpoint = <&vin4csi40>; 2660 }; 2661 csi40vin5: endpoint@5 { 2662 reg = <5>; 2663 remote-endpoint = <&vin5csi40>; 2664 }; 2665 csi40vin6: endpoint@6 { 2666 reg = <6>; 2667 remote-endpoint = <&vin6csi40>; 2668 }; 2669 csi40vin7: endpoint@7 { 2670 reg = <7>; 2671 remote-endpoint = <&vin7csi40>; 2672 }; 2673 }; 2674 2675 }; 2676 }; 2677 2678 hdmi0: hdmi@fead0000 { 2679 compatible = "renesas,r8a774a1-hdmi", 2680 "renesas,rcar-gen3-hdmi"; 2681 reg = <0 0xfead0000 0 0x10000>; 2682 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2683 clocks = <&cpg CPG_MOD 729>, 2684 <&cpg CPG_CORE R8A774A1_CLK_HDMI>; 2685 clock-names = "iahb", "isfr"; 2686 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2687 resets = <&cpg 729>; 2688 status = "disabled"; 2689 2690 ports { 2691 #address-cells = <1>; 2692 #size-cells = <0>; 2693 port@0 { 2694 reg = <0>; 2695 dw_hdmi0_in: endpoint { 2696 remote-endpoint = <&du_out_hdmi0>; 2697 }; 2698 }; 2699 port@1 { 2700 reg = <1>; 2701 }; 2702 port@2 { 2703 /* HDMI sound */ 2704 reg = <2>; 2705 }; 2706 }; 2707 }; 2708 2709 du: display@feb00000 { 2710 compatible = "renesas,du-r8a774a1"; 2711 reg = <0 0xfeb00000 0 0x70000>; 2712 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2713 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2715 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 2716 <&cpg CPG_MOD 722>; 2717 clock-names = "du.0", "du.1", "du.2"; 2718 resets = <&cpg 724>, <&cpg 722>; 2719 reset-names = "du.0", "du.2"; 2720 status = "disabled"; 2721 2722 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; 2723 2724 ports { 2725 #address-cells = <1>; 2726 #size-cells = <0>; 2727 2728 port@0 { 2729 reg = <0>; 2730 }; 2731 port@1 { 2732 reg = <1>; 2733 du_out_hdmi0: endpoint { 2734 remote-endpoint = <&dw_hdmi0_in>; 2735 }; 2736 }; 2737 port@2 { 2738 reg = <2>; 2739 du_out_lvds0: endpoint { 2740 remote-endpoint = <&lvds0_in>; 2741 }; 2742 }; 2743 }; 2744 }; 2745 2746 lvds0: lvds@feb90000 { 2747 compatible = "renesas,r8a774a1-lvds"; 2748 reg = <0 0xfeb90000 0 0x14>; 2749 clocks = <&cpg CPG_MOD 727>; 2750 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2751 resets = <&cpg 727>; 2752 status = "disabled"; 2753 2754 ports { 2755 #address-cells = <1>; 2756 #size-cells = <0>; 2757 2758 port@0 { 2759 reg = <0>; 2760 lvds0_in: endpoint { 2761 remote-endpoint = <&du_out_lvds0>; 2762 }; 2763 }; 2764 port@1 { 2765 reg = <1>; 2766 }; 2767 }; 2768 }; 2769 2770 prr: chipid@fff00044 { 2771 compatible = "renesas,prr"; 2772 reg = <0 0xfff00044 0 4>; 2773 }; 2774 }; 2775 2776 thermal-zones { 2777 sensor1_thermal: sensor1-thermal { 2778 polling-delay-passive = <250>; 2779 polling-delay = <1000>; 2780 thermal-sensors = <&tsc 0>; 2781 sustainable-power = <3874>; 2782 2783 trips { 2784 sensor1_crit: sensor1-crit { 2785 temperature = <120000>; 2786 hysteresis = <1000>; 2787 type = "critical"; 2788 }; 2789 }; 2790 }; 2791 2792 sensor2_thermal: sensor2-thermal { 2793 polling-delay-passive = <250>; 2794 polling-delay = <1000>; 2795 thermal-sensors = <&tsc 1>; 2796 sustainable-power = <3874>; 2797 2798 trips { 2799 sensor2_crit: sensor2-crit { 2800 temperature = <120000>; 2801 hysteresis = <1000>; 2802 type = "critical"; 2803 }; 2804 }; 2805 }; 2806 2807 sensor3_thermal: sensor3-thermal { 2808 polling-delay-passive = <250>; 2809 polling-delay = <1000>; 2810 thermal-sensors = <&tsc 2>; 2811 sustainable-power = <3874>; 2812 2813 cooling-maps { 2814 map0 { 2815 trip = <&target>; 2816 cooling-device = <&a57_0 0 2>; 2817 contribution = <1024>; 2818 }; 2819 map1 { 2820 trip = <&target>; 2821 cooling-device = <&a53_0 0 2>; 2822 contribution = <1024>; 2823 }; 2824 }; 2825 trips { 2826 target: trip-point1 { 2827 temperature = <100000>; 2828 hysteresis = <1000>; 2829 type = "passive"; 2830 }; 2831 2832 sensor3_crit: sensor3-crit { 2833 temperature = <120000>; 2834 hysteresis = <1000>; 2835 type = "critical"; 2836 }; 2837 }; 2838 }; 2839 }; 2840 2841 timer { 2842 compatible = "arm,armv8-timer"; 2843 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2844 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2845 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2846 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2847 }; 2848 2849 /* External USB clocks - can be overridden by the board */ 2850 usb3s0_clk: usb3s0 { 2851 compatible = "fixed-clock"; 2852 #clock-cells = <0>; 2853 clock-frequency = <0>; 2854 }; 2855 2856 usb_extal_clk: usb_extal { 2857 compatible = "fixed-clock"; 2858 #clock-cells = <0>; 2859 clock-frequency = <0>; 2860 }; 2861}; 2862