1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774a1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774a1-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a774a1"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &i2c0; 22 i2c1 = &i2c1; 23 i2c2 = &i2c2; 24 i2c3 = &i2c3; 25 i2c4 = &i2c4; 26 i2c5 = &i2c5; 27 i2c6 = &i2c6; 28 i2c7 = &iic_pmic; 29 }; 30 31 /* 32 * The external audio clocks are configured as 0 Hz fixed frequency 33 * clocks by default. 34 * Boards that provide audio clocks should override them. 35 */ 36 audio_clk_a: audio_clk_a { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 audio_clk_b: audio_clk_b { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <0>; 46 }; 47 48 audio_clk_c: audio_clk_c { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <0>; 52 }; 53 54 /* External CAN clock - to be overridden by boards that provide it */ 55 can_clk: can { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 59 }; 60 61 cluster0_opp: opp-table-0 { 62 compatible = "operating-points-v2"; 63 opp-shared; 64 65 opp-500000000 { 66 opp-hz = /bits/ 64 <500000000>; 67 opp-microvolt = <820000>; 68 clock-latency-ns = <300000>; 69 }; 70 opp-1000000000 { 71 opp-hz = /bits/ 64 <1000000000>; 72 opp-microvolt = <820000>; 73 clock-latency-ns = <300000>; 74 }; 75 opp-1500000000 { 76 opp-hz = /bits/ 64 <1500000000>; 77 opp-microvolt = <820000>; 78 clock-latency-ns = <300000>; 79 opp-suspend; 80 }; 81 }; 82 83 cluster1_opp: opp-table-1 { 84 compatible = "operating-points-v2"; 85 opp-shared; 86 87 opp-800000000 { 88 opp-hz = /bits/ 64 <800000000>; 89 opp-microvolt = <820000>; 90 clock-latency-ns = <300000>; 91 }; 92 opp-1000000000 { 93 opp-hz = /bits/ 64 <1000000000>; 94 opp-microvolt = <820000>; 95 clock-latency-ns = <300000>; 96 }; 97 opp-1200000000 { 98 opp-hz = /bits/ 64 <1200000000>; 99 opp-microvolt = <820000>; 100 clock-latency-ns = <300000>; 101 }; 102 }; 103 104 cpus { 105 #address-cells = <1>; 106 #size-cells = <0>; 107 108 cpu-map { 109 cluster0 { 110 core0 { 111 cpu = <&a57_0>; 112 }; 113 core1 { 114 cpu = <&a57_1>; 115 }; 116 }; 117 118 cluster1 { 119 core0 { 120 cpu = <&a53_0>; 121 }; 122 core1 { 123 cpu = <&a53_1>; 124 }; 125 core2 { 126 cpu = <&a53_2>; 127 }; 128 core3 { 129 cpu = <&a53_3>; 130 }; 131 }; 132 }; 133 134 a57_0: cpu@0 { 135 compatible = "arm,cortex-a57"; 136 reg = <0x0>; 137 device_type = "cpu"; 138 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; 139 next-level-cache = <&L2_CA57>; 140 enable-method = "psci"; 141 dynamic-power-coefficient = <854>; 142 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 143 operating-points-v2 = <&cluster0_opp>; 144 capacity-dmips-mhz = <1024>; 145 #cooling-cells = <2>; 146 }; 147 148 a57_1: cpu@1 { 149 compatible = "arm,cortex-a57"; 150 reg = <0x1>; 151 device_type = "cpu"; 152 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; 153 next-level-cache = <&L2_CA57>; 154 enable-method = "psci"; 155 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 156 operating-points-v2 = <&cluster0_opp>; 157 capacity-dmips-mhz = <1024>; 158 #cooling-cells = <2>; 159 }; 160 161 a53_0: cpu@100 { 162 compatible = "arm,cortex-a53"; 163 reg = <0x100>; 164 device_type = "cpu"; 165 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; 166 next-level-cache = <&L2_CA53>; 167 enable-method = "psci"; 168 #cooling-cells = <2>; 169 dynamic-power-coefficient = <277>; 170 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 171 operating-points-v2 = <&cluster1_opp>; 172 capacity-dmips-mhz = <560>; 173 }; 174 175 a53_1: cpu@101 { 176 compatible = "arm,cortex-a53"; 177 reg = <0x101>; 178 device_type = "cpu"; 179 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; 180 next-level-cache = <&L2_CA53>; 181 enable-method = "psci"; 182 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 183 operating-points-v2 = <&cluster1_opp>; 184 capacity-dmips-mhz = <560>; 185 }; 186 187 a53_2: cpu@102 { 188 compatible = "arm,cortex-a53"; 189 reg = <0x102>; 190 device_type = "cpu"; 191 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; 192 next-level-cache = <&L2_CA53>; 193 enable-method = "psci"; 194 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 195 operating-points-v2 = <&cluster1_opp>; 196 capacity-dmips-mhz = <560>; 197 }; 198 199 a53_3: cpu@103 { 200 compatible = "arm,cortex-a53"; 201 reg = <0x103>; 202 device_type = "cpu"; 203 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; 204 next-level-cache = <&L2_CA53>; 205 enable-method = "psci"; 206 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 207 operating-points-v2 = <&cluster1_opp>; 208 capacity-dmips-mhz = <560>; 209 }; 210 211 L2_CA57: cache-controller-0 { 212 compatible = "cache"; 213 power-domains = <&sysc R8A774A1_PD_CA57_SCU>; 214 cache-unified; 215 cache-level = <2>; 216 }; 217 218 L2_CA53: cache-controller-1 { 219 compatible = "cache"; 220 power-domains = <&sysc R8A774A1_PD_CA53_SCU>; 221 cache-unified; 222 cache-level = <2>; 223 }; 224 }; 225 226 extal_clk: extal { 227 compatible = "fixed-clock"; 228 #clock-cells = <0>; 229 /* This value must be overridden by the board */ 230 clock-frequency = <0>; 231 }; 232 233 extalr_clk: extalr { 234 compatible = "fixed-clock"; 235 #clock-cells = <0>; 236 /* This value must be overridden by the board */ 237 clock-frequency = <0>; 238 }; 239 240 /* External PCIe clock - can be overridden by the board */ 241 pcie_bus_clk: pcie_bus { 242 compatible = "fixed-clock"; 243 #clock-cells = <0>; 244 clock-frequency = <0>; 245 }; 246 247 pmu_a53 { 248 compatible = "arm,cortex-a53-pmu"; 249 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 250 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 251 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 252 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 253 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 254 }; 255 256 pmu_a57 { 257 compatible = "arm,cortex-a57-pmu"; 258 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 259 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 260 interrupt-affinity = <&a57_0>, <&a57_1>; 261 }; 262 263 psci { 264 compatible = "arm,psci-1.0", "arm,psci-0.2"; 265 method = "smc"; 266 }; 267 268 /* External SCIF clock - to be overridden by boards that provide it */ 269 scif_clk: scif { 270 compatible = "fixed-clock"; 271 #clock-cells = <0>; 272 clock-frequency = <0>; 273 }; 274 275 soc { 276 compatible = "simple-bus"; 277 interrupt-parent = <&gic>; 278 #address-cells = <2>; 279 #size-cells = <2>; 280 ranges; 281 282 rwdt: watchdog@e6020000 { 283 compatible = "renesas,r8a774a1-wdt", 284 "renesas,rcar-gen3-wdt"; 285 reg = <0 0xe6020000 0 0x0c>; 286 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&cpg CPG_MOD 402>; 288 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 289 resets = <&cpg 402>; 290 status = "disabled"; 291 }; 292 293 gpio0: gpio@e6050000 { 294 compatible = "renesas,gpio-r8a774a1", 295 "renesas,rcar-gen3-gpio"; 296 reg = <0 0xe6050000 0 0x50>; 297 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 298 #gpio-cells = <2>; 299 gpio-controller; 300 gpio-ranges = <&pfc 0 0 16>; 301 #interrupt-cells = <2>; 302 interrupt-controller; 303 clocks = <&cpg CPG_MOD 912>; 304 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 305 resets = <&cpg 912>; 306 }; 307 308 gpio1: gpio@e6051000 { 309 compatible = "renesas,gpio-r8a774a1", 310 "renesas,rcar-gen3-gpio"; 311 reg = <0 0xe6051000 0 0x50>; 312 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 313 #gpio-cells = <2>; 314 gpio-controller; 315 gpio-ranges = <&pfc 0 32 29>; 316 #interrupt-cells = <2>; 317 interrupt-controller; 318 clocks = <&cpg CPG_MOD 911>; 319 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 320 resets = <&cpg 911>; 321 }; 322 323 gpio2: gpio@e6052000 { 324 compatible = "renesas,gpio-r8a774a1", 325 "renesas,rcar-gen3-gpio"; 326 reg = <0 0xe6052000 0 0x50>; 327 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 328 #gpio-cells = <2>; 329 gpio-controller; 330 gpio-ranges = <&pfc 0 64 15>; 331 #interrupt-cells = <2>; 332 interrupt-controller; 333 clocks = <&cpg CPG_MOD 910>; 334 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 335 resets = <&cpg 910>; 336 }; 337 338 gpio3: gpio@e6053000 { 339 compatible = "renesas,gpio-r8a774a1", 340 "renesas,rcar-gen3-gpio"; 341 reg = <0 0xe6053000 0 0x50>; 342 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 343 #gpio-cells = <2>; 344 gpio-controller; 345 gpio-ranges = <&pfc 0 96 16>; 346 #interrupt-cells = <2>; 347 interrupt-controller; 348 clocks = <&cpg CPG_MOD 909>; 349 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 350 resets = <&cpg 909>; 351 }; 352 353 gpio4: gpio@e6054000 { 354 compatible = "renesas,gpio-r8a774a1", 355 "renesas,rcar-gen3-gpio"; 356 reg = <0 0xe6054000 0 0x50>; 357 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 358 #gpio-cells = <2>; 359 gpio-controller; 360 gpio-ranges = <&pfc 0 128 18>; 361 #interrupt-cells = <2>; 362 interrupt-controller; 363 clocks = <&cpg CPG_MOD 908>; 364 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 365 resets = <&cpg 908>; 366 }; 367 368 gpio5: gpio@e6055000 { 369 compatible = "renesas,gpio-r8a774a1", 370 "renesas,rcar-gen3-gpio"; 371 reg = <0 0xe6055000 0 0x50>; 372 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 373 #gpio-cells = <2>; 374 gpio-controller; 375 gpio-ranges = <&pfc 0 160 26>; 376 #interrupt-cells = <2>; 377 interrupt-controller; 378 clocks = <&cpg CPG_MOD 907>; 379 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 380 resets = <&cpg 907>; 381 }; 382 383 gpio6: gpio@e6055400 { 384 compatible = "renesas,gpio-r8a774a1", 385 "renesas,rcar-gen3-gpio"; 386 reg = <0 0xe6055400 0 0x50>; 387 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 388 #gpio-cells = <2>; 389 gpio-controller; 390 gpio-ranges = <&pfc 0 192 32>; 391 #interrupt-cells = <2>; 392 interrupt-controller; 393 clocks = <&cpg CPG_MOD 906>; 394 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 395 resets = <&cpg 906>; 396 }; 397 398 gpio7: gpio@e6055800 { 399 compatible = "renesas,gpio-r8a774a1", 400 "renesas,rcar-gen3-gpio"; 401 reg = <0 0xe6055800 0 0x50>; 402 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 403 #gpio-cells = <2>; 404 gpio-controller; 405 gpio-ranges = <&pfc 0 224 4>; 406 #interrupt-cells = <2>; 407 interrupt-controller; 408 clocks = <&cpg CPG_MOD 905>; 409 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 410 resets = <&cpg 905>; 411 }; 412 413 pfc: pinctrl@e6060000 { 414 compatible = "renesas,pfc-r8a774a1"; 415 reg = <0 0xe6060000 0 0x50c>; 416 }; 417 418 cmt0: timer@e60f0000 { 419 compatible = "renesas,r8a774a1-cmt0", 420 "renesas,rcar-gen3-cmt0"; 421 reg = <0 0xe60f0000 0 0x1004>; 422 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&cpg CPG_MOD 303>; 425 clock-names = "fck"; 426 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 427 resets = <&cpg 303>; 428 status = "disabled"; 429 }; 430 431 cmt1: timer@e6130000 { 432 compatible = "renesas,r8a774a1-cmt1", 433 "renesas,rcar-gen3-cmt1"; 434 reg = <0 0xe6130000 0 0x1004>; 435 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&cpg CPG_MOD 302>; 444 clock-names = "fck"; 445 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 446 resets = <&cpg 302>; 447 status = "disabled"; 448 }; 449 450 cmt2: timer@e6140000 { 451 compatible = "renesas,r8a774a1-cmt1", 452 "renesas,rcar-gen3-cmt1"; 453 reg = <0 0xe6140000 0 0x1004>; 454 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&cpg CPG_MOD 301>; 463 clock-names = "fck"; 464 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 465 resets = <&cpg 301>; 466 status = "disabled"; 467 }; 468 469 cmt3: timer@e6148000 { 470 compatible = "renesas,r8a774a1-cmt1", 471 "renesas,rcar-gen3-cmt1"; 472 reg = <0 0xe6148000 0 0x1004>; 473 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&cpg CPG_MOD 300>; 482 clock-names = "fck"; 483 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 484 resets = <&cpg 300>; 485 status = "disabled"; 486 }; 487 488 cpg: clock-controller@e6150000 { 489 compatible = "renesas,r8a774a1-cpg-mssr"; 490 reg = <0 0xe6150000 0 0x0bb0>; 491 clocks = <&extal_clk>, <&extalr_clk>; 492 clock-names = "extal", "extalr"; 493 #clock-cells = <2>; 494 #power-domain-cells = <0>; 495 #reset-cells = <1>; 496 }; 497 498 rst: reset-controller@e6160000 { 499 compatible = "renesas,r8a774a1-rst"; 500 reg = <0 0xe6160000 0 0x018c>; 501 }; 502 503 sysc: system-controller@e6180000 { 504 compatible = "renesas,r8a774a1-sysc"; 505 reg = <0 0xe6180000 0 0x0400>; 506 #power-domain-cells = <1>; 507 }; 508 509 tsc: thermal@e6198000 { 510 compatible = "renesas,r8a774a1-thermal"; 511 reg = <0 0xe6198000 0 0x100>, 512 <0 0xe61a0000 0 0x100>, 513 <0 0xe61a8000 0 0x100>; 514 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&cpg CPG_MOD 522>; 518 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 519 resets = <&cpg 522>; 520 #thermal-sensor-cells = <1>; 521 }; 522 523 intc_ex: interrupt-controller@e61c0000 { 524 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; 525 #interrupt-cells = <2>; 526 interrupt-controller; 527 reg = <0 0xe61c0000 0 0x200>; 528 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&cpg CPG_MOD 407>; 535 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 536 resets = <&cpg 407>; 537 }; 538 539 tmu0: timer@e61e0000 { 540 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 541 reg = <0 0xe61e0000 0 0x30>; 542 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&cpg CPG_MOD 125>; 546 clock-names = "fck"; 547 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 548 resets = <&cpg 125>; 549 status = "disabled"; 550 }; 551 552 tmu1: timer@e6fc0000 { 553 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 554 reg = <0 0xe6fc0000 0 0x30>; 555 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&cpg CPG_MOD 124>; 559 clock-names = "fck"; 560 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 561 resets = <&cpg 124>; 562 status = "disabled"; 563 }; 564 565 tmu2: timer@e6fd0000 { 566 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 567 reg = <0 0xe6fd0000 0 0x30>; 568 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&cpg CPG_MOD 123>; 572 clock-names = "fck"; 573 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 574 resets = <&cpg 123>; 575 status = "disabled"; 576 }; 577 578 tmu3: timer@e6fe0000 { 579 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 580 reg = <0 0xe6fe0000 0 0x30>; 581 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&cpg CPG_MOD 122>; 585 clock-names = "fck"; 586 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 587 resets = <&cpg 122>; 588 status = "disabled"; 589 }; 590 591 tmu4: timer@ffc00000 { 592 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 593 reg = <0 0xffc00000 0 0x30>; 594 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&cpg CPG_MOD 121>; 598 clock-names = "fck"; 599 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 600 resets = <&cpg 121>; 601 status = "disabled"; 602 }; 603 604 i2c0: i2c@e6500000 { 605 #address-cells = <1>; 606 #size-cells = <0>; 607 compatible = "renesas,i2c-r8a774a1", 608 "renesas,rcar-gen3-i2c"; 609 reg = <0 0xe6500000 0 0x40>; 610 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&cpg CPG_MOD 931>; 612 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 613 resets = <&cpg 931>; 614 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 615 <&dmac2 0x91>, <&dmac2 0x90>; 616 dma-names = "tx", "rx", "tx", "rx"; 617 i2c-scl-internal-delay-ns = <110>; 618 status = "disabled"; 619 }; 620 621 i2c1: i2c@e6508000 { 622 #address-cells = <1>; 623 #size-cells = <0>; 624 compatible = "renesas,i2c-r8a774a1", 625 "renesas,rcar-gen3-i2c"; 626 reg = <0 0xe6508000 0 0x40>; 627 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&cpg CPG_MOD 930>; 629 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 630 resets = <&cpg 930>; 631 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 632 <&dmac2 0x93>, <&dmac2 0x92>; 633 dma-names = "tx", "rx", "tx", "rx"; 634 i2c-scl-internal-delay-ns = <6>; 635 status = "disabled"; 636 }; 637 638 i2c2: i2c@e6510000 { 639 #address-cells = <1>; 640 #size-cells = <0>; 641 compatible = "renesas,i2c-r8a774a1", 642 "renesas,rcar-gen3-i2c"; 643 reg = <0 0xe6510000 0 0x40>; 644 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&cpg CPG_MOD 929>; 646 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 647 resets = <&cpg 929>; 648 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 649 <&dmac2 0x95>, <&dmac2 0x94>; 650 dma-names = "tx", "rx", "tx", "rx"; 651 i2c-scl-internal-delay-ns = <6>; 652 status = "disabled"; 653 }; 654 655 i2c3: i2c@e66d0000 { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 compatible = "renesas,i2c-r8a774a1", 659 "renesas,rcar-gen3-i2c"; 660 reg = <0 0xe66d0000 0 0x40>; 661 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&cpg CPG_MOD 928>; 663 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 664 resets = <&cpg 928>; 665 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 666 dma-names = "tx", "rx"; 667 i2c-scl-internal-delay-ns = <110>; 668 status = "disabled"; 669 }; 670 671 i2c4: i2c@e66d8000 { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 compatible = "renesas,i2c-r8a774a1", 675 "renesas,rcar-gen3-i2c"; 676 reg = <0 0xe66d8000 0 0x40>; 677 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&cpg CPG_MOD 927>; 679 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 680 resets = <&cpg 927>; 681 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 682 dma-names = "tx", "rx"; 683 i2c-scl-internal-delay-ns = <110>; 684 status = "disabled"; 685 }; 686 687 i2c5: i2c@e66e0000 { 688 #address-cells = <1>; 689 #size-cells = <0>; 690 compatible = "renesas,i2c-r8a774a1", 691 "renesas,rcar-gen3-i2c"; 692 reg = <0 0xe66e0000 0 0x40>; 693 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&cpg CPG_MOD 919>; 695 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 696 resets = <&cpg 919>; 697 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 698 dma-names = "tx", "rx"; 699 i2c-scl-internal-delay-ns = <110>; 700 status = "disabled"; 701 }; 702 703 i2c6: i2c@e66e8000 { 704 #address-cells = <1>; 705 #size-cells = <0>; 706 compatible = "renesas,i2c-r8a774a1", 707 "renesas,rcar-gen3-i2c"; 708 reg = <0 0xe66e8000 0 0x40>; 709 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&cpg CPG_MOD 918>; 711 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 712 resets = <&cpg 918>; 713 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 714 dma-names = "tx", "rx"; 715 i2c-scl-internal-delay-ns = <6>; 716 status = "disabled"; 717 }; 718 719 iic_pmic: i2c@e60b0000 { 720 #address-cells = <1>; 721 #size-cells = <0>; 722 compatible = "renesas,iic-r8a774a1", 723 "renesas,rcar-gen3-iic", 724 "renesas,rmobile-iic"; 725 reg = <0 0xe60b0000 0 0x425>; 726 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&cpg CPG_MOD 926>; 728 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 729 resets = <&cpg 926>; 730 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 731 dma-names = "tx", "rx"; 732 status = "disabled"; 733 }; 734 735 hscif0: serial@e6540000 { 736 compatible = "renesas,hscif-r8a774a1", 737 "renesas,rcar-gen3-hscif", 738 "renesas,hscif"; 739 reg = <0 0xe6540000 0 0x60>; 740 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&cpg CPG_MOD 520>, 742 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 743 <&scif_clk>; 744 clock-names = "fck", "brg_int", "scif_clk"; 745 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 746 <&dmac2 0x31>, <&dmac2 0x30>; 747 dma-names = "tx", "rx", "tx", "rx"; 748 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 749 resets = <&cpg 520>; 750 status = "disabled"; 751 }; 752 753 hscif1: serial@e6550000 { 754 compatible = "renesas,hscif-r8a774a1", 755 "renesas,rcar-gen3-hscif", 756 "renesas,hscif"; 757 reg = <0 0xe6550000 0 0x60>; 758 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&cpg CPG_MOD 519>, 760 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 761 <&scif_clk>; 762 clock-names = "fck", "brg_int", "scif_clk"; 763 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 764 <&dmac2 0x33>, <&dmac2 0x32>; 765 dma-names = "tx", "rx", "tx", "rx"; 766 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 767 resets = <&cpg 519>; 768 status = "disabled"; 769 }; 770 771 hscif2: serial@e6560000 { 772 compatible = "renesas,hscif-r8a774a1", 773 "renesas,rcar-gen3-hscif", 774 "renesas,hscif"; 775 reg = <0 0xe6560000 0 0x60>; 776 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&cpg CPG_MOD 518>, 778 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 779 <&scif_clk>; 780 clock-names = "fck", "brg_int", "scif_clk"; 781 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 782 <&dmac2 0x35>, <&dmac2 0x34>; 783 dma-names = "tx", "rx", "tx", "rx"; 784 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 785 resets = <&cpg 518>; 786 status = "disabled"; 787 }; 788 789 hscif3: serial@e66a0000 { 790 compatible = "renesas,hscif-r8a774a1", 791 "renesas,rcar-gen3-hscif", 792 "renesas,hscif"; 793 reg = <0 0xe66a0000 0 0x60>; 794 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&cpg CPG_MOD 517>, 796 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 797 <&scif_clk>; 798 clock-names = "fck", "brg_int", "scif_clk"; 799 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 800 dma-names = "tx", "rx"; 801 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 802 resets = <&cpg 517>; 803 status = "disabled"; 804 }; 805 806 hscif4: serial@e66b0000 { 807 compatible = "renesas,hscif-r8a774a1", 808 "renesas,rcar-gen3-hscif", 809 "renesas,hscif"; 810 reg = <0 0xe66b0000 0 0x60>; 811 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&cpg CPG_MOD 516>, 813 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 814 <&scif_clk>; 815 clock-names = "fck", "brg_int", "scif_clk"; 816 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 817 dma-names = "tx", "rx"; 818 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 819 resets = <&cpg 516>; 820 status = "disabled"; 821 }; 822 823 hsusb: usb@e6590000 { 824 compatible = "renesas,usbhs-r8a774a1", 825 "renesas,rcar-gen3-usbhs"; 826 reg = <0 0xe6590000 0 0x200>; 827 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 828 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 829 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 830 <&usb_dmac1 0>, <&usb_dmac1 1>; 831 dma-names = "ch0", "ch1", "ch2", "ch3"; 832 renesas,buswait = <11>; 833 phys = <&usb2_phy0 3>; 834 phy-names = "usb"; 835 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 836 resets = <&cpg 704>, <&cpg 703>; 837 status = "disabled"; 838 }; 839 840 usb2_clksel: clock-controller@e6590630 { 841 compatible = "renesas,r8a774a1-rcar-usb2-clock-sel", 842 "renesas,rcar-gen3-usb2-clock-sel"; 843 reg = <0 0xe6590630 0 0x02>; 844 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, 845 <&usb_extal_clk>, <&usb3s0_clk>; 846 clock-names = "ehci_ohci", "hs-usb-if", 847 "usb_extal", "usb_xtal"; 848 #clock-cells = <0>; 849 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 850 resets = <&cpg 703>, <&cpg 704>; 851 reset-names = "ehci_ohci", "hs-usb-if"; 852 status = "disabled"; 853 }; 854 855 usb_dmac0: dma-controller@e65a0000 { 856 compatible = "renesas,r8a774a1-usb-dmac", 857 "renesas,usb-dmac"; 858 reg = <0 0xe65a0000 0 0x100>; 859 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 861 interrupt-names = "ch0", "ch1"; 862 clocks = <&cpg CPG_MOD 330>; 863 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 864 resets = <&cpg 330>; 865 #dma-cells = <1>; 866 dma-channels = <2>; 867 }; 868 869 usb_dmac1: dma-controller@e65b0000 { 870 compatible = "renesas,r8a774a1-usb-dmac", 871 "renesas,usb-dmac"; 872 reg = <0 0xe65b0000 0 0x100>; 873 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 875 interrupt-names = "ch0", "ch1"; 876 clocks = <&cpg CPG_MOD 331>; 877 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 878 resets = <&cpg 331>; 879 #dma-cells = <1>; 880 dma-channels = <2>; 881 }; 882 883 usb3_phy0: usb-phy@e65ee000 { 884 compatible = "renesas,r8a774a1-usb3-phy", 885 "renesas,rcar-gen3-usb3-phy"; 886 reg = <0 0xe65ee000 0 0x90>; 887 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 888 <&usb_extal_clk>; 889 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 890 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 891 resets = <&cpg 328>; 892 #phy-cells = <0>; 893 status = "disabled"; 894 }; 895 896 dmac0: dma-controller@e6700000 { 897 compatible = "renesas,dmac-r8a774a1", 898 "renesas,rcar-dmac"; 899 reg = <0 0xe6700000 0 0x10000>; 900 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 917 interrupt-names = "error", 918 "ch0", "ch1", "ch2", "ch3", 919 "ch4", "ch5", "ch6", "ch7", 920 "ch8", "ch9", "ch10", "ch11", 921 "ch12", "ch13", "ch14", "ch15"; 922 clocks = <&cpg CPG_MOD 219>; 923 clock-names = "fck"; 924 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 925 resets = <&cpg 219>; 926 #dma-cells = <1>; 927 dma-channels = <16>; 928 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 929 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 930 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 931 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 932 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 933 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 934 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 935 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 936 }; 937 938 dmac1: dma-controller@e7300000 { 939 compatible = "renesas,dmac-r8a774a1", 940 "renesas,rcar-dmac"; 941 reg = <0 0xe7300000 0 0x10000>; 942 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 959 interrupt-names = "error", 960 "ch0", "ch1", "ch2", "ch3", 961 "ch4", "ch5", "ch6", "ch7", 962 "ch8", "ch9", "ch10", "ch11", 963 "ch12", "ch13", "ch14", "ch15"; 964 clocks = <&cpg CPG_MOD 218>; 965 clock-names = "fck"; 966 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 967 resets = <&cpg 218>; 968 #dma-cells = <1>; 969 dma-channels = <16>; 970 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 971 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 972 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 973 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 974 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 975 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 976 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 977 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 978 }; 979 980 dmac2: dma-controller@e7310000 { 981 compatible = "renesas,dmac-r8a774a1", 982 "renesas,rcar-dmac"; 983 reg = <0 0xe7310000 0 0x10000>; 984 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1001 interrupt-names = "error", 1002 "ch0", "ch1", "ch2", "ch3", 1003 "ch4", "ch5", "ch6", "ch7", 1004 "ch8", "ch9", "ch10", "ch11", 1005 "ch12", "ch13", "ch14", "ch15"; 1006 clocks = <&cpg CPG_MOD 217>; 1007 clock-names = "fck"; 1008 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1009 resets = <&cpg 217>; 1010 #dma-cells = <1>; 1011 dma-channels = <16>; 1012 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1013 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1014 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1015 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1016 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1017 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1018 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1019 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1020 }; 1021 1022 ipmmu_ds0: iommu@e6740000 { 1023 compatible = "renesas,ipmmu-r8a774a1"; 1024 reg = <0 0xe6740000 0 0x1000>; 1025 renesas,ipmmu-main = <&ipmmu_mm 0>; 1026 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1027 #iommu-cells = <1>; 1028 }; 1029 1030 ipmmu_ds1: iommu@e7740000 { 1031 compatible = "renesas,ipmmu-r8a774a1"; 1032 reg = <0 0xe7740000 0 0x1000>; 1033 renesas,ipmmu-main = <&ipmmu_mm 1>; 1034 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1035 #iommu-cells = <1>; 1036 }; 1037 1038 ipmmu_hc: iommu@e6570000 { 1039 compatible = "renesas,ipmmu-r8a774a1"; 1040 reg = <0 0xe6570000 0 0x1000>; 1041 renesas,ipmmu-main = <&ipmmu_mm 2>; 1042 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1043 #iommu-cells = <1>; 1044 }; 1045 1046 ipmmu_mm: iommu@e67b0000 { 1047 compatible = "renesas,ipmmu-r8a774a1"; 1048 reg = <0 0xe67b0000 0 0x1000>; 1049 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1051 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1052 #iommu-cells = <1>; 1053 }; 1054 1055 ipmmu_mp: iommu@ec670000 { 1056 compatible = "renesas,ipmmu-r8a774a1"; 1057 reg = <0 0xec670000 0 0x1000>; 1058 renesas,ipmmu-main = <&ipmmu_mm 4>; 1059 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1060 #iommu-cells = <1>; 1061 }; 1062 1063 ipmmu_pv0: iommu@fd800000 { 1064 compatible = "renesas,ipmmu-r8a774a1"; 1065 reg = <0 0xfd800000 0 0x1000>; 1066 renesas,ipmmu-main = <&ipmmu_mm 5>; 1067 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1068 #iommu-cells = <1>; 1069 }; 1070 1071 ipmmu_pv1: iommu@fd950000 { 1072 compatible = "renesas,ipmmu-r8a774a1"; 1073 reg = <0 0xfd950000 0 0x1000>; 1074 renesas,ipmmu-main = <&ipmmu_mm 6>; 1075 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1076 #iommu-cells = <1>; 1077 }; 1078 1079 ipmmu_vc0: iommu@fe6b0000 { 1080 compatible = "renesas,ipmmu-r8a774a1"; 1081 reg = <0 0xfe6b0000 0 0x1000>; 1082 renesas,ipmmu-main = <&ipmmu_mm 8>; 1083 power-domains = <&sysc R8A774A1_PD_A3VC>; 1084 #iommu-cells = <1>; 1085 }; 1086 1087 ipmmu_vi0: iommu@febd0000 { 1088 compatible = "renesas,ipmmu-r8a774a1"; 1089 reg = <0 0xfebd0000 0 0x1000>; 1090 renesas,ipmmu-main = <&ipmmu_mm 9>; 1091 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1092 #iommu-cells = <1>; 1093 }; 1094 1095 avb: ethernet@e6800000 { 1096 compatible = "renesas,etheravb-r8a774a1", 1097 "renesas,etheravb-rcar-gen3"; 1098 reg = <0 0xe6800000 0 0x800>; 1099 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1124 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1125 "ch4", "ch5", "ch6", "ch7", 1126 "ch8", "ch9", "ch10", "ch11", 1127 "ch12", "ch13", "ch14", "ch15", 1128 "ch16", "ch17", "ch18", "ch19", 1129 "ch20", "ch21", "ch22", "ch23", 1130 "ch24"; 1131 clocks = <&cpg CPG_MOD 812>; 1132 clock-names = "fck"; 1133 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1134 resets = <&cpg 812>; 1135 phy-mode = "rgmii"; 1136 rx-internal-delay-ps = <0>; 1137 tx-internal-delay-ps = <0>; 1138 iommus = <&ipmmu_ds0 16>; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 status = "disabled"; 1142 }; 1143 1144 can0: can@e6c30000 { 1145 compatible = "renesas,can-r8a774a1", 1146 "renesas,rcar-gen3-can"; 1147 reg = <0 0xe6c30000 0 0x1000>; 1148 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&cpg CPG_MOD 916>, 1150 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1151 <&can_clk>; 1152 clock-names = "clkp1", "clkp2", "can_clk"; 1153 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1154 assigned-clock-rates = <40000000>; 1155 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1156 resets = <&cpg 916>; 1157 status = "disabled"; 1158 }; 1159 1160 can1: can@e6c38000 { 1161 compatible = "renesas,can-r8a774a1", 1162 "renesas,rcar-gen3-can"; 1163 reg = <0 0xe6c38000 0 0x1000>; 1164 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1165 clocks = <&cpg CPG_MOD 915>, 1166 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1167 <&can_clk>; 1168 clock-names = "clkp1", "clkp2", "can_clk"; 1169 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1170 assigned-clock-rates = <40000000>; 1171 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1172 resets = <&cpg 915>; 1173 status = "disabled"; 1174 }; 1175 1176 canfd: can@e66c0000 { 1177 compatible = "renesas,r8a774a1-canfd", 1178 "renesas,rcar-gen3-canfd"; 1179 reg = <0 0xe66c0000 0 0x8000>; 1180 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&cpg CPG_MOD 914>, 1183 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1184 <&can_clk>; 1185 clock-names = "fck", "canfd", "can_clk"; 1186 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1187 assigned-clock-rates = <40000000>; 1188 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1189 resets = <&cpg 914>; 1190 status = "disabled"; 1191 1192 channel0 { 1193 status = "disabled"; 1194 }; 1195 1196 channel1 { 1197 status = "disabled"; 1198 }; 1199 }; 1200 1201 pwm0: pwm@e6e30000 { 1202 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1203 reg = <0 0xe6e30000 0 0x8>; 1204 #pwm-cells = <2>; 1205 clocks = <&cpg CPG_MOD 523>; 1206 resets = <&cpg 523>; 1207 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1208 status = "disabled"; 1209 }; 1210 1211 pwm1: pwm@e6e31000 { 1212 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1213 reg = <0 0xe6e31000 0 0x8>; 1214 #pwm-cells = <2>; 1215 clocks = <&cpg CPG_MOD 523>; 1216 resets = <&cpg 523>; 1217 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1218 status = "disabled"; 1219 }; 1220 1221 pwm2: pwm@e6e32000 { 1222 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1223 reg = <0 0xe6e32000 0 0x8>; 1224 #pwm-cells = <2>; 1225 clocks = <&cpg CPG_MOD 523>; 1226 resets = <&cpg 523>; 1227 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1228 status = "disabled"; 1229 }; 1230 1231 pwm3: pwm@e6e33000 { 1232 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1233 reg = <0 0xe6e33000 0 0x8>; 1234 #pwm-cells = <2>; 1235 clocks = <&cpg CPG_MOD 523>; 1236 resets = <&cpg 523>; 1237 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1238 status = "disabled"; 1239 }; 1240 1241 pwm4: pwm@e6e34000 { 1242 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1243 reg = <0 0xe6e34000 0 0x8>; 1244 #pwm-cells = <2>; 1245 clocks = <&cpg CPG_MOD 523>; 1246 resets = <&cpg 523>; 1247 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1248 status = "disabled"; 1249 }; 1250 1251 pwm5: pwm@e6e35000 { 1252 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1253 reg = <0 0xe6e35000 0 0x8>; 1254 #pwm-cells = <2>; 1255 clocks = <&cpg CPG_MOD 523>; 1256 resets = <&cpg 523>; 1257 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1258 status = "disabled"; 1259 }; 1260 1261 pwm6: pwm@e6e36000 { 1262 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1263 reg = <0 0xe6e36000 0 0x8>; 1264 #pwm-cells = <2>; 1265 clocks = <&cpg CPG_MOD 523>; 1266 resets = <&cpg 523>; 1267 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1268 status = "disabled"; 1269 }; 1270 1271 scif0: serial@e6e60000 { 1272 compatible = "renesas,scif-r8a774a1", 1273 "renesas,rcar-gen3-scif", "renesas,scif"; 1274 reg = <0 0xe6e60000 0 0x40>; 1275 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1276 clocks = <&cpg CPG_MOD 207>, 1277 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1278 <&scif_clk>; 1279 clock-names = "fck", "brg_int", "scif_clk"; 1280 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1281 <&dmac2 0x51>, <&dmac2 0x50>; 1282 dma-names = "tx", "rx", "tx", "rx"; 1283 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1284 resets = <&cpg 207>; 1285 status = "disabled"; 1286 }; 1287 1288 scif1: serial@e6e68000 { 1289 compatible = "renesas,scif-r8a774a1", 1290 "renesas,rcar-gen3-scif", "renesas,scif"; 1291 reg = <0 0xe6e68000 0 0x40>; 1292 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1293 clocks = <&cpg CPG_MOD 206>, 1294 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1295 <&scif_clk>; 1296 clock-names = "fck", "brg_int", "scif_clk"; 1297 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1298 <&dmac2 0x53>, <&dmac2 0x52>; 1299 dma-names = "tx", "rx", "tx", "rx"; 1300 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1301 resets = <&cpg 206>; 1302 status = "disabled"; 1303 }; 1304 1305 scif2: serial@e6e88000 { 1306 compatible = "renesas,scif-r8a774a1", 1307 "renesas,rcar-gen3-scif", "renesas,scif"; 1308 reg = <0 0xe6e88000 0 0x40>; 1309 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1310 clocks = <&cpg CPG_MOD 310>, 1311 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1312 <&scif_clk>; 1313 clock-names = "fck", "brg_int", "scif_clk"; 1314 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1315 <&dmac2 0x13>, <&dmac2 0x12>; 1316 dma-names = "tx", "rx", "tx", "rx"; 1317 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1318 resets = <&cpg 310>; 1319 status = "disabled"; 1320 }; 1321 1322 scif3: serial@e6c50000 { 1323 compatible = "renesas,scif-r8a774a1", 1324 "renesas,rcar-gen3-scif", "renesas,scif"; 1325 reg = <0 0xe6c50000 0 0x40>; 1326 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1327 clocks = <&cpg CPG_MOD 204>, 1328 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1329 <&scif_clk>; 1330 clock-names = "fck", "brg_int", "scif_clk"; 1331 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1332 dma-names = "tx", "rx"; 1333 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1334 resets = <&cpg 204>; 1335 status = "disabled"; 1336 }; 1337 1338 scif4: serial@e6c40000 { 1339 compatible = "renesas,scif-r8a774a1", 1340 "renesas,rcar-gen3-scif", "renesas,scif"; 1341 reg = <0 0xe6c40000 0 0x40>; 1342 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1343 clocks = <&cpg CPG_MOD 203>, 1344 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1345 <&scif_clk>; 1346 clock-names = "fck", "brg_int", "scif_clk"; 1347 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1348 dma-names = "tx", "rx"; 1349 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1350 resets = <&cpg 203>; 1351 status = "disabled"; 1352 }; 1353 1354 scif5: serial@e6f30000 { 1355 compatible = "renesas,scif-r8a774a1", 1356 "renesas,rcar-gen3-scif", "renesas,scif"; 1357 reg = <0 0xe6f30000 0 0x40>; 1358 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1359 clocks = <&cpg CPG_MOD 202>, 1360 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1361 <&scif_clk>; 1362 clock-names = "fck", "brg_int", "scif_clk"; 1363 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1364 <&dmac2 0x5b>, <&dmac2 0x5a>; 1365 dma-names = "tx", "rx", "tx", "rx"; 1366 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1367 resets = <&cpg 202>; 1368 status = "disabled"; 1369 }; 1370 1371 msiof0: spi@e6e90000 { 1372 compatible = "renesas,msiof-r8a774a1", 1373 "renesas,rcar-gen3-msiof"; 1374 reg = <0 0xe6e90000 0 0x0064>; 1375 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1376 clocks = <&cpg CPG_MOD 211>; 1377 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1378 <&dmac2 0x41>, <&dmac2 0x40>; 1379 dma-names = "tx", "rx", "tx", "rx"; 1380 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1381 resets = <&cpg 211>; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 status = "disabled"; 1385 }; 1386 1387 msiof1: spi@e6ea0000 { 1388 compatible = "renesas,msiof-r8a774a1", 1389 "renesas,rcar-gen3-msiof"; 1390 reg = <0 0xe6ea0000 0 0x0064>; 1391 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1392 clocks = <&cpg CPG_MOD 210>; 1393 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1394 <&dmac2 0x43>, <&dmac2 0x42>; 1395 dma-names = "tx", "rx", "tx", "rx"; 1396 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1397 resets = <&cpg 210>; 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 status = "disabled"; 1401 }; 1402 1403 msiof2: spi@e6c00000 { 1404 compatible = "renesas,msiof-r8a774a1", 1405 "renesas,rcar-gen3-msiof"; 1406 reg = <0 0xe6c00000 0 0x0064>; 1407 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1408 clocks = <&cpg CPG_MOD 209>; 1409 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1410 dma-names = "tx", "rx"; 1411 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1412 resets = <&cpg 209>; 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 status = "disabled"; 1416 }; 1417 1418 msiof3: spi@e6c10000 { 1419 compatible = "renesas,msiof-r8a774a1", 1420 "renesas,rcar-gen3-msiof"; 1421 reg = <0 0xe6c10000 0 0x0064>; 1422 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1423 clocks = <&cpg CPG_MOD 208>; 1424 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1425 dma-names = "tx", "rx"; 1426 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1427 resets = <&cpg 208>; 1428 #address-cells = <1>; 1429 #size-cells = <0>; 1430 status = "disabled"; 1431 }; 1432 1433 vin0: video@e6ef0000 { 1434 compatible = "renesas,vin-r8a774a1"; 1435 reg = <0 0xe6ef0000 0 0x1000>; 1436 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1437 clocks = <&cpg CPG_MOD 811>; 1438 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1439 resets = <&cpg 811>; 1440 renesas,id = <0>; 1441 status = "disabled"; 1442 1443 ports { 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 1447 port@1 { 1448 #address-cells = <1>; 1449 #size-cells = <0>; 1450 1451 reg = <1>; 1452 1453 vin0csi20: endpoint@0 { 1454 reg = <0>; 1455 remote-endpoint = <&csi20vin0>; 1456 }; 1457 vin0csi40: endpoint@2 { 1458 reg = <2>; 1459 remote-endpoint = <&csi40vin0>; 1460 }; 1461 }; 1462 }; 1463 }; 1464 1465 vin1: video@e6ef1000 { 1466 compatible = "renesas,vin-r8a774a1"; 1467 reg = <0 0xe6ef1000 0 0x1000>; 1468 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1469 clocks = <&cpg CPG_MOD 810>; 1470 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1471 resets = <&cpg 810>; 1472 renesas,id = <1>; 1473 status = "disabled"; 1474 1475 ports { 1476 #address-cells = <1>; 1477 #size-cells = <0>; 1478 1479 port@1 { 1480 #address-cells = <1>; 1481 #size-cells = <0>; 1482 1483 reg = <1>; 1484 1485 vin1csi20: endpoint@0 { 1486 reg = <0>; 1487 remote-endpoint = <&csi20vin1>; 1488 }; 1489 vin1csi40: endpoint@2 { 1490 reg = <2>; 1491 remote-endpoint = <&csi40vin1>; 1492 }; 1493 }; 1494 }; 1495 }; 1496 1497 vin2: video@e6ef2000 { 1498 compatible = "renesas,vin-r8a774a1"; 1499 reg = <0 0xe6ef2000 0 0x1000>; 1500 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1501 clocks = <&cpg CPG_MOD 809>; 1502 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1503 resets = <&cpg 809>; 1504 renesas,id = <2>; 1505 status = "disabled"; 1506 1507 ports { 1508 #address-cells = <1>; 1509 #size-cells = <0>; 1510 1511 port@1 { 1512 #address-cells = <1>; 1513 #size-cells = <0>; 1514 1515 reg = <1>; 1516 1517 vin2csi20: endpoint@0 { 1518 reg = <0>; 1519 remote-endpoint = <&csi20vin2>; 1520 }; 1521 vin2csi40: endpoint@2 { 1522 reg = <2>; 1523 remote-endpoint = <&csi40vin2>; 1524 }; 1525 }; 1526 }; 1527 }; 1528 1529 vin3: video@e6ef3000 { 1530 compatible = "renesas,vin-r8a774a1"; 1531 reg = <0 0xe6ef3000 0 0x1000>; 1532 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1533 clocks = <&cpg CPG_MOD 808>; 1534 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1535 resets = <&cpg 808>; 1536 renesas,id = <3>; 1537 status = "disabled"; 1538 1539 ports { 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 1543 port@1 { 1544 #address-cells = <1>; 1545 #size-cells = <0>; 1546 1547 reg = <1>; 1548 1549 vin3csi20: endpoint@0 { 1550 reg = <0>; 1551 remote-endpoint = <&csi20vin3>; 1552 }; 1553 vin3csi40: endpoint@2 { 1554 reg = <2>; 1555 remote-endpoint = <&csi40vin3>; 1556 }; 1557 }; 1558 }; 1559 }; 1560 1561 vin4: video@e6ef4000 { 1562 compatible = "renesas,vin-r8a774a1"; 1563 reg = <0 0xe6ef4000 0 0x1000>; 1564 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1565 clocks = <&cpg CPG_MOD 807>; 1566 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1567 resets = <&cpg 807>; 1568 renesas,id = <4>; 1569 status = "disabled"; 1570 1571 ports { 1572 #address-cells = <1>; 1573 #size-cells = <0>; 1574 1575 port@1 { 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 1579 reg = <1>; 1580 1581 vin4csi20: endpoint@0 { 1582 reg = <0>; 1583 remote-endpoint = <&csi20vin4>; 1584 }; 1585 vin4csi40: endpoint@2 { 1586 reg = <2>; 1587 remote-endpoint = <&csi40vin4>; 1588 }; 1589 }; 1590 }; 1591 }; 1592 1593 vin5: video@e6ef5000 { 1594 compatible = "renesas,vin-r8a774a1"; 1595 reg = <0 0xe6ef5000 0 0x1000>; 1596 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1597 clocks = <&cpg CPG_MOD 806>; 1598 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1599 resets = <&cpg 806>; 1600 renesas,id = <5>; 1601 status = "disabled"; 1602 1603 ports { 1604 #address-cells = <1>; 1605 #size-cells = <0>; 1606 1607 port@1 { 1608 #address-cells = <1>; 1609 #size-cells = <0>; 1610 1611 reg = <1>; 1612 1613 vin5csi20: endpoint@0 { 1614 reg = <0>; 1615 remote-endpoint = <&csi20vin5>; 1616 }; 1617 vin5csi40: endpoint@2 { 1618 reg = <2>; 1619 remote-endpoint = <&csi40vin5>; 1620 }; 1621 }; 1622 }; 1623 }; 1624 1625 vin6: video@e6ef6000 { 1626 compatible = "renesas,vin-r8a774a1"; 1627 reg = <0 0xe6ef6000 0 0x1000>; 1628 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1629 clocks = <&cpg CPG_MOD 805>; 1630 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1631 resets = <&cpg 805>; 1632 renesas,id = <6>; 1633 status = "disabled"; 1634 1635 ports { 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 1639 port@1 { 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 1643 reg = <1>; 1644 1645 vin6csi20: endpoint@0 { 1646 reg = <0>; 1647 remote-endpoint = <&csi20vin6>; 1648 }; 1649 vin6csi40: endpoint@2 { 1650 reg = <2>; 1651 remote-endpoint = <&csi40vin6>; 1652 }; 1653 }; 1654 }; 1655 }; 1656 1657 vin7: video@e6ef7000 { 1658 compatible = "renesas,vin-r8a774a1"; 1659 reg = <0 0xe6ef7000 0 0x1000>; 1660 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1661 clocks = <&cpg CPG_MOD 804>; 1662 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1663 resets = <&cpg 804>; 1664 renesas,id = <7>; 1665 status = "disabled"; 1666 1667 ports { 1668 #address-cells = <1>; 1669 #size-cells = <0>; 1670 1671 port@1 { 1672 #address-cells = <1>; 1673 #size-cells = <0>; 1674 1675 reg = <1>; 1676 1677 vin7csi20: endpoint@0 { 1678 reg = <0>; 1679 remote-endpoint = <&csi20vin7>; 1680 }; 1681 vin7csi40: endpoint@2 { 1682 reg = <2>; 1683 remote-endpoint = <&csi40vin7>; 1684 }; 1685 }; 1686 }; 1687 }; 1688 1689 rcar_sound: sound@ec500000 { 1690 /* 1691 * #sound-dai-cells is required 1692 * 1693 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1694 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1695 */ 1696 /* 1697 * #clock-cells is required for audio_clkout0/1/2/3 1698 * 1699 * clkout : #clock-cells = <0>; <&rcar_sound>; 1700 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1701 */ 1702 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; 1703 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1704 <0 0xec5a0000 0 0x100>, /* ADG */ 1705 <0 0xec540000 0 0x1000>, /* SSIU */ 1706 <0 0xec541000 0 0x280>, /* SSI */ 1707 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1708 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1709 1710 clocks = <&cpg CPG_MOD 1005>, 1711 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1712 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1713 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1714 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1715 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1716 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1717 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1718 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1719 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1720 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1721 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1722 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1723 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1724 <&audio_clk_a>, <&audio_clk_b>, 1725 <&audio_clk_c>, 1726 <&cpg CPG_CORE R8A774A1_CLK_S0D4>; 1727 clock-names = "ssi-all", 1728 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1729 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1730 "ssi.1", "ssi.0", 1731 "src.9", "src.8", "src.7", "src.6", 1732 "src.5", "src.4", "src.3", "src.2", 1733 "src.1", "src.0", 1734 "mix.1", "mix.0", 1735 "ctu.1", "ctu.0", 1736 "dvc.0", "dvc.1", 1737 "clk_a", "clk_b", "clk_c", "clk_i"; 1738 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1739 resets = <&cpg 1005>, 1740 <&cpg 1006>, <&cpg 1007>, 1741 <&cpg 1008>, <&cpg 1009>, 1742 <&cpg 1010>, <&cpg 1011>, 1743 <&cpg 1012>, <&cpg 1013>, 1744 <&cpg 1014>, <&cpg 1015>; 1745 reset-names = "ssi-all", 1746 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1747 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1748 "ssi.1", "ssi.0"; 1749 status = "disabled"; 1750 1751 rcar_sound,ctu { 1752 ctu00: ctu-0 { }; 1753 ctu01: ctu-1 { }; 1754 ctu02: ctu-2 { }; 1755 ctu03: ctu-3 { }; 1756 ctu10: ctu-4 { }; 1757 ctu11: ctu-5 { }; 1758 ctu12: ctu-6 { }; 1759 ctu13: ctu-7 { }; 1760 }; 1761 1762 rcar_sound,dvc { 1763 dvc0: dvc-0 { 1764 dmas = <&audma1 0xbc>; 1765 dma-names = "tx"; 1766 }; 1767 dvc1: dvc-1 { 1768 dmas = <&audma1 0xbe>; 1769 dma-names = "tx"; 1770 }; 1771 }; 1772 1773 rcar_sound,mix { 1774 mix0: mix-0 { }; 1775 mix1: mix-1 { }; 1776 }; 1777 1778 rcar_sound,src { 1779 src0: src-0 { 1780 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1781 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1782 dma-names = "rx", "tx"; 1783 }; 1784 src1: src-1 { 1785 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1786 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1787 dma-names = "rx", "tx"; 1788 }; 1789 src2: src-2 { 1790 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1791 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1792 dma-names = "rx", "tx"; 1793 }; 1794 src3: src-3 { 1795 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1796 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1797 dma-names = "rx", "tx"; 1798 }; 1799 src4: src-4 { 1800 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1801 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1802 dma-names = "rx", "tx"; 1803 }; 1804 src5: src-5 { 1805 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1806 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1807 dma-names = "rx", "tx"; 1808 }; 1809 src6: src-6 { 1810 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1811 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1812 dma-names = "rx", "tx"; 1813 }; 1814 src7: src-7 { 1815 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1816 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1817 dma-names = "rx", "tx"; 1818 }; 1819 src8: src-8 { 1820 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1821 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1822 dma-names = "rx", "tx"; 1823 }; 1824 src9: src-9 { 1825 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1826 dmas = <&audma0 0x97>, <&audma1 0xba>; 1827 dma-names = "rx", "tx"; 1828 }; 1829 }; 1830 1831 rcar_sound,ssi { 1832 ssi0: ssi-0 { 1833 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1834 dmas = <&audma0 0x01>, <&audma1 0x02>; 1835 dma-names = "rx", "tx"; 1836 }; 1837 ssi1: ssi-1 { 1838 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1839 dmas = <&audma0 0x03>, <&audma1 0x04>; 1840 dma-names = "rx", "tx"; 1841 }; 1842 ssi2: ssi-2 { 1843 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1844 dmas = <&audma0 0x05>, <&audma1 0x06>; 1845 dma-names = "rx", "tx"; 1846 }; 1847 ssi3: ssi-3 { 1848 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1849 dmas = <&audma0 0x07>, <&audma1 0x08>; 1850 dma-names = "rx", "tx"; 1851 }; 1852 ssi4: ssi-4 { 1853 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1854 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1855 dma-names = "rx", "tx"; 1856 }; 1857 ssi5: ssi-5 { 1858 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1859 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1860 dma-names = "rx", "tx"; 1861 }; 1862 ssi6: ssi-6 { 1863 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1864 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1865 dma-names = "rx", "tx"; 1866 }; 1867 ssi7: ssi-7 { 1868 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1869 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1870 dma-names = "rx", "tx"; 1871 }; 1872 ssi8: ssi-8 { 1873 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1874 dmas = <&audma0 0x11>, <&audma1 0x12>; 1875 dma-names = "rx", "tx"; 1876 }; 1877 ssi9: ssi-9 { 1878 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1879 dmas = <&audma0 0x13>, <&audma1 0x14>; 1880 dma-names = "rx", "tx"; 1881 }; 1882 }; 1883 1884 rcar_sound,ssiu { 1885 ssiu00: ssiu-0 { 1886 dmas = <&audma0 0x15>, <&audma1 0x16>; 1887 dma-names = "rx", "tx"; 1888 }; 1889 ssiu01: ssiu-1 { 1890 dmas = <&audma0 0x35>, <&audma1 0x36>; 1891 dma-names = "rx", "tx"; 1892 }; 1893 ssiu02: ssiu-2 { 1894 dmas = <&audma0 0x37>, <&audma1 0x38>; 1895 dma-names = "rx", "tx"; 1896 }; 1897 ssiu03: ssiu-3 { 1898 dmas = <&audma0 0x47>, <&audma1 0x48>; 1899 dma-names = "rx", "tx"; 1900 }; 1901 ssiu04: ssiu-4 { 1902 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1903 dma-names = "rx", "tx"; 1904 }; 1905 ssiu05: ssiu-5 { 1906 dmas = <&audma0 0x43>, <&audma1 0x44>; 1907 dma-names = "rx", "tx"; 1908 }; 1909 ssiu06: ssiu-6 { 1910 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1911 dma-names = "rx", "tx"; 1912 }; 1913 ssiu07: ssiu-7 { 1914 dmas = <&audma0 0x53>, <&audma1 0x54>; 1915 dma-names = "rx", "tx"; 1916 }; 1917 ssiu10: ssiu-8 { 1918 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1919 dma-names = "rx", "tx"; 1920 }; 1921 ssiu11: ssiu-9 { 1922 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1923 dma-names = "rx", "tx"; 1924 }; 1925 ssiu12: ssiu-10 { 1926 dmas = <&audma0 0x57>, <&audma1 0x58>; 1927 dma-names = "rx", "tx"; 1928 }; 1929 ssiu13: ssiu-11 { 1930 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1931 dma-names = "rx", "tx"; 1932 }; 1933 ssiu14: ssiu-12 { 1934 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1935 dma-names = "rx", "tx"; 1936 }; 1937 ssiu15: ssiu-13 { 1938 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1939 dma-names = "rx", "tx"; 1940 }; 1941 ssiu16: ssiu-14 { 1942 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1943 dma-names = "rx", "tx"; 1944 }; 1945 ssiu17: ssiu-15 { 1946 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1947 dma-names = "rx", "tx"; 1948 }; 1949 ssiu20: ssiu-16 { 1950 dmas = <&audma0 0x63>, <&audma1 0x64>; 1951 dma-names = "rx", "tx"; 1952 }; 1953 ssiu21: ssiu-17 { 1954 dmas = <&audma0 0x67>, <&audma1 0x68>; 1955 dma-names = "rx", "tx"; 1956 }; 1957 ssiu22: ssiu-18 { 1958 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1959 dma-names = "rx", "tx"; 1960 }; 1961 ssiu23: ssiu-19 { 1962 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1963 dma-names = "rx", "tx"; 1964 }; 1965 ssiu24: ssiu-20 { 1966 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1967 dma-names = "rx", "tx"; 1968 }; 1969 ssiu25: ssiu-21 { 1970 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1971 dma-names = "rx", "tx"; 1972 }; 1973 ssiu26: ssiu-22 { 1974 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1975 dma-names = "rx", "tx"; 1976 }; 1977 ssiu27: ssiu-23 { 1978 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1979 dma-names = "rx", "tx"; 1980 }; 1981 ssiu30: ssiu-24 { 1982 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1983 dma-names = "rx", "tx"; 1984 }; 1985 ssiu31: ssiu-25 { 1986 dmas = <&audma0 0x21>, <&audma1 0x22>; 1987 dma-names = "rx", "tx"; 1988 }; 1989 ssiu32: ssiu-26 { 1990 dmas = <&audma0 0x23>, <&audma1 0x24>; 1991 dma-names = "rx", "tx"; 1992 }; 1993 ssiu33: ssiu-27 { 1994 dmas = <&audma0 0x25>, <&audma1 0x26>; 1995 dma-names = "rx", "tx"; 1996 }; 1997 ssiu34: ssiu-28 { 1998 dmas = <&audma0 0x27>, <&audma1 0x28>; 1999 dma-names = "rx", "tx"; 2000 }; 2001 ssiu35: ssiu-29 { 2002 dmas = <&audma0 0x29>, <&audma1 0x2A>; 2003 dma-names = "rx", "tx"; 2004 }; 2005 ssiu36: ssiu-30 { 2006 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 2007 dma-names = "rx", "tx"; 2008 }; 2009 ssiu37: ssiu-31 { 2010 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 2011 dma-names = "rx", "tx"; 2012 }; 2013 ssiu40: ssiu-32 { 2014 dmas = <&audma0 0x71>, <&audma1 0x72>; 2015 dma-names = "rx", "tx"; 2016 }; 2017 ssiu41: ssiu-33 { 2018 dmas = <&audma0 0x17>, <&audma1 0x18>; 2019 dma-names = "rx", "tx"; 2020 }; 2021 ssiu42: ssiu-34 { 2022 dmas = <&audma0 0x19>, <&audma1 0x1A>; 2023 dma-names = "rx", "tx"; 2024 }; 2025 ssiu43: ssiu-35 { 2026 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 2027 dma-names = "rx", "tx"; 2028 }; 2029 ssiu44: ssiu-36 { 2030 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 2031 dma-names = "rx", "tx"; 2032 }; 2033 ssiu45: ssiu-37 { 2034 dmas = <&audma0 0x1F>, <&audma1 0x20>; 2035 dma-names = "rx", "tx"; 2036 }; 2037 ssiu46: ssiu-38 { 2038 dmas = <&audma0 0x31>, <&audma1 0x32>; 2039 dma-names = "rx", "tx"; 2040 }; 2041 ssiu47: ssiu-39 { 2042 dmas = <&audma0 0x33>, <&audma1 0x34>; 2043 dma-names = "rx", "tx"; 2044 }; 2045 ssiu50: ssiu-40 { 2046 dmas = <&audma0 0x73>, <&audma1 0x74>; 2047 dma-names = "rx", "tx"; 2048 }; 2049 ssiu60: ssiu-41 { 2050 dmas = <&audma0 0x75>, <&audma1 0x76>; 2051 dma-names = "rx", "tx"; 2052 }; 2053 ssiu70: ssiu-42 { 2054 dmas = <&audma0 0x79>, <&audma1 0x7a>; 2055 dma-names = "rx", "tx"; 2056 }; 2057 ssiu80: ssiu-43 { 2058 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 2059 dma-names = "rx", "tx"; 2060 }; 2061 ssiu90: ssiu-44 { 2062 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 2063 dma-names = "rx", "tx"; 2064 }; 2065 ssiu91: ssiu-45 { 2066 dmas = <&audma0 0x7F>, <&audma1 0x80>; 2067 dma-names = "rx", "tx"; 2068 }; 2069 ssiu92: ssiu-46 { 2070 dmas = <&audma0 0x81>, <&audma1 0x82>; 2071 dma-names = "rx", "tx"; 2072 }; 2073 ssiu93: ssiu-47 { 2074 dmas = <&audma0 0x83>, <&audma1 0x84>; 2075 dma-names = "rx", "tx"; 2076 }; 2077 ssiu94: ssiu-48 { 2078 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 2079 dma-names = "rx", "tx"; 2080 }; 2081 ssiu95: ssiu-49 { 2082 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 2083 dma-names = "rx", "tx"; 2084 }; 2085 ssiu96: ssiu-50 { 2086 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2087 dma-names = "rx", "tx"; 2088 }; 2089 ssiu97: ssiu-51 { 2090 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2091 dma-names = "rx", "tx"; 2092 }; 2093 }; 2094 }; 2095 2096 audma0: dma-controller@ec700000 { 2097 compatible = "renesas,dmac-r8a774a1", 2098 "renesas,rcar-dmac"; 2099 reg = <0 0xec700000 0 0x10000>; 2100 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2117 interrupt-names = "error", 2118 "ch0", "ch1", "ch2", "ch3", 2119 "ch4", "ch5", "ch6", "ch7", 2120 "ch8", "ch9", "ch10", "ch11", 2121 "ch12", "ch13", "ch14", "ch15"; 2122 clocks = <&cpg CPG_MOD 502>; 2123 clock-names = "fck"; 2124 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2125 resets = <&cpg 502>; 2126 #dma-cells = <1>; 2127 dma-channels = <16>; 2128 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 2129 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 2130 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 2131 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 2132 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 2133 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 2134 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 2135 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 2136 }; 2137 2138 audma1: dma-controller@ec720000 { 2139 compatible = "renesas,dmac-r8a774a1", 2140 "renesas,rcar-dmac"; 2141 reg = <0 0xec720000 0 0x10000>; 2142 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2158 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2159 interrupt-names = "error", 2160 "ch0", "ch1", "ch2", "ch3", 2161 "ch4", "ch5", "ch6", "ch7", 2162 "ch8", "ch9", "ch10", "ch11", 2163 "ch12", "ch13", "ch14", "ch15"; 2164 clocks = <&cpg CPG_MOD 501>; 2165 clock-names = "fck"; 2166 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2167 resets = <&cpg 501>; 2168 #dma-cells = <1>; 2169 dma-channels = <16>; 2170 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 2171 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 2172 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 2173 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 2174 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 2175 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 2176 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 2177 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 2178 }; 2179 2180 xhci0: usb@ee000000 { 2181 compatible = "renesas,xhci-r8a774a1", 2182 "renesas,rcar-gen3-xhci"; 2183 reg = <0 0xee000000 0 0xc00>; 2184 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2185 clocks = <&cpg CPG_MOD 328>; 2186 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2187 resets = <&cpg 328>; 2188 status = "disabled"; 2189 }; 2190 2191 usb3_peri0: usb@ee020000 { 2192 compatible = "renesas,r8a774a1-usb3-peri", 2193 "renesas,rcar-gen3-usb3-peri"; 2194 reg = <0 0xee020000 0 0x400>; 2195 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2196 clocks = <&cpg CPG_MOD 328>; 2197 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2198 resets = <&cpg 328>; 2199 status = "disabled"; 2200 }; 2201 2202 ohci0: usb@ee080000 { 2203 compatible = "generic-ohci"; 2204 reg = <0 0xee080000 0 0x100>; 2205 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2206 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2207 phys = <&usb2_phy0 1>; 2208 phy-names = "usb"; 2209 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2210 resets = <&cpg 703>, <&cpg 704>; 2211 status = "disabled"; 2212 }; 2213 2214 ohci1: usb@ee0a0000 { 2215 compatible = "generic-ohci"; 2216 reg = <0 0xee0a0000 0 0x100>; 2217 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2218 clocks = <&cpg CPG_MOD 702>; 2219 phys = <&usb2_phy1 1>; 2220 phy-names = "usb"; 2221 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2222 resets = <&cpg 702>; 2223 status = "disabled"; 2224 }; 2225 2226 ehci0: usb@ee080100 { 2227 compatible = "generic-ehci"; 2228 reg = <0 0xee080100 0 0x100>; 2229 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2230 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2231 phys = <&usb2_phy0 2>; 2232 phy-names = "usb"; 2233 companion = <&ohci0>; 2234 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2235 resets = <&cpg 703>, <&cpg 704>; 2236 status = "disabled"; 2237 }; 2238 2239 ehci1: usb@ee0a0100 { 2240 compatible = "generic-ehci"; 2241 reg = <0 0xee0a0100 0 0x100>; 2242 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2243 clocks = <&cpg CPG_MOD 702>; 2244 phys = <&usb2_phy1 2>; 2245 phy-names = "usb"; 2246 companion = <&ohci1>; 2247 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2248 resets = <&cpg 702>; 2249 status = "disabled"; 2250 }; 2251 2252 usb2_phy0: usb-phy@ee080200 { 2253 compatible = "renesas,usb2-phy-r8a774a1", 2254 "renesas,rcar-gen3-usb2-phy"; 2255 reg = <0 0xee080200 0 0x700>; 2256 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2257 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2258 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2259 resets = <&cpg 703>, <&cpg 704>; 2260 #phy-cells = <1>; 2261 status = "disabled"; 2262 }; 2263 2264 usb2_phy1: usb-phy@ee0a0200 { 2265 compatible = "renesas,usb2-phy-r8a774a1", 2266 "renesas,rcar-gen3-usb2-phy"; 2267 reg = <0 0xee0a0200 0 0x700>; 2268 clocks = <&cpg CPG_MOD 702>; 2269 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2270 resets = <&cpg 702>; 2271 #phy-cells = <1>; 2272 status = "disabled"; 2273 }; 2274 2275 sdhi0: mmc@ee100000 { 2276 compatible = "renesas,sdhi-r8a774a1", 2277 "renesas,rcar-gen3-sdhi"; 2278 reg = <0 0xee100000 0 0x2000>; 2279 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2280 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>; 2281 clock-names = "core", "clkh"; 2282 max-frequency = <200000000>; 2283 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2284 resets = <&cpg 314>; 2285 status = "disabled"; 2286 }; 2287 2288 sdhi1: mmc@ee120000 { 2289 compatible = "renesas,sdhi-r8a774a1", 2290 "renesas,rcar-gen3-sdhi"; 2291 reg = <0 0xee120000 0 0x2000>; 2292 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2293 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>; 2294 clock-names = "core", "clkh"; 2295 max-frequency = <200000000>; 2296 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2297 resets = <&cpg 313>; 2298 status = "disabled"; 2299 }; 2300 2301 sdhi2: mmc@ee140000 { 2302 compatible = "renesas,sdhi-r8a774a1", 2303 "renesas,rcar-gen3-sdhi"; 2304 reg = <0 0xee140000 0 0x2000>; 2305 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2306 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>; 2307 clock-names = "core", "clkh"; 2308 max-frequency = <200000000>; 2309 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2310 resets = <&cpg 312>; 2311 status = "disabled"; 2312 }; 2313 2314 sdhi3: mmc@ee160000 { 2315 compatible = "renesas,sdhi-r8a774a1", 2316 "renesas,rcar-gen3-sdhi"; 2317 reg = <0 0xee160000 0 0x2000>; 2318 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2319 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>; 2320 clock-names = "core", "clkh"; 2321 max-frequency = <200000000>; 2322 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2323 resets = <&cpg 311>; 2324 status = "disabled"; 2325 }; 2326 2327 rpc: spi@ee200000 { 2328 compatible = "renesas,r8a774a1-rpc-if", 2329 "renesas,rcar-gen3-rpc-if"; 2330 reg = <0 0xee200000 0 0x200>, 2331 <0 0x08000000 0 0x4000000>, 2332 <0 0xee208000 0 0x100>; 2333 reg-names = "regs", "dirmap", "wbuf"; 2334 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 2335 clocks = <&cpg CPG_MOD 917>; 2336 clock-names = "rpc"; 2337 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2338 resets = <&cpg 917>; 2339 #address-cells = <1>; 2340 #size-cells = <0>; 2341 status = "disabled"; 2342 }; 2343 2344 gic: interrupt-controller@f1010000 { 2345 compatible = "arm,gic-400"; 2346 #interrupt-cells = <3>; 2347 #address-cells = <0>; 2348 interrupt-controller; 2349 reg = <0x0 0xf1010000 0 0x1000>, 2350 <0x0 0xf1020000 0 0x20000>, 2351 <0x0 0xf1040000 0 0x20000>, 2352 <0x0 0xf1060000 0 0x20000>; 2353 interrupts = <GIC_PPI 9 2354 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 2355 clocks = <&cpg CPG_MOD 408>; 2356 clock-names = "clk"; 2357 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2358 resets = <&cpg 408>; 2359 }; 2360 2361 pciec0: pcie@fe000000 { 2362 compatible = "renesas,pcie-r8a774a1", 2363 "renesas,pcie-rcar-gen3"; 2364 reg = <0 0xfe000000 0 0x80000>; 2365 #address-cells = <3>; 2366 #size-cells = <2>; 2367 bus-range = <0x00 0xff>; 2368 device_type = "pci"; 2369 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2370 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2371 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2372 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2373 /* Map all possible DDR as inbound ranges */ 2374 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2375 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2376 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2377 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2378 #interrupt-cells = <1>; 2379 interrupt-map-mask = <0 0 0 0>; 2380 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2381 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2382 clock-names = "pcie", "pcie_bus"; 2383 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2384 resets = <&cpg 319>; 2385 status = "disabled"; 2386 }; 2387 2388 pciec1: pcie@ee800000 { 2389 compatible = "renesas,pcie-r8a774a1", 2390 "renesas,pcie-rcar-gen3"; 2391 reg = <0 0xee800000 0 0x80000>; 2392 #address-cells = <3>; 2393 #size-cells = <2>; 2394 bus-range = <0x00 0xff>; 2395 device_type = "pci"; 2396 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2397 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2398 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2399 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2400 /* Map all possible DDR as inbound ranges */ 2401 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2402 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2404 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2405 #interrupt-cells = <1>; 2406 interrupt-map-mask = <0 0 0 0>; 2407 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2408 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2409 clock-names = "pcie", "pcie_bus"; 2410 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2411 resets = <&cpg 318>; 2412 status = "disabled"; 2413 }; 2414 2415 pciec0_ep: pcie-ep@fe000000 { 2416 compatible = "renesas,r8a774a1-pcie-ep", 2417 "renesas,rcar-gen3-pcie-ep"; 2418 reg = <0x0 0xfe000000 0 0x80000>, 2419 <0x0 0xfe100000 0 0x100000>, 2420 <0x0 0xfe200000 0 0x200000>, 2421 <0x0 0x30000000 0 0x8000000>, 2422 <0x0 0x38000000 0 0x8000000>; 2423 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2424 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2425 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2426 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2427 clocks = <&cpg CPG_MOD 319>; 2428 clock-names = "pcie"; 2429 resets = <&cpg 319>; 2430 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2431 status = "disabled"; 2432 }; 2433 2434 pciec1_ep: pcie-ep@ee800000 { 2435 compatible = "renesas,r8a774a1-pcie-ep", 2436 "renesas,rcar-gen3-pcie-ep"; 2437 reg = <0x0 0xee800000 0 0x80000>, 2438 <0x0 0xee900000 0 0x100000>, 2439 <0x0 0xeea00000 0 0x200000>, 2440 <0x0 0xc0000000 0 0x8000000>, 2441 <0x0 0xc8000000 0 0x8000000>; 2442 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2443 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2446 clocks = <&cpg CPG_MOD 318>; 2447 clock-names = "pcie"; 2448 resets = <&cpg 318>; 2449 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2450 status = "disabled"; 2451 }; 2452 2453 fdp1@fe940000 { 2454 compatible = "renesas,fdp1"; 2455 reg = <0 0xfe940000 0 0x2400>; 2456 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2457 clocks = <&cpg CPG_MOD 119>; 2458 power-domains = <&sysc R8A774A1_PD_A3VC>; 2459 resets = <&cpg 119>; 2460 renesas,fcp = <&fcpf0>; 2461 }; 2462 2463 fcpf0: fcp@fe950000 { 2464 compatible = "renesas,fcpf"; 2465 reg = <0 0xfe950000 0 0x200>; 2466 clocks = <&cpg CPG_MOD 615>; 2467 power-domains = <&sysc R8A774A1_PD_A3VC>; 2468 resets = <&cpg 615>; 2469 }; 2470 2471 fcpvb0: fcp@fe96f000 { 2472 compatible = "renesas,fcpv"; 2473 reg = <0 0xfe96f000 0 0x200>; 2474 clocks = <&cpg CPG_MOD 607>; 2475 power-domains = <&sysc R8A774A1_PD_A3VC>; 2476 resets = <&cpg 607>; 2477 }; 2478 2479 fcpvd0: fcp@fea27000 { 2480 compatible = "renesas,fcpv"; 2481 reg = <0 0xfea27000 0 0x200>; 2482 clocks = <&cpg CPG_MOD 603>; 2483 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2484 resets = <&cpg 603>; 2485 iommus = <&ipmmu_vi0 8>; 2486 }; 2487 2488 fcpvd1: fcp@fea2f000 { 2489 compatible = "renesas,fcpv"; 2490 reg = <0 0xfea2f000 0 0x200>; 2491 clocks = <&cpg CPG_MOD 602>; 2492 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2493 resets = <&cpg 602>; 2494 iommus = <&ipmmu_vi0 9>; 2495 }; 2496 2497 fcpvd2: fcp@fea37000 { 2498 compatible = "renesas,fcpv"; 2499 reg = <0 0xfea37000 0 0x200>; 2500 clocks = <&cpg CPG_MOD 601>; 2501 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2502 resets = <&cpg 601>; 2503 iommus = <&ipmmu_vi0 10>; 2504 }; 2505 2506 fcpvi0: fcp@fe9af000 { 2507 compatible = "renesas,fcpv"; 2508 reg = <0 0xfe9af000 0 0x200>; 2509 clocks = <&cpg CPG_MOD 611>; 2510 power-domains = <&sysc R8A774A1_PD_A3VC>; 2511 resets = <&cpg 611>; 2512 iommus = <&ipmmu_vc0 19>; 2513 }; 2514 2515 vspb: vsp@fe960000 { 2516 compatible = "renesas,vsp2"; 2517 reg = <0 0xfe960000 0 0x8000>; 2518 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2519 clocks = <&cpg CPG_MOD 626>; 2520 power-domains = <&sysc R8A774A1_PD_A3VC>; 2521 resets = <&cpg 626>; 2522 2523 renesas,fcp = <&fcpvb0>; 2524 }; 2525 2526 vspd0: vsp@fea20000 { 2527 compatible = "renesas,vsp2"; 2528 reg = <0 0xfea20000 0 0x5000>; 2529 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2530 clocks = <&cpg CPG_MOD 623>; 2531 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2532 resets = <&cpg 623>; 2533 2534 renesas,fcp = <&fcpvd0>; 2535 }; 2536 2537 vspd1: vsp@fea28000 { 2538 compatible = "renesas,vsp2"; 2539 reg = <0 0xfea28000 0 0x5000>; 2540 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2541 clocks = <&cpg CPG_MOD 622>; 2542 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2543 resets = <&cpg 622>; 2544 2545 renesas,fcp = <&fcpvd1>; 2546 }; 2547 2548 vspd2: vsp@fea30000 { 2549 compatible = "renesas,vsp2"; 2550 reg = <0 0xfea30000 0 0x5000>; 2551 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2552 clocks = <&cpg CPG_MOD 621>; 2553 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2554 resets = <&cpg 621>; 2555 2556 renesas,fcp = <&fcpvd2>; 2557 }; 2558 2559 vspi0: vsp@fe9a0000 { 2560 compatible = "renesas,vsp2"; 2561 reg = <0 0xfe9a0000 0 0x8000>; 2562 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2563 clocks = <&cpg CPG_MOD 631>; 2564 power-domains = <&sysc R8A774A1_PD_A3VC>; 2565 resets = <&cpg 631>; 2566 2567 renesas,fcp = <&fcpvi0>; 2568 }; 2569 2570 csi20: csi2@fea80000 { 2571 compatible = "renesas,r8a774a1-csi2"; 2572 reg = <0 0xfea80000 0 0x10000>; 2573 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2574 clocks = <&cpg CPG_MOD 714>; 2575 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2576 resets = <&cpg 714>; 2577 status = "disabled"; 2578 2579 ports { 2580 #address-cells = <1>; 2581 #size-cells = <0>; 2582 2583 port@0 { 2584 reg = <0>; 2585 }; 2586 2587 port@1 { 2588 #address-cells = <1>; 2589 #size-cells = <0>; 2590 2591 reg = <1>; 2592 2593 csi20vin0: endpoint@0 { 2594 reg = <0>; 2595 remote-endpoint = <&vin0csi20>; 2596 }; 2597 csi20vin1: endpoint@1 { 2598 reg = <1>; 2599 remote-endpoint = <&vin1csi20>; 2600 }; 2601 csi20vin2: endpoint@2 { 2602 reg = <2>; 2603 remote-endpoint = <&vin2csi20>; 2604 }; 2605 csi20vin3: endpoint@3 { 2606 reg = <3>; 2607 remote-endpoint = <&vin3csi20>; 2608 }; 2609 csi20vin4: endpoint@4 { 2610 reg = <4>; 2611 remote-endpoint = <&vin4csi20>; 2612 }; 2613 csi20vin5: endpoint@5 { 2614 reg = <5>; 2615 remote-endpoint = <&vin5csi20>; 2616 }; 2617 csi20vin6: endpoint@6 { 2618 reg = <6>; 2619 remote-endpoint = <&vin6csi20>; 2620 }; 2621 csi20vin7: endpoint@7 { 2622 reg = <7>; 2623 remote-endpoint = <&vin7csi20>; 2624 }; 2625 }; 2626 }; 2627 }; 2628 2629 csi40: csi2@feaa0000 { 2630 compatible = "renesas,r8a774a1-csi2"; 2631 reg = <0 0xfeaa0000 0 0x10000>; 2632 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2633 clocks = <&cpg CPG_MOD 716>; 2634 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2635 resets = <&cpg 716>; 2636 status = "disabled"; 2637 2638 ports { 2639 #address-cells = <1>; 2640 #size-cells = <0>; 2641 2642 port@0 { 2643 reg = <0>; 2644 }; 2645 2646 port@1 { 2647 #address-cells = <1>; 2648 #size-cells = <0>; 2649 2650 reg = <1>; 2651 2652 csi40vin0: endpoint@0 { 2653 reg = <0>; 2654 remote-endpoint = <&vin0csi40>; 2655 }; 2656 csi40vin1: endpoint@1 { 2657 reg = <1>; 2658 remote-endpoint = <&vin1csi40>; 2659 }; 2660 csi40vin2: endpoint@2 { 2661 reg = <2>; 2662 remote-endpoint = <&vin2csi40>; 2663 }; 2664 csi40vin3: endpoint@3 { 2665 reg = <3>; 2666 remote-endpoint = <&vin3csi40>; 2667 }; 2668 csi40vin4: endpoint@4 { 2669 reg = <4>; 2670 remote-endpoint = <&vin4csi40>; 2671 }; 2672 csi40vin5: endpoint@5 { 2673 reg = <5>; 2674 remote-endpoint = <&vin5csi40>; 2675 }; 2676 csi40vin6: endpoint@6 { 2677 reg = <6>; 2678 remote-endpoint = <&vin6csi40>; 2679 }; 2680 csi40vin7: endpoint@7 { 2681 reg = <7>; 2682 remote-endpoint = <&vin7csi40>; 2683 }; 2684 }; 2685 2686 }; 2687 }; 2688 2689 hdmi0: hdmi@fead0000 { 2690 compatible = "renesas,r8a774a1-hdmi", 2691 "renesas,rcar-gen3-hdmi"; 2692 reg = <0 0xfead0000 0 0x10000>; 2693 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2694 clocks = <&cpg CPG_MOD 729>, 2695 <&cpg CPG_CORE R8A774A1_CLK_HDMI>; 2696 clock-names = "iahb", "isfr"; 2697 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2698 resets = <&cpg 729>; 2699 status = "disabled"; 2700 2701 ports { 2702 #address-cells = <1>; 2703 #size-cells = <0>; 2704 port@0 { 2705 reg = <0>; 2706 dw_hdmi0_in: endpoint { 2707 remote-endpoint = <&du_out_hdmi0>; 2708 }; 2709 }; 2710 port@1 { 2711 reg = <1>; 2712 }; 2713 port@2 { 2714 /* HDMI sound */ 2715 reg = <2>; 2716 }; 2717 }; 2718 }; 2719 2720 du: display@feb00000 { 2721 compatible = "renesas,du-r8a774a1"; 2722 reg = <0 0xfeb00000 0 0x70000>; 2723 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2724 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2725 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2726 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 2727 <&cpg CPG_MOD 722>; 2728 clock-names = "du.0", "du.1", "du.2"; 2729 resets = <&cpg 724>, <&cpg 722>; 2730 reset-names = "du.0", "du.2"; 2731 status = "disabled"; 2732 2733 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; 2734 2735 ports { 2736 #address-cells = <1>; 2737 #size-cells = <0>; 2738 2739 port@0 { 2740 reg = <0>; 2741 du_out_rgb: endpoint { 2742 }; 2743 }; 2744 port@1 { 2745 reg = <1>; 2746 du_out_hdmi0: endpoint { 2747 remote-endpoint = <&dw_hdmi0_in>; 2748 }; 2749 }; 2750 port@2 { 2751 reg = <2>; 2752 du_out_lvds0: endpoint { 2753 remote-endpoint = <&lvds0_in>; 2754 }; 2755 }; 2756 }; 2757 }; 2758 2759 lvds0: lvds@feb90000 { 2760 compatible = "renesas,r8a774a1-lvds"; 2761 reg = <0 0xfeb90000 0 0x14>; 2762 clocks = <&cpg CPG_MOD 727>; 2763 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2764 resets = <&cpg 727>; 2765 status = "disabled"; 2766 2767 ports { 2768 #address-cells = <1>; 2769 #size-cells = <0>; 2770 2771 port@0 { 2772 reg = <0>; 2773 lvds0_in: endpoint { 2774 remote-endpoint = <&du_out_lvds0>; 2775 }; 2776 }; 2777 port@1 { 2778 reg = <1>; 2779 }; 2780 }; 2781 }; 2782 2783 prr: chipid@fff00044 { 2784 compatible = "renesas,prr"; 2785 reg = <0 0xfff00044 0 4>; 2786 }; 2787 }; 2788 2789 thermal-zones { 2790 sensor1_thermal: sensor1-thermal { 2791 polling-delay-passive = <250>; 2792 polling-delay = <1000>; 2793 thermal-sensors = <&tsc 0>; 2794 sustainable-power = <3874>; 2795 2796 trips { 2797 sensor1_crit: sensor1-crit { 2798 temperature = <120000>; 2799 hysteresis = <1000>; 2800 type = "critical"; 2801 }; 2802 }; 2803 }; 2804 2805 sensor2_thermal: sensor2-thermal { 2806 polling-delay-passive = <250>; 2807 polling-delay = <1000>; 2808 thermal-sensors = <&tsc 1>; 2809 sustainable-power = <3874>; 2810 2811 trips { 2812 sensor2_crit: sensor2-crit { 2813 temperature = <120000>; 2814 hysteresis = <1000>; 2815 type = "critical"; 2816 }; 2817 }; 2818 }; 2819 2820 sensor3_thermal: sensor3-thermal { 2821 polling-delay-passive = <250>; 2822 polling-delay = <1000>; 2823 thermal-sensors = <&tsc 2>; 2824 sustainable-power = <3874>; 2825 2826 cooling-maps { 2827 map0 { 2828 trip = <&target>; 2829 cooling-device = <&a57_0 0 2>; 2830 contribution = <1024>; 2831 }; 2832 map1 { 2833 trip = <&target>; 2834 cooling-device = <&a53_0 0 2>; 2835 contribution = <1024>; 2836 }; 2837 }; 2838 trips { 2839 target: trip-point1 { 2840 temperature = <100000>; 2841 hysteresis = <1000>; 2842 type = "passive"; 2843 }; 2844 2845 sensor3_crit: sensor3-crit { 2846 temperature = <120000>; 2847 hysteresis = <1000>; 2848 type = "critical"; 2849 }; 2850 }; 2851 }; 2852 }; 2853 2854 timer { 2855 compatible = "arm,armv8-timer"; 2856 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2857 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2858 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2859 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2860 }; 2861 2862 /* External USB clocks - can be overridden by the board */ 2863 usb3s0_clk: usb3s0 { 2864 compatible = "fixed-clock"; 2865 #clock-cells = <0>; 2866 clock-frequency = <0>; 2867 }; 2868 2869 usb_extal_clk: usb_extal { 2870 compatible = "fixed-clock"; 2871 #clock-cells = <0>; 2872 clock-frequency = <0>; 2873 }; 2874}; 2875