1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12/ { 13 compatible = "renesas,r8a774a1"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 /* 18 * The external audio clocks are configured as 0 Hz fixed frequency 19 * clocks by default. 20 * Boards that provide audio clocks should override them. 21 */ 22 audio_clk_a: audio_clk_a { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <0>; 26 }; 27 28 audio_clk_b: audio_clk_b { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 audio_clk_c: audio_clk_c { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 /* External CAN clock - to be overridden by boards that provide it */ 41 can_clk: can { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 a57_0: cpu@0 { 52 compatible = "arm,cortex-a57", "arm,armv8"; 53 reg = <0x0>; 54 device_type = "cpu"; 55 power-domains = <&sysc 0>; 56 next-level-cache = <&L2_CA57>; 57 enable-method = "psci"; 58 clocks =<&cpg CPG_CORE 0>; 59 }; 60 61 a57_1: cpu@1 { 62 compatible = "arm,cortex-a57", "arm,armv8"; 63 reg = <0x1>; 64 device_type = "cpu"; 65 power-domains = <&sysc 1>; 66 next-level-cache = <&L2_CA57>; 67 enable-method = "psci"; 68 clocks =<&cpg CPG_CORE 0>; 69 }; 70 71 L2_CA57: cache-controller-0 { 72 compatible = "cache"; 73 power-domains = <&sysc 12>; 74 cache-unified; 75 cache-level = <2>; 76 }; 77 }; 78 79 extal_clk: extal { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 /* This value must be overridden by the board */ 83 clock-frequency = <0>; 84 }; 85 86 extalr_clk: extalr { 87 compatible = "fixed-clock"; 88 #clock-cells = <0>; 89 /* This value must be overridden by the board */ 90 clock-frequency = <0>; 91 }; 92 93 /* External PCIe clock - can be overridden by the board */ 94 pcie_bus_clk: pcie_bus { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <0>; 98 }; 99 100 pmu_a57 { 101 compatible = "arm,cortex-a57-pmu"; 102 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 103 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 104 interrupt-affinity = <&a57_0>, <&a57_1>; 105 }; 106 107 psci { 108 compatible = "arm,psci-1.0", "arm,psci-0.2"; 109 method = "smc"; 110 }; 111 112 /* External SCIF clock - to be overridden by boards that provide it */ 113 scif_clk: scif { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 clock-frequency = <0>; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 interrupt-parent = <&gic>; 122 #address-cells = <2>; 123 #size-cells = <2>; 124 ranges; 125 126 cpg: clock-controller@e6150000 { 127 compatible = "renesas,r8a774a1-cpg-mssr"; 128 reg = <0 0xe6150000 0 0x0bb0>; 129 clocks = <&extal_clk>, <&extalr_clk>; 130 clock-names = "extal", "extalr"; 131 #clock-cells = <2>; 132 #power-domain-cells = <0>; 133 #reset-cells = <1>; 134 }; 135 136 rst: reset-controller@e6160000 { 137 compatible = "renesas,r8a774a1-rst"; 138 reg = <0 0xe6160000 0 0x018c>; 139 }; 140 141 sysc: system-controller@e6180000 { 142 compatible = "renesas,r8a774a1-sysc"; 143 reg = <0 0xe6180000 0 0x0400>; 144 #power-domain-cells = <1>; 145 }; 146 147 intc_ex: interrupt-controller@e61c0000 { 148 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; 149 #interrupt-cells = <2>; 150 interrupt-controller; 151 reg = <0 0xe61c0000 0 0x200>; 152 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 153 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 154 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 155 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 156 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 157 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&cpg CPG_MOD 407>; 159 power-domains = <&sysc 32>; 160 resets = <&cpg 407>; 161 }; 162 163 hscif0: serial@e6540000 { 164 compatible = "renesas,hscif-r8a774a1", 165 "renesas,rcar-gen3-hscif", 166 "renesas,hscif"; 167 reg = <0 0xe6540000 0 0x60>; 168 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&cpg CPG_MOD 520>, 170 <&cpg CPG_CORE 19>, 171 <&scif_clk>; 172 clock-names = "fck", "brg_int", "scif_clk"; 173 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 174 <&dmac2 0x31>, <&dmac2 0x30>; 175 dma-names = "tx", "rx", "tx", "rx"; 176 power-domains = <&sysc 32>; 177 resets = <&cpg 520>; 178 status = "disabled"; 179 }; 180 181 hscif1: serial@e6550000 { 182 compatible = "renesas,hscif-r8a774a1", 183 "renesas,rcar-gen3-hscif", 184 "renesas,hscif"; 185 reg = <0 0xe6550000 0 0x60>; 186 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&cpg CPG_MOD 519>, 188 <&cpg CPG_CORE 19>, 189 <&scif_clk>; 190 clock-names = "fck", "brg_int", "scif_clk"; 191 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 192 <&dmac2 0x33>, <&dmac2 0x32>; 193 dma-names = "tx", "rx", "tx", "rx"; 194 power-domains = <&sysc 32>; 195 resets = <&cpg 519>; 196 status = "disabled"; 197 }; 198 199 hscif2: serial@e6560000 { 200 compatible = "renesas,hscif-r8a774a1", 201 "renesas,rcar-gen3-hscif", 202 "renesas,hscif"; 203 reg = <0 0xe6560000 0 0x60>; 204 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&cpg CPG_MOD 518>, 206 <&cpg CPG_CORE 19>, 207 <&scif_clk>; 208 clock-names = "fck", "brg_int", "scif_clk"; 209 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 210 <&dmac2 0x35>, <&dmac2 0x34>; 211 dma-names = "tx", "rx", "tx", "rx"; 212 power-domains = <&sysc 32>; 213 resets = <&cpg 518>; 214 status = "disabled"; 215 }; 216 217 hscif3: serial@e66a0000 { 218 compatible = "renesas,hscif-r8a774a1", 219 "renesas,rcar-gen3-hscif", 220 "renesas,hscif"; 221 reg = <0 0xe66a0000 0 0x60>; 222 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&cpg CPG_MOD 517>, 224 <&cpg CPG_CORE 19>, 225 <&scif_clk>; 226 clock-names = "fck", "brg_int", "scif_clk"; 227 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 228 dma-names = "tx", "rx"; 229 power-domains = <&sysc 32>; 230 resets = <&cpg 517>; 231 status = "disabled"; 232 }; 233 234 hscif4: serial@e66b0000 { 235 compatible = "renesas,hscif-r8a774a1", 236 "renesas,rcar-gen3-hscif", 237 "renesas,hscif"; 238 reg = <0 0xe66b0000 0 0x60>; 239 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&cpg CPG_MOD 516>, 241 <&cpg CPG_CORE 19>, 242 <&scif_clk>; 243 clock-names = "fck", "brg_int", "scif_clk"; 244 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 245 dma-names = "tx", "rx"; 246 power-domains = <&sysc 32>; 247 resets = <&cpg 516>; 248 status = "disabled"; 249 }; 250 251 dmac0: dma-controller@e6700000 { 252 compatible = "renesas,dmac-r8a774a1", 253 "renesas,rcar-dmac"; 254 reg = <0 0xe6700000 0 0x10000>; 255 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 256 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 257 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 258 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 259 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 260 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 261 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 262 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 263 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 264 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 265 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 266 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 267 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 268 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 269 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 270 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 271 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 272 interrupt-names = "error", 273 "ch0", "ch1", "ch2", "ch3", 274 "ch4", "ch5", "ch6", "ch7", 275 "ch8", "ch9", "ch10", "ch11", 276 "ch12", "ch13", "ch14", "ch15"; 277 clocks = <&cpg CPG_MOD 219>; 278 clock-names = "fck"; 279 power-domains = <&sysc 32>; 280 resets = <&cpg 219>; 281 #dma-cells = <1>; 282 dma-channels = <16>; 283 }; 284 285 dmac1: dma-controller@e7300000 { 286 compatible = "renesas,dmac-r8a774a1", 287 "renesas,rcar-dmac"; 288 reg = <0 0xe7300000 0 0x10000>; 289 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 290 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 291 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 292 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 293 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 294 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 295 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 296 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 297 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 298 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 299 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 300 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 301 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 302 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 303 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 304 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 305 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 306 interrupt-names = "error", 307 "ch0", "ch1", "ch2", "ch3", 308 "ch4", "ch5", "ch6", "ch7", 309 "ch8", "ch9", "ch10", "ch11", 310 "ch12", "ch13", "ch14", "ch15"; 311 clocks = <&cpg CPG_MOD 218>; 312 clock-names = "fck"; 313 power-domains = <&sysc 32>; 314 resets = <&cpg 218>; 315 #dma-cells = <1>; 316 dma-channels = <16>; 317 }; 318 319 dmac2: dma-controller@e7310000 { 320 compatible = "renesas,dmac-r8a774a1", 321 "renesas,rcar-dmac"; 322 reg = <0 0xe7310000 0 0x10000>; 323 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 324 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 325 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 326 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 327 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 328 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 329 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 330 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 331 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 332 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 333 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 334 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 335 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 336 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 337 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 338 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 339 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-names = "error", 341 "ch0", "ch1", "ch2", "ch3", 342 "ch4", "ch5", "ch6", "ch7", 343 "ch8", "ch9", "ch10", "ch11", 344 "ch12", "ch13", "ch14", "ch15"; 345 clocks = <&cpg CPG_MOD 217>; 346 clock-names = "fck"; 347 power-domains = <&sysc 32>; 348 resets = <&cpg 217>; 349 #dma-cells = <1>; 350 dma-channels = <16>; 351 }; 352 353 scif0: serial@e6e60000 { 354 compatible = "renesas,scif-r8a774a1", 355 "renesas,rcar-gen3-scif", "renesas,scif"; 356 reg = <0 0xe6e60000 0 0x40>; 357 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&cpg CPG_MOD 207>, 359 <&cpg CPG_CORE 19>, 360 <&scif_clk>; 361 clock-names = "fck", "brg_int", "scif_clk"; 362 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 363 <&dmac2 0x51>, <&dmac2 0x50>; 364 dma-names = "tx", "rx", "tx", "rx"; 365 power-domains = <&sysc 32>; 366 resets = <&cpg 207>; 367 status = "disabled"; 368 }; 369 370 scif1: serial@e6e68000 { 371 compatible = "renesas,scif-r8a774a1", 372 "renesas,rcar-gen3-scif", "renesas,scif"; 373 reg = <0 0xe6e68000 0 0x40>; 374 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&cpg CPG_MOD 206>, 376 <&cpg CPG_CORE 19>, 377 <&scif_clk>; 378 clock-names = "fck", "brg_int", "scif_clk"; 379 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 380 <&dmac2 0x53>, <&dmac2 0x52>; 381 dma-names = "tx", "rx", "tx", "rx"; 382 power-domains = <&sysc 32>; 383 resets = <&cpg 206>; 384 status = "disabled"; 385 }; 386 387 scif2: serial@e6e88000 { 388 compatible = "renesas,scif-r8a774a1", 389 "renesas,rcar-gen3-scif", "renesas,scif"; 390 reg = <0 0xe6e88000 0 0x40>; 391 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&cpg CPG_MOD 310>, 393 <&cpg CPG_CORE 19>, 394 <&scif_clk>; 395 clock-names = "fck", "brg_int", "scif_clk"; 396 power-domains = <&sysc 32>; 397 resets = <&cpg 310>; 398 status = "disabled"; 399 }; 400 401 scif3: serial@e6c50000 { 402 compatible = "renesas,scif-r8a774a1", 403 "renesas,rcar-gen3-scif", "renesas,scif"; 404 reg = <0 0xe6c50000 0 0x40>; 405 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&cpg CPG_MOD 204>, 407 <&cpg CPG_CORE 19>, 408 <&scif_clk>; 409 clock-names = "fck", "brg_int", "scif_clk"; 410 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 411 dma-names = "tx", "rx"; 412 power-domains = <&sysc 32>; 413 resets = <&cpg 204>; 414 status = "disabled"; 415 }; 416 417 scif4: serial@e6c40000 { 418 compatible = "renesas,scif-r8a774a1", 419 "renesas,rcar-gen3-scif", "renesas,scif"; 420 reg = <0 0xe6c40000 0 0x40>; 421 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&cpg CPG_MOD 203>, 423 <&cpg CPG_CORE 19>, 424 <&scif_clk>; 425 clock-names = "fck", "brg_int", "scif_clk"; 426 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 427 dma-names = "tx", "rx"; 428 power-domains = <&sysc 32>; 429 resets = <&cpg 203>; 430 status = "disabled"; 431 }; 432 433 scif5: serial@e6f30000 { 434 compatible = "renesas,scif-r8a774a1", 435 "renesas,rcar-gen3-scif", "renesas,scif"; 436 reg = <0 0xe6f30000 0 0x40>; 437 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&cpg CPG_MOD 202>, 439 <&cpg CPG_CORE 19>, 440 <&scif_clk>; 441 clock-names = "fck", "brg_int", "scif_clk"; 442 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 443 <&dmac2 0x5b>, <&dmac2 0x5a>; 444 dma-names = "tx", "rx", "tx", "rx"; 445 power-domains = <&sysc 32>; 446 resets = <&cpg 202>; 447 status = "disabled"; 448 }; 449 450 gic: interrupt-controller@f1010000 { 451 compatible = "arm,gic-400"; 452 #interrupt-cells = <3>; 453 #address-cells = <0>; 454 interrupt-controller; 455 reg = <0x0 0xf1010000 0 0x1000>, 456 <0x0 0xf1020000 0 0x20000>, 457 <0x0 0xf1040000 0 0x20000>, 458 <0x0 0xf1060000 0 0x20000>; 459 interrupts = <GIC_PPI 9 460 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 461 clocks = <&cpg CPG_MOD 408>; 462 clock-names = "clk"; 463 power-domains = <&sysc 32>; 464 resets = <&cpg 408>; 465 }; 466 467 prr: chipid@fff00044 { 468 compatible = "renesas,prr"; 469 reg = <0 0xfff00044 0 4>; 470 }; 471 }; 472 473 timer { 474 compatible = "arm,armv8-timer"; 475 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 476 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 477 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 478 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 479 }; 480 481 /* External USB clocks - can be overridden by the board */ 482 usb3s0_clk: usb3s0 { 483 compatible = "fixed-clock"; 484 #clock-cells = <0>; 485 clock-frequency = <0>; 486 }; 487 488 usb_extal_clk: usb_extal { 489 compatible = "fixed-clock"; 490 #clock-cells = <0>; 491 clock-frequency = <0>; 492 }; 493}; 494