1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12/ { 13 compatible = "renesas,r8a774a1"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 /* 18 * The external audio clocks are configured as 0 Hz fixed frequency 19 * clocks by default. 20 * Boards that provide audio clocks should override them. 21 */ 22 audio_clk_a: audio_clk_a { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <0>; 26 }; 27 28 audio_clk_b: audio_clk_b { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 audio_clk_c: audio_clk_c { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 /* External CAN clock - to be overridden by boards that provide it */ 41 can_clk: can { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 a57_0: cpu@0 { 52 compatible = "arm,cortex-a57", "arm,armv8"; 53 reg = <0x0>; 54 device_type = "cpu"; 55 power-domains = <&sysc 0>; 56 next-level-cache = <&L2_CA57>; 57 enable-method = "psci"; 58 clocks =<&cpg CPG_CORE 0>; 59 }; 60 61 a57_1: cpu@1 { 62 compatible = "arm,cortex-a57", "arm,armv8"; 63 reg = <0x1>; 64 device_type = "cpu"; 65 power-domains = <&sysc 1>; 66 next-level-cache = <&L2_CA57>; 67 enable-method = "psci"; 68 clocks =<&cpg CPG_CORE 0>; 69 }; 70 71 L2_CA57: cache-controller-0 { 72 compatible = "cache"; 73 power-domains = <&sysc 12>; 74 cache-unified; 75 cache-level = <2>; 76 }; 77 }; 78 79 extal_clk: extal { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 /* This value must be overridden by the board */ 83 clock-frequency = <0>; 84 }; 85 86 extalr_clk: extalr { 87 compatible = "fixed-clock"; 88 #clock-cells = <0>; 89 /* This value must be overridden by the board */ 90 clock-frequency = <0>; 91 }; 92 93 /* External PCIe clock - can be overridden by the board */ 94 pcie_bus_clk: pcie_bus { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <0>; 98 }; 99 100 pmu_a57 { 101 compatible = "arm,cortex-a57-pmu"; 102 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 103 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 104 interrupt-affinity = <&a57_0>, <&a57_1>; 105 }; 106 107 psci { 108 compatible = "arm,psci-1.0", "arm,psci-0.2"; 109 method = "smc"; 110 }; 111 112 /* External SCIF clock - to be overridden by boards that provide it */ 113 scif_clk: scif { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 clock-frequency = <0>; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 interrupt-parent = <&gic>; 122 #address-cells = <2>; 123 #size-cells = <2>; 124 ranges; 125 126 cpg: clock-controller@e6150000 { 127 compatible = "renesas,r8a774a1-cpg-mssr"; 128 reg = <0 0xe6150000 0 0x0bb0>; 129 clocks = <&extal_clk>, <&extalr_clk>; 130 clock-names = "extal", "extalr"; 131 #clock-cells = <2>; 132 #power-domain-cells = <0>; 133 #reset-cells = <1>; 134 }; 135 136 rst: reset-controller@e6160000 { 137 compatible = "renesas,r8a774a1-rst"; 138 reg = <0 0xe6160000 0 0x018c>; 139 }; 140 141 sysc: system-controller@e6180000 { 142 compatible = "renesas,r8a774a1-sysc"; 143 reg = <0 0xe6180000 0 0x0400>; 144 #power-domain-cells = <1>; 145 }; 146 147 gic: interrupt-controller@f1010000 { 148 compatible = "arm,gic-400"; 149 #interrupt-cells = <3>; 150 #address-cells = <0>; 151 interrupt-controller; 152 reg = <0x0 0xf1010000 0 0x1000>, 153 <0x0 0xf1020000 0 0x20000>, 154 <0x0 0xf1040000 0 0x20000>, 155 <0x0 0xf1060000 0 0x20000>; 156 interrupts = <GIC_PPI 9 157 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 158 clocks = <&cpg CPG_MOD 408>; 159 clock-names = "clk"; 160 power-domains = <&sysc 32>; 161 resets = <&cpg 408>; 162 }; 163 164 prr: chipid@fff00044 { 165 compatible = "renesas,prr"; 166 reg = <0 0xfff00044 0 4>; 167 }; 168 }; 169 170 timer { 171 compatible = "arm,armv8-timer"; 172 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 173 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 174 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 175 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 176 }; 177 178 /* External USB clocks - can be overridden by the board */ 179 usb3s0_clk: usb3s0 { 180 compatible = "fixed-clock"; 181 #clock-cells = <0>; 182 clock-frequency = <0>; 183 }; 184 185 usb_extal_clk: usb_extal { 186 compatible = "fixed-clock"; 187 #clock-cells = <0>; 188 clock-frequency = <0>; 189 }; 190}; 191