1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12/ { 13 compatible = "renesas,r8a774a1"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 aliases { 18 i2c0 = &i2c0; 19 i2c1 = &i2c1; 20 i2c2 = &i2c2; 21 i2c3 = &i2c3; 22 i2c4 = &i2c4; 23 i2c5 = &i2c5; 24 i2c6 = &i2c6; 25 i2c7 = &i2c_dvfs; 26 }; 27 28 /* 29 * The external audio clocks are configured as 0 Hz fixed frequency 30 * clocks by default. 31 * Boards that provide audio clocks should override them. 32 */ 33 audio_clk_a: audio_clk_a { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <0>; 37 }; 38 39 audio_clk_b: audio_clk_b { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <0>; 43 }; 44 45 audio_clk_c: audio_clk_c { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <0>; 49 }; 50 51 /* External CAN clock - to be overridden by boards that provide it */ 52 can_clk: can { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <0>; 56 }; 57 58 cpus { 59 #address-cells = <1>; 60 #size-cells = <0>; 61 62 a57_0: cpu@0 { 63 compatible = "arm,cortex-a57", "arm,armv8"; 64 reg = <0x0>; 65 device_type = "cpu"; 66 power-domains = <&sysc 0>; 67 next-level-cache = <&L2_CA57>; 68 enable-method = "psci"; 69 clocks =<&cpg CPG_CORE 0>; 70 }; 71 72 a57_1: cpu@1 { 73 compatible = "arm,cortex-a57", "arm,armv8"; 74 reg = <0x1>; 75 device_type = "cpu"; 76 power-domains = <&sysc 1>; 77 next-level-cache = <&L2_CA57>; 78 enable-method = "psci"; 79 clocks =<&cpg CPG_CORE 0>; 80 }; 81 82 L2_CA57: cache-controller-0 { 83 compatible = "cache"; 84 power-domains = <&sysc 12>; 85 cache-unified; 86 cache-level = <2>; 87 }; 88 }; 89 90 extal_clk: extal { 91 compatible = "fixed-clock"; 92 #clock-cells = <0>; 93 /* This value must be overridden by the board */ 94 clock-frequency = <0>; 95 }; 96 97 extalr_clk: extalr { 98 compatible = "fixed-clock"; 99 #clock-cells = <0>; 100 /* This value must be overridden by the board */ 101 clock-frequency = <0>; 102 }; 103 104 /* External PCIe clock - can be overridden by the board */ 105 pcie_bus_clk: pcie_bus { 106 compatible = "fixed-clock"; 107 #clock-cells = <0>; 108 clock-frequency = <0>; 109 }; 110 111 pmu_a57 { 112 compatible = "arm,cortex-a57-pmu"; 113 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 114 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 115 interrupt-affinity = <&a57_0>, <&a57_1>; 116 }; 117 118 psci { 119 compatible = "arm,psci-1.0", "arm,psci-0.2"; 120 method = "smc"; 121 }; 122 123 /* External SCIF clock - to be overridden by boards that provide it */ 124 scif_clk: scif { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <0>; 128 }; 129 130 soc { 131 compatible = "simple-bus"; 132 interrupt-parent = <&gic>; 133 #address-cells = <2>; 134 #size-cells = <2>; 135 ranges; 136 137 rwdt: watchdog@e6020000 { 138 compatible = "renesas,r8a774a1-wdt", 139 "renesas,rcar-gen3-wdt"; 140 reg = <0 0xe6020000 0 0x0c>; 141 clocks = <&cpg CPG_MOD 402>; 142 power-domains = <&sysc 32>; 143 resets = <&cpg 402>; 144 status = "disabled"; 145 }; 146 147 gpio0: gpio@e6050000 { 148 compatible = "renesas,gpio-r8a774a1", 149 "renesas,rcar-gen3-gpio"; 150 reg = <0 0xe6050000 0 0x50>; 151 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 152 #gpio-cells = <2>; 153 gpio-controller; 154 gpio-ranges = <&pfc 0 0 16>; 155 #interrupt-cells = <2>; 156 interrupt-controller; 157 clocks = <&cpg CPG_MOD 912>; 158 power-domains = <&sysc 32>; 159 resets = <&cpg 912>; 160 }; 161 162 gpio1: gpio@e6051000 { 163 compatible = "renesas,gpio-r8a774a1", 164 "renesas,rcar-gen3-gpio"; 165 reg = <0 0xe6051000 0 0x50>; 166 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 167 #gpio-cells = <2>; 168 gpio-controller; 169 gpio-ranges = <&pfc 0 32 29>; 170 #interrupt-cells = <2>; 171 interrupt-controller; 172 clocks = <&cpg CPG_MOD 911>; 173 power-domains = <&sysc 32>; 174 resets = <&cpg 911>; 175 }; 176 177 gpio2: gpio@e6052000 { 178 compatible = "renesas,gpio-r8a774a1", 179 "renesas,rcar-gen3-gpio"; 180 reg = <0 0xe6052000 0 0x50>; 181 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 182 #gpio-cells = <2>; 183 gpio-controller; 184 gpio-ranges = <&pfc 0 64 15>; 185 #interrupt-cells = <2>; 186 interrupt-controller; 187 clocks = <&cpg CPG_MOD 910>; 188 power-domains = <&sysc 32>; 189 resets = <&cpg 910>; 190 }; 191 192 gpio3: gpio@e6053000 { 193 compatible = "renesas,gpio-r8a774a1", 194 "renesas,rcar-gen3-gpio"; 195 reg = <0 0xe6053000 0 0x50>; 196 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 197 #gpio-cells = <2>; 198 gpio-controller; 199 gpio-ranges = <&pfc 0 96 16>; 200 #interrupt-cells = <2>; 201 interrupt-controller; 202 clocks = <&cpg CPG_MOD 909>; 203 power-domains = <&sysc 32>; 204 resets = <&cpg 909>; 205 }; 206 207 gpio4: gpio@e6054000 { 208 compatible = "renesas,gpio-r8a774a1", 209 "renesas,rcar-gen3-gpio"; 210 reg = <0 0xe6054000 0 0x50>; 211 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 212 #gpio-cells = <2>; 213 gpio-controller; 214 gpio-ranges = <&pfc 0 128 18>; 215 #interrupt-cells = <2>; 216 interrupt-controller; 217 clocks = <&cpg CPG_MOD 908>; 218 power-domains = <&sysc 32>; 219 resets = <&cpg 908>; 220 }; 221 222 gpio5: gpio@e6055000 { 223 compatible = "renesas,gpio-r8a774a1", 224 "renesas,rcar-gen3-gpio"; 225 reg = <0 0xe6055000 0 0x50>; 226 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 227 #gpio-cells = <2>; 228 gpio-controller; 229 gpio-ranges = <&pfc 0 160 26>; 230 #interrupt-cells = <2>; 231 interrupt-controller; 232 clocks = <&cpg CPG_MOD 907>; 233 power-domains = <&sysc 32>; 234 resets = <&cpg 907>; 235 }; 236 237 gpio6: gpio@e6055400 { 238 compatible = "renesas,gpio-r8a774a1", 239 "renesas,rcar-gen3-gpio"; 240 reg = <0 0xe6055400 0 0x50>; 241 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 242 #gpio-cells = <2>; 243 gpio-controller; 244 gpio-ranges = <&pfc 0 192 32>; 245 #interrupt-cells = <2>; 246 interrupt-controller; 247 clocks = <&cpg CPG_MOD 906>; 248 power-domains = <&sysc 32>; 249 resets = <&cpg 906>; 250 }; 251 252 gpio7: gpio@e6055800 { 253 compatible = "renesas,gpio-r8a774a1", 254 "renesas,rcar-gen3-gpio"; 255 reg = <0 0xe6055800 0 0x50>; 256 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 257 #gpio-cells = <2>; 258 gpio-controller; 259 gpio-ranges = <&pfc 0 224 4>; 260 #interrupt-cells = <2>; 261 interrupt-controller; 262 clocks = <&cpg CPG_MOD 905>; 263 power-domains = <&sysc 32>; 264 resets = <&cpg 905>; 265 }; 266 267 pfc: pin-controller@e6060000 { 268 compatible = "renesas,pfc-r8a774a1"; 269 reg = <0 0xe6060000 0 0x50c>; 270 }; 271 272 cpg: clock-controller@e6150000 { 273 compatible = "renesas,r8a774a1-cpg-mssr"; 274 reg = <0 0xe6150000 0 0x0bb0>; 275 clocks = <&extal_clk>, <&extalr_clk>; 276 clock-names = "extal", "extalr"; 277 #clock-cells = <2>; 278 #power-domain-cells = <0>; 279 #reset-cells = <1>; 280 }; 281 282 rst: reset-controller@e6160000 { 283 compatible = "renesas,r8a774a1-rst"; 284 reg = <0 0xe6160000 0 0x018c>; 285 }; 286 287 sysc: system-controller@e6180000 { 288 compatible = "renesas,r8a774a1-sysc"; 289 reg = <0 0xe6180000 0 0x0400>; 290 #power-domain-cells = <1>; 291 }; 292 293 tsc: thermal@e6198000 { 294 compatible = "renesas,r8a774a1-thermal"; 295 reg = <0 0xe6198000 0 0x100>, 296 <0 0xe61a0000 0 0x100>, 297 <0 0xe61a8000 0 0x100>; 298 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&cpg CPG_MOD 522>; 302 power-domains = <&sysc 32>; 303 resets = <&cpg 522>; 304 #thermal-sensor-cells = <1>; 305 status = "okay"; 306 }; 307 308 intc_ex: interrupt-controller@e61c0000 { 309 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; 310 #interrupt-cells = <2>; 311 interrupt-controller; 312 reg = <0 0xe61c0000 0 0x200>; 313 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 314 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 315 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 316 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 317 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 318 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&cpg CPG_MOD 407>; 320 power-domains = <&sysc 32>; 321 resets = <&cpg 407>; 322 }; 323 324 i2c0: i2c@e6500000 { 325 #address-cells = <1>; 326 #size-cells = <0>; 327 compatible = "renesas,i2c-r8a774a1", 328 "renesas,rcar-gen3-i2c"; 329 reg = <0 0xe6500000 0 0x40>; 330 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&cpg CPG_MOD 931>; 332 power-domains = <&sysc 32>; 333 resets = <&cpg 931>; 334 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 335 <&dmac2 0x91>, <&dmac2 0x90>; 336 dma-names = "tx", "rx", "tx", "rx"; 337 i2c-scl-internal-delay-ns = <110>; 338 status = "disabled"; 339 }; 340 341 i2c1: i2c@e6508000 { 342 #address-cells = <1>; 343 #size-cells = <0>; 344 compatible = "renesas,i2c-r8a774a1", 345 "renesas,rcar-gen3-i2c"; 346 reg = <0 0xe6508000 0 0x40>; 347 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&cpg CPG_MOD 930>; 349 power-domains = <&sysc 32>; 350 resets = <&cpg 930>; 351 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 352 <&dmac2 0x93>, <&dmac2 0x92>; 353 dma-names = "tx", "rx", "tx", "rx"; 354 i2c-scl-internal-delay-ns = <6>; 355 status = "disabled"; 356 }; 357 358 i2c2: i2c@e6510000 { 359 #address-cells = <1>; 360 #size-cells = <0>; 361 compatible = "renesas,i2c-r8a774a1", 362 "renesas,rcar-gen3-i2c"; 363 reg = <0 0xe6510000 0 0x40>; 364 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&cpg CPG_MOD 929>; 366 power-domains = <&sysc 32>; 367 resets = <&cpg 929>; 368 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 369 <&dmac2 0x95>, <&dmac2 0x94>; 370 dma-names = "tx", "rx", "tx", "rx"; 371 i2c-scl-internal-delay-ns = <6>; 372 status = "disabled"; 373 }; 374 375 i2c3: i2c@e66d0000 { 376 #address-cells = <1>; 377 #size-cells = <0>; 378 compatible = "renesas,i2c-r8a774a1", 379 "renesas,rcar-gen3-i2c"; 380 reg = <0 0xe66d0000 0 0x40>; 381 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&cpg CPG_MOD 928>; 383 power-domains = <&sysc 32>; 384 resets = <&cpg 928>; 385 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 386 dma-names = "tx", "rx"; 387 i2c-scl-internal-delay-ns = <110>; 388 status = "disabled"; 389 }; 390 391 i2c4: i2c@e66d8000 { 392 #address-cells = <1>; 393 #size-cells = <0>; 394 compatible = "renesas,i2c-r8a774a1", 395 "renesas,rcar-gen3-i2c"; 396 reg = <0 0xe66d8000 0 0x40>; 397 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&cpg CPG_MOD 927>; 399 power-domains = <&sysc 32>; 400 resets = <&cpg 927>; 401 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 402 dma-names = "tx", "rx"; 403 i2c-scl-internal-delay-ns = <110>; 404 status = "disabled"; 405 }; 406 407 i2c5: i2c@e66e0000 { 408 #address-cells = <1>; 409 #size-cells = <0>; 410 compatible = "renesas,i2c-r8a774a1", 411 "renesas,rcar-gen3-i2c"; 412 reg = <0 0xe66e0000 0 0x40>; 413 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&cpg CPG_MOD 919>; 415 power-domains = <&sysc 32>; 416 resets = <&cpg 919>; 417 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 418 dma-names = "tx", "rx"; 419 i2c-scl-internal-delay-ns = <110>; 420 status = "disabled"; 421 }; 422 423 i2c6: i2c@e66e8000 { 424 #address-cells = <1>; 425 #size-cells = <0>; 426 compatible = "renesas,i2c-r8a774a1", 427 "renesas,rcar-gen3-i2c"; 428 reg = <0 0xe66e8000 0 0x40>; 429 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&cpg CPG_MOD 918>; 431 power-domains = <&sysc 32>; 432 resets = <&cpg 918>; 433 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 434 dma-names = "tx", "rx"; 435 i2c-scl-internal-delay-ns = <6>; 436 status = "disabled"; 437 }; 438 439 i2c_dvfs: i2c@e60b0000 { 440 #address-cells = <1>; 441 #size-cells = <0>; 442 compatible = "renesas,iic-r8a774a1", 443 "renesas,rcar-gen3-iic", 444 "renesas,rmobile-iic"; 445 reg = <0 0xe60b0000 0 0x425>; 446 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&cpg CPG_MOD 926>; 448 power-domains = <&sysc 32>; 449 resets = <&cpg 926>; 450 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 451 dma-names = "tx", "rx"; 452 status = "disabled"; 453 }; 454 455 hscif0: serial@e6540000 { 456 compatible = "renesas,hscif-r8a774a1", 457 "renesas,rcar-gen3-hscif", 458 "renesas,hscif"; 459 reg = <0 0xe6540000 0 0x60>; 460 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&cpg CPG_MOD 520>, 462 <&cpg CPG_CORE 19>, 463 <&scif_clk>; 464 clock-names = "fck", "brg_int", "scif_clk"; 465 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 466 <&dmac2 0x31>, <&dmac2 0x30>; 467 dma-names = "tx", "rx", "tx", "rx"; 468 power-domains = <&sysc 32>; 469 resets = <&cpg 520>; 470 status = "disabled"; 471 }; 472 473 hscif1: serial@e6550000 { 474 compatible = "renesas,hscif-r8a774a1", 475 "renesas,rcar-gen3-hscif", 476 "renesas,hscif"; 477 reg = <0 0xe6550000 0 0x60>; 478 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&cpg CPG_MOD 519>, 480 <&cpg CPG_CORE 19>, 481 <&scif_clk>; 482 clock-names = "fck", "brg_int", "scif_clk"; 483 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 484 <&dmac2 0x33>, <&dmac2 0x32>; 485 dma-names = "tx", "rx", "tx", "rx"; 486 power-domains = <&sysc 32>; 487 resets = <&cpg 519>; 488 status = "disabled"; 489 }; 490 491 hscif2: serial@e6560000 { 492 compatible = "renesas,hscif-r8a774a1", 493 "renesas,rcar-gen3-hscif", 494 "renesas,hscif"; 495 reg = <0 0xe6560000 0 0x60>; 496 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&cpg CPG_MOD 518>, 498 <&cpg CPG_CORE 19>, 499 <&scif_clk>; 500 clock-names = "fck", "brg_int", "scif_clk"; 501 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 502 <&dmac2 0x35>, <&dmac2 0x34>; 503 dma-names = "tx", "rx", "tx", "rx"; 504 power-domains = <&sysc 32>; 505 resets = <&cpg 518>; 506 status = "disabled"; 507 }; 508 509 hscif3: serial@e66a0000 { 510 compatible = "renesas,hscif-r8a774a1", 511 "renesas,rcar-gen3-hscif", 512 "renesas,hscif"; 513 reg = <0 0xe66a0000 0 0x60>; 514 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&cpg CPG_MOD 517>, 516 <&cpg CPG_CORE 19>, 517 <&scif_clk>; 518 clock-names = "fck", "brg_int", "scif_clk"; 519 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 520 dma-names = "tx", "rx"; 521 power-domains = <&sysc 32>; 522 resets = <&cpg 517>; 523 status = "disabled"; 524 }; 525 526 hscif4: serial@e66b0000 { 527 compatible = "renesas,hscif-r8a774a1", 528 "renesas,rcar-gen3-hscif", 529 "renesas,hscif"; 530 reg = <0 0xe66b0000 0 0x60>; 531 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&cpg CPG_MOD 516>, 533 <&cpg CPG_CORE 19>, 534 <&scif_clk>; 535 clock-names = "fck", "brg_int", "scif_clk"; 536 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 537 dma-names = "tx", "rx"; 538 power-domains = <&sysc 32>; 539 resets = <&cpg 516>; 540 status = "disabled"; 541 }; 542 543 dmac0: dma-controller@e6700000 { 544 compatible = "renesas,dmac-r8a774a1", 545 "renesas,rcar-dmac"; 546 reg = <0 0xe6700000 0 0x10000>; 547 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 548 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 549 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 550 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 551 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 552 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 553 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 554 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 555 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 556 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 557 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 558 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 559 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 560 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 561 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 562 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 563 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 564 interrupt-names = "error", 565 "ch0", "ch1", "ch2", "ch3", 566 "ch4", "ch5", "ch6", "ch7", 567 "ch8", "ch9", "ch10", "ch11", 568 "ch12", "ch13", "ch14", "ch15"; 569 clocks = <&cpg CPG_MOD 219>; 570 clock-names = "fck"; 571 power-domains = <&sysc 32>; 572 resets = <&cpg 219>; 573 #dma-cells = <1>; 574 dma-channels = <16>; 575 }; 576 577 dmac1: dma-controller@e7300000 { 578 compatible = "renesas,dmac-r8a774a1", 579 "renesas,rcar-dmac"; 580 reg = <0 0xe7300000 0 0x10000>; 581 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 582 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 583 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 584 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 585 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 586 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 587 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 588 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 589 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 590 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 591 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 592 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 593 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 594 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 595 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 596 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 597 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 598 interrupt-names = "error", 599 "ch0", "ch1", "ch2", "ch3", 600 "ch4", "ch5", "ch6", "ch7", 601 "ch8", "ch9", "ch10", "ch11", 602 "ch12", "ch13", "ch14", "ch15"; 603 clocks = <&cpg CPG_MOD 218>; 604 clock-names = "fck"; 605 power-domains = <&sysc 32>; 606 resets = <&cpg 218>; 607 #dma-cells = <1>; 608 dma-channels = <16>; 609 }; 610 611 dmac2: dma-controller@e7310000 { 612 compatible = "renesas,dmac-r8a774a1", 613 "renesas,rcar-dmac"; 614 reg = <0 0xe7310000 0 0x10000>; 615 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 616 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 617 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 618 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 619 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 620 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 621 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 622 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 623 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 624 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 625 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 626 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 627 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 628 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 629 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 630 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 631 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 632 interrupt-names = "error", 633 "ch0", "ch1", "ch2", "ch3", 634 "ch4", "ch5", "ch6", "ch7", 635 "ch8", "ch9", "ch10", "ch11", 636 "ch12", "ch13", "ch14", "ch15"; 637 clocks = <&cpg CPG_MOD 217>; 638 clock-names = "fck"; 639 power-domains = <&sysc 32>; 640 resets = <&cpg 217>; 641 #dma-cells = <1>; 642 dma-channels = <16>; 643 }; 644 645 ipmmu_ds0: mmu@e6740000 { 646 compatible = "renesas,ipmmu-r8a774a1"; 647 reg = <0 0xe6740000 0 0x1000>; 648 renesas,ipmmu-main = <&ipmmu_mm 0>; 649 power-domains = <&sysc 32>; 650 #iommu-cells = <1>; 651 }; 652 653 ipmmu_ds1: mmu@e7740000 { 654 compatible = "renesas,ipmmu-r8a774a1"; 655 reg = <0 0xe7740000 0 0x1000>; 656 renesas,ipmmu-main = <&ipmmu_mm 1>; 657 power-domains = <&sysc 32>; 658 #iommu-cells = <1>; 659 }; 660 661 ipmmu_hc: mmu@e6570000 { 662 compatible = "renesas,ipmmu-r8a774a1"; 663 reg = <0 0xe6570000 0 0x1000>; 664 renesas,ipmmu-main = <&ipmmu_mm 2>; 665 power-domains = <&sysc 32>; 666 #iommu-cells = <1>; 667 }; 668 669 ipmmu_mm: mmu@e67b0000 { 670 compatible = "renesas,ipmmu-r8a774a1"; 671 reg = <0 0xe67b0000 0 0x1000>; 672 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 674 power-domains = <&sysc 32>; 675 #iommu-cells = <1>; 676 }; 677 678 ipmmu_mp: mmu@ec670000 { 679 compatible = "renesas,ipmmu-r8a774a1"; 680 reg = <0 0xec670000 0 0x1000>; 681 renesas,ipmmu-main = <&ipmmu_mm 4>; 682 power-domains = <&sysc 32>; 683 #iommu-cells = <1>; 684 }; 685 686 ipmmu_pv0: mmu@fd800000 { 687 compatible = "renesas,ipmmu-r8a774a1"; 688 reg = <0 0xfd800000 0 0x1000>; 689 renesas,ipmmu-main = <&ipmmu_mm 5>; 690 power-domains = <&sysc 32>; 691 #iommu-cells = <1>; 692 }; 693 694 ipmmu_pv1: mmu@fd950000 { 695 compatible = "renesas,ipmmu-r8a774a1"; 696 reg = <0 0xfd950000 0 0x1000>; 697 renesas,ipmmu-main = <&ipmmu_mm 6>; 698 power-domains = <&sysc 32>; 699 #iommu-cells = <1>; 700 }; 701 702 ipmmu_vc0: mmu@fe6b0000 { 703 compatible = "renesas,ipmmu-r8a774a1"; 704 reg = <0 0xfe6b0000 0 0x1000>; 705 renesas,ipmmu-main = <&ipmmu_mm 8>; 706 power-domains = <&sysc 14>; 707 #iommu-cells = <1>; 708 }; 709 710 ipmmu_vi0: mmu@febd0000 { 711 compatible = "renesas,ipmmu-r8a774a1"; 712 reg = <0 0xfebd0000 0 0x1000>; 713 renesas,ipmmu-main = <&ipmmu_mm 9>; 714 power-domains = <&sysc 32>; 715 #iommu-cells = <1>; 716 }; 717 718 avb: ethernet@e6800000 { 719 compatible = "renesas,etheravb-r8a774a1", 720 "renesas,etheravb-rcar-gen3"; 721 reg = <0 0xe6800000 0 0x800>; 722 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 747 interrupt-names = "ch0", "ch1", "ch2", "ch3", 748 "ch4", "ch5", "ch6", "ch7", 749 "ch8", "ch9", "ch10", "ch11", 750 "ch12", "ch13", "ch14", "ch15", 751 "ch16", "ch17", "ch18", "ch19", 752 "ch20", "ch21", "ch22", "ch23", 753 "ch24"; 754 clocks = <&cpg CPG_MOD 812>; 755 power-domains = <&sysc 32>; 756 resets = <&cpg 812>; 757 phy-mode = "rgmii"; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 status = "disabled"; 761 }; 762 763 scif0: serial@e6e60000 { 764 compatible = "renesas,scif-r8a774a1", 765 "renesas,rcar-gen3-scif", "renesas,scif"; 766 reg = <0 0xe6e60000 0 0x40>; 767 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&cpg CPG_MOD 207>, 769 <&cpg CPG_CORE 19>, 770 <&scif_clk>; 771 clock-names = "fck", "brg_int", "scif_clk"; 772 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 773 <&dmac2 0x51>, <&dmac2 0x50>; 774 dma-names = "tx", "rx", "tx", "rx"; 775 power-domains = <&sysc 32>; 776 resets = <&cpg 207>; 777 status = "disabled"; 778 }; 779 780 scif1: serial@e6e68000 { 781 compatible = "renesas,scif-r8a774a1", 782 "renesas,rcar-gen3-scif", "renesas,scif"; 783 reg = <0 0xe6e68000 0 0x40>; 784 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&cpg CPG_MOD 206>, 786 <&cpg CPG_CORE 19>, 787 <&scif_clk>; 788 clock-names = "fck", "brg_int", "scif_clk"; 789 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 790 <&dmac2 0x53>, <&dmac2 0x52>; 791 dma-names = "tx", "rx", "tx", "rx"; 792 power-domains = <&sysc 32>; 793 resets = <&cpg 206>; 794 status = "disabled"; 795 }; 796 797 scif2: serial@e6e88000 { 798 compatible = "renesas,scif-r8a774a1", 799 "renesas,rcar-gen3-scif", "renesas,scif"; 800 reg = <0 0xe6e88000 0 0x40>; 801 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&cpg CPG_MOD 310>, 803 <&cpg CPG_CORE 19>, 804 <&scif_clk>; 805 clock-names = "fck", "brg_int", "scif_clk"; 806 power-domains = <&sysc 32>; 807 resets = <&cpg 310>; 808 status = "disabled"; 809 }; 810 811 scif3: serial@e6c50000 { 812 compatible = "renesas,scif-r8a774a1", 813 "renesas,rcar-gen3-scif", "renesas,scif"; 814 reg = <0 0xe6c50000 0 0x40>; 815 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 816 clocks = <&cpg CPG_MOD 204>, 817 <&cpg CPG_CORE 19>, 818 <&scif_clk>; 819 clock-names = "fck", "brg_int", "scif_clk"; 820 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 821 dma-names = "tx", "rx"; 822 power-domains = <&sysc 32>; 823 resets = <&cpg 204>; 824 status = "disabled"; 825 }; 826 827 scif4: serial@e6c40000 { 828 compatible = "renesas,scif-r8a774a1", 829 "renesas,rcar-gen3-scif", "renesas,scif"; 830 reg = <0 0xe6c40000 0 0x40>; 831 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 832 clocks = <&cpg CPG_MOD 203>, 833 <&cpg CPG_CORE 19>, 834 <&scif_clk>; 835 clock-names = "fck", "brg_int", "scif_clk"; 836 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 837 dma-names = "tx", "rx"; 838 power-domains = <&sysc 32>; 839 resets = <&cpg 203>; 840 status = "disabled"; 841 }; 842 843 scif5: serial@e6f30000 { 844 compatible = "renesas,scif-r8a774a1", 845 "renesas,rcar-gen3-scif", "renesas,scif"; 846 reg = <0 0xe6f30000 0 0x40>; 847 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&cpg CPG_MOD 202>, 849 <&cpg CPG_CORE 19>, 850 <&scif_clk>; 851 clock-names = "fck", "brg_int", "scif_clk"; 852 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 853 <&dmac2 0x5b>, <&dmac2 0x5a>; 854 dma-names = "tx", "rx", "tx", "rx"; 855 power-domains = <&sysc 32>; 856 resets = <&cpg 202>; 857 status = "disabled"; 858 }; 859 860 sdhi0: sd@ee100000 { 861 compatible = "renesas,sdhi-r8a774a1", 862 "renesas,rcar-gen3-sdhi"; 863 reg = <0 0xee100000 0 0x2000>; 864 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&cpg CPG_MOD 314>; 866 max-frequency = <200000000>; 867 power-domains = <&sysc 32>; 868 resets = <&cpg 314>; 869 status = "disabled"; 870 }; 871 872 sdhi1: sd@ee120000 { 873 compatible = "renesas,sdhi-r8a774a1", 874 "renesas,rcar-gen3-sdhi"; 875 reg = <0 0xee120000 0 0x2000>; 876 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 877 clocks = <&cpg CPG_MOD 313>; 878 max-frequency = <200000000>; 879 power-domains = <&sysc 32>; 880 resets = <&cpg 313>; 881 status = "disabled"; 882 }; 883 884 sdhi2: sd@ee140000 { 885 compatible = "renesas,sdhi-r8a774a1", 886 "renesas,rcar-gen3-sdhi"; 887 reg = <0 0xee140000 0 0x2000>; 888 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&cpg CPG_MOD 312>; 890 max-frequency = <200000000>; 891 power-domains = <&sysc 32>; 892 resets = <&cpg 312>; 893 status = "disabled"; 894 }; 895 896 sdhi3: sd@ee160000 { 897 compatible = "renesas,sdhi-r8a774a1", 898 "renesas,rcar-gen3-sdhi"; 899 reg = <0 0xee160000 0 0x2000>; 900 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&cpg CPG_MOD 311>; 902 max-frequency = <200000000>; 903 power-domains = <&sysc 32>; 904 resets = <&cpg 311>; 905 status = "disabled"; 906 }; 907 908 gic: interrupt-controller@f1010000 { 909 compatible = "arm,gic-400"; 910 #interrupt-cells = <3>; 911 #address-cells = <0>; 912 interrupt-controller; 913 reg = <0x0 0xf1010000 0 0x1000>, 914 <0x0 0xf1020000 0 0x20000>, 915 <0x0 0xf1040000 0 0x20000>, 916 <0x0 0xf1060000 0 0x20000>; 917 interrupts = <GIC_PPI 9 918 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 919 clocks = <&cpg CPG_MOD 408>; 920 clock-names = "clk"; 921 power-domains = <&sysc 32>; 922 resets = <&cpg 408>; 923 }; 924 925 prr: chipid@fff00044 { 926 compatible = "renesas,prr"; 927 reg = <0 0xfff00044 0 4>; 928 }; 929 }; 930 931 thermal-zones { 932 sensor_thermal1: sensor-thermal1 { 933 polling-delay-passive = <250>; 934 polling-delay = <1000>; 935 thermal-sensors = <&tsc 0>; 936 937 trips { 938 sensor1_crit: sensor1-crit { 939 temperature = <120000>; 940 hysteresis = <1000>; 941 type = "critical"; 942 }; 943 }; 944 }; 945 946 sensor_thermal2: sensor-thermal2 { 947 polling-delay-passive = <250>; 948 polling-delay = <1000>; 949 thermal-sensors = <&tsc 1>; 950 951 trips { 952 sensor2_crit: sensor2-crit { 953 temperature = <120000>; 954 hysteresis = <1000>; 955 type = "critical"; 956 }; 957 }; 958 959 }; 960 961 sensor_thermal3: sensor-thermal3 { 962 polling-delay-passive = <250>; 963 polling-delay = <1000>; 964 thermal-sensors = <&tsc 2>; 965 966 trips { 967 sensor3_crit: sensor3-crit { 968 temperature = <120000>; 969 hysteresis = <1000>; 970 type = "critical"; 971 }; 972 }; 973 }; 974 }; 975 976 timer { 977 compatible = "arm,armv8-timer"; 978 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 979 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 980 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 981 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 982 }; 983 984 /* External USB clocks - can be overridden by the board */ 985 usb3s0_clk: usb3s0 { 986 compatible = "fixed-clock"; 987 #clock-cells = <0>; 988 clock-frequency = <0>; 989 }; 990 991 usb_extal_clk: usb_extal { 992 compatible = "fixed-clock"; 993 #clock-cells = <0>; 994 clock-frequency = <0>; 995 }; 996}; 997