1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774a1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774a1-sysc.h> 12 13/ { 14 compatible = "renesas,r8a774a1"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 i2c5 = &i2c5; 25 i2c6 = &i2c6; 26 i2c7 = &i2c_dvfs; 27 }; 28 29 /* 30 * The external audio clocks are configured as 0 Hz fixed frequency 31 * clocks by default. 32 * Boards that provide audio clocks should override them. 33 */ 34 audio_clk_a: audio_clk_a { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 audio_clk_b: audio_clk_b { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <0>; 44 }; 45 46 audio_clk_c: audio_clk_c { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <0>; 50 }; 51 52 /* External CAN clock - to be overridden by boards that provide it */ 53 can_clk: can { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <0>; 57 }; 58 59 cpus { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 a57_0: cpu@0 { 64 compatible = "arm,cortex-a57"; 65 reg = <0x0>; 66 device_type = "cpu"; 67 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; 68 next-level-cache = <&L2_CA57>; 69 enable-method = "psci"; 70 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 71 }; 72 73 a57_1: cpu@1 { 74 compatible = "arm,cortex-a57"; 75 reg = <0x1>; 76 device_type = "cpu"; 77 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; 78 next-level-cache = <&L2_CA57>; 79 enable-method = "psci"; 80 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 81 }; 82 83 a53_0: cpu@100 { 84 compatible = "arm,cortex-a53"; 85 reg = <0x100>; 86 device_type = "cpu"; 87 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; 88 next-level-cache = <&L2_CA53>; 89 enable-method = "psci"; 90 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 91 }; 92 93 a53_1: cpu@101 { 94 compatible = "arm,cortex-a53"; 95 reg = <0x101>; 96 device_type = "cpu"; 97 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; 98 next-level-cache = <&L2_CA53>; 99 enable-method = "psci"; 100 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 101 }; 102 103 a53_2: cpu@102 { 104 compatible = "arm,cortex-a53"; 105 reg = <0x102>; 106 device_type = "cpu"; 107 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; 108 next-level-cache = <&L2_CA53>; 109 enable-method = "psci"; 110 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 111 }; 112 113 a53_3: cpu@103 { 114 compatible = "arm,cortex-a53"; 115 reg = <0x103>; 116 device_type = "cpu"; 117 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; 118 next-level-cache = <&L2_CA53>; 119 enable-method = "psci"; 120 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 121 }; 122 123 L2_CA57: cache-controller-0 { 124 compatible = "cache"; 125 power-domains = <&sysc R8A774A1_PD_CA57_SCU>; 126 cache-unified; 127 cache-level = <2>; 128 }; 129 130 L2_CA53: cache-controller-1 { 131 compatible = "cache"; 132 power-domains = <&sysc R8A774A1_PD_CA53_SCU>; 133 cache-unified; 134 cache-level = <2>; 135 }; 136 }; 137 138 extal_clk: extal { 139 compatible = "fixed-clock"; 140 #clock-cells = <0>; 141 /* This value must be overridden by the board */ 142 clock-frequency = <0>; 143 }; 144 145 extalr_clk: extalr { 146 compatible = "fixed-clock"; 147 #clock-cells = <0>; 148 /* This value must be overridden by the board */ 149 clock-frequency = <0>; 150 }; 151 152 /* External PCIe clock - can be overridden by the board */ 153 pcie_bus_clk: pcie_bus { 154 compatible = "fixed-clock"; 155 #clock-cells = <0>; 156 clock-frequency = <0>; 157 }; 158 159 pmu_a53 { 160 compatible = "arm,cortex-a53-pmu"; 161 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 162 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 163 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 164 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 165 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 166 }; 167 168 pmu_a57 { 169 compatible = "arm,cortex-a57-pmu"; 170 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 171 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 172 interrupt-affinity = <&a57_0>, <&a57_1>; 173 }; 174 175 psci { 176 compatible = "arm,psci-1.0", "arm,psci-0.2"; 177 method = "smc"; 178 }; 179 180 /* External SCIF clock - to be overridden by boards that provide it */ 181 scif_clk: scif { 182 compatible = "fixed-clock"; 183 #clock-cells = <0>; 184 clock-frequency = <0>; 185 }; 186 187 soc { 188 compatible = "simple-bus"; 189 interrupt-parent = <&gic>; 190 #address-cells = <2>; 191 #size-cells = <2>; 192 ranges; 193 194 rwdt: watchdog@e6020000 { 195 compatible = "renesas,r8a774a1-wdt", 196 "renesas,rcar-gen3-wdt"; 197 reg = <0 0xe6020000 0 0x0c>; 198 clocks = <&cpg CPG_MOD 402>; 199 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 200 resets = <&cpg 402>; 201 status = "disabled"; 202 }; 203 204 gpio0: gpio@e6050000 { 205 compatible = "renesas,gpio-r8a774a1", 206 "renesas,rcar-gen3-gpio"; 207 reg = <0 0xe6050000 0 0x50>; 208 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 209 #gpio-cells = <2>; 210 gpio-controller; 211 gpio-ranges = <&pfc 0 0 16>; 212 #interrupt-cells = <2>; 213 interrupt-controller; 214 clocks = <&cpg CPG_MOD 912>; 215 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 216 resets = <&cpg 912>; 217 }; 218 219 gpio1: gpio@e6051000 { 220 compatible = "renesas,gpio-r8a774a1", 221 "renesas,rcar-gen3-gpio"; 222 reg = <0 0xe6051000 0 0x50>; 223 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 224 #gpio-cells = <2>; 225 gpio-controller; 226 gpio-ranges = <&pfc 0 32 29>; 227 #interrupt-cells = <2>; 228 interrupt-controller; 229 clocks = <&cpg CPG_MOD 911>; 230 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 231 resets = <&cpg 911>; 232 }; 233 234 gpio2: gpio@e6052000 { 235 compatible = "renesas,gpio-r8a774a1", 236 "renesas,rcar-gen3-gpio"; 237 reg = <0 0xe6052000 0 0x50>; 238 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 239 #gpio-cells = <2>; 240 gpio-controller; 241 gpio-ranges = <&pfc 0 64 15>; 242 #interrupt-cells = <2>; 243 interrupt-controller; 244 clocks = <&cpg CPG_MOD 910>; 245 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 246 resets = <&cpg 910>; 247 }; 248 249 gpio3: gpio@e6053000 { 250 compatible = "renesas,gpio-r8a774a1", 251 "renesas,rcar-gen3-gpio"; 252 reg = <0 0xe6053000 0 0x50>; 253 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 254 #gpio-cells = <2>; 255 gpio-controller; 256 gpio-ranges = <&pfc 0 96 16>; 257 #interrupt-cells = <2>; 258 interrupt-controller; 259 clocks = <&cpg CPG_MOD 909>; 260 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 261 resets = <&cpg 909>; 262 }; 263 264 gpio4: gpio@e6054000 { 265 compatible = "renesas,gpio-r8a774a1", 266 "renesas,rcar-gen3-gpio"; 267 reg = <0 0xe6054000 0 0x50>; 268 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 269 #gpio-cells = <2>; 270 gpio-controller; 271 gpio-ranges = <&pfc 0 128 18>; 272 #interrupt-cells = <2>; 273 interrupt-controller; 274 clocks = <&cpg CPG_MOD 908>; 275 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 276 resets = <&cpg 908>; 277 }; 278 279 gpio5: gpio@e6055000 { 280 compatible = "renesas,gpio-r8a774a1", 281 "renesas,rcar-gen3-gpio"; 282 reg = <0 0xe6055000 0 0x50>; 283 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 284 #gpio-cells = <2>; 285 gpio-controller; 286 gpio-ranges = <&pfc 0 160 26>; 287 #interrupt-cells = <2>; 288 interrupt-controller; 289 clocks = <&cpg CPG_MOD 907>; 290 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 291 resets = <&cpg 907>; 292 }; 293 294 gpio6: gpio@e6055400 { 295 compatible = "renesas,gpio-r8a774a1", 296 "renesas,rcar-gen3-gpio"; 297 reg = <0 0xe6055400 0 0x50>; 298 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 299 #gpio-cells = <2>; 300 gpio-controller; 301 gpio-ranges = <&pfc 0 192 32>; 302 #interrupt-cells = <2>; 303 interrupt-controller; 304 clocks = <&cpg CPG_MOD 906>; 305 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 306 resets = <&cpg 906>; 307 }; 308 309 gpio7: gpio@e6055800 { 310 compatible = "renesas,gpio-r8a774a1", 311 "renesas,rcar-gen3-gpio"; 312 reg = <0 0xe6055800 0 0x50>; 313 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 314 #gpio-cells = <2>; 315 gpio-controller; 316 gpio-ranges = <&pfc 0 224 4>; 317 #interrupt-cells = <2>; 318 interrupt-controller; 319 clocks = <&cpg CPG_MOD 905>; 320 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 321 resets = <&cpg 905>; 322 }; 323 324 pfc: pin-controller@e6060000 { 325 compatible = "renesas,pfc-r8a774a1"; 326 reg = <0 0xe6060000 0 0x50c>; 327 }; 328 329 cpg: clock-controller@e6150000 { 330 compatible = "renesas,r8a774a1-cpg-mssr"; 331 reg = <0 0xe6150000 0 0x0bb0>; 332 clocks = <&extal_clk>, <&extalr_clk>; 333 clock-names = "extal", "extalr"; 334 #clock-cells = <2>; 335 #power-domain-cells = <0>; 336 #reset-cells = <1>; 337 }; 338 339 rst: reset-controller@e6160000 { 340 compatible = "renesas,r8a774a1-rst"; 341 reg = <0 0xe6160000 0 0x018c>; 342 }; 343 344 sysc: system-controller@e6180000 { 345 compatible = "renesas,r8a774a1-sysc"; 346 reg = <0 0xe6180000 0 0x0400>; 347 #power-domain-cells = <1>; 348 }; 349 350 tsc: thermal@e6198000 { 351 compatible = "renesas,r8a774a1-thermal"; 352 reg = <0 0xe6198000 0 0x100>, 353 <0 0xe61a0000 0 0x100>, 354 <0 0xe61a8000 0 0x100>; 355 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&cpg CPG_MOD 522>; 359 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 360 resets = <&cpg 522>; 361 #thermal-sensor-cells = <1>; 362 }; 363 364 intc_ex: interrupt-controller@e61c0000 { 365 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; 366 #interrupt-cells = <2>; 367 interrupt-controller; 368 reg = <0 0xe61c0000 0 0x200>; 369 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 370 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 371 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 372 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 373 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 374 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&cpg CPG_MOD 407>; 376 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 377 resets = <&cpg 407>; 378 }; 379 380 i2c0: i2c@e6500000 { 381 #address-cells = <1>; 382 #size-cells = <0>; 383 compatible = "renesas,i2c-r8a774a1", 384 "renesas,rcar-gen3-i2c"; 385 reg = <0 0xe6500000 0 0x40>; 386 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&cpg CPG_MOD 931>; 388 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 389 resets = <&cpg 931>; 390 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 391 <&dmac2 0x91>, <&dmac2 0x90>; 392 dma-names = "tx", "rx", "tx", "rx"; 393 i2c-scl-internal-delay-ns = <110>; 394 status = "disabled"; 395 }; 396 397 i2c1: i2c@e6508000 { 398 #address-cells = <1>; 399 #size-cells = <0>; 400 compatible = "renesas,i2c-r8a774a1", 401 "renesas,rcar-gen3-i2c"; 402 reg = <0 0xe6508000 0 0x40>; 403 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&cpg CPG_MOD 930>; 405 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 406 resets = <&cpg 930>; 407 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 408 <&dmac2 0x93>, <&dmac2 0x92>; 409 dma-names = "tx", "rx", "tx", "rx"; 410 i2c-scl-internal-delay-ns = <6>; 411 status = "disabled"; 412 }; 413 414 i2c2: i2c@e6510000 { 415 #address-cells = <1>; 416 #size-cells = <0>; 417 compatible = "renesas,i2c-r8a774a1", 418 "renesas,rcar-gen3-i2c"; 419 reg = <0 0xe6510000 0 0x40>; 420 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&cpg CPG_MOD 929>; 422 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 423 resets = <&cpg 929>; 424 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 425 <&dmac2 0x95>, <&dmac2 0x94>; 426 dma-names = "tx", "rx", "tx", "rx"; 427 i2c-scl-internal-delay-ns = <6>; 428 status = "disabled"; 429 }; 430 431 i2c3: i2c@e66d0000 { 432 #address-cells = <1>; 433 #size-cells = <0>; 434 compatible = "renesas,i2c-r8a774a1", 435 "renesas,rcar-gen3-i2c"; 436 reg = <0 0xe66d0000 0 0x40>; 437 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&cpg CPG_MOD 928>; 439 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 440 resets = <&cpg 928>; 441 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 442 dma-names = "tx", "rx"; 443 i2c-scl-internal-delay-ns = <110>; 444 status = "disabled"; 445 }; 446 447 i2c4: i2c@e66d8000 { 448 #address-cells = <1>; 449 #size-cells = <0>; 450 compatible = "renesas,i2c-r8a774a1", 451 "renesas,rcar-gen3-i2c"; 452 reg = <0 0xe66d8000 0 0x40>; 453 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&cpg CPG_MOD 927>; 455 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 456 resets = <&cpg 927>; 457 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 458 dma-names = "tx", "rx"; 459 i2c-scl-internal-delay-ns = <110>; 460 status = "disabled"; 461 }; 462 463 i2c5: i2c@e66e0000 { 464 #address-cells = <1>; 465 #size-cells = <0>; 466 compatible = "renesas,i2c-r8a774a1", 467 "renesas,rcar-gen3-i2c"; 468 reg = <0 0xe66e0000 0 0x40>; 469 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&cpg CPG_MOD 919>; 471 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 472 resets = <&cpg 919>; 473 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 474 dma-names = "tx", "rx"; 475 i2c-scl-internal-delay-ns = <110>; 476 status = "disabled"; 477 }; 478 479 i2c6: i2c@e66e8000 { 480 #address-cells = <1>; 481 #size-cells = <0>; 482 compatible = "renesas,i2c-r8a774a1", 483 "renesas,rcar-gen3-i2c"; 484 reg = <0 0xe66e8000 0 0x40>; 485 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&cpg CPG_MOD 918>; 487 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 488 resets = <&cpg 918>; 489 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 490 dma-names = "tx", "rx"; 491 i2c-scl-internal-delay-ns = <6>; 492 status = "disabled"; 493 }; 494 495 i2c_dvfs: i2c@e60b0000 { 496 #address-cells = <1>; 497 #size-cells = <0>; 498 compatible = "renesas,iic-r8a774a1", 499 "renesas,rcar-gen3-iic", 500 "renesas,rmobile-iic"; 501 reg = <0 0xe60b0000 0 0x425>; 502 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&cpg CPG_MOD 926>; 504 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 505 resets = <&cpg 926>; 506 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 507 dma-names = "tx", "rx"; 508 status = "disabled"; 509 }; 510 511 hscif0: serial@e6540000 { 512 compatible = "renesas,hscif-r8a774a1", 513 "renesas,rcar-gen3-hscif", 514 "renesas,hscif"; 515 reg = <0 0xe6540000 0 0x60>; 516 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&cpg CPG_MOD 520>, 518 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 519 <&scif_clk>; 520 clock-names = "fck", "brg_int", "scif_clk"; 521 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 522 <&dmac2 0x31>, <&dmac2 0x30>; 523 dma-names = "tx", "rx", "tx", "rx"; 524 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 525 resets = <&cpg 520>; 526 status = "disabled"; 527 }; 528 529 hscif1: serial@e6550000 { 530 compatible = "renesas,hscif-r8a774a1", 531 "renesas,rcar-gen3-hscif", 532 "renesas,hscif"; 533 reg = <0 0xe6550000 0 0x60>; 534 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&cpg CPG_MOD 519>, 536 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 537 <&scif_clk>; 538 clock-names = "fck", "brg_int", "scif_clk"; 539 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 540 <&dmac2 0x33>, <&dmac2 0x32>; 541 dma-names = "tx", "rx", "tx", "rx"; 542 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 543 resets = <&cpg 519>; 544 status = "disabled"; 545 }; 546 547 hscif2: serial@e6560000 { 548 compatible = "renesas,hscif-r8a774a1", 549 "renesas,rcar-gen3-hscif", 550 "renesas,hscif"; 551 reg = <0 0xe6560000 0 0x60>; 552 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&cpg CPG_MOD 518>, 554 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 555 <&scif_clk>; 556 clock-names = "fck", "brg_int", "scif_clk"; 557 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 558 <&dmac2 0x35>, <&dmac2 0x34>; 559 dma-names = "tx", "rx", "tx", "rx"; 560 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 561 resets = <&cpg 518>; 562 status = "disabled"; 563 }; 564 565 hscif3: serial@e66a0000 { 566 compatible = "renesas,hscif-r8a774a1", 567 "renesas,rcar-gen3-hscif", 568 "renesas,hscif"; 569 reg = <0 0xe66a0000 0 0x60>; 570 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&cpg CPG_MOD 517>, 572 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 573 <&scif_clk>; 574 clock-names = "fck", "brg_int", "scif_clk"; 575 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 576 dma-names = "tx", "rx"; 577 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 578 resets = <&cpg 517>; 579 status = "disabled"; 580 }; 581 582 hscif4: serial@e66b0000 { 583 compatible = "renesas,hscif-r8a774a1", 584 "renesas,rcar-gen3-hscif", 585 "renesas,hscif"; 586 reg = <0 0xe66b0000 0 0x60>; 587 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&cpg CPG_MOD 516>, 589 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 590 <&scif_clk>; 591 clock-names = "fck", "brg_int", "scif_clk"; 592 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 593 dma-names = "tx", "rx"; 594 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 595 resets = <&cpg 516>; 596 status = "disabled"; 597 }; 598 599 hsusb: usb@e6590000 { 600 compatible = "renesas,usbhs-r8a774a1", 601 "renesas,rcar-gen3-usbhs"; 602 reg = <0 0xe6590000 0 0x200>; 603 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&cpg CPG_MOD 704>; 605 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 606 <&usb_dmac1 0>, <&usb_dmac1 1>; 607 dma-names = "ch0", "ch1", "ch2", "ch3"; 608 renesas,buswait = <11>; 609 phys = <&usb2_phy0 3>; 610 phy-names = "usb"; 611 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 612 resets = <&cpg 704>; 613 status = "disabled"; 614 }; 615 616 usb_dmac0: dma-controller@e65a0000 { 617 compatible = "renesas,r8a774a1-usb-dmac", 618 "renesas,usb-dmac"; 619 reg = <0 0xe65a0000 0 0x100>; 620 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 621 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 622 interrupt-names = "ch0", "ch1"; 623 clocks = <&cpg CPG_MOD 330>; 624 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 625 resets = <&cpg 330>; 626 #dma-cells = <1>; 627 dma-channels = <2>; 628 }; 629 630 usb_dmac1: dma-controller@e65b0000 { 631 compatible = "renesas,r8a774a1-usb-dmac", 632 "renesas,usb-dmac"; 633 reg = <0 0xe65b0000 0 0x100>; 634 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 635 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 636 interrupt-names = "ch0", "ch1"; 637 clocks = <&cpg CPG_MOD 331>; 638 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 639 resets = <&cpg 331>; 640 #dma-cells = <1>; 641 dma-channels = <2>; 642 }; 643 644 usb3_phy0: usb-phy@e65ee000 { 645 compatible = "renesas,r8a774a1-usb3-phy", 646 "renesas,rcar-gen3-usb3-phy"; 647 reg = <0 0xe65ee000 0 0x90>; 648 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 649 <&usb_extal_clk>; 650 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 651 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 652 resets = <&cpg 328>; 653 #phy-cells = <0>; 654 status = "disabled"; 655 }; 656 657 dmac0: dma-controller@e6700000 { 658 compatible = "renesas,dmac-r8a774a1", 659 "renesas,rcar-dmac"; 660 reg = <0 0xe6700000 0 0x10000>; 661 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 662 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 663 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 664 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 665 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 666 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 667 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 668 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 669 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 670 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 671 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 672 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 673 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 674 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 675 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 676 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 677 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 678 interrupt-names = "error", 679 "ch0", "ch1", "ch2", "ch3", 680 "ch4", "ch5", "ch6", "ch7", 681 "ch8", "ch9", "ch10", "ch11", 682 "ch12", "ch13", "ch14", "ch15"; 683 clocks = <&cpg CPG_MOD 219>; 684 clock-names = "fck"; 685 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 686 resets = <&cpg 219>; 687 #dma-cells = <1>; 688 dma-channels = <16>; 689 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 690 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 691 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 692 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 693 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 694 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 695 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 696 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 697 }; 698 699 dmac1: dma-controller@e7300000 { 700 compatible = "renesas,dmac-r8a774a1", 701 "renesas,rcar-dmac"; 702 reg = <0 0xe7300000 0 0x10000>; 703 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 704 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 705 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 706 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 707 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 708 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 709 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 710 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 711 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 712 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 713 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 714 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 715 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 716 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 717 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 718 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 719 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 720 interrupt-names = "error", 721 "ch0", "ch1", "ch2", "ch3", 722 "ch4", "ch5", "ch6", "ch7", 723 "ch8", "ch9", "ch10", "ch11", 724 "ch12", "ch13", "ch14", "ch15"; 725 clocks = <&cpg CPG_MOD 218>; 726 clock-names = "fck"; 727 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 728 resets = <&cpg 218>; 729 #dma-cells = <1>; 730 dma-channels = <16>; 731 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 732 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 733 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 734 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 735 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 736 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 737 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 738 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 739 }; 740 741 dmac2: dma-controller@e7310000 { 742 compatible = "renesas,dmac-r8a774a1", 743 "renesas,rcar-dmac"; 744 reg = <0 0xe7310000 0 0x10000>; 745 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 746 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 747 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 748 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 749 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 750 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 751 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 752 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 753 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 754 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 755 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 756 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 757 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 758 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 759 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 760 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 761 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 762 interrupt-names = "error", 763 "ch0", "ch1", "ch2", "ch3", 764 "ch4", "ch5", "ch6", "ch7", 765 "ch8", "ch9", "ch10", "ch11", 766 "ch12", "ch13", "ch14", "ch15"; 767 clocks = <&cpg CPG_MOD 217>; 768 clock-names = "fck"; 769 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 770 resets = <&cpg 217>; 771 #dma-cells = <1>; 772 dma-channels = <16>; 773 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 774 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 775 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 776 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 777 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 778 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 779 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 780 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 781 }; 782 783 ipmmu_ds0: mmu@e6740000 { 784 compatible = "renesas,ipmmu-r8a774a1"; 785 reg = <0 0xe6740000 0 0x1000>; 786 renesas,ipmmu-main = <&ipmmu_mm 0>; 787 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 788 #iommu-cells = <1>; 789 }; 790 791 ipmmu_ds1: mmu@e7740000 { 792 compatible = "renesas,ipmmu-r8a774a1"; 793 reg = <0 0xe7740000 0 0x1000>; 794 renesas,ipmmu-main = <&ipmmu_mm 1>; 795 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 796 #iommu-cells = <1>; 797 }; 798 799 ipmmu_hc: mmu@e6570000 { 800 compatible = "renesas,ipmmu-r8a774a1"; 801 reg = <0 0xe6570000 0 0x1000>; 802 renesas,ipmmu-main = <&ipmmu_mm 2>; 803 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 804 #iommu-cells = <1>; 805 }; 806 807 ipmmu_mm: mmu@e67b0000 { 808 compatible = "renesas,ipmmu-r8a774a1"; 809 reg = <0 0xe67b0000 0 0x1000>; 810 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 812 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 813 #iommu-cells = <1>; 814 }; 815 816 ipmmu_mp: mmu@ec670000 { 817 compatible = "renesas,ipmmu-r8a774a1"; 818 reg = <0 0xec670000 0 0x1000>; 819 renesas,ipmmu-main = <&ipmmu_mm 4>; 820 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 821 #iommu-cells = <1>; 822 }; 823 824 ipmmu_pv0: mmu@fd800000 { 825 compatible = "renesas,ipmmu-r8a774a1"; 826 reg = <0 0xfd800000 0 0x1000>; 827 renesas,ipmmu-main = <&ipmmu_mm 5>; 828 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 829 #iommu-cells = <1>; 830 }; 831 832 ipmmu_pv1: mmu@fd950000 { 833 compatible = "renesas,ipmmu-r8a774a1"; 834 reg = <0 0xfd950000 0 0x1000>; 835 renesas,ipmmu-main = <&ipmmu_mm 6>; 836 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 837 #iommu-cells = <1>; 838 }; 839 840 ipmmu_vc0: mmu@fe6b0000 { 841 compatible = "renesas,ipmmu-r8a774a1"; 842 reg = <0 0xfe6b0000 0 0x1000>; 843 renesas,ipmmu-main = <&ipmmu_mm 8>; 844 power-domains = <&sysc R8A774A1_PD_A3VC>; 845 #iommu-cells = <1>; 846 }; 847 848 ipmmu_vi0: mmu@febd0000 { 849 compatible = "renesas,ipmmu-r8a774a1"; 850 reg = <0 0xfebd0000 0 0x1000>; 851 renesas,ipmmu-main = <&ipmmu_mm 9>; 852 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 853 #iommu-cells = <1>; 854 }; 855 856 avb: ethernet@e6800000 { 857 compatible = "renesas,etheravb-r8a774a1", 858 "renesas,etheravb-rcar-gen3"; 859 reg = <0 0xe6800000 0 0x800>; 860 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 885 interrupt-names = "ch0", "ch1", "ch2", "ch3", 886 "ch4", "ch5", "ch6", "ch7", 887 "ch8", "ch9", "ch10", "ch11", 888 "ch12", "ch13", "ch14", "ch15", 889 "ch16", "ch17", "ch18", "ch19", 890 "ch20", "ch21", "ch22", "ch23", 891 "ch24"; 892 clocks = <&cpg CPG_MOD 812>; 893 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 894 resets = <&cpg 812>; 895 phy-mode = "rgmii"; 896 iommus = <&ipmmu_ds0 16>; 897 #address-cells = <1>; 898 #size-cells = <0>; 899 status = "disabled"; 900 }; 901 902 can0: can@e6c30000 { 903 compatible = "renesas,can-r8a774a1", 904 "renesas,rcar-gen3-can"; 905 reg = <0 0xe6c30000 0 0x1000>; 906 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&cpg CPG_MOD 916>, 908 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 909 <&can_clk>; 910 clock-names = "clkp1", "clkp2", "can_clk"; 911 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 912 resets = <&cpg 916>; 913 status = "disabled"; 914 }; 915 916 can1: can@e6c38000 { 917 compatible = "renesas,can-r8a774a1", 918 "renesas,rcar-gen3-can"; 919 reg = <0 0xe6c38000 0 0x1000>; 920 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&cpg CPG_MOD 915>, 922 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 923 <&can_clk>; 924 clock-names = "clkp1", "clkp2", "can_clk"; 925 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 926 resets = <&cpg 915>; 927 status = "disabled"; 928 }; 929 930 pwm0: pwm@e6e30000 { 931 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 932 reg = <0 0xe6e30000 0 0x8>; 933 #pwm-cells = <2>; 934 clocks = <&cpg CPG_MOD 523>; 935 resets = <&cpg 523>; 936 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 937 status = "disabled"; 938 }; 939 940 pwm1: pwm@e6e31000 { 941 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 942 reg = <0 0xe6e31000 0 0x8>; 943 #pwm-cells = <2>; 944 clocks = <&cpg CPG_MOD 523>; 945 resets = <&cpg 523>; 946 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 947 status = "disabled"; 948 }; 949 950 pwm2: pwm@e6e32000 { 951 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 952 reg = <0 0xe6e32000 0 0x8>; 953 #pwm-cells = <2>; 954 clocks = <&cpg CPG_MOD 523>; 955 resets = <&cpg 523>; 956 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 957 status = "disabled"; 958 }; 959 960 pwm3: pwm@e6e33000 { 961 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 962 reg = <0 0xe6e33000 0 0x8>; 963 #pwm-cells = <2>; 964 clocks = <&cpg CPG_MOD 523>; 965 resets = <&cpg 523>; 966 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 967 status = "disabled"; 968 }; 969 970 pwm4: pwm@e6e34000 { 971 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 972 reg = <0 0xe6e34000 0 0x8>; 973 #pwm-cells = <2>; 974 clocks = <&cpg CPG_MOD 523>; 975 resets = <&cpg 523>; 976 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 977 status = "disabled"; 978 }; 979 980 pwm5: pwm@e6e35000 { 981 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 982 reg = <0 0xe6e35000 0 0x8>; 983 #pwm-cells = <2>; 984 clocks = <&cpg CPG_MOD 523>; 985 resets = <&cpg 523>; 986 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 987 status = "disabled"; 988 }; 989 990 pwm6: pwm@e6e36000 { 991 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 992 reg = <0 0xe6e36000 0 0x8>; 993 #pwm-cells = <2>; 994 clocks = <&cpg CPG_MOD 523>; 995 resets = <&cpg 523>; 996 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 997 status = "disabled"; 998 }; 999 1000 scif0: serial@e6e60000 { 1001 compatible = "renesas,scif-r8a774a1", 1002 "renesas,rcar-gen3-scif", "renesas,scif"; 1003 reg = <0 0xe6e60000 0 0x40>; 1004 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&cpg CPG_MOD 207>, 1006 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1007 <&scif_clk>; 1008 clock-names = "fck", "brg_int", "scif_clk"; 1009 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1010 <&dmac2 0x51>, <&dmac2 0x50>; 1011 dma-names = "tx", "rx", "tx", "rx"; 1012 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1013 resets = <&cpg 207>; 1014 status = "disabled"; 1015 }; 1016 1017 scif1: serial@e6e68000 { 1018 compatible = "renesas,scif-r8a774a1", 1019 "renesas,rcar-gen3-scif", "renesas,scif"; 1020 reg = <0 0xe6e68000 0 0x40>; 1021 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&cpg CPG_MOD 206>, 1023 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1024 <&scif_clk>; 1025 clock-names = "fck", "brg_int", "scif_clk"; 1026 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1027 <&dmac2 0x53>, <&dmac2 0x52>; 1028 dma-names = "tx", "rx", "tx", "rx"; 1029 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1030 resets = <&cpg 206>; 1031 status = "disabled"; 1032 }; 1033 1034 scif2: serial@e6e88000 { 1035 compatible = "renesas,scif-r8a774a1", 1036 "renesas,rcar-gen3-scif", "renesas,scif"; 1037 reg = <0 0xe6e88000 0 0x40>; 1038 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&cpg CPG_MOD 310>, 1040 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1041 <&scif_clk>; 1042 clock-names = "fck", "brg_int", "scif_clk"; 1043 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1044 <&dmac2 0x13>, <&dmac2 0x12>; 1045 dma-names = "tx", "rx", "tx", "rx"; 1046 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1047 resets = <&cpg 310>; 1048 status = "disabled"; 1049 }; 1050 1051 scif3: serial@e6c50000 { 1052 compatible = "renesas,scif-r8a774a1", 1053 "renesas,rcar-gen3-scif", "renesas,scif"; 1054 reg = <0 0xe6c50000 0 0x40>; 1055 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1056 clocks = <&cpg CPG_MOD 204>, 1057 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1058 <&scif_clk>; 1059 clock-names = "fck", "brg_int", "scif_clk"; 1060 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1061 dma-names = "tx", "rx"; 1062 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1063 resets = <&cpg 204>; 1064 status = "disabled"; 1065 }; 1066 1067 scif4: serial@e6c40000 { 1068 compatible = "renesas,scif-r8a774a1", 1069 "renesas,rcar-gen3-scif", "renesas,scif"; 1070 reg = <0 0xe6c40000 0 0x40>; 1071 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&cpg CPG_MOD 203>, 1073 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1074 <&scif_clk>; 1075 clock-names = "fck", "brg_int", "scif_clk"; 1076 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1077 dma-names = "tx", "rx"; 1078 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1079 resets = <&cpg 203>; 1080 status = "disabled"; 1081 }; 1082 1083 scif5: serial@e6f30000 { 1084 compatible = "renesas,scif-r8a774a1", 1085 "renesas,rcar-gen3-scif", "renesas,scif"; 1086 reg = <0 0xe6f30000 0 0x40>; 1087 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1088 clocks = <&cpg CPG_MOD 202>, 1089 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1090 <&scif_clk>; 1091 clock-names = "fck", "brg_int", "scif_clk"; 1092 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1093 <&dmac2 0x5b>, <&dmac2 0x5a>; 1094 dma-names = "tx", "rx", "tx", "rx"; 1095 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1096 resets = <&cpg 202>; 1097 status = "disabled"; 1098 }; 1099 1100 msiof0: spi@e6e90000 { 1101 compatible = "renesas,msiof-r8a774a1", 1102 "renesas,rcar-gen3-msiof"; 1103 reg = <0 0xe6e90000 0 0x0064>; 1104 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1105 clocks = <&cpg CPG_MOD 211>; 1106 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1107 <&dmac2 0x41>, <&dmac2 0x40>; 1108 dma-names = "tx", "rx", "tx", "rx"; 1109 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1110 resets = <&cpg 211>; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 status = "disabled"; 1114 }; 1115 1116 msiof1: spi@e6ea0000 { 1117 compatible = "renesas,msiof-r8a774a1", 1118 "renesas,rcar-gen3-msiof"; 1119 reg = <0 0xe6ea0000 0 0x0064>; 1120 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&cpg CPG_MOD 210>; 1122 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1123 <&dmac2 0x43>, <&dmac2 0x42>; 1124 dma-names = "tx", "rx", "tx", "rx"; 1125 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1126 resets = <&cpg 210>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 msiof2: spi@e6c00000 { 1133 compatible = "renesas,msiof-r8a774a1", 1134 "renesas,rcar-gen3-msiof"; 1135 reg = <0 0xe6c00000 0 0x0064>; 1136 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&cpg CPG_MOD 209>; 1138 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1139 dma-names = "tx", "rx"; 1140 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1141 resets = <&cpg 209>; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 status = "disabled"; 1145 }; 1146 1147 msiof3: spi@e6c10000 { 1148 compatible = "renesas,msiof-r8a774a1", 1149 "renesas,rcar-gen3-msiof"; 1150 reg = <0 0xe6c10000 0 0x0064>; 1151 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1152 clocks = <&cpg CPG_MOD 208>; 1153 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1154 dma-names = "tx", "rx"; 1155 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1156 resets = <&cpg 208>; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 status = "disabled"; 1160 }; 1161 1162 vin0: video@e6ef0000 { 1163 compatible = "renesas,vin-r8a774a1"; 1164 reg = <0 0xe6ef0000 0 0x1000>; 1165 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1166 clocks = <&cpg CPG_MOD 811>; 1167 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1168 resets = <&cpg 811>; 1169 renesas,id = <0>; 1170 status = "disabled"; 1171 1172 ports { 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 1176 port@1 { 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 1180 reg = <1>; 1181 1182 vin0csi20: endpoint@0 { 1183 reg = <0>; 1184 remote-endpoint = <&csi20vin0>; 1185 }; 1186 vin0csi40: endpoint@2 { 1187 reg = <2>; 1188 remote-endpoint = <&csi40vin0>; 1189 }; 1190 }; 1191 }; 1192 }; 1193 1194 vin1: video@e6ef1000 { 1195 compatible = "renesas,vin-r8a774a1"; 1196 reg = <0 0xe6ef1000 0 0x1000>; 1197 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&cpg CPG_MOD 810>; 1199 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1200 resets = <&cpg 810>; 1201 renesas,id = <1>; 1202 status = "disabled"; 1203 1204 ports { 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 1208 port@1 { 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 1212 reg = <1>; 1213 1214 vin1csi20: endpoint@0 { 1215 reg = <0>; 1216 remote-endpoint = <&csi20vin1>; 1217 }; 1218 vin1csi40: endpoint@2 { 1219 reg = <2>; 1220 remote-endpoint = <&csi40vin1>; 1221 }; 1222 }; 1223 }; 1224 }; 1225 1226 vin2: video@e6ef2000 { 1227 compatible = "renesas,vin-r8a774a1"; 1228 reg = <0 0xe6ef2000 0 0x1000>; 1229 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1230 clocks = <&cpg CPG_MOD 809>; 1231 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1232 resets = <&cpg 809>; 1233 renesas,id = <2>; 1234 status = "disabled"; 1235 1236 ports { 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 1240 port@1 { 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 1244 reg = <1>; 1245 1246 vin2csi20: endpoint@0 { 1247 reg = <0>; 1248 remote-endpoint = <&csi20vin2>; 1249 }; 1250 vin2csi40: endpoint@2 { 1251 reg = <2>; 1252 remote-endpoint = <&csi40vin2>; 1253 }; 1254 }; 1255 }; 1256 }; 1257 1258 vin3: video@e6ef3000 { 1259 compatible = "renesas,vin-r8a774a1"; 1260 reg = <0 0xe6ef3000 0 0x1000>; 1261 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1262 clocks = <&cpg CPG_MOD 808>; 1263 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1264 resets = <&cpg 808>; 1265 renesas,id = <3>; 1266 status = "disabled"; 1267 1268 ports { 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 1272 port@1 { 1273 #address-cells = <1>; 1274 #size-cells = <0>; 1275 1276 reg = <1>; 1277 1278 vin3csi20: endpoint@0 { 1279 reg = <0>; 1280 remote-endpoint = <&csi20vin3>; 1281 }; 1282 vin3csi40: endpoint@2 { 1283 reg = <2>; 1284 remote-endpoint = <&csi40vin3>; 1285 }; 1286 }; 1287 }; 1288 }; 1289 1290 vin4: video@e6ef4000 { 1291 compatible = "renesas,vin-r8a774a1"; 1292 reg = <0 0xe6ef4000 0 0x1000>; 1293 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1294 clocks = <&cpg CPG_MOD 807>; 1295 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1296 resets = <&cpg 807>; 1297 renesas,id = <4>; 1298 status = "disabled"; 1299 1300 ports { 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 1304 port@1 { 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 1308 reg = <1>; 1309 1310 vin4csi20: endpoint@0 { 1311 reg = <0>; 1312 remote-endpoint = <&csi20vin4>; 1313 }; 1314 vin4csi40: endpoint@2 { 1315 reg = <2>; 1316 remote-endpoint = <&csi40vin4>; 1317 }; 1318 }; 1319 }; 1320 }; 1321 1322 vin5: video@e6ef5000 { 1323 compatible = "renesas,vin-r8a774a1"; 1324 reg = <0 0xe6ef5000 0 0x1000>; 1325 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1326 clocks = <&cpg CPG_MOD 806>; 1327 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1328 resets = <&cpg 806>; 1329 renesas,id = <5>; 1330 status = "disabled"; 1331 1332 ports { 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 1336 port@1 { 1337 #address-cells = <1>; 1338 #size-cells = <0>; 1339 1340 reg = <1>; 1341 1342 vin5csi20: endpoint@0 { 1343 reg = <0>; 1344 remote-endpoint = <&csi20vin5>; 1345 }; 1346 vin5csi40: endpoint@2 { 1347 reg = <2>; 1348 remote-endpoint = <&csi40vin5>; 1349 }; 1350 }; 1351 }; 1352 }; 1353 1354 vin6: video@e6ef6000 { 1355 compatible = "renesas,vin-r8a774a1"; 1356 reg = <0 0xe6ef6000 0 0x1000>; 1357 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1358 clocks = <&cpg CPG_MOD 805>; 1359 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1360 resets = <&cpg 805>; 1361 renesas,id = <6>; 1362 status = "disabled"; 1363 1364 ports { 1365 #address-cells = <1>; 1366 #size-cells = <0>; 1367 1368 port@1 { 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 1372 reg = <1>; 1373 1374 vin6csi20: endpoint@0 { 1375 reg = <0>; 1376 remote-endpoint = <&csi20vin6>; 1377 }; 1378 vin6csi40: endpoint@2 { 1379 reg = <2>; 1380 remote-endpoint = <&csi40vin6>; 1381 }; 1382 }; 1383 }; 1384 }; 1385 1386 vin7: video@e6ef7000 { 1387 compatible = "renesas,vin-r8a774a1"; 1388 reg = <0 0xe6ef7000 0 0x1000>; 1389 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1390 clocks = <&cpg CPG_MOD 804>; 1391 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1392 resets = <&cpg 804>; 1393 renesas,id = <7>; 1394 status = "disabled"; 1395 1396 ports { 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 1400 port@1 { 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 1404 reg = <1>; 1405 1406 vin7csi20: endpoint@0 { 1407 reg = <0>; 1408 remote-endpoint = <&csi20vin7>; 1409 }; 1410 vin7csi40: endpoint@2 { 1411 reg = <2>; 1412 remote-endpoint = <&csi40vin7>; 1413 }; 1414 }; 1415 }; 1416 }; 1417 1418 rcar_sound: sound@ec500000 { 1419 /* 1420 * #sound-dai-cells is required 1421 * 1422 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1423 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1424 */ 1425 /* 1426 * #clock-cells is required for audio_clkout0/1/2/3 1427 * 1428 * clkout : #clock-cells = <0>; <&rcar_sound>; 1429 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1430 */ 1431 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; 1432 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1433 <0 0xec5a0000 0 0x100>, /* ADG */ 1434 <0 0xec540000 0 0x1000>, /* SSIU */ 1435 <0 0xec541000 0 0x280>, /* SSI */ 1436 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1437 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1438 1439 clocks = <&cpg CPG_MOD 1005>, 1440 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1441 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1442 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1443 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1444 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1445 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1446 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1447 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1448 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1449 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1450 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1451 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1452 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1453 <&audio_clk_a>, <&audio_clk_b>, 1454 <&audio_clk_c>, 1455 <&cpg CPG_CORE R8A774A1_CLK_S0D4>; 1456 clock-names = "ssi-all", 1457 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1458 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1459 "ssi.1", "ssi.0", 1460 "src.9", "src.8", "src.7", "src.6", 1461 "src.5", "src.4", "src.3", "src.2", 1462 "src.1", "src.0", 1463 "mix.1", "mix.0", 1464 "ctu.1", "ctu.0", 1465 "dvc.0", "dvc.1", 1466 "clk_a", "clk_b", "clk_c", "clk_i"; 1467 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1468 resets = <&cpg 1005>, 1469 <&cpg 1006>, <&cpg 1007>, 1470 <&cpg 1008>, <&cpg 1009>, 1471 <&cpg 1010>, <&cpg 1011>, 1472 <&cpg 1012>, <&cpg 1013>, 1473 <&cpg 1014>, <&cpg 1015>; 1474 reset-names = "ssi-all", 1475 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1476 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1477 "ssi.1", "ssi.0"; 1478 status = "disabled"; 1479 1480 rcar_sound,dvc { 1481 dvc0: dvc-0 { 1482 dmas = <&audma1 0xbc>; 1483 dma-names = "tx"; 1484 }; 1485 dvc1: dvc-1 { 1486 dmas = <&audma1 0xbe>; 1487 dma-names = "tx"; 1488 }; 1489 }; 1490 1491 rcar_sound,mix { 1492 mix0: mix-0 { }; 1493 mix1: mix-1 { }; 1494 }; 1495 1496 rcar_sound,ctu { 1497 ctu00: ctu-0 { }; 1498 ctu01: ctu-1 { }; 1499 ctu02: ctu-2 { }; 1500 ctu03: ctu-3 { }; 1501 ctu10: ctu-4 { }; 1502 ctu11: ctu-5 { }; 1503 ctu12: ctu-6 { }; 1504 ctu13: ctu-7 { }; 1505 }; 1506 1507 rcar_sound,src { 1508 src0: src-0 { 1509 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1510 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1511 dma-names = "rx", "tx"; 1512 }; 1513 src1: src-1 { 1514 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1515 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1516 dma-names = "rx", "tx"; 1517 }; 1518 src2: src-2 { 1519 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1520 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1521 dma-names = "rx", "tx"; 1522 }; 1523 src3: src-3 { 1524 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1525 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1526 dma-names = "rx", "tx"; 1527 }; 1528 src4: src-4 { 1529 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1530 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1531 dma-names = "rx", "tx"; 1532 }; 1533 src5: src-5 { 1534 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1535 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1536 dma-names = "rx", "tx"; 1537 }; 1538 src6: src-6 { 1539 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1540 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1541 dma-names = "rx", "tx"; 1542 }; 1543 src7: src-7 { 1544 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1545 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1546 dma-names = "rx", "tx"; 1547 }; 1548 src8: src-8 { 1549 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1550 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1551 dma-names = "rx", "tx"; 1552 }; 1553 src9: src-9 { 1554 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1555 dmas = <&audma0 0x97>, <&audma1 0xba>; 1556 dma-names = "rx", "tx"; 1557 }; 1558 }; 1559 1560 rcar_sound,ssi { 1561 ssi0: ssi-0 { 1562 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1563 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; 1564 dma-names = "rx", "tx", "rxu", "txu"; 1565 }; 1566 ssi1: ssi-1 { 1567 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1568 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; 1569 dma-names = "rx", "tx", "rxu", "txu"; 1570 }; 1571 ssi2: ssi-2 { 1572 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1573 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; 1574 dma-names = "rx", "tx", "rxu", "txu"; 1575 }; 1576 ssi3: ssi-3 { 1577 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1578 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; 1579 dma-names = "rx", "tx", "rxu", "txu"; 1580 }; 1581 ssi4: ssi-4 { 1582 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1583 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; 1584 dma-names = "rx", "tx", "rxu", "txu"; 1585 }; 1586 ssi5: ssi-5 { 1587 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1588 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; 1589 dma-names = "rx", "tx", "rxu", "txu"; 1590 }; 1591 ssi6: ssi-6 { 1592 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1593 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; 1594 dma-names = "rx", "tx", "rxu", "txu"; 1595 }; 1596 ssi7: ssi-7 { 1597 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1598 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; 1599 dma-names = "rx", "tx", "rxu", "txu"; 1600 }; 1601 ssi8: ssi-8 { 1602 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1603 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; 1604 dma-names = "rx", "tx", "rxu", "txu"; 1605 }; 1606 ssi9: ssi-9 { 1607 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1608 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; 1609 dma-names = "rx", "tx", "rxu", "txu"; 1610 }; 1611 }; 1612 1613 ports { 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 port@0 { 1617 reg = <0>; 1618 }; 1619 port@1 { 1620 reg = <1>; 1621 }; 1622 }; 1623 }; 1624 1625 audma0: dma-controller@ec700000 { 1626 compatible = "renesas,dmac-r8a774a1", 1627 "renesas,rcar-dmac"; 1628 reg = <0 0xec700000 0 0x10000>; 1629 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 1630 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 1631 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 1632 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 1633 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 1634 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 1635 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 1636 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 1637 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 1638 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 1639 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 1640 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 1641 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 1642 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 1643 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 1644 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 1645 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1646 interrupt-names = "error", 1647 "ch0", "ch1", "ch2", "ch3", 1648 "ch4", "ch5", "ch6", "ch7", 1649 "ch8", "ch9", "ch10", "ch11", 1650 "ch12", "ch13", "ch14", "ch15"; 1651 clocks = <&cpg CPG_MOD 502>; 1652 clock-names = "fck"; 1653 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1654 resets = <&cpg 502>; 1655 #dma-cells = <1>; 1656 dma-channels = <16>; 1657 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1658 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1659 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1660 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1661 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1662 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1663 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1664 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1665 }; 1666 1667 audma1: dma-controller@ec720000 { 1668 compatible = "renesas,dmac-r8a774a1", 1669 "renesas,rcar-dmac"; 1670 reg = <0 0xec720000 0 0x10000>; 1671 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 1672 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 1673 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 1674 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 1675 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 1676 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 1677 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 1678 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 1679 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 1680 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 1681 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 1682 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 1683 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 1684 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 1685 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH 1686 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 1687 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 1688 interrupt-names = "error", 1689 "ch0", "ch1", "ch2", "ch3", 1690 "ch4", "ch5", "ch6", "ch7", 1691 "ch8", "ch9", "ch10", "ch11", 1692 "ch12", "ch13", "ch14", "ch15"; 1693 clocks = <&cpg CPG_MOD 501>; 1694 clock-names = "fck"; 1695 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1696 resets = <&cpg 501>; 1697 #dma-cells = <1>; 1698 dma-channels = <16>; 1699 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 1700 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 1701 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 1702 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 1703 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 1704 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 1705 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 1706 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 1707 }; 1708 1709 xhci0: usb@ee000000 { 1710 compatible = "renesas,xhci-r8a774a1", 1711 "renesas,rcar-gen3-xhci"; 1712 reg = <0 0xee000000 0 0xc00>; 1713 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1714 clocks = <&cpg CPG_MOD 328>; 1715 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1716 resets = <&cpg 328>; 1717 status = "disabled"; 1718 }; 1719 1720 usb3_peri0: usb@ee020000 { 1721 compatible = "renesas,r8a774a1-usb3-peri", 1722 "renesas,rcar-gen3-usb3-peri"; 1723 reg = <0 0xee020000 0 0x400>; 1724 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1725 clocks = <&cpg CPG_MOD 328>; 1726 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1727 resets = <&cpg 328>; 1728 status = "disabled"; 1729 }; 1730 1731 ohci0: usb@ee080000 { 1732 compatible = "generic-ohci"; 1733 reg = <0 0xee080000 0 0x100>; 1734 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1735 clocks = <&cpg CPG_MOD 703>; 1736 phys = <&usb2_phy0 1>; 1737 phy-names = "usb"; 1738 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1739 resets = <&cpg 703>; 1740 status = "disabled"; 1741 }; 1742 1743 ohci1: usb@ee0a0000 { 1744 compatible = "generic-ohci"; 1745 reg = <0 0xee0a0000 0 0x100>; 1746 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1747 clocks = <&cpg CPG_MOD 702>; 1748 phys = <&usb2_phy1 1>; 1749 phy-names = "usb"; 1750 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1751 resets = <&cpg 702>; 1752 status = "disabled"; 1753 }; 1754 1755 ehci0: usb@ee080100 { 1756 compatible = "generic-ehci"; 1757 reg = <0 0xee080100 0 0x100>; 1758 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1759 clocks = <&cpg CPG_MOD 703>; 1760 phys = <&usb2_phy0 2>; 1761 phy-names = "usb"; 1762 companion = <&ohci0>; 1763 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1764 resets = <&cpg 703>; 1765 status = "disabled"; 1766 }; 1767 1768 ehci1: usb@ee0a0100 { 1769 compatible = "generic-ehci"; 1770 reg = <0 0xee0a0100 0 0x100>; 1771 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1772 clocks = <&cpg CPG_MOD 702>; 1773 phys = <&usb2_phy1 2>; 1774 phy-names = "usb"; 1775 companion = <&ohci1>; 1776 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1777 resets = <&cpg 702>; 1778 status = "disabled"; 1779 }; 1780 1781 usb2_phy0: usb-phy@ee080200 { 1782 compatible = "renesas,usb2-phy-r8a774a1", 1783 "renesas,rcar-gen3-usb2-phy"; 1784 reg = <0 0xee080200 0 0x700>; 1785 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1786 clocks = <&cpg CPG_MOD 703>; 1787 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1788 resets = <&cpg 703>; 1789 #phy-cells = <1>; 1790 status = "disabled"; 1791 }; 1792 1793 usb2_phy1: usb-phy@ee0a0200 { 1794 compatible = "renesas,usb2-phy-r8a774a1", 1795 "renesas,rcar-gen3-usb2-phy"; 1796 reg = <0 0xee0a0200 0 0x700>; 1797 clocks = <&cpg CPG_MOD 702>; 1798 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1799 resets = <&cpg 702>; 1800 #phy-cells = <1>; 1801 status = "disabled"; 1802 }; 1803 1804 sdhi0: sd@ee100000 { 1805 compatible = "renesas,sdhi-r8a774a1", 1806 "renesas,rcar-gen3-sdhi"; 1807 reg = <0 0xee100000 0 0x2000>; 1808 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1809 clocks = <&cpg CPG_MOD 314>; 1810 max-frequency = <200000000>; 1811 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1812 resets = <&cpg 314>; 1813 status = "disabled"; 1814 }; 1815 1816 sdhi1: sd@ee120000 { 1817 compatible = "renesas,sdhi-r8a774a1", 1818 "renesas,rcar-gen3-sdhi"; 1819 reg = <0 0xee120000 0 0x2000>; 1820 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1821 clocks = <&cpg CPG_MOD 313>; 1822 max-frequency = <200000000>; 1823 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1824 resets = <&cpg 313>; 1825 status = "disabled"; 1826 }; 1827 1828 sdhi2: sd@ee140000 { 1829 compatible = "renesas,sdhi-r8a774a1", 1830 "renesas,rcar-gen3-sdhi"; 1831 reg = <0 0xee140000 0 0x2000>; 1832 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1833 clocks = <&cpg CPG_MOD 312>; 1834 max-frequency = <200000000>; 1835 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1836 resets = <&cpg 312>; 1837 status = "disabled"; 1838 }; 1839 1840 sdhi3: sd@ee160000 { 1841 compatible = "renesas,sdhi-r8a774a1", 1842 "renesas,rcar-gen3-sdhi"; 1843 reg = <0 0xee160000 0 0x2000>; 1844 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1845 clocks = <&cpg CPG_MOD 311>; 1846 max-frequency = <200000000>; 1847 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1848 resets = <&cpg 311>; 1849 status = "disabled"; 1850 }; 1851 1852 gic: interrupt-controller@f1010000 { 1853 compatible = "arm,gic-400"; 1854 #interrupt-cells = <3>; 1855 #address-cells = <0>; 1856 interrupt-controller; 1857 reg = <0x0 0xf1010000 0 0x1000>, 1858 <0x0 0xf1020000 0 0x20000>, 1859 <0x0 0xf1040000 0 0x20000>, 1860 <0x0 0xf1060000 0 0x20000>; 1861 interrupts = <GIC_PPI 9 1862 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 1863 clocks = <&cpg CPG_MOD 408>; 1864 clock-names = "clk"; 1865 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1866 resets = <&cpg 408>; 1867 }; 1868 1869 fdp1@fe940000 { 1870 compatible = "renesas,fdp1"; 1871 reg = <0 0xfe940000 0 0x2400>; 1872 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 1873 clocks = <&cpg CPG_MOD 119>; 1874 power-domains = <&sysc R8A774A1_PD_A3VC>; 1875 resets = <&cpg 119>; 1876 renesas,fcp = <&fcpf0>; 1877 }; 1878 1879 fcpf0: fcp@fe950000 { 1880 compatible = "renesas,fcpf"; 1881 reg = <0 0xfe950000 0 0x200>; 1882 clocks = <&cpg CPG_MOD 615>; 1883 power-domains = <&sysc R8A774A1_PD_A3VC>; 1884 resets = <&cpg 615>; 1885 }; 1886 1887 fcpvb0: fcp@fe96f000 { 1888 compatible = "renesas,fcpv"; 1889 reg = <0 0xfe96f000 0 0x200>; 1890 clocks = <&cpg CPG_MOD 607>; 1891 power-domains = <&sysc R8A774A1_PD_A3VC>; 1892 resets = <&cpg 607>; 1893 }; 1894 1895 fcpvd0: fcp@fea27000 { 1896 compatible = "renesas,fcpv"; 1897 reg = <0 0xfea27000 0 0x200>; 1898 clocks = <&cpg CPG_MOD 603>; 1899 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1900 resets = <&cpg 603>; 1901 iommus = <&ipmmu_vi0 8>; 1902 }; 1903 1904 fcpvd1: fcp@fea2f000 { 1905 compatible = "renesas,fcpv"; 1906 reg = <0 0xfea2f000 0 0x200>; 1907 clocks = <&cpg CPG_MOD 602>; 1908 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1909 resets = <&cpg 602>; 1910 iommus = <&ipmmu_vi0 9>; 1911 }; 1912 1913 fcpvd2: fcp@fea37000 { 1914 compatible = "renesas,fcpv"; 1915 reg = <0 0xfea37000 0 0x200>; 1916 clocks = <&cpg CPG_MOD 601>; 1917 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1918 resets = <&cpg 601>; 1919 iommus = <&ipmmu_vi0 10>; 1920 }; 1921 1922 fcpvi0: fcp@fe9af000 { 1923 compatible = "renesas,fcpv"; 1924 reg = <0 0xfe9af000 0 0x200>; 1925 clocks = <&cpg CPG_MOD 611>; 1926 power-domains = <&sysc R8A774A1_PD_A3VC>; 1927 resets = <&cpg 611>; 1928 iommus = <&ipmmu_vc0 19>; 1929 }; 1930 1931 vspb: vsp@fe960000 { 1932 compatible = "renesas,vsp2"; 1933 reg = <0 0xfe960000 0 0x8000>; 1934 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1935 clocks = <&cpg CPG_MOD 626>; 1936 power-domains = <&sysc R8A774A1_PD_A3VC>; 1937 resets = <&cpg 626>; 1938 1939 renesas,fcp = <&fcpvb0>; 1940 }; 1941 1942 vspd0: vsp@fea20000 { 1943 compatible = "renesas,vsp2"; 1944 reg = <0 0xfea20000 0 0x5000>; 1945 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1946 clocks = <&cpg CPG_MOD 623>; 1947 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1948 resets = <&cpg 623>; 1949 1950 renesas,fcp = <&fcpvd0>; 1951 }; 1952 1953 vspd1: vsp@fea28000 { 1954 compatible = "renesas,vsp2"; 1955 reg = <0 0xfea28000 0 0x5000>; 1956 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1957 clocks = <&cpg CPG_MOD 622>; 1958 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1959 resets = <&cpg 622>; 1960 1961 renesas,fcp = <&fcpvd1>; 1962 }; 1963 1964 vspd2: vsp@fea30000 { 1965 compatible = "renesas,vsp2"; 1966 reg = <0 0xfea30000 0 0x5000>; 1967 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1968 clocks = <&cpg CPG_MOD 621>; 1969 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1970 resets = <&cpg 621>; 1971 1972 renesas,fcp = <&fcpvd2>; 1973 }; 1974 1975 vspi0: vsp@fe9a0000 { 1976 compatible = "renesas,vsp2"; 1977 reg = <0 0xfe9a0000 0 0x8000>; 1978 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1979 clocks = <&cpg CPG_MOD 631>; 1980 power-domains = <&sysc R8A774A1_PD_A3VC>; 1981 resets = <&cpg 631>; 1982 1983 renesas,fcp = <&fcpvi0>; 1984 }; 1985 1986 csi20: csi2@fea80000 { 1987 compatible = "renesas,r8a774a1-csi2"; 1988 reg = <0 0xfea80000 0 0x10000>; 1989 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1990 clocks = <&cpg CPG_MOD 714>; 1991 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1992 resets = <&cpg 714>; 1993 status = "disabled"; 1994 1995 ports { 1996 #address-cells = <1>; 1997 #size-cells = <0>; 1998 1999 port@1 { 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 2003 reg = <1>; 2004 2005 csi20vin0: endpoint@0 { 2006 reg = <0>; 2007 remote-endpoint = <&vin0csi20>; 2008 }; 2009 csi20vin1: endpoint@1 { 2010 reg = <1>; 2011 remote-endpoint = <&vin1csi20>; 2012 }; 2013 csi20vin2: endpoint@2 { 2014 reg = <2>; 2015 remote-endpoint = <&vin2csi20>; 2016 }; 2017 csi20vin3: endpoint@3 { 2018 reg = <3>; 2019 remote-endpoint = <&vin3csi20>; 2020 }; 2021 csi20vin4: endpoint@4 { 2022 reg = <4>; 2023 remote-endpoint = <&vin4csi20>; 2024 }; 2025 csi20vin5: endpoint@5 { 2026 reg = <5>; 2027 remote-endpoint = <&vin5csi20>; 2028 }; 2029 csi20vin6: endpoint@6 { 2030 reg = <6>; 2031 remote-endpoint = <&vin6csi20>; 2032 }; 2033 csi20vin7: endpoint@7 { 2034 reg = <7>; 2035 remote-endpoint = <&vin7csi20>; 2036 }; 2037 }; 2038 }; 2039 }; 2040 2041 csi40: csi2@feaa0000 { 2042 compatible = "renesas,r8a774a1-csi2"; 2043 reg = <0 0xfeaa0000 0 0x10000>; 2044 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2045 clocks = <&cpg CPG_MOD 716>; 2046 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2047 resets = <&cpg 716>; 2048 status = "disabled"; 2049 2050 ports { 2051 #address-cells = <1>; 2052 #size-cells = <0>; 2053 2054 port@1 { 2055 #address-cells = <1>; 2056 #size-cells = <0>; 2057 2058 reg = <1>; 2059 2060 csi40vin0: endpoint@0 { 2061 reg = <0>; 2062 remote-endpoint = <&vin0csi40>; 2063 }; 2064 csi40vin1: endpoint@1 { 2065 reg = <1>; 2066 remote-endpoint = <&vin1csi40>; 2067 }; 2068 csi40vin2: endpoint@2 { 2069 reg = <2>; 2070 remote-endpoint = <&vin2csi40>; 2071 }; 2072 csi40vin3: endpoint@3 { 2073 reg = <3>; 2074 remote-endpoint = <&vin3csi40>; 2075 }; 2076 csi40vin4: endpoint@4 { 2077 reg = <4>; 2078 remote-endpoint = <&vin4csi40>; 2079 }; 2080 csi40vin5: endpoint@5 { 2081 reg = <5>; 2082 remote-endpoint = <&vin5csi40>; 2083 }; 2084 csi40vin6: endpoint@6 { 2085 reg = <6>; 2086 remote-endpoint = <&vin6csi40>; 2087 }; 2088 csi40vin7: endpoint@7 { 2089 reg = <7>; 2090 remote-endpoint = <&vin7csi40>; 2091 }; 2092 }; 2093 2094 }; 2095 }; 2096 2097 du: display@feb00000 { 2098 compatible = "renesas,du-r8a774a1"; 2099 reg = <0 0xfeb00000 0 0x70000>; 2100 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2103 clocks = <&cpg CPG_MOD 724>, 2104 <&cpg CPG_MOD 723>, 2105 <&cpg CPG_MOD 722>; 2106 clock-names = "du.0", "du.1", "du.2"; 2107 status = "disabled"; 2108 2109 vsps = <&vspd0 &vspd1 &vspd2>; 2110 2111 ports { 2112 #address-cells = <1>; 2113 #size-cells = <0>; 2114 2115 port@0 { 2116 reg = <0>; 2117 du_out_rgb: endpoint { 2118 }; 2119 }; 2120 port@1 { 2121 reg = <1>; 2122 du_out_hdmi0: endpoint { 2123 }; 2124 }; 2125 port@2 { 2126 reg = <2>; 2127 du_out_lvds0: endpoint { 2128 remote-endpoint = <&lvds0_in>; 2129 }; 2130 }; 2131 }; 2132 }; 2133 2134 lvds0: lvds@feb90000 { 2135 compatible = "renesas,r8a774a1-lvds"; 2136 reg = <0 0xfeb90000 0 0x14>; 2137 clocks = <&cpg CPG_MOD 727>; 2138 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2139 resets = <&cpg 727>; 2140 status = "disabled"; 2141 2142 ports { 2143 #address-cells = <1>; 2144 #size-cells = <0>; 2145 2146 port@0 { 2147 reg = <0>; 2148 lvds0_in: endpoint { 2149 remote-endpoint = <&du_out_lvds0>; 2150 }; 2151 }; 2152 port@1 { 2153 reg = <1>; 2154 lvds0_out: endpoint { 2155 }; 2156 }; 2157 }; 2158 }; 2159 2160 prr: chipid@fff00044 { 2161 compatible = "renesas,prr"; 2162 reg = <0 0xfff00044 0 4>; 2163 }; 2164 }; 2165 2166 thermal-zones { 2167 sensor_thermal1: sensor-thermal1 { 2168 polling-delay-passive = <250>; 2169 polling-delay = <1000>; 2170 thermal-sensors = <&tsc 0>; 2171 2172 trips { 2173 sensor1_crit: sensor1-crit { 2174 temperature = <120000>; 2175 hysteresis = <1000>; 2176 type = "critical"; 2177 }; 2178 }; 2179 }; 2180 2181 sensor_thermal2: sensor-thermal2 { 2182 polling-delay-passive = <250>; 2183 polling-delay = <1000>; 2184 thermal-sensors = <&tsc 1>; 2185 2186 trips { 2187 sensor2_crit: sensor2-crit { 2188 temperature = <120000>; 2189 hysteresis = <1000>; 2190 type = "critical"; 2191 }; 2192 }; 2193 2194 }; 2195 2196 sensor_thermal3: sensor-thermal3 { 2197 polling-delay-passive = <250>; 2198 polling-delay = <1000>; 2199 thermal-sensors = <&tsc 2>; 2200 2201 trips { 2202 sensor3_crit: sensor3-crit { 2203 temperature = <120000>; 2204 hysteresis = <1000>; 2205 type = "critical"; 2206 }; 2207 }; 2208 }; 2209 }; 2210 2211 timer { 2212 compatible = "arm,armv8-timer"; 2213 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2214 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2215 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2216 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2217 }; 2218 2219 /* External USB clocks - can be overridden by the board */ 2220 usb3s0_clk: usb3s0 { 2221 compatible = "fixed-clock"; 2222 #clock-cells = <0>; 2223 clock-frequency = <0>; 2224 }; 2225 2226 usb_extal_clk: usb_extal { 2227 compatible = "fixed-clock"; 2228 #clock-cells = <0>; 2229 clock-frequency = <0>; 2230 }; 2231}; 2232