1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774a1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774a1-sysc.h> 12 13/ { 14 compatible = "renesas,r8a774a1"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 i2c5 = &i2c5; 25 i2c6 = &i2c6; 26 i2c7 = &i2c_dvfs; 27 }; 28 29 /* 30 * The external audio clocks are configured as 0 Hz fixed frequency 31 * clocks by default. 32 * Boards that provide audio clocks should override them. 33 */ 34 audio_clk_a: audio_clk_a { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 audio_clk_b: audio_clk_b { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <0>; 44 }; 45 46 audio_clk_c: audio_clk_c { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <0>; 50 }; 51 52 /* External CAN clock - to be overridden by boards that provide it */ 53 can_clk: can { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <0>; 57 }; 58 59 cluster0_opp: opp_table0 { 60 compatible = "operating-points-v2"; 61 opp-shared; 62 63 opp-500000000 { 64 opp-hz = /bits/ 64 <500000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1000000000 { 69 opp-hz = /bits/ 64 <1000000000>; 70 opp-microvolt = <820000>; 71 clock-latency-ns = <300000>; 72 }; 73 opp-1500000000 { 74 opp-hz = /bits/ 64 <1500000000>; 75 opp-microvolt = <820000>; 76 clock-latency-ns = <300000>; 77 }; 78 }; 79 80 cluster1_opp: opp_table1 { 81 compatible = "operating-points-v2"; 82 opp-shared; 83 84 opp-800000000 { 85 opp-hz = /bits/ 64 <800000000>; 86 opp-microvolt = <820000>; 87 clock-latency-ns = <300000>; 88 }; 89 opp-1000000000 { 90 opp-hz = /bits/ 64 <1000000000>; 91 opp-microvolt = <820000>; 92 clock-latency-ns = <300000>; 93 }; 94 opp-1200000000 { 95 opp-hz = /bits/ 64 <1200000000>; 96 opp-microvolt = <820000>; 97 clock-latency-ns = <300000>; 98 }; 99 }; 100 101 cpus { 102 #address-cells = <1>; 103 #size-cells = <0>; 104 105 a57_0: cpu@0 { 106 compatible = "arm,cortex-a57"; 107 reg = <0x0>; 108 device_type = "cpu"; 109 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; 110 next-level-cache = <&L2_CA57>; 111 enable-method = "psci"; 112 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 113 operating-points-v2 = <&cluster0_opp>; 114 }; 115 116 a57_1: cpu@1 { 117 compatible = "arm,cortex-a57"; 118 reg = <0x1>; 119 device_type = "cpu"; 120 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; 121 next-level-cache = <&L2_CA57>; 122 enable-method = "psci"; 123 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 124 operating-points-v2 = <&cluster0_opp>; 125 }; 126 127 a53_0: cpu@100 { 128 compatible = "arm,cortex-a53"; 129 reg = <0x100>; 130 device_type = "cpu"; 131 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; 132 next-level-cache = <&L2_CA53>; 133 enable-method = "psci"; 134 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 135 operating-points-v2 = <&cluster1_opp>; 136 }; 137 138 a53_1: cpu@101 { 139 compatible = "arm,cortex-a53"; 140 reg = <0x101>; 141 device_type = "cpu"; 142 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; 143 next-level-cache = <&L2_CA53>; 144 enable-method = "psci"; 145 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 146 operating-points-v2 = <&cluster1_opp>; 147 }; 148 149 a53_2: cpu@102 { 150 compatible = "arm,cortex-a53"; 151 reg = <0x102>; 152 device_type = "cpu"; 153 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; 154 next-level-cache = <&L2_CA53>; 155 enable-method = "psci"; 156 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 157 operating-points-v2 = <&cluster1_opp>; 158 }; 159 160 a53_3: cpu@103 { 161 compatible = "arm,cortex-a53"; 162 reg = <0x103>; 163 device_type = "cpu"; 164 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; 165 next-level-cache = <&L2_CA53>; 166 enable-method = "psci"; 167 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 168 operating-points-v2 = <&cluster1_opp>; 169 }; 170 171 L2_CA57: cache-controller-0 { 172 compatible = "cache"; 173 power-domains = <&sysc R8A774A1_PD_CA57_SCU>; 174 cache-unified; 175 cache-level = <2>; 176 }; 177 178 L2_CA53: cache-controller-1 { 179 compatible = "cache"; 180 power-domains = <&sysc R8A774A1_PD_CA53_SCU>; 181 cache-unified; 182 cache-level = <2>; 183 }; 184 }; 185 186 extal_clk: extal { 187 compatible = "fixed-clock"; 188 #clock-cells = <0>; 189 /* This value must be overridden by the board */ 190 clock-frequency = <0>; 191 }; 192 193 extalr_clk: extalr { 194 compatible = "fixed-clock"; 195 #clock-cells = <0>; 196 /* This value must be overridden by the board */ 197 clock-frequency = <0>; 198 }; 199 200 /* External PCIe clock - can be overridden by the board */ 201 pcie_bus_clk: pcie_bus { 202 compatible = "fixed-clock"; 203 #clock-cells = <0>; 204 clock-frequency = <0>; 205 }; 206 207 pmu_a53 { 208 compatible = "arm,cortex-a53-pmu"; 209 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 210 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 211 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 212 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 213 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 214 }; 215 216 pmu_a57 { 217 compatible = "arm,cortex-a57-pmu"; 218 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 219 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 220 interrupt-affinity = <&a57_0>, <&a57_1>; 221 }; 222 223 psci { 224 compatible = "arm,psci-1.0", "arm,psci-0.2"; 225 method = "smc"; 226 }; 227 228 /* External SCIF clock - to be overridden by boards that provide it */ 229 scif_clk: scif { 230 compatible = "fixed-clock"; 231 #clock-cells = <0>; 232 clock-frequency = <0>; 233 }; 234 235 soc { 236 compatible = "simple-bus"; 237 interrupt-parent = <&gic>; 238 #address-cells = <2>; 239 #size-cells = <2>; 240 ranges; 241 242 rwdt: watchdog@e6020000 { 243 compatible = "renesas,r8a774a1-wdt", 244 "renesas,rcar-gen3-wdt"; 245 reg = <0 0xe6020000 0 0x0c>; 246 clocks = <&cpg CPG_MOD 402>; 247 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 248 resets = <&cpg 402>; 249 status = "disabled"; 250 }; 251 252 gpio0: gpio@e6050000 { 253 compatible = "renesas,gpio-r8a774a1", 254 "renesas,rcar-gen3-gpio"; 255 reg = <0 0xe6050000 0 0x50>; 256 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 257 #gpio-cells = <2>; 258 gpio-controller; 259 gpio-ranges = <&pfc 0 0 16>; 260 #interrupt-cells = <2>; 261 interrupt-controller; 262 clocks = <&cpg CPG_MOD 912>; 263 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 264 resets = <&cpg 912>; 265 }; 266 267 gpio1: gpio@e6051000 { 268 compatible = "renesas,gpio-r8a774a1", 269 "renesas,rcar-gen3-gpio"; 270 reg = <0 0xe6051000 0 0x50>; 271 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 272 #gpio-cells = <2>; 273 gpio-controller; 274 gpio-ranges = <&pfc 0 32 29>; 275 #interrupt-cells = <2>; 276 interrupt-controller; 277 clocks = <&cpg CPG_MOD 911>; 278 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 279 resets = <&cpg 911>; 280 }; 281 282 gpio2: gpio@e6052000 { 283 compatible = "renesas,gpio-r8a774a1", 284 "renesas,rcar-gen3-gpio"; 285 reg = <0 0xe6052000 0 0x50>; 286 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 287 #gpio-cells = <2>; 288 gpio-controller; 289 gpio-ranges = <&pfc 0 64 15>; 290 #interrupt-cells = <2>; 291 interrupt-controller; 292 clocks = <&cpg CPG_MOD 910>; 293 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 294 resets = <&cpg 910>; 295 }; 296 297 gpio3: gpio@e6053000 { 298 compatible = "renesas,gpio-r8a774a1", 299 "renesas,rcar-gen3-gpio"; 300 reg = <0 0xe6053000 0 0x50>; 301 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 302 #gpio-cells = <2>; 303 gpio-controller; 304 gpio-ranges = <&pfc 0 96 16>; 305 #interrupt-cells = <2>; 306 interrupt-controller; 307 clocks = <&cpg CPG_MOD 909>; 308 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 309 resets = <&cpg 909>; 310 }; 311 312 gpio4: gpio@e6054000 { 313 compatible = "renesas,gpio-r8a774a1", 314 "renesas,rcar-gen3-gpio"; 315 reg = <0 0xe6054000 0 0x50>; 316 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 317 #gpio-cells = <2>; 318 gpio-controller; 319 gpio-ranges = <&pfc 0 128 18>; 320 #interrupt-cells = <2>; 321 interrupt-controller; 322 clocks = <&cpg CPG_MOD 908>; 323 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 324 resets = <&cpg 908>; 325 }; 326 327 gpio5: gpio@e6055000 { 328 compatible = "renesas,gpio-r8a774a1", 329 "renesas,rcar-gen3-gpio"; 330 reg = <0 0xe6055000 0 0x50>; 331 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 332 #gpio-cells = <2>; 333 gpio-controller; 334 gpio-ranges = <&pfc 0 160 26>; 335 #interrupt-cells = <2>; 336 interrupt-controller; 337 clocks = <&cpg CPG_MOD 907>; 338 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 339 resets = <&cpg 907>; 340 }; 341 342 gpio6: gpio@e6055400 { 343 compatible = "renesas,gpio-r8a774a1", 344 "renesas,rcar-gen3-gpio"; 345 reg = <0 0xe6055400 0 0x50>; 346 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 347 #gpio-cells = <2>; 348 gpio-controller; 349 gpio-ranges = <&pfc 0 192 32>; 350 #interrupt-cells = <2>; 351 interrupt-controller; 352 clocks = <&cpg CPG_MOD 906>; 353 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 354 resets = <&cpg 906>; 355 }; 356 357 gpio7: gpio@e6055800 { 358 compatible = "renesas,gpio-r8a774a1", 359 "renesas,rcar-gen3-gpio"; 360 reg = <0 0xe6055800 0 0x50>; 361 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 362 #gpio-cells = <2>; 363 gpio-controller; 364 gpio-ranges = <&pfc 0 224 4>; 365 #interrupt-cells = <2>; 366 interrupt-controller; 367 clocks = <&cpg CPG_MOD 905>; 368 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 369 resets = <&cpg 905>; 370 }; 371 372 pfc: pin-controller@e6060000 { 373 compatible = "renesas,pfc-r8a774a1"; 374 reg = <0 0xe6060000 0 0x50c>; 375 }; 376 377 cmt0: timer@e60f0000 { 378 compatible = "renesas,r8a774a1-cmt0", 379 "renesas,rcar-gen3-cmt0"; 380 reg = <0 0xe60f0000 0 0x1004>; 381 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&cpg CPG_MOD 303>; 384 clock-names = "fck"; 385 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 386 resets = <&cpg 303>; 387 status = "disabled"; 388 }; 389 390 cmt1: timer@e6130000 { 391 compatible = "renesas,r8a774a1-cmt1", 392 "renesas,rcar-gen3-cmt1"; 393 reg = <0 0xe6130000 0 0x1004>; 394 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&cpg CPG_MOD 302>; 403 clock-names = "fck"; 404 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 405 resets = <&cpg 302>; 406 status = "disabled"; 407 }; 408 409 cmt2: timer@e6140000 { 410 compatible = "renesas,r8a774a1-cmt1", 411 "renesas,rcar-gen3-cmt1"; 412 reg = <0 0xe6140000 0 0x1004>; 413 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&cpg CPG_MOD 301>; 422 clock-names = "fck"; 423 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 424 resets = <&cpg 301>; 425 status = "disabled"; 426 }; 427 428 cmt3: timer@e6148000 { 429 compatible = "renesas,r8a774a1-cmt1", 430 "renesas,rcar-gen3-cmt1"; 431 reg = <0 0xe6148000 0 0x1004>; 432 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&cpg CPG_MOD 300>; 441 clock-names = "fck"; 442 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 443 resets = <&cpg 300>; 444 status = "disabled"; 445 }; 446 447 cpg: clock-controller@e6150000 { 448 compatible = "renesas,r8a774a1-cpg-mssr"; 449 reg = <0 0xe6150000 0 0x0bb0>; 450 clocks = <&extal_clk>, <&extalr_clk>; 451 clock-names = "extal", "extalr"; 452 #clock-cells = <2>; 453 #power-domain-cells = <0>; 454 #reset-cells = <1>; 455 }; 456 457 rst: reset-controller@e6160000 { 458 compatible = "renesas,r8a774a1-rst"; 459 reg = <0 0xe6160000 0 0x018c>; 460 }; 461 462 sysc: system-controller@e6180000 { 463 compatible = "renesas,r8a774a1-sysc"; 464 reg = <0 0xe6180000 0 0x0400>; 465 #power-domain-cells = <1>; 466 }; 467 468 tsc: thermal@e6198000 { 469 compatible = "renesas,r8a774a1-thermal"; 470 reg = <0 0xe6198000 0 0x100>, 471 <0 0xe61a0000 0 0x100>, 472 <0 0xe61a8000 0 0x100>; 473 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&cpg CPG_MOD 522>; 477 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 478 resets = <&cpg 522>; 479 #thermal-sensor-cells = <1>; 480 }; 481 482 intc_ex: interrupt-controller@e61c0000 { 483 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; 484 #interrupt-cells = <2>; 485 interrupt-controller; 486 reg = <0 0xe61c0000 0 0x200>; 487 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 488 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 489 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 490 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 491 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 492 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&cpg CPG_MOD 407>; 494 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 495 resets = <&cpg 407>; 496 }; 497 498 tmu0: timer@e61e0000 { 499 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 500 reg = <0 0xe61e0000 0 0x30>; 501 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&cpg CPG_MOD 125>; 505 clock-names = "fck"; 506 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 507 resets = <&cpg 125>; 508 status = "disabled"; 509 }; 510 511 tmu1: timer@e6fc0000 { 512 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 513 reg = <0 0xe6fc0000 0 0x30>; 514 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&cpg CPG_MOD 124>; 518 clock-names = "fck"; 519 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 520 resets = <&cpg 124>; 521 status = "disabled"; 522 }; 523 524 tmu2: timer@e6fd0000 { 525 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 526 reg = <0 0xe6fd0000 0 0x30>; 527 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&cpg CPG_MOD 123>; 531 clock-names = "fck"; 532 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 533 resets = <&cpg 123>; 534 status = "disabled"; 535 }; 536 537 tmu3: timer@e6fe0000 { 538 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 539 reg = <0 0xe6fe0000 0 0x30>; 540 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&cpg CPG_MOD 122>; 544 clock-names = "fck"; 545 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 546 resets = <&cpg 122>; 547 status = "disabled"; 548 }; 549 550 tmu4: timer@ffc00000 { 551 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 552 reg = <0 0xffc00000 0 0x30>; 553 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&cpg CPG_MOD 121>; 557 clock-names = "fck"; 558 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 559 resets = <&cpg 121>; 560 status = "disabled"; 561 }; 562 563 i2c0: i2c@e6500000 { 564 #address-cells = <1>; 565 #size-cells = <0>; 566 compatible = "renesas,i2c-r8a774a1", 567 "renesas,rcar-gen3-i2c"; 568 reg = <0 0xe6500000 0 0x40>; 569 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&cpg CPG_MOD 931>; 571 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 572 resets = <&cpg 931>; 573 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 574 <&dmac2 0x91>, <&dmac2 0x90>; 575 dma-names = "tx", "rx", "tx", "rx"; 576 i2c-scl-internal-delay-ns = <110>; 577 status = "disabled"; 578 }; 579 580 i2c1: i2c@e6508000 { 581 #address-cells = <1>; 582 #size-cells = <0>; 583 compatible = "renesas,i2c-r8a774a1", 584 "renesas,rcar-gen3-i2c"; 585 reg = <0 0xe6508000 0 0x40>; 586 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&cpg CPG_MOD 930>; 588 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 589 resets = <&cpg 930>; 590 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 591 <&dmac2 0x93>, <&dmac2 0x92>; 592 dma-names = "tx", "rx", "tx", "rx"; 593 i2c-scl-internal-delay-ns = <6>; 594 status = "disabled"; 595 }; 596 597 i2c2: i2c@e6510000 { 598 #address-cells = <1>; 599 #size-cells = <0>; 600 compatible = "renesas,i2c-r8a774a1", 601 "renesas,rcar-gen3-i2c"; 602 reg = <0 0xe6510000 0 0x40>; 603 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&cpg CPG_MOD 929>; 605 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 606 resets = <&cpg 929>; 607 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 608 <&dmac2 0x95>, <&dmac2 0x94>; 609 dma-names = "tx", "rx", "tx", "rx"; 610 i2c-scl-internal-delay-ns = <6>; 611 status = "disabled"; 612 }; 613 614 i2c3: i2c@e66d0000 { 615 #address-cells = <1>; 616 #size-cells = <0>; 617 compatible = "renesas,i2c-r8a774a1", 618 "renesas,rcar-gen3-i2c"; 619 reg = <0 0xe66d0000 0 0x40>; 620 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&cpg CPG_MOD 928>; 622 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 623 resets = <&cpg 928>; 624 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 625 dma-names = "tx", "rx"; 626 i2c-scl-internal-delay-ns = <110>; 627 status = "disabled"; 628 }; 629 630 i2c4: i2c@e66d8000 { 631 #address-cells = <1>; 632 #size-cells = <0>; 633 compatible = "renesas,i2c-r8a774a1", 634 "renesas,rcar-gen3-i2c"; 635 reg = <0 0xe66d8000 0 0x40>; 636 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&cpg CPG_MOD 927>; 638 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 639 resets = <&cpg 927>; 640 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 641 dma-names = "tx", "rx"; 642 i2c-scl-internal-delay-ns = <110>; 643 status = "disabled"; 644 }; 645 646 i2c5: i2c@e66e0000 { 647 #address-cells = <1>; 648 #size-cells = <0>; 649 compatible = "renesas,i2c-r8a774a1", 650 "renesas,rcar-gen3-i2c"; 651 reg = <0 0xe66e0000 0 0x40>; 652 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&cpg CPG_MOD 919>; 654 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 655 resets = <&cpg 919>; 656 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 657 dma-names = "tx", "rx"; 658 i2c-scl-internal-delay-ns = <110>; 659 status = "disabled"; 660 }; 661 662 i2c6: i2c@e66e8000 { 663 #address-cells = <1>; 664 #size-cells = <0>; 665 compatible = "renesas,i2c-r8a774a1", 666 "renesas,rcar-gen3-i2c"; 667 reg = <0 0xe66e8000 0 0x40>; 668 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&cpg CPG_MOD 918>; 670 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 671 resets = <&cpg 918>; 672 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 673 dma-names = "tx", "rx"; 674 i2c-scl-internal-delay-ns = <6>; 675 status = "disabled"; 676 }; 677 678 i2c_dvfs: i2c@e60b0000 { 679 #address-cells = <1>; 680 #size-cells = <0>; 681 compatible = "renesas,iic-r8a774a1", 682 "renesas,rcar-gen3-iic", 683 "renesas,rmobile-iic"; 684 reg = <0 0xe60b0000 0 0x425>; 685 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&cpg CPG_MOD 926>; 687 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 688 resets = <&cpg 926>; 689 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 690 dma-names = "tx", "rx"; 691 status = "disabled"; 692 }; 693 694 hscif0: serial@e6540000 { 695 compatible = "renesas,hscif-r8a774a1", 696 "renesas,rcar-gen3-hscif", 697 "renesas,hscif"; 698 reg = <0 0xe6540000 0 0x60>; 699 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&cpg CPG_MOD 520>, 701 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 702 <&scif_clk>; 703 clock-names = "fck", "brg_int", "scif_clk"; 704 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 705 <&dmac2 0x31>, <&dmac2 0x30>; 706 dma-names = "tx", "rx", "tx", "rx"; 707 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 708 resets = <&cpg 520>; 709 status = "disabled"; 710 }; 711 712 hscif1: serial@e6550000 { 713 compatible = "renesas,hscif-r8a774a1", 714 "renesas,rcar-gen3-hscif", 715 "renesas,hscif"; 716 reg = <0 0xe6550000 0 0x60>; 717 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&cpg CPG_MOD 519>, 719 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 720 <&scif_clk>; 721 clock-names = "fck", "brg_int", "scif_clk"; 722 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 723 <&dmac2 0x33>, <&dmac2 0x32>; 724 dma-names = "tx", "rx", "tx", "rx"; 725 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 726 resets = <&cpg 519>; 727 status = "disabled"; 728 }; 729 730 hscif2: serial@e6560000 { 731 compatible = "renesas,hscif-r8a774a1", 732 "renesas,rcar-gen3-hscif", 733 "renesas,hscif"; 734 reg = <0 0xe6560000 0 0x60>; 735 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&cpg CPG_MOD 518>, 737 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 738 <&scif_clk>; 739 clock-names = "fck", "brg_int", "scif_clk"; 740 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 741 <&dmac2 0x35>, <&dmac2 0x34>; 742 dma-names = "tx", "rx", "tx", "rx"; 743 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 744 resets = <&cpg 518>; 745 status = "disabled"; 746 }; 747 748 hscif3: serial@e66a0000 { 749 compatible = "renesas,hscif-r8a774a1", 750 "renesas,rcar-gen3-hscif", 751 "renesas,hscif"; 752 reg = <0 0xe66a0000 0 0x60>; 753 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&cpg CPG_MOD 517>, 755 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 756 <&scif_clk>; 757 clock-names = "fck", "brg_int", "scif_clk"; 758 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 759 dma-names = "tx", "rx"; 760 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 761 resets = <&cpg 517>; 762 status = "disabled"; 763 }; 764 765 hscif4: serial@e66b0000 { 766 compatible = "renesas,hscif-r8a774a1", 767 "renesas,rcar-gen3-hscif", 768 "renesas,hscif"; 769 reg = <0 0xe66b0000 0 0x60>; 770 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&cpg CPG_MOD 516>, 772 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 773 <&scif_clk>; 774 clock-names = "fck", "brg_int", "scif_clk"; 775 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 776 dma-names = "tx", "rx"; 777 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 778 resets = <&cpg 516>; 779 status = "disabled"; 780 }; 781 782 hsusb: usb@e6590000 { 783 compatible = "renesas,usbhs-r8a774a1", 784 "renesas,rcar-gen3-usbhs"; 785 reg = <0 0xe6590000 0 0x200>; 786 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&cpg CPG_MOD 704>; 788 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 789 <&usb_dmac1 0>, <&usb_dmac1 1>; 790 dma-names = "ch0", "ch1", "ch2", "ch3"; 791 renesas,buswait = <11>; 792 phys = <&usb2_phy0 3>; 793 phy-names = "usb"; 794 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 795 resets = <&cpg 704>; 796 status = "disabled"; 797 }; 798 799 usb_dmac0: dma-controller@e65a0000 { 800 compatible = "renesas,r8a774a1-usb-dmac", 801 "renesas,usb-dmac"; 802 reg = <0 0xe65a0000 0 0x100>; 803 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 804 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 805 interrupt-names = "ch0", "ch1"; 806 clocks = <&cpg CPG_MOD 330>; 807 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 808 resets = <&cpg 330>; 809 #dma-cells = <1>; 810 dma-channels = <2>; 811 }; 812 813 usb_dmac1: dma-controller@e65b0000 { 814 compatible = "renesas,r8a774a1-usb-dmac", 815 "renesas,usb-dmac"; 816 reg = <0 0xe65b0000 0 0x100>; 817 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 818 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 819 interrupt-names = "ch0", "ch1"; 820 clocks = <&cpg CPG_MOD 331>; 821 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 822 resets = <&cpg 331>; 823 #dma-cells = <1>; 824 dma-channels = <2>; 825 }; 826 827 usb3_phy0: usb-phy@e65ee000 { 828 compatible = "renesas,r8a774a1-usb3-phy", 829 "renesas,rcar-gen3-usb3-phy"; 830 reg = <0 0xe65ee000 0 0x90>; 831 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 832 <&usb_extal_clk>; 833 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 834 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 835 resets = <&cpg 328>; 836 #phy-cells = <0>; 837 status = "disabled"; 838 }; 839 840 dmac0: dma-controller@e6700000 { 841 compatible = "renesas,dmac-r8a774a1", 842 "renesas,rcar-dmac"; 843 reg = <0 0xe6700000 0 0x10000>; 844 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 845 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 846 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 847 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 848 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 849 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 850 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 851 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 852 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 853 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 854 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 855 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 856 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 857 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 858 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 859 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 860 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 861 interrupt-names = "error", 862 "ch0", "ch1", "ch2", "ch3", 863 "ch4", "ch5", "ch6", "ch7", 864 "ch8", "ch9", "ch10", "ch11", 865 "ch12", "ch13", "ch14", "ch15"; 866 clocks = <&cpg CPG_MOD 219>; 867 clock-names = "fck"; 868 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 869 resets = <&cpg 219>; 870 #dma-cells = <1>; 871 dma-channels = <16>; 872 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 873 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 874 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 875 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 876 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 877 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 878 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 879 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 880 }; 881 882 dmac1: dma-controller@e7300000 { 883 compatible = "renesas,dmac-r8a774a1", 884 "renesas,rcar-dmac"; 885 reg = <0 0xe7300000 0 0x10000>; 886 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 887 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 888 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 889 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 890 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 891 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 892 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 893 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 894 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 895 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 896 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 897 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 898 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 899 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 900 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 901 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 902 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 903 interrupt-names = "error", 904 "ch0", "ch1", "ch2", "ch3", 905 "ch4", "ch5", "ch6", "ch7", 906 "ch8", "ch9", "ch10", "ch11", 907 "ch12", "ch13", "ch14", "ch15"; 908 clocks = <&cpg CPG_MOD 218>; 909 clock-names = "fck"; 910 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 911 resets = <&cpg 218>; 912 #dma-cells = <1>; 913 dma-channels = <16>; 914 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 915 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 916 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 917 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 918 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 919 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 920 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 921 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 922 }; 923 924 dmac2: dma-controller@e7310000 { 925 compatible = "renesas,dmac-r8a774a1", 926 "renesas,rcar-dmac"; 927 reg = <0 0xe7310000 0 0x10000>; 928 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 929 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 930 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 931 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 932 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 933 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 934 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 935 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 936 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 937 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 938 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 939 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 940 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 941 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 942 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 943 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 944 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 945 interrupt-names = "error", 946 "ch0", "ch1", "ch2", "ch3", 947 "ch4", "ch5", "ch6", "ch7", 948 "ch8", "ch9", "ch10", "ch11", 949 "ch12", "ch13", "ch14", "ch15"; 950 clocks = <&cpg CPG_MOD 217>; 951 clock-names = "fck"; 952 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 953 resets = <&cpg 217>; 954 #dma-cells = <1>; 955 dma-channels = <16>; 956 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 957 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 958 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 959 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 960 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 961 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 962 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 963 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 964 }; 965 966 ipmmu_ds0: mmu@e6740000 { 967 compatible = "renesas,ipmmu-r8a774a1"; 968 reg = <0 0xe6740000 0 0x1000>; 969 renesas,ipmmu-main = <&ipmmu_mm 0>; 970 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 971 #iommu-cells = <1>; 972 }; 973 974 ipmmu_ds1: mmu@e7740000 { 975 compatible = "renesas,ipmmu-r8a774a1"; 976 reg = <0 0xe7740000 0 0x1000>; 977 renesas,ipmmu-main = <&ipmmu_mm 1>; 978 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 979 #iommu-cells = <1>; 980 }; 981 982 ipmmu_hc: mmu@e6570000 { 983 compatible = "renesas,ipmmu-r8a774a1"; 984 reg = <0 0xe6570000 0 0x1000>; 985 renesas,ipmmu-main = <&ipmmu_mm 2>; 986 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 987 #iommu-cells = <1>; 988 }; 989 990 ipmmu_mm: mmu@e67b0000 { 991 compatible = "renesas,ipmmu-r8a774a1"; 992 reg = <0 0xe67b0000 0 0x1000>; 993 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 995 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 996 #iommu-cells = <1>; 997 }; 998 999 ipmmu_mp: mmu@ec670000 { 1000 compatible = "renesas,ipmmu-r8a774a1"; 1001 reg = <0 0xec670000 0 0x1000>; 1002 renesas,ipmmu-main = <&ipmmu_mm 4>; 1003 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1004 #iommu-cells = <1>; 1005 }; 1006 1007 ipmmu_pv0: mmu@fd800000 { 1008 compatible = "renesas,ipmmu-r8a774a1"; 1009 reg = <0 0xfd800000 0 0x1000>; 1010 renesas,ipmmu-main = <&ipmmu_mm 5>; 1011 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1012 #iommu-cells = <1>; 1013 }; 1014 1015 ipmmu_pv1: mmu@fd950000 { 1016 compatible = "renesas,ipmmu-r8a774a1"; 1017 reg = <0 0xfd950000 0 0x1000>; 1018 renesas,ipmmu-main = <&ipmmu_mm 6>; 1019 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1020 #iommu-cells = <1>; 1021 }; 1022 1023 ipmmu_vc0: mmu@fe6b0000 { 1024 compatible = "renesas,ipmmu-r8a774a1"; 1025 reg = <0 0xfe6b0000 0 0x1000>; 1026 renesas,ipmmu-main = <&ipmmu_mm 8>; 1027 power-domains = <&sysc R8A774A1_PD_A3VC>; 1028 #iommu-cells = <1>; 1029 }; 1030 1031 ipmmu_vi0: mmu@febd0000 { 1032 compatible = "renesas,ipmmu-r8a774a1"; 1033 reg = <0 0xfebd0000 0 0x1000>; 1034 renesas,ipmmu-main = <&ipmmu_mm 9>; 1035 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1036 #iommu-cells = <1>; 1037 }; 1038 1039 avb: ethernet@e6800000 { 1040 compatible = "renesas,etheravb-r8a774a1", 1041 "renesas,etheravb-rcar-gen3"; 1042 reg = <0 0xe6800000 0 0x800>; 1043 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1045 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1068 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1069 "ch4", "ch5", "ch6", "ch7", 1070 "ch8", "ch9", "ch10", "ch11", 1071 "ch12", "ch13", "ch14", "ch15", 1072 "ch16", "ch17", "ch18", "ch19", 1073 "ch20", "ch21", "ch22", "ch23", 1074 "ch24"; 1075 clocks = <&cpg CPG_MOD 812>; 1076 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1077 resets = <&cpg 812>; 1078 phy-mode = "rgmii"; 1079 iommus = <&ipmmu_ds0 16>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 status = "disabled"; 1083 }; 1084 1085 can0: can@e6c30000 { 1086 compatible = "renesas,can-r8a774a1", 1087 "renesas,rcar-gen3-can"; 1088 reg = <0 0xe6c30000 0 0x1000>; 1089 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&cpg CPG_MOD 916>, 1091 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1092 <&can_clk>; 1093 clock-names = "clkp1", "clkp2", "can_clk"; 1094 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1095 resets = <&cpg 916>; 1096 status = "disabled"; 1097 }; 1098 1099 can1: can@e6c38000 { 1100 compatible = "renesas,can-r8a774a1", 1101 "renesas,rcar-gen3-can"; 1102 reg = <0 0xe6c38000 0 0x1000>; 1103 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&cpg CPG_MOD 915>, 1105 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1106 <&can_clk>; 1107 clock-names = "clkp1", "clkp2", "can_clk"; 1108 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1109 resets = <&cpg 915>; 1110 status = "disabled"; 1111 }; 1112 1113 pwm0: pwm@e6e30000 { 1114 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1115 reg = <0 0xe6e30000 0 0x8>; 1116 #pwm-cells = <2>; 1117 clocks = <&cpg CPG_MOD 523>; 1118 resets = <&cpg 523>; 1119 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1120 status = "disabled"; 1121 }; 1122 1123 pwm1: pwm@e6e31000 { 1124 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1125 reg = <0 0xe6e31000 0 0x8>; 1126 #pwm-cells = <2>; 1127 clocks = <&cpg CPG_MOD 523>; 1128 resets = <&cpg 523>; 1129 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1130 status = "disabled"; 1131 }; 1132 1133 pwm2: pwm@e6e32000 { 1134 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1135 reg = <0 0xe6e32000 0 0x8>; 1136 #pwm-cells = <2>; 1137 clocks = <&cpg CPG_MOD 523>; 1138 resets = <&cpg 523>; 1139 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1140 status = "disabled"; 1141 }; 1142 1143 pwm3: pwm@e6e33000 { 1144 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1145 reg = <0 0xe6e33000 0 0x8>; 1146 #pwm-cells = <2>; 1147 clocks = <&cpg CPG_MOD 523>; 1148 resets = <&cpg 523>; 1149 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1150 status = "disabled"; 1151 }; 1152 1153 pwm4: pwm@e6e34000 { 1154 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1155 reg = <0 0xe6e34000 0 0x8>; 1156 #pwm-cells = <2>; 1157 clocks = <&cpg CPG_MOD 523>; 1158 resets = <&cpg 523>; 1159 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1160 status = "disabled"; 1161 }; 1162 1163 pwm5: pwm@e6e35000 { 1164 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1165 reg = <0 0xe6e35000 0 0x8>; 1166 #pwm-cells = <2>; 1167 clocks = <&cpg CPG_MOD 523>; 1168 resets = <&cpg 523>; 1169 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1170 status = "disabled"; 1171 }; 1172 1173 pwm6: pwm@e6e36000 { 1174 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1175 reg = <0 0xe6e36000 0 0x8>; 1176 #pwm-cells = <2>; 1177 clocks = <&cpg CPG_MOD 523>; 1178 resets = <&cpg 523>; 1179 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1180 status = "disabled"; 1181 }; 1182 1183 scif0: serial@e6e60000 { 1184 compatible = "renesas,scif-r8a774a1", 1185 "renesas,rcar-gen3-scif", "renesas,scif"; 1186 reg = <0 0xe6e60000 0 0x40>; 1187 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&cpg CPG_MOD 207>, 1189 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1190 <&scif_clk>; 1191 clock-names = "fck", "brg_int", "scif_clk"; 1192 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1193 <&dmac2 0x51>, <&dmac2 0x50>; 1194 dma-names = "tx", "rx", "tx", "rx"; 1195 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1196 resets = <&cpg 207>; 1197 status = "disabled"; 1198 }; 1199 1200 scif1: serial@e6e68000 { 1201 compatible = "renesas,scif-r8a774a1", 1202 "renesas,rcar-gen3-scif", "renesas,scif"; 1203 reg = <0 0xe6e68000 0 0x40>; 1204 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1205 clocks = <&cpg CPG_MOD 206>, 1206 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1207 <&scif_clk>; 1208 clock-names = "fck", "brg_int", "scif_clk"; 1209 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1210 <&dmac2 0x53>, <&dmac2 0x52>; 1211 dma-names = "tx", "rx", "tx", "rx"; 1212 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1213 resets = <&cpg 206>; 1214 status = "disabled"; 1215 }; 1216 1217 scif2: serial@e6e88000 { 1218 compatible = "renesas,scif-r8a774a1", 1219 "renesas,rcar-gen3-scif", "renesas,scif"; 1220 reg = <0 0xe6e88000 0 0x40>; 1221 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&cpg CPG_MOD 310>, 1223 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1224 <&scif_clk>; 1225 clock-names = "fck", "brg_int", "scif_clk"; 1226 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1227 <&dmac2 0x13>, <&dmac2 0x12>; 1228 dma-names = "tx", "rx", "tx", "rx"; 1229 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1230 resets = <&cpg 310>; 1231 status = "disabled"; 1232 }; 1233 1234 scif3: serial@e6c50000 { 1235 compatible = "renesas,scif-r8a774a1", 1236 "renesas,rcar-gen3-scif", "renesas,scif"; 1237 reg = <0 0xe6c50000 0 0x40>; 1238 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1239 clocks = <&cpg CPG_MOD 204>, 1240 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1241 <&scif_clk>; 1242 clock-names = "fck", "brg_int", "scif_clk"; 1243 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1244 dma-names = "tx", "rx"; 1245 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1246 resets = <&cpg 204>; 1247 status = "disabled"; 1248 }; 1249 1250 scif4: serial@e6c40000 { 1251 compatible = "renesas,scif-r8a774a1", 1252 "renesas,rcar-gen3-scif", "renesas,scif"; 1253 reg = <0 0xe6c40000 0 0x40>; 1254 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1255 clocks = <&cpg CPG_MOD 203>, 1256 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1257 <&scif_clk>; 1258 clock-names = "fck", "brg_int", "scif_clk"; 1259 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1260 dma-names = "tx", "rx"; 1261 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1262 resets = <&cpg 203>; 1263 status = "disabled"; 1264 }; 1265 1266 scif5: serial@e6f30000 { 1267 compatible = "renesas,scif-r8a774a1", 1268 "renesas,rcar-gen3-scif", "renesas,scif"; 1269 reg = <0 0xe6f30000 0 0x40>; 1270 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1271 clocks = <&cpg CPG_MOD 202>, 1272 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1273 <&scif_clk>; 1274 clock-names = "fck", "brg_int", "scif_clk"; 1275 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1276 <&dmac2 0x5b>, <&dmac2 0x5a>; 1277 dma-names = "tx", "rx", "tx", "rx"; 1278 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1279 resets = <&cpg 202>; 1280 status = "disabled"; 1281 }; 1282 1283 msiof0: spi@e6e90000 { 1284 compatible = "renesas,msiof-r8a774a1", 1285 "renesas,rcar-gen3-msiof"; 1286 reg = <0 0xe6e90000 0 0x0064>; 1287 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1288 clocks = <&cpg CPG_MOD 211>; 1289 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1290 <&dmac2 0x41>, <&dmac2 0x40>; 1291 dma-names = "tx", "rx", "tx", "rx"; 1292 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1293 resets = <&cpg 211>; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 status = "disabled"; 1297 }; 1298 1299 msiof1: spi@e6ea0000 { 1300 compatible = "renesas,msiof-r8a774a1", 1301 "renesas,rcar-gen3-msiof"; 1302 reg = <0 0xe6ea0000 0 0x0064>; 1303 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1304 clocks = <&cpg CPG_MOD 210>; 1305 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1306 <&dmac2 0x43>, <&dmac2 0x42>; 1307 dma-names = "tx", "rx", "tx", "rx"; 1308 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1309 resets = <&cpg 210>; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 status = "disabled"; 1313 }; 1314 1315 msiof2: spi@e6c00000 { 1316 compatible = "renesas,msiof-r8a774a1", 1317 "renesas,rcar-gen3-msiof"; 1318 reg = <0 0xe6c00000 0 0x0064>; 1319 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1320 clocks = <&cpg CPG_MOD 209>; 1321 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1322 dma-names = "tx", "rx"; 1323 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1324 resets = <&cpg 209>; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 status = "disabled"; 1328 }; 1329 1330 msiof3: spi@e6c10000 { 1331 compatible = "renesas,msiof-r8a774a1", 1332 "renesas,rcar-gen3-msiof"; 1333 reg = <0 0xe6c10000 0 0x0064>; 1334 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1335 clocks = <&cpg CPG_MOD 208>; 1336 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1337 dma-names = "tx", "rx"; 1338 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1339 resets = <&cpg 208>; 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 status = "disabled"; 1343 }; 1344 1345 vin0: video@e6ef0000 { 1346 compatible = "renesas,vin-r8a774a1"; 1347 reg = <0 0xe6ef0000 0 0x1000>; 1348 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1349 clocks = <&cpg CPG_MOD 811>; 1350 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1351 resets = <&cpg 811>; 1352 renesas,id = <0>; 1353 status = "disabled"; 1354 1355 ports { 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 1359 port@1 { 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 1363 reg = <1>; 1364 1365 vin0csi20: endpoint@0 { 1366 reg = <0>; 1367 remote-endpoint = <&csi20vin0>; 1368 }; 1369 vin0csi40: endpoint@2 { 1370 reg = <2>; 1371 remote-endpoint = <&csi40vin0>; 1372 }; 1373 }; 1374 }; 1375 }; 1376 1377 vin1: video@e6ef1000 { 1378 compatible = "renesas,vin-r8a774a1"; 1379 reg = <0 0xe6ef1000 0 0x1000>; 1380 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1381 clocks = <&cpg CPG_MOD 810>; 1382 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1383 resets = <&cpg 810>; 1384 renesas,id = <1>; 1385 status = "disabled"; 1386 1387 ports { 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 1391 port@1 { 1392 #address-cells = <1>; 1393 #size-cells = <0>; 1394 1395 reg = <1>; 1396 1397 vin1csi20: endpoint@0 { 1398 reg = <0>; 1399 remote-endpoint = <&csi20vin1>; 1400 }; 1401 vin1csi40: endpoint@2 { 1402 reg = <2>; 1403 remote-endpoint = <&csi40vin1>; 1404 }; 1405 }; 1406 }; 1407 }; 1408 1409 vin2: video@e6ef2000 { 1410 compatible = "renesas,vin-r8a774a1"; 1411 reg = <0 0xe6ef2000 0 0x1000>; 1412 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1413 clocks = <&cpg CPG_MOD 809>; 1414 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1415 resets = <&cpg 809>; 1416 renesas,id = <2>; 1417 status = "disabled"; 1418 1419 ports { 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 1423 port@1 { 1424 #address-cells = <1>; 1425 #size-cells = <0>; 1426 1427 reg = <1>; 1428 1429 vin2csi20: endpoint@0 { 1430 reg = <0>; 1431 remote-endpoint = <&csi20vin2>; 1432 }; 1433 vin2csi40: endpoint@2 { 1434 reg = <2>; 1435 remote-endpoint = <&csi40vin2>; 1436 }; 1437 }; 1438 }; 1439 }; 1440 1441 vin3: video@e6ef3000 { 1442 compatible = "renesas,vin-r8a774a1"; 1443 reg = <0 0xe6ef3000 0 0x1000>; 1444 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1445 clocks = <&cpg CPG_MOD 808>; 1446 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1447 resets = <&cpg 808>; 1448 renesas,id = <3>; 1449 status = "disabled"; 1450 1451 ports { 1452 #address-cells = <1>; 1453 #size-cells = <0>; 1454 1455 port@1 { 1456 #address-cells = <1>; 1457 #size-cells = <0>; 1458 1459 reg = <1>; 1460 1461 vin3csi20: endpoint@0 { 1462 reg = <0>; 1463 remote-endpoint = <&csi20vin3>; 1464 }; 1465 vin3csi40: endpoint@2 { 1466 reg = <2>; 1467 remote-endpoint = <&csi40vin3>; 1468 }; 1469 }; 1470 }; 1471 }; 1472 1473 vin4: video@e6ef4000 { 1474 compatible = "renesas,vin-r8a774a1"; 1475 reg = <0 0xe6ef4000 0 0x1000>; 1476 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1477 clocks = <&cpg CPG_MOD 807>; 1478 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1479 resets = <&cpg 807>; 1480 renesas,id = <4>; 1481 status = "disabled"; 1482 1483 ports { 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 1487 port@1 { 1488 #address-cells = <1>; 1489 #size-cells = <0>; 1490 1491 reg = <1>; 1492 1493 vin4csi20: endpoint@0 { 1494 reg = <0>; 1495 remote-endpoint = <&csi20vin4>; 1496 }; 1497 vin4csi40: endpoint@2 { 1498 reg = <2>; 1499 remote-endpoint = <&csi40vin4>; 1500 }; 1501 }; 1502 }; 1503 }; 1504 1505 vin5: video@e6ef5000 { 1506 compatible = "renesas,vin-r8a774a1"; 1507 reg = <0 0xe6ef5000 0 0x1000>; 1508 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1509 clocks = <&cpg CPG_MOD 806>; 1510 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1511 resets = <&cpg 806>; 1512 renesas,id = <5>; 1513 status = "disabled"; 1514 1515 ports { 1516 #address-cells = <1>; 1517 #size-cells = <0>; 1518 1519 port@1 { 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 1523 reg = <1>; 1524 1525 vin5csi20: endpoint@0 { 1526 reg = <0>; 1527 remote-endpoint = <&csi20vin5>; 1528 }; 1529 vin5csi40: endpoint@2 { 1530 reg = <2>; 1531 remote-endpoint = <&csi40vin5>; 1532 }; 1533 }; 1534 }; 1535 }; 1536 1537 vin6: video@e6ef6000 { 1538 compatible = "renesas,vin-r8a774a1"; 1539 reg = <0 0xe6ef6000 0 0x1000>; 1540 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1541 clocks = <&cpg CPG_MOD 805>; 1542 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1543 resets = <&cpg 805>; 1544 renesas,id = <6>; 1545 status = "disabled"; 1546 1547 ports { 1548 #address-cells = <1>; 1549 #size-cells = <0>; 1550 1551 port@1 { 1552 #address-cells = <1>; 1553 #size-cells = <0>; 1554 1555 reg = <1>; 1556 1557 vin6csi20: endpoint@0 { 1558 reg = <0>; 1559 remote-endpoint = <&csi20vin6>; 1560 }; 1561 vin6csi40: endpoint@2 { 1562 reg = <2>; 1563 remote-endpoint = <&csi40vin6>; 1564 }; 1565 }; 1566 }; 1567 }; 1568 1569 vin7: video@e6ef7000 { 1570 compatible = "renesas,vin-r8a774a1"; 1571 reg = <0 0xe6ef7000 0 0x1000>; 1572 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1573 clocks = <&cpg CPG_MOD 804>; 1574 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1575 resets = <&cpg 804>; 1576 renesas,id = <7>; 1577 status = "disabled"; 1578 1579 ports { 1580 #address-cells = <1>; 1581 #size-cells = <0>; 1582 1583 port@1 { 1584 #address-cells = <1>; 1585 #size-cells = <0>; 1586 1587 reg = <1>; 1588 1589 vin7csi20: endpoint@0 { 1590 reg = <0>; 1591 remote-endpoint = <&csi20vin7>; 1592 }; 1593 vin7csi40: endpoint@2 { 1594 reg = <2>; 1595 remote-endpoint = <&csi40vin7>; 1596 }; 1597 }; 1598 }; 1599 }; 1600 1601 rcar_sound: sound@ec500000 { 1602 /* 1603 * #sound-dai-cells is required 1604 * 1605 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1606 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1607 */ 1608 /* 1609 * #clock-cells is required for audio_clkout0/1/2/3 1610 * 1611 * clkout : #clock-cells = <0>; <&rcar_sound>; 1612 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1613 */ 1614 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; 1615 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1616 <0 0xec5a0000 0 0x100>, /* ADG */ 1617 <0 0xec540000 0 0x1000>, /* SSIU */ 1618 <0 0xec541000 0 0x280>, /* SSI */ 1619 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1620 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1621 1622 clocks = <&cpg CPG_MOD 1005>, 1623 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1624 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1625 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1626 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1627 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1628 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1629 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1630 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1631 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1632 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1633 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1634 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1635 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1636 <&audio_clk_a>, <&audio_clk_b>, 1637 <&audio_clk_c>, 1638 <&cpg CPG_CORE R8A774A1_CLK_S0D4>; 1639 clock-names = "ssi-all", 1640 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1641 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1642 "ssi.1", "ssi.0", 1643 "src.9", "src.8", "src.7", "src.6", 1644 "src.5", "src.4", "src.3", "src.2", 1645 "src.1", "src.0", 1646 "mix.1", "mix.0", 1647 "ctu.1", "ctu.0", 1648 "dvc.0", "dvc.1", 1649 "clk_a", "clk_b", "clk_c", "clk_i"; 1650 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1651 resets = <&cpg 1005>, 1652 <&cpg 1006>, <&cpg 1007>, 1653 <&cpg 1008>, <&cpg 1009>, 1654 <&cpg 1010>, <&cpg 1011>, 1655 <&cpg 1012>, <&cpg 1013>, 1656 <&cpg 1014>, <&cpg 1015>; 1657 reset-names = "ssi-all", 1658 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1659 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1660 "ssi.1", "ssi.0"; 1661 status = "disabled"; 1662 1663 rcar_sound,dvc { 1664 dvc0: dvc-0 { 1665 dmas = <&audma1 0xbc>; 1666 dma-names = "tx"; 1667 }; 1668 dvc1: dvc-1 { 1669 dmas = <&audma1 0xbe>; 1670 dma-names = "tx"; 1671 }; 1672 }; 1673 1674 rcar_sound,mix { 1675 mix0: mix-0 { }; 1676 mix1: mix-1 { }; 1677 }; 1678 1679 rcar_sound,ctu { 1680 ctu00: ctu-0 { }; 1681 ctu01: ctu-1 { }; 1682 ctu02: ctu-2 { }; 1683 ctu03: ctu-3 { }; 1684 ctu10: ctu-4 { }; 1685 ctu11: ctu-5 { }; 1686 ctu12: ctu-6 { }; 1687 ctu13: ctu-7 { }; 1688 }; 1689 1690 rcar_sound,src { 1691 src0: src-0 { 1692 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1693 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1694 dma-names = "rx", "tx"; 1695 }; 1696 src1: src-1 { 1697 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1698 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1699 dma-names = "rx", "tx"; 1700 }; 1701 src2: src-2 { 1702 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1703 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1704 dma-names = "rx", "tx"; 1705 }; 1706 src3: src-3 { 1707 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1708 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1709 dma-names = "rx", "tx"; 1710 }; 1711 src4: src-4 { 1712 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1713 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1714 dma-names = "rx", "tx"; 1715 }; 1716 src5: src-5 { 1717 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1718 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1719 dma-names = "rx", "tx"; 1720 }; 1721 src6: src-6 { 1722 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1723 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1724 dma-names = "rx", "tx"; 1725 }; 1726 src7: src-7 { 1727 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1728 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1729 dma-names = "rx", "tx"; 1730 }; 1731 src8: src-8 { 1732 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1733 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1734 dma-names = "rx", "tx"; 1735 }; 1736 src9: src-9 { 1737 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1738 dmas = <&audma0 0x97>, <&audma1 0xba>; 1739 dma-names = "rx", "tx"; 1740 }; 1741 }; 1742 1743 rcar_sound,ssi { 1744 ssi0: ssi-0 { 1745 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1746 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; 1747 dma-names = "rx", "tx", "rxu", "txu"; 1748 }; 1749 ssi1: ssi-1 { 1750 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1751 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; 1752 dma-names = "rx", "tx", "rxu", "txu"; 1753 }; 1754 ssi2: ssi-2 { 1755 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1756 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; 1757 dma-names = "rx", "tx", "rxu", "txu"; 1758 }; 1759 ssi3: ssi-3 { 1760 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1761 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; 1762 dma-names = "rx", "tx", "rxu", "txu"; 1763 }; 1764 ssi4: ssi-4 { 1765 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1766 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; 1767 dma-names = "rx", "tx", "rxu", "txu"; 1768 }; 1769 ssi5: ssi-5 { 1770 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1771 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; 1772 dma-names = "rx", "tx", "rxu", "txu"; 1773 }; 1774 ssi6: ssi-6 { 1775 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1776 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; 1777 dma-names = "rx", "tx", "rxu", "txu"; 1778 }; 1779 ssi7: ssi-7 { 1780 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1781 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; 1782 dma-names = "rx", "tx", "rxu", "txu"; 1783 }; 1784 ssi8: ssi-8 { 1785 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1786 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; 1787 dma-names = "rx", "tx", "rxu", "txu"; 1788 }; 1789 ssi9: ssi-9 { 1790 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1791 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; 1792 dma-names = "rx", "tx", "rxu", "txu"; 1793 }; 1794 }; 1795 1796 ports { 1797 #address-cells = <1>; 1798 #size-cells = <0>; 1799 port@0 { 1800 reg = <0>; 1801 }; 1802 port@1 { 1803 reg = <1>; 1804 }; 1805 }; 1806 }; 1807 1808 audma0: dma-controller@ec700000 { 1809 compatible = "renesas,dmac-r8a774a1", 1810 "renesas,rcar-dmac"; 1811 reg = <0 0xec700000 0 0x10000>; 1812 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 1813 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 1814 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 1815 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 1816 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 1817 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 1818 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 1819 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 1820 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 1821 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 1822 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 1823 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 1824 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 1825 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 1826 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 1827 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 1828 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1829 interrupt-names = "error", 1830 "ch0", "ch1", "ch2", "ch3", 1831 "ch4", "ch5", "ch6", "ch7", 1832 "ch8", "ch9", "ch10", "ch11", 1833 "ch12", "ch13", "ch14", "ch15"; 1834 clocks = <&cpg CPG_MOD 502>; 1835 clock-names = "fck"; 1836 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1837 resets = <&cpg 502>; 1838 #dma-cells = <1>; 1839 dma-channels = <16>; 1840 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1841 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1842 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1843 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1844 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1845 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1846 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1847 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1848 }; 1849 1850 audma1: dma-controller@ec720000 { 1851 compatible = "renesas,dmac-r8a774a1", 1852 "renesas,rcar-dmac"; 1853 reg = <0 0xec720000 0 0x10000>; 1854 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 1855 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 1856 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 1857 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 1858 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 1859 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 1860 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 1861 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 1862 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 1863 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 1864 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 1865 GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 1866 GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 1867 GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 1868 GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH 1869 GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 1870 GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 1871 interrupt-names = "error", 1872 "ch0", "ch1", "ch2", "ch3", 1873 "ch4", "ch5", "ch6", "ch7", 1874 "ch8", "ch9", "ch10", "ch11", 1875 "ch12", "ch13", "ch14", "ch15"; 1876 clocks = <&cpg CPG_MOD 501>; 1877 clock-names = "fck"; 1878 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1879 resets = <&cpg 501>; 1880 #dma-cells = <1>; 1881 dma-channels = <16>; 1882 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 1883 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 1884 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 1885 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 1886 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 1887 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 1888 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 1889 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 1890 }; 1891 1892 xhci0: usb@ee000000 { 1893 compatible = "renesas,xhci-r8a774a1", 1894 "renesas,rcar-gen3-xhci"; 1895 reg = <0 0xee000000 0 0xc00>; 1896 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1897 clocks = <&cpg CPG_MOD 328>; 1898 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1899 resets = <&cpg 328>; 1900 status = "disabled"; 1901 }; 1902 1903 usb3_peri0: usb@ee020000 { 1904 compatible = "renesas,r8a774a1-usb3-peri", 1905 "renesas,rcar-gen3-usb3-peri"; 1906 reg = <0 0xee020000 0 0x400>; 1907 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1908 clocks = <&cpg CPG_MOD 328>; 1909 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1910 resets = <&cpg 328>; 1911 status = "disabled"; 1912 }; 1913 1914 ohci0: usb@ee080000 { 1915 compatible = "generic-ohci"; 1916 reg = <0 0xee080000 0 0x100>; 1917 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1918 clocks = <&cpg CPG_MOD 703>; 1919 phys = <&usb2_phy0 1>; 1920 phy-names = "usb"; 1921 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1922 resets = <&cpg 703>; 1923 status = "disabled"; 1924 }; 1925 1926 ohci1: usb@ee0a0000 { 1927 compatible = "generic-ohci"; 1928 reg = <0 0xee0a0000 0 0x100>; 1929 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1930 clocks = <&cpg CPG_MOD 702>; 1931 phys = <&usb2_phy1 1>; 1932 phy-names = "usb"; 1933 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1934 resets = <&cpg 702>; 1935 status = "disabled"; 1936 }; 1937 1938 ehci0: usb@ee080100 { 1939 compatible = "generic-ehci"; 1940 reg = <0 0xee080100 0 0x100>; 1941 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1942 clocks = <&cpg CPG_MOD 703>; 1943 phys = <&usb2_phy0 2>; 1944 phy-names = "usb"; 1945 companion = <&ohci0>; 1946 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1947 resets = <&cpg 703>; 1948 status = "disabled"; 1949 }; 1950 1951 ehci1: usb@ee0a0100 { 1952 compatible = "generic-ehci"; 1953 reg = <0 0xee0a0100 0 0x100>; 1954 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1955 clocks = <&cpg CPG_MOD 702>; 1956 phys = <&usb2_phy1 2>; 1957 phy-names = "usb"; 1958 companion = <&ohci1>; 1959 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1960 resets = <&cpg 702>; 1961 status = "disabled"; 1962 }; 1963 1964 usb2_phy0: usb-phy@ee080200 { 1965 compatible = "renesas,usb2-phy-r8a774a1", 1966 "renesas,rcar-gen3-usb2-phy"; 1967 reg = <0 0xee080200 0 0x700>; 1968 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1969 clocks = <&cpg CPG_MOD 703>; 1970 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1971 resets = <&cpg 703>; 1972 #phy-cells = <1>; 1973 status = "disabled"; 1974 }; 1975 1976 usb2_phy1: usb-phy@ee0a0200 { 1977 compatible = "renesas,usb2-phy-r8a774a1", 1978 "renesas,rcar-gen3-usb2-phy"; 1979 reg = <0 0xee0a0200 0 0x700>; 1980 clocks = <&cpg CPG_MOD 702>; 1981 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1982 resets = <&cpg 702>; 1983 #phy-cells = <1>; 1984 status = "disabled"; 1985 }; 1986 1987 sdhi0: sd@ee100000 { 1988 compatible = "renesas,sdhi-r8a774a1", 1989 "renesas,rcar-gen3-sdhi"; 1990 reg = <0 0xee100000 0 0x2000>; 1991 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1992 clocks = <&cpg CPG_MOD 314>; 1993 max-frequency = <200000000>; 1994 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1995 resets = <&cpg 314>; 1996 status = "disabled"; 1997 }; 1998 1999 sdhi1: sd@ee120000 { 2000 compatible = "renesas,sdhi-r8a774a1", 2001 "renesas,rcar-gen3-sdhi"; 2002 reg = <0 0xee120000 0 0x2000>; 2003 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2004 clocks = <&cpg CPG_MOD 313>; 2005 max-frequency = <200000000>; 2006 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2007 resets = <&cpg 313>; 2008 status = "disabled"; 2009 }; 2010 2011 sdhi2: sd@ee140000 { 2012 compatible = "renesas,sdhi-r8a774a1", 2013 "renesas,rcar-gen3-sdhi"; 2014 reg = <0 0xee140000 0 0x2000>; 2015 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2016 clocks = <&cpg CPG_MOD 312>; 2017 max-frequency = <200000000>; 2018 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2019 resets = <&cpg 312>; 2020 status = "disabled"; 2021 }; 2022 2023 sdhi3: sd@ee160000 { 2024 compatible = "renesas,sdhi-r8a774a1", 2025 "renesas,rcar-gen3-sdhi"; 2026 reg = <0 0xee160000 0 0x2000>; 2027 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2028 clocks = <&cpg CPG_MOD 311>; 2029 max-frequency = <200000000>; 2030 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2031 resets = <&cpg 311>; 2032 status = "disabled"; 2033 }; 2034 2035 gic: interrupt-controller@f1010000 { 2036 compatible = "arm,gic-400"; 2037 #interrupt-cells = <3>; 2038 #address-cells = <0>; 2039 interrupt-controller; 2040 reg = <0x0 0xf1010000 0 0x1000>, 2041 <0x0 0xf1020000 0 0x20000>, 2042 <0x0 0xf1040000 0 0x20000>, 2043 <0x0 0xf1060000 0 0x20000>; 2044 interrupts = <GIC_PPI 9 2045 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 2046 clocks = <&cpg CPG_MOD 408>; 2047 clock-names = "clk"; 2048 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2049 resets = <&cpg 408>; 2050 }; 2051 2052 pciec0: pcie@fe000000 { 2053 compatible = "renesas,pcie-r8a774a1", 2054 "renesas,pcie-rcar-gen3"; 2055 reg = <0 0xfe000000 0 0x80000>; 2056 #address-cells = <3>; 2057 #size-cells = <2>; 2058 bus-range = <0x00 0xff>; 2059 device_type = "pci"; 2060 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 2061 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 2062 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 2063 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2064 /* Map all possible DDR as inbound ranges */ 2065 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2066 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2068 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2069 #interrupt-cells = <1>; 2070 interrupt-map-mask = <0 0 0 0>; 2071 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2072 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2073 clock-names = "pcie", "pcie_bus"; 2074 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2075 resets = <&cpg 319>; 2076 status = "disabled"; 2077 }; 2078 2079 pciec1: pcie@ee800000 { 2080 compatible = "renesas,pcie-r8a774a1", 2081 "renesas,pcie-rcar-gen3"; 2082 reg = <0 0xee800000 0 0x80000>; 2083 #address-cells = <3>; 2084 #size-cells = <2>; 2085 bus-range = <0x00 0xff>; 2086 device_type = "pci"; 2087 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 2088 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 2089 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 2090 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2091 /* Map all possible DDR as inbound ranges */ 2092 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2093 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2096 #interrupt-cells = <1>; 2097 interrupt-map-mask = <0 0 0 0>; 2098 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2099 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2100 clock-names = "pcie", "pcie_bus"; 2101 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2102 resets = <&cpg 318>; 2103 status = "disabled"; 2104 }; 2105 2106 fdp1@fe940000 { 2107 compatible = "renesas,fdp1"; 2108 reg = <0 0xfe940000 0 0x2400>; 2109 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2110 clocks = <&cpg CPG_MOD 119>; 2111 power-domains = <&sysc R8A774A1_PD_A3VC>; 2112 resets = <&cpg 119>; 2113 renesas,fcp = <&fcpf0>; 2114 }; 2115 2116 fcpf0: fcp@fe950000 { 2117 compatible = "renesas,fcpf"; 2118 reg = <0 0xfe950000 0 0x200>; 2119 clocks = <&cpg CPG_MOD 615>; 2120 power-domains = <&sysc R8A774A1_PD_A3VC>; 2121 resets = <&cpg 615>; 2122 }; 2123 2124 fcpvb0: fcp@fe96f000 { 2125 compatible = "renesas,fcpv"; 2126 reg = <0 0xfe96f000 0 0x200>; 2127 clocks = <&cpg CPG_MOD 607>; 2128 power-domains = <&sysc R8A774A1_PD_A3VC>; 2129 resets = <&cpg 607>; 2130 }; 2131 2132 fcpvd0: fcp@fea27000 { 2133 compatible = "renesas,fcpv"; 2134 reg = <0 0xfea27000 0 0x200>; 2135 clocks = <&cpg CPG_MOD 603>; 2136 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2137 resets = <&cpg 603>; 2138 iommus = <&ipmmu_vi0 8>; 2139 }; 2140 2141 fcpvd1: fcp@fea2f000 { 2142 compatible = "renesas,fcpv"; 2143 reg = <0 0xfea2f000 0 0x200>; 2144 clocks = <&cpg CPG_MOD 602>; 2145 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2146 resets = <&cpg 602>; 2147 iommus = <&ipmmu_vi0 9>; 2148 }; 2149 2150 fcpvd2: fcp@fea37000 { 2151 compatible = "renesas,fcpv"; 2152 reg = <0 0xfea37000 0 0x200>; 2153 clocks = <&cpg CPG_MOD 601>; 2154 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2155 resets = <&cpg 601>; 2156 iommus = <&ipmmu_vi0 10>; 2157 }; 2158 2159 fcpvi0: fcp@fe9af000 { 2160 compatible = "renesas,fcpv"; 2161 reg = <0 0xfe9af000 0 0x200>; 2162 clocks = <&cpg CPG_MOD 611>; 2163 power-domains = <&sysc R8A774A1_PD_A3VC>; 2164 resets = <&cpg 611>; 2165 iommus = <&ipmmu_vc0 19>; 2166 }; 2167 2168 vspb: vsp@fe960000 { 2169 compatible = "renesas,vsp2"; 2170 reg = <0 0xfe960000 0 0x8000>; 2171 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2172 clocks = <&cpg CPG_MOD 626>; 2173 power-domains = <&sysc R8A774A1_PD_A3VC>; 2174 resets = <&cpg 626>; 2175 2176 renesas,fcp = <&fcpvb0>; 2177 }; 2178 2179 vspd0: vsp@fea20000 { 2180 compatible = "renesas,vsp2"; 2181 reg = <0 0xfea20000 0 0x5000>; 2182 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2183 clocks = <&cpg CPG_MOD 623>; 2184 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2185 resets = <&cpg 623>; 2186 2187 renesas,fcp = <&fcpvd0>; 2188 }; 2189 2190 vspd1: vsp@fea28000 { 2191 compatible = "renesas,vsp2"; 2192 reg = <0 0xfea28000 0 0x5000>; 2193 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2194 clocks = <&cpg CPG_MOD 622>; 2195 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2196 resets = <&cpg 622>; 2197 2198 renesas,fcp = <&fcpvd1>; 2199 }; 2200 2201 vspd2: vsp@fea30000 { 2202 compatible = "renesas,vsp2"; 2203 reg = <0 0xfea30000 0 0x5000>; 2204 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2205 clocks = <&cpg CPG_MOD 621>; 2206 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2207 resets = <&cpg 621>; 2208 2209 renesas,fcp = <&fcpvd2>; 2210 }; 2211 2212 vspi0: vsp@fe9a0000 { 2213 compatible = "renesas,vsp2"; 2214 reg = <0 0xfe9a0000 0 0x8000>; 2215 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2216 clocks = <&cpg CPG_MOD 631>; 2217 power-domains = <&sysc R8A774A1_PD_A3VC>; 2218 resets = <&cpg 631>; 2219 2220 renesas,fcp = <&fcpvi0>; 2221 }; 2222 2223 csi20: csi2@fea80000 { 2224 compatible = "renesas,r8a774a1-csi2"; 2225 reg = <0 0xfea80000 0 0x10000>; 2226 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2227 clocks = <&cpg CPG_MOD 714>; 2228 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2229 resets = <&cpg 714>; 2230 status = "disabled"; 2231 2232 ports { 2233 #address-cells = <1>; 2234 #size-cells = <0>; 2235 2236 port@1 { 2237 #address-cells = <1>; 2238 #size-cells = <0>; 2239 2240 reg = <1>; 2241 2242 csi20vin0: endpoint@0 { 2243 reg = <0>; 2244 remote-endpoint = <&vin0csi20>; 2245 }; 2246 csi20vin1: endpoint@1 { 2247 reg = <1>; 2248 remote-endpoint = <&vin1csi20>; 2249 }; 2250 csi20vin2: endpoint@2 { 2251 reg = <2>; 2252 remote-endpoint = <&vin2csi20>; 2253 }; 2254 csi20vin3: endpoint@3 { 2255 reg = <3>; 2256 remote-endpoint = <&vin3csi20>; 2257 }; 2258 csi20vin4: endpoint@4 { 2259 reg = <4>; 2260 remote-endpoint = <&vin4csi20>; 2261 }; 2262 csi20vin5: endpoint@5 { 2263 reg = <5>; 2264 remote-endpoint = <&vin5csi20>; 2265 }; 2266 csi20vin6: endpoint@6 { 2267 reg = <6>; 2268 remote-endpoint = <&vin6csi20>; 2269 }; 2270 csi20vin7: endpoint@7 { 2271 reg = <7>; 2272 remote-endpoint = <&vin7csi20>; 2273 }; 2274 }; 2275 }; 2276 }; 2277 2278 csi40: csi2@feaa0000 { 2279 compatible = "renesas,r8a774a1-csi2"; 2280 reg = <0 0xfeaa0000 0 0x10000>; 2281 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2282 clocks = <&cpg CPG_MOD 716>; 2283 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2284 resets = <&cpg 716>; 2285 status = "disabled"; 2286 2287 ports { 2288 #address-cells = <1>; 2289 #size-cells = <0>; 2290 2291 port@1 { 2292 #address-cells = <1>; 2293 #size-cells = <0>; 2294 2295 reg = <1>; 2296 2297 csi40vin0: endpoint@0 { 2298 reg = <0>; 2299 remote-endpoint = <&vin0csi40>; 2300 }; 2301 csi40vin1: endpoint@1 { 2302 reg = <1>; 2303 remote-endpoint = <&vin1csi40>; 2304 }; 2305 csi40vin2: endpoint@2 { 2306 reg = <2>; 2307 remote-endpoint = <&vin2csi40>; 2308 }; 2309 csi40vin3: endpoint@3 { 2310 reg = <3>; 2311 remote-endpoint = <&vin3csi40>; 2312 }; 2313 csi40vin4: endpoint@4 { 2314 reg = <4>; 2315 remote-endpoint = <&vin4csi40>; 2316 }; 2317 csi40vin5: endpoint@5 { 2318 reg = <5>; 2319 remote-endpoint = <&vin5csi40>; 2320 }; 2321 csi40vin6: endpoint@6 { 2322 reg = <6>; 2323 remote-endpoint = <&vin6csi40>; 2324 }; 2325 csi40vin7: endpoint@7 { 2326 reg = <7>; 2327 remote-endpoint = <&vin7csi40>; 2328 }; 2329 }; 2330 2331 }; 2332 }; 2333 2334 du: display@feb00000 { 2335 compatible = "renesas,du-r8a774a1"; 2336 reg = <0 0xfeb00000 0 0x70000>; 2337 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2338 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2339 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2340 clocks = <&cpg CPG_MOD 724>, 2341 <&cpg CPG_MOD 723>, 2342 <&cpg CPG_MOD 722>; 2343 clock-names = "du.0", "du.1", "du.2"; 2344 status = "disabled"; 2345 2346 vsps = <&vspd0 &vspd1 &vspd2>; 2347 2348 ports { 2349 #address-cells = <1>; 2350 #size-cells = <0>; 2351 2352 port@0 { 2353 reg = <0>; 2354 du_out_rgb: endpoint { 2355 }; 2356 }; 2357 port@1 { 2358 reg = <1>; 2359 du_out_hdmi0: endpoint { 2360 }; 2361 }; 2362 port@2 { 2363 reg = <2>; 2364 du_out_lvds0: endpoint { 2365 remote-endpoint = <&lvds0_in>; 2366 }; 2367 }; 2368 }; 2369 }; 2370 2371 lvds0: lvds@feb90000 { 2372 compatible = "renesas,r8a774a1-lvds"; 2373 reg = <0 0xfeb90000 0 0x14>; 2374 clocks = <&cpg CPG_MOD 727>; 2375 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2376 resets = <&cpg 727>; 2377 status = "disabled"; 2378 2379 ports { 2380 #address-cells = <1>; 2381 #size-cells = <0>; 2382 2383 port@0 { 2384 reg = <0>; 2385 lvds0_in: endpoint { 2386 remote-endpoint = <&du_out_lvds0>; 2387 }; 2388 }; 2389 port@1 { 2390 reg = <1>; 2391 lvds0_out: endpoint { 2392 }; 2393 }; 2394 }; 2395 }; 2396 2397 prr: chipid@fff00044 { 2398 compatible = "renesas,prr"; 2399 reg = <0 0xfff00044 0 4>; 2400 }; 2401 }; 2402 2403 thermal-zones { 2404 sensor_thermal1: sensor-thermal1 { 2405 polling-delay-passive = <250>; 2406 polling-delay = <1000>; 2407 thermal-sensors = <&tsc 0>; 2408 2409 trips { 2410 sensor1_crit: sensor1-crit { 2411 temperature = <120000>; 2412 hysteresis = <1000>; 2413 type = "critical"; 2414 }; 2415 }; 2416 }; 2417 2418 sensor_thermal2: sensor-thermal2 { 2419 polling-delay-passive = <250>; 2420 polling-delay = <1000>; 2421 thermal-sensors = <&tsc 1>; 2422 2423 trips { 2424 sensor2_crit: sensor2-crit { 2425 temperature = <120000>; 2426 hysteresis = <1000>; 2427 type = "critical"; 2428 }; 2429 }; 2430 2431 }; 2432 2433 sensor_thermal3: sensor-thermal3 { 2434 polling-delay-passive = <250>; 2435 polling-delay = <1000>; 2436 thermal-sensors = <&tsc 2>; 2437 2438 trips { 2439 sensor3_crit: sensor3-crit { 2440 temperature = <120000>; 2441 hysteresis = <1000>; 2442 type = "critical"; 2443 }; 2444 }; 2445 }; 2446 }; 2447 2448 timer { 2449 compatible = "arm,armv8-timer"; 2450 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2451 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2452 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2453 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2454 }; 2455 2456 /* External USB clocks - can be overridden by the board */ 2457 usb3s0_clk: usb3s0 { 2458 compatible = "fixed-clock"; 2459 #clock-cells = <0>; 2460 clock-frequency = <0>; 2461 }; 2462 2463 usb_extal_clk: usb_extal { 2464 compatible = "fixed-clock"; 2465 #clock-cells = <0>; 2466 clock-frequency = <0>; 2467 }; 2468}; 2469