1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r8a774a1-cpg-mssr.h> 11#include <dt-bindings/power/r8a774a1-sysc.h> 12 13#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4 14 15/ { 16 compatible = "renesas,r8a774a1"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &i2c0; 22 i2c1 = &i2c1; 23 i2c2 = &i2c2; 24 i2c3 = &i2c3; 25 i2c4 = &i2c4; 26 i2c5 = &i2c5; 27 i2c6 = &i2c6; 28 i2c7 = &i2c_dvfs; 29 }; 30 31 /* 32 * The external audio clocks are configured as 0 Hz fixed frequency 33 * clocks by default. 34 * Boards that provide audio clocks should override them. 35 */ 36 audio_clk_a: audio_clk_a { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 audio_clk_b: audio_clk_b { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <0>; 46 }; 47 48 audio_clk_c: audio_clk_c { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <0>; 52 }; 53 54 /* External CAN clock - to be overridden by boards that provide it */ 55 can_clk: can { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 59 }; 60 61 cluster0_opp: opp_table0 { 62 compatible = "operating-points-v2"; 63 opp-shared; 64 65 opp-500000000 { 66 opp-hz = /bits/ 64 <500000000>; 67 opp-microvolt = <820000>; 68 clock-latency-ns = <300000>; 69 }; 70 opp-1000000000 { 71 opp-hz = /bits/ 64 <1000000000>; 72 opp-microvolt = <820000>; 73 clock-latency-ns = <300000>; 74 }; 75 opp-1500000000 { 76 opp-hz = /bits/ 64 <1500000000>; 77 opp-microvolt = <820000>; 78 clock-latency-ns = <300000>; 79 }; 80 }; 81 82 cluster1_opp: opp_table1 { 83 compatible = "operating-points-v2"; 84 opp-shared; 85 86 opp-800000000 { 87 opp-hz = /bits/ 64 <800000000>; 88 opp-microvolt = <820000>; 89 clock-latency-ns = <300000>; 90 }; 91 opp-1000000000 { 92 opp-hz = /bits/ 64 <1000000000>; 93 opp-microvolt = <820000>; 94 clock-latency-ns = <300000>; 95 }; 96 opp-1200000000 { 97 opp-hz = /bits/ 64 <1200000000>; 98 opp-microvolt = <820000>; 99 clock-latency-ns = <300000>; 100 }; 101 }; 102 103 cpus { 104 #address-cells = <1>; 105 #size-cells = <0>; 106 107 cpu-map { 108 cluster0 { 109 core0 { 110 cpu = <&a57_0>; 111 }; 112 core1 { 113 cpu = <&a57_1>; 114 }; 115 }; 116 117 cluster1 { 118 core0 { 119 cpu = <&a53_0>; 120 }; 121 core1 { 122 cpu = <&a53_1>; 123 }; 124 core2 { 125 cpu = <&a53_2>; 126 }; 127 core3 { 128 cpu = <&a53_3>; 129 }; 130 }; 131 }; 132 133 a57_0: cpu@0 { 134 compatible = "arm,cortex-a57"; 135 reg = <0x0>; 136 device_type = "cpu"; 137 power-domains = <&sysc R8A774A1_PD_CA57_CPU0>; 138 next-level-cache = <&L2_CA57>; 139 enable-method = "psci"; 140 dynamic-power-coefficient = <854>; 141 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 142 operating-points-v2 = <&cluster0_opp>; 143 capacity-dmips-mhz = <1024>; 144 #cooling-cells = <2>; 145 }; 146 147 a57_1: cpu@1 { 148 compatible = "arm,cortex-a57"; 149 reg = <0x1>; 150 device_type = "cpu"; 151 power-domains = <&sysc R8A774A1_PD_CA57_CPU1>; 152 next-level-cache = <&L2_CA57>; 153 enable-method = "psci"; 154 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; 155 operating-points-v2 = <&cluster0_opp>; 156 capacity-dmips-mhz = <1024>; 157 #cooling-cells = <2>; 158 }; 159 160 a53_0: cpu@100 { 161 compatible = "arm,cortex-a53"; 162 reg = <0x100>; 163 device_type = "cpu"; 164 power-domains = <&sysc R8A774A1_PD_CA53_CPU0>; 165 next-level-cache = <&L2_CA53>; 166 enable-method = "psci"; 167 #cooling-cells = <2>; 168 dynamic-power-coefficient = <277>; 169 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 170 operating-points-v2 = <&cluster1_opp>; 171 capacity-dmips-mhz = <560>; 172 }; 173 174 a53_1: cpu@101 { 175 compatible = "arm,cortex-a53"; 176 reg = <0x101>; 177 device_type = "cpu"; 178 power-domains = <&sysc R8A774A1_PD_CA53_CPU1>; 179 next-level-cache = <&L2_CA53>; 180 enable-method = "psci"; 181 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 182 operating-points-v2 = <&cluster1_opp>; 183 capacity-dmips-mhz = <560>; 184 }; 185 186 a53_2: cpu@102 { 187 compatible = "arm,cortex-a53"; 188 reg = <0x102>; 189 device_type = "cpu"; 190 power-domains = <&sysc R8A774A1_PD_CA53_CPU2>; 191 next-level-cache = <&L2_CA53>; 192 enable-method = "psci"; 193 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 194 operating-points-v2 = <&cluster1_opp>; 195 capacity-dmips-mhz = <560>; 196 }; 197 198 a53_3: cpu@103 { 199 compatible = "arm,cortex-a53"; 200 reg = <0x103>; 201 device_type = "cpu"; 202 power-domains = <&sysc R8A774A1_PD_CA53_CPU3>; 203 next-level-cache = <&L2_CA53>; 204 enable-method = "psci"; 205 clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; 206 operating-points-v2 = <&cluster1_opp>; 207 capacity-dmips-mhz = <560>; 208 }; 209 210 L2_CA57: cache-controller-0 { 211 compatible = "cache"; 212 power-domains = <&sysc R8A774A1_PD_CA57_SCU>; 213 cache-unified; 214 cache-level = <2>; 215 }; 216 217 L2_CA53: cache-controller-1 { 218 compatible = "cache"; 219 power-domains = <&sysc R8A774A1_PD_CA53_SCU>; 220 cache-unified; 221 cache-level = <2>; 222 }; 223 }; 224 225 extal_clk: extal { 226 compatible = "fixed-clock"; 227 #clock-cells = <0>; 228 /* This value must be overridden by the board */ 229 clock-frequency = <0>; 230 }; 231 232 extalr_clk: extalr { 233 compatible = "fixed-clock"; 234 #clock-cells = <0>; 235 /* This value must be overridden by the board */ 236 clock-frequency = <0>; 237 }; 238 239 /* External PCIe clock - can be overridden by the board */ 240 pcie_bus_clk: pcie_bus { 241 compatible = "fixed-clock"; 242 #clock-cells = <0>; 243 clock-frequency = <0>; 244 }; 245 246 pmu_a53 { 247 compatible = "arm,cortex-a53-pmu"; 248 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 249 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 250 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 251 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 252 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 253 }; 254 255 pmu_a57 { 256 compatible = "arm,cortex-a57-pmu"; 257 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 258 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 259 interrupt-affinity = <&a57_0>, <&a57_1>; 260 }; 261 262 psci { 263 compatible = "arm,psci-1.0", "arm,psci-0.2"; 264 method = "smc"; 265 }; 266 267 /* External SCIF clock - to be overridden by boards that provide it */ 268 scif_clk: scif { 269 compatible = "fixed-clock"; 270 #clock-cells = <0>; 271 clock-frequency = <0>; 272 }; 273 274 soc { 275 compatible = "simple-bus"; 276 interrupt-parent = <&gic>; 277 #address-cells = <2>; 278 #size-cells = <2>; 279 ranges; 280 281 rwdt: watchdog@e6020000 { 282 compatible = "renesas,r8a774a1-wdt", 283 "renesas,rcar-gen3-wdt"; 284 reg = <0 0xe6020000 0 0x0c>; 285 clocks = <&cpg CPG_MOD 402>; 286 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 287 resets = <&cpg 402>; 288 status = "disabled"; 289 }; 290 291 gpio0: gpio@e6050000 { 292 compatible = "renesas,gpio-r8a774a1", 293 "renesas,rcar-gen3-gpio"; 294 reg = <0 0xe6050000 0 0x50>; 295 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 296 #gpio-cells = <2>; 297 gpio-controller; 298 gpio-ranges = <&pfc 0 0 16>; 299 #interrupt-cells = <2>; 300 interrupt-controller; 301 clocks = <&cpg CPG_MOD 912>; 302 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 303 resets = <&cpg 912>; 304 }; 305 306 gpio1: gpio@e6051000 { 307 compatible = "renesas,gpio-r8a774a1", 308 "renesas,rcar-gen3-gpio"; 309 reg = <0 0xe6051000 0 0x50>; 310 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 311 #gpio-cells = <2>; 312 gpio-controller; 313 gpio-ranges = <&pfc 0 32 29>; 314 #interrupt-cells = <2>; 315 interrupt-controller; 316 clocks = <&cpg CPG_MOD 911>; 317 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 318 resets = <&cpg 911>; 319 }; 320 321 gpio2: gpio@e6052000 { 322 compatible = "renesas,gpio-r8a774a1", 323 "renesas,rcar-gen3-gpio"; 324 reg = <0 0xe6052000 0 0x50>; 325 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 326 #gpio-cells = <2>; 327 gpio-controller; 328 gpio-ranges = <&pfc 0 64 15>; 329 #interrupt-cells = <2>; 330 interrupt-controller; 331 clocks = <&cpg CPG_MOD 910>; 332 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 333 resets = <&cpg 910>; 334 }; 335 336 gpio3: gpio@e6053000 { 337 compatible = "renesas,gpio-r8a774a1", 338 "renesas,rcar-gen3-gpio"; 339 reg = <0 0xe6053000 0 0x50>; 340 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 341 #gpio-cells = <2>; 342 gpio-controller; 343 gpio-ranges = <&pfc 0 96 16>; 344 #interrupt-cells = <2>; 345 interrupt-controller; 346 clocks = <&cpg CPG_MOD 909>; 347 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 348 resets = <&cpg 909>; 349 }; 350 351 gpio4: gpio@e6054000 { 352 compatible = "renesas,gpio-r8a774a1", 353 "renesas,rcar-gen3-gpio"; 354 reg = <0 0xe6054000 0 0x50>; 355 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 356 #gpio-cells = <2>; 357 gpio-controller; 358 gpio-ranges = <&pfc 0 128 18>; 359 #interrupt-cells = <2>; 360 interrupt-controller; 361 clocks = <&cpg CPG_MOD 908>; 362 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 363 resets = <&cpg 908>; 364 }; 365 366 gpio5: gpio@e6055000 { 367 compatible = "renesas,gpio-r8a774a1", 368 "renesas,rcar-gen3-gpio"; 369 reg = <0 0xe6055000 0 0x50>; 370 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 371 #gpio-cells = <2>; 372 gpio-controller; 373 gpio-ranges = <&pfc 0 160 26>; 374 #interrupt-cells = <2>; 375 interrupt-controller; 376 clocks = <&cpg CPG_MOD 907>; 377 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 378 resets = <&cpg 907>; 379 }; 380 381 gpio6: gpio@e6055400 { 382 compatible = "renesas,gpio-r8a774a1", 383 "renesas,rcar-gen3-gpio"; 384 reg = <0 0xe6055400 0 0x50>; 385 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 386 #gpio-cells = <2>; 387 gpio-controller; 388 gpio-ranges = <&pfc 0 192 32>; 389 #interrupt-cells = <2>; 390 interrupt-controller; 391 clocks = <&cpg CPG_MOD 906>; 392 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 393 resets = <&cpg 906>; 394 }; 395 396 gpio7: gpio@e6055800 { 397 compatible = "renesas,gpio-r8a774a1", 398 "renesas,rcar-gen3-gpio"; 399 reg = <0 0xe6055800 0 0x50>; 400 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 401 #gpio-cells = <2>; 402 gpio-controller; 403 gpio-ranges = <&pfc 0 224 4>; 404 #interrupt-cells = <2>; 405 interrupt-controller; 406 clocks = <&cpg CPG_MOD 905>; 407 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 408 resets = <&cpg 905>; 409 }; 410 411 pfc: pinctrl@e6060000 { 412 compatible = "renesas,pfc-r8a774a1"; 413 reg = <0 0xe6060000 0 0x50c>; 414 }; 415 416 cmt0: timer@e60f0000 { 417 compatible = "renesas,r8a774a1-cmt0", 418 "renesas,rcar-gen3-cmt0"; 419 reg = <0 0xe60f0000 0 0x1004>; 420 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&cpg CPG_MOD 303>; 423 clock-names = "fck"; 424 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 425 resets = <&cpg 303>; 426 status = "disabled"; 427 }; 428 429 cmt1: timer@e6130000 { 430 compatible = "renesas,r8a774a1-cmt1", 431 "renesas,rcar-gen3-cmt1"; 432 reg = <0 0xe6130000 0 0x1004>; 433 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&cpg CPG_MOD 302>; 442 clock-names = "fck"; 443 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 444 resets = <&cpg 302>; 445 status = "disabled"; 446 }; 447 448 cmt2: timer@e6140000 { 449 compatible = "renesas,r8a774a1-cmt1", 450 "renesas,rcar-gen3-cmt1"; 451 reg = <0 0xe6140000 0 0x1004>; 452 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&cpg CPG_MOD 301>; 461 clock-names = "fck"; 462 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 463 resets = <&cpg 301>; 464 status = "disabled"; 465 }; 466 467 cmt3: timer@e6148000 { 468 compatible = "renesas,r8a774a1-cmt1", 469 "renesas,rcar-gen3-cmt1"; 470 reg = <0 0xe6148000 0 0x1004>; 471 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&cpg CPG_MOD 300>; 480 clock-names = "fck"; 481 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 482 resets = <&cpg 300>; 483 status = "disabled"; 484 }; 485 486 cpg: clock-controller@e6150000 { 487 compatible = "renesas,r8a774a1-cpg-mssr"; 488 reg = <0 0xe6150000 0 0x0bb0>; 489 clocks = <&extal_clk>, <&extalr_clk>; 490 clock-names = "extal", "extalr"; 491 #clock-cells = <2>; 492 #power-domain-cells = <0>; 493 #reset-cells = <1>; 494 }; 495 496 rst: reset-controller@e6160000 { 497 compatible = "renesas,r8a774a1-rst"; 498 reg = <0 0xe6160000 0 0x018c>; 499 }; 500 501 sysc: system-controller@e6180000 { 502 compatible = "renesas,r8a774a1-sysc"; 503 reg = <0 0xe6180000 0 0x0400>; 504 #power-domain-cells = <1>; 505 }; 506 507 tsc: thermal@e6198000 { 508 compatible = "renesas,r8a774a1-thermal"; 509 reg = <0 0xe6198000 0 0x100>, 510 <0 0xe61a0000 0 0x100>, 511 <0 0xe61a8000 0 0x100>; 512 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&cpg CPG_MOD 522>; 516 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 517 resets = <&cpg 522>; 518 #thermal-sensor-cells = <1>; 519 }; 520 521 intc_ex: interrupt-controller@e61c0000 { 522 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc"; 523 #interrupt-cells = <2>; 524 interrupt-controller; 525 reg = <0 0xe61c0000 0 0x200>; 526 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&cpg CPG_MOD 407>; 533 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 534 resets = <&cpg 407>; 535 }; 536 537 tmu0: timer@e61e0000 { 538 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 539 reg = <0 0xe61e0000 0 0x30>; 540 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&cpg CPG_MOD 125>; 544 clock-names = "fck"; 545 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 546 resets = <&cpg 125>; 547 status = "disabled"; 548 }; 549 550 tmu1: timer@e6fc0000 { 551 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 552 reg = <0 0xe6fc0000 0 0x30>; 553 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&cpg CPG_MOD 124>; 557 clock-names = "fck"; 558 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 559 resets = <&cpg 124>; 560 status = "disabled"; 561 }; 562 563 tmu2: timer@e6fd0000 { 564 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 565 reg = <0 0xe6fd0000 0 0x30>; 566 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&cpg CPG_MOD 123>; 570 clock-names = "fck"; 571 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 572 resets = <&cpg 123>; 573 status = "disabled"; 574 }; 575 576 tmu3: timer@e6fe0000 { 577 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 578 reg = <0 0xe6fe0000 0 0x30>; 579 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&cpg CPG_MOD 122>; 583 clock-names = "fck"; 584 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 585 resets = <&cpg 122>; 586 status = "disabled"; 587 }; 588 589 tmu4: timer@ffc00000 { 590 compatible = "renesas,tmu-r8a774a1", "renesas,tmu"; 591 reg = <0 0xffc00000 0 0x30>; 592 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&cpg CPG_MOD 121>; 596 clock-names = "fck"; 597 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 598 resets = <&cpg 121>; 599 status = "disabled"; 600 }; 601 602 i2c0: i2c@e6500000 { 603 #address-cells = <1>; 604 #size-cells = <0>; 605 compatible = "renesas,i2c-r8a774a1", 606 "renesas,rcar-gen3-i2c"; 607 reg = <0 0xe6500000 0 0x40>; 608 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&cpg CPG_MOD 931>; 610 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 611 resets = <&cpg 931>; 612 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 613 <&dmac2 0x91>, <&dmac2 0x90>; 614 dma-names = "tx", "rx", "tx", "rx"; 615 i2c-scl-internal-delay-ns = <110>; 616 status = "disabled"; 617 }; 618 619 i2c1: i2c@e6508000 { 620 #address-cells = <1>; 621 #size-cells = <0>; 622 compatible = "renesas,i2c-r8a774a1", 623 "renesas,rcar-gen3-i2c"; 624 reg = <0 0xe6508000 0 0x40>; 625 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&cpg CPG_MOD 930>; 627 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 628 resets = <&cpg 930>; 629 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 630 <&dmac2 0x93>, <&dmac2 0x92>; 631 dma-names = "tx", "rx", "tx", "rx"; 632 i2c-scl-internal-delay-ns = <6>; 633 status = "disabled"; 634 }; 635 636 i2c2: i2c@e6510000 { 637 #address-cells = <1>; 638 #size-cells = <0>; 639 compatible = "renesas,i2c-r8a774a1", 640 "renesas,rcar-gen3-i2c"; 641 reg = <0 0xe6510000 0 0x40>; 642 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&cpg CPG_MOD 929>; 644 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 645 resets = <&cpg 929>; 646 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 647 <&dmac2 0x95>, <&dmac2 0x94>; 648 dma-names = "tx", "rx", "tx", "rx"; 649 i2c-scl-internal-delay-ns = <6>; 650 status = "disabled"; 651 }; 652 653 i2c3: i2c@e66d0000 { 654 #address-cells = <1>; 655 #size-cells = <0>; 656 compatible = "renesas,i2c-r8a774a1", 657 "renesas,rcar-gen3-i2c"; 658 reg = <0 0xe66d0000 0 0x40>; 659 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&cpg CPG_MOD 928>; 661 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 662 resets = <&cpg 928>; 663 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 664 dma-names = "tx", "rx"; 665 i2c-scl-internal-delay-ns = <110>; 666 status = "disabled"; 667 }; 668 669 i2c4: i2c@e66d8000 { 670 #address-cells = <1>; 671 #size-cells = <0>; 672 compatible = "renesas,i2c-r8a774a1", 673 "renesas,rcar-gen3-i2c"; 674 reg = <0 0xe66d8000 0 0x40>; 675 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&cpg CPG_MOD 927>; 677 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 678 resets = <&cpg 927>; 679 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 680 dma-names = "tx", "rx"; 681 i2c-scl-internal-delay-ns = <110>; 682 status = "disabled"; 683 }; 684 685 i2c5: i2c@e66e0000 { 686 #address-cells = <1>; 687 #size-cells = <0>; 688 compatible = "renesas,i2c-r8a774a1", 689 "renesas,rcar-gen3-i2c"; 690 reg = <0 0xe66e0000 0 0x40>; 691 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&cpg CPG_MOD 919>; 693 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 694 resets = <&cpg 919>; 695 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 696 dma-names = "tx", "rx"; 697 i2c-scl-internal-delay-ns = <110>; 698 status = "disabled"; 699 }; 700 701 i2c6: i2c@e66e8000 { 702 #address-cells = <1>; 703 #size-cells = <0>; 704 compatible = "renesas,i2c-r8a774a1", 705 "renesas,rcar-gen3-i2c"; 706 reg = <0 0xe66e8000 0 0x40>; 707 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&cpg CPG_MOD 918>; 709 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 710 resets = <&cpg 918>; 711 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 712 dma-names = "tx", "rx"; 713 i2c-scl-internal-delay-ns = <6>; 714 status = "disabled"; 715 }; 716 717 i2c_dvfs: i2c@e60b0000 { 718 #address-cells = <1>; 719 #size-cells = <0>; 720 compatible = "renesas,iic-r8a774a1", 721 "renesas,rcar-gen3-iic", 722 "renesas,rmobile-iic"; 723 reg = <0 0xe60b0000 0 0x425>; 724 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&cpg CPG_MOD 926>; 726 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 727 resets = <&cpg 926>; 728 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 729 dma-names = "tx", "rx"; 730 status = "disabled"; 731 }; 732 733 hscif0: serial@e6540000 { 734 compatible = "renesas,hscif-r8a774a1", 735 "renesas,rcar-gen3-hscif", 736 "renesas,hscif"; 737 reg = <0 0xe6540000 0 0x60>; 738 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&cpg CPG_MOD 520>, 740 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 741 <&scif_clk>; 742 clock-names = "fck", "brg_int", "scif_clk"; 743 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 744 <&dmac2 0x31>, <&dmac2 0x30>; 745 dma-names = "tx", "rx", "tx", "rx"; 746 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 747 resets = <&cpg 520>; 748 status = "disabled"; 749 }; 750 751 hscif1: serial@e6550000 { 752 compatible = "renesas,hscif-r8a774a1", 753 "renesas,rcar-gen3-hscif", 754 "renesas,hscif"; 755 reg = <0 0xe6550000 0 0x60>; 756 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&cpg CPG_MOD 519>, 758 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 759 <&scif_clk>; 760 clock-names = "fck", "brg_int", "scif_clk"; 761 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 762 <&dmac2 0x33>, <&dmac2 0x32>; 763 dma-names = "tx", "rx", "tx", "rx"; 764 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 765 resets = <&cpg 519>; 766 status = "disabled"; 767 }; 768 769 hscif2: serial@e6560000 { 770 compatible = "renesas,hscif-r8a774a1", 771 "renesas,rcar-gen3-hscif", 772 "renesas,hscif"; 773 reg = <0 0xe6560000 0 0x60>; 774 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&cpg CPG_MOD 518>, 776 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 777 <&scif_clk>; 778 clock-names = "fck", "brg_int", "scif_clk"; 779 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 780 <&dmac2 0x35>, <&dmac2 0x34>; 781 dma-names = "tx", "rx", "tx", "rx"; 782 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 783 resets = <&cpg 518>; 784 status = "disabled"; 785 }; 786 787 hscif3: serial@e66a0000 { 788 compatible = "renesas,hscif-r8a774a1", 789 "renesas,rcar-gen3-hscif", 790 "renesas,hscif"; 791 reg = <0 0xe66a0000 0 0x60>; 792 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&cpg CPG_MOD 517>, 794 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 795 <&scif_clk>; 796 clock-names = "fck", "brg_int", "scif_clk"; 797 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 798 dma-names = "tx", "rx"; 799 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 800 resets = <&cpg 517>; 801 status = "disabled"; 802 }; 803 804 hscif4: serial@e66b0000 { 805 compatible = "renesas,hscif-r8a774a1", 806 "renesas,rcar-gen3-hscif", 807 "renesas,hscif"; 808 reg = <0 0xe66b0000 0 0x60>; 809 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&cpg CPG_MOD 516>, 811 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 812 <&scif_clk>; 813 clock-names = "fck", "brg_int", "scif_clk"; 814 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 815 dma-names = "tx", "rx"; 816 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 817 resets = <&cpg 516>; 818 status = "disabled"; 819 }; 820 821 hsusb: usb@e6590000 { 822 compatible = "renesas,usbhs-r8a774a1", 823 "renesas,rcar-gen3-usbhs"; 824 reg = <0 0xe6590000 0 0x200>; 825 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 827 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 828 <&usb_dmac1 0>, <&usb_dmac1 1>; 829 dma-names = "ch0", "ch1", "ch2", "ch3"; 830 renesas,buswait = <11>; 831 phys = <&usb2_phy0 3>; 832 phy-names = "usb"; 833 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 834 resets = <&cpg 704>, <&cpg 703>; 835 status = "disabled"; 836 }; 837 838 usb2_clksel: clock-controller@e6590630 { 839 compatible = "renesas,r8a774a1-rcar-usb2-clock-sel", 840 "renesas,rcar-gen3-usb2-clock-sel"; 841 reg = <0 0xe6590630 0 0x02>; 842 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, 843 <&usb_extal_clk>, <&usb3s0_clk>; 844 clock-names = "ehci_ohci", "hs-usb-if", 845 "usb_extal", "usb_xtal"; 846 #clock-cells = <0>; 847 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 848 resets = <&cpg 703>, <&cpg 704>; 849 reset-names = "ehci_ohci", "hs-usb-if"; 850 status = "disabled"; 851 }; 852 853 usb_dmac0: dma-controller@e65a0000 { 854 compatible = "renesas,r8a774a1-usb-dmac", 855 "renesas,usb-dmac"; 856 reg = <0 0xe65a0000 0 0x100>; 857 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 859 interrupt-names = "ch0", "ch1"; 860 clocks = <&cpg CPG_MOD 330>; 861 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 862 resets = <&cpg 330>; 863 #dma-cells = <1>; 864 dma-channels = <2>; 865 }; 866 867 usb_dmac1: dma-controller@e65b0000 { 868 compatible = "renesas,r8a774a1-usb-dmac", 869 "renesas,usb-dmac"; 870 reg = <0 0xe65b0000 0 0x100>; 871 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 873 interrupt-names = "ch0", "ch1"; 874 clocks = <&cpg CPG_MOD 331>; 875 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 876 resets = <&cpg 331>; 877 #dma-cells = <1>; 878 dma-channels = <2>; 879 }; 880 881 usb3_phy0: usb-phy@e65ee000 { 882 compatible = "renesas,r8a774a1-usb3-phy", 883 "renesas,rcar-gen3-usb3-phy"; 884 reg = <0 0xe65ee000 0 0x90>; 885 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 886 <&usb_extal_clk>; 887 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 888 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 889 resets = <&cpg 328>; 890 #phy-cells = <0>; 891 status = "disabled"; 892 }; 893 894 dmac0: dma-controller@e6700000 { 895 compatible = "renesas,dmac-r8a774a1", 896 "renesas,rcar-dmac"; 897 reg = <0 0xe6700000 0 0x10000>; 898 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 915 interrupt-names = "error", 916 "ch0", "ch1", "ch2", "ch3", 917 "ch4", "ch5", "ch6", "ch7", 918 "ch8", "ch9", "ch10", "ch11", 919 "ch12", "ch13", "ch14", "ch15"; 920 clocks = <&cpg CPG_MOD 219>; 921 clock-names = "fck"; 922 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 923 resets = <&cpg 219>; 924 #dma-cells = <1>; 925 dma-channels = <16>; 926 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 927 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 928 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 929 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 930 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 931 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 932 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 933 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 934 }; 935 936 dmac1: dma-controller@e7300000 { 937 compatible = "renesas,dmac-r8a774a1", 938 "renesas,rcar-dmac"; 939 reg = <0 0xe7300000 0 0x10000>; 940 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 957 interrupt-names = "error", 958 "ch0", "ch1", "ch2", "ch3", 959 "ch4", "ch5", "ch6", "ch7", 960 "ch8", "ch9", "ch10", "ch11", 961 "ch12", "ch13", "ch14", "ch15"; 962 clocks = <&cpg CPG_MOD 218>; 963 clock-names = "fck"; 964 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 965 resets = <&cpg 218>; 966 #dma-cells = <1>; 967 dma-channels = <16>; 968 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 969 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 970 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 971 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 972 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 973 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 974 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 975 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 976 }; 977 978 dmac2: dma-controller@e7310000 { 979 compatible = "renesas,dmac-r8a774a1", 980 "renesas,rcar-dmac"; 981 reg = <0 0xe7310000 0 0x10000>; 982 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 999 interrupt-names = "error", 1000 "ch0", "ch1", "ch2", "ch3", 1001 "ch4", "ch5", "ch6", "ch7", 1002 "ch8", "ch9", "ch10", "ch11", 1003 "ch12", "ch13", "ch14", "ch15"; 1004 clocks = <&cpg CPG_MOD 217>; 1005 clock-names = "fck"; 1006 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1007 resets = <&cpg 217>; 1008 #dma-cells = <1>; 1009 dma-channels = <16>; 1010 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1011 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1012 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1013 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1014 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1015 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1016 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1017 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1018 }; 1019 1020 ipmmu_ds0: iommu@e6740000 { 1021 compatible = "renesas,ipmmu-r8a774a1"; 1022 reg = <0 0xe6740000 0 0x1000>; 1023 renesas,ipmmu-main = <&ipmmu_mm 0>; 1024 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1025 #iommu-cells = <1>; 1026 }; 1027 1028 ipmmu_ds1: iommu@e7740000 { 1029 compatible = "renesas,ipmmu-r8a774a1"; 1030 reg = <0 0xe7740000 0 0x1000>; 1031 renesas,ipmmu-main = <&ipmmu_mm 1>; 1032 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1033 #iommu-cells = <1>; 1034 }; 1035 1036 ipmmu_hc: iommu@e6570000 { 1037 compatible = "renesas,ipmmu-r8a774a1"; 1038 reg = <0 0xe6570000 0 0x1000>; 1039 renesas,ipmmu-main = <&ipmmu_mm 2>; 1040 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1041 #iommu-cells = <1>; 1042 }; 1043 1044 ipmmu_mm: iommu@e67b0000 { 1045 compatible = "renesas,ipmmu-r8a774a1"; 1046 reg = <0 0xe67b0000 0 0x1000>; 1047 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1049 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1050 #iommu-cells = <1>; 1051 }; 1052 1053 ipmmu_mp: iommu@ec670000 { 1054 compatible = "renesas,ipmmu-r8a774a1"; 1055 reg = <0 0xec670000 0 0x1000>; 1056 renesas,ipmmu-main = <&ipmmu_mm 4>; 1057 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1058 #iommu-cells = <1>; 1059 }; 1060 1061 ipmmu_pv0: iommu@fd800000 { 1062 compatible = "renesas,ipmmu-r8a774a1"; 1063 reg = <0 0xfd800000 0 0x1000>; 1064 renesas,ipmmu-main = <&ipmmu_mm 5>; 1065 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1066 #iommu-cells = <1>; 1067 }; 1068 1069 ipmmu_pv1: iommu@fd950000 { 1070 compatible = "renesas,ipmmu-r8a774a1"; 1071 reg = <0 0xfd950000 0 0x1000>; 1072 renesas,ipmmu-main = <&ipmmu_mm 6>; 1073 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1074 #iommu-cells = <1>; 1075 }; 1076 1077 ipmmu_vc0: iommu@fe6b0000 { 1078 compatible = "renesas,ipmmu-r8a774a1"; 1079 reg = <0 0xfe6b0000 0 0x1000>; 1080 renesas,ipmmu-main = <&ipmmu_mm 8>; 1081 power-domains = <&sysc R8A774A1_PD_A3VC>; 1082 #iommu-cells = <1>; 1083 }; 1084 1085 ipmmu_vi0: iommu@febd0000 { 1086 compatible = "renesas,ipmmu-r8a774a1"; 1087 reg = <0 0xfebd0000 0 0x1000>; 1088 renesas,ipmmu-main = <&ipmmu_mm 9>; 1089 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1090 #iommu-cells = <1>; 1091 }; 1092 1093 avb: ethernet@e6800000 { 1094 compatible = "renesas,etheravb-r8a774a1", 1095 "renesas,etheravb-rcar-gen3"; 1096 reg = <0 0xe6800000 0 0x800>; 1097 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1122 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1123 "ch4", "ch5", "ch6", "ch7", 1124 "ch8", "ch9", "ch10", "ch11", 1125 "ch12", "ch13", "ch14", "ch15", 1126 "ch16", "ch17", "ch18", "ch19", 1127 "ch20", "ch21", "ch22", "ch23", 1128 "ch24"; 1129 clocks = <&cpg CPG_MOD 812>; 1130 clock-names = "fck"; 1131 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1132 resets = <&cpg 812>; 1133 phy-mode = "rgmii"; 1134 rx-internal-delay-ps = <0>; 1135 tx-internal-delay-ps = <0>; 1136 iommus = <&ipmmu_ds0 16>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 status = "disabled"; 1140 }; 1141 1142 can0: can@e6c30000 { 1143 compatible = "renesas,can-r8a774a1", 1144 "renesas,rcar-gen3-can"; 1145 reg = <0 0xe6c30000 0 0x1000>; 1146 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1147 clocks = <&cpg CPG_MOD 916>, 1148 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1149 <&can_clk>; 1150 clock-names = "clkp1", "clkp2", "can_clk"; 1151 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1152 assigned-clock-rates = <40000000>; 1153 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1154 resets = <&cpg 916>; 1155 status = "disabled"; 1156 }; 1157 1158 can1: can@e6c38000 { 1159 compatible = "renesas,can-r8a774a1", 1160 "renesas,rcar-gen3-can"; 1161 reg = <0 0xe6c38000 0 0x1000>; 1162 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1163 clocks = <&cpg CPG_MOD 915>, 1164 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1165 <&can_clk>; 1166 clock-names = "clkp1", "clkp2", "can_clk"; 1167 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1168 assigned-clock-rates = <40000000>; 1169 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1170 resets = <&cpg 915>; 1171 status = "disabled"; 1172 }; 1173 1174 canfd: can@e66c0000 { 1175 compatible = "renesas,r8a774a1-canfd", 1176 "renesas,rcar-gen3-canfd"; 1177 reg = <0 0xe66c0000 0 0x8000>; 1178 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1180 clocks = <&cpg CPG_MOD 914>, 1181 <&cpg CPG_CORE R8A774A1_CLK_CANFD>, 1182 <&can_clk>; 1183 clock-names = "fck", "canfd", "can_clk"; 1184 assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; 1185 assigned-clock-rates = <40000000>; 1186 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1187 resets = <&cpg 914>; 1188 status = "disabled"; 1189 1190 channel0 { 1191 status = "disabled"; 1192 }; 1193 1194 channel1 { 1195 status = "disabled"; 1196 }; 1197 }; 1198 1199 pwm0: pwm@e6e30000 { 1200 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1201 reg = <0 0xe6e30000 0 0x8>; 1202 #pwm-cells = <2>; 1203 clocks = <&cpg CPG_MOD 523>; 1204 resets = <&cpg 523>; 1205 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1206 status = "disabled"; 1207 }; 1208 1209 pwm1: pwm@e6e31000 { 1210 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1211 reg = <0 0xe6e31000 0 0x8>; 1212 #pwm-cells = <2>; 1213 clocks = <&cpg CPG_MOD 523>; 1214 resets = <&cpg 523>; 1215 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1216 status = "disabled"; 1217 }; 1218 1219 pwm2: pwm@e6e32000 { 1220 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1221 reg = <0 0xe6e32000 0 0x8>; 1222 #pwm-cells = <2>; 1223 clocks = <&cpg CPG_MOD 523>; 1224 resets = <&cpg 523>; 1225 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1226 status = "disabled"; 1227 }; 1228 1229 pwm3: pwm@e6e33000 { 1230 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1231 reg = <0 0xe6e33000 0 0x8>; 1232 #pwm-cells = <2>; 1233 clocks = <&cpg CPG_MOD 523>; 1234 resets = <&cpg 523>; 1235 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1236 status = "disabled"; 1237 }; 1238 1239 pwm4: pwm@e6e34000 { 1240 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1241 reg = <0 0xe6e34000 0 0x8>; 1242 #pwm-cells = <2>; 1243 clocks = <&cpg CPG_MOD 523>; 1244 resets = <&cpg 523>; 1245 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1246 status = "disabled"; 1247 }; 1248 1249 pwm5: pwm@e6e35000 { 1250 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1251 reg = <0 0xe6e35000 0 0x8>; 1252 #pwm-cells = <2>; 1253 clocks = <&cpg CPG_MOD 523>; 1254 resets = <&cpg 523>; 1255 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1256 status = "disabled"; 1257 }; 1258 1259 pwm6: pwm@e6e36000 { 1260 compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar"; 1261 reg = <0 0xe6e36000 0 0x8>; 1262 #pwm-cells = <2>; 1263 clocks = <&cpg CPG_MOD 523>; 1264 resets = <&cpg 523>; 1265 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1266 status = "disabled"; 1267 }; 1268 1269 scif0: serial@e6e60000 { 1270 compatible = "renesas,scif-r8a774a1", 1271 "renesas,rcar-gen3-scif", "renesas,scif"; 1272 reg = <0 0xe6e60000 0 0x40>; 1273 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1274 clocks = <&cpg CPG_MOD 207>, 1275 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1276 <&scif_clk>; 1277 clock-names = "fck", "brg_int", "scif_clk"; 1278 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1279 <&dmac2 0x51>, <&dmac2 0x50>; 1280 dma-names = "tx", "rx", "tx", "rx"; 1281 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1282 resets = <&cpg 207>; 1283 status = "disabled"; 1284 }; 1285 1286 scif1: serial@e6e68000 { 1287 compatible = "renesas,scif-r8a774a1", 1288 "renesas,rcar-gen3-scif", "renesas,scif"; 1289 reg = <0 0xe6e68000 0 0x40>; 1290 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1291 clocks = <&cpg CPG_MOD 206>, 1292 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1293 <&scif_clk>; 1294 clock-names = "fck", "brg_int", "scif_clk"; 1295 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1296 <&dmac2 0x53>, <&dmac2 0x52>; 1297 dma-names = "tx", "rx", "tx", "rx"; 1298 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1299 resets = <&cpg 206>; 1300 status = "disabled"; 1301 }; 1302 1303 scif2: serial@e6e88000 { 1304 compatible = "renesas,scif-r8a774a1", 1305 "renesas,rcar-gen3-scif", "renesas,scif"; 1306 reg = <0 0xe6e88000 0 0x40>; 1307 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1308 clocks = <&cpg CPG_MOD 310>, 1309 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1310 <&scif_clk>; 1311 clock-names = "fck", "brg_int", "scif_clk"; 1312 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1313 <&dmac2 0x13>, <&dmac2 0x12>; 1314 dma-names = "tx", "rx", "tx", "rx"; 1315 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1316 resets = <&cpg 310>; 1317 status = "disabled"; 1318 }; 1319 1320 scif3: serial@e6c50000 { 1321 compatible = "renesas,scif-r8a774a1", 1322 "renesas,rcar-gen3-scif", "renesas,scif"; 1323 reg = <0 0xe6c50000 0 0x40>; 1324 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1325 clocks = <&cpg CPG_MOD 204>, 1326 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1327 <&scif_clk>; 1328 clock-names = "fck", "brg_int", "scif_clk"; 1329 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1330 dma-names = "tx", "rx"; 1331 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1332 resets = <&cpg 204>; 1333 status = "disabled"; 1334 }; 1335 1336 scif4: serial@e6c40000 { 1337 compatible = "renesas,scif-r8a774a1", 1338 "renesas,rcar-gen3-scif", "renesas,scif"; 1339 reg = <0 0xe6c40000 0 0x40>; 1340 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1341 clocks = <&cpg CPG_MOD 203>, 1342 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1343 <&scif_clk>; 1344 clock-names = "fck", "brg_int", "scif_clk"; 1345 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1346 dma-names = "tx", "rx"; 1347 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1348 resets = <&cpg 203>; 1349 status = "disabled"; 1350 }; 1351 1352 scif5: serial@e6f30000 { 1353 compatible = "renesas,scif-r8a774a1", 1354 "renesas,rcar-gen3-scif", "renesas,scif"; 1355 reg = <0 0xe6f30000 0 0x40>; 1356 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1357 clocks = <&cpg CPG_MOD 202>, 1358 <&cpg CPG_CORE R8A774A1_CLK_S3D1>, 1359 <&scif_clk>; 1360 clock-names = "fck", "brg_int", "scif_clk"; 1361 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1362 <&dmac2 0x5b>, <&dmac2 0x5a>; 1363 dma-names = "tx", "rx", "tx", "rx"; 1364 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1365 resets = <&cpg 202>; 1366 status = "disabled"; 1367 }; 1368 1369 msiof0: spi@e6e90000 { 1370 compatible = "renesas,msiof-r8a774a1", 1371 "renesas,rcar-gen3-msiof"; 1372 reg = <0 0xe6e90000 0 0x0064>; 1373 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1374 clocks = <&cpg CPG_MOD 211>; 1375 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1376 <&dmac2 0x41>, <&dmac2 0x40>; 1377 dma-names = "tx", "rx", "tx", "rx"; 1378 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1379 resets = <&cpg 211>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 status = "disabled"; 1383 }; 1384 1385 msiof1: spi@e6ea0000 { 1386 compatible = "renesas,msiof-r8a774a1", 1387 "renesas,rcar-gen3-msiof"; 1388 reg = <0 0xe6ea0000 0 0x0064>; 1389 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1390 clocks = <&cpg CPG_MOD 210>; 1391 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1392 <&dmac2 0x43>, <&dmac2 0x42>; 1393 dma-names = "tx", "rx", "tx", "rx"; 1394 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1395 resets = <&cpg 210>; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 status = "disabled"; 1399 }; 1400 1401 msiof2: spi@e6c00000 { 1402 compatible = "renesas,msiof-r8a774a1", 1403 "renesas,rcar-gen3-msiof"; 1404 reg = <0 0xe6c00000 0 0x0064>; 1405 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1406 clocks = <&cpg CPG_MOD 209>; 1407 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1408 dma-names = "tx", "rx"; 1409 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1410 resets = <&cpg 209>; 1411 #address-cells = <1>; 1412 #size-cells = <0>; 1413 status = "disabled"; 1414 }; 1415 1416 msiof3: spi@e6c10000 { 1417 compatible = "renesas,msiof-r8a774a1", 1418 "renesas,rcar-gen3-msiof"; 1419 reg = <0 0xe6c10000 0 0x0064>; 1420 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1421 clocks = <&cpg CPG_MOD 208>; 1422 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1423 dma-names = "tx", "rx"; 1424 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1425 resets = <&cpg 208>; 1426 #address-cells = <1>; 1427 #size-cells = <0>; 1428 status = "disabled"; 1429 }; 1430 1431 vin0: video@e6ef0000 { 1432 compatible = "renesas,vin-r8a774a1"; 1433 reg = <0 0xe6ef0000 0 0x1000>; 1434 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1435 clocks = <&cpg CPG_MOD 811>; 1436 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1437 resets = <&cpg 811>; 1438 renesas,id = <0>; 1439 status = "disabled"; 1440 1441 ports { 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 1445 port@1 { 1446 #address-cells = <1>; 1447 #size-cells = <0>; 1448 1449 reg = <1>; 1450 1451 vin0csi20: endpoint@0 { 1452 reg = <0>; 1453 remote-endpoint = <&csi20vin0>; 1454 }; 1455 vin0csi40: endpoint@2 { 1456 reg = <2>; 1457 remote-endpoint = <&csi40vin0>; 1458 }; 1459 }; 1460 }; 1461 }; 1462 1463 vin1: video@e6ef1000 { 1464 compatible = "renesas,vin-r8a774a1"; 1465 reg = <0 0xe6ef1000 0 0x1000>; 1466 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1467 clocks = <&cpg CPG_MOD 810>; 1468 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1469 resets = <&cpg 810>; 1470 renesas,id = <1>; 1471 status = "disabled"; 1472 1473 ports { 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 1477 port@1 { 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 1481 reg = <1>; 1482 1483 vin1csi20: endpoint@0 { 1484 reg = <0>; 1485 remote-endpoint = <&csi20vin1>; 1486 }; 1487 vin1csi40: endpoint@2 { 1488 reg = <2>; 1489 remote-endpoint = <&csi40vin1>; 1490 }; 1491 }; 1492 }; 1493 }; 1494 1495 vin2: video@e6ef2000 { 1496 compatible = "renesas,vin-r8a774a1"; 1497 reg = <0 0xe6ef2000 0 0x1000>; 1498 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1499 clocks = <&cpg CPG_MOD 809>; 1500 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1501 resets = <&cpg 809>; 1502 renesas,id = <2>; 1503 status = "disabled"; 1504 1505 ports { 1506 #address-cells = <1>; 1507 #size-cells = <0>; 1508 1509 port@1 { 1510 #address-cells = <1>; 1511 #size-cells = <0>; 1512 1513 reg = <1>; 1514 1515 vin2csi20: endpoint@0 { 1516 reg = <0>; 1517 remote-endpoint = <&csi20vin2>; 1518 }; 1519 vin2csi40: endpoint@2 { 1520 reg = <2>; 1521 remote-endpoint = <&csi40vin2>; 1522 }; 1523 }; 1524 }; 1525 }; 1526 1527 vin3: video@e6ef3000 { 1528 compatible = "renesas,vin-r8a774a1"; 1529 reg = <0 0xe6ef3000 0 0x1000>; 1530 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1531 clocks = <&cpg CPG_MOD 808>; 1532 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1533 resets = <&cpg 808>; 1534 renesas,id = <3>; 1535 status = "disabled"; 1536 1537 ports { 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 1541 port@1 { 1542 #address-cells = <1>; 1543 #size-cells = <0>; 1544 1545 reg = <1>; 1546 1547 vin3csi20: endpoint@0 { 1548 reg = <0>; 1549 remote-endpoint = <&csi20vin3>; 1550 }; 1551 vin3csi40: endpoint@2 { 1552 reg = <2>; 1553 remote-endpoint = <&csi40vin3>; 1554 }; 1555 }; 1556 }; 1557 }; 1558 1559 vin4: video@e6ef4000 { 1560 compatible = "renesas,vin-r8a774a1"; 1561 reg = <0 0xe6ef4000 0 0x1000>; 1562 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1563 clocks = <&cpg CPG_MOD 807>; 1564 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1565 resets = <&cpg 807>; 1566 renesas,id = <4>; 1567 status = "disabled"; 1568 1569 ports { 1570 #address-cells = <1>; 1571 #size-cells = <0>; 1572 1573 port@1 { 1574 #address-cells = <1>; 1575 #size-cells = <0>; 1576 1577 reg = <1>; 1578 1579 vin4csi20: endpoint@0 { 1580 reg = <0>; 1581 remote-endpoint = <&csi20vin4>; 1582 }; 1583 vin4csi40: endpoint@2 { 1584 reg = <2>; 1585 remote-endpoint = <&csi40vin4>; 1586 }; 1587 }; 1588 }; 1589 }; 1590 1591 vin5: video@e6ef5000 { 1592 compatible = "renesas,vin-r8a774a1"; 1593 reg = <0 0xe6ef5000 0 0x1000>; 1594 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1595 clocks = <&cpg CPG_MOD 806>; 1596 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1597 resets = <&cpg 806>; 1598 renesas,id = <5>; 1599 status = "disabled"; 1600 1601 ports { 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 1605 port@1 { 1606 #address-cells = <1>; 1607 #size-cells = <0>; 1608 1609 reg = <1>; 1610 1611 vin5csi20: endpoint@0 { 1612 reg = <0>; 1613 remote-endpoint = <&csi20vin5>; 1614 }; 1615 vin5csi40: endpoint@2 { 1616 reg = <2>; 1617 remote-endpoint = <&csi40vin5>; 1618 }; 1619 }; 1620 }; 1621 }; 1622 1623 vin6: video@e6ef6000 { 1624 compatible = "renesas,vin-r8a774a1"; 1625 reg = <0 0xe6ef6000 0 0x1000>; 1626 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1627 clocks = <&cpg CPG_MOD 805>; 1628 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1629 resets = <&cpg 805>; 1630 renesas,id = <6>; 1631 status = "disabled"; 1632 1633 ports { 1634 #address-cells = <1>; 1635 #size-cells = <0>; 1636 1637 port@1 { 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 1641 reg = <1>; 1642 1643 vin6csi20: endpoint@0 { 1644 reg = <0>; 1645 remote-endpoint = <&csi20vin6>; 1646 }; 1647 vin6csi40: endpoint@2 { 1648 reg = <2>; 1649 remote-endpoint = <&csi40vin6>; 1650 }; 1651 }; 1652 }; 1653 }; 1654 1655 vin7: video@e6ef7000 { 1656 compatible = "renesas,vin-r8a774a1"; 1657 reg = <0 0xe6ef7000 0 0x1000>; 1658 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1659 clocks = <&cpg CPG_MOD 804>; 1660 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1661 resets = <&cpg 804>; 1662 renesas,id = <7>; 1663 status = "disabled"; 1664 1665 ports { 1666 #address-cells = <1>; 1667 #size-cells = <0>; 1668 1669 port@1 { 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 1673 reg = <1>; 1674 1675 vin7csi20: endpoint@0 { 1676 reg = <0>; 1677 remote-endpoint = <&csi20vin7>; 1678 }; 1679 vin7csi40: endpoint@2 { 1680 reg = <2>; 1681 remote-endpoint = <&csi40vin7>; 1682 }; 1683 }; 1684 }; 1685 }; 1686 1687 rcar_sound: sound@ec500000 { 1688 /* 1689 * #sound-dai-cells is required 1690 * 1691 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1692 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1693 */ 1694 /* 1695 * #clock-cells is required for audio_clkout0/1/2/3 1696 * 1697 * clkout : #clock-cells = <0>; <&rcar_sound>; 1698 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1699 */ 1700 compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; 1701 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1702 <0 0xec5a0000 0 0x100>, /* ADG */ 1703 <0 0xec540000 0 0x1000>, /* SSIU */ 1704 <0 0xec541000 0 0x280>, /* SSI */ 1705 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1706 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1707 1708 clocks = <&cpg CPG_MOD 1005>, 1709 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1710 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1711 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1712 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1713 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1714 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1715 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1716 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1717 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1718 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1719 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1720 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1721 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1722 <&audio_clk_a>, <&audio_clk_b>, 1723 <&audio_clk_c>, 1724 <&cpg CPG_CORE R8A774A1_CLK_S0D4>; 1725 clock-names = "ssi-all", 1726 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1727 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1728 "ssi.1", "ssi.0", 1729 "src.9", "src.8", "src.7", "src.6", 1730 "src.5", "src.4", "src.3", "src.2", 1731 "src.1", "src.0", 1732 "mix.1", "mix.0", 1733 "ctu.1", "ctu.0", 1734 "dvc.0", "dvc.1", 1735 "clk_a", "clk_b", "clk_c", "clk_i"; 1736 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 1737 resets = <&cpg 1005>, 1738 <&cpg 1006>, <&cpg 1007>, 1739 <&cpg 1008>, <&cpg 1009>, 1740 <&cpg 1010>, <&cpg 1011>, 1741 <&cpg 1012>, <&cpg 1013>, 1742 <&cpg 1014>, <&cpg 1015>; 1743 reset-names = "ssi-all", 1744 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1745 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1746 "ssi.1", "ssi.0"; 1747 status = "disabled"; 1748 1749 rcar_sound,ctu { 1750 ctu00: ctu-0 { }; 1751 ctu01: ctu-1 { }; 1752 ctu02: ctu-2 { }; 1753 ctu03: ctu-3 { }; 1754 ctu10: ctu-4 { }; 1755 ctu11: ctu-5 { }; 1756 ctu12: ctu-6 { }; 1757 ctu13: ctu-7 { }; 1758 }; 1759 1760 rcar_sound,dvc { 1761 dvc0: dvc-0 { 1762 dmas = <&audma1 0xbc>; 1763 dma-names = "tx"; 1764 }; 1765 dvc1: dvc-1 { 1766 dmas = <&audma1 0xbe>; 1767 dma-names = "tx"; 1768 }; 1769 }; 1770 1771 rcar_sound,mix { 1772 mix0: mix-0 { }; 1773 mix1: mix-1 { }; 1774 }; 1775 1776 rcar_sound,src { 1777 src0: src-0 { 1778 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1779 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1780 dma-names = "rx", "tx"; 1781 }; 1782 src1: src-1 { 1783 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1784 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1785 dma-names = "rx", "tx"; 1786 }; 1787 src2: src-2 { 1788 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1789 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1790 dma-names = "rx", "tx"; 1791 }; 1792 src3: src-3 { 1793 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1794 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1795 dma-names = "rx", "tx"; 1796 }; 1797 src4: src-4 { 1798 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1799 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1800 dma-names = "rx", "tx"; 1801 }; 1802 src5: src-5 { 1803 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1804 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1805 dma-names = "rx", "tx"; 1806 }; 1807 src6: src-6 { 1808 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1809 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1810 dma-names = "rx", "tx"; 1811 }; 1812 src7: src-7 { 1813 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1814 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1815 dma-names = "rx", "tx"; 1816 }; 1817 src8: src-8 { 1818 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1819 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1820 dma-names = "rx", "tx"; 1821 }; 1822 src9: src-9 { 1823 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1824 dmas = <&audma0 0x97>, <&audma1 0xba>; 1825 dma-names = "rx", "tx"; 1826 }; 1827 }; 1828 1829 rcar_sound,ssi { 1830 ssi0: ssi-0 { 1831 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1832 dmas = <&audma0 0x01>, <&audma1 0x02>; 1833 dma-names = "rx", "tx"; 1834 }; 1835 ssi1: ssi-1 { 1836 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1837 dmas = <&audma0 0x03>, <&audma1 0x04>; 1838 dma-names = "rx", "tx"; 1839 }; 1840 ssi2: ssi-2 { 1841 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1842 dmas = <&audma0 0x05>, <&audma1 0x06>; 1843 dma-names = "rx", "tx"; 1844 }; 1845 ssi3: ssi-3 { 1846 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1847 dmas = <&audma0 0x07>, <&audma1 0x08>; 1848 dma-names = "rx", "tx"; 1849 }; 1850 ssi4: ssi-4 { 1851 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1852 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1853 dma-names = "rx", "tx"; 1854 }; 1855 ssi5: ssi-5 { 1856 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1857 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1858 dma-names = "rx", "tx"; 1859 }; 1860 ssi6: ssi-6 { 1861 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1862 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1863 dma-names = "rx", "tx"; 1864 }; 1865 ssi7: ssi-7 { 1866 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1867 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1868 dma-names = "rx", "tx"; 1869 }; 1870 ssi8: ssi-8 { 1871 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1872 dmas = <&audma0 0x11>, <&audma1 0x12>; 1873 dma-names = "rx", "tx"; 1874 }; 1875 ssi9: ssi-9 { 1876 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1877 dmas = <&audma0 0x13>, <&audma1 0x14>; 1878 dma-names = "rx", "tx"; 1879 }; 1880 }; 1881 1882 rcar_sound,ssiu { 1883 ssiu00: ssiu-0 { 1884 dmas = <&audma0 0x15>, <&audma1 0x16>; 1885 dma-names = "rx", "tx"; 1886 }; 1887 ssiu01: ssiu-1 { 1888 dmas = <&audma0 0x35>, <&audma1 0x36>; 1889 dma-names = "rx", "tx"; 1890 }; 1891 ssiu02: ssiu-2 { 1892 dmas = <&audma0 0x37>, <&audma1 0x38>; 1893 dma-names = "rx", "tx"; 1894 }; 1895 ssiu03: ssiu-3 { 1896 dmas = <&audma0 0x47>, <&audma1 0x48>; 1897 dma-names = "rx", "tx"; 1898 }; 1899 ssiu04: ssiu-4 { 1900 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1901 dma-names = "rx", "tx"; 1902 }; 1903 ssiu05: ssiu-5 { 1904 dmas = <&audma0 0x43>, <&audma1 0x44>; 1905 dma-names = "rx", "tx"; 1906 }; 1907 ssiu06: ssiu-6 { 1908 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1909 dma-names = "rx", "tx"; 1910 }; 1911 ssiu07: ssiu-7 { 1912 dmas = <&audma0 0x53>, <&audma1 0x54>; 1913 dma-names = "rx", "tx"; 1914 }; 1915 ssiu10: ssiu-8 { 1916 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1917 dma-names = "rx", "tx"; 1918 }; 1919 ssiu11: ssiu-9 { 1920 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1921 dma-names = "rx", "tx"; 1922 }; 1923 ssiu12: ssiu-10 { 1924 dmas = <&audma0 0x57>, <&audma1 0x58>; 1925 dma-names = "rx", "tx"; 1926 }; 1927 ssiu13: ssiu-11 { 1928 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1929 dma-names = "rx", "tx"; 1930 }; 1931 ssiu14: ssiu-12 { 1932 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1933 dma-names = "rx", "tx"; 1934 }; 1935 ssiu15: ssiu-13 { 1936 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1937 dma-names = "rx", "tx"; 1938 }; 1939 ssiu16: ssiu-14 { 1940 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1941 dma-names = "rx", "tx"; 1942 }; 1943 ssiu17: ssiu-15 { 1944 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1945 dma-names = "rx", "tx"; 1946 }; 1947 ssiu20: ssiu-16 { 1948 dmas = <&audma0 0x63>, <&audma1 0x64>; 1949 dma-names = "rx", "tx"; 1950 }; 1951 ssiu21: ssiu-17 { 1952 dmas = <&audma0 0x67>, <&audma1 0x68>; 1953 dma-names = "rx", "tx"; 1954 }; 1955 ssiu22: ssiu-18 { 1956 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1957 dma-names = "rx", "tx"; 1958 }; 1959 ssiu23: ssiu-19 { 1960 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1961 dma-names = "rx", "tx"; 1962 }; 1963 ssiu24: ssiu-20 { 1964 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1965 dma-names = "rx", "tx"; 1966 }; 1967 ssiu25: ssiu-21 { 1968 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1969 dma-names = "rx", "tx"; 1970 }; 1971 ssiu26: ssiu-22 { 1972 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1973 dma-names = "rx", "tx"; 1974 }; 1975 ssiu27: ssiu-23 { 1976 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1977 dma-names = "rx", "tx"; 1978 }; 1979 ssiu30: ssiu-24 { 1980 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1981 dma-names = "rx", "tx"; 1982 }; 1983 ssiu31: ssiu-25 { 1984 dmas = <&audma0 0x21>, <&audma1 0x22>; 1985 dma-names = "rx", "tx"; 1986 }; 1987 ssiu32: ssiu-26 { 1988 dmas = <&audma0 0x23>, <&audma1 0x24>; 1989 dma-names = "rx", "tx"; 1990 }; 1991 ssiu33: ssiu-27 { 1992 dmas = <&audma0 0x25>, <&audma1 0x26>; 1993 dma-names = "rx", "tx"; 1994 }; 1995 ssiu34: ssiu-28 { 1996 dmas = <&audma0 0x27>, <&audma1 0x28>; 1997 dma-names = "rx", "tx"; 1998 }; 1999 ssiu35: ssiu-29 { 2000 dmas = <&audma0 0x29>, <&audma1 0x2A>; 2001 dma-names = "rx", "tx"; 2002 }; 2003 ssiu36: ssiu-30 { 2004 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 2005 dma-names = "rx", "tx"; 2006 }; 2007 ssiu37: ssiu-31 { 2008 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 2009 dma-names = "rx", "tx"; 2010 }; 2011 ssiu40: ssiu-32 { 2012 dmas = <&audma0 0x71>, <&audma1 0x72>; 2013 dma-names = "rx", "tx"; 2014 }; 2015 ssiu41: ssiu-33 { 2016 dmas = <&audma0 0x17>, <&audma1 0x18>; 2017 dma-names = "rx", "tx"; 2018 }; 2019 ssiu42: ssiu-34 { 2020 dmas = <&audma0 0x19>, <&audma1 0x1A>; 2021 dma-names = "rx", "tx"; 2022 }; 2023 ssiu43: ssiu-35 { 2024 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 2025 dma-names = "rx", "tx"; 2026 }; 2027 ssiu44: ssiu-36 { 2028 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 2029 dma-names = "rx", "tx"; 2030 }; 2031 ssiu45: ssiu-37 { 2032 dmas = <&audma0 0x1F>, <&audma1 0x20>; 2033 dma-names = "rx", "tx"; 2034 }; 2035 ssiu46: ssiu-38 { 2036 dmas = <&audma0 0x31>, <&audma1 0x32>; 2037 dma-names = "rx", "tx"; 2038 }; 2039 ssiu47: ssiu-39 { 2040 dmas = <&audma0 0x33>, <&audma1 0x34>; 2041 dma-names = "rx", "tx"; 2042 }; 2043 ssiu50: ssiu-40 { 2044 dmas = <&audma0 0x73>, <&audma1 0x74>; 2045 dma-names = "rx", "tx"; 2046 }; 2047 ssiu60: ssiu-41 { 2048 dmas = <&audma0 0x75>, <&audma1 0x76>; 2049 dma-names = "rx", "tx"; 2050 }; 2051 ssiu70: ssiu-42 { 2052 dmas = <&audma0 0x79>, <&audma1 0x7a>; 2053 dma-names = "rx", "tx"; 2054 }; 2055 ssiu80: ssiu-43 { 2056 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 2057 dma-names = "rx", "tx"; 2058 }; 2059 ssiu90: ssiu-44 { 2060 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 2061 dma-names = "rx", "tx"; 2062 }; 2063 ssiu91: ssiu-45 { 2064 dmas = <&audma0 0x7F>, <&audma1 0x80>; 2065 dma-names = "rx", "tx"; 2066 }; 2067 ssiu92: ssiu-46 { 2068 dmas = <&audma0 0x81>, <&audma1 0x82>; 2069 dma-names = "rx", "tx"; 2070 }; 2071 ssiu93: ssiu-47 { 2072 dmas = <&audma0 0x83>, <&audma1 0x84>; 2073 dma-names = "rx", "tx"; 2074 }; 2075 ssiu94: ssiu-48 { 2076 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 2077 dma-names = "rx", "tx"; 2078 }; 2079 ssiu95: ssiu-49 { 2080 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 2081 dma-names = "rx", "tx"; 2082 }; 2083 ssiu96: ssiu-50 { 2084 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2085 dma-names = "rx", "tx"; 2086 }; 2087 ssiu97: ssiu-51 { 2088 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2089 dma-names = "rx", "tx"; 2090 }; 2091 }; 2092 }; 2093 2094 audma0: dma-controller@ec700000 { 2095 compatible = "renesas,dmac-r8a774a1", 2096 "renesas,rcar-dmac"; 2097 reg = <0 0xec700000 0 0x10000>; 2098 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2115 interrupt-names = "error", 2116 "ch0", "ch1", "ch2", "ch3", 2117 "ch4", "ch5", "ch6", "ch7", 2118 "ch8", "ch9", "ch10", "ch11", 2119 "ch12", "ch13", "ch14", "ch15"; 2120 clocks = <&cpg CPG_MOD 502>; 2121 clock-names = "fck"; 2122 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2123 resets = <&cpg 502>; 2124 #dma-cells = <1>; 2125 dma-channels = <16>; 2126 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 2127 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 2128 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 2129 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 2130 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 2131 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 2132 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 2133 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 2134 }; 2135 2136 audma1: dma-controller@ec720000 { 2137 compatible = "renesas,dmac-r8a774a1", 2138 "renesas,rcar-dmac"; 2139 reg = <0 0xec720000 0 0x10000>; 2140 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2157 interrupt-names = "error", 2158 "ch0", "ch1", "ch2", "ch3", 2159 "ch4", "ch5", "ch6", "ch7", 2160 "ch8", "ch9", "ch10", "ch11", 2161 "ch12", "ch13", "ch14", "ch15"; 2162 clocks = <&cpg CPG_MOD 501>; 2163 clock-names = "fck"; 2164 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2165 resets = <&cpg 501>; 2166 #dma-cells = <1>; 2167 dma-channels = <16>; 2168 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 2169 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 2170 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 2171 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 2172 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 2173 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 2174 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 2175 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 2176 }; 2177 2178 xhci0: usb@ee000000 { 2179 compatible = "renesas,xhci-r8a774a1", 2180 "renesas,rcar-gen3-xhci"; 2181 reg = <0 0xee000000 0 0xc00>; 2182 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2183 clocks = <&cpg CPG_MOD 328>; 2184 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2185 resets = <&cpg 328>; 2186 status = "disabled"; 2187 }; 2188 2189 usb3_peri0: usb@ee020000 { 2190 compatible = "renesas,r8a774a1-usb3-peri", 2191 "renesas,rcar-gen3-usb3-peri"; 2192 reg = <0 0xee020000 0 0x400>; 2193 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2194 clocks = <&cpg CPG_MOD 328>; 2195 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2196 resets = <&cpg 328>; 2197 status = "disabled"; 2198 }; 2199 2200 ohci0: usb@ee080000 { 2201 compatible = "generic-ohci"; 2202 reg = <0 0xee080000 0 0x100>; 2203 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2204 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2205 phys = <&usb2_phy0 1>; 2206 phy-names = "usb"; 2207 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2208 resets = <&cpg 703>, <&cpg 704>; 2209 status = "disabled"; 2210 }; 2211 2212 ohci1: usb@ee0a0000 { 2213 compatible = "generic-ohci"; 2214 reg = <0 0xee0a0000 0 0x100>; 2215 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2216 clocks = <&cpg CPG_MOD 702>; 2217 phys = <&usb2_phy1 1>; 2218 phy-names = "usb"; 2219 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2220 resets = <&cpg 702>; 2221 status = "disabled"; 2222 }; 2223 2224 ehci0: usb@ee080100 { 2225 compatible = "generic-ehci"; 2226 reg = <0 0xee080100 0 0x100>; 2227 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2228 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2229 phys = <&usb2_phy0 2>; 2230 phy-names = "usb"; 2231 companion = <&ohci0>; 2232 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2233 resets = <&cpg 703>, <&cpg 704>; 2234 status = "disabled"; 2235 }; 2236 2237 ehci1: usb@ee0a0100 { 2238 compatible = "generic-ehci"; 2239 reg = <0 0xee0a0100 0 0x100>; 2240 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2241 clocks = <&cpg CPG_MOD 702>; 2242 phys = <&usb2_phy1 2>; 2243 phy-names = "usb"; 2244 companion = <&ohci1>; 2245 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2246 resets = <&cpg 702>; 2247 status = "disabled"; 2248 }; 2249 2250 usb2_phy0: usb-phy@ee080200 { 2251 compatible = "renesas,usb2-phy-r8a774a1", 2252 "renesas,rcar-gen3-usb2-phy"; 2253 reg = <0 0xee080200 0 0x700>; 2254 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2255 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2256 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2257 resets = <&cpg 703>, <&cpg 704>; 2258 #phy-cells = <1>; 2259 status = "disabled"; 2260 }; 2261 2262 usb2_phy1: usb-phy@ee0a0200 { 2263 compatible = "renesas,usb2-phy-r8a774a1", 2264 "renesas,rcar-gen3-usb2-phy"; 2265 reg = <0 0xee0a0200 0 0x700>; 2266 clocks = <&cpg CPG_MOD 702>; 2267 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2268 resets = <&cpg 702>; 2269 #phy-cells = <1>; 2270 status = "disabled"; 2271 }; 2272 2273 sdhi0: mmc@ee100000 { 2274 compatible = "renesas,sdhi-r8a774a1", 2275 "renesas,rcar-gen3-sdhi"; 2276 reg = <0 0xee100000 0 0x2000>; 2277 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2278 clocks = <&cpg CPG_MOD 314>; 2279 max-frequency = <200000000>; 2280 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2281 resets = <&cpg 314>; 2282 status = "disabled"; 2283 }; 2284 2285 sdhi1: mmc@ee120000 { 2286 compatible = "renesas,sdhi-r8a774a1", 2287 "renesas,rcar-gen3-sdhi"; 2288 reg = <0 0xee120000 0 0x2000>; 2289 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2290 clocks = <&cpg CPG_MOD 313>; 2291 max-frequency = <200000000>; 2292 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2293 resets = <&cpg 313>; 2294 status = "disabled"; 2295 }; 2296 2297 sdhi2: mmc@ee140000 { 2298 compatible = "renesas,sdhi-r8a774a1", 2299 "renesas,rcar-gen3-sdhi"; 2300 reg = <0 0xee140000 0 0x2000>; 2301 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2302 clocks = <&cpg CPG_MOD 312>; 2303 max-frequency = <200000000>; 2304 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2305 resets = <&cpg 312>; 2306 status = "disabled"; 2307 }; 2308 2309 sdhi3: mmc@ee160000 { 2310 compatible = "renesas,sdhi-r8a774a1", 2311 "renesas,rcar-gen3-sdhi"; 2312 reg = <0 0xee160000 0 0x2000>; 2313 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2314 clocks = <&cpg CPG_MOD 311>; 2315 max-frequency = <200000000>; 2316 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2317 resets = <&cpg 311>; 2318 status = "disabled"; 2319 }; 2320 2321 rpc: spi@ee200000 { 2322 compatible = "renesas,r8a774a1-rpc-if", 2323 "renesas,rcar-gen3-rpc-if"; 2324 reg = <0 0xee200000 0 0x200>, 2325 <0 0x08000000 0 0x4000000>, 2326 <0 0xee208000 0 0x100>; 2327 reg-names = "regs", "dirmap", "wbuf"; 2328 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 2329 clocks = <&cpg CPG_MOD 917>; 2330 clock-names = "rpc"; 2331 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2332 resets = <&cpg 917>; 2333 #address-cells = <1>; 2334 #size-cells = <0>; 2335 status = "disabled"; 2336 }; 2337 2338 gic: interrupt-controller@f1010000 { 2339 compatible = "arm,gic-400"; 2340 #interrupt-cells = <3>; 2341 #address-cells = <0>; 2342 interrupt-controller; 2343 reg = <0x0 0xf1010000 0 0x1000>, 2344 <0x0 0xf1020000 0 0x20000>, 2345 <0x0 0xf1040000 0 0x20000>, 2346 <0x0 0xf1060000 0 0x20000>; 2347 interrupts = <GIC_PPI 9 2348 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 2349 clocks = <&cpg CPG_MOD 408>; 2350 clock-names = "clk"; 2351 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2352 resets = <&cpg 408>; 2353 }; 2354 2355 pciec0: pcie@fe000000 { 2356 compatible = "renesas,pcie-r8a774a1", 2357 "renesas,pcie-rcar-gen3"; 2358 reg = <0 0xfe000000 0 0x80000>; 2359 #address-cells = <3>; 2360 #size-cells = <2>; 2361 bus-range = <0x00 0xff>; 2362 device_type = "pci"; 2363 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2364 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2365 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2366 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2367 /* Map all possible DDR as inbound ranges */ 2368 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2369 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2370 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2371 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2372 #interrupt-cells = <1>; 2373 interrupt-map-mask = <0 0 0 0>; 2374 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2375 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2376 clock-names = "pcie", "pcie_bus"; 2377 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2378 resets = <&cpg 319>; 2379 status = "disabled"; 2380 }; 2381 2382 pciec1: pcie@ee800000 { 2383 compatible = "renesas,pcie-r8a774a1", 2384 "renesas,pcie-rcar-gen3"; 2385 reg = <0 0xee800000 0 0x80000>; 2386 #address-cells = <3>; 2387 #size-cells = <2>; 2388 bus-range = <0x00 0xff>; 2389 device_type = "pci"; 2390 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2391 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2392 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2393 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2394 /* Map all possible DDR as inbound ranges */ 2395 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 2396 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2398 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2399 #interrupt-cells = <1>; 2400 interrupt-map-mask = <0 0 0 0>; 2401 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2402 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2403 clock-names = "pcie", "pcie_bus"; 2404 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2405 resets = <&cpg 318>; 2406 status = "disabled"; 2407 }; 2408 2409 pciec0_ep: pcie-ep@fe000000 { 2410 compatible = "renesas,r8a774a1-pcie-ep", 2411 "renesas,rcar-gen3-pcie-ep"; 2412 reg = <0x0 0xfe000000 0 0x80000>, 2413 <0x0 0xfe100000 0 0x100000>, 2414 <0x0 0xfe200000 0 0x200000>, 2415 <0x0 0x30000000 0 0x8000000>, 2416 <0x0 0x38000000 0 0x8000000>; 2417 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2418 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2419 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2420 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2421 clocks = <&cpg CPG_MOD 319>; 2422 clock-names = "pcie"; 2423 resets = <&cpg 319>; 2424 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2425 status = "disabled"; 2426 }; 2427 2428 pciec1_ep: pcie-ep@ee800000 { 2429 compatible = "renesas,r8a774a1-pcie-ep", 2430 "renesas,rcar-gen3-pcie-ep"; 2431 reg = <0x0 0xee800000 0 0x80000>, 2432 <0x0 0xee900000 0 0x100000>, 2433 <0x0 0xeea00000 0 0x200000>, 2434 <0x0 0xc0000000 0 0x8000000>, 2435 <0x0 0xc8000000 0 0x8000000>; 2436 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2437 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2439 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2440 clocks = <&cpg CPG_MOD 318>; 2441 clock-names = "pcie"; 2442 resets = <&cpg 318>; 2443 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2444 status = "disabled"; 2445 }; 2446 2447 fdp1@fe940000 { 2448 compatible = "renesas,fdp1"; 2449 reg = <0 0xfe940000 0 0x2400>; 2450 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2451 clocks = <&cpg CPG_MOD 119>; 2452 power-domains = <&sysc R8A774A1_PD_A3VC>; 2453 resets = <&cpg 119>; 2454 renesas,fcp = <&fcpf0>; 2455 }; 2456 2457 fcpf0: fcp@fe950000 { 2458 compatible = "renesas,fcpf"; 2459 reg = <0 0xfe950000 0 0x200>; 2460 clocks = <&cpg CPG_MOD 615>; 2461 power-domains = <&sysc R8A774A1_PD_A3VC>; 2462 resets = <&cpg 615>; 2463 }; 2464 2465 fcpvb0: fcp@fe96f000 { 2466 compatible = "renesas,fcpv"; 2467 reg = <0 0xfe96f000 0 0x200>; 2468 clocks = <&cpg CPG_MOD 607>; 2469 power-domains = <&sysc R8A774A1_PD_A3VC>; 2470 resets = <&cpg 607>; 2471 }; 2472 2473 fcpvd0: fcp@fea27000 { 2474 compatible = "renesas,fcpv"; 2475 reg = <0 0xfea27000 0 0x200>; 2476 clocks = <&cpg CPG_MOD 603>; 2477 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2478 resets = <&cpg 603>; 2479 iommus = <&ipmmu_vi0 8>; 2480 }; 2481 2482 fcpvd1: fcp@fea2f000 { 2483 compatible = "renesas,fcpv"; 2484 reg = <0 0xfea2f000 0 0x200>; 2485 clocks = <&cpg CPG_MOD 602>; 2486 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2487 resets = <&cpg 602>; 2488 iommus = <&ipmmu_vi0 9>; 2489 }; 2490 2491 fcpvd2: fcp@fea37000 { 2492 compatible = "renesas,fcpv"; 2493 reg = <0 0xfea37000 0 0x200>; 2494 clocks = <&cpg CPG_MOD 601>; 2495 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2496 resets = <&cpg 601>; 2497 iommus = <&ipmmu_vi0 10>; 2498 }; 2499 2500 fcpvi0: fcp@fe9af000 { 2501 compatible = "renesas,fcpv"; 2502 reg = <0 0xfe9af000 0 0x200>; 2503 clocks = <&cpg CPG_MOD 611>; 2504 power-domains = <&sysc R8A774A1_PD_A3VC>; 2505 resets = <&cpg 611>; 2506 iommus = <&ipmmu_vc0 19>; 2507 }; 2508 2509 vspb: vsp@fe960000 { 2510 compatible = "renesas,vsp2"; 2511 reg = <0 0xfe960000 0 0x8000>; 2512 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2513 clocks = <&cpg CPG_MOD 626>; 2514 power-domains = <&sysc R8A774A1_PD_A3VC>; 2515 resets = <&cpg 626>; 2516 2517 renesas,fcp = <&fcpvb0>; 2518 }; 2519 2520 vspd0: vsp@fea20000 { 2521 compatible = "renesas,vsp2"; 2522 reg = <0 0xfea20000 0 0x5000>; 2523 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2524 clocks = <&cpg CPG_MOD 623>; 2525 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2526 resets = <&cpg 623>; 2527 2528 renesas,fcp = <&fcpvd0>; 2529 }; 2530 2531 vspd1: vsp@fea28000 { 2532 compatible = "renesas,vsp2"; 2533 reg = <0 0xfea28000 0 0x5000>; 2534 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2535 clocks = <&cpg CPG_MOD 622>; 2536 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2537 resets = <&cpg 622>; 2538 2539 renesas,fcp = <&fcpvd1>; 2540 }; 2541 2542 vspd2: vsp@fea30000 { 2543 compatible = "renesas,vsp2"; 2544 reg = <0 0xfea30000 0 0x5000>; 2545 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2546 clocks = <&cpg CPG_MOD 621>; 2547 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2548 resets = <&cpg 621>; 2549 2550 renesas,fcp = <&fcpvd2>; 2551 }; 2552 2553 vspi0: vsp@fe9a0000 { 2554 compatible = "renesas,vsp2"; 2555 reg = <0 0xfe9a0000 0 0x8000>; 2556 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2557 clocks = <&cpg CPG_MOD 631>; 2558 power-domains = <&sysc R8A774A1_PD_A3VC>; 2559 resets = <&cpg 631>; 2560 2561 renesas,fcp = <&fcpvi0>; 2562 }; 2563 2564 csi20: csi2@fea80000 { 2565 compatible = "renesas,r8a774a1-csi2"; 2566 reg = <0 0xfea80000 0 0x10000>; 2567 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2568 clocks = <&cpg CPG_MOD 714>; 2569 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2570 resets = <&cpg 714>; 2571 status = "disabled"; 2572 2573 ports { 2574 #address-cells = <1>; 2575 #size-cells = <0>; 2576 2577 port@0 { 2578 reg = <0>; 2579 }; 2580 2581 port@1 { 2582 #address-cells = <1>; 2583 #size-cells = <0>; 2584 2585 reg = <1>; 2586 2587 csi20vin0: endpoint@0 { 2588 reg = <0>; 2589 remote-endpoint = <&vin0csi20>; 2590 }; 2591 csi20vin1: endpoint@1 { 2592 reg = <1>; 2593 remote-endpoint = <&vin1csi20>; 2594 }; 2595 csi20vin2: endpoint@2 { 2596 reg = <2>; 2597 remote-endpoint = <&vin2csi20>; 2598 }; 2599 csi20vin3: endpoint@3 { 2600 reg = <3>; 2601 remote-endpoint = <&vin3csi20>; 2602 }; 2603 csi20vin4: endpoint@4 { 2604 reg = <4>; 2605 remote-endpoint = <&vin4csi20>; 2606 }; 2607 csi20vin5: endpoint@5 { 2608 reg = <5>; 2609 remote-endpoint = <&vin5csi20>; 2610 }; 2611 csi20vin6: endpoint@6 { 2612 reg = <6>; 2613 remote-endpoint = <&vin6csi20>; 2614 }; 2615 csi20vin7: endpoint@7 { 2616 reg = <7>; 2617 remote-endpoint = <&vin7csi20>; 2618 }; 2619 }; 2620 }; 2621 }; 2622 2623 csi40: csi2@feaa0000 { 2624 compatible = "renesas,r8a774a1-csi2"; 2625 reg = <0 0xfeaa0000 0 0x10000>; 2626 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2627 clocks = <&cpg CPG_MOD 716>; 2628 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2629 resets = <&cpg 716>; 2630 status = "disabled"; 2631 2632 ports { 2633 #address-cells = <1>; 2634 #size-cells = <0>; 2635 2636 port@0 { 2637 reg = <0>; 2638 }; 2639 2640 port@1 { 2641 #address-cells = <1>; 2642 #size-cells = <0>; 2643 2644 reg = <1>; 2645 2646 csi40vin0: endpoint@0 { 2647 reg = <0>; 2648 remote-endpoint = <&vin0csi40>; 2649 }; 2650 csi40vin1: endpoint@1 { 2651 reg = <1>; 2652 remote-endpoint = <&vin1csi40>; 2653 }; 2654 csi40vin2: endpoint@2 { 2655 reg = <2>; 2656 remote-endpoint = <&vin2csi40>; 2657 }; 2658 csi40vin3: endpoint@3 { 2659 reg = <3>; 2660 remote-endpoint = <&vin3csi40>; 2661 }; 2662 csi40vin4: endpoint@4 { 2663 reg = <4>; 2664 remote-endpoint = <&vin4csi40>; 2665 }; 2666 csi40vin5: endpoint@5 { 2667 reg = <5>; 2668 remote-endpoint = <&vin5csi40>; 2669 }; 2670 csi40vin6: endpoint@6 { 2671 reg = <6>; 2672 remote-endpoint = <&vin6csi40>; 2673 }; 2674 csi40vin7: endpoint@7 { 2675 reg = <7>; 2676 remote-endpoint = <&vin7csi40>; 2677 }; 2678 }; 2679 2680 }; 2681 }; 2682 2683 hdmi0: hdmi@fead0000 { 2684 compatible = "renesas,r8a774a1-hdmi", 2685 "renesas,rcar-gen3-hdmi"; 2686 reg = <0 0xfead0000 0 0x10000>; 2687 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2688 clocks = <&cpg CPG_MOD 729>, 2689 <&cpg CPG_CORE R8A774A1_CLK_HDMI>; 2690 clock-names = "iahb", "isfr"; 2691 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2692 resets = <&cpg 729>; 2693 status = "disabled"; 2694 2695 ports { 2696 #address-cells = <1>; 2697 #size-cells = <0>; 2698 port@0 { 2699 reg = <0>; 2700 dw_hdmi0_in: endpoint { 2701 remote-endpoint = <&du_out_hdmi0>; 2702 }; 2703 }; 2704 port@1 { 2705 reg = <1>; 2706 }; 2707 port@2 { 2708 /* HDMI sound */ 2709 reg = <2>; 2710 }; 2711 }; 2712 }; 2713 2714 du: display@feb00000 { 2715 compatible = "renesas,du-r8a774a1"; 2716 reg = <0 0xfeb00000 0 0x70000>; 2717 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2720 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 2721 <&cpg CPG_MOD 722>; 2722 clock-names = "du.0", "du.1", "du.2"; 2723 resets = <&cpg 724>, <&cpg 722>; 2724 reset-names = "du.0", "du.2"; 2725 status = "disabled"; 2726 2727 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; 2728 2729 ports { 2730 #address-cells = <1>; 2731 #size-cells = <0>; 2732 2733 port@0 { 2734 reg = <0>; 2735 du_out_rgb: endpoint { 2736 }; 2737 }; 2738 port@1 { 2739 reg = <1>; 2740 du_out_hdmi0: endpoint { 2741 remote-endpoint = <&dw_hdmi0_in>; 2742 }; 2743 }; 2744 port@2 { 2745 reg = <2>; 2746 du_out_lvds0: endpoint { 2747 remote-endpoint = <&lvds0_in>; 2748 }; 2749 }; 2750 }; 2751 }; 2752 2753 lvds0: lvds@feb90000 { 2754 compatible = "renesas,r8a774a1-lvds"; 2755 reg = <0 0xfeb90000 0 0x14>; 2756 clocks = <&cpg CPG_MOD 727>; 2757 power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; 2758 resets = <&cpg 727>; 2759 status = "disabled"; 2760 2761 ports { 2762 #address-cells = <1>; 2763 #size-cells = <0>; 2764 2765 port@0 { 2766 reg = <0>; 2767 lvds0_in: endpoint { 2768 remote-endpoint = <&du_out_lvds0>; 2769 }; 2770 }; 2771 port@1 { 2772 reg = <1>; 2773 lvds0_out: endpoint { 2774 }; 2775 }; 2776 }; 2777 }; 2778 2779 prr: chipid@fff00044 { 2780 compatible = "renesas,prr"; 2781 reg = <0 0xfff00044 0 4>; 2782 }; 2783 }; 2784 2785 thermal-zones { 2786 sensor_thermal1: sensor-thermal1 { 2787 polling-delay-passive = <250>; 2788 polling-delay = <1000>; 2789 thermal-sensors = <&tsc 0>; 2790 sustainable-power = <3874>; 2791 2792 trips { 2793 sensor1_crit: sensor1-crit { 2794 temperature = <120000>; 2795 hysteresis = <1000>; 2796 type = "critical"; 2797 }; 2798 }; 2799 }; 2800 2801 sensor_thermal2: sensor-thermal2 { 2802 polling-delay-passive = <250>; 2803 polling-delay = <1000>; 2804 thermal-sensors = <&tsc 1>; 2805 sustainable-power = <3874>; 2806 2807 trips { 2808 sensor2_crit: sensor2-crit { 2809 temperature = <120000>; 2810 hysteresis = <1000>; 2811 type = "critical"; 2812 }; 2813 }; 2814 }; 2815 2816 sensor_thermal3: sensor-thermal3 { 2817 polling-delay-passive = <250>; 2818 polling-delay = <1000>; 2819 thermal-sensors = <&tsc 2>; 2820 sustainable-power = <3874>; 2821 2822 cooling-maps { 2823 map0 { 2824 trip = <&target>; 2825 cooling-device = <&a57_0 0 2>; 2826 contribution = <1024>; 2827 }; 2828 map1 { 2829 trip = <&target>; 2830 cooling-device = <&a53_0 0 2>; 2831 contribution = <1024>; 2832 }; 2833 }; 2834 trips { 2835 target: trip-point1 { 2836 temperature = <100000>; 2837 hysteresis = <1000>; 2838 type = "passive"; 2839 }; 2840 2841 sensor3_crit: sensor3-crit { 2842 temperature = <120000>; 2843 hysteresis = <1000>; 2844 type = "critical"; 2845 }; 2846 }; 2847 }; 2848 }; 2849 2850 timer { 2851 compatible = "arm,armv8-timer"; 2852 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2853 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2854 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2855 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2856 }; 2857 2858 /* External USB clocks - can be overridden by the board */ 2859 usb3s0_clk: usb3s0 { 2860 compatible = "fixed-clock"; 2861 #clock-cells = <0>; 2862 clock-frequency = <0>; 2863 }; 2864 2865 usb_extal_clk: usb_extal { 2866 compatible = "fixed-clock"; 2867 #clock-cells = <0>; 2868 clock-frequency = <0>; 2869 }; 2870}; 2871