1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12/ { 13 compatible = "renesas,r8a774a1"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 /* 18 * The external audio clocks are configured as 0 Hz fixed frequency 19 * clocks by default. 20 * Boards that provide audio clocks should override them. 21 */ 22 audio_clk_a: audio_clk_a { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <0>; 26 }; 27 28 audio_clk_b: audio_clk_b { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 audio_clk_c: audio_clk_c { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 /* External CAN clock - to be overridden by boards that provide it */ 41 can_clk: can { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 a57_0: cpu@0 { 52 compatible = "arm,cortex-a57", "arm,armv8"; 53 reg = <0x0>; 54 device_type = "cpu"; 55 power-domains = <&sysc 0>; 56 next-level-cache = <&L2_CA57>; 57 enable-method = "psci"; 58 clocks =<&cpg CPG_CORE 0>; 59 }; 60 61 a57_1: cpu@1 { 62 compatible = "arm,cortex-a57", "arm,armv8"; 63 reg = <0x1>; 64 device_type = "cpu"; 65 power-domains = <&sysc 1>; 66 next-level-cache = <&L2_CA57>; 67 enable-method = "psci"; 68 clocks =<&cpg CPG_CORE 0>; 69 }; 70 71 L2_CA57: cache-controller-0 { 72 compatible = "cache"; 73 power-domains = <&sysc 12>; 74 cache-unified; 75 cache-level = <2>; 76 }; 77 }; 78 79 extal_clk: extal { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 /* This value must be overridden by the board */ 83 clock-frequency = <0>; 84 }; 85 86 extalr_clk: extalr { 87 compatible = "fixed-clock"; 88 #clock-cells = <0>; 89 /* This value must be overridden by the board */ 90 clock-frequency = <0>; 91 }; 92 93 /* External PCIe clock - can be overridden by the board */ 94 pcie_bus_clk: pcie_bus { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <0>; 98 }; 99 100 pmu_a57 { 101 compatible = "arm,cortex-a57-pmu"; 102 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 103 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 104 interrupt-affinity = <&a57_0>, <&a57_1>; 105 }; 106 107 psci { 108 compatible = "arm,psci-1.0", "arm,psci-0.2"; 109 method = "smc"; 110 }; 111 112 /* External SCIF clock - to be overridden by boards that provide it */ 113 scif_clk: scif { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 clock-frequency = <0>; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 interrupt-parent = <&gic>; 122 #address-cells = <2>; 123 #size-cells = <2>; 124 ranges; 125 126 cpg: clock-controller@e6150000 { 127 compatible = "renesas,r8a774a1-cpg-mssr"; 128 reg = <0 0xe6150000 0 0x0bb0>; 129 clocks = <&extal_clk>, <&extalr_clk>; 130 clock-names = "extal", "extalr"; 131 #clock-cells = <2>; 132 #power-domain-cells = <0>; 133 #reset-cells = <1>; 134 }; 135 136 rst: reset-controller@e6160000 { 137 compatible = "renesas,r8a774a1-rst"; 138 reg = <0 0xe6160000 0 0x018c>; 139 }; 140 141 sysc: system-controller@e6180000 { 142 compatible = "renesas,r8a774a1-sysc"; 143 reg = <0 0xe6180000 0 0x0400>; 144 #power-domain-cells = <1>; 145 }; 146 147 hscif0: serial@e6540000 { 148 compatible = "renesas,hscif-r8a774a1", 149 "renesas,rcar-gen3-hscif", 150 "renesas,hscif"; 151 reg = <0 0xe6540000 0 0x60>; 152 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&cpg CPG_MOD 520>, 154 <&cpg CPG_CORE 19>, 155 <&scif_clk>; 156 clock-names = "fck", "brg_int", "scif_clk"; 157 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 158 <&dmac2 0x31>, <&dmac2 0x30>; 159 dma-names = "tx", "rx", "tx", "rx"; 160 power-domains = <&sysc 32>; 161 resets = <&cpg 520>; 162 status = "disabled"; 163 }; 164 165 hscif1: serial@e6550000 { 166 compatible = "renesas,hscif-r8a774a1", 167 "renesas,rcar-gen3-hscif", 168 "renesas,hscif"; 169 reg = <0 0xe6550000 0 0x60>; 170 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 171 clocks = <&cpg CPG_MOD 519>, 172 <&cpg CPG_CORE 19>, 173 <&scif_clk>; 174 clock-names = "fck", "brg_int", "scif_clk"; 175 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 176 <&dmac2 0x33>, <&dmac2 0x32>; 177 dma-names = "tx", "rx", "tx", "rx"; 178 power-domains = <&sysc 32>; 179 resets = <&cpg 519>; 180 status = "disabled"; 181 }; 182 183 hscif2: serial@e6560000 { 184 compatible = "renesas,hscif-r8a774a1", 185 "renesas,rcar-gen3-hscif", 186 "renesas,hscif"; 187 reg = <0 0xe6560000 0 0x60>; 188 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&cpg CPG_MOD 518>, 190 <&cpg CPG_CORE 19>, 191 <&scif_clk>; 192 clock-names = "fck", "brg_int", "scif_clk"; 193 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 194 <&dmac2 0x35>, <&dmac2 0x34>; 195 dma-names = "tx", "rx", "tx", "rx"; 196 power-domains = <&sysc 32>; 197 resets = <&cpg 518>; 198 status = "disabled"; 199 }; 200 201 hscif3: serial@e66a0000 { 202 compatible = "renesas,hscif-r8a774a1", 203 "renesas,rcar-gen3-hscif", 204 "renesas,hscif"; 205 reg = <0 0xe66a0000 0 0x60>; 206 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&cpg CPG_MOD 517>, 208 <&cpg CPG_CORE 19>, 209 <&scif_clk>; 210 clock-names = "fck", "brg_int", "scif_clk"; 211 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 212 dma-names = "tx", "rx"; 213 power-domains = <&sysc 32>; 214 resets = <&cpg 517>; 215 status = "disabled"; 216 }; 217 218 hscif4: serial@e66b0000 { 219 compatible = "renesas,hscif-r8a774a1", 220 "renesas,rcar-gen3-hscif", 221 "renesas,hscif"; 222 reg = <0 0xe66b0000 0 0x60>; 223 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&cpg CPG_MOD 516>, 225 <&cpg CPG_CORE 19>, 226 <&scif_clk>; 227 clock-names = "fck", "brg_int", "scif_clk"; 228 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 229 dma-names = "tx", "rx"; 230 power-domains = <&sysc 32>; 231 resets = <&cpg 516>; 232 status = "disabled"; 233 }; 234 235 dmac0: dma-controller@e6700000 { 236 compatible = "renesas,dmac-r8a774a1", 237 "renesas,rcar-dmac"; 238 reg = <0 0xe6700000 0 0x10000>; 239 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 240 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 241 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 242 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 243 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 244 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 245 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 246 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 247 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 248 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 249 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 250 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 251 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 252 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 253 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 254 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 255 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 256 interrupt-names = "error", 257 "ch0", "ch1", "ch2", "ch3", 258 "ch4", "ch5", "ch6", "ch7", 259 "ch8", "ch9", "ch10", "ch11", 260 "ch12", "ch13", "ch14", "ch15"; 261 clocks = <&cpg CPG_MOD 219>; 262 clock-names = "fck"; 263 power-domains = <&sysc 32>; 264 resets = <&cpg 219>; 265 #dma-cells = <1>; 266 dma-channels = <16>; 267 }; 268 269 dmac1: dma-controller@e7300000 { 270 compatible = "renesas,dmac-r8a774a1", 271 "renesas,rcar-dmac"; 272 reg = <0 0xe7300000 0 0x10000>; 273 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 274 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 275 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 276 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 277 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 278 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 279 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 280 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 281 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 282 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 283 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 284 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 285 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 286 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 287 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 288 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 289 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-names = "error", 291 "ch0", "ch1", "ch2", "ch3", 292 "ch4", "ch5", "ch6", "ch7", 293 "ch8", "ch9", "ch10", "ch11", 294 "ch12", "ch13", "ch14", "ch15"; 295 clocks = <&cpg CPG_MOD 218>; 296 clock-names = "fck"; 297 power-domains = <&sysc 32>; 298 resets = <&cpg 218>; 299 #dma-cells = <1>; 300 dma-channels = <16>; 301 }; 302 303 dmac2: dma-controller@e7310000 { 304 compatible = "renesas,dmac-r8a774a1", 305 "renesas,rcar-dmac"; 306 reg = <0 0xe7310000 0 0x10000>; 307 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 308 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 309 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 310 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 311 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 312 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 313 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 314 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 315 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 316 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 317 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 318 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 319 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 320 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 321 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 322 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 323 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 324 interrupt-names = "error", 325 "ch0", "ch1", "ch2", "ch3", 326 "ch4", "ch5", "ch6", "ch7", 327 "ch8", "ch9", "ch10", "ch11", 328 "ch12", "ch13", "ch14", "ch15"; 329 clocks = <&cpg CPG_MOD 217>; 330 clock-names = "fck"; 331 power-domains = <&sysc 32>; 332 resets = <&cpg 217>; 333 #dma-cells = <1>; 334 dma-channels = <16>; 335 }; 336 337 scif0: serial@e6e60000 { 338 compatible = "renesas,scif-r8a774a1", 339 "renesas,rcar-gen3-scif", "renesas,scif"; 340 reg = <0 0xe6e60000 0 0x40>; 341 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&cpg CPG_MOD 207>, 343 <&cpg CPG_CORE 19>, 344 <&scif_clk>; 345 clock-names = "fck", "brg_int", "scif_clk"; 346 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 347 <&dmac2 0x51>, <&dmac2 0x50>; 348 dma-names = "tx", "rx", "tx", "rx"; 349 power-domains = <&sysc 32>; 350 resets = <&cpg 207>; 351 status = "disabled"; 352 }; 353 354 scif1: serial@e6e68000 { 355 compatible = "renesas,scif-r8a774a1", 356 "renesas,rcar-gen3-scif", "renesas,scif"; 357 reg = <0 0xe6e68000 0 0x40>; 358 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&cpg CPG_MOD 206>, 360 <&cpg CPG_CORE 19>, 361 <&scif_clk>; 362 clock-names = "fck", "brg_int", "scif_clk"; 363 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 364 <&dmac2 0x53>, <&dmac2 0x52>; 365 dma-names = "tx", "rx", "tx", "rx"; 366 power-domains = <&sysc 32>; 367 resets = <&cpg 206>; 368 status = "disabled"; 369 }; 370 371 scif2: serial@e6e88000 { 372 compatible = "renesas,scif-r8a774a1", 373 "renesas,rcar-gen3-scif", "renesas,scif"; 374 reg = <0 0xe6e88000 0 0x40>; 375 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&cpg CPG_MOD 310>, 377 <&cpg CPG_CORE 19>, 378 <&scif_clk>; 379 clock-names = "fck", "brg_int", "scif_clk"; 380 power-domains = <&sysc 32>; 381 resets = <&cpg 310>; 382 status = "disabled"; 383 }; 384 385 scif3: serial@e6c50000 { 386 compatible = "renesas,scif-r8a774a1", 387 "renesas,rcar-gen3-scif", "renesas,scif"; 388 reg = <0 0xe6c50000 0 0x40>; 389 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&cpg CPG_MOD 204>, 391 <&cpg CPG_CORE 19>, 392 <&scif_clk>; 393 clock-names = "fck", "brg_int", "scif_clk"; 394 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 395 dma-names = "tx", "rx"; 396 power-domains = <&sysc 32>; 397 resets = <&cpg 204>; 398 status = "disabled"; 399 }; 400 401 scif4: serial@e6c40000 { 402 compatible = "renesas,scif-r8a774a1", 403 "renesas,rcar-gen3-scif", "renesas,scif"; 404 reg = <0 0xe6c40000 0 0x40>; 405 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&cpg CPG_MOD 203>, 407 <&cpg CPG_CORE 19>, 408 <&scif_clk>; 409 clock-names = "fck", "brg_int", "scif_clk"; 410 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 411 dma-names = "tx", "rx"; 412 power-domains = <&sysc 32>; 413 resets = <&cpg 203>; 414 status = "disabled"; 415 }; 416 417 scif5: serial@e6f30000 { 418 compatible = "renesas,scif-r8a774a1", 419 "renesas,rcar-gen3-scif", "renesas,scif"; 420 reg = <0 0xe6f30000 0 0x40>; 421 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&cpg CPG_MOD 202>, 423 <&cpg CPG_CORE 19>, 424 <&scif_clk>; 425 clock-names = "fck", "brg_int", "scif_clk"; 426 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 427 <&dmac2 0x5b>, <&dmac2 0x5a>; 428 dma-names = "tx", "rx", "tx", "rx"; 429 power-domains = <&sysc 32>; 430 resets = <&cpg 202>; 431 status = "disabled"; 432 }; 433 434 gic: interrupt-controller@f1010000 { 435 compatible = "arm,gic-400"; 436 #interrupt-cells = <3>; 437 #address-cells = <0>; 438 interrupt-controller; 439 reg = <0x0 0xf1010000 0 0x1000>, 440 <0x0 0xf1020000 0 0x20000>, 441 <0x0 0xf1040000 0 0x20000>, 442 <0x0 0xf1060000 0 0x20000>; 443 interrupts = <GIC_PPI 9 444 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 445 clocks = <&cpg CPG_MOD 408>; 446 clock-names = "clk"; 447 power-domains = <&sysc 32>; 448 resets = <&cpg 408>; 449 }; 450 451 prr: chipid@fff00044 { 452 compatible = "renesas,prr"; 453 reg = <0 0xfff00044 0 4>; 454 }; 455 }; 456 457 timer { 458 compatible = "arm,armv8-timer"; 459 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 460 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 461 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 462 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 463 }; 464 465 /* External USB clocks - can be overridden by the board */ 466 usb3s0_clk: usb3s0 { 467 compatible = "fixed-clock"; 468 #clock-cells = <0>; 469 clock-frequency = <0>; 470 }; 471 472 usb_extal_clk: usb_extal { 473 compatible = "fixed-clock"; 474 #clock-cells = <0>; 475 clock-frequency = <0>; 476 }; 477}; 478