1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a774a1 SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12/ { 13 compatible = "renesas,r8a774a1"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 /* 18 * The external audio clocks are configured as 0 Hz fixed frequency 19 * clocks by default. 20 * Boards that provide audio clocks should override them. 21 */ 22 audio_clk_a: audio_clk_a { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <0>; 26 }; 27 28 audio_clk_b: audio_clk_b { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 audio_clk_c: audio_clk_c { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 /* External CAN clock - to be overridden by boards that provide it */ 41 can_clk: can { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 a57_0: cpu@0 { 52 compatible = "arm,cortex-a57", "arm,armv8"; 53 reg = <0x0>; 54 device_type = "cpu"; 55 power-domains = <&sysc 0>; 56 next-level-cache = <&L2_CA57>; 57 enable-method = "psci"; 58 clocks =<&cpg CPG_CORE 0>; 59 }; 60 61 a57_1: cpu@1 { 62 compatible = "arm,cortex-a57", "arm,armv8"; 63 reg = <0x1>; 64 device_type = "cpu"; 65 power-domains = <&sysc 1>; 66 next-level-cache = <&L2_CA57>; 67 enable-method = "psci"; 68 clocks =<&cpg CPG_CORE 0>; 69 }; 70 71 L2_CA57: cache-controller-0 { 72 compatible = "cache"; 73 power-domains = <&sysc 12>; 74 cache-unified; 75 cache-level = <2>; 76 }; 77 }; 78 79 extal_clk: extal { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 /* This value must be overridden by the board */ 83 clock-frequency = <0>; 84 }; 85 86 extalr_clk: extalr { 87 compatible = "fixed-clock"; 88 #clock-cells = <0>; 89 /* This value must be overridden by the board */ 90 clock-frequency = <0>; 91 }; 92 93 /* External PCIe clock - can be overridden by the board */ 94 pcie_bus_clk: pcie_bus { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <0>; 98 }; 99 100 pmu_a57 { 101 compatible = "arm,cortex-a57-pmu"; 102 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 103 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 104 interrupt-affinity = <&a57_0>, <&a57_1>; 105 }; 106 107 psci { 108 compatible = "arm,psci-1.0", "arm,psci-0.2"; 109 method = "smc"; 110 }; 111 112 /* External SCIF clock - to be overridden by boards that provide it */ 113 scif_clk: scif { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 clock-frequency = <0>; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 interrupt-parent = <&gic>; 122 #address-cells = <2>; 123 #size-cells = <2>; 124 ranges; 125 126 cpg: clock-controller@e6150000 { 127 compatible = "renesas,r8a774a1-cpg-mssr"; 128 reg = <0 0xe6150000 0 0x0bb0>; 129 clocks = <&extal_clk>, <&extalr_clk>; 130 clock-names = "extal", "extalr"; 131 #clock-cells = <2>; 132 #power-domain-cells = <0>; 133 #reset-cells = <1>; 134 }; 135 136 rst: reset-controller@e6160000 { 137 compatible = "renesas,r8a774a1-rst"; 138 reg = <0 0xe6160000 0 0x018c>; 139 }; 140 141 sysc: system-controller@e6180000 { 142 compatible = "renesas,r8a774a1-sysc"; 143 reg = <0 0xe6180000 0 0x0400>; 144 #power-domain-cells = <1>; 145 }; 146 147 dmac0: dma-controller@e6700000 { 148 compatible = "renesas,dmac-r8a774a1", 149 "renesas,rcar-dmac"; 150 reg = <0 0xe6700000 0 0x10000>; 151 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 152 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 153 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 154 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 155 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 156 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 157 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 158 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 159 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 160 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 161 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 162 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 163 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 164 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 165 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 166 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH 167 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 168 interrupt-names = "error", 169 "ch0", "ch1", "ch2", "ch3", 170 "ch4", "ch5", "ch6", "ch7", 171 "ch8", "ch9", "ch10", "ch11", 172 "ch12", "ch13", "ch14", "ch15"; 173 clocks = <&cpg CPG_MOD 219>; 174 clock-names = "fck"; 175 power-domains = <&sysc 32>; 176 resets = <&cpg 219>; 177 #dma-cells = <1>; 178 dma-channels = <16>; 179 }; 180 181 dmac1: dma-controller@e7300000 { 182 compatible = "renesas,dmac-r8a774a1", 183 "renesas,rcar-dmac"; 184 reg = <0 0xe7300000 0 0x10000>; 185 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 186 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 187 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 188 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 189 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 190 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 191 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 192 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 193 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 194 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 195 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 196 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 197 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 198 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 199 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 200 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 201 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 202 interrupt-names = "error", 203 "ch0", "ch1", "ch2", "ch3", 204 "ch4", "ch5", "ch6", "ch7", 205 "ch8", "ch9", "ch10", "ch11", 206 "ch12", "ch13", "ch14", "ch15"; 207 clocks = <&cpg CPG_MOD 218>; 208 clock-names = "fck"; 209 power-domains = <&sysc 32>; 210 resets = <&cpg 218>; 211 #dma-cells = <1>; 212 dma-channels = <16>; 213 }; 214 215 dmac2: dma-controller@e7310000 { 216 compatible = "renesas,dmac-r8a774a1", 217 "renesas,rcar-dmac"; 218 reg = <0 0xe7310000 0 0x10000>; 219 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH 220 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 221 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 222 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 223 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 224 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 225 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 226 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 227 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 228 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 229 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 230 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 231 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 232 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 233 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 234 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 235 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 236 interrupt-names = "error", 237 "ch0", "ch1", "ch2", "ch3", 238 "ch4", "ch5", "ch6", "ch7", 239 "ch8", "ch9", "ch10", "ch11", 240 "ch12", "ch13", "ch14", "ch15"; 241 clocks = <&cpg CPG_MOD 217>; 242 clock-names = "fck"; 243 power-domains = <&sysc 32>; 244 resets = <&cpg 217>; 245 #dma-cells = <1>; 246 dma-channels = <16>; 247 }; 248 249 gic: interrupt-controller@f1010000 { 250 compatible = "arm,gic-400"; 251 #interrupt-cells = <3>; 252 #address-cells = <0>; 253 interrupt-controller; 254 reg = <0x0 0xf1010000 0 0x1000>, 255 <0x0 0xf1020000 0 0x20000>, 256 <0x0 0xf1040000 0 0x20000>, 257 <0x0 0xf1060000 0 0x20000>; 258 interrupts = <GIC_PPI 9 259 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 260 clocks = <&cpg CPG_MOD 408>; 261 clock-names = "clk"; 262 power-domains = <&sysc 32>; 263 resets = <&cpg 408>; 264 }; 265 266 prr: chipid@fff00044 { 267 compatible = "renesas,prr"; 268 reg = <0 0xfff00044 0 4>; 269 }; 270 }; 271 272 timer { 273 compatible = "arm,armv8-timer"; 274 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 275 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 276 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 277 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 278 }; 279 280 /* External USB clocks - can be overridden by the board */ 281 usb3s0_clk: usb3s0 { 282 compatible = "fixed-clock"; 283 #clock-cells = <0>; 284 clock-frequency = <0>; 285 }; 286 287 usb_extal_clk: usb_extal { 288 compatible = "fixed-clock"; 289 #clock-cells = <0>; 290 clock-frequency = <0>; 291 }; 292}; 293