1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the Draak board 4 * 5 * Copyright (C) 2016-2018 Renesas Electronics Corp. 6 * Copyright (C) 2017 Glider bvba 7 */ 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11 12/ { 13 model = "Renesas Draak board"; 14 compatible = "renesas,draak"; 15 16 aliases { 17 serial0 = &scif2; 18 ethernet0 = &avb; 19 }; 20 21 audio_clkout: audio-clkout { 22 /* 23 * This is same as <&rcar_sound 0> 24 * but needed to avoid cs2000/rcar_sound probe dead-lock 25 */ 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <12288000>; 29 }; 30 31 backlight: backlight { 32 compatible = "pwm-backlight"; 33 pwms = <&pwm1 0 50000>; 34 35 brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>; 36 default-brightness-level = <10>; 37 38 power-supply = <®_12p0v>; 39 enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; 40 }; 41 42 chosen { 43 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 44 stdout-path = "serial0:115200n8"; 45 }; 46 47 composite-in { 48 compatible = "composite-video-connector"; 49 50 port { 51 composite_con_in: endpoint { 52 remote-endpoint = <&adv7180_in>; 53 }; 54 }; 55 }; 56 57 hdmi-in { 58 compatible = "hdmi-connector"; 59 type = "a"; 60 61 port { 62 hdmi_con_in: endpoint { 63 remote-endpoint = <&adv7612_in>; 64 }; 65 }; 66 }; 67 68 hdmi-out { 69 compatible = "hdmi-connector"; 70 type = "a"; 71 72 port { 73 hdmi_con_out: endpoint { 74 remote-endpoint = <&adv7511_out>; 75 }; 76 }; 77 }; 78 79 keys { 80 compatible = "gpio-keys"; 81 82 pinctrl-0 = <&keys_pins>; 83 pinctrl-names = "default"; 84 85 key-1 { 86 gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; 87 linux,code = <KEY_1>; 88 label = "SW56-1"; 89 wakeup-source; 90 debounce-interval = <20>; 91 }; 92 key-2 { 93 gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; 94 linux,code = <KEY_2>; 95 label = "SW56-2"; 96 wakeup-source; 97 debounce-interval = <20>; 98 }; 99 key-3 { 100 gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; 101 linux,code = <KEY_3>; 102 label = "SW56-3"; 103 wakeup-source; 104 debounce-interval = <20>; 105 }; 106 key-4 { 107 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; 108 linux,code = <KEY_4>; 109 label = "SW56-4"; 110 wakeup-source; 111 debounce-interval = <20>; 112 }; 113 }; 114 115 lvds-decoder { 116 compatible = "thine,thc63lvd1024"; 117 vcc-supply = <®_3p3v>; 118 119 ports { 120 #address-cells = <1>; 121 #size-cells = <0>; 122 123 port@0 { 124 reg = <0>; 125 thc63lvd1024_in: endpoint { 126 remote-endpoint = <&lvds0_out>; 127 }; 128 }; 129 130 port@2 { 131 reg = <2>; 132 thc63lvd1024_out: endpoint { 133 remote-endpoint = <&adv7511_in>; 134 }; 135 }; 136 }; 137 }; 138 139 memory@48000000 { 140 device_type = "memory"; 141 /* first 128MB is reserved for secure area. */ 142 reg = <0x0 0x48000000 0x0 0x18000000>; 143 }; 144 145 reg_1p8v: regulator-1p8v { 146 compatible = "regulator-fixed"; 147 regulator-name = "fixed-1.8V"; 148 regulator-min-microvolt = <1800000>; 149 regulator-max-microvolt = <1800000>; 150 regulator-boot-on; 151 regulator-always-on; 152 }; 153 154 reg_3p3v: regulator-3p3v { 155 compatible = "regulator-fixed"; 156 regulator-name = "fixed-3.3V"; 157 regulator-min-microvolt = <3300000>; 158 regulator-max-microvolt = <3300000>; 159 regulator-boot-on; 160 regulator-always-on; 161 }; 162 163 reg_12p0v: regulator-12p0v { 164 compatible = "regulator-fixed"; 165 regulator-name = "D12.0V"; 166 regulator-min-microvolt = <12000000>; 167 regulator-max-microvolt = <12000000>; 168 regulator-boot-on; 169 regulator-always-on; 170 }; 171 172 sound_card: sound { 173 compatible = "audio-graph-card"; 174 175 dais = <&rsnd_port0 /* ak4613 */ 176 /* HDMI is not yet supported */ 177 >; 178 }; 179 180 vga { 181 compatible = "vga-connector"; 182 183 port { 184 vga_in: endpoint { 185 remote-endpoint = <&adv7123_out>; 186 }; 187 }; 188 }; 189 190 vga-encoder { 191 compatible = "adi,adv7123"; 192 193 ports { 194 #address-cells = <1>; 195 #size-cells = <0>; 196 197 port@0 { 198 reg = <0>; 199 adv7123_in: endpoint { 200 remote-endpoint = <&du_out_rgb>; 201 }; 202 }; 203 port@1 { 204 reg = <1>; 205 adv7123_out: endpoint { 206 remote-endpoint = <&vga_in>; 207 }; 208 }; 209 }; 210 }; 211 212 x12_clk: x12 { 213 compatible = "fixed-clock"; 214 #clock-cells = <0>; 215 clock-frequency = <74250000>; 216 }; 217 218 x19_clk: x19 { 219 compatible = "fixed-clock"; 220 #clock-cells = <0>; 221 clock-frequency = <24576000>; 222 }; 223}; 224 225&audio_clk_b { 226 /* 227 * X11 is connected to VI4_FIELD/SCIF_CLK/AUDIO_CLKB, 228 * and R-Car Sound uses AUDIO_CLKB. 229 * Note is that schematic indicates VI4_FIELD conection only 230 * not AUDIO_CLKB at SoC page. 231 * And this VI4_FIELD/SCIF_CLK/AUDIO_CLKB is connected to SW60. 232 * SW60 should be 1-2. 233 */ 234 235 clock-frequency = <22579200>; 236}; 237 238&avb { 239 pinctrl-0 = <&avb0_pins>; 240 pinctrl-names = "default"; 241 renesas,no-ether-link; 242 phy-handle = <&phy0>; 243 status = "okay"; 244 245 phy0: ethernet-phy@0 { 246 compatible = "ethernet-phy-id0022.1622", 247 "ethernet-phy-ieee802.3-c22"; 248 rxc-skew-ps = <1500>; 249 reg = <0>; 250 interrupts-extended = <&gpio5 19 IRQ_TYPE_LEVEL_LOW>; 251 reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>; 252 /* 253 * TX clock internal delay mode is required for reliable 254 * 1Gbps communication using the KSZ9031RNX phy present on 255 * the Draak board, however, TX clock internal delay mode 256 * isn't supported on R-Car D3(e). Thus, limit speed to 257 * 100Mbps for reliable communication. 258 */ 259 max-speed = <100>; 260 }; 261}; 262 263&can0 { 264 pinctrl-0 = <&can0_pins>; 265 pinctrl-names = "default"; 266 status = "okay"; 267}; 268 269&can1 { 270 pinctrl-0 = <&can1_pins>; 271 pinctrl-names = "default"; 272 status = "okay"; 273}; 274 275&du { 276 pinctrl-0 = <&du_pins>; 277 pinctrl-names = "default"; 278 status = "okay"; 279 280 clocks = <&cpg CPG_MOD 724>, 281 <&cpg CPG_MOD 723>, 282 <&x12_clk>; 283 clock-names = "du.0", "du.1", "dclkin.0"; 284 285 ports { 286 port@0 { 287 du_out_rgb: endpoint { 288 remote-endpoint = <&adv7123_in>; 289 }; 290 }; 291 }; 292}; 293 294&ehci0 { 295 dr_mode = "host"; 296 status = "okay"; 297}; 298 299&extal_clk { 300 clock-frequency = <48000000>; 301}; 302 303&hsusb { 304 dr_mode = "host"; 305 status = "okay"; 306}; 307 308&i2c0 { 309 pinctrl-0 = <&i2c0_pins>; 310 pinctrl-names = "default"; 311 status = "okay"; 312 313 ak4613: codec@10 { 314 compatible = "asahi-kasei,ak4613"; 315 #sound-dai-cells = <0>; 316 reg = <0x10>; 317 clocks = <&rcar_sound 0>; /* audio_clkout */ 318 319 asahi-kasei,in1-single-end; 320 asahi-kasei,in2-single-end; 321 asahi-kasei,out1-single-end; 322 asahi-kasei,out2-single-end; 323 asahi-kasei,out3-single-end; 324 asahi-kasei,out4-single-end; 325 asahi-kasei,out5-single-end; 326 asahi-kasei,out6-single-end; 327 328 port { 329 ak4613_endpoint: endpoint { 330 remote-endpoint = <&rsnd_for_ak4613>; 331 }; 332 }; 333 }; 334 335 composite-in@20 { 336 compatible = "adi,adv7180cp"; 337 reg = <0x20>; 338 339 ports { 340 #address-cells = <1>; 341 #size-cells = <0>; 342 343 port@0 { 344 reg = <0>; 345 adv7180_in: endpoint { 346 remote-endpoint = <&composite_con_in>; 347 }; 348 }; 349 350 port@3 { 351 reg = <3>; 352 353 /* 354 * The VIN4 video input path is shared between 355 * CVBS and HDMI inputs through SW[49-53] 356 * switches. 357 * 358 * HDMI is the default selection, leave CVBS 359 * not connected here. 360 */ 361 }; 362 }; 363 364 }; 365 366 hdmi-encoder@39 { 367 compatible = "adi,adv7511w"; 368 reg = <0x39>, <0x3f>, <0x3c>, <0x38>; 369 reg-names = "main", "edid", "cec", "packet"; 370 interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; 371 372 avdd-supply = <®_1p8v>; 373 dvdd-supply = <®_1p8v>; 374 pvdd-supply = <®_1p8v>; 375 dvdd-3v-supply = <®_3p3v>; 376 bgvdd-supply = <®_1p8v>; 377 378 adi,input-depth = <8>; 379 adi,input-colorspace = "rgb"; 380 adi,input-clock = "1x"; 381 382 ports { 383 #address-cells = <1>; 384 #size-cells = <0>; 385 386 port@0 { 387 reg = <0>; 388 adv7511_in: endpoint { 389 remote-endpoint = <&thc63lvd1024_out>; 390 }; 391 }; 392 393 port@1 { 394 reg = <1>; 395 adv7511_out: endpoint { 396 remote-endpoint = <&hdmi_con_out>; 397 }; 398 }; 399 }; 400 }; 401 402 hdmi-decoder@4c { 403 compatible = "adi,adv7612"; 404 reg = <0x4c>; 405 default-input = <0>; 406 407 ports { 408 #address-cells = <1>; 409 #size-cells = <0>; 410 411 port@0 { 412 reg = <0>; 413 414 adv7612_in: endpoint { 415 remote-endpoint = <&hdmi_con_in>; 416 }; 417 }; 418 419 port@2 { 420 reg = <2>; 421 422 /* 423 * The VIN4 video input path is shared between 424 * CVBS and HDMI inputs through SW[49-53] 425 * switches. 426 * 427 * HDMI is the default selection, link it to 428 * VIN4 here. 429 */ 430 adv7612_out: endpoint { 431 remote-endpoint = <&vin4_in>; 432 }; 433 }; 434 }; 435 }; 436 437 cs2000: clk-multiplier@4f { 438 #clock-cells = <0>; 439 compatible = "cirrus,cs2000-cp"; 440 reg = <0x4f>; 441 clocks = <&audio_clkout>, <&x19_clk>; /* audio_clkout_1, x19 */ 442 clock-names = "clk_in", "ref_clk"; 443 444 assigned-clocks = <&cs2000>; 445 assigned-clock-rates = <24576000>; /* 1/1 divide */ 446 }; 447 448 eeprom@50 { 449 compatible = "rohm,br24t01", "atmel,24c01"; 450 reg = <0x50>; 451 pagesize = <8>; 452 }; 453}; 454 455&i2c1 { 456 pinctrl-0 = <&i2c1_pins>; 457 pinctrl-names = "default"; 458 status = "okay"; 459}; 460 461&lvds0 { 462 status = "okay"; 463 464 clocks = <&cpg CPG_MOD 727>, 465 <&x12_clk>, 466 <&extal_clk>; 467 clock-names = "fck", "dclkin.0", "extal"; 468 469 ports { 470 port@1 { 471 lvds0_out: endpoint { 472 remote-endpoint = <&thc63lvd1024_in>; 473 }; 474 }; 475 }; 476}; 477 478&lvds1 { 479 /* 480 * Even though the LVDS1 output is not connected, the encoder must be 481 * enabled to supply a pixel clock to the DU for the DPAD output when 482 * LVDS0 is in use. 483 */ 484 status = "okay"; 485 486 clocks = <&cpg CPG_MOD 727>, 487 <&x12_clk>, 488 <&extal_clk>; 489 clock-names = "fck", "dclkin.0", "extal"; 490}; 491 492&ohci0 { 493 dr_mode = "host"; 494 status = "okay"; 495}; 496 497&pfc { 498 avb0_pins: avb { 499 groups = "avb0_link", "avb0_mdio", "avb0_mii"; 500 function = "avb0"; 501 }; 502 503 can0_pins: can0 { 504 groups = "can0_data_a"; 505 function = "can0"; 506 }; 507 508 can1_pins: can1 { 509 groups = "can1_data_a"; 510 function = "can1"; 511 }; 512 513 du_pins: du { 514 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; 515 function = "du"; 516 }; 517 518 i2c0_pins: i2c0 { 519 groups = "i2c0"; 520 function = "i2c0"; 521 }; 522 523 i2c1_pins: i2c1 { 524 groups = "i2c1"; 525 function = "i2c1"; 526 }; 527 528 keys_pins: keys { 529 pins = "GP_4_12", "GP_4_13", "GP_4_14", "GP_4_15"; 530 bias-pull-up; 531 }; 532 533 pwm0_pins: pwm0 { 534 groups = "pwm0_c"; 535 function = "pwm0"; 536 }; 537 538 pwm1_pins: pwm1 { 539 groups = "pwm1_c"; 540 function = "pwm1"; 541 }; 542 543 rpc_pins: rpc { 544 groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset", 545 "rpc_int"; 546 function = "rpc"; 547 }; 548 549 scif2_pins: scif2 { 550 groups = "scif2_data"; 551 function = "scif2"; 552 }; 553 554 sdhi2_pins: sd2 { 555 groups = "mmc_data8", "mmc_ctrl"; 556 function = "mmc"; 557 power-source = <1800>; 558 }; 559 560 sdhi2_pins_uhs: sd2_uhs { 561 groups = "mmc_data8", "mmc_ctrl"; 562 function = "mmc"; 563 power-source = <1800>; 564 }; 565 566 sound_pins: sound { 567 groups = "ssi34_ctrl", "ssi3_data", "ssi4_data_a"; 568 function = "ssi"; 569 }; 570 571 sound_clk_pins: sound-clk { 572 groups = "audio_clk_a", "audio_clk_b", 573 "audio_clkout", "audio_clkout1"; 574 function = "audio_clk"; 575 }; 576 577 usb0_pins: usb0 { 578 groups = "usb0"; 579 function = "usb0"; 580 }; 581 582 vin4_pins: vin4 { 583 groups = "vin4_data24", "vin4_sync", "vin4_clk"; 584 function = "vin4"; 585 }; 586}; 587 588&pwm0 { 589 pinctrl-0 = <&pwm0_pins>; 590 pinctrl-names = "default"; 591 592 status = "okay"; 593}; 594 595&pwm1 { 596 pinctrl-0 = <&pwm1_pins>; 597 pinctrl-names = "default"; 598 599 status = "okay"; 600}; 601 602&rcar_sound { 603 pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; 604 pinctrl-names = "default"; 605 606 /* Single DAI */ 607 #sound-dai-cells = <0>; 608 609 /* audio_clkout0/1 */ 610 #clock-cells = <1>; 611 clock-frequency = <12288000 11289600>; 612 613 status = "okay"; 614 615 clocks = <&cpg CPG_MOD 1005>, 616 <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>, 617 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, 618 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 619 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 620 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 621 <&cs2000>, <&audio_clk_b>, 622 <&cpg CPG_CORE R8A77995_CLK_ZA2>; 623 624 ports { 625 rsnd_port0: port { 626 rsnd_for_ak4613: endpoint { 627 remote-endpoint = <&ak4613_endpoint>; 628 dai-format = "left_j"; 629 bitclock-master = <&rsnd_for_ak4613>; 630 frame-master = <&rsnd_for_ak4613>; 631 playback = <&ssi3>, <&src5>, <&dvc0>; 632 capture = <&ssi4>, <&src6>, <&dvc1>; 633 }; 634 }; 635 }; 636}; 637 638&rpc { 639 pinctrl-0 = <&rpc_pins>; 640 pinctrl-names = "default"; 641 642 /* Left disabled. To be enabled by firmware when unlocked. */ 643 644 flash@0 { 645 compatible = "cypress,hyperflash", "cfi-flash"; 646 reg = <0>; 647 648 partitions { 649 compatible = "fixed-partitions"; 650 #address-cells = <1>; 651 #size-cells = <1>; 652 653 bootparam@0 { 654 reg = <0x00000000 0x040000>; 655 read-only; 656 }; 657 bl2@40000 { 658 reg = <0x00040000 0x140000>; 659 read-only; 660 }; 661 cert_header_sa6@180000 { 662 reg = <0x00180000 0x040000>; 663 read-only; 664 }; 665 bl31@1c0000 { 666 reg = <0x001c0000 0x040000>; 667 read-only; 668 }; 669 tee@200000 { 670 reg = <0x00200000 0x440000>; 671 read-only; 672 }; 673 uboot@640000 { 674 reg = <0x00640000 0x100000>; 675 read-only; 676 }; 677 dtb@740000 { 678 reg = <0x00740000 0x080000>; 679 }; 680 kernel@7c0000 { 681 reg = <0x007c0000 0x1400000>; 682 }; 683 user@1bc0000 { 684 reg = <0x01bc0000 0x2440000>; 685 }; 686 }; 687 }; 688}; 689 690&rwdt { 691 timeout-sec = <60>; 692 status = "okay"; 693}; 694 695&scif2 { 696 pinctrl-0 = <&scif2_pins>; 697 pinctrl-names = "default"; 698 699 status = "okay"; 700}; 701 702&sdhi2 { 703 /* used for on-board eMMC */ 704 pinctrl-0 = <&sdhi2_pins>; 705 pinctrl-1 = <&sdhi2_pins_uhs>; 706 pinctrl-names = "default", "state_uhs"; 707 708 vmmc-supply = <®_3p3v>; 709 vqmmc-supply = <®_1p8v>; 710 bus-width = <8>; 711 mmc-hs200-1_8v; 712 no-sd; 713 no-sdio; 714 non-removable; 715 status = "okay"; 716}; 717 718&ssi4 { 719 shared-pin; 720}; 721 722&usb2_phy0 { 723 pinctrl-0 = <&usb0_pins>; 724 pinctrl-names = "default"; 725 726 renesas,no-otg-pins; 727 status = "okay"; 728}; 729 730&vin4 { 731 pinctrl-0 = <&vin4_pins>; 732 pinctrl-names = "default"; 733 734 status = "okay"; 735 736 ports { 737 port { 738 vin4_in: endpoint { 739 pclk-sample = <0>; 740 hsync-active = <0>; 741 vsync-active = <0>; 742 remote-endpoint = <&adv7612_out>; 743 }; 744 }; 745 }; 746}; 747