1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the Condor board with R-Car V3H 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 serial0 = &scif0; 19 ethernet0 = &gether; 20 }; 21 22 chosen { 23 stdout-path = "serial0:115200n8"; 24 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 25 }; 26 27 d1_8v: regulator-2 { 28 compatible = "regulator-fixed"; 29 regulator-name = "D1.8V"; 30 regulator-min-microvolt = <1800000>; 31 regulator-max-microvolt = <1800000>; 32 regulator-boot-on; 33 regulator-always-on; 34 }; 35 36 d3_3v: regulator-0 { 37 compatible = "regulator-fixed"; 38 regulator-name = "D3.3V"; 39 regulator-min-microvolt = <3300000>; 40 regulator-max-microvolt = <3300000>; 41 regulator-boot-on; 42 regulator-always-on; 43 }; 44 45 hdmi-out { 46 compatible = "hdmi-connector"; 47 type = "a"; 48 49 port { 50 hdmi_con: endpoint { 51 remote-endpoint = <&adv7511_out>; 52 }; 53 }; 54 }; 55 56 lvds-decoder { 57 compatible = "thine,thc63lvd1024"; 58 vcc-supply = <&d3_3v>; 59 60 ports { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 64 port@0 { 65 reg = <0>; 66 thc63lvd1024_in: endpoint { 67 remote-endpoint = <&lvds0_out>; 68 }; 69 }; 70 71 port@2 { 72 reg = <2>; 73 thc63lvd1024_out: endpoint { 74 remote-endpoint = <&adv7511_in>; 75 }; 76 }; 77 }; 78 }; 79 80 memory@48000000 { 81 device_type = "memory"; 82 /* first 128MB is reserved for secure area. */ 83 reg = <0 0x48000000 0 0x78000000>; 84 }; 85 86 vddq_vin01: regulator-1 { 87 compatible = "regulator-fixed"; 88 regulator-name = "VDDQ_VIN01"; 89 regulator-min-microvolt = <1800000>; 90 regulator-max-microvolt = <1800000>; 91 regulator-boot-on; 92 regulator-always-on; 93 }; 94 95 x1_clk: x1-clock { 96 compatible = "fixed-clock"; 97 #clock-cells = <0>; 98 clock-frequency = <148500000>; 99 }; 100}; 101 102&canfd { 103 pinctrl-0 = <&canfd0_pins>; 104 pinctrl-names = "default"; 105 status = "okay"; 106 107 channel0 { 108 status = "okay"; 109 }; 110}; 111 112&csi40 { 113 status = "okay"; 114 115 ports { 116 port@0 { 117 csi40_in: endpoint { 118 clock-lanes = <0>; 119 data-lanes = <1 2 3 4>; 120 remote-endpoint = <&max9286_out0>; 121 }; 122 }; 123 }; 124}; 125 126&csi41 { 127 status = "okay"; 128 129 ports { 130 port@0 { 131 csi41_in: endpoint { 132 clock-lanes = <0>; 133 data-lanes = <1 2 3 4>; 134 remote-endpoint = <&max9286_out1>; 135 }; 136 }; 137 }; 138}; 139 140&du { 141 clocks = <&cpg CPG_MOD 724>, 142 <&x1_clk>; 143 clock-names = "du.0", "dclkin.0"; 144 status = "okay"; 145}; 146 147&extal_clk { 148 clock-frequency = <16666666>; 149}; 150 151&extalr_clk { 152 clock-frequency = <32768>; 153}; 154 155&gether { 156 pinctrl-0 = <&gether_pins>; 157 pinctrl-names = "default"; 158 159 phy-mode = "rgmii-id"; 160 phy-handle = <&phy0>; 161 renesas,no-ether-link; 162 status = "okay"; 163 164 phy0: ethernet-phy@0 { 165 compatible = "ethernet-phy-id0022.1622", 166 "ethernet-phy-ieee802.3-c22"; 167 rxc-skew-ps = <1500>; 168 reg = <0>; 169 interrupts-extended = <&gpio4 23 IRQ_TYPE_LEVEL_LOW>; 170 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 171 }; 172}; 173 174&i2c0 { 175 pinctrl-0 = <&i2c0_pins>; 176 pinctrl-names = "default"; 177 178 status = "okay"; 179 clock-frequency = <400000>; 180 181 io_expander0: gpio@20 { 182 compatible = "onnn,pca9654"; 183 reg = <0x20>; 184 gpio-controller; 185 #gpio-cells = <2>; 186 }; 187 188 io_expander1: gpio@21 { 189 compatible = "onnn,pca9654"; 190 reg = <0x21>; 191 gpio-controller; 192 #gpio-cells = <2>; 193 }; 194 195 hdmi@39 { 196 compatible = "adi,adv7511w"; 197 reg = <0x39>; 198 interrupts-extended = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; 199 avdd-supply = <&d1_8v>; 200 dvdd-supply = <&d1_8v>; 201 pvdd-supply = <&d1_8v>; 202 bgvdd-supply = <&d1_8v>; 203 dvdd-3v-supply = <&d3_3v>; 204 205 adi,input-depth = <8>; 206 adi,input-colorspace = "rgb"; 207 adi,input-clock = "1x"; 208 209 ports { 210 #address-cells = <1>; 211 #size-cells = <0>; 212 213 port@0 { 214 reg = <0>; 215 adv7511_in: endpoint { 216 remote-endpoint = <&thc63lvd1024_out>; 217 }; 218 }; 219 220 port@1 { 221 reg = <1>; 222 adv7511_out: endpoint { 223 remote-endpoint = <&hdmi_con>; 224 }; 225 }; 226 }; 227 }; 228 229 eeprom@50 { 230 compatible = "rohm,br24t01", "atmel,24c01"; 231 reg = <0x50>; 232 pagesize = <8>; 233 }; 234}; 235 236&i2c1 { 237 pinctrl-0 = <&i2c1_pins>; 238 pinctrl-names = "default"; 239 240 status = "okay"; 241 clock-frequency = <400000>; 242 243 gmsl0: gmsl-deserializer@48 { 244 compatible = "maxim,max9286"; 245 reg = <0x48>; 246 247 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; 248 enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>; 249 250 ports { 251 #address-cells = <1>; 252 #size-cells = <0>; 253 254 port@0 { 255 reg = <0>; 256 }; 257 258 port@1 { 259 reg = <1>; 260 }; 261 262 port@2 { 263 reg = <2>; 264 }; 265 266 port@3 { 267 reg = <3>; 268 }; 269 270 port@4 { 271 reg = <4>; 272 max9286_out0: endpoint { 273 clock-lanes = <0>; 274 data-lanes = <1 2 3 4>; 275 remote-endpoint = <&csi40_in>; 276 }; 277 }; 278 }; 279 280 i2c-mux { 281 #address-cells = <1>; 282 #size-cells = <0>; 283 284 i2c@0 { 285 #address-cells = <1>; 286 #size-cells = <0>; 287 reg = <0>; 288 289 status = "disabled"; 290 }; 291 292 i2c@1 { 293 #address-cells = <1>; 294 #size-cells = <0>; 295 reg = <1>; 296 297 status = "disabled"; 298 }; 299 300 i2c@2 { 301 #address-cells = <1>; 302 #size-cells = <0>; 303 reg = <2>; 304 305 status = "disabled"; 306 }; 307 308 i2c@3 { 309 #address-cells = <1>; 310 #size-cells = <0>; 311 reg = <3>; 312 313 status = "disabled"; 314 }; 315 }; 316 }; 317 318 gmsl1: gmsl-deserializer@4a { 319 compatible = "maxim,max9286"; 320 reg = <0x4a>; 321 322 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; 323 enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>; 324 325 ports { 326 #address-cells = <1>; 327 #size-cells = <0>; 328 329 port@0 { 330 reg = <0>; 331 }; 332 333 port@1 { 334 reg = <1>; 335 }; 336 337 port@2 { 338 reg = <2>; 339 }; 340 341 port@3 { 342 reg = <3>; 343 }; 344 345 port@4 { 346 reg = <4>; 347 max9286_out1: endpoint { 348 clock-lanes = <0>; 349 data-lanes = <1 2 3 4>; 350 remote-endpoint = <&csi41_in>; 351 }; 352 }; 353 }; 354 355 i2c-mux { 356 #address-cells = <1>; 357 #size-cells = <0>; 358 359 i2c@0 { 360 #address-cells = <1>; 361 #size-cells = <0>; 362 reg = <0>; 363 364 status = "disabled"; 365 }; 366 367 i2c@1 { 368 #address-cells = <1>; 369 #size-cells = <0>; 370 reg = <1>; 371 372 status = "disabled"; 373 }; 374 375 i2c@2 { 376 #address-cells = <1>; 377 #size-cells = <0>; 378 reg = <2>; 379 380 status = "disabled"; 381 }; 382 383 i2c@3 { 384 #address-cells = <1>; 385 #size-cells = <0>; 386 reg = <3>; 387 388 status = "disabled"; 389 }; 390 }; 391 }; 392}; 393 394&lvds0 { 395 status = "okay"; 396 397 ports { 398 port@1 { 399 lvds0_out: endpoint { 400 remote-endpoint = <&thc63lvd1024_in>; 401 }; 402 }; 403 }; 404}; 405 406&mmc0 { 407 pinctrl-0 = <&mmc_pins>; 408 pinctrl-1 = <&mmc_pins>; 409 pinctrl-names = "default", "state_uhs"; 410 411 vmmc-supply = <&d3_3v>; 412 vqmmc-supply = <&vddq_vin01>; 413 mmc-hs200-1_8v; 414 bus-width = <8>; 415 no-sd; 416 no-sdio; 417 non-removable; 418 status = "okay"; 419}; 420 421&pciec { 422 status = "okay"; 423}; 424 425&pcie_bus_clk { 426 clock-frequency = <100000000>; 427}; 428 429&pcie_phy { 430 status = "okay"; 431}; 432 433&pfc { 434 canfd0_pins: canfd0 { 435 groups = "canfd0_data_a"; 436 function = "canfd0"; 437 }; 438 439 gether_pins: gether { 440 groups = "gether_mdio_a", "gether_rgmii", 441 "gether_txcrefclk", "gether_txcrefclk_mega"; 442 function = "gether"; 443 }; 444 445 i2c0_pins: i2c0 { 446 groups = "i2c0"; 447 function = "i2c0"; 448 }; 449 450 i2c1_pins: i2c1 { 451 groups = "i2c1"; 452 function = "i2c1"; 453 }; 454 455 mmc_pins: mmc { 456 groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; 457 function = "mmc"; 458 power-source = <1800>; 459 }; 460 461 qspi0_pins: qspi0 { 462 groups = "qspi0_ctrl", "qspi0_data4"; 463 function = "qspi0"; 464 }; 465 466 scif0_pins: scif0 { 467 groups = "scif0_data"; 468 function = "scif0"; 469 }; 470 471 scif_clk_pins: scif_clk { 472 groups = "scif_clk_b"; 473 function = "scif_clk"; 474 }; 475}; 476 477&rpc { 478 pinctrl-0 = <&qspi0_pins>; 479 pinctrl-names = "default"; 480 481 status = "okay"; 482 483 flash@0 { 484 compatible = "spansion,s25fs512s", "jedec,spi-nor"; 485 reg = <0>; 486 spi-max-frequency = <50000000>; 487 spi-rx-bus-width = <4>; 488 489 partitions { 490 compatible = "fixed-partitions"; 491 #address-cells = <1>; 492 #size-cells = <1>; 493 494 bootparam@0 { 495 reg = <0x00000000 0x040000>; 496 read-only; 497 }; 498 cr7@40000 { 499 reg = <0x00040000 0x080000>; 500 read-only; 501 }; 502 cert_header_sa3@c0000 { 503 reg = <0x000c0000 0x080000>; 504 read-only; 505 }; 506 bl2@140000 { 507 reg = <0x00140000 0x040000>; 508 read-only; 509 }; 510 cert_header_sa6@180000 { 511 reg = <0x00180000 0x040000>; 512 read-only; 513 }; 514 bl31@1c0000 { 515 reg = <0x001c0000 0x460000>; 516 read-only; 517 }; 518 uboot@640000 { 519 reg = <0x00640000 0x0c0000>; 520 read-only; 521 }; 522 uboot-env@700000 { 523 reg = <0x00700000 0x040000>; 524 read-only; 525 }; 526 dtb@740000 { 527 reg = <0x00740000 0x080000>; 528 }; 529 kernel@7c0000 { 530 reg = <0x007c0000 0x1400000>; 531 }; 532 user@1bc0000 { 533 reg = <0x01bc0000 0x2440000>; 534 }; 535 }; 536 }; 537}; 538 539&rwdt { 540 timeout-sec = <60>; 541 status = "okay"; 542}; 543 544&scif0 { 545 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; 546 pinctrl-names = "default"; 547 548 status = "okay"; 549}; 550 551&scif_clk { 552 clock-frequency = <14745600>; 553}; 554