1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) 2/* 3 * Realtek RTD16xx SoC family 4 * 5 * Copyright (c) 2019 Realtek Semiconductor Corp. 6 * Copyright (c) 2019 Andreas Färber 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 interrupt-parent = <&gic>; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 reserved-memory { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 ranges; 21 22 rpc_comm: rpc@2f000 { 23 reg = <0x2f000 0x1000>; 24 }; 25 26 rpc_ringbuf: rpc@1ffe000 { 27 reg = <0x1ffe000 0x4000>; 28 }; 29 30 tee: tee@10100000 { 31 reg = <0x10100000 0xf00000>; 32 no-map; 33 }; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a55"; 43 reg = <0x0>; 44 enable-method = "psci"; 45 next-level-cache = <&l2>; 46 }; 47 48 cpu1: cpu@100 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a55"; 51 reg = <0x100>; 52 enable-method = "psci"; 53 next-level-cache = <&l3>; 54 }; 55 56 cpu2: cpu@200 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a55"; 59 reg = <0x200>; 60 enable-method = "psci"; 61 next-level-cache = <&l3>; 62 }; 63 64 cpu3: cpu@300 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a55"; 67 reg = <0x300>; 68 enable-method = "psci"; 69 next-level-cache = <&l3>; 70 }; 71 72 cpu4: cpu@400 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x400>; 76 enable-method = "psci"; 77 next-level-cache = <&l3>; 78 }; 79 80 cpu5: cpu@500 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x500>; 84 enable-method = "psci"; 85 next-level-cache = <&l3>; 86 }; 87 88 l2: l2-cache { 89 compatible = "cache"; 90 next-level-cache = <&l3>; 91 92 }; 93 94 l3: l3-cache { 95 compatible = "cache"; 96 }; 97 }; 98 99 timer { 100 compatible = "arm,armv8-timer"; 101 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 102 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 103 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 104 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 105 }; 106 107 arm_pmu: pmu { 108 compatible = "arm,armv8-pmuv3"; 109 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 110 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, 111 <&cpu3>, <&cpu4>, <&cpu5>; 112 }; 113 114 psci { 115 compatible = "arm,psci-1.0"; 116 method = "smc"; 117 }; 118 119 osc27M: osc { 120 compatible = "fixed-clock"; 121 clock-frequency = <27000000>; 122 clock-output-names = "osc27M"; 123 #clock-cells = <0>; 124 }; 125 126 soc { 127 compatible = "simple-bus"; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 ranges = <0x00000000 0x00000000 0x0002e000>, /* boot ROM */ 131 <0x98000000 0x98000000 0x68000000>; 132 133 rbus: bus@98000000 { 134 compatible = "simple-bus"; 135 reg = <0x98000000 0x200000>; 136 #address-cells = <1>; 137 #size-cells = <1>; 138 ranges = <0x0 0x98000000 0x200000>; 139 140 crt: syscon@0 { 141 compatible = "syscon", "simple-mfd"; 142 reg = <0x0 0x1000>; 143 reg-io-width = <4>; 144 #address-cells = <1>; 145 #size-cells = <1>; 146 ranges = <0x0 0x0 0x1000>; 147 }; 148 149 iso: syscon@7000 { 150 compatible = "syscon", "simple-mfd"; 151 reg = <0x7000 0x1000>; 152 reg-io-width = <4>; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 ranges = <0x0 0x7000 0x1000>; 156 }; 157 158 sb2: syscon@1a000 { 159 compatible = "syscon", "simple-mfd"; 160 reg = <0x1a000 0x1000>; 161 reg-io-width = <4>; 162 #address-cells = <1>; 163 #size-cells = <1>; 164 ranges = <0x0 0x1a000 0x1000>; 165 }; 166 167 misc: syscon@1b000 { 168 compatible = "syscon", "simple-mfd"; 169 reg = <0x1b000 0x1000>; 170 reg-io-width = <4>; 171 #address-cells = <1>; 172 #size-cells = <1>; 173 ranges = <0x0 0x1b000 0x1000>; 174 }; 175 176 scpu_wrapper: syscon@1d000 { 177 compatible = "syscon", "simple-mfd"; 178 reg = <0x1d000 0x1000>; 179 reg-io-width = <4>; 180 #address-cells = <1>; 181 #size-cells = <1>; 182 ranges = <0x0 0x1d000 0x1000>; 183 }; 184 }; 185 186 gic: interrupt-controller@ff100000 { 187 compatible = "arm,gic-v3"; 188 reg = <0xff100000 0x10000>, 189 <0xff140000 0xc0000>; 190 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 191 interrupt-controller; 192 #interrupt-cells = <3>; 193 }; 194 }; 195}; 196 197&iso { 198 uart0: serial@800 { 199 compatible = "snps,dw-apb-uart"; 200 reg = <0x800 0x400>; 201 reg-shift = <2>; 202 reg-io-width = <4>; 203 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 204 clock-frequency = <27000000>; 205 status = "disabled"; 206 }; 207}; 208 209&misc { 210 uart1: serial@200 { 211 compatible = "snps,dw-apb-uart"; 212 reg = <0x200 0x400>; 213 reg-shift = <2>; 214 reg-io-width = <4>; 215 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 216 clock-frequency = <432000000>; 217 status = "disabled"; 218 }; 219 220 uart2: serial@400 { 221 compatible = "snps,dw-apb-uart"; 222 reg = <0x400 0x400>; 223 reg-shift = <2>; 224 reg-io-width = <4>; 225 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 226 clock-frequency = <432000000>; 227 status = "disabled"; 228 }; 229}; 230