1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) 2/* 3 * Realtek RTD1395 SoC family 4 * 5 * Copyright (c) 2019 Andreas Färber 6 */ 7 8/memreserve/ 0x0000000000000000 0x000000000002f000; 9/memreserve/ 0x000000000002f000 0x00000000000d1000; 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/realtek,rtd1295.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 reserved-memory { 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges; 23 24 rpc_comm: rpc@2f000 { 25 reg = <0x2f000 0x1000>; 26 }; 27 28 rpc_ringbuf: rpc@1ffe000 { 29 reg = <0x1ffe000 0x4000>; 30 }; 31 32 tee: tee@10100000 { 33 reg = <0x10100000 0xf00000>; 34 no-map; 35 }; 36 }; 37 38 arm_pmu: arm-pmu { 39 compatible = "arm,cortex-a53-pmu"; 40 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 41 }; 42 43 osc27M: osc { 44 compatible = "fixed-clock"; 45 clock-frequency = <27000000>; 46 #clock-cells = <0>; 47 clock-output-names = "osc27M"; 48 }; 49 50 soc { 51 compatible = "simple-bus"; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */ 55 <0x98000000 0x98000000 0x68000000>; 56 57 rbus: bus@98000000 { 58 compatible = "simple-bus"; 59 reg = <0x98000000 0x200000>; 60 #address-cells = <1>; 61 #size-cells = <1>; 62 ranges = <0x0 0x98000000 0x200000>; 63 64 crt: syscon@0 { 65 compatible = "syscon", "simple-mfd"; 66 reg = <0x0 0x1000>; 67 reg-io-width = <4>; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 ranges = <0x0 0x0 0x1000>; 71 }; 72 73 iso: syscon@7000 { 74 compatible = "syscon", "simple-mfd"; 75 reg = <0x7000 0x1000>; 76 reg-io-width = <4>; 77 #address-cells = <1>; 78 #size-cells = <1>; 79 ranges = <0x0 0x7000 0x1000>; 80 }; 81 82 misc: syscon@1b000 { 83 compatible = "syscon", "simple-mfd"; 84 reg = <0x1b000 0x1000>; 85 reg-io-width = <4>; 86 #address-cells = <1>; 87 #size-cells = <1>; 88 ranges = <0x0 0x1b000 0x1000>; 89 }; 90 }; 91 92 gic: interrupt-controller@ff011000 { 93 compatible = "arm,gic-400"; 94 reg = <0xff011000 0x1000>, 95 <0xff012000 0x2000>, 96 <0xff014000 0x2000>, 97 <0xff016000 0x2000>; 98 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 99 interrupt-controller; 100 #interrupt-cells = <3>; 101 }; 102 }; 103}; 104 105&crt { 106 reset1: reset-controller@0 { 107 compatible = "snps,dw-low-reset"; 108 reg = <0x0 0x4>; 109 #reset-cells = <1>; 110 }; 111 112 reset2: reset-controller@4 { 113 compatible = "snps,dw-low-reset"; 114 reg = <0x4 0x4>; 115 #reset-cells = <1>; 116 }; 117 118 reset3: reset-controller@8 { 119 compatible = "snps,dw-low-reset"; 120 reg = <0x8 0x4>; 121 #reset-cells = <1>; 122 }; 123 124 reset4: reset-controller@50 { 125 compatible = "snps,dw-low-reset"; 126 reg = <0x50 0x4>; 127 #reset-cells = <1>; 128 }; 129}; 130 131&iso { 132 iso_reset: reset-controller@88 { 133 compatible = "snps,dw-low-reset"; 134 reg = <0x88 0x4>; 135 #reset-cells = <1>; 136 }; 137 138 wdt: watchdog@680 { 139 compatible = "realtek,rtd1295-watchdog"; 140 reg = <0x680 0x100>; 141 clocks = <&osc27M>; 142 }; 143 144 uart0: serial@800 { 145 compatible = "snps,dw-apb-uart"; 146 reg = <0x800 0x400>; 147 reg-shift = <2>; 148 reg-io-width = <4>; 149 clock-frequency = <27000000>; 150 resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; 151 status = "disabled"; 152 }; 153}; 154 155&misc { 156 uart1: serial@200 { 157 compatible = "snps,dw-apb-uart"; 158 reg = <0x200 0x100>; 159 reg-shift = <2>; 160 reg-io-width = <4>; 161 clock-frequency = <432000000>; 162 resets = <&reset2 RTD1295_RSTN_UR1>; 163 status = "disabled"; 164 }; 165 166 uart2: serial@400 { 167 compatible = "snps,dw-apb-uart"; 168 reg = <0x400 0x100>; 169 reg-shift = <2>; 170 reg-io-width = <4>; 171 clock-frequency = <432000000>; 172 resets = <&reset2 RTD1295_RSTN_UR2>; 173 status = "disabled"; 174 }; 175}; 176