1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) 2/* 3 * Realtek RTD1395 SoC family 4 * 5 * Copyright (c) 2019 Andreas Färber 6 */ 7 8/memreserve/ 0x0000000000000000 0x000000000002f000; 9/memreserve/ 0x000000000002f000 0x00000000000d1000; 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/realtek,rtd1295.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 reserved-memory { 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges; 23 24 rpc_comm: rpc@2f000 { 25 reg = <0x2f000 0x1000>; 26 }; 27 28 rpc_ringbuf: rpc@1ffe000 { 29 reg = <0x1ffe000 0x4000>; 30 }; 31 32 tee: tee@10100000 { 33 reg = <0x10100000 0xf00000>; 34 no-map; 35 }; 36 }; 37 38 arm_pmu: arm-pmu { 39 compatible = "arm,cortex-a53-pmu"; 40 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 41 }; 42 43 osc27M: osc { 44 compatible = "fixed-clock"; 45 clock-frequency = <27000000>; 46 #clock-cells = <0>; 47 clock-output-names = "osc27M"; 48 }; 49 50 soc { 51 compatible = "simple-bus"; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */ 55 <0x98000000 0x98000000 0x68000000>; 56 57 rbus: bus@98000000 { 58 compatible = "simple-bus"; 59 reg = <0x98000000 0x200000>; 60 #address-cells = <1>; 61 #size-cells = <1>; 62 ranges = <0x0 0x98000000 0x200000>; 63 64 reset1: reset-controller@0 { 65 compatible = "snps,dw-low-reset"; 66 reg = <0x0 0x4>; 67 #reset-cells = <1>; 68 }; 69 70 reset2: reset-controller@4 { 71 compatible = "snps,dw-low-reset"; 72 reg = <0x4 0x4>; 73 #reset-cells = <1>; 74 }; 75 76 reset3: reset-controller@8 { 77 compatible = "snps,dw-low-reset"; 78 reg = <0x8 0x4>; 79 #reset-cells = <1>; 80 }; 81 82 reset4: reset-controller@50 { 83 compatible = "snps,dw-low-reset"; 84 reg = <0x50 0x4>; 85 #reset-cells = <1>; 86 }; 87 88 iso_reset: reset-controller@7088 { 89 compatible = "snps,dw-low-reset"; 90 reg = <0x7088 0x4>; 91 #reset-cells = <1>; 92 }; 93 94 wdt: watchdog@7680 { 95 compatible = "realtek,rtd1295-watchdog"; 96 reg = <0x7680 0x100>; 97 clocks = <&osc27M>; 98 }; 99 100 uart0: serial@7800 { 101 compatible = "snps,dw-apb-uart"; 102 reg = <0x7800 0x400>; 103 reg-shift = <2>; 104 reg-io-width = <4>; 105 clock-frequency = <27000000>; 106 resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; 107 status = "disabled"; 108 }; 109 110 uart1: serial@1b200 { 111 compatible = "snps,dw-apb-uart"; 112 reg = <0x1b200 0x100>; 113 reg-shift = <2>; 114 reg-io-width = <4>; 115 clock-frequency = <432000000>; 116 resets = <&reset2 RTD1295_RSTN_UR1>; 117 status = "disabled"; 118 }; 119 120 uart2: serial@1b400 { 121 compatible = "snps,dw-apb-uart"; 122 reg = <0x1b400 0x100>; 123 reg-shift = <2>; 124 reg-io-width = <4>; 125 clock-frequency = <432000000>; 126 resets = <&reset2 RTD1295_RSTN_UR2>; 127 status = "disabled"; 128 }; 129 }; 130 131 gic: interrupt-controller@ff011000 { 132 compatible = "arm,gic-400"; 133 reg = <0xff011000 0x1000>, 134 <0xff012000 0x2000>, 135 <0xff014000 0x2000>, 136 <0xff016000 0x2000>; 137 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 138 interrupt-controller; 139 #interrupt-cells = <3>; 140 }; 141 }; 142}; 143