1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) 2/* 3 * Realtek RTD1293/RTD1295/RTD1296 SoC 4 * 5 * Copyright (c) 2016-2019 Andreas Färber 6 */ 7 8/memreserve/ 0x0000000000000000 0x000000000001f000; 9/memreserve/ 0x000000000001f000 0x00000000000e1000; 10/memreserve/ 0x0000000001b00000 0x00000000004be000; 11 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/realtek,rtd1295.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 reserved-memory { 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges; 24 25 rpc_comm: rpc@1f000 { 26 reg = <0x1f000 0x1000>; 27 }; 28 29 rpc_ringbuf: rpc@1ffe000 { 30 reg = <0x1ffe000 0x4000>; 31 }; 32 33 tee: tee@10100000 { 34 reg = <0x10100000 0xf00000>; 35 no-map; 36 }; 37 }; 38 39 arm_pmu: arm-pmu { 40 compatible = "arm,cortex-a53-pmu"; 41 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 42 }; 43 44 osc27M: osc { 45 compatible = "fixed-clock"; 46 clock-frequency = <27000000>; 47 #clock-cells = <0>; 48 clock-output-names = "osc27M"; 49 }; 50 51 soc { 52 compatible = "simple-bus"; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */ 56 /* Exclude up to 2 GiB of RAM */ 57 <0x80000000 0x80000000 0x80000000>; 58 59 rbus: bus@98000000 { 60 compatible = "simple-bus"; 61 reg = <0x98000000 0x200000>; 62 #address-cells = <1>; 63 #size-cells = <1>; 64 ranges = <0x0 0x98000000 0x200000>; 65 66 crt: syscon@0 { 67 compatible = "syscon", "simple-mfd"; 68 reg = <0x0 0x1800>; 69 reg-io-width = <4>; 70 #address-cells = <1>; 71 #size-cells = <1>; 72 ranges = <0x0 0x0 0x1800>; 73 }; 74 75 iso: syscon@7000 { 76 compatible = "syscon", "simple-mfd"; 77 reg = <0x7000 0x1000>; 78 reg-io-width = <4>; 79 #address-cells = <1>; 80 #size-cells = <1>; 81 ranges = <0x0 0x7000 0x1000>; 82 }; 83 84 sb2: syscon@1a000 { 85 compatible = "syscon", "simple-mfd"; 86 reg = <0x1a000 0x1000>; 87 reg-io-width = <4>; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 ranges = <0x0 0x1a000 0x1000>; 91 }; 92 93 misc: syscon@1b000 { 94 compatible = "syscon", "simple-mfd"; 95 reg = <0x1b000 0x1000>; 96 reg-io-width = <4>; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 ranges = <0x0 0x1b000 0x1000>; 100 }; 101 102 scpu_wrapper: syscon@1d000 { 103 compatible = "syscon", "simple-mfd"; 104 reg = <0x1d000 0x2000>; 105 reg-io-width = <4>; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 ranges = <0x0 0x1d000 0x2000>; 109 }; 110 }; 111 112 gic: interrupt-controller@ff011000 { 113 compatible = "arm,gic-400"; 114 reg = <0xff011000 0x1000>, 115 <0xff012000 0x2000>, 116 <0xff014000 0x2000>, 117 <0xff016000 0x2000>; 118 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 119 interrupt-controller; 120 #interrupt-cells = <3>; 121 }; 122 }; 123}; 124 125&crt { 126 reset1: reset-controller@0 { 127 compatible = "snps,dw-low-reset"; 128 reg = <0x0 0x4>; 129 #reset-cells = <1>; 130 }; 131 132 reset2: reset-controller@4 { 133 compatible = "snps,dw-low-reset"; 134 reg = <0x4 0x4>; 135 #reset-cells = <1>; 136 }; 137 138 reset3: reset-controller@8 { 139 compatible = "snps,dw-low-reset"; 140 reg = <0x8 0x4>; 141 #reset-cells = <1>; 142 }; 143 144 reset4: reset-controller@50 { 145 compatible = "snps,dw-low-reset"; 146 reg = <0x50 0x4>; 147 #reset-cells = <1>; 148 }; 149}; 150 151&iso { 152 iso_reset: reset-controller@88 { 153 compatible = "snps,dw-low-reset"; 154 reg = <0x88 0x4>; 155 #reset-cells = <1>; 156 }; 157 158 wdt: watchdog@680 { 159 compatible = "realtek,rtd1295-watchdog"; 160 reg = <0x680 0x100>; 161 clocks = <&osc27M>; 162 }; 163 164 uart0: serial@800 { 165 compatible = "snps,dw-apb-uart"; 166 reg = <0x800 0x400>; 167 reg-shift = <2>; 168 reg-io-width = <4>; 169 clock-frequency = <27000000>; 170 resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; 171 status = "disabled"; 172 }; 173}; 174 175&misc { 176 uart1: serial@200 { 177 compatible = "snps,dw-apb-uart"; 178 reg = <0x200 0x100>; 179 reg-shift = <2>; 180 reg-io-width = <4>; 181 clock-frequency = <432000000>; 182 resets = <&reset2 RTD1295_RSTN_UR1>; 183 status = "disabled"; 184 }; 185 186 uart2: serial@400 { 187 compatible = "snps,dw-apb-uart"; 188 reg = <0x400 0x100>; 189 reg-shift = <2>; 190 reg-io-width = <4>; 191 clock-frequency = <432000000>; 192 resets = <&reset2 RTD1295_RSTN_UR2>; 193 status = "disabled"; 194 }; 195}; 196