1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 8#include <dt-bindings/clock/qcom,x1e80100-gcc.h> 9#include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/interconnect/qcom,icc.h> 12#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/phy/phy-qcom-qmp.h> 16#include <dt-bindings/power/qcom,rpmhpd.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,gpr.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 clock-frequency = <76800000>; 34 #clock-cells = <0>; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 clock-frequency = <32000>; 40 #clock-cells = <0>; 41 }; 42 43 bi_tcxo_div2: bi-tcxo-div2-clk { 44 compatible = "fixed-factor-clock"; 45 #clock-cells = <0>; 46 47 clocks = <&rpmhcc RPMH_CXO_CLK>; 48 clock-mult = <1>; 49 clock-div = <2>; 50 }; 51 52 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 53 compatible = "fixed-factor-clock"; 54 #clock-cells = <0>; 55 56 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 57 clock-mult = <1>; 58 clock-div = <2>; 59 }; 60 }; 61 62 cpus { 63 #address-cells = <2>; 64 #size-cells = <0>; 65 66 CPU0: cpu@0 { 67 device_type = "cpu"; 68 compatible = "qcom,oryon"; 69 reg = <0x0 0x0>; 70 enable-method = "psci"; 71 next-level-cache = <&L2_0>; 72 power-domains = <&CPU_PD0>; 73 power-domain-names = "psci"; 74 cpu-idle-states = <&CLUSTER_C4>; 75 76 L2_0: l2-cache { 77 compatible = "cache"; 78 cache-level = <2>; 79 cache-unified; 80 }; 81 }; 82 83 CPU1: cpu@100 { 84 device_type = "cpu"; 85 compatible = "qcom,oryon"; 86 reg = <0x0 0x100>; 87 enable-method = "psci"; 88 next-level-cache = <&L2_0>; 89 power-domains = <&CPU_PD1>; 90 power-domain-names = "psci"; 91 cpu-idle-states = <&CLUSTER_C4>; 92 }; 93 94 CPU2: cpu@200 { 95 device_type = "cpu"; 96 compatible = "qcom,oryon"; 97 reg = <0x0 0x200>; 98 enable-method = "psci"; 99 next-level-cache = <&L2_0>; 100 power-domains = <&CPU_PD2>; 101 power-domain-names = "psci"; 102 cpu-idle-states = <&CLUSTER_C4>; 103 }; 104 105 CPU3: cpu@300 { 106 device_type = "cpu"; 107 compatible = "qcom,oryon"; 108 reg = <0x0 0x300>; 109 enable-method = "psci"; 110 next-level-cache = <&L2_0>; 111 power-domains = <&CPU_PD3>; 112 power-domain-names = "psci"; 113 cpu-idle-states = <&CLUSTER_C4>; 114 }; 115 116 CPU4: cpu@10000 { 117 device_type = "cpu"; 118 compatible = "qcom,oryon"; 119 reg = <0x0 0x10000>; 120 enable-method = "psci"; 121 next-level-cache = <&L2_1>; 122 power-domains = <&CPU_PD4>; 123 power-domain-names = "psci"; 124 cpu-idle-states = <&CLUSTER_C4>; 125 126 L2_1: l2-cache { 127 compatible = "cache"; 128 cache-level = <2>; 129 cache-unified; 130 }; 131 }; 132 133 CPU5: cpu@10100 { 134 device_type = "cpu"; 135 compatible = "qcom,oryon"; 136 reg = <0x0 0x10100>; 137 enable-method = "psci"; 138 next-level-cache = <&L2_1>; 139 power-domains = <&CPU_PD5>; 140 power-domain-names = "psci"; 141 cpu-idle-states = <&CLUSTER_C4>; 142 }; 143 144 CPU6: cpu@10200 { 145 device_type = "cpu"; 146 compatible = "qcom,oryon"; 147 reg = <0x0 0x10200>; 148 enable-method = "psci"; 149 next-level-cache = <&L2_1>; 150 power-domains = <&CPU_PD6>; 151 power-domain-names = "psci"; 152 cpu-idle-states = <&CLUSTER_C4>; 153 }; 154 155 CPU7: cpu@10300 { 156 device_type = "cpu"; 157 compatible = "qcom,oryon"; 158 reg = <0x0 0x10300>; 159 enable-method = "psci"; 160 next-level-cache = <&L2_1>; 161 power-domains = <&CPU_PD7>; 162 power-domain-names = "psci"; 163 cpu-idle-states = <&CLUSTER_C4>; 164 }; 165 166 CPU8: cpu@20000 { 167 device_type = "cpu"; 168 compatible = "qcom,oryon"; 169 reg = <0x0 0x20000>; 170 enable-method = "psci"; 171 next-level-cache = <&L2_2>; 172 power-domains = <&CPU_PD8>; 173 power-domain-names = "psci"; 174 cpu-idle-states = <&CLUSTER_C4>; 175 176 L2_2: l2-cache { 177 compatible = "cache"; 178 cache-level = <2>; 179 cache-unified; 180 }; 181 }; 182 183 CPU9: cpu@20100 { 184 device_type = "cpu"; 185 compatible = "qcom,oryon"; 186 reg = <0x0 0x20100>; 187 enable-method = "psci"; 188 next-level-cache = <&L2_2>; 189 power-domains = <&CPU_PD9>; 190 power-domain-names = "psci"; 191 cpu-idle-states = <&CLUSTER_C4>; 192 }; 193 194 CPU10: cpu@20200 { 195 device_type = "cpu"; 196 compatible = "qcom,oryon"; 197 reg = <0x0 0x20200>; 198 enable-method = "psci"; 199 next-level-cache = <&L2_2>; 200 power-domains = <&CPU_PD10>; 201 power-domain-names = "psci"; 202 cpu-idle-states = <&CLUSTER_C4>; 203 }; 204 205 CPU11: cpu@20300 { 206 device_type = "cpu"; 207 compatible = "qcom,oryon"; 208 reg = <0x0 0x20300>; 209 enable-method = "psci"; 210 next-level-cache = <&L2_2>; 211 power-domains = <&CPU_PD11>; 212 power-domain-names = "psci"; 213 cpu-idle-states = <&CLUSTER_C4>; 214 }; 215 216 cpu-map { 217 cluster0 { 218 core0 { 219 cpu = <&CPU0>; 220 }; 221 222 core1 { 223 cpu = <&CPU1>; 224 }; 225 226 core2 { 227 cpu = <&CPU2>; 228 }; 229 230 core3 { 231 cpu = <&CPU3>; 232 }; 233 }; 234 235 cluster1 { 236 core0 { 237 cpu = <&CPU4>; 238 }; 239 240 core1 { 241 cpu = <&CPU5>; 242 }; 243 244 core2 { 245 cpu = <&CPU6>; 246 }; 247 248 core3 { 249 cpu = <&CPU7>; 250 }; 251 }; 252 253 cluster2 { 254 core0 { 255 cpu = <&CPU8>; 256 }; 257 258 core1 { 259 cpu = <&CPU9>; 260 }; 261 262 core2 { 263 cpu = <&CPU10>; 264 }; 265 266 core3 { 267 cpu = <&CPU11>; 268 }; 269 }; 270 }; 271 272 idle-states { 273 entry-method = "psci"; 274 275 CLUSTER_C4: cpu-sleep-0 { 276 compatible = "arm,idle-state"; 277 idle-state-name = "ret"; 278 arm,psci-suspend-param = <0x00000004>; 279 entry-latency-us = <180>; 280 exit-latency-us = <320>; 281 min-residency-us = <1000>; 282 }; 283 }; 284 285 domain-idle-states { 286 CLUSTER_CL4: cluster-sleep-0 { 287 compatible = "domain-idle-state"; 288 idle-state-name = "l2-ret"; 289 arm,psci-suspend-param = <0x01000044>; 290 entry-latency-us = <350>; 291 exit-latency-us = <500>; 292 min-residency-us = <2500>; 293 }; 294 295 CLUSTER_CL5: cluster-sleep-1 { 296 compatible = "domain-idle-state"; 297 idle-state-name = "ret-pll-off"; 298 arm,psci-suspend-param = <0x01000054>; 299 entry-latency-us = <2200>; 300 exit-latency-us = <2500>; 301 min-residency-us = <7000>; 302 }; 303 }; 304 }; 305 306 firmware { 307 scm: scm { 308 compatible = "qcom,scm-x1e80100", "qcom,scm"; 309 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 310 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 311 }; 312 }; 313 314 clk_virt: interconnect-0 { 315 compatible = "qcom,x1e80100-clk-virt"; 316 #interconnect-cells = <2>; 317 qcom,bcm-voters = <&apps_bcm_voter>; 318 }; 319 320 mc_virt: interconnect-1 { 321 compatible = "qcom,x1e80100-mc-virt"; 322 #interconnect-cells = <2>; 323 qcom,bcm-voters = <&apps_bcm_voter>; 324 }; 325 326 memory@80000000 { 327 device_type = "memory"; 328 /* We expect the bootloader to fill in the size */ 329 reg = <0 0x80000000 0 0>; 330 }; 331 332 pmu { 333 compatible = "arm,armv8-pmuv3"; 334 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 335 }; 336 337 psci { 338 compatible = "arm,psci-1.0"; 339 method = "smc"; 340 341 CPU_PD0: power-domain-cpu0 { 342 #power-domain-cells = <0>; 343 power-domains = <&CLUSTER_PD0>; 344 }; 345 346 CPU_PD1: power-domain-cpu1 { 347 #power-domain-cells = <0>; 348 power-domains = <&CLUSTER_PD0>; 349 }; 350 351 CPU_PD2: power-domain-cpu2 { 352 #power-domain-cells = <0>; 353 power-domains = <&CLUSTER_PD0>; 354 }; 355 356 CPU_PD3: power-domain-cpu3 { 357 #power-domain-cells = <0>; 358 power-domains = <&CLUSTER_PD0>; 359 }; 360 361 CPU_PD4: power-domain-cpu4 { 362 #power-domain-cells = <0>; 363 power-domains = <&CLUSTER_PD1>; 364 }; 365 366 CPU_PD5: power-domain-cpu5 { 367 #power-domain-cells = <0>; 368 power-domains = <&CLUSTER_PD1>; 369 }; 370 371 CPU_PD6: power-domain-cpu6 { 372 #power-domain-cells = <0>; 373 power-domains = <&CLUSTER_PD1>; 374 }; 375 376 CPU_PD7: power-domain-cpu7 { 377 #power-domain-cells = <0>; 378 power-domains = <&CLUSTER_PD1>; 379 }; 380 381 CPU_PD8: power-domain-cpu8 { 382 #power-domain-cells = <0>; 383 power-domains = <&CLUSTER_PD2>; 384 }; 385 386 CPU_PD9: power-domain-cpu9 { 387 #power-domain-cells = <0>; 388 power-domains = <&CLUSTER_PD2>; 389 }; 390 391 CPU_PD10: power-domain-cpu10 { 392 #power-domain-cells = <0>; 393 power-domains = <&CLUSTER_PD2>; 394 }; 395 396 CPU_PD11: power-domain-cpu11 { 397 #power-domain-cells = <0>; 398 power-domains = <&CLUSTER_PD2>; 399 }; 400 401 CLUSTER_PD0: power-domain-cpu-cluster0 { 402 #power-domain-cells = <0>; 403 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 404 power-domains = <&SYSTEM_PD>; 405 }; 406 407 CLUSTER_PD1: power-domain-cpu-cluster1 { 408 #power-domain-cells = <0>; 409 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 410 power-domains = <&SYSTEM_PD>; 411 }; 412 413 CLUSTER_PD2: power-domain-cpu-cluster2 { 414 #power-domain-cells = <0>; 415 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 416 power-domains = <&SYSTEM_PD>; 417 }; 418 419 SYSTEM_PD: power-domain-system { 420 #power-domain-cells = <0>; 421 /* TODO: system-wide idle states */ 422 }; 423 }; 424 425 reserved-memory { 426 #address-cells = <2>; 427 #size-cells = <2>; 428 ranges; 429 430 gunyah_hyp_mem: gunyah-hyp@80000000 { 431 reg = <0x0 0x80000000 0x0 0x800000>; 432 no-map; 433 }; 434 435 hyp_elf_package_mem: hyp-elf-package@80800000 { 436 reg = <0x0 0x80800000 0x0 0x200000>; 437 no-map; 438 }; 439 440 ncc_mem: ncc@80a00000 { 441 reg = <0x0 0x80a00000 0x0 0x400000>; 442 no-map; 443 }; 444 445 cpucp_log_mem: cpucp-log@80e00000 { 446 reg = <0x0 0x80e00000 0x0 0x40000>; 447 no-map; 448 }; 449 450 cpucp_mem: cpucp@80e40000 { 451 reg = <0x0 0x80e40000 0x0 0x540000>; 452 no-map; 453 }; 454 455 reserved-region@81380000 { 456 reg = <0x0 0x81380000 0x0 0x80000>; 457 no-map; 458 }; 459 460 tags_mem: tags-region@81400000 { 461 reg = <0x0 0x81400000 0x0 0x1a0000>; 462 no-map; 463 }; 464 465 xbl_dtlog_mem: xbl-dtlog@81a00000 { 466 reg = <0x0 0x81a00000 0x0 0x40000>; 467 no-map; 468 }; 469 470 xbl_ramdump_mem: xbl-ramdump@81a40000 { 471 reg = <0x0 0x81a40000 0x0 0x1c0000>; 472 no-map; 473 }; 474 475 aop_image_mem: aop-image@81c00000 { 476 reg = <0x0 0x81c00000 0x0 0x60000>; 477 no-map; 478 }; 479 480 aop_cmd_db_mem: aop-cmd-db@81c60000 { 481 compatible = "qcom,cmd-db"; 482 reg = <0x0 0x81c60000 0x0 0x20000>; 483 no-map; 484 }; 485 486 aop_config_mem: aop-config@81c80000 { 487 reg = <0x0 0x81c80000 0x0 0x20000>; 488 no-map; 489 }; 490 491 tme_crash_dump_mem: tme-crash-dump@81ca0000 { 492 reg = <0x0 0x81ca0000 0x0 0x40000>; 493 no-map; 494 }; 495 496 tme_log_mem: tme-log@81ce0000 { 497 reg = <0x0 0x81ce0000 0x0 0x4000>; 498 no-map; 499 }; 500 501 uefi_log_mem: uefi-log@81ce4000 { 502 reg = <0x0 0x81ce4000 0x0 0x10000>; 503 no-map; 504 }; 505 506 secdata_apss_mem: secdata-apss@81cff000 { 507 reg = <0x0 0x81cff000 0x0 0x1000>; 508 no-map; 509 }; 510 511 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 512 reg = <0x0 0x81e00000 0x0 0x100000>; 513 no-map; 514 }; 515 516 gpu_prr_mem: gpu-prr@81f00000 { 517 reg = <0x0 0x81f00000 0x0 0x10000>; 518 no-map; 519 }; 520 521 tpm_control_mem: tpm-control@81f10000 { 522 reg = <0x0 0x81f10000 0x0 0x10000>; 523 no-map; 524 }; 525 526 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 { 527 reg = <0x0 0x81f20000 0x0 0x10000>; 528 no-map; 529 }; 530 531 pld_pep_mem: pld-pep@81f30000 { 532 reg = <0x0 0x81f30000 0x0 0x6000>; 533 no-map; 534 }; 535 536 pld_gmu_mem: pld-gmu@81f36000 { 537 reg = <0x0 0x81f36000 0x0 0x1000>; 538 no-map; 539 }; 540 541 pld_pdp_mem: pld-pdp@81f37000 { 542 reg = <0x0 0x81f37000 0x0 0x1000>; 543 no-map; 544 }; 545 546 tz_stat_mem: tz-stat@82700000 { 547 reg = <0x0 0x82700000 0x0 0x100000>; 548 no-map; 549 }; 550 551 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 { 552 reg = <0x0 0x82800000 0x0 0xc00000>; 553 no-map; 554 }; 555 556 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 { 557 reg = <0x0 0x84b00000 0x0 0x800000>; 558 no-map; 559 }; 560 561 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 { 562 reg = <0x0 0x85300000 0x0 0x80000>; 563 no-map; 564 }; 565 566 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 { 567 reg = <0x0 0x866c0000 0x0 0x40000>; 568 no-map; 569 }; 570 571 spss_region_mem: spss-region@86700000 { 572 reg = <0x0 0x86700000 0x0 0x400000>; 573 no-map; 574 }; 575 576 adsp_boot_mem: adsp-boot@86b00000 { 577 reg = <0x0 0x86b00000 0x0 0xc00000>; 578 no-map; 579 }; 580 581 video_mem: video@87700000 { 582 reg = <0x0 0x87700000 0x0 0x700000>; 583 no-map; 584 }; 585 586 adspslpi_mem: adspslpi@87e00000 { 587 reg = <0x0 0x87e00000 0x0 0x3a00000>; 588 no-map; 589 }; 590 591 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 { 592 reg = <0x0 0x8b800000 0x0 0x80000>; 593 no-map; 594 }; 595 596 cdsp_mem: cdsp@8b900000 { 597 reg = <0x0 0x8b900000 0x0 0x2000000>; 598 no-map; 599 }; 600 601 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 { 602 reg = <0x0 0x8d900000 0x0 0x80000>; 603 no-map; 604 }; 605 606 gpu_microcode_mem: gpu-microcode@8d9fe000 { 607 reg = <0x0 0x8d9fe000 0x0 0x2000>; 608 no-map; 609 }; 610 611 cvp_mem: cvp@8da00000 { 612 reg = <0x0 0x8da00000 0x0 0x700000>; 613 no-map; 614 }; 615 616 camera_mem: camera@8e100000 { 617 reg = <0x0 0x8e100000 0x0 0x800000>; 618 no-map; 619 }; 620 621 av1_encoder_mem: av1-encoder@8e900000 { 622 reg = <0x0 0x8e900000 0x0 0x700000>; 623 no-map; 624 }; 625 626 reserved-region@8f000000 { 627 reg = <0x0 0x8f000000 0x0 0xa00000>; 628 no-map; 629 }; 630 631 wpss_mem: wpss@8fa00000 { 632 reg = <0x0 0x8fa00000 0x0 0x1900000>; 633 no-map; 634 }; 635 636 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 { 637 reg = <0x0 0x91300000 0x0 0x80000>; 638 no-map; 639 }; 640 641 xbl_sc_mem: xbl-sc@d8000000 { 642 reg = <0x0 0xd8000000 0x0 0x40000>; 643 no-map; 644 }; 645 646 reserved-region@d8040000 { 647 reg = <0x0 0xd8040000 0x0 0xa0000>; 648 no-map; 649 }; 650 651 qtee_mem: qtee@d80e0000 { 652 reg = <0x0 0xd80e0000 0x0 0x520000>; 653 no-map; 654 }; 655 656 ta_mem: ta@d8600000 { 657 reg = <0x0 0xd8600000 0x0 0x8a00000>; 658 no-map; 659 }; 660 661 tags_mem1: tags@e1000000 { 662 reg = <0x0 0xe1000000 0x0 0x26a0000>; 663 no-map; 664 }; 665 666 llcc_lpi_mem: llcc-lpi@ff800000 { 667 reg = <0x0 0xff800000 0x0 0x600000>; 668 no-map; 669 }; 670 671 smem_mem: smem@ffe00000 { 672 compatible = "qcom,smem"; 673 reg = <0x0 0xffe00000 0x0 0x200000>; 674 hwlocks = <&tcsr_mutex 3>; 675 no-map; 676 }; 677 }; 678 679 smp2p-adsp { 680 compatible = "qcom,smp2p"; 681 682 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 683 IPCC_MPROC_SIGNAL_SMP2P 684 IRQ_TYPE_EDGE_RISING>; 685 686 mboxes = <&ipcc IPCC_CLIENT_LPASS 687 IPCC_MPROC_SIGNAL_SMP2P>; 688 689 qcom,smem = <443>, <429>; 690 qcom,local-pid = <0>; 691 qcom,remote-pid = <2>; 692 693 smp2p_adsp_out: master-kernel { 694 qcom,entry-name = "master-kernel"; 695 #qcom,smem-state-cells = <1>; 696 }; 697 698 smp2p_adsp_in: slave-kernel { 699 qcom,entry-name = "slave-kernel"; 700 interrupt-controller; 701 #interrupt-cells = <2>; 702 }; 703 }; 704 705 smp2p-cdsp { 706 compatible = "qcom,smp2p"; 707 708 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 709 IPCC_MPROC_SIGNAL_SMP2P 710 IRQ_TYPE_EDGE_RISING>; 711 712 mboxes = <&ipcc IPCC_CLIENT_CDSP 713 IPCC_MPROC_SIGNAL_SMP2P>; 714 715 qcom,smem = <94>, <432>; 716 qcom,local-pid = <0>; 717 qcom,remote-pid = <5>; 718 719 smp2p_cdsp_out: master-kernel { 720 qcom,entry-name = "master-kernel"; 721 #qcom,smem-state-cells = <1>; 722 }; 723 724 smp2p_cdsp_in: slave-kernel { 725 qcom,entry-name = "slave-kernel"; 726 interrupt-controller; 727 #interrupt-cells = <2>; 728 }; 729 }; 730 731 soc: soc@0 { 732 compatible = "simple-bus"; 733 734 #address-cells = <2>; 735 #size-cells = <2>; 736 dma-ranges = <0 0 0 0 0x10 0>; 737 ranges = <0 0 0 0 0x10 0>; 738 739 gcc: clock-controller@100000 { 740 compatible = "qcom,x1e80100-gcc"; 741 reg = <0 0x00100000 0 0x200000>; 742 743 clocks = <&bi_tcxo_div2>, 744 <&sleep_clk>, 745 <0>, 746 <&pcie4_phy>, 747 <0>, 748 <&pcie6a_phy>, 749 <0>, 750 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 751 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 752 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 753 754 power-domains = <&rpmhpd RPMHPD_CX>; 755 #clock-cells = <1>; 756 #reset-cells = <1>; 757 #power-domain-cells = <1>; 758 }; 759 760 ipcc: mailbox@408000 { 761 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; 762 reg = <0 0x00408000 0 0x1000>; 763 764 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 765 interrupt-controller; 766 #interrupt-cells = <3>; 767 768 #mbox-cells = <2>; 769 }; 770 771 gpi_dma2: dma-controller@800000 { 772 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 773 reg = <0 0x00800000 0 0x60000>; 774 775 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 787 788 dma-channels = <12>; 789 dma-channel-mask = <0x3e>; 790 #dma-cells = <3>; 791 792 iommus = <&apps_smmu 0x436 0x0>; 793 794 status = "disabled"; 795 }; 796 797 qupv3_2: geniqup@8c0000 { 798 compatible = "qcom,geni-se-qup"; 799 reg = <0 0x008c0000 0 0x2000>; 800 801 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 802 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 803 clock-names = "m-ahb", 804 "s-ahb"; 805 806 iommus = <&apps_smmu 0x423 0x0>; 807 808 #address-cells = <2>; 809 #size-cells = <2>; 810 ranges; 811 812 status = "disabled"; 813 814 i2c16: i2c@880000 { 815 compatible = "qcom,geni-i2c"; 816 reg = <0 0x00880000 0 0x4000>; 817 818 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 819 820 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 821 clock-names = "se"; 822 823 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 824 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 825 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 826 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 827 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 828 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 829 interconnect-names = "qup-core", 830 "qup-config", 831 "qup-memory"; 832 833 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 834 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 835 dma-names = "tx", 836 "rx"; 837 838 pinctrl-0 = <&qup_i2c16_data_clk>; 839 pinctrl-names = "default"; 840 841 #address-cells = <1>; 842 #size-cells = <0>; 843 844 status = "disabled"; 845 }; 846 847 spi16: spi@880000 { 848 compatible = "qcom,geni-spi"; 849 reg = <0 0x00880000 0 0x4000>; 850 851 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 852 853 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 854 clock-names = "se"; 855 856 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 857 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 858 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 859 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 860 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 861 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 862 interconnect-names = "qup-core", 863 "qup-config", 864 "qup-memory"; 865 866 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 867 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 868 dma-names = "tx", 869 "rx"; 870 871 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 872 pinctrl-names = "default"; 873 874 #address-cells = <1>; 875 #size-cells = <0>; 876 877 status = "disabled"; 878 }; 879 880 i2c17: i2c@884000 { 881 compatible = "qcom,geni-i2c"; 882 reg = <0 0x00884000 0 0x4000>; 883 884 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 885 886 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 887 clock-names = "se"; 888 889 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 890 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 891 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 892 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 893 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 894 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 895 interconnect-names = "qup-core", 896 "qup-config", 897 "qup-memory"; 898 899 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 900 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 901 dma-names = "tx", 902 "rx"; 903 904 pinctrl-0 = <&qup_i2c17_data_clk>; 905 pinctrl-names = "default"; 906 907 #address-cells = <1>; 908 #size-cells = <0>; 909 910 status = "disabled"; 911 }; 912 913 spi17: spi@884000 { 914 compatible = "qcom,geni-spi"; 915 reg = <0 0x00884000 0 0x4000>; 916 917 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 918 919 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 920 clock-names = "se"; 921 922 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 923 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 924 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 925 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 926 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 927 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 928 interconnect-names = "qup-core", 929 "qup-config", 930 "qup-memory"; 931 932 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 933 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 934 dma-names = "tx", 935 "rx"; 936 937 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 938 pinctrl-names = "default"; 939 940 #address-cells = <1>; 941 #size-cells = <0>; 942 943 status = "disabled"; 944 }; 945 946 i2c18: i2c@888000 { 947 compatible = "qcom,geni-i2c"; 948 reg = <0 0x00888000 0 0x4000>; 949 950 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 951 952 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 953 clock-names = "se"; 954 955 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 956 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 957 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 958 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 959 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 960 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 961 interconnect-names = "qup-core", 962 "qup-config", 963 "qup-memory"; 964 965 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 966 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 967 dma-names = "tx", 968 "rx"; 969 970 pinctrl-0 = <&qup_i2c18_data_clk>; 971 pinctrl-names = "default"; 972 973 #address-cells = <1>; 974 #size-cells = <0>; 975 976 status = "disabled"; 977 }; 978 979 spi18: spi@888000 { 980 compatible = "qcom,geni-spi"; 981 reg = <0 0x00888000 0 0x4000>; 982 983 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 984 985 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 986 clock-names = "se"; 987 988 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 989 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 990 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 991 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 992 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 993 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 994 interconnect-names = "qup-core", 995 "qup-config", 996 "qup-memory"; 997 998 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 999 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1000 dma-names = "tx", 1001 "rx"; 1002 1003 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1004 pinctrl-names = "default"; 1005 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 1009 status = "disabled"; 1010 }; 1011 1012 i2c19: i2c@88c000 { 1013 compatible = "qcom,geni-i2c"; 1014 reg = <0 0x0088c000 0 0x4000>; 1015 1016 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1017 1018 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1019 clock-names = "se"; 1020 1021 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1022 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1023 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1024 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1025 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1026 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1027 interconnect-names = "qup-core", 1028 "qup-config", 1029 "qup-memory"; 1030 1031 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1032 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1033 dma-names = "tx", 1034 "rx"; 1035 1036 pinctrl-0 = <&qup_i2c19_data_clk>; 1037 pinctrl-names = "default"; 1038 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 1042 status = "disabled"; 1043 }; 1044 1045 spi19: spi@88c000 { 1046 compatible = "qcom,geni-spi"; 1047 reg = <0 0x0088c000 0 0x4000>; 1048 1049 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1050 1051 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1052 clock-names = "se"; 1053 1054 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1055 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1056 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1057 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1058 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1059 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1060 interconnect-names = "qup-core", 1061 "qup-config", 1062 "qup-memory"; 1063 1064 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1065 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1066 dma-names = "tx", 1067 "rx"; 1068 1069 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1070 pinctrl-names = "default"; 1071 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 1075 status = "disabled"; 1076 }; 1077 1078 i2c20: i2c@890000 { 1079 compatible = "qcom,geni-i2c"; 1080 reg = <0 0x00890000 0 0x4000>; 1081 1082 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1083 1084 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1085 clock-names = "se"; 1086 1087 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1088 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1089 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1090 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1091 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1092 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1093 interconnect-names = "qup-core", 1094 "qup-config", 1095 "qup-memory"; 1096 1097 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1098 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1099 dma-names = "tx", 1100 "rx"; 1101 1102 pinctrl-0 = <&qup_i2c20_data_clk>; 1103 pinctrl-names = "default"; 1104 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 1108 status = "disabled"; 1109 }; 1110 1111 spi20: spi@890000 { 1112 compatible = "qcom,geni-spi"; 1113 reg = <0 0x00890000 0 0x4000>; 1114 1115 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1116 1117 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1118 clock-names = "se"; 1119 1120 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1121 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1122 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1123 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1124 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1125 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1126 interconnect-names = "qup-core", 1127 "qup-config", 1128 "qup-memory"; 1129 1130 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1131 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1132 dma-names = "tx", 1133 "rx"; 1134 1135 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1136 pinctrl-names = "default"; 1137 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 1141 status = "disabled"; 1142 }; 1143 1144 i2c21: i2c@894000 { 1145 compatible = "qcom,geni-i2c"; 1146 reg = <0 0x00894000 0 0x4000>; 1147 1148 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1149 1150 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1151 clock-names = "se"; 1152 1153 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1154 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1155 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1156 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1157 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1158 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1159 interconnect-names = "qup-core", 1160 "qup-config", 1161 "qup-memory"; 1162 1163 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1164 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1165 dma-names = "tx", 1166 "rx"; 1167 1168 pinctrl-0 = <&qup_i2c21_data_clk>; 1169 pinctrl-names = "default"; 1170 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 1174 status = "disabled"; 1175 }; 1176 1177 spi21: spi@894000 { 1178 compatible = "qcom,geni-spi"; 1179 reg = <0 0x00894000 0 0x4000>; 1180 1181 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1182 1183 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1184 clock-names = "se"; 1185 1186 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1187 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1188 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1189 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1190 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1191 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1192 interconnect-names = "qup-core", 1193 "qup-config", 1194 "qup-memory"; 1195 1196 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1197 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1198 dma-names = "tx", 1199 "rx"; 1200 1201 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1202 pinctrl-names = "default"; 1203 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 1207 status = "disabled"; 1208 }; 1209 1210 uart21: serial@894000 { 1211 compatible = "qcom,geni-uart"; 1212 reg = <0 0x00894000 0 0x4000>; 1213 1214 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1215 1216 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1217 clock-names = "se"; 1218 1219 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1220 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1221 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1222 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1223 interconnect-names = "qup-core", 1224 "qup-config"; 1225 1226 pinctrl-0 = <&qup_uart21_default>; 1227 pinctrl-names = "default"; 1228 1229 status = "disabled"; 1230 }; 1231 1232 i2c22: i2c@898000 { 1233 compatible = "qcom,geni-i2c"; 1234 reg = <0 0x00898000 0 0x4000>; 1235 1236 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1237 1238 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1239 clock-names = "se"; 1240 1241 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1242 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1243 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1244 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1245 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1246 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1247 interconnect-names = "qup-core", 1248 "qup-config", 1249 "qup-memory"; 1250 1251 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1252 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1253 dma-names = "tx", 1254 "rx"; 1255 1256 pinctrl-0 = <&qup_i2c22_data_clk>; 1257 pinctrl-names = "default"; 1258 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 1262 status = "disabled"; 1263 }; 1264 1265 spi22: spi@898000 { 1266 compatible = "qcom,geni-spi"; 1267 reg = <0 0x00898000 0 0x4000>; 1268 1269 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1270 1271 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1272 clock-names = "se"; 1273 1274 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1275 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1276 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1277 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1278 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1279 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1280 interconnect-names = "qup-core", 1281 "qup-config", 1282 "qup-memory"; 1283 1284 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1285 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1286 dma-names = "tx", 1287 "rx"; 1288 1289 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1290 pinctrl-names = "default"; 1291 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 1295 status = "disabled"; 1296 }; 1297 1298 i2c23: i2c@89c000 { 1299 compatible = "qcom,geni-i2c"; 1300 reg = <0 0x0089c000 0 0x4000>; 1301 1302 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1303 1304 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1305 clock-names = "se"; 1306 1307 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1308 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1309 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1310 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1311 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1312 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1313 interconnect-names = "qup-core", 1314 "qup-config", 1315 "qup-memory"; 1316 1317 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1318 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1319 dma-names = "tx", 1320 "rx"; 1321 1322 pinctrl-0 = <&qup_i2c23_data_clk>; 1323 pinctrl-names = "default"; 1324 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 1328 status = "disabled"; 1329 }; 1330 1331 spi23: spi@89c000 { 1332 compatible = "qcom,geni-spi"; 1333 reg = <0 0x0089c000 0 0x4000>; 1334 1335 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1336 1337 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1338 clock-names = "se"; 1339 1340 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1341 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1342 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1343 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1344 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1345 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1346 interconnect-names = "qup-core", 1347 "qup-config", 1348 "qup-memory"; 1349 1350 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1351 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1352 dma-names = "tx", 1353 "rx"; 1354 1355 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1356 pinctrl-names = "default"; 1357 1358 #address-cells = <1>; 1359 #size-cells = <0>; 1360 1361 status = "disabled"; 1362 }; 1363 }; 1364 1365 gpi_dma1: dma-controller@a00000 { 1366 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1367 reg = <0 0x00a00000 0 0x60000>; 1368 1369 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 1381 1382 dma-channels = <12>; 1383 dma-channel-mask = <0x3e>; 1384 #dma-cells = <3>; 1385 1386 iommus = <&apps_smmu 0x136 0x0>; 1387 1388 status = "disabled"; 1389 }; 1390 1391 qupv3_1: geniqup@ac0000 { 1392 compatible = "qcom,geni-se-qup"; 1393 reg = <0 0x00ac0000 0 0x2000>; 1394 1395 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1396 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1397 clock-names = "m-ahb", 1398 "s-ahb"; 1399 1400 iommus = <&apps_smmu 0x123 0x0>; 1401 1402 #address-cells = <2>; 1403 #size-cells = <2>; 1404 ranges; 1405 1406 status = "disabled"; 1407 1408 i2c8: i2c@a80000 { 1409 compatible = "qcom,geni-i2c"; 1410 reg = <0 0x00a80000 0 0x4000>; 1411 1412 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1413 1414 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1415 clock-names = "se"; 1416 1417 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1418 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1419 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1420 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1421 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1422 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1423 interconnect-names = "qup-core", 1424 "qup-config", 1425 "qup-memory"; 1426 1427 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1428 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1429 dma-names = "tx", 1430 "rx"; 1431 1432 pinctrl-0 = <&qup_i2c8_data_clk>; 1433 pinctrl-names = "default"; 1434 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 1438 status = "disabled"; 1439 }; 1440 1441 spi8: spi@a80000 { 1442 compatible = "qcom,geni-spi"; 1443 reg = <0 0x00a80000 0 0x4000>; 1444 1445 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1446 1447 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1448 clock-names = "se"; 1449 1450 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1451 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1452 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1453 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1454 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1455 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1456 interconnect-names = "qup-core", 1457 "qup-config", 1458 "qup-memory"; 1459 1460 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1461 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1462 dma-names = "tx", 1463 "rx"; 1464 1465 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1466 pinctrl-names = "default"; 1467 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 1471 status = "disabled"; 1472 }; 1473 1474 i2c9: i2c@a84000 { 1475 compatible = "qcom,geni-i2c"; 1476 reg = <0 0x00a84000 0 0x4000>; 1477 1478 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1479 1480 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1481 clock-names = "se"; 1482 1483 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1484 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1485 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1486 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1487 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1488 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1489 interconnect-names = "qup-core", 1490 "qup-config", 1491 "qup-memory"; 1492 1493 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1494 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1495 dma-names = "tx", 1496 "rx"; 1497 1498 pinctrl-0 = <&qup_i2c9_data_clk>; 1499 pinctrl-names = "default"; 1500 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 1504 status = "disabled"; 1505 }; 1506 1507 spi9: spi@a84000 { 1508 compatible = "qcom,geni-spi"; 1509 reg = <0 0x00a84000 0 0x4000>; 1510 1511 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1512 1513 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1514 clock-names = "se"; 1515 1516 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1517 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1518 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1519 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1520 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1521 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1522 interconnect-names = "qup-core", 1523 "qup-config", 1524 "qup-memory"; 1525 1526 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1527 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1528 dma-names = "tx", 1529 "rx"; 1530 1531 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1532 pinctrl-names = "default"; 1533 1534 #address-cells = <1>; 1535 #size-cells = <0>; 1536 1537 status = "disabled"; 1538 }; 1539 1540 i2c10: i2c@a88000 { 1541 compatible = "qcom,geni-i2c"; 1542 reg = <0 0x00a88000 0 0x4000>; 1543 1544 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1545 1546 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1547 clock-names = "se"; 1548 1549 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1550 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1551 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1552 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1553 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1554 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1555 interconnect-names = "qup-core", 1556 "qup-config", 1557 "qup-memory"; 1558 1559 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1560 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1561 dma-names = "tx", 1562 "rx"; 1563 1564 pinctrl-0 = <&qup_i2c10_data_clk>; 1565 pinctrl-names = "default"; 1566 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 1570 status = "disabled"; 1571 }; 1572 1573 spi10: spi@a88000 { 1574 compatible = "qcom,geni-spi"; 1575 reg = <0 0x00a88000 0 0x4000>; 1576 1577 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1578 1579 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1580 clock-names = "se"; 1581 1582 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1583 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1584 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1585 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1586 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1587 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1588 interconnect-names = "qup-core", 1589 "qup-config", 1590 "qup-memory"; 1591 1592 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1593 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1594 dma-names = "tx", 1595 "rx"; 1596 1597 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1598 pinctrl-names = "default"; 1599 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 1603 status = "disabled"; 1604 }; 1605 1606 i2c11: i2c@a8c000 { 1607 compatible = "qcom,geni-i2c"; 1608 reg = <0 0x00a8c000 0 0x4000>; 1609 1610 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1611 1612 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1613 clock-names = "se"; 1614 1615 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1616 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1617 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1618 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1619 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1620 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1621 interconnect-names = "qup-core", 1622 "qup-config", 1623 "qup-memory"; 1624 1625 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1626 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1627 dma-names = "tx", 1628 "rx"; 1629 1630 pinctrl-0 = <&qup_i2c11_data_clk>; 1631 pinctrl-names = "default"; 1632 1633 #address-cells = <1>; 1634 #size-cells = <0>; 1635 1636 status = "disabled"; 1637 }; 1638 1639 spi11: spi@a8c000 { 1640 compatible = "qcom,geni-spi"; 1641 reg = <0 0x00a8c000 0 0x4000>; 1642 1643 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1644 1645 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1646 clock-names = "se"; 1647 1648 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1649 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1650 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1651 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1652 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1653 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1654 interconnect-names = "qup-core", 1655 "qup-config", 1656 "qup-memory"; 1657 1658 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1659 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1660 dma-names = "tx", 1661 "rx"; 1662 1663 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1664 pinctrl-names = "default"; 1665 1666 #address-cells = <1>; 1667 #size-cells = <0>; 1668 1669 status = "disabled"; 1670 }; 1671 1672 i2c12: i2c@a90000 { 1673 compatible = "qcom,geni-i2c"; 1674 reg = <0 0x00a90000 0 0x4000>; 1675 1676 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1677 1678 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1679 clock-names = "se"; 1680 1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1682 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1683 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1684 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1685 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1686 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1687 interconnect-names = "qup-core", 1688 "qup-config", 1689 "qup-memory"; 1690 1691 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1692 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1693 dma-names = "tx", 1694 "rx"; 1695 1696 pinctrl-0 = <&qup_i2c12_data_clk>; 1697 pinctrl-names = "default"; 1698 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 1702 status = "disabled"; 1703 }; 1704 1705 spi12: spi@a90000 { 1706 compatible = "qcom,geni-spi"; 1707 reg = <0 0x00a90000 0 0x4000>; 1708 1709 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1710 1711 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1712 clock-names = "se"; 1713 1714 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1715 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1716 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1717 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1718 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1719 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1720 interconnect-names = "qup-core", 1721 "qup-config", 1722 "qup-memory"; 1723 1724 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1725 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1726 dma-names = "tx", 1727 "rx"; 1728 1729 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1730 pinctrl-names = "default"; 1731 1732 #address-cells = <1>; 1733 #size-cells = <0>; 1734 1735 status = "disabled"; 1736 }; 1737 1738 i2c13: i2c@a94000 { 1739 compatible = "qcom,geni-i2c"; 1740 reg = <0 0x00a94000 0 0x4000>; 1741 1742 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1743 1744 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1745 clock-names = "se"; 1746 1747 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1748 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1749 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1750 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1751 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1752 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1753 interconnect-names = "qup-core", 1754 "qup-config", 1755 "qup-memory"; 1756 1757 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1758 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1759 dma-names = "tx", 1760 "rx"; 1761 1762 pinctrl-0 = <&qup_i2c13_data_clk>; 1763 pinctrl-names = "default"; 1764 1765 #address-cells = <1>; 1766 #size-cells = <0>; 1767 1768 status = "disabled"; 1769 }; 1770 1771 spi13: spi@a94000 { 1772 compatible = "qcom,geni-spi"; 1773 reg = <0 0x00a94000 0 0x4000>; 1774 1775 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1776 1777 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1778 clock-names = "se"; 1779 1780 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1781 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1782 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1783 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1784 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1785 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1786 interconnect-names = "qup-core", 1787 "qup-config", 1788 "qup-memory"; 1789 1790 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1791 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1792 dma-names = "tx", 1793 "rx"; 1794 1795 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1796 pinctrl-names = "default"; 1797 1798 #address-cells = <1>; 1799 #size-cells = <0>; 1800 1801 status = "disabled"; 1802 }; 1803 1804 i2c14: i2c@a98000 { 1805 compatible = "qcom,geni-i2c"; 1806 reg = <0 0x00a98000 0 0x4000>; 1807 1808 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1809 1810 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1811 clock-names = "se"; 1812 1813 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1814 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1815 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1816 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1817 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1818 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1819 interconnect-names = "qup-core", 1820 "qup-config", 1821 "qup-memory"; 1822 1823 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1824 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1825 dma-names = "tx", 1826 "rx"; 1827 1828 pinctrl-0 = <&qup_i2c14_data_clk>; 1829 pinctrl-names = "default"; 1830 1831 #address-cells = <1>; 1832 #size-cells = <0>; 1833 1834 status = "disabled"; 1835 }; 1836 1837 spi14: spi@a98000 { 1838 compatible = "qcom,geni-spi"; 1839 reg = <0 0x00a98000 0 0x4000>; 1840 1841 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1842 1843 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1844 clock-names = "se"; 1845 1846 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1847 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1848 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1849 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1850 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1851 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1852 interconnect-names = "qup-core", 1853 "qup-config", 1854 "qup-memory"; 1855 1856 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1857 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1858 dma-names = "tx", 1859 "rx"; 1860 1861 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1862 pinctrl-names = "default"; 1863 1864 #address-cells = <1>; 1865 #size-cells = <0>; 1866 1867 status = "disabled"; 1868 }; 1869 1870 i2c15: i2c@a9c000 { 1871 compatible = "qcom,geni-i2c"; 1872 reg = <0 0x00a9c000 0 0x4000>; 1873 1874 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 1875 1876 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1877 clock-names = "se"; 1878 1879 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1880 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1881 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1882 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1883 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1884 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1885 interconnect-names = "qup-core", 1886 "qup-config", 1887 "qup-memory"; 1888 1889 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1890 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1891 dma-names = "tx", 1892 "rx"; 1893 1894 pinctrl-0 = <&qup_i2c15_data_clk>; 1895 pinctrl-names = "default"; 1896 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 1900 status = "disabled"; 1901 }; 1902 1903 spi15: spi@a9c000 { 1904 compatible = "qcom,geni-spi"; 1905 reg = <0 0x00a9c000 0 0x4000>; 1906 1907 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 1908 1909 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1910 clock-names = "se"; 1911 1912 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1913 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1914 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1915 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1916 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1917 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1918 interconnect-names = "qup-core", 1919 "qup-config", 1920 "qup-memory"; 1921 1922 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1923 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1924 dma-names = "tx", 1925 "rx"; 1926 1927 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1928 pinctrl-names = "default"; 1929 1930 #address-cells = <1>; 1931 #size-cells = <0>; 1932 1933 status = "disabled"; 1934 }; 1935 }; 1936 1937 gpi_dma0: dma-controller@b00000 { 1938 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1939 reg = <0 0x00b00000 0 0x60000>; 1940 1941 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 1953 1954 dma-channels = <12>; 1955 dma-channel-mask = <0x3e>; 1956 #dma-cells = <3>; 1957 1958 iommus = <&apps_smmu 0x456 0x0>; 1959 1960 status = "disabled"; 1961 }; 1962 1963 qupv3_0: geniqup@bc0000 { 1964 compatible = "qcom,geni-se-qup"; 1965 reg = <0 0x00bc0000 0 0x2000>; 1966 1967 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1968 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1969 clock-names = "m-ahb", 1970 "s-ahb"; 1971 1972 iommus = <&apps_smmu 0x443 0x0>; 1973 #address-cells = <2>; 1974 #size-cells = <2>; 1975 ranges; 1976 1977 status = "disabled"; 1978 1979 i2c0: i2c@b80000 { 1980 compatible = "qcom,geni-i2c"; 1981 reg = <0 0xb80000 0 0x4000>; 1982 1983 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1984 1985 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1986 clock-names = "se"; 1987 1988 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1989 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1990 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1991 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1992 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1993 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1994 interconnect-names = "qup-core", 1995 "qup-config", 1996 "qup-memory"; 1997 1998 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1999 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 2000 dma-names = "tx", 2001 "rx"; 2002 2003 pinctrl-0 = <&qup_i2c0_data_clk>; 2004 pinctrl-names = "default"; 2005 2006 #address-cells = <1>; 2007 #size-cells = <0>; 2008 2009 status = "disabled"; 2010 }; 2011 2012 spi0: spi@b80000 { 2013 compatible = "qcom,geni-spi"; 2014 reg = <0 0x00b80000 0 0x4000>; 2015 2016 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2017 2018 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2019 clock-names = "se"; 2020 2021 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2022 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2023 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2024 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2025 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2026 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2027 interconnect-names = "qup-core", 2028 "qup-config", 2029 "qup-memory"; 2030 2031 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 2032 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 2033 dma-names = "tx", 2034 "rx"; 2035 2036 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2037 pinctrl-names = "default"; 2038 2039 #address-cells = <1>; 2040 #size-cells = <0>; 2041 2042 status = "disabled"; 2043 }; 2044 2045 i2c1: i2c@b84000 { 2046 compatible = "qcom,geni-i2c"; 2047 reg = <0 0x00b84000 0 0x4000>; 2048 2049 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2050 2051 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2052 clock-names = "se"; 2053 2054 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2055 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2056 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2057 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2058 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2059 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2060 interconnect-names = "qup-core", 2061 "qup-config", 2062 "qup-memory"; 2063 2064 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 2065 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 2066 dma-names = "tx", 2067 "rx"; 2068 2069 pinctrl-0 = <&qup_i2c1_data_clk>; 2070 pinctrl-names = "default"; 2071 2072 #address-cells = <1>; 2073 #size-cells = <0>; 2074 2075 status = "disabled"; 2076 }; 2077 2078 spi1: spi@b84000 { 2079 compatible = "qcom,geni-spi"; 2080 reg = <0 0x00b84000 0 0x4000>; 2081 2082 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2083 2084 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2085 clock-names = "se"; 2086 2087 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2088 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2089 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2090 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2091 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2092 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2093 interconnect-names = "qup-core", 2094 "qup-config", 2095 "qup-memory"; 2096 2097 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 2098 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 2099 dma-names = "tx", 2100 "rx"; 2101 2102 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 2103 pinctrl-names = "default"; 2104 2105 #address-cells = <1>; 2106 #size-cells = <0>; 2107 2108 status = "disabled"; 2109 }; 2110 2111 i2c2: i2c@b88000 { 2112 compatible = "qcom,geni-i2c"; 2113 reg = <0 0x00b88000 0 0x4000>; 2114 2115 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2116 2117 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2118 clock-names = "se"; 2119 2120 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2121 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2122 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2123 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2124 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2125 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2126 interconnect-names = "qup-core", 2127 "qup-config", 2128 "qup-memory"; 2129 2130 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2131 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2132 dma-names = "tx", 2133 "rx"; 2134 2135 pinctrl-0 = <&qup_i2c2_data_clk>; 2136 pinctrl-names = "default"; 2137 2138 #address-cells = <1>; 2139 #size-cells = <0>; 2140 2141 status = "disabled"; 2142 }; 2143 2144 spi2: spi@b88000 { 2145 compatible = "qcom,geni-spi"; 2146 reg = <0 0xb88000 0 0x4000>; 2147 2148 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2149 2150 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2151 clock-names = "se"; 2152 2153 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2154 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2155 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2156 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2157 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2158 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2159 interconnect-names = "qup-core", 2160 "qup-config", 2161 "qup-memory"; 2162 2163 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2164 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2165 dma-names = "tx", 2166 "rx"; 2167 2168 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2169 pinctrl-names = "default"; 2170 2171 #address-cells = <1>; 2172 #size-cells = <0>; 2173 2174 status = "disabled"; 2175 }; 2176 2177 i2c3: i2c@b8c000 { 2178 compatible = "qcom,geni-i2c"; 2179 reg = <0 0x00b8c000 0 0x4000>; 2180 2181 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2182 2183 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2184 clock-names = "se"; 2185 2186 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2187 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2188 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2189 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2190 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2191 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2192 interconnect-names = "qup-core", 2193 "qup-config", 2194 "qup-memory"; 2195 2196 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2197 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2198 dma-names = "tx", 2199 "rx"; 2200 2201 pinctrl-0 = <&qup_i2c3_data_clk>; 2202 pinctrl-names = "default"; 2203 2204 #address-cells = <1>; 2205 #size-cells = <0>; 2206 2207 status = "disabled"; 2208 }; 2209 2210 spi3: spi@b8c000 { 2211 compatible = "qcom,geni-spi"; 2212 reg = <0 0x00b8c000 0 0x4000>; 2213 2214 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2215 2216 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2217 clock-names = "se"; 2218 2219 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2220 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2221 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2222 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2223 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2224 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2225 interconnect-names = "qup-core", 2226 "qup-config", 2227 "qup-memory"; 2228 2229 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2230 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2231 dma-names = "tx", 2232 "rx"; 2233 2234 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2235 pinctrl-names = "default"; 2236 2237 #address-cells = <1>; 2238 #size-cells = <0>; 2239 2240 status = "disabled"; 2241 }; 2242 2243 i2c4: i2c@b90000 { 2244 compatible = "qcom,geni-i2c"; 2245 reg = <0 0xb90000 0 0x4000>; 2246 2247 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2248 2249 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2250 clock-names = "se"; 2251 2252 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2253 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2254 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2255 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2256 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2257 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2258 interconnect-names = "qup-core", 2259 "qup-config", 2260 "qup-memory"; 2261 2262 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2263 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2264 dma-names = "tx", 2265 "rx"; 2266 2267 pinctrl-0 = <&qup_i2c4_data_clk>; 2268 pinctrl-names = "default"; 2269 2270 #address-cells = <1>; 2271 #size-cells = <0>; 2272 2273 status = "disabled"; 2274 }; 2275 2276 spi4: spi@b90000 { 2277 compatible = "qcom,geni-spi"; 2278 reg = <0 0x00b90000 0 0x4000>; 2279 2280 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2281 2282 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2283 clock-names = "se"; 2284 2285 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2286 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2287 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2288 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2289 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2290 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2291 interconnect-names = "qup-core", 2292 "qup-config", 2293 "qup-memory"; 2294 2295 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2296 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2297 dma-names = "tx", 2298 "rx"; 2299 2300 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2301 pinctrl-names = "default"; 2302 2303 #address-cells = <1>; 2304 #size-cells = <0>; 2305 2306 status = "disabled"; 2307 }; 2308 2309 i2c5: i2c@b94000 { 2310 compatible = "qcom,geni-i2c"; 2311 reg = <0 0x00b94000 0 0x4000>; 2312 2313 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2314 2315 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2316 clock-names = "se"; 2317 2318 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2319 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2320 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2321 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2322 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2323 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2324 interconnect-names = "qup-core", 2325 "qup-config", 2326 "qup-memory"; 2327 2328 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2329 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2330 dma-names = "tx", 2331 "rx"; 2332 2333 pinctrl-0 = <&qup_i2c5_data_clk>; 2334 pinctrl-names = "default"; 2335 2336 #address-cells = <1>; 2337 #size-cells = <0>; 2338 2339 status = "disabled"; 2340 }; 2341 2342 spi5: spi@b94000 { 2343 compatible = "qcom,geni-spi"; 2344 reg = <0 0x00b94000 0 0x4000>; 2345 2346 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2347 2348 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2349 clock-names = "se"; 2350 2351 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2352 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2353 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2354 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2355 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2356 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2357 interconnect-names = "qup-core", 2358 "qup-config", 2359 "qup-memory"; 2360 2361 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2362 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2363 dma-names = "tx", 2364 "rx"; 2365 2366 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2367 pinctrl-names = "default"; 2368 2369 #address-cells = <1>; 2370 #size-cells = <0>; 2371 2372 status = "disabled"; 2373 }; 2374 2375 i2c6: i2c@b98000 { 2376 compatible = "qcom,geni-i2c"; 2377 reg = <0 0x00b98000 0 0x4000>; 2378 2379 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2380 2381 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2382 clock-names = "se"; 2383 2384 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2385 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2386 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2387 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2388 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2389 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2390 interconnect-names = "qup-core", 2391 "qup-config", 2392 "qup-memory"; 2393 2394 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2395 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2396 dma-names = "tx", 2397 "rx"; 2398 2399 pinctrl-0 = <&qup_i2c6_data_clk>; 2400 pinctrl-names = "default"; 2401 2402 #address-cells = <1>; 2403 #size-cells = <0>; 2404 2405 status = "disabled"; 2406 }; 2407 2408 spi6: spi@b98000 { 2409 compatible = "qcom,geni-spi"; 2410 reg = <0 0x00b98000 0 0x4000>; 2411 2412 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2413 2414 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2415 clock-names = "se"; 2416 2417 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2418 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2419 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2420 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2421 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2422 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2423 interconnect-names = "qup-core", 2424 "qup-config", 2425 "qup-memory"; 2426 2427 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2428 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2429 dma-names = "tx", 2430 "rx"; 2431 2432 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2433 pinctrl-names = "default"; 2434 2435 #address-cells = <1>; 2436 #size-cells = <0>; 2437 2438 status = "disabled"; 2439 }; 2440 2441 i2c7: i2c@b9c000 { 2442 compatible = "qcom,geni-i2c"; 2443 reg = <0 0x00b9c000 0 0x4000>; 2444 2445 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2446 2447 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2448 clock-names = "se"; 2449 2450 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2451 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2452 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2453 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2454 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2455 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2456 interconnect-names = "qup-core", 2457 "qup-config", 2458 "qup-memory"; 2459 2460 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2461 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2462 dma-names = "tx", 2463 "rx"; 2464 2465 pinctrl-0 = <&qup_i2c7_data_clk>; 2466 pinctrl-names = "default"; 2467 2468 #address-cells = <1>; 2469 #size-cells = <0>; 2470 2471 status = "disabled"; 2472 }; 2473 2474 spi7: spi@b9c000 { 2475 compatible = "qcom,geni-spi"; 2476 reg = <0 0x00b9c000 0 0x4000>; 2477 2478 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2479 2480 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2481 clock-names = "se"; 2482 2483 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2484 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2485 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2486 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2487 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2488 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2489 interconnect-names = "qup-core", 2490 "qup-config", 2491 "qup-memory"; 2492 2493 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2494 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2495 dma-names = "tx", 2496 "rx"; 2497 2498 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2499 pinctrl-names = "default"; 2500 2501 #address-cells = <1>; 2502 #size-cells = <0>; 2503 2504 status = "disabled"; 2505 }; 2506 }; 2507 2508 usb_1_ss0_hsphy: phy@fd3000 { 2509 compatible = "qcom,x1e80100-snps-eusb2-phy", 2510 "qcom,sm8550-snps-eusb2-phy"; 2511 reg = <0 0x00fd3000 0 0x154>; 2512 #phy-cells = <0>; 2513 2514 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2515 clock-names = "ref"; 2516 2517 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2518 2519 status = "disabled"; 2520 }; 2521 2522 usb_1_ss0_qmpphy: phy@fd5000 { 2523 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2524 reg = <0 0x00fd5000 0 0x4000>; 2525 2526 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2527 <&rpmhcc RPMH_CXO_CLK>, 2528 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2529 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2530 clock-names = "aux", 2531 "ref", 2532 "com_aux", 2533 "usb3_pipe"; 2534 2535 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2536 2537 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2538 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; 2539 reset-names = "phy", 2540 "common"; 2541 2542 #clock-cells = <1>; 2543 #phy-cells = <1>; 2544 2545 status = "disabled"; 2546 }; 2547 2548 usb_1_ss1_hsphy: phy@fd9000 { 2549 compatible = "qcom,x1e80100-snps-eusb2-phy", 2550 "qcom,sm8550-snps-eusb2-phy"; 2551 reg = <0 0x00fd9000 0 0x154>; 2552 #phy-cells = <0>; 2553 2554 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2555 clock-names = "ref"; 2556 2557 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2558 2559 status = "disabled"; 2560 }; 2561 2562 usb_1_ss1_qmpphy: phy@fda000 { 2563 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2564 reg = <0 0x00fda000 0 0x4000>; 2565 2566 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2567 <&rpmhcc RPMH_CXO_CLK>, 2568 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2569 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2570 clock-names = "aux", 2571 "ref", 2572 "com_aux", 2573 "usb3_pipe"; 2574 2575 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2576 2577 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2578 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; 2579 reset-names = "phy", 2580 "common"; 2581 2582 #clock-cells = <1>; 2583 #phy-cells = <1>; 2584 2585 status = "disabled"; 2586 }; 2587 2588 usb_1_ss2_hsphy: phy@fde000 { 2589 compatible = "qcom,x1e80100-snps-eusb2-phy", 2590 "qcom,sm8550-snps-eusb2-phy"; 2591 reg = <0 0x00fde000 0 0x154>; 2592 #phy-cells = <0>; 2593 2594 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2595 clock-names = "ref"; 2596 2597 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 2598 2599 status = "disabled"; 2600 }; 2601 2602 usb_1_ss2_qmpphy: phy@fdf000 { 2603 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2604 reg = <0 0x00fdf000 0 0x4000>; 2605 2606 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 2607 <&rpmhcc RPMH_CXO_CLK>, 2608 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 2609 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 2610 clock-names = "aux", 2611 "ref", 2612 "com_aux", 2613 "usb3_pipe"; 2614 2615 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 2616 2617 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 2618 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; 2619 reset-names = "phy", 2620 "common"; 2621 2622 #clock-cells = <1>; 2623 #phy-cells = <1>; 2624 2625 status = "disabled"; 2626 }; 2627 2628 cnoc_main: interconnect@1500000 { 2629 compatible = "qcom,x1e80100-cnoc-main"; 2630 reg = <0 0x1500000 0 0x14400>; 2631 2632 qcom,bcm-voters = <&apps_bcm_voter>; 2633 2634 #interconnect-cells = <2>; 2635 }; 2636 2637 config_noc: interconnect@1600000 { 2638 compatible = "qcom,x1e80100-cnoc-cfg"; 2639 reg = <0 0x1600000 0 0x6600>; 2640 2641 qcom,bcm-voters = <&apps_bcm_voter>; 2642 2643 #interconnect-cells = <2>; 2644 }; 2645 2646 system_noc: interconnect@1680000 { 2647 compatible = "qcom,x1e80100-system-noc"; 2648 reg = <0 0x1680000 0 0x1c080>; 2649 2650 qcom,bcm-voters = <&apps_bcm_voter>; 2651 2652 #interconnect-cells = <2>; 2653 }; 2654 2655 pcie_south_anoc: interconnect@16c0000 { 2656 compatible = "qcom,x1e80100-pcie-south-anoc"; 2657 reg = <0 0x16c0000 0 0xd080>; 2658 2659 qcom,bcm-voters = <&apps_bcm_voter>; 2660 2661 #interconnect-cells = <2>; 2662 }; 2663 2664 pcie_center_anoc: interconnect@16d0000 { 2665 compatible = "qcom,x1e80100-pcie-center-anoc"; 2666 reg = <0 0x16d0000 0 0x7000>; 2667 2668 qcom,bcm-voters = <&apps_bcm_voter>; 2669 2670 #interconnect-cells = <2>; 2671 }; 2672 2673 aggre1_noc: interconnect@16e0000 { 2674 compatible = "qcom,x1e80100-aggre1-noc"; 2675 reg = <0 0x16E0000 0 0x14400>; 2676 2677 qcom,bcm-voters = <&apps_bcm_voter>; 2678 2679 #interconnect-cells = <2>; 2680 }; 2681 2682 aggre2_noc: interconnect@1700000 { 2683 compatible = "qcom,x1e80100-aggre2-noc"; 2684 reg = <0 0x1700000 0 0x1c400>; 2685 2686 qcom,bcm-voters = <&apps_bcm_voter>; 2687 2688 #interconnect-cells = <2>; 2689 }; 2690 2691 pcie_north_anoc: interconnect@1740000 { 2692 compatible = "qcom,x1e80100-pcie-north-anoc"; 2693 reg = <0 0x1740000 0 0x9080>; 2694 2695 qcom,bcm-voters = <&apps_bcm_voter>; 2696 2697 #interconnect-cells = <2>; 2698 }; 2699 2700 usb_center_anoc: interconnect@1750000 { 2701 compatible = "qcom,x1e80100-usb-center-anoc"; 2702 reg = <0 0x1750000 0 0x8800>; 2703 2704 qcom,bcm-voters = <&apps_bcm_voter>; 2705 2706 #interconnect-cells = <2>; 2707 }; 2708 2709 usb_north_anoc: interconnect@1760000 { 2710 compatible = "qcom,x1e80100-usb-north-anoc"; 2711 reg = <0 0x1760000 0 0x7080>; 2712 2713 qcom,bcm-voters = <&apps_bcm_voter>; 2714 2715 #interconnect-cells = <2>; 2716 }; 2717 2718 usb_south_anoc: interconnect@1770000 { 2719 compatible = "qcom,x1e80100-usb-south-anoc"; 2720 reg = <0 0x1770000 0 0xf080>; 2721 2722 qcom,bcm-voters = <&apps_bcm_voter>; 2723 2724 #interconnect-cells = <2>; 2725 }; 2726 2727 mmss_noc: interconnect@1780000 { 2728 compatible = "qcom,x1e80100-mmss-noc"; 2729 reg = <0 0x1780000 0 0x5B800>; 2730 2731 qcom,bcm-voters = <&apps_bcm_voter>; 2732 2733 #interconnect-cells = <2>; 2734 }; 2735 2736 pcie6a: pci@1bf8000 { 2737 device_type = "pci"; 2738 compatible = "qcom,pcie-x1e80100"; 2739 reg = <0 0x01bf8000 0 0x3000>, 2740 <0 0x70000000 0 0xf1d>, 2741 <0 0x70000f20 0 0xa8>, 2742 <0 0x70001000 0 0x1000>, 2743 <0 0x70100000 0 0x100000>; 2744 reg-names = "parf", 2745 "dbi", 2746 "elbi", 2747 "atu", 2748 "config"; 2749 #address-cells = <3>; 2750 #size-cells = <2>; 2751 ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>, 2752 <0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>; 2753 bus-range = <0 0xff>; 2754 2755 dma-coherent; 2756 2757 linux,pci-domain = <7>; 2758 num-lanes = <2>; 2759 2760 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 2761 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 2762 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 2763 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 2764 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 2765 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 2766 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 2767 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>; 2768 interrupt-names = "msi0", 2769 "msi1", 2770 "msi2", 2771 "msi3", 2772 "msi4", 2773 "msi5", 2774 "msi6", 2775 "msi7"; 2776 2777 #interrupt-cells = <1>; 2778 interrupt-map-mask = <0 0 0 0x7>; 2779 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>, 2780 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>, 2781 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>, 2782 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>; 2783 2784 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, 2785 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 2786 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, 2787 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, 2788 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, 2789 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>, 2790 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; 2791 clock-names = "aux", 2792 "cfg", 2793 "bus_master", 2794 "bus_slave", 2795 "slave_q2a", 2796 "noc_aggr", 2797 "cnoc_sf_axi"; 2798 2799 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; 2800 assigned-clock-rates = <19200000>; 2801 2802 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS 2803 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2804 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2805 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>; 2806 interconnect-names = "pcie-mem", 2807 "cpu-pcie"; 2808 2809 resets = <&gcc GCC_PCIE_6A_BCR>, 2810 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; 2811 reset-names = "pci", 2812 "link_down"; 2813 2814 power-domains = <&gcc GCC_PCIE_6A_GDSC>; 2815 2816 phys = <&pcie6a_phy>; 2817 phy-names = "pciephy"; 2818 2819 status = "disabled"; 2820 }; 2821 2822 pcie6a_phy: phy@1bfc000 { 2823 compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy"; 2824 reg = <0 0x01bfc000 0 0x2000>; 2825 2826 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, 2827 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 2828 <&rpmhcc RPMH_CXO_CLK>, 2829 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, 2830 <&gcc GCC_PCIE_6A_PIPE_CLK>; 2831 clock-names = "aux", 2832 "cfg_ahb", 2833 "ref", 2834 "rchng", 2835 "pipe"; 2836 2837 resets = <&gcc GCC_PCIE_6A_PHY_BCR>, 2838 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; 2839 reset-names = "phy", 2840 "phy_nocsr"; 2841 2842 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; 2843 assigned-clock-rates = <100000000>; 2844 2845 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 2846 2847 #clock-cells = <0>; 2848 clock-output-names = "pcie6a_pipe_clk"; 2849 2850 #phy-cells = <0>; 2851 2852 status = "disabled"; 2853 }; 2854 2855 pcie4: pci@1c08000 { 2856 device_type = "pci"; 2857 compatible = "qcom,pcie-x1e80100"; 2858 reg = <0 0x01c08000 0 0x3000>, 2859 <0 0x7c000000 0 0xf1d>, 2860 <0 0x7c000f40 0 0xa8>, 2861 <0 0x7c001000 0 0x1000>, 2862 <0 0x7c100000 0 0x100000>, 2863 <0 0x01c0b000 0 0x1000>; 2864 reg-names = "parf", 2865 "dbi", 2866 "elbi", 2867 "atu", 2868 "config", 2869 "mhi"; 2870 #address-cells = <3>; 2871 #size-cells = <2>; 2872 ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>, 2873 <0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>; 2874 bus-range = <0x00 0xff>; 2875 2876 dma-coherent; 2877 2878 linux,pci-domain = <5>; 2879 num-lanes = <2>; 2880 2881 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2882 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2883 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2884 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2885 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2886 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2887 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2888 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2889 interrupt-names = "msi0", 2890 "msi1", 2891 "msi2", 2892 "msi3", 2893 "msi4", 2894 "msi5", 2895 "msi6", 2896 "msi7"; 2897 2898 #interrupt-cells = <1>; 2899 interrupt-map-mask = <0 0 0 0x7>; 2900 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 2901 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 2902 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 2903 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 2904 2905 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2906 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2907 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 2908 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 2909 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 2910 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 2911 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 2912 clock-names = "aux", 2913 "cfg", 2914 "bus_master", 2915 "bus_slave", 2916 "slave_q2a", 2917 "noc_aggr", 2918 "cnoc_sf_axi"; 2919 2920 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 2921 assigned-clock-rates = <19200000>; 2922 2923 interconnects = <&pcie_south_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 2924 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2925 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2926 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; 2927 interconnect-names = "pcie-mem", 2928 "cpu-pcie"; 2929 2930 resets = <&gcc GCC_PCIE_4_BCR>, 2931 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 2932 reset-names = "pci", 2933 "link_down"; 2934 2935 power-domains = <&gcc GCC_PCIE_4_GDSC>; 2936 2937 phys = <&pcie4_phy>; 2938 phy-names = "pciephy"; 2939 2940 status = "disabled"; 2941 }; 2942 2943 pcie4_phy: phy@1c0e000 { 2944 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 2945 reg = <0 0x01c0e000 0 0x2000>; 2946 2947 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2948 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2949 <&rpmhcc RPMH_CXO_CLK>, 2950 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 2951 <&gcc GCC_PCIE_4_PIPE_CLK>; 2952 clock-names = "aux", 2953 "cfg_ahb", 2954 "ref", 2955 "rchng", 2956 "pipe"; 2957 2958 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 2959 reset-names = "phy"; 2960 2961 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 2962 assigned-clock-rates = <100000000>; 2963 2964 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 2965 2966 #clock-cells = <0>; 2967 clock-output-names = "pcie4_pipe_clk"; 2968 2969 #phy-cells = <0>; 2970 2971 status = "disabled"; 2972 }; 2973 2974 tcsr_mutex: hwlock@1f40000 { 2975 compatible = "qcom,tcsr-mutex"; 2976 reg = <0 0x01f40000 0 0x20000>; 2977 #hwlock-cells = <1>; 2978 }; 2979 2980 tcsr: clock-controller@1fc0000 { 2981 compatible = "qcom,x1e80100-tcsr", "syscon"; 2982 reg = <0 0x01fc0000 0 0x30000>; 2983 clocks = <&rpmhcc RPMH_CXO_CLK>; 2984 #clock-cells = <1>; 2985 #reset-cells = <1>; 2986 }; 2987 2988 gem_noc: interconnect@26400000 { 2989 compatible = "qcom,x1e80100-gem-noc"; 2990 reg = <0 0x26400000 0 0x311200>; 2991 2992 qcom,bcm-voters = <&apps_bcm_voter>; 2993 2994 #interconnect-cells = <2>; 2995 }; 2996 2997 nsp_noc: interconnect@320c0000 { 2998 compatible = "qcom,x1e80100-nsp-noc"; 2999 reg = <0 0x320C0000 0 0xE080>; 3000 3001 qcom,bcm-voters = <&apps_bcm_voter>; 3002 3003 #interconnect-cells = <2>; 3004 }; 3005 3006 lpass_wsa2macro: codec@6aa0000 { 3007 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 3008 reg = <0 0x06aa0000 0 0x1000>; 3009 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3010 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3011 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3012 <&lpass_vamacro>; 3013 clock-names = "mclk", 3014 "macro", 3015 "dcodec", 3016 "fsgen"; 3017 3018 #clock-cells = <0>; 3019 clock-output-names = "wsa2-mclk"; 3020 #sound-dai-cells = <1>; 3021 sound-name-prefix = "WSA2"; 3022 }; 3023 3024 swr3: soundwire@6ab0000 { 3025 compatible = "qcom,soundwire-v2.0.0"; 3026 reg = <0 0x06ab0000 0 0x10000>; 3027 clocks = <&lpass_wsa2macro>; 3028 clock-names = "iface"; 3029 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 3030 label = "WSA2"; 3031 3032 pinctrl-0 = <&wsa2_swr_active>; 3033 pinctrl-names = "default"; 3034 3035 qcom,din-ports = <4>; 3036 qcom,dout-ports = <9>; 3037 3038 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3039 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3040 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3041 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3042 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3043 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3044 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3045 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3046 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3047 3048 #address-cells = <2>; 3049 #size-cells = <0>; 3050 #sound-dai-cells = <1>; 3051 status = "disabled"; 3052 }; 3053 3054 lpass_rxmacro: codec@6ac0000 { 3055 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 3056 reg = <0 0x06ac0000 0 0x1000>; 3057 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3058 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3059 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3060 <&lpass_vamacro>; 3061 clock-names = "mclk", 3062 "macro", 3063 "dcodec", 3064 "fsgen"; 3065 3066 #clock-cells = <0>; 3067 clock-output-names = "mclk"; 3068 #sound-dai-cells = <1>; 3069 }; 3070 3071 swr1: soundwire@6ad0000 { 3072 compatible = "qcom,soundwire-v2.0.0"; 3073 reg = <0 0x06ad0000 0 0x10000>; 3074 clocks = <&lpass_rxmacro>; 3075 clock-names = "iface"; 3076 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 3077 label = "RX"; 3078 3079 pinctrl-0 = <&rx_swr_active>; 3080 pinctrl-names = "default"; 3081 3082 qcom,din-ports = <1>; 3083 qcom,dout-ports = <11>; 3084 3085 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3086 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3087 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3088 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3089 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3090 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3091 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3092 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3093 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3094 3095 #address-cells = <2>; 3096 #size-cells = <0>; 3097 #sound-dai-cells = <1>; 3098 status = "disabled"; 3099 }; 3100 3101 lpass_txmacro: codec@6ae0000 { 3102 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 3103 reg = <0 0x06ae0000 0 0x1000>; 3104 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3105 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3106 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3107 <&lpass_vamacro>; 3108 clock-names = "mclk", 3109 "macro", 3110 "dcodec", 3111 "fsgen"; 3112 3113 #clock-cells = <0>; 3114 clock-output-names = "mclk"; 3115 #sound-dai-cells = <1>; 3116 }; 3117 3118 lpass_wsamacro: codec@6b00000 { 3119 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 3120 reg = <0 0x06b00000 0 0x1000>; 3121 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3122 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3123 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3124 <&lpass_vamacro>; 3125 clock-names = "mclk", 3126 "macro", 3127 "dcodec", 3128 "fsgen"; 3129 3130 #clock-cells = <0>; 3131 clock-output-names = "mclk"; 3132 #sound-dai-cells = <1>; 3133 sound-name-prefix = "WSA"; 3134 }; 3135 3136 swr0: soundwire@6b10000 { 3137 compatible = "qcom,soundwire-v2.0.0"; 3138 reg = <0 0x06b10000 0 0x10000>; 3139 clocks = <&lpass_wsamacro>; 3140 clock-names = "iface"; 3141 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 3142 label = "WSA"; 3143 3144 pinctrl-0 = <&wsa_swr_active>; 3145 pinctrl-names = "default"; 3146 3147 qcom,din-ports = <4>; 3148 qcom,dout-ports = <9>; 3149 3150 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3151 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3152 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3153 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3154 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3155 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3156 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3157 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3158 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3159 3160 #address-cells = <2>; 3161 #size-cells = <0>; 3162 #sound-dai-cells = <1>; 3163 status = "disabled"; 3164 }; 3165 3166 swr2: soundwire@6d30000 { 3167 compatible = "qcom,soundwire-v2.0.0"; 3168 reg = <0 0x06d30000 0 0x10000>; 3169 clocks = <&lpass_txmacro>; 3170 clock-names = "iface"; 3171 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 3172 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 3173 interrupt-names = "core", "wakeup"; 3174 label = "TX"; 3175 3176 pinctrl-0 = <&tx_swr_active>; 3177 pinctrl-names = "default"; 3178 3179 qcom,din-ports = <4>; 3180 qcom,dout-ports = <1>; 3181 3182 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; 3183 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; 3184 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; 3185 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3186 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3187 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3188 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3189 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3190 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; 3191 3192 #address-cells = <2>; 3193 #size-cells = <0>; 3194 #sound-dai-cells = <1>; 3195 status = "disabled"; 3196 }; 3197 3198 lpass_vamacro: codec@6d44000 { 3199 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 3200 reg = <0 0x06d44000 0 0x1000>; 3201 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3202 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3203 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3204 clock-names = "mclk", 3205 "macro", 3206 "dcodec"; 3207 3208 #clock-cells = <0>; 3209 clock-output-names = "fsgen"; 3210 #sound-dai-cells = <1>; 3211 }; 3212 3213 lpass_tlmm: pinctrl@6e80000 { 3214 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl"; 3215 reg = <0 0x06e80000 0 0x20000>, 3216 <0 0x07250000 0 0x10000>; 3217 3218 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3219 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3220 clock-names = "core", "audio"; 3221 3222 gpio-controller; 3223 #gpio-cells = <2>; 3224 gpio-ranges = <&lpass_tlmm 0 0 23>; 3225 3226 tx_swr_active: tx-swr-active-state { 3227 clk-pins { 3228 pins = "gpio0"; 3229 function = "swr_tx_clk"; 3230 drive-strength = <2>; 3231 slew-rate = <1>; 3232 bias-disable; 3233 }; 3234 3235 data-pins { 3236 pins = "gpio1", "gpio2"; 3237 function = "swr_tx_data"; 3238 drive-strength = <2>; 3239 slew-rate = <1>; 3240 bias-bus-hold; 3241 }; 3242 }; 3243 3244 rx_swr_active: rx-swr-active-state { 3245 clk-pins { 3246 pins = "gpio3"; 3247 function = "swr_rx_clk"; 3248 drive-strength = <2>; 3249 slew-rate = <1>; 3250 bias-disable; 3251 }; 3252 3253 data-pins { 3254 pins = "gpio4", "gpio5"; 3255 function = "swr_rx_data"; 3256 drive-strength = <2>; 3257 slew-rate = <1>; 3258 bias-bus-hold; 3259 }; 3260 }; 3261 3262 dmic01_default: dmic01-default-state { 3263 clk-pins { 3264 pins = "gpio6"; 3265 function = "dmic1_clk"; 3266 drive-strength = <8>; 3267 output-high; 3268 }; 3269 3270 data-pins { 3271 pins = "gpio7"; 3272 function = "dmic1_data"; 3273 drive-strength = <8>; 3274 input-enable; 3275 }; 3276 }; 3277 3278 dmic23_default: dmic23-default-state { 3279 clk-pins { 3280 pins = "gpio8"; 3281 function = "dmic2_clk"; 3282 drive-strength = <8>; 3283 output-high; 3284 }; 3285 3286 data-pins { 3287 pins = "gpio9"; 3288 function = "dmic2_data"; 3289 drive-strength = <8>; 3290 input-enable; 3291 }; 3292 }; 3293 3294 wsa_swr_active: wsa-swr-active-state { 3295 clk-pins { 3296 pins = "gpio10"; 3297 function = "wsa_swr_clk"; 3298 drive-strength = <2>; 3299 slew-rate = <1>; 3300 bias-disable; 3301 }; 3302 3303 data-pins { 3304 pins = "gpio11"; 3305 function = "wsa_swr_data"; 3306 drive-strength = <2>; 3307 slew-rate = <1>; 3308 bias-bus-hold; 3309 }; 3310 }; 3311 3312 wsa2_swr_active: wsa2-swr-active-state { 3313 clk-pins { 3314 pins = "gpio15"; 3315 function = "wsa2_swr_clk"; 3316 drive-strength = <2>; 3317 slew-rate = <1>; 3318 bias-disable; 3319 }; 3320 3321 data-pins { 3322 pins = "gpio16"; 3323 function = "wsa2_swr_data"; 3324 drive-strength = <2>; 3325 slew-rate = <1>; 3326 bias-bus-hold; 3327 }; 3328 }; 3329 }; 3330 3331 lpass_ag_noc: interconnect@7e40000 { 3332 compatible = "qcom,x1e80100-lpass-ag-noc"; 3333 reg = <0 0x7e40000 0 0xE080>; 3334 3335 qcom,bcm-voters = <&apps_bcm_voter>; 3336 3337 #interconnect-cells = <2>; 3338 }; 3339 3340 lpass_lpiaon_noc: interconnect@7400000 { 3341 compatible = "qcom,x1e80100-lpass-lpiaon-noc"; 3342 reg = <0 0x7400000 0 0x19080>; 3343 3344 qcom,bcm-voters = <&apps_bcm_voter>; 3345 3346 #interconnect-cells = <2>; 3347 }; 3348 3349 lpass_lpicx_noc: interconnect@7430000 { 3350 compatible = "qcom,x1e80100-lpass-lpicx-noc"; 3351 reg = <0 0x7430000 0 0x3A200>; 3352 3353 qcom,bcm-voters = <&apps_bcm_voter>; 3354 3355 #interconnect-cells = <2>; 3356 }; 3357 3358 usb_2_hsphy: phy@88e0000 { 3359 compatible = "qcom,x1e80100-snps-eusb2-phy", 3360 "qcom,sm8550-snps-eusb2-phy"; 3361 reg = <0 0x088e0000 0 0x154>; 3362 #phy-cells = <0>; 3363 3364 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 3365 clock-names = "ref"; 3366 3367 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 3368 3369 status = "disabled"; 3370 }; 3371 3372 usb_1_ss2: usb@a0f8800 { 3373 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 3374 reg = <0 0x0a0f8800 0 0x400>; 3375 3376 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 3377 <&gcc GCC_USB30_TERT_MASTER_CLK>, 3378 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 3379 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 3380 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 3381 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3382 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 3383 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 3384 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3385 clock-names = "cfg_noc", 3386 "core", 3387 "iface", 3388 "sleep", 3389 "mock_utmi", 3390 "noc_aggr", 3391 "noc_aggr_north", 3392 "noc_aggr_south", 3393 "noc_sys"; 3394 3395 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 3396 <&gcc GCC_USB30_TERT_MASTER_CLK>; 3397 assigned-clock-rates = <19200000>, 3398 <200000000>; 3399 3400 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 3401 <&pdc 58 IRQ_TYPE_EDGE_BOTH>, 3402 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 3403 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; 3404 interrupt-names = "pwr_event", 3405 "dp_hs_phy_irq", 3406 "dm_hs_phy_irq", 3407 "ss_phy_irq"; 3408 3409 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 3410 required-opps = <&rpmhpd_opp_nom>; 3411 3412 resets = <&gcc GCC_USB30_TERT_BCR>; 3413 3414 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS 3415 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3416 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3417 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>; 3418 interconnect-names = "usb-ddr", 3419 "apps-usb"; 3420 3421 wakeup-source; 3422 3423 #address-cells = <2>; 3424 #size-cells = <2>; 3425 ranges; 3426 3427 status = "disabled"; 3428 3429 usb_1_ss2_dwc3: usb@a000000 { 3430 compatible = "snps,dwc3"; 3431 reg = <0 0x0a000000 0 0xcd00>; 3432 3433 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 3434 3435 iommus = <&apps_smmu 0x14a0 0x0>; 3436 3437 phys = <&usb_1_ss2_hsphy>, 3438 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; 3439 phy-names = "usb2-phy", 3440 "usb3-phy"; 3441 3442 snps,dis_u2_susphy_quirk; 3443 snps,dis_enblslpm_quirk; 3444 snps,usb3_lpm_capable; 3445 3446 dma-coherent; 3447 3448 port { 3449 usb_1_ss2_role_switch: endpoint { 3450 }; 3451 }; 3452 }; 3453 }; 3454 3455 usb_2: usb@a2f8800 { 3456 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 3457 reg = <0 0x0a2f8800 0 0x400>; 3458 #address-cells = <2>; 3459 #size-cells = <2>; 3460 ranges; 3461 3462 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 3463 <&gcc GCC_USB20_MASTER_CLK>, 3464 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 3465 <&gcc GCC_USB20_SLEEP_CLK>, 3466 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3467 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3468 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 3469 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 3470 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3471 clock-names = "cfg_noc", 3472 "core", 3473 "iface", 3474 "sleep", 3475 "mock_utmi", 3476 "noc_aggr", 3477 "noc_aggr_north", 3478 "noc_aggr_south", 3479 "noc_sys"; 3480 3481 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3482 <&gcc GCC_USB20_MASTER_CLK>; 3483 assigned-clock-rates = <19200000>, <200000000>; 3484 3485 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3486 <&pdc 50 IRQ_TYPE_EDGE_BOTH>, 3487 <&pdc 49 IRQ_TYPE_EDGE_BOTH>; 3488 interrupt-names = "pwr_event", 3489 "dp_hs_phy_irq", 3490 "dm_hs_phy_irq"; 3491 3492 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 3493 required-opps = <&rpmhpd_opp_nom>; 3494 3495 resets = <&gcc GCC_USB20_PRIM_BCR>; 3496 3497 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 3498 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3499 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3500 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; 3501 interconnect-names = "usb-ddr", 3502 "apps-usb"; 3503 3504 wakeup-source; 3505 3506 status = "disabled"; 3507 3508 usb_2_dwc3: usb@a200000 { 3509 compatible = "snps,dwc3"; 3510 reg = <0 0x0a200000 0 0xcd00>; 3511 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 3512 iommus = <&apps_smmu 0x14e0 0x0>; 3513 phys = <&usb_2_hsphy>; 3514 phy-names = "usb2-phy"; 3515 maximum-speed = "high-speed"; 3516 3517 port { 3518 usb_2_role_switch: endpoint { 3519 }; 3520 }; 3521 }; 3522 }; 3523 3524 usb_1_ss0: usb@a6f8800 { 3525 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 3526 reg = <0 0x0a6f8800 0 0x400>; 3527 3528 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3529 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3530 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3531 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3532 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3533 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3534 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>, 3535 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>, 3536 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3537 clock-names = "cfg_noc", 3538 "core", 3539 "iface", 3540 "sleep", 3541 "mock_utmi", 3542 "noc_aggr", 3543 "noc_aggr_north", 3544 "noc_aggr_south", 3545 "noc_sys"; 3546 3547 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3548 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3549 assigned-clock-rates = <19200000>, 3550 <200000000>; 3551 3552 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 3553 <&pdc 61 IRQ_TYPE_EDGE_BOTH>, 3554 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3555 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3556 interrupt-names = "pwr_event", 3557 "dp_hs_phy_irq", 3558 "dm_hs_phy_irq", 3559 "ss_phy_irq"; 3560 3561 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3562 required-opps = <&rpmhpd_opp_nom>; 3563 3564 resets = <&gcc GCC_USB30_PRIM_BCR>; 3565 3566 wakeup-source; 3567 3568 #address-cells = <2>; 3569 #size-cells = <2>; 3570 ranges; 3571 3572 status = "disabled"; 3573 3574 usb_1_ss0_dwc3: usb@a600000 { 3575 compatible = "snps,dwc3"; 3576 reg = <0 0x0a600000 0 0xcd00>; 3577 3578 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 3579 3580 iommus = <&apps_smmu 0x1420 0x0>; 3581 3582 phys = <&usb_1_ss0_hsphy>, 3583 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; 3584 phy-names = "usb2-phy", 3585 "usb3-phy"; 3586 3587 snps,dis_u2_susphy_quirk; 3588 snps,dis_enblslpm_quirk; 3589 snps,usb3_lpm_capable; 3590 3591 dma-coherent; 3592 3593 port { 3594 usb_1_ss0_role_switch: endpoint { 3595 }; 3596 }; 3597 }; 3598 }; 3599 3600 usb_1_ss1: usb@a8f8800 { 3601 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 3602 reg = <0 0x0a8f8800 0 0x400>; 3603 3604 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3605 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3606 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3607 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3608 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3609 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3610 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 3611 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 3612 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3613 clock-names = "cfg_noc", 3614 "core", 3615 "iface", 3616 "sleep", 3617 "mock_utmi", 3618 "noc_aggr", 3619 "noc_aggr_north", 3620 "noc_aggr_south", 3621 "noc_sys"; 3622 3623 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3624 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3625 assigned-clock-rates = <19200000>, 3626 <200000000>; 3627 3628 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 3629 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 3630 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 3631 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; 3632 interrupt-names = "pwr_event", 3633 "dp_hs_phy_irq", 3634 "dm_hs_phy_irq", 3635 "ss_phy_irq"; 3636 3637 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3638 required-opps = <&rpmhpd_opp_nom>; 3639 3640 resets = <&gcc GCC_USB30_SEC_BCR>; 3641 3642 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS 3643 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3644 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3645 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>; 3646 interconnect-names = "usb-ddr", 3647 "apps-usb"; 3648 3649 wakeup-source; 3650 3651 #address-cells = <2>; 3652 #size-cells = <2>; 3653 ranges; 3654 3655 status = "disabled"; 3656 3657 usb_1_ss1_dwc3: usb@a800000 { 3658 compatible = "snps,dwc3"; 3659 reg = <0 0x0a800000 0 0xcd00>; 3660 3661 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 3662 3663 iommus = <&apps_smmu 0x1460 0x0>; 3664 3665 phys = <&usb_1_ss1_hsphy>, 3666 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; 3667 phy-names = "usb2-phy", 3668 "usb3-phy"; 3669 3670 snps,dis_u2_susphy_quirk; 3671 snps,dis_enblslpm_quirk; 3672 snps,usb3_lpm_capable; 3673 3674 dma-coherent; 3675 3676 port { 3677 usb_1_ss1_role_switch: endpoint { 3678 }; 3679 }; 3680 }; 3681 }; 3682 3683 mdss: display-subsystem@ae00000 { 3684 compatible = "qcom,x1e80100-mdss"; 3685 reg = <0 0x0ae00000 0 0x1000>; 3686 reg-names = "mdss"; 3687 3688 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3689 3690 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3691 <&gcc GCC_DISP_HF_AXI_CLK>, 3692 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3693 3694 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3695 3696 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 3697 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 3698 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 3699 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3700 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3701 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3702 interconnect-names = "mdp0-mem", 3703 "mdp1-mem", 3704 "cpu-cfg"; 3705 3706 power-domains = <&dispcc MDSS_GDSC>; 3707 3708 iommus = <&apps_smmu 0x1c00 0x2>; 3709 3710 interrupt-controller; 3711 #interrupt-cells = <1>; 3712 3713 #address-cells = <2>; 3714 #size-cells = <2>; 3715 ranges; 3716 3717 status = "disabled"; 3718 3719 mdss_mdp: display-controller@ae01000 { 3720 compatible = "qcom,x1e80100-dpu"; 3721 reg = <0 0x0ae01000 0 0x8f000>, 3722 <0 0x0aeb0000 0 0x2008>; 3723 reg-names = "mdp", 3724 "vbif"; 3725 3726 interrupts-extended = <&mdss 0>; 3727 3728 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3729 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3730 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3731 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3732 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3733 clock-names = "nrt_bus", 3734 "iface", 3735 "lut", 3736 "core", 3737 "vsync"; 3738 3739 operating-points-v2 = <&mdp_opp_table>; 3740 3741 power-domains = <&rpmhpd RPMHPD_MMCX>; 3742 3743 ports { 3744 #address-cells = <1>; 3745 #size-cells = <0>; 3746 3747 port@0 { 3748 reg = <0>; 3749 3750 mdss_intf0_out: endpoint { 3751 remote-endpoint = <&mdss_dp0_in>; 3752 }; 3753 }; 3754 3755 port@4 { 3756 reg = <4>; 3757 3758 mdss_intf4_out: endpoint { 3759 remote-endpoint = <&mdss_dp1_in>; 3760 }; 3761 }; 3762 3763 port@5 { 3764 reg = <5>; 3765 3766 mdss_intf5_out: endpoint { 3767 remote-endpoint = <&mdss_dp3_in>; 3768 }; 3769 }; 3770 3771 port@6 { 3772 reg = <6>; 3773 3774 mdss_intf6_out: endpoint { 3775 remote-endpoint = <&mdss_dp2_in>; 3776 }; 3777 }; 3778 }; 3779 3780 mdp_opp_table: opp-table { 3781 compatible = "operating-points-v2"; 3782 3783 opp-200000000 { 3784 opp-hz = /bits/ 64 <200000000>; 3785 required-opps = <&rpmhpd_opp_low_svs>; 3786 }; 3787 3788 opp-325000000 { 3789 opp-hz = /bits/ 64 <325000000>; 3790 required-opps = <&rpmhpd_opp_svs>; 3791 }; 3792 3793 opp-375000000 { 3794 opp-hz = /bits/ 64 <375000000>; 3795 required-opps = <&rpmhpd_opp_svs_l1>; 3796 }; 3797 3798 opp-514000000 { 3799 opp-hz = /bits/ 64 <514000000>; 3800 required-opps = <&rpmhpd_opp_nom>; 3801 }; 3802 3803 opp-575000000 { 3804 opp-hz = /bits/ 64 <575000000>; 3805 required-opps = <&rpmhpd_opp_nom_l1>; 3806 }; 3807 }; 3808 }; 3809 3810 mdss_dp0: displayport-controller@ae90000 { 3811 compatible = "qcom,x1e80100-dp"; 3812 reg = <0 0xae90000 0 0x200>, 3813 <0 0xae90200 0 0x200>, 3814 <0 0xae90400 0 0x600>, 3815 <0 0xae91000 0 0x400>, 3816 <0 0xae91400 0 0x400>; 3817 3818 interrupts-extended = <&mdss 12>; 3819 3820 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3821 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3822 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3823 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3824 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3825 clock-names = "core_iface", 3826 "core_aux", 3827 "ctrl_link", 3828 "ctrl_link_iface", 3829 "stream_pixel"; 3830 3831 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3832 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3833 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3834 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3835 3836 operating-points-v2 = <&mdss_dp0_opp_table>; 3837 3838 power-domains = <&rpmhpd RPMHPD_MMCX>; 3839 3840 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; 3841 phy-names = "dp"; 3842 3843 #sound-dai-cells = <0>; 3844 3845 status = "disabled"; 3846 3847 ports { 3848 #address-cells = <1>; 3849 #size-cells = <0>; 3850 3851 port@0 { 3852 reg = <0>; 3853 3854 mdss_dp0_in: endpoint { 3855 remote-endpoint = <&mdss_intf0_out>; 3856 }; 3857 }; 3858 3859 port@1 { 3860 reg = <1>; 3861 3862 mdss_dp0_out: endpoint { 3863 }; 3864 }; 3865 }; 3866 3867 mdss_dp0_opp_table: opp-table { 3868 compatible = "operating-points-v2"; 3869 3870 opp-160000000 { 3871 opp-hz = /bits/ 64 <160000000>; 3872 required-opps = <&rpmhpd_opp_low_svs>; 3873 }; 3874 3875 opp-270000000 { 3876 opp-hz = /bits/ 64 <270000000>; 3877 required-opps = <&rpmhpd_opp_svs>; 3878 }; 3879 3880 opp-540000000 { 3881 opp-hz = /bits/ 64 <540000000>; 3882 required-opps = <&rpmhpd_opp_svs_l1>; 3883 }; 3884 3885 opp-810000000 { 3886 opp-hz = /bits/ 64 <810000000>; 3887 required-opps = <&rpmhpd_opp_nom>; 3888 }; 3889 }; 3890 }; 3891 3892 mdss_dp1: displayport-controller@ae98000 { 3893 compatible = "qcom,x1e80100-dp"; 3894 reg = <0 0xae98000 0 0x200>, 3895 <0 0xae98200 0 0x200>, 3896 <0 0xae98400 0 0x600>, 3897 <0 0xae99000 0 0x400>, 3898 <0 0xae99400 0 0x400>; 3899 3900 interrupts-extended = <&mdss 13>; 3901 3902 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3903 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 3904 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 3905 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 3906 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 3907 clock-names = "core_iface", 3908 "core_aux", 3909 "ctrl_link", 3910 "ctrl_link_iface", 3911 "stream_pixel"; 3912 3913 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 3914 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 3915 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3916 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3917 3918 operating-points-v2 = <&mdss_dp1_opp_table>; 3919 3920 power-domains = <&rpmhpd RPMHPD_MMCX>; 3921 3922 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; 3923 phy-names = "dp"; 3924 3925 #sound-dai-cells = <0>; 3926 3927 status = "disabled"; 3928 3929 ports { 3930 #address-cells = <1>; 3931 #size-cells = <0>; 3932 3933 port@0 { 3934 reg = <0>; 3935 3936 mdss_dp1_in: endpoint { 3937 remote-endpoint = <&mdss_intf4_out>; 3938 }; 3939 }; 3940 3941 port@1 { 3942 reg = <1>; 3943 3944 mdss_dp1_out: endpoint { 3945 }; 3946 }; 3947 }; 3948 3949 mdss_dp1_opp_table: opp-table { 3950 compatible = "operating-points-v2"; 3951 3952 opp-160000000 { 3953 opp-hz = /bits/ 64 <160000000>; 3954 required-opps = <&rpmhpd_opp_low_svs>; 3955 }; 3956 3957 opp-270000000 { 3958 opp-hz = /bits/ 64 <270000000>; 3959 required-opps = <&rpmhpd_opp_svs>; 3960 }; 3961 3962 opp-540000000 { 3963 opp-hz = /bits/ 64 <540000000>; 3964 required-opps = <&rpmhpd_opp_svs_l1>; 3965 }; 3966 3967 opp-810000000 { 3968 opp-hz = /bits/ 64 <810000000>; 3969 required-opps = <&rpmhpd_opp_nom>; 3970 }; 3971 }; 3972 }; 3973 3974 mdss_dp2: displayport-controller@ae9a000 { 3975 compatible = "qcom,x1e80100-dp"; 3976 reg = <0 0xae9a000 0 0x200>, 3977 <0 0xae9a200 0 0x200>, 3978 <0 0xae9a400 0 0x600>, 3979 <0 0xae9b000 0 0x400>, 3980 <0 0xae9b400 0 0x400>; 3981 3982 interrupts-extended = <&mdss 14>; 3983 3984 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3985 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 3986 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 3987 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 3988 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 3989 clock-names = "core_iface", 3990 "core_aux", 3991 "ctrl_link", 3992 "ctrl_link_iface", 3993 "stream_pixel"; 3994 3995 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 3996 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 3997 assigned-clock-parents = <&mdss_dp2_phy 0>, 3998 <&mdss_dp2_phy 1>; 3999 4000 operating-points-v2 = <&mdss_dp2_opp_table>; 4001 4002 power-domains = <&rpmhpd RPMHPD_MMCX>; 4003 4004 phys = <&mdss_dp2_phy>; 4005 phy-names = "dp"; 4006 4007 #sound-dai-cells = <0>; 4008 4009 status = "disabled"; 4010 4011 ports { 4012 #address-cells = <1>; 4013 #size-cells = <0>; 4014 4015 port@0 { 4016 reg = <0>; 4017 mdss_dp2_in: endpoint { 4018 remote-endpoint = <&mdss_intf6_out>; 4019 }; 4020 }; 4021 4022 port@1 { 4023 reg = <1>; 4024 }; 4025 }; 4026 4027 mdss_dp2_opp_table: opp-table { 4028 compatible = "operating-points-v2"; 4029 4030 opp-160000000 { 4031 opp-hz = /bits/ 64 <160000000>; 4032 required-opps = <&rpmhpd_opp_low_svs>; 4033 }; 4034 4035 opp-270000000 { 4036 opp-hz = /bits/ 64 <270000000>; 4037 required-opps = <&rpmhpd_opp_svs>; 4038 }; 4039 4040 opp-540000000 { 4041 opp-hz = /bits/ 64 <540000000>; 4042 required-opps = <&rpmhpd_opp_svs_l1>; 4043 }; 4044 4045 opp-810000000 { 4046 opp-hz = /bits/ 64 <810000000>; 4047 required-opps = <&rpmhpd_opp_nom>; 4048 }; 4049 }; 4050 }; 4051 4052 mdss_dp3: displayport-controller@aea0000 { 4053 compatible = "qcom,x1e80100-dp"; 4054 reg = <0 0xaea0000 0 0x200>, 4055 <0 0xaea0200 0 0x200>, 4056 <0 0xaea0400 0 0x600>, 4057 <0 0xaea1000 0 0x400>, 4058 <0 0xaea1400 0 0x400>; 4059 4060 interrupts-extended = <&mdss 15>; 4061 4062 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4063 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 4064 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 4065 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4066 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4067 clock-names = "core_iface", 4068 "core_aux", 4069 "ctrl_link", 4070 "ctrl_link_iface", 4071 "stream_pixel"; 4072 4073 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4074 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4075 assigned-clock-parents = <&mdss_dp3_phy 0>, 4076 <&mdss_dp3_phy 1>; 4077 4078 operating-points-v2 = <&mdss_dp3_opp_table>; 4079 4080 power-domains = <&rpmhpd RPMHPD_MMCX>; 4081 4082 phys = <&mdss_dp3_phy>; 4083 phy-names = "dp"; 4084 4085 #sound-dai-cells = <0>; 4086 4087 status = "disabled"; 4088 4089 ports { 4090 #address-cells = <1>; 4091 #size-cells = <0>; 4092 4093 port@0 { 4094 reg = <0>; 4095 4096 mdss_dp3_in: endpoint { 4097 remote-endpoint = <&mdss_intf5_out>; 4098 }; 4099 }; 4100 4101 port@1 { 4102 reg = <1>; 4103 }; 4104 }; 4105 4106 mdss_dp3_opp_table: opp-table { 4107 compatible = "operating-points-v2"; 4108 4109 opp-160000000 { 4110 opp-hz = /bits/ 64 <160000000>; 4111 required-opps = <&rpmhpd_opp_low_svs>; 4112 }; 4113 4114 opp-270000000 { 4115 opp-hz = /bits/ 64 <270000000>; 4116 required-opps = <&rpmhpd_opp_svs>; 4117 }; 4118 4119 opp-540000000 { 4120 opp-hz = /bits/ 64 <540000000>; 4121 required-opps = <&rpmhpd_opp_svs_l1>; 4122 }; 4123 4124 opp-810000000 { 4125 opp-hz = /bits/ 64 <810000000>; 4126 required-opps = <&rpmhpd_opp_nom>; 4127 }; 4128 }; 4129 }; 4130 4131 }; 4132 4133 mdss_dp2_phy: phy@aec2a00 { 4134 compatible = "qcom,x1e80100-dp-phy"; 4135 reg = <0 0x0aec2a00 0 0x19c>, 4136 <0 0x0aec2200 0 0xec>, 4137 <0 0x0aec2600 0 0xec>, 4138 <0 0x0aec2000 0 0x1c8>; 4139 4140 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 4141 <&dispcc DISP_CC_MDSS_AHB_CLK>; 4142 clock-names = "aux", 4143 "cfg_ahb"; 4144 4145 power-domains = <&rpmhpd RPMHPD_MX>; 4146 4147 #clock-cells = <1>; 4148 #phy-cells = <0>; 4149 4150 status = "disabled"; 4151 }; 4152 4153 mdss_dp3_phy: phy@aec5a00 { 4154 compatible = "qcom,x1e80100-dp-phy"; 4155 reg = <0 0x0aec5a00 0 0x19c>, 4156 <0 0x0aec5200 0 0xec>, 4157 <0 0x0aec5600 0 0xec>, 4158 <0 0x0aec5000 0 0x1c8>; 4159 4160 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 4161 <&dispcc DISP_CC_MDSS_AHB_CLK>; 4162 clock-names = "aux", 4163 "cfg_ahb"; 4164 4165 power-domains = <&rpmhpd RPMHPD_MX>; 4166 4167 #clock-cells = <1>; 4168 #phy-cells = <0>; 4169 4170 status = "disabled"; 4171 }; 4172 4173 dispcc: clock-controller@af00000 { 4174 compatible = "qcom,x1e80100-dispcc"; 4175 reg = <0 0x0af00000 0 0x20000>; 4176 clocks = <&bi_tcxo_div2>, 4177 <&bi_tcxo_ao_div2>, 4178 <&gcc GCC_DISP_AHB_CLK>, 4179 <&sleep_clk>, 4180 <0>, /* dsi0 */ 4181 <0>, 4182 <0>, /* dsi1 */ 4183 <0>, 4184 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 4185 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4186 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 4187 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4188 <&mdss_dp2_phy 0>, /* dp2 */ 4189 <&mdss_dp2_phy 1>, 4190 <&mdss_dp3_phy 0>, /* dp3 */ 4191 <&mdss_dp3_phy 1>; 4192 power-domains = <&rpmhpd RPMHPD_MMCX>; 4193 required-opps = <&rpmhpd_opp_low_svs>; 4194 #clock-cells = <1>; 4195 #reset-cells = <1>; 4196 #power-domain-cells = <1>; 4197 }; 4198 4199 pdc: interrupt-controller@b220000 { 4200 compatible = "qcom,x1e80100-pdc", "qcom,pdc"; 4201 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 4202 4203 qcom,pdc-ranges = <0 480 42>, <42 251 5>, 4204 <47 522 52>, <99 609 32>, 4205 <131 717 12>, <143 816 19>; 4206 #interrupt-cells = <2>; 4207 interrupt-parent = <&intc>; 4208 interrupt-controller; 4209 }; 4210 4211 aoss_qmp: power-management@c300000 { 4212 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp"; 4213 reg = <0 0x0c300000 0 0x400>; 4214 interrupt-parent = <&ipcc>; 4215 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4216 IRQ_TYPE_EDGE_RISING>; 4217 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4218 4219 #clock-cells = <0>; 4220 }; 4221 4222 spmi: arbiter@c400000 { 4223 compatible = "qcom,x1e80100-spmi-pmic-arb"; 4224 reg = <0 0x0c400000 0 0x3000>, 4225 <0 0x0c500000 0 0x400000>, 4226 <0 0x0c440000 0 0x80000>; 4227 reg-names = "core", "chnls", "obsrvr"; 4228 4229 qcom,ee = <0>; 4230 qcom,channel = <0>; 4231 4232 #address-cells = <2>; 4233 #size-cells = <2>; 4234 ranges; 4235 4236 spmi_bus0: spmi@c42d000 { 4237 reg = <0 0x0c42d000 0 0x4000>, 4238 <0 0x0c4c0000 0 0x10000>; 4239 reg-names = "cnfg", "intr"; 4240 4241 interrupt-names = "periph_irq"; 4242 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4243 interrupt-controller; 4244 #interrupt-cells = <4>; 4245 4246 #address-cells = <2>; 4247 #size-cells = <0>; 4248 }; 4249 4250 spmi_bus1: spmi@c432000 { 4251 reg = <0 0x0c432000 0 0x4000>, 4252 <0 0x0c4d0000 0 0x10000>; 4253 reg-names = "cnfg", "intr"; 4254 4255 interrupt-names = "periph_irq"; 4256 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 4257 interrupt-controller; 4258 #interrupt-cells = <4>; 4259 4260 #address-cells = <2>; 4261 #size-cells = <0>; 4262 }; 4263 }; 4264 4265 tlmm: pinctrl@f100000 { 4266 compatible = "qcom,x1e80100-tlmm"; 4267 reg = <0 0x0f100000 0 0xf00000>; 4268 4269 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4270 4271 gpio-controller; 4272 #gpio-cells = <2>; 4273 4274 interrupt-controller; 4275 #interrupt-cells = <2>; 4276 4277 gpio-ranges = <&tlmm 0 0 239>; 4278 wakeup-parent = <&pdc>; 4279 4280 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4281 /* SDA, SCL */ 4282 pins = "gpio0", "gpio1"; 4283 function = "qup0_se0"; 4284 drive-strength = <2>; 4285 bias-pull-up = <2200>; 4286 }; 4287 4288 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4289 /* SDA, SCL */ 4290 pins = "gpio4", "gpio5"; 4291 function = "qup0_se1"; 4292 drive-strength = <2>; 4293 bias-pull-up = <2200>; 4294 }; 4295 4296 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4297 /* SDA, SCL */ 4298 pins = "gpio8", "gpio9"; 4299 function = "qup0_se2"; 4300 drive-strength = <2>; 4301 bias-pull-up = <2200>; 4302 }; 4303 4304 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4305 /* SDA, SCL */ 4306 pins = "gpio12", "gpio13"; 4307 function = "qup0_se3"; 4308 drive-strength = <2>; 4309 bias-pull-up = <2200>; 4310 }; 4311 4312 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4313 /* SDA, SCL */ 4314 pins = "gpio16", "gpio17"; 4315 function = "qup0_se4"; 4316 drive-strength = <2>; 4317 bias-pull-up = <2200>; 4318 }; 4319 4320 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4321 /* SDA, SCL */ 4322 pins = "gpio20", "gpio21"; 4323 function = "qup0_se5"; 4324 drive-strength = <2>; 4325 bias-pull-up = <2200>; 4326 }; 4327 4328 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4329 /* SDA, SCL */ 4330 pins = "gpio24", "gpio25"; 4331 function = "qup0_se6"; 4332 drive-strength = <2>; 4333 bias-pull-up = <2200>; 4334 }; 4335 4336 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4337 /* SDA, SCL */ 4338 pins = "gpio14", "gpio15"; 4339 function = "qup0_se7"; 4340 drive-strength = <2>; 4341 bias-pull-up = <2200>; 4342 }; 4343 4344 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4345 /* SDA, SCL */ 4346 pins = "gpio32", "gpio33"; 4347 function = "qup1_se0"; 4348 drive-strength = <2>; 4349 bias-pull-up = <2200>; 4350 }; 4351 4352 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4353 /* SDA, SCL */ 4354 pins = "gpio36", "gpio37"; 4355 function = "qup1_se1"; 4356 drive-strength = <2>; 4357 bias-pull-up = <2200>; 4358 }; 4359 4360 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4361 /* SDA, SCL */ 4362 pins = "gpio40", "gpio41"; 4363 function = "qup1_se2"; 4364 drive-strength = <2>; 4365 bias-pull-up = <2200>; 4366 }; 4367 4368 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4369 /* SDA, SCL */ 4370 pins = "gpio44", "gpio45"; 4371 function = "qup1_se3"; 4372 drive-strength = <2>; 4373 bias-pull-up = <2200>; 4374 }; 4375 4376 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4377 /* SDA, SCL */ 4378 pins = "gpio48", "gpio49"; 4379 function = "qup1_se4"; 4380 drive-strength = <2>; 4381 bias-pull-up = <2200>; 4382 }; 4383 4384 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4385 /* SDA, SCL */ 4386 pins = "gpio52", "gpio53"; 4387 function = "qup1_se5"; 4388 drive-strength = <2>; 4389 bias-pull-up = <2200>; 4390 }; 4391 4392 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4393 /* SDA, SCL */ 4394 pins = "gpio56", "gpio57"; 4395 function = "qup1_se6"; 4396 drive-strength = <2>; 4397 bias-pull-up = <2200>; 4398 }; 4399 4400 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4401 /* SDA, SCL */ 4402 pins = "gpio54", "gpio55"; 4403 function = "qup1_se7"; 4404 drive-strength = <2>; 4405 bias-pull-up = <2200>; 4406 }; 4407 4408 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 4409 /* SDA, SCL */ 4410 pins = "gpio64", "gpio65"; 4411 function = "qup2_se0"; 4412 drive-strength = <2>; 4413 bias-pull-up = <2200>; 4414 }; 4415 4416 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 4417 /* SDA, SCL */ 4418 pins = "gpio68", "gpio69"; 4419 function = "qup2_se1"; 4420 drive-strength = <2>; 4421 bias-pull-up = <2200>; 4422 }; 4423 4424 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 4425 /* SDA, SCL */ 4426 pins = "gpio72", "gpio73"; 4427 function = "qup2_se2"; 4428 drive-strength = <2>; 4429 bias-pull-up = <2200>; 4430 }; 4431 4432 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 4433 /* SDA, SCL */ 4434 pins = "gpio76", "gpio77"; 4435 function = "qup2_se3"; 4436 drive-strength = <2>; 4437 bias-pull-up = <2200>; 4438 }; 4439 4440 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 4441 /* SDA, SCL */ 4442 pins = "gpio80", "gpio81"; 4443 function = "qup2_se4"; 4444 drive-strength = <2>; 4445 bias-pull-up = <2200>; 4446 }; 4447 4448 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 4449 /* SDA, SCL */ 4450 pins = "gpio84", "gpio85"; 4451 function = "qup2_se5"; 4452 drive-strength = <2>; 4453 bias-pull-up = <2200>; 4454 }; 4455 4456 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 4457 /* SDA, SCL */ 4458 pins = "gpio88", "gpio89"; 4459 function = "qup2_se6"; 4460 drive-strength = <2>; 4461 bias-pull-up = <2200>; 4462 }; 4463 4464 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 4465 /* SDA, SCL */ 4466 pins = "gpio86", "gpio87"; 4467 function = "qup2_se7"; 4468 drive-strength = <2>; 4469 bias-pull-up = <2200>; 4470 }; 4471 4472 qup_spi0_cs: qup-spi0-cs-state { 4473 pins = "gpio3"; 4474 function = "qup0_se0"; 4475 drive-strength = <6>; 4476 bias-disable; 4477 }; 4478 4479 qup_spi0_data_clk: qup-spi0-data-clk-state { 4480 /* MISO, MOSI, CLK */ 4481 pins = "gpio0", "gpio1", "gpio2"; 4482 function = "qup0_se0"; 4483 drive-strength = <6>; 4484 bias-disable; 4485 }; 4486 4487 qup_spi1_cs: qup-spi1-cs-state { 4488 pins = "gpio7"; 4489 function = "qup0_se1"; 4490 drive-strength = <6>; 4491 bias-disable; 4492 }; 4493 4494 qup_spi1_data_clk: qup-spi1-data-clk-state { 4495 /* MISO, MOSI, CLK */ 4496 pins = "gpio4", "gpio5", "gpio6"; 4497 function = "qup0_se1"; 4498 drive-strength = <6>; 4499 bias-disable; 4500 }; 4501 4502 qup_spi2_cs: qup-spi2-cs-state { 4503 pins = "gpio11"; 4504 function = "qup0_se2"; 4505 drive-strength = <6>; 4506 bias-disable; 4507 }; 4508 4509 qup_spi2_data_clk: qup-spi2-data-clk-state { 4510 /* MISO, MOSI, CLK */ 4511 pins = "gpio8", "gpio9", "gpio10"; 4512 function = "qup0_se2"; 4513 drive-strength = <6>; 4514 bias-disable; 4515 }; 4516 4517 qup_spi3_cs: qup-spi3-cs-state { 4518 pins = "gpio15"; 4519 function = "qup0_se3"; 4520 drive-strength = <6>; 4521 bias-disable; 4522 }; 4523 4524 qup_spi3_data_clk: qup-spi3-data-clk-state { 4525 /* MISO, MOSI, CLK */ 4526 pins = "gpio12", "gpio13", "gpio14"; 4527 function = "qup0_se3"; 4528 drive-strength = <6>; 4529 bias-disable; 4530 }; 4531 4532 qup_spi4_cs: qup-spi4-cs-state { 4533 pins = "gpio19"; 4534 function = "qup0_se4"; 4535 drive-strength = <6>; 4536 bias-disable; 4537 }; 4538 4539 qup_spi4_data_clk: qup-spi4-data-clk-state { 4540 /* MISO, MOSI, CLK */ 4541 pins = "gpio16", "gpio17", "gpio18"; 4542 function = "qup0_se4"; 4543 drive-strength = <6>; 4544 bias-disable; 4545 }; 4546 4547 qup_spi5_cs: qup-spi5-cs-state { 4548 pins = "gpio23"; 4549 function = "qup0_se5"; 4550 drive-strength = <6>; 4551 bias-disable; 4552 }; 4553 4554 qup_spi5_data_clk: qup-spi5-data-clk-state { 4555 /* MISO, MOSI, CLK */ 4556 pins = "gpio20", "gpio21", "gpio22"; 4557 function = "qup0_se5"; 4558 drive-strength = <6>; 4559 bias-disable; 4560 }; 4561 4562 qup_spi6_cs: qup-spi6-cs-state { 4563 pins = "gpio27"; 4564 function = "qup0_se6"; 4565 drive-strength = <6>; 4566 bias-disable; 4567 }; 4568 4569 qup_spi6_data_clk: qup-spi6-data-clk-state { 4570 /* MISO, MOSI, CLK */ 4571 pins = "gpio24", "gpio25", "gpio26"; 4572 function = "qup0_se6"; 4573 drive-strength = <6>; 4574 bias-disable; 4575 }; 4576 4577 qup_spi7_cs: qup-spi7-cs-state { 4578 pins = "gpio13"; 4579 function = "qup0_se7"; 4580 drive-strength = <6>; 4581 bias-disable; 4582 }; 4583 4584 qup_spi7_data_clk: qup-spi7-data-clk-state { 4585 /* MISO, MOSI, CLK */ 4586 pins = "gpio14", "gpio15", "gpio12"; 4587 function = "qup0_se7"; 4588 drive-strength = <6>; 4589 bias-disable; 4590 }; 4591 4592 qup_spi8_cs: qup-spi8-cs-state { 4593 pins = "gpio35"; 4594 function = "qup1_se0"; 4595 drive-strength = <6>; 4596 bias-disable; 4597 }; 4598 4599 qup_spi8_data_clk: qup-spi8-data-clk-state { 4600 /* MISO, MOSI, CLK */ 4601 pins = "gpio32", "gpio33", "gpio34"; 4602 function = "qup1_se0"; 4603 drive-strength = <6>; 4604 bias-disable; 4605 }; 4606 4607 qup_spi9_cs: qup-spi9-cs-state { 4608 pins = "gpio39"; 4609 function = "qup1_se1"; 4610 drive-strength = <6>; 4611 bias-disable; 4612 }; 4613 4614 qup_spi9_data_clk: qup-spi9-data-clk-state { 4615 /* MISO, MOSI, CLK */ 4616 pins = "gpio36", "gpio37", "gpio38"; 4617 function = "qup1_se1"; 4618 drive-strength = <6>; 4619 bias-disable; 4620 }; 4621 4622 qup_spi10_cs: qup-spi10-cs-state { 4623 pins = "gpio43"; 4624 function = "qup1_se2"; 4625 drive-strength = <6>; 4626 bias-disable; 4627 }; 4628 4629 qup_spi10_data_clk: qup-spi10-data-clk-state { 4630 /* MISO, MOSI, CLK */ 4631 pins = "gpio40", "gpio41", "gpio42"; 4632 function = "qup1_se2"; 4633 drive-strength = <6>; 4634 bias-disable; 4635 }; 4636 4637 qup_spi11_cs: qup-spi11-cs-state { 4638 pins = "gpio47"; 4639 function = "qup1_se3"; 4640 drive-strength = <6>; 4641 bias-disable; 4642 }; 4643 4644 qup_spi11_data_clk: qup-spi11-data-clk-state { 4645 /* MISO, MOSI, CLK */ 4646 pins = "gpio44", "gpio45", "gpio46"; 4647 function = "qup1_se3"; 4648 drive-strength = <6>; 4649 bias-disable; 4650 }; 4651 4652 qup_spi12_cs: qup-spi12-cs-state { 4653 pins = "gpio51"; 4654 function = "qup1_se4"; 4655 drive-strength = <6>; 4656 bias-disable; 4657 }; 4658 4659 qup_spi12_data_clk: qup-spi12-data-clk-state { 4660 /* MISO, MOSI, CLK */ 4661 pins = "gpio48", "gpio49", "gpio50"; 4662 function = "qup1_se4"; 4663 drive-strength = <6>; 4664 bias-disable; 4665 }; 4666 4667 qup_spi13_cs: qup-spi13-cs-state { 4668 pins = "gpio55"; 4669 function = "qup1_se5"; 4670 drive-strength = <6>; 4671 bias-disable; 4672 }; 4673 4674 qup_spi13_data_clk: qup-spi13-data-clk-state { 4675 /* MISO, MOSI, CLK */ 4676 pins = "gpio52", "gpio53", "gpio54"; 4677 function = "qup1_se5"; 4678 drive-strength = <6>; 4679 bias-disable; 4680 }; 4681 4682 qup_spi14_cs: qup-spi14-cs-state { 4683 pins = "gpio59"; 4684 function = "qup1_se6"; 4685 drive-strength = <6>; 4686 bias-disable; 4687 }; 4688 4689 qup_spi14_data_clk: qup-spi14-data-clk-state { 4690 /* MISO, MOSI, CLK */ 4691 pins = "gpio56", "gpio57", "gpio58"; 4692 function = "qup1_se6"; 4693 drive-strength = <6>; 4694 bias-disable; 4695 }; 4696 4697 qup_spi15_cs: qup-spi15-cs-state { 4698 pins = "gpio53"; 4699 function = "qup1_se7"; 4700 drive-strength = <6>; 4701 bias-disable; 4702 }; 4703 4704 qup_spi15_data_clk: qup-spi15-data-clk-state { 4705 /* MISO, MOSI, CLK */ 4706 pins = "gpio54", "gpio55", "gpio52"; 4707 function = "qup1_se7"; 4708 drive-strength = <6>; 4709 bias-disable; 4710 }; 4711 4712 qup_spi16_cs: qup-spi16-cs-state { 4713 pins = "gpio67"; 4714 function = "qup2_se0"; 4715 drive-strength = <6>; 4716 bias-disable; 4717 }; 4718 4719 qup_spi16_data_clk: qup-spi16-data-clk-state { 4720 /* MISO, MOSI, CLK */ 4721 pins = "gpio64", "gpio65", "gpio66"; 4722 function = "qup2_se0"; 4723 drive-strength = <6>; 4724 bias-disable; 4725 }; 4726 4727 qup_spi17_cs: qup-spi17-cs-state { 4728 pins = "gpio71"; 4729 function = "qup2_se1"; 4730 drive-strength = <6>; 4731 bias-disable; 4732 }; 4733 4734 qup_spi17_data_clk: qup-spi17-data-clk-state { 4735 /* MISO, MOSI, CLK */ 4736 pins = "gpio68", "gpio69", "gpio70"; 4737 function = "qup2_se1"; 4738 drive-strength = <6>; 4739 bias-disable; 4740 }; 4741 4742 qup_spi18_cs: qup-spi18-cs-state { 4743 pins = "gpio75"; 4744 function = "qup2_se2"; 4745 drive-strength = <6>; 4746 bias-disable; 4747 }; 4748 4749 qup_spi18_data_clk: qup-spi18-data-clk-state { 4750 /* MISO, MOSI, CLK */ 4751 pins = "gpio72", "gpio73", "gpio74"; 4752 function = "qup2_se2"; 4753 drive-strength = <6>; 4754 bias-disable; 4755 }; 4756 4757 qup_spi19_cs: qup-spi19-cs-state { 4758 pins = "gpio79"; 4759 function = "qup2_se3"; 4760 drive-strength = <6>; 4761 bias-disable; 4762 }; 4763 4764 qup_spi19_data_clk: qup-spi19-data-clk-state { 4765 /* MISO, MOSI, CLK */ 4766 pins = "gpio76", "gpio77", "gpio78"; 4767 function = "qup2_se3"; 4768 drive-strength = <6>; 4769 bias-disable; 4770 }; 4771 4772 qup_spi20_cs: qup-spi20-cs-state { 4773 pins = "gpio83"; 4774 function = "qup2_se4"; 4775 drive-strength = <6>; 4776 bias-disable; 4777 }; 4778 4779 qup_spi20_data_clk: qup-spi20-data-clk-state { 4780 /* MISO, MOSI, CLK */ 4781 pins = "gpio80", "gpio81", "gpio82"; 4782 function = "qup2_se4"; 4783 drive-strength = <6>; 4784 bias-disable; 4785 }; 4786 4787 qup_spi21_cs: qup-spi21-cs-state { 4788 pins = "gpio87"; 4789 function = "qup2_se5"; 4790 drive-strength = <6>; 4791 bias-disable; 4792 }; 4793 4794 qup_spi21_data_clk: qup-spi21-data-clk-state { 4795 /* MISO, MOSI, CLK */ 4796 pins = "gpio84", "gpio85", "gpio86"; 4797 function = "qup2_se5"; 4798 drive-strength = <6>; 4799 bias-disable; 4800 }; 4801 4802 qup_spi22_cs: qup-spi22-cs-state { 4803 pins = "gpio91"; 4804 function = "qup2_se6"; 4805 drive-strength = <6>; 4806 bias-disable; 4807 }; 4808 4809 qup_spi22_data_clk: qup-spi22-data-clk-state { 4810 /* MISO, MOSI, CLK */ 4811 pins = "gpio88", "gpio89", "gpio90"; 4812 function = "qup2_se6"; 4813 drive-strength = <6>; 4814 bias-disable; 4815 }; 4816 4817 qup_spi23_cs: qup-spi23-cs-state { 4818 pins = "gpio85"; 4819 function = "qup2_se7"; 4820 drive-strength = <6>; 4821 bias-disable; 4822 }; 4823 4824 qup_spi23_data_clk: qup-spi23-data-clk-state { 4825 /* MISO, MOSI, CLK */ 4826 pins = "gpio86", "gpio87", "gpio84"; 4827 function = "qup2_se7"; 4828 drive-strength = <6>; 4829 bias-disable; 4830 }; 4831 4832 qup_uart21_default: qup-uart21-default-state { 4833 /* TX, RX */ 4834 pins = "gpio86", "gpio87"; 4835 function = "qup2_se5"; 4836 drive-strength = <2>; 4837 bias-disable; 4838 }; 4839 }; 4840 4841 apps_smmu: iommu@15000000 { 4842 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4843 reg = <0 0x15000000 0 0x100000>; 4844 4845 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4846 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4847 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4848 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4849 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4850 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4851 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4852 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4853 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4854 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4855 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4856 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4857 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4858 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4859 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4860 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4861 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4862 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4863 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4864 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4865 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4866 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4867 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4868 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4869 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4870 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4871 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4872 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4873 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4874 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4875 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4876 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4877 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4878 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4879 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4880 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4881 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4882 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4883 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4884 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4885 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4886 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4887 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4888 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4889 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4890 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4891 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4892 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4893 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4894 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4895 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4896 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4897 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4898 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4899 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4900 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4901 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4902 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4903 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4904 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4905 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4906 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4907 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4908 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4909 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4910 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4911 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4912 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4913 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4914 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4915 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4916 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4917 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4918 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4919 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4920 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4921 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4922 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4923 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4924 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4925 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4926 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4927 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4928 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4929 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4930 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4931 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4932 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4933 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4934 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4935 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4936 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4937 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4938 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4939 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4940 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4941 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 4942 4943 #iommu-cells = <2>; 4944 #global-interrupts = <1>; 4945 }; 4946 4947 intc: interrupt-controller@17000000 { 4948 compatible = "arm,gic-v3"; 4949 reg = <0 0x17000000 0 0x10000>, /* GICD */ 4950 <0 0x17080000 0 0x480000>; /* GICR * 12 */ 4951 4952 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4953 4954 #interrupt-cells = <3>; 4955 interrupt-controller; 4956 4957 #redistributor-regions = <1>; 4958 redistributor-stride = <0x0 0x40000>; 4959 4960 #address-cells = <2>; 4961 #size-cells = <2>; 4962 ranges; 4963 4964 gic_its: msi-controller@17040000 { 4965 compatible = "arm,gic-v3-its"; 4966 reg = <0 0x17040000 0 0x40000>; 4967 4968 msi-controller; 4969 #msi-cells = <1>; 4970 4971 status = "disabled"; 4972 }; 4973 }; 4974 4975 apps_rsc: rsc@17500000 { 4976 compatible = "qcom,rpmh-rsc"; 4977 reg = <0 0x17500000 0 0x10000>, 4978 <0 0x17510000 0 0x10000>, 4979 <0 0x17520000 0 0x10000>; 4980 reg-names = "drv-0", "drv-1", "drv-2"; 4981 4982 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4983 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4984 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4985 qcom,tcs-offset = <0xd00>; 4986 qcom,drv-id = <2>; 4987 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4988 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4989 4990 label = "apps_rsc"; 4991 power-domains = <&SYSTEM_PD>; 4992 4993 apps_bcm_voter: bcm-voter { 4994 compatible = "qcom,bcm-voter"; 4995 }; 4996 4997 rpmhcc: clock-controller { 4998 compatible = "qcom,x1e80100-rpmh-clk"; 4999 5000 clocks = <&xo_board>; 5001 clock-names = "xo"; 5002 5003 #clock-cells = <1>; 5004 }; 5005 5006 rpmhpd: power-controller { 5007 compatible = "qcom,x1e80100-rpmhpd"; 5008 5009 operating-points-v2 = <&rpmhpd_opp_table>; 5010 5011 #power-domain-cells = <1>; 5012 5013 rpmhpd_opp_table: opp-table { 5014 compatible = "operating-points-v2"; 5015 5016 rpmhpd_opp_ret: opp-16 { 5017 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5018 }; 5019 5020 rpmhpd_opp_min_svs: opp-48 { 5021 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5022 }; 5023 5024 rpmhpd_opp_low_svs_d2: opp-52 { 5025 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5026 }; 5027 5028 rpmhpd_opp_low_svs_d1: opp-56 { 5029 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5030 }; 5031 5032 rpmhpd_opp_low_svs_d0: opp-60 { 5033 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5034 }; 5035 5036 rpmhpd_opp_low_svs: opp-64 { 5037 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5038 }; 5039 5040 rpmhpd_opp_low_svs_l1: opp-80 { 5041 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5042 }; 5043 5044 rpmhpd_opp_svs: opp-128 { 5045 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5046 }; 5047 5048 rpmhpd_opp_svs_l0: opp-144 { 5049 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5050 }; 5051 5052 rpmhpd_opp_svs_l1: opp-192 { 5053 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5054 }; 5055 5056 rpmhpd_opp_nom: opp-256 { 5057 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5058 }; 5059 5060 rpmhpd_opp_nom_l1: opp-320 { 5061 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5062 }; 5063 5064 rpmhpd_opp_nom_l2: opp-336 { 5065 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5066 }; 5067 5068 rpmhpd_opp_turbo: opp-384 { 5069 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5070 }; 5071 5072 rpmhpd_opp_turbo_l1: opp-416 { 5073 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5074 }; 5075 }; 5076 }; 5077 }; 5078 5079 timer@17800000 { 5080 compatible = "arm,armv7-timer-mem"; 5081 reg = <0 0x17800000 0 0x1000>; 5082 5083 #address-cells = <2>; 5084 #size-cells = <1>; 5085 ranges = <0 0 0 0 0x20000000>; 5086 5087 frame@17801000 { 5088 reg = <0 0x17801000 0x1000>, 5089 <0 0x17802000 0x1000>; 5090 5091 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5093 5094 frame-number = <0>; 5095 }; 5096 5097 frame@17803000 { 5098 reg = <0 0x17803000 0x1000>; 5099 5100 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5101 5102 frame-number = <1>; 5103 5104 status = "disabled"; 5105 }; 5106 5107 frame@17805000 { 5108 reg = <0 0x17805000 0x1000>; 5109 5110 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5111 5112 frame-number = <2>; 5113 5114 status = "disabled"; 5115 }; 5116 5117 frame@17807000 { 5118 reg = <0 0x17807000 0x1000>; 5119 5120 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5121 5122 frame-number = <3>; 5123 5124 status = "disabled"; 5125 }; 5126 5127 frame@17809000 { 5128 reg = <0 0x17809000 0x1000>; 5129 5130 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5131 5132 frame-number = <4>; 5133 5134 status = "disabled"; 5135 }; 5136 5137 frame@1780b000 { 5138 reg = <0 0x1780b000 0x1000>; 5139 5140 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5141 5142 frame-number = <5>; 5143 5144 status = "disabled"; 5145 }; 5146 5147 frame@1780d000 { 5148 reg = <0 0x1780d000 0x1000>; 5149 5150 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5151 5152 frame-number = <6>; 5153 5154 status = "disabled"; 5155 }; 5156 }; 5157 5158 system-cache-controller@25000000 { 5159 compatible = "qcom,x1e80100-llcc"; 5160 reg = <0 0x25000000 0 0x200000>, 5161 <0 0x25200000 0 0x200000>, 5162 <0 0x25400000 0 0x200000>, 5163 <0 0x25600000 0 0x200000>, 5164 <0 0x25800000 0 0x200000>, 5165 <0 0x25a00000 0 0x200000>, 5166 <0 0x25c00000 0 0x200000>, 5167 <0 0x25e00000 0 0x200000>, 5168 <0 0x26000000 0 0x200000>; 5169 reg-names = "llcc0_base", 5170 "llcc1_base", 5171 "llcc2_base", 5172 "llcc3_base", 5173 "llcc4_base", 5174 "llcc5_base", 5175 "llcc6_base", 5176 "llcc7_base", 5177 "llcc_broadcast_base"; 5178 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 5179 }; 5180 5181 remoteproc_adsp: remoteproc@30000000 { 5182 compatible = "qcom,x1e80100-adsp-pas"; 5183 reg = <0 0x30000000 0 0x100>; 5184 5185 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 5186 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5187 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5188 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5189 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5190 interrupt-names = "wdog", 5191 "fatal", 5192 "ready", 5193 "handover", 5194 "stop-ack"; 5195 5196 clocks = <&rpmhcc RPMH_CXO_CLK>; 5197 clock-names = "xo"; 5198 5199 power-domains = <&rpmhpd RPMHPD_LCX>, 5200 <&rpmhpd RPMHPD_LMX>; 5201 power-domain-names = "lcx", 5202 "lmx"; 5203 5204 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 5205 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5206 5207 memory-region = <&adspslpi_mem>, 5208 <&q6_adsp_dtb_mem>; 5209 5210 qcom,qmp = <&aoss_qmp>; 5211 5212 qcom,smem-states = <&smp2p_adsp_out 0>; 5213 qcom,smem-state-names = "stop"; 5214 5215 status = "disabled"; 5216 5217 glink-edge { 5218 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5219 IPCC_MPROC_SIGNAL_GLINK_QMP 5220 IRQ_TYPE_EDGE_RISING>; 5221 mboxes = <&ipcc IPCC_CLIENT_LPASS 5222 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5223 5224 label = "lpass"; 5225 qcom,remote-pid = <2>; 5226 5227 gpr { 5228 compatible = "qcom,gpr"; 5229 qcom,glink-channels = "adsp_apps"; 5230 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 5231 qcom,intents = <512 20>; 5232 #address-cells = <1>; 5233 #size-cells = <0>; 5234 5235 q6apm: service@1 { 5236 compatible = "qcom,q6apm"; 5237 reg = <GPR_APM_MODULE_IID>; 5238 #sound-dai-cells = <0>; 5239 qcom,protection-domain = "avs/audio", 5240 "msm/adsp/audio_pd"; 5241 5242 q6apmbedai: bedais { 5243 compatible = "qcom,q6apm-lpass-dais"; 5244 #sound-dai-cells = <1>; 5245 }; 5246 5247 q6apmdai: dais { 5248 compatible = "qcom,q6apm-dais"; 5249 iommus = <&apps_smmu 0x1001 0x80>, 5250 <&apps_smmu 0x1061 0x0>; 5251 }; 5252 }; 5253 5254 q6prm: service@2 { 5255 compatible = "qcom,q6prm"; 5256 reg = <GPR_PRM_MODULE_IID>; 5257 qcom,protection-domain = "avs/audio", 5258 "msm/adsp/audio_pd"; 5259 5260 q6prmcc: clock-controller { 5261 compatible = "qcom,q6prm-lpass-clocks"; 5262 #clock-cells = <2>; 5263 }; 5264 }; 5265 }; 5266 }; 5267 }; 5268 5269 remoteproc_cdsp: remoteproc@32300000 { 5270 compatible = "qcom,x1e80100-cdsp-pas"; 5271 reg = <0 0x32300000 0 0x1400000>; 5272 5273 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5274 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 5275 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 5276 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 5277 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 5278 interrupt-names = "wdog", 5279 "fatal", 5280 "ready", 5281 "handover", 5282 "stop-ack"; 5283 5284 clocks = <&rpmhcc RPMH_CXO_CLK>; 5285 clock-names = "xo"; 5286 5287 power-domains = <&rpmhpd RPMHPD_CX>, 5288 <&rpmhpd RPMHPD_MXC>, 5289 <&rpmhpd RPMHPD_NSP>; 5290 power-domain-names = "cx", 5291 "mxc", 5292 "nsp"; 5293 5294 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 5295 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5296 5297 memory-region = <&cdsp_mem>, 5298 <&q6_cdsp_dtb_mem>; 5299 5300 qcom,qmp = <&aoss_qmp>; 5301 5302 qcom,smem-states = <&smp2p_cdsp_out 0>; 5303 qcom,smem-state-names = "stop"; 5304 5305 status = "disabled"; 5306 5307 glink-edge { 5308 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5309 IPCC_MPROC_SIGNAL_GLINK_QMP 5310 IRQ_TYPE_EDGE_RISING>; 5311 mboxes = <&ipcc IPCC_CLIENT_CDSP 5312 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5313 5314 label = "cdsp"; 5315 qcom,remote-pid = <5>; 5316 }; 5317 }; 5318 }; 5319 5320 timer { 5321 compatible = "arm,armv8-timer"; 5322 5323 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5324 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5325 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5326 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 5327 }; 5328}; 5329