1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 8#include <dt-bindings/clock/qcom,sm8450-videocc.h> 9#include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 10#include <dt-bindings/clock/qcom,x1e80100-gcc.h> 11#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> 12#include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 24#include <dt-bindings/thermal/thermal.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 chosen { }; 33 34 clocks { 35 xo_board: xo-board { 36 compatible = "fixed-clock"; 37 clock-frequency = <76800000>; 38 #clock-cells = <0>; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 clock-frequency = <32764>; 44 #clock-cells = <0>; 45 }; 46 47 bi_tcxo_div2: bi-tcxo-div2-clk { 48 compatible = "fixed-factor-clock"; 49 #clock-cells = <0>; 50 51 clocks = <&rpmhcc RPMH_CXO_CLK>; 52 clock-mult = <1>; 53 clock-div = <2>; 54 }; 55 56 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 57 compatible = "fixed-factor-clock"; 58 #clock-cells = <0>; 59 60 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 61 clock-mult = <1>; 62 clock-div = <2>; 63 }; 64 }; 65 66 cpus { 67 #address-cells = <2>; 68 #size-cells = <0>; 69 70 cpu0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "qcom,oryon"; 73 reg = <0x0 0x0>; 74 enable-method = "psci"; 75 next-level-cache = <&l2_0>; 76 power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; 77 power-domain-names = "psci", "perf"; 78 cpu-idle-states = <&cluster_c4>; 79 80 l2_0: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 }; 85 }; 86 87 cpu1: cpu@100 { 88 device_type = "cpu"; 89 compatible = "qcom,oryon"; 90 reg = <0x0 0x100>; 91 enable-method = "psci"; 92 next-level-cache = <&l2_0>; 93 power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; 94 power-domain-names = "psci", "perf"; 95 cpu-idle-states = <&cluster_c4>; 96 }; 97 98 cpu2: cpu@200 { 99 device_type = "cpu"; 100 compatible = "qcom,oryon"; 101 reg = <0x0 0x200>; 102 enable-method = "psci"; 103 next-level-cache = <&l2_0>; 104 power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; 105 power-domain-names = "psci", "perf"; 106 cpu-idle-states = <&cluster_c4>; 107 }; 108 109 cpu3: cpu@300 { 110 device_type = "cpu"; 111 compatible = "qcom,oryon"; 112 reg = <0x0 0x300>; 113 enable-method = "psci"; 114 next-level-cache = <&l2_0>; 115 power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; 116 power-domain-names = "psci", "perf"; 117 cpu-idle-states = <&cluster_c4>; 118 }; 119 120 cpu4: cpu@10000 { 121 device_type = "cpu"; 122 compatible = "qcom,oryon"; 123 reg = <0x0 0x10000>; 124 enable-method = "psci"; 125 next-level-cache = <&l2_1>; 126 power-domains = <&cpu_pd4>, <&scmi_dvfs 1>; 127 power-domain-names = "psci", "perf"; 128 cpu-idle-states = <&cluster_c4>; 129 130 l2_1: l2-cache { 131 compatible = "cache"; 132 cache-level = <2>; 133 cache-unified; 134 }; 135 }; 136 137 cpu5: cpu@10100 { 138 device_type = "cpu"; 139 compatible = "qcom,oryon"; 140 reg = <0x0 0x10100>; 141 enable-method = "psci"; 142 next-level-cache = <&l2_1>; 143 power-domains = <&cpu_pd5>, <&scmi_dvfs 1>; 144 power-domain-names = "psci", "perf"; 145 cpu-idle-states = <&cluster_c4>; 146 }; 147 148 cpu6: cpu@10200 { 149 device_type = "cpu"; 150 compatible = "qcom,oryon"; 151 reg = <0x0 0x10200>; 152 enable-method = "psci"; 153 next-level-cache = <&l2_1>; 154 power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; 155 power-domain-names = "psci", "perf"; 156 cpu-idle-states = <&cluster_c4>; 157 }; 158 159 cpu7: cpu@10300 { 160 device_type = "cpu"; 161 compatible = "qcom,oryon"; 162 reg = <0x0 0x10300>; 163 enable-method = "psci"; 164 next-level-cache = <&l2_1>; 165 power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; 166 power-domain-names = "psci", "perf"; 167 cpu-idle-states = <&cluster_c4>; 168 }; 169 170 cpu8: cpu@20000 { 171 device_type = "cpu"; 172 compatible = "qcom,oryon"; 173 reg = <0x0 0x20000>; 174 enable-method = "psci"; 175 next-level-cache = <&l2_2>; 176 power-domains = <&cpu_pd8>, <&scmi_dvfs 2>; 177 power-domain-names = "psci", "perf"; 178 cpu-idle-states = <&cluster_c4>; 179 180 l2_2: l2-cache { 181 compatible = "cache"; 182 cache-level = <2>; 183 cache-unified; 184 }; 185 }; 186 187 cpu9: cpu@20100 { 188 device_type = "cpu"; 189 compatible = "qcom,oryon"; 190 reg = <0x0 0x20100>; 191 enable-method = "psci"; 192 next-level-cache = <&l2_2>; 193 power-domains = <&cpu_pd9>, <&scmi_dvfs 2>; 194 power-domain-names = "psci", "perf"; 195 cpu-idle-states = <&cluster_c4>; 196 }; 197 198 cpu10: cpu@20200 { 199 device_type = "cpu"; 200 compatible = "qcom,oryon"; 201 reg = <0x0 0x20200>; 202 enable-method = "psci"; 203 next-level-cache = <&l2_2>; 204 power-domains = <&cpu_pd10>, <&scmi_dvfs 2>; 205 power-domain-names = "psci", "perf"; 206 cpu-idle-states = <&cluster_c4>; 207 }; 208 209 cpu11: cpu@20300 { 210 device_type = "cpu"; 211 compatible = "qcom,oryon"; 212 reg = <0x0 0x20300>; 213 enable-method = "psci"; 214 next-level-cache = <&l2_2>; 215 power-domains = <&cpu_pd11>, <&scmi_dvfs 2>; 216 power-domain-names = "psci", "perf"; 217 cpu-idle-states = <&cluster_c4>; 218 }; 219 220 cpu-map { 221 cluster0 { 222 core0 { 223 cpu = <&cpu0>; 224 }; 225 226 core1 { 227 cpu = <&cpu1>; 228 }; 229 230 core2 { 231 cpu = <&cpu2>; 232 }; 233 234 core3 { 235 cpu = <&cpu3>; 236 }; 237 }; 238 239 cluster1 { 240 core0 { 241 cpu = <&cpu4>; 242 }; 243 244 core1 { 245 cpu = <&cpu5>; 246 }; 247 248 core2 { 249 cpu = <&cpu6>; 250 }; 251 252 core3 { 253 cpu = <&cpu7>; 254 }; 255 }; 256 257 cpu_map_cluster2: cluster2 { 258 core0 { 259 cpu = <&cpu8>; 260 }; 261 262 core1 { 263 cpu = <&cpu9>; 264 }; 265 266 core2 { 267 cpu = <&cpu10>; 268 }; 269 270 core3 { 271 cpu = <&cpu11>; 272 }; 273 }; 274 }; 275 276 idle-states { 277 entry-method = "psci"; 278 279 cluster_c4: cpu-sleep-0 { 280 compatible = "arm,idle-state"; 281 idle-state-name = "ret"; 282 arm,psci-suspend-param = <0x00000004>; 283 entry-latency-us = <180>; 284 exit-latency-us = <500>; 285 min-residency-us = <600>; 286 }; 287 }; 288 289 domain-idle-states { 290 cluster_cl4: cluster-sleep-0 { 291 compatible = "domain-idle-state"; 292 arm,psci-suspend-param = <0x01000044>; 293 entry-latency-us = <350>; 294 exit-latency-us = <500>; 295 min-residency-us = <2500>; 296 }; 297 298 cluster_cl5: cluster-sleep-1 { 299 compatible = "domain-idle-state"; 300 arm,psci-suspend-param = <0x01000054>; 301 entry-latency-us = <2200>; 302 exit-latency-us = <4000>; 303 min-residency-us = <7000>; 304 }; 305 }; 306 }; 307 308 dummy-sink { 309 compatible = "arm,coresight-dummy-sink"; 310 311 in-ports { 312 port { 313 eud_in: endpoint { 314 remote-endpoint = <&swao_rep_out1>; 315 }; 316 }; 317 }; 318 }; 319 320 firmware { 321 scm: scm { 322 compatible = "qcom,scm-x1e80100", "qcom,scm"; 323 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 324 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 325 qcom,dload-mode = <&tcsr 0x19000>; 326 }; 327 328 scmi { 329 compatible = "arm,scmi"; 330 mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>; 331 mbox-names = "tx", "rx"; 332 shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; 333 334 #address-cells = <1>; 335 #size-cells = <0>; 336 337 scmi_dvfs: protocol@13 { 338 reg = <0x13>; 339 #power-domain-cells = <1>; 340 }; 341 }; 342 }; 343 344 clk_virt: interconnect-0 { 345 compatible = "qcom,x1e80100-clk-virt"; 346 #interconnect-cells = <2>; 347 qcom,bcm-voters = <&apps_bcm_voter>; 348 }; 349 350 mc_virt: interconnect-1 { 351 compatible = "qcom,x1e80100-mc-virt"; 352 #interconnect-cells = <2>; 353 qcom,bcm-voters = <&apps_bcm_voter>; 354 }; 355 356 memory@80000000 { 357 device_type = "memory"; 358 /* We expect the bootloader to fill in the size */ 359 reg = <0 0x80000000 0 0>; 360 }; 361 362 pmu { 363 compatible = "arm,armv8-pmuv3"; 364 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 365 }; 366 367 psci { 368 compatible = "arm,psci-1.0"; 369 method = "smc"; 370 371 cpu_pd0: power-domain-cpu0 { 372 #power-domain-cells = <0>; 373 power-domains = <&cluster_pd0>; 374 }; 375 376 cpu_pd1: power-domain-cpu1 { 377 #power-domain-cells = <0>; 378 power-domains = <&cluster_pd0>; 379 }; 380 381 cpu_pd2: power-domain-cpu2 { 382 #power-domain-cells = <0>; 383 power-domains = <&cluster_pd0>; 384 }; 385 386 cpu_pd3: power-domain-cpu3 { 387 #power-domain-cells = <0>; 388 power-domains = <&cluster_pd0>; 389 }; 390 391 cpu_pd4: power-domain-cpu4 { 392 #power-domain-cells = <0>; 393 power-domains = <&cluster_pd1>; 394 }; 395 396 cpu_pd5: power-domain-cpu5 { 397 #power-domain-cells = <0>; 398 power-domains = <&cluster_pd1>; 399 }; 400 401 cpu_pd6: power-domain-cpu6 { 402 #power-domain-cells = <0>; 403 power-domains = <&cluster_pd1>; 404 }; 405 406 cpu_pd7: power-domain-cpu7 { 407 #power-domain-cells = <0>; 408 power-domains = <&cluster_pd1>; 409 }; 410 411 cpu_pd8: power-domain-cpu8 { 412 #power-domain-cells = <0>; 413 power-domains = <&cluster_pd2>; 414 }; 415 416 cpu_pd9: power-domain-cpu9 { 417 #power-domain-cells = <0>; 418 power-domains = <&cluster_pd2>; 419 }; 420 421 cpu_pd10: power-domain-cpu10 { 422 #power-domain-cells = <0>; 423 power-domains = <&cluster_pd2>; 424 }; 425 426 cpu_pd11: power-domain-cpu11 { 427 #power-domain-cells = <0>; 428 power-domains = <&cluster_pd2>; 429 }; 430 431 cluster_pd0: power-domain-cpu-cluster0 { 432 #power-domain-cells = <0>; 433 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 434 power-domains = <&system_pd>; 435 }; 436 437 cluster_pd1: power-domain-cpu-cluster1 { 438 #power-domain-cells = <0>; 439 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 440 power-domains = <&system_pd>; 441 }; 442 443 cluster_pd2: power-domain-cpu-cluster2 { 444 #power-domain-cells = <0>; 445 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 446 power-domains = <&system_pd>; 447 }; 448 449 system_pd: power-domain-system { 450 #power-domain-cells = <0>; 451 /* TODO: system-wide idle states */ 452 }; 453 }; 454 455 reserved-memory { 456 #address-cells = <2>; 457 #size-cells = <2>; 458 ranges; 459 460 gunyah_hyp_mem: gunyah-hyp@80000000 { 461 reg = <0x0 0x80000000 0x0 0x800000>; 462 no-map; 463 }; 464 465 hyp_elf_package_mem: hyp-elf-package@80800000 { 466 reg = <0x0 0x80800000 0x0 0x200000>; 467 no-map; 468 }; 469 470 ncc_mem: ncc@80a00000 { 471 reg = <0x0 0x80a00000 0x0 0x400000>; 472 no-map; 473 }; 474 475 cpucp_log_mem: cpucp-log@80e00000 { 476 reg = <0x0 0x80e00000 0x0 0x40000>; 477 no-map; 478 }; 479 480 cpucp_mem: cpucp@80e40000 { 481 reg = <0x0 0x80e40000 0x0 0x540000>; 482 no-map; 483 }; 484 485 reserved-region@81380000 { 486 reg = <0x0 0x81380000 0x0 0x80000>; 487 no-map; 488 }; 489 490 tags_mem: tags-region@81400000 { 491 reg = <0x0 0x81400000 0x0 0x1a0000>; 492 no-map; 493 }; 494 495 xbl_dtlog_mem: xbl-dtlog@81a00000 { 496 reg = <0x0 0x81a00000 0x0 0x40000>; 497 no-map; 498 }; 499 500 xbl_ramdump_mem: xbl-ramdump@81a40000 { 501 reg = <0x0 0x81a40000 0x0 0x1c0000>; 502 no-map; 503 }; 504 505 aop_image_mem: aop-image@81c00000 { 506 reg = <0x0 0x81c00000 0x0 0x60000>; 507 no-map; 508 }; 509 510 aop_cmd_db_mem: aop-cmd-db@81c60000 { 511 compatible = "qcom,cmd-db"; 512 reg = <0x0 0x81c60000 0x0 0x20000>; 513 no-map; 514 }; 515 516 aop_config_mem: aop-config@81c80000 { 517 reg = <0x0 0x81c80000 0x0 0x20000>; 518 no-map; 519 }; 520 521 tme_crash_dump_mem: tme-crash-dump@81ca0000 { 522 reg = <0x0 0x81ca0000 0x0 0x40000>; 523 no-map; 524 }; 525 526 tme_log_mem: tme-log@81ce0000 { 527 reg = <0x0 0x81ce0000 0x0 0x4000>; 528 no-map; 529 }; 530 531 uefi_log_mem: uefi-log@81ce4000 { 532 reg = <0x0 0x81ce4000 0x0 0x10000>; 533 no-map; 534 }; 535 536 secdata_apss_mem: secdata-apss@81cff000 { 537 reg = <0x0 0x81cff000 0x0 0x1000>; 538 no-map; 539 }; 540 541 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 542 reg = <0x0 0x81e00000 0x0 0x100000>; 543 no-map; 544 }; 545 546 gpu_prr_mem: gpu-prr@81f00000 { 547 reg = <0x0 0x81f00000 0x0 0x10000>; 548 no-map; 549 }; 550 551 tpm_control_mem: tpm-control@81f10000 { 552 reg = <0x0 0x81f10000 0x0 0x10000>; 553 no-map; 554 }; 555 556 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 { 557 reg = <0x0 0x81f20000 0x0 0x10000>; 558 no-map; 559 }; 560 561 pld_pep_mem: pld-pep@81f30000 { 562 reg = <0x0 0x81f30000 0x0 0x6000>; 563 no-map; 564 }; 565 566 pld_gmu_mem: pld-gmu@81f36000 { 567 reg = <0x0 0x81f36000 0x0 0x1000>; 568 no-map; 569 }; 570 571 pld_pdp_mem: pld-pdp@81f37000 { 572 reg = <0x0 0x81f37000 0x0 0x1000>; 573 no-map; 574 }; 575 576 tz_stat_mem: tz-stat@82700000 { 577 reg = <0x0 0x82700000 0x0 0x100000>; 578 no-map; 579 }; 580 581 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 { 582 reg = <0x0 0x82800000 0x0 0xc00000>; 583 no-map; 584 }; 585 586 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 { 587 reg = <0x0 0x84b00000 0x0 0x800000>; 588 no-map; 589 }; 590 591 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 { 592 reg = <0x0 0x85300000 0x0 0x80000>; 593 no-map; 594 }; 595 596 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 { 597 reg = <0x0 0x866c0000 0x0 0x40000>; 598 no-map; 599 }; 600 601 spss_region_mem: spss-region@86700000 { 602 reg = <0x0 0x86700000 0x0 0x400000>; 603 no-map; 604 }; 605 606 adsp_boot_mem: adsp-boot@86b00000 { 607 reg = <0x0 0x86b00000 0x0 0xc00000>; 608 no-map; 609 }; 610 611 video_mem: video@87700000 { 612 reg = <0x0 0x87700000 0x0 0x700000>; 613 no-map; 614 }; 615 616 adspslpi_mem: adspslpi@87e00000 { 617 reg = <0x0 0x87e00000 0x0 0x3a00000>; 618 no-map; 619 }; 620 621 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 { 622 reg = <0x0 0x8b800000 0x0 0x80000>; 623 no-map; 624 }; 625 626 cdsp_mem: cdsp@8b900000 { 627 reg = <0x0 0x8b900000 0x0 0x2000000>; 628 no-map; 629 }; 630 631 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 { 632 reg = <0x0 0x8d900000 0x0 0x80000>; 633 no-map; 634 }; 635 636 gpu_microcode_mem: gpu-microcode@8d9fe000 { 637 reg = <0x0 0x8d9fe000 0x0 0x2000>; 638 no-map; 639 }; 640 641 cvp_mem: cvp@8da00000 { 642 reg = <0x0 0x8da00000 0x0 0x700000>; 643 no-map; 644 }; 645 646 camera_mem: camera@8e100000 { 647 reg = <0x0 0x8e100000 0x0 0x800000>; 648 no-map; 649 }; 650 651 av1_encoder_mem: av1-encoder@8e900000 { 652 reg = <0x0 0x8e900000 0x0 0x700000>; 653 no-map; 654 }; 655 656 reserved-region@8f000000 { 657 reg = <0x0 0x8f000000 0x0 0xa00000>; 658 no-map; 659 }; 660 661 wpss_mem: wpss@8fa00000 { 662 reg = <0x0 0x8fa00000 0x0 0x1900000>; 663 no-map; 664 }; 665 666 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 { 667 reg = <0x0 0x91300000 0x0 0x80000>; 668 no-map; 669 }; 670 671 xbl_sc_mem: xbl-sc@d8000000 { 672 reg = <0x0 0xd8000000 0x0 0x40000>; 673 no-map; 674 }; 675 676 reserved-region@d8040000 { 677 reg = <0x0 0xd8040000 0x0 0xa0000>; 678 no-map; 679 }; 680 681 qtee_mem: qtee@d80e0000 { 682 reg = <0x0 0xd80e0000 0x0 0x520000>; 683 no-map; 684 }; 685 686 ta_mem: ta@d8600000 { 687 reg = <0x0 0xd8600000 0x0 0x8a00000>; 688 no-map; 689 }; 690 691 tags_mem1: tags@e1000000 { 692 reg = <0x0 0xe1000000 0x0 0x26a0000>; 693 no-map; 694 }; 695 696 llcc_lpi_mem: llcc-lpi@ff800000 { 697 reg = <0x0 0xff800000 0x0 0x600000>; 698 no-map; 699 }; 700 701 smem_mem: smem@ffe00000 { 702 compatible = "qcom,smem"; 703 reg = <0x0 0xffe00000 0x0 0x200000>; 704 hwlocks = <&tcsr_mutex 3>; 705 no-map; 706 }; 707 }; 708 709 qup_opp_table_100mhz: opp-table-qup100mhz { 710 compatible = "operating-points-v2"; 711 712 opp-75000000 { 713 opp-hz = /bits/ 64 <75000000>; 714 required-opps = <&rpmhpd_opp_low_svs>; 715 }; 716 717 opp-100000000 { 718 opp-hz = /bits/ 64 <100000000>; 719 required-opps = <&rpmhpd_opp_svs>; 720 }; 721 }; 722 723 qup_opp_table_120mhz: opp-table-qup120mhz { 724 compatible = "operating-points-v2"; 725 726 opp-75000000 { 727 opp-hz = /bits/ 64 <75000000>; 728 required-opps = <&rpmhpd_opp_low_svs>; 729 }; 730 731 opp-120000000 { 732 opp-hz = /bits/ 64 <120000000>; 733 required-opps = <&rpmhpd_opp_svs>; 734 }; 735 }; 736 737 smp2p-adsp { 738 compatible = "qcom,smp2p"; 739 740 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 741 IPCC_MPROC_SIGNAL_SMP2P 742 IRQ_TYPE_EDGE_RISING>; 743 744 mboxes = <&ipcc IPCC_CLIENT_LPASS 745 IPCC_MPROC_SIGNAL_SMP2P>; 746 747 qcom,smem = <443>, <429>; 748 qcom,local-pid = <0>; 749 qcom,remote-pid = <2>; 750 751 smp2p_adsp_out: master-kernel { 752 qcom,entry-name = "master-kernel"; 753 #qcom,smem-state-cells = <1>; 754 }; 755 756 smp2p_adsp_in: slave-kernel { 757 qcom,entry-name = "slave-kernel"; 758 interrupt-controller; 759 #interrupt-cells = <2>; 760 }; 761 }; 762 763 smp2p-cdsp { 764 compatible = "qcom,smp2p"; 765 766 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 767 IPCC_MPROC_SIGNAL_SMP2P 768 IRQ_TYPE_EDGE_RISING>; 769 770 mboxes = <&ipcc IPCC_CLIENT_CDSP 771 IPCC_MPROC_SIGNAL_SMP2P>; 772 773 qcom,smem = <94>, <432>; 774 qcom,local-pid = <0>; 775 qcom,remote-pid = <5>; 776 777 smp2p_cdsp_out: master-kernel { 778 qcom,entry-name = "master-kernel"; 779 #qcom,smem-state-cells = <1>; 780 }; 781 782 smp2p_cdsp_in: slave-kernel { 783 qcom,entry-name = "slave-kernel"; 784 interrupt-controller; 785 #interrupt-cells = <2>; 786 }; 787 }; 788 789 soc: soc@0 { 790 compatible = "simple-bus"; 791 792 #address-cells = <2>; 793 #size-cells = <2>; 794 dma-ranges = <0 0 0 0 0x10 0>; 795 ranges = <0 0 0 0 0x10 0>; 796 797 gcc: clock-controller@100000 { 798 compatible = "qcom,x1e80100-gcc"; 799 reg = <0 0x00100000 0 0x200000>; 800 801 clocks = <&bi_tcxo_div2>, 802 <&sleep_clk>, 803 <&pcie3_phy>, 804 <&pcie4_phy>, 805 <&pcie5_phy>, 806 <&pcie6a_phy>, 807 <0>, 808 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 809 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 810 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 811 812 power-domains = <&rpmhpd RPMHPD_CX>; 813 #clock-cells = <1>; 814 #reset-cells = <1>; 815 #power-domain-cells = <1>; 816 }; 817 818 ipcc: mailbox@408000 { 819 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; 820 reg = <0 0x00408000 0 0x1000>; 821 822 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 823 interrupt-controller; 824 #interrupt-cells = <3>; 825 826 #mbox-cells = <2>; 827 }; 828 829 gpi_dma2: dma-controller@800000 { 830 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 831 reg = <0 0x00800000 0 0x60000>; 832 833 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 845 846 dma-channels = <12>; 847 dma-channel-mask = <0x3e>; 848 #dma-cells = <3>; 849 850 iommus = <&apps_smmu 0x436 0x0>; 851 852 status = "disabled"; 853 }; 854 855 qupv3_2: geniqup@8c0000 { 856 compatible = "qcom,geni-se-qup"; 857 reg = <0 0x008c0000 0 0x2000>; 858 859 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 860 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 861 clock-names = "m-ahb", 862 "s-ahb"; 863 864 iommus = <&apps_smmu 0x423 0x0>; 865 866 #address-cells = <2>; 867 #size-cells = <2>; 868 ranges; 869 870 status = "disabled"; 871 872 i2c16: i2c@880000 { 873 compatible = "qcom,geni-i2c"; 874 reg = <0 0x00880000 0 0x4000>; 875 876 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 877 878 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 879 clock-names = "se"; 880 881 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 882 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 883 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 884 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 885 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 886 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 887 interconnect-names = "qup-core", 888 "qup-config", 889 "qup-memory"; 890 891 power-domains = <&rpmhpd RPMHPD_CX>; 892 required-opps = <&rpmhpd_opp_low_svs>; 893 894 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 895 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 896 dma-names = "tx", 897 "rx"; 898 899 pinctrl-0 = <&qup_i2c16_data_clk>; 900 pinctrl-names = "default"; 901 902 #address-cells = <1>; 903 #size-cells = <0>; 904 905 status = "disabled"; 906 }; 907 908 spi16: spi@880000 { 909 compatible = "qcom,geni-spi"; 910 reg = <0 0x00880000 0 0x4000>; 911 912 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 913 914 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 915 clock-names = "se"; 916 917 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 918 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 919 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 920 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 921 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 922 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 923 interconnect-names = "qup-core", 924 "qup-config", 925 "qup-memory"; 926 927 power-domains = <&rpmhpd RPMHPD_CX>; 928 operating-points-v2 = <&qup_opp_table_120mhz>; 929 930 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 931 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 932 dma-names = "tx", 933 "rx"; 934 935 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 936 pinctrl-names = "default"; 937 938 #address-cells = <1>; 939 #size-cells = <0>; 940 941 status = "disabled"; 942 }; 943 944 i2c17: i2c@884000 { 945 compatible = "qcom,geni-i2c"; 946 reg = <0 0x00884000 0 0x4000>; 947 948 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 949 950 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 951 clock-names = "se"; 952 953 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 954 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 955 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 956 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 957 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 958 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 959 interconnect-names = "qup-core", 960 "qup-config", 961 "qup-memory"; 962 963 power-domains = <&rpmhpd RPMHPD_CX>; 964 required-opps = <&rpmhpd_opp_low_svs>; 965 966 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 967 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 968 dma-names = "tx", 969 "rx"; 970 971 pinctrl-0 = <&qup_i2c17_data_clk>; 972 pinctrl-names = "default"; 973 974 #address-cells = <1>; 975 #size-cells = <0>; 976 977 status = "disabled"; 978 }; 979 980 spi17: spi@884000 { 981 compatible = "qcom,geni-spi"; 982 reg = <0 0x00884000 0 0x4000>; 983 984 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 985 986 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 987 clock-names = "se"; 988 989 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 990 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 991 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 992 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 993 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 994 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 995 interconnect-names = "qup-core", 996 "qup-config", 997 "qup-memory"; 998 999 power-domains = <&rpmhpd RPMHPD_CX>; 1000 operating-points-v2 = <&qup_opp_table_120mhz>; 1001 1002 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1003 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1004 dma-names = "tx", 1005 "rx"; 1006 1007 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 1008 pinctrl-names = "default"; 1009 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 1013 status = "disabled"; 1014 }; 1015 1016 i2c18: i2c@888000 { 1017 compatible = "qcom,geni-i2c"; 1018 reg = <0 0x00888000 0 0x4000>; 1019 1020 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1021 1022 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1023 clock-names = "se"; 1024 1025 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1026 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1027 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1028 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1029 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1030 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1031 interconnect-names = "qup-core", 1032 "qup-config", 1033 "qup-memory"; 1034 1035 power-domains = <&rpmhpd RPMHPD_CX>; 1036 required-opps = <&rpmhpd_opp_low_svs>; 1037 1038 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1039 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1040 dma-names = "tx", 1041 "rx"; 1042 1043 pinctrl-0 = <&qup_i2c18_data_clk>; 1044 pinctrl-names = "default"; 1045 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 1049 status = "disabled"; 1050 }; 1051 1052 spi18: spi@888000 { 1053 compatible = "qcom,geni-spi"; 1054 reg = <0 0x00888000 0 0x4000>; 1055 1056 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1057 1058 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1059 clock-names = "se"; 1060 1061 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1062 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1063 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1064 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1065 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1066 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1067 interconnect-names = "qup-core", 1068 "qup-config", 1069 "qup-memory"; 1070 1071 power-domains = <&rpmhpd RPMHPD_CX>; 1072 operating-points-v2 = <&qup_opp_table_100mhz>; 1073 1074 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1075 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1076 dma-names = "tx", 1077 "rx"; 1078 1079 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1080 pinctrl-names = "default"; 1081 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 1085 status = "disabled"; 1086 }; 1087 1088 i2c19: i2c@88c000 { 1089 compatible = "qcom,geni-i2c"; 1090 reg = <0 0x0088c000 0 0x4000>; 1091 1092 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1093 1094 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1095 clock-names = "se"; 1096 1097 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1098 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1099 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1100 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1101 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1102 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1103 interconnect-names = "qup-core", 1104 "qup-config", 1105 "qup-memory"; 1106 1107 power-domains = <&rpmhpd RPMHPD_CX>; 1108 required-opps = <&rpmhpd_opp_low_svs>; 1109 1110 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1111 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1112 dma-names = "tx", 1113 "rx"; 1114 1115 pinctrl-0 = <&qup_i2c19_data_clk>; 1116 pinctrl-names = "default"; 1117 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 1121 status = "disabled"; 1122 }; 1123 1124 spi19: spi@88c000 { 1125 compatible = "qcom,geni-spi"; 1126 reg = <0 0x0088c000 0 0x4000>; 1127 1128 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1129 1130 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1131 clock-names = "se"; 1132 1133 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1134 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1135 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1136 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1137 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1138 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1139 interconnect-names = "qup-core", 1140 "qup-config", 1141 "qup-memory"; 1142 1143 power-domains = <&rpmhpd RPMHPD_CX>; 1144 operating-points-v2 = <&qup_opp_table_100mhz>; 1145 1146 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1147 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1148 dma-names = "tx", 1149 "rx"; 1150 1151 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1152 pinctrl-names = "default"; 1153 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 1157 status = "disabled"; 1158 }; 1159 1160 i2c20: i2c@890000 { 1161 compatible = "qcom,geni-i2c"; 1162 reg = <0 0x00890000 0 0x4000>; 1163 1164 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1165 1166 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1167 clock-names = "se"; 1168 1169 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1170 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1171 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1172 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1173 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1174 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1175 interconnect-names = "qup-core", 1176 "qup-config", 1177 "qup-memory"; 1178 1179 power-domains = <&rpmhpd RPMHPD_CX>; 1180 required-opps = <&rpmhpd_opp_low_svs>; 1181 1182 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1183 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1184 dma-names = "tx", 1185 "rx"; 1186 1187 pinctrl-0 = <&qup_i2c20_data_clk>; 1188 pinctrl-names = "default"; 1189 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 1193 status = "disabled"; 1194 }; 1195 1196 spi20: spi@890000 { 1197 compatible = "qcom,geni-spi"; 1198 reg = <0 0x00890000 0 0x4000>; 1199 1200 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1201 1202 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1203 clock-names = "se"; 1204 1205 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1206 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1207 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1208 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1209 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1210 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1211 interconnect-names = "qup-core", 1212 "qup-config", 1213 "qup-memory"; 1214 1215 power-domains = <&rpmhpd RPMHPD_CX>; 1216 operating-points-v2 = <&qup_opp_table_100mhz>; 1217 1218 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1219 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1220 dma-names = "tx", 1221 "rx"; 1222 1223 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1224 pinctrl-names = "default"; 1225 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 1229 status = "disabled"; 1230 }; 1231 1232 i2c21: i2c@894000 { 1233 compatible = "qcom,geni-i2c"; 1234 reg = <0 0x00894000 0 0x4000>; 1235 1236 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1237 1238 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1239 clock-names = "se"; 1240 1241 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1242 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1243 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1244 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1245 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1246 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1247 interconnect-names = "qup-core", 1248 "qup-config", 1249 "qup-memory"; 1250 1251 power-domains = <&rpmhpd RPMHPD_CX>; 1252 required-opps = <&rpmhpd_opp_low_svs>; 1253 1254 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1255 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1256 dma-names = "tx", 1257 "rx"; 1258 1259 pinctrl-0 = <&qup_i2c21_data_clk>; 1260 pinctrl-names = "default"; 1261 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 1265 status = "disabled"; 1266 }; 1267 1268 spi21: spi@894000 { 1269 compatible = "qcom,geni-spi"; 1270 reg = <0 0x00894000 0 0x4000>; 1271 1272 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1273 1274 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1275 clock-names = "se"; 1276 1277 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1278 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1279 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1280 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1281 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1282 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1283 interconnect-names = "qup-core", 1284 "qup-config", 1285 "qup-memory"; 1286 1287 power-domains = <&rpmhpd RPMHPD_CX>; 1288 operating-points-v2 = <&qup_opp_table_100mhz>; 1289 1290 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1291 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1292 dma-names = "tx", 1293 "rx"; 1294 1295 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1296 pinctrl-names = "default"; 1297 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 1301 status = "disabled"; 1302 }; 1303 1304 uart21: serial@894000 { 1305 compatible = "qcom,geni-uart"; 1306 reg = <0 0x00894000 0 0x4000>; 1307 1308 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1309 1310 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1311 clock-names = "se"; 1312 1313 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1314 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1315 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1316 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1317 interconnect-names = "qup-core", 1318 "qup-config"; 1319 1320 power-domains = <&rpmhpd RPMHPD_CX>; 1321 operating-points-v2 = <&qup_opp_table_100mhz>; 1322 1323 pinctrl-0 = <&qup_uart21_default>; 1324 pinctrl-names = "default"; 1325 1326 status = "disabled"; 1327 }; 1328 1329 i2c22: i2c@898000 { 1330 compatible = "qcom,geni-i2c"; 1331 reg = <0 0x00898000 0 0x4000>; 1332 1333 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1334 1335 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1336 clock-names = "se"; 1337 1338 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1339 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1340 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1341 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1342 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1343 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1344 interconnect-names = "qup-core", 1345 "qup-config", 1346 "qup-memory"; 1347 1348 power-domains = <&rpmhpd RPMHPD_CX>; 1349 required-opps = <&rpmhpd_opp_low_svs>; 1350 1351 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1352 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1353 dma-names = "tx", 1354 "rx"; 1355 1356 pinctrl-0 = <&qup_i2c22_data_clk>; 1357 pinctrl-names = "default"; 1358 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 1362 status = "disabled"; 1363 }; 1364 1365 spi22: spi@898000 { 1366 compatible = "qcom,geni-spi"; 1367 reg = <0 0x00898000 0 0x4000>; 1368 1369 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1370 1371 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1372 clock-names = "se"; 1373 1374 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1375 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1376 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1377 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1378 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1379 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1380 interconnect-names = "qup-core", 1381 "qup-config", 1382 "qup-memory"; 1383 1384 power-domains = <&rpmhpd RPMHPD_CX>; 1385 operating-points-v2 = <&qup_opp_table_100mhz>; 1386 1387 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1388 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1389 dma-names = "tx", 1390 "rx"; 1391 1392 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1393 pinctrl-names = "default"; 1394 1395 #address-cells = <1>; 1396 #size-cells = <0>; 1397 1398 status = "disabled"; 1399 }; 1400 1401 i2c23: i2c@89c000 { 1402 compatible = "qcom,geni-i2c"; 1403 reg = <0 0x0089c000 0 0x4000>; 1404 1405 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1406 1407 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1408 clock-names = "se"; 1409 1410 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1411 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1412 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1413 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1414 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1415 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1416 interconnect-names = "qup-core", 1417 "qup-config", 1418 "qup-memory"; 1419 1420 power-domains = <&rpmhpd RPMHPD_CX>; 1421 required-opps = <&rpmhpd_opp_low_svs>; 1422 1423 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1424 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1425 dma-names = "tx", 1426 "rx"; 1427 1428 pinctrl-0 = <&qup_i2c23_data_clk>; 1429 pinctrl-names = "default"; 1430 1431 #address-cells = <1>; 1432 #size-cells = <0>; 1433 1434 status = "disabled"; 1435 }; 1436 1437 spi23: spi@89c000 { 1438 compatible = "qcom,geni-spi"; 1439 reg = <0 0x0089c000 0 0x4000>; 1440 1441 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1442 1443 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1444 clock-names = "se"; 1445 1446 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1447 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1448 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1449 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1450 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1451 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1452 interconnect-names = "qup-core", 1453 "qup-config", 1454 "qup-memory"; 1455 1456 power-domains = <&rpmhpd RPMHPD_CX>; 1457 operating-points-v2 = <&qup_opp_table_100mhz>; 1458 1459 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1460 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1461 dma-names = "tx", 1462 "rx"; 1463 1464 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1465 pinctrl-names = "default"; 1466 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 1470 status = "disabled"; 1471 }; 1472 }; 1473 1474 gpi_dma1: dma-controller@a00000 { 1475 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1476 reg = <0 0x00a00000 0 0x60000>; 1477 1478 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 1490 1491 dma-channels = <12>; 1492 dma-channel-mask = <0x3e>; 1493 #dma-cells = <3>; 1494 1495 iommus = <&apps_smmu 0x136 0x0>; 1496 1497 status = "disabled"; 1498 }; 1499 1500 qupv3_1: geniqup@ac0000 { 1501 compatible = "qcom,geni-se-qup"; 1502 reg = <0 0x00ac0000 0 0x2000>; 1503 1504 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1505 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1506 clock-names = "m-ahb", 1507 "s-ahb"; 1508 1509 iommus = <&apps_smmu 0x123 0x0>; 1510 1511 #address-cells = <2>; 1512 #size-cells = <2>; 1513 ranges; 1514 1515 status = "disabled"; 1516 1517 i2c8: i2c@a80000 { 1518 compatible = "qcom,geni-i2c"; 1519 reg = <0 0x00a80000 0 0x4000>; 1520 1521 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1522 1523 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1524 clock-names = "se"; 1525 1526 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1527 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1528 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1529 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1530 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1531 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1532 interconnect-names = "qup-core", 1533 "qup-config", 1534 "qup-memory"; 1535 1536 power-domains = <&rpmhpd RPMHPD_CX>; 1537 required-opps = <&rpmhpd_opp_low_svs>; 1538 1539 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1540 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1541 dma-names = "tx", 1542 "rx"; 1543 1544 pinctrl-0 = <&qup_i2c8_data_clk>; 1545 pinctrl-names = "default"; 1546 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 1550 status = "disabled"; 1551 }; 1552 1553 spi8: spi@a80000 { 1554 compatible = "qcom,geni-spi"; 1555 reg = <0 0x00a80000 0 0x4000>; 1556 1557 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1558 1559 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1560 clock-names = "se"; 1561 1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1563 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1564 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1565 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1566 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1567 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1568 interconnect-names = "qup-core", 1569 "qup-config", 1570 "qup-memory"; 1571 1572 power-domains = <&rpmhpd RPMHPD_CX>; 1573 operating-points-v2 = <&qup_opp_table_120mhz>; 1574 1575 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1576 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1577 dma-names = "tx", 1578 "rx"; 1579 1580 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1581 pinctrl-names = "default"; 1582 1583 #address-cells = <1>; 1584 #size-cells = <0>; 1585 1586 status = "disabled"; 1587 }; 1588 1589 i2c9: i2c@a84000 { 1590 compatible = "qcom,geni-i2c"; 1591 reg = <0 0x00a84000 0 0x4000>; 1592 1593 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1594 1595 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1596 clock-names = "se"; 1597 1598 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1599 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1600 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1601 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1602 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1603 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1604 interconnect-names = "qup-core", 1605 "qup-config", 1606 "qup-memory"; 1607 1608 power-domains = <&rpmhpd RPMHPD_CX>; 1609 required-opps = <&rpmhpd_opp_low_svs>; 1610 1611 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1612 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1613 dma-names = "tx", 1614 "rx"; 1615 1616 pinctrl-0 = <&qup_i2c9_data_clk>; 1617 pinctrl-names = "default"; 1618 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 1622 status = "disabled"; 1623 }; 1624 1625 spi9: spi@a84000 { 1626 compatible = "qcom,geni-spi"; 1627 reg = <0 0x00a84000 0 0x4000>; 1628 1629 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1630 1631 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1632 clock-names = "se"; 1633 1634 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1635 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1636 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1637 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1638 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1639 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1640 interconnect-names = "qup-core", 1641 "qup-config", 1642 "qup-memory"; 1643 1644 power-domains = <&rpmhpd RPMHPD_CX>; 1645 operating-points-v2 = <&qup_opp_table_120mhz>; 1646 1647 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1648 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1649 dma-names = "tx", 1650 "rx"; 1651 1652 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1653 pinctrl-names = "default"; 1654 1655 #address-cells = <1>; 1656 #size-cells = <0>; 1657 1658 status = "disabled"; 1659 }; 1660 1661 i2c10: i2c@a88000 { 1662 compatible = "qcom,geni-i2c"; 1663 reg = <0 0x00a88000 0 0x4000>; 1664 1665 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1666 1667 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1668 clock-names = "se"; 1669 1670 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1671 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1672 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1673 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1674 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1675 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1676 interconnect-names = "qup-core", 1677 "qup-config", 1678 "qup-memory"; 1679 1680 power-domains = <&rpmhpd RPMHPD_CX>; 1681 required-opps = <&rpmhpd_opp_low_svs>; 1682 1683 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1684 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1685 dma-names = "tx", 1686 "rx"; 1687 1688 pinctrl-0 = <&qup_i2c10_data_clk>; 1689 pinctrl-names = "default"; 1690 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 1694 status = "disabled"; 1695 }; 1696 1697 spi10: spi@a88000 { 1698 compatible = "qcom,geni-spi"; 1699 reg = <0 0x00a88000 0 0x4000>; 1700 1701 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1702 1703 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1704 clock-names = "se"; 1705 1706 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1707 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1708 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1709 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1710 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1711 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1712 interconnect-names = "qup-core", 1713 "qup-config", 1714 "qup-memory"; 1715 1716 power-domains = <&rpmhpd RPMHPD_CX>; 1717 operating-points-v2 = <&qup_opp_table_100mhz>; 1718 1719 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1720 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1721 dma-names = "tx", 1722 "rx"; 1723 1724 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1725 pinctrl-names = "default"; 1726 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 1730 status = "disabled"; 1731 }; 1732 1733 i2c11: i2c@a8c000 { 1734 compatible = "qcom,geni-i2c"; 1735 reg = <0 0x00a8c000 0 0x4000>; 1736 1737 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1738 1739 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1740 clock-names = "se"; 1741 1742 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1743 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1744 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1745 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1746 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1747 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1748 interconnect-names = "qup-core", 1749 "qup-config", 1750 "qup-memory"; 1751 1752 power-domains = <&rpmhpd RPMHPD_CX>; 1753 required-opps = <&rpmhpd_opp_low_svs>; 1754 1755 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1756 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1757 dma-names = "tx", 1758 "rx"; 1759 1760 pinctrl-0 = <&qup_i2c11_data_clk>; 1761 pinctrl-names = "default"; 1762 1763 #address-cells = <1>; 1764 #size-cells = <0>; 1765 1766 status = "disabled"; 1767 }; 1768 1769 spi11: spi@a8c000 { 1770 compatible = "qcom,geni-spi"; 1771 reg = <0 0x00a8c000 0 0x4000>; 1772 1773 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1774 1775 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1776 clock-names = "se"; 1777 1778 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1779 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1780 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1781 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1782 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1783 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1784 interconnect-names = "qup-core", 1785 "qup-config", 1786 "qup-memory"; 1787 1788 power-domains = <&rpmhpd RPMHPD_CX>; 1789 operating-points-v2 = <&qup_opp_table_100mhz>; 1790 1791 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1792 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1793 dma-names = "tx", 1794 "rx"; 1795 1796 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1797 pinctrl-names = "default"; 1798 1799 #address-cells = <1>; 1800 #size-cells = <0>; 1801 1802 status = "disabled"; 1803 }; 1804 1805 i2c12: i2c@a90000 { 1806 compatible = "qcom,geni-i2c"; 1807 reg = <0 0x00a90000 0 0x4000>; 1808 1809 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1810 1811 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1812 clock-names = "se"; 1813 1814 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1815 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1816 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1817 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1818 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1819 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1820 interconnect-names = "qup-core", 1821 "qup-config", 1822 "qup-memory"; 1823 1824 power-domains = <&rpmhpd RPMHPD_CX>; 1825 required-opps = <&rpmhpd_opp_low_svs>; 1826 1827 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1828 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1829 dma-names = "tx", 1830 "rx"; 1831 1832 pinctrl-0 = <&qup_i2c12_data_clk>; 1833 pinctrl-names = "default"; 1834 1835 #address-cells = <1>; 1836 #size-cells = <0>; 1837 1838 status = "disabled"; 1839 }; 1840 1841 spi12: spi@a90000 { 1842 compatible = "qcom,geni-spi"; 1843 reg = <0 0x00a90000 0 0x4000>; 1844 1845 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1846 1847 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1848 clock-names = "se"; 1849 1850 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1851 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1852 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1853 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1854 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1855 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1856 interconnect-names = "qup-core", 1857 "qup-config", 1858 "qup-memory"; 1859 1860 power-domains = <&rpmhpd RPMHPD_CX>; 1861 operating-points-v2 = <&qup_opp_table_100mhz>; 1862 1863 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1864 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1865 dma-names = "tx", 1866 "rx"; 1867 1868 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1869 pinctrl-names = "default"; 1870 1871 #address-cells = <1>; 1872 #size-cells = <0>; 1873 1874 status = "disabled"; 1875 }; 1876 1877 i2c13: i2c@a94000 { 1878 compatible = "qcom,geni-i2c"; 1879 reg = <0 0x00a94000 0 0x4000>; 1880 1881 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1882 1883 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1884 clock-names = "se"; 1885 1886 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1887 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1888 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1889 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1890 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1891 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1892 interconnect-names = "qup-core", 1893 "qup-config", 1894 "qup-memory"; 1895 1896 power-domains = <&rpmhpd RPMHPD_CX>; 1897 required-opps = <&rpmhpd_opp_low_svs>; 1898 1899 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1900 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1901 dma-names = "tx", 1902 "rx"; 1903 1904 pinctrl-0 = <&qup_i2c13_data_clk>; 1905 pinctrl-names = "default"; 1906 1907 #address-cells = <1>; 1908 #size-cells = <0>; 1909 1910 status = "disabled"; 1911 }; 1912 1913 spi13: spi@a94000 { 1914 compatible = "qcom,geni-spi"; 1915 reg = <0 0x00a94000 0 0x4000>; 1916 1917 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1918 1919 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1920 clock-names = "se"; 1921 1922 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1923 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1924 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1925 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1926 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1927 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1928 interconnect-names = "qup-core", 1929 "qup-config", 1930 "qup-memory"; 1931 1932 power-domains = <&rpmhpd RPMHPD_CX>; 1933 operating-points-v2 = <&qup_opp_table_100mhz>; 1934 1935 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1936 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1937 dma-names = "tx", 1938 "rx"; 1939 1940 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1941 pinctrl-names = "default"; 1942 1943 #address-cells = <1>; 1944 #size-cells = <0>; 1945 1946 status = "disabled"; 1947 }; 1948 1949 i2c14: i2c@a98000 { 1950 compatible = "qcom,geni-i2c"; 1951 reg = <0 0x00a98000 0 0x4000>; 1952 1953 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1954 1955 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1956 clock-names = "se"; 1957 1958 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1959 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1960 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1961 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1962 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1963 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1964 interconnect-names = "qup-core", 1965 "qup-config", 1966 "qup-memory"; 1967 1968 power-domains = <&rpmhpd RPMHPD_CX>; 1969 required-opps = <&rpmhpd_opp_low_svs>; 1970 1971 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1972 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1973 dma-names = "tx", 1974 "rx"; 1975 1976 pinctrl-0 = <&qup_i2c14_data_clk>; 1977 pinctrl-names = "default"; 1978 1979 #address-cells = <1>; 1980 #size-cells = <0>; 1981 1982 status = "disabled"; 1983 }; 1984 1985 spi14: spi@a98000 { 1986 compatible = "qcom,geni-spi"; 1987 reg = <0 0x00a98000 0 0x4000>; 1988 1989 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1990 1991 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1992 clock-names = "se"; 1993 1994 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1995 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1996 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1997 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1998 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1999 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2000 interconnect-names = "qup-core", 2001 "qup-config", 2002 "qup-memory"; 2003 2004 power-domains = <&rpmhpd RPMHPD_CX>; 2005 operating-points-v2 = <&qup_opp_table_100mhz>; 2006 2007 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2008 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2009 dma-names = "tx", 2010 "rx"; 2011 2012 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2013 pinctrl-names = "default"; 2014 2015 #address-cells = <1>; 2016 #size-cells = <0>; 2017 2018 status = "disabled"; 2019 }; 2020 2021 uart14: serial@a98000 { 2022 compatible = "qcom,geni-uart"; 2023 reg = <0 0x00a98000 0 0x4000>; 2024 2025 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 2026 2027 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2028 clock-names = "se"; 2029 2030 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2031 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2032 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2033 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2034 interconnect-names = "qup-core", 2035 "qup-config"; 2036 2037 power-domains = <&rpmhpd RPMHPD_CX>; 2038 operating-points-v2 = <&qup_opp_table_100mhz>; 2039 2040 pinctrl-0 = <&qup_uart14_default>; 2041 pinctrl-names = "default"; 2042 2043 status = "disabled"; 2044 }; 2045 2046 i2c15: i2c@a9c000 { 2047 compatible = "qcom,geni-i2c"; 2048 reg = <0 0x00a9c000 0 0x4000>; 2049 2050 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2051 2052 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2053 clock-names = "se"; 2054 2055 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2056 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2057 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2058 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2059 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2060 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2061 interconnect-names = "qup-core", 2062 "qup-config", 2063 "qup-memory"; 2064 2065 power-domains = <&rpmhpd RPMHPD_CX>; 2066 required-opps = <&rpmhpd_opp_low_svs>; 2067 2068 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2069 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2070 dma-names = "tx", 2071 "rx"; 2072 2073 pinctrl-0 = <&qup_i2c15_data_clk>; 2074 pinctrl-names = "default"; 2075 2076 #address-cells = <1>; 2077 #size-cells = <0>; 2078 2079 status = "disabled"; 2080 }; 2081 2082 spi15: spi@a9c000 { 2083 compatible = "qcom,geni-spi"; 2084 reg = <0 0x00a9c000 0 0x4000>; 2085 2086 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2087 2088 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2089 clock-names = "se"; 2090 2091 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2092 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2093 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2094 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2095 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2096 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2097 interconnect-names = "qup-core", 2098 "qup-config", 2099 "qup-memory"; 2100 2101 power-domains = <&rpmhpd RPMHPD_CX>; 2102 operating-points-v2 = <&qup_opp_table_100mhz>; 2103 2104 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2105 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2106 dma-names = "tx", 2107 "rx"; 2108 2109 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2110 pinctrl-names = "default"; 2111 2112 #address-cells = <1>; 2113 #size-cells = <0>; 2114 2115 status = "disabled"; 2116 }; 2117 }; 2118 2119 gpi_dma0: dma-controller@b00000 { 2120 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 2121 reg = <0 0x00b00000 0 0x60000>; 2122 2123 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 2125 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 2128 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 2131 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 2135 2136 dma-channels = <12>; 2137 dma-channel-mask = <0x3e>; 2138 #dma-cells = <3>; 2139 2140 iommus = <&apps_smmu 0x456 0x0>; 2141 2142 status = "disabled"; 2143 }; 2144 2145 qupv3_0: geniqup@bc0000 { 2146 compatible = "qcom,geni-se-qup"; 2147 reg = <0 0x00bc0000 0 0x2000>; 2148 2149 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 2150 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 2151 clock-names = "m-ahb", 2152 "s-ahb"; 2153 2154 iommus = <&apps_smmu 0x443 0x0>; 2155 #address-cells = <2>; 2156 #size-cells = <2>; 2157 ranges; 2158 2159 status = "disabled"; 2160 2161 i2c0: i2c@b80000 { 2162 compatible = "qcom,geni-i2c"; 2163 reg = <0 0x00b80000 0 0x4000>; 2164 2165 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2166 2167 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2168 clock-names = "se"; 2169 2170 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2171 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2172 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2173 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2174 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2176 interconnect-names = "qup-core", 2177 "qup-config", 2178 "qup-memory"; 2179 2180 power-domains = <&rpmhpd RPMHPD_CX>; 2181 required-opps = <&rpmhpd_opp_low_svs>; 2182 2183 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 2184 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 2185 dma-names = "tx", 2186 "rx"; 2187 2188 pinctrl-0 = <&qup_i2c0_data_clk>; 2189 pinctrl-names = "default"; 2190 2191 #address-cells = <1>; 2192 #size-cells = <0>; 2193 2194 status = "disabled"; 2195 }; 2196 2197 spi0: spi@b80000 { 2198 compatible = "qcom,geni-spi"; 2199 reg = <0 0x00b80000 0 0x4000>; 2200 2201 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2202 2203 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2204 clock-names = "se"; 2205 2206 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2207 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2208 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2209 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2210 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2211 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2212 interconnect-names = "qup-core", 2213 "qup-config", 2214 "qup-memory"; 2215 2216 power-domains = <&rpmhpd RPMHPD_CX>; 2217 operating-points-v2 = <&qup_opp_table_120mhz>; 2218 2219 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 2220 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 2221 dma-names = "tx", 2222 "rx"; 2223 2224 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2225 pinctrl-names = "default"; 2226 2227 #address-cells = <1>; 2228 #size-cells = <0>; 2229 2230 status = "disabled"; 2231 }; 2232 2233 i2c1: i2c@b84000 { 2234 compatible = "qcom,geni-i2c"; 2235 reg = <0 0x00b84000 0 0x4000>; 2236 2237 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2238 2239 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2240 clock-names = "se"; 2241 2242 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2243 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2244 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2245 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2246 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2247 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2248 interconnect-names = "qup-core", 2249 "qup-config", 2250 "qup-memory"; 2251 2252 power-domains = <&rpmhpd RPMHPD_CX>; 2253 required-opps = <&rpmhpd_opp_low_svs>; 2254 2255 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 2256 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 2257 dma-names = "tx", 2258 "rx"; 2259 2260 pinctrl-0 = <&qup_i2c1_data_clk>; 2261 pinctrl-names = "default"; 2262 2263 #address-cells = <1>; 2264 #size-cells = <0>; 2265 2266 status = "disabled"; 2267 }; 2268 2269 spi1: spi@b84000 { 2270 compatible = "qcom,geni-spi"; 2271 reg = <0 0x00b84000 0 0x4000>; 2272 2273 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2274 2275 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2276 clock-names = "se"; 2277 2278 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2279 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2280 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2281 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2282 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2283 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2284 interconnect-names = "qup-core", 2285 "qup-config", 2286 "qup-memory"; 2287 2288 power-domains = <&rpmhpd RPMHPD_CX>; 2289 operating-points-v2 = <&qup_opp_table_120mhz>; 2290 2291 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 2292 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 2293 dma-names = "tx", 2294 "rx"; 2295 2296 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 2297 pinctrl-names = "default"; 2298 2299 #address-cells = <1>; 2300 #size-cells = <0>; 2301 2302 status = "disabled"; 2303 }; 2304 2305 i2c2: i2c@b88000 { 2306 compatible = "qcom,geni-i2c"; 2307 reg = <0 0x00b88000 0 0x4000>; 2308 2309 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2310 2311 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2312 clock-names = "se"; 2313 2314 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2315 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2316 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2317 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2318 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2319 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2320 interconnect-names = "qup-core", 2321 "qup-config", 2322 "qup-memory"; 2323 2324 power-domains = <&rpmhpd RPMHPD_CX>; 2325 required-opps = <&rpmhpd_opp_low_svs>; 2326 2327 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2328 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2329 dma-names = "tx", 2330 "rx"; 2331 2332 pinctrl-0 = <&qup_i2c2_data_clk>; 2333 pinctrl-names = "default"; 2334 2335 #address-cells = <1>; 2336 #size-cells = <0>; 2337 2338 status = "disabled"; 2339 }; 2340 2341 uart2: serial@b88000 { 2342 compatible = "qcom,geni-uart"; 2343 reg = <0 0x00b88000 0 0x4000>; 2344 2345 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2346 2347 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2348 clock-names = "se"; 2349 2350 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2351 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2352 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2353 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2354 interconnect-names = "qup-core", 2355 "qup-config"; 2356 2357 power-domains = <&rpmhpd RPMHPD_CX>; 2358 operating-points-v2 = <&qup_opp_table_100mhz>; 2359 2360 pinctrl-0 = <&qup_uart2_default>; 2361 pinctrl-names = "default"; 2362 2363 status = "disabled"; 2364 }; 2365 2366 spi2: spi@b88000 { 2367 compatible = "qcom,geni-spi"; 2368 reg = <0 0x00b88000 0 0x4000>; 2369 2370 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2371 2372 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2373 clock-names = "se"; 2374 2375 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2376 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2377 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2378 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2379 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2380 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2381 interconnect-names = "qup-core", 2382 "qup-config", 2383 "qup-memory"; 2384 2385 power-domains = <&rpmhpd RPMHPD_CX>; 2386 operating-points-v2 = <&qup_opp_table_100mhz>; 2387 2388 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2389 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2390 dma-names = "tx", 2391 "rx"; 2392 2393 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2394 pinctrl-names = "default"; 2395 2396 #address-cells = <1>; 2397 #size-cells = <0>; 2398 2399 status = "disabled"; 2400 }; 2401 2402 i2c3: i2c@b8c000 { 2403 compatible = "qcom,geni-i2c"; 2404 reg = <0 0x00b8c000 0 0x4000>; 2405 2406 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2407 2408 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2409 clock-names = "se"; 2410 2411 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2412 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2413 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2414 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2415 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2416 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2417 interconnect-names = "qup-core", 2418 "qup-config", 2419 "qup-memory"; 2420 2421 power-domains = <&rpmhpd RPMHPD_CX>; 2422 required-opps = <&rpmhpd_opp_low_svs>; 2423 2424 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2425 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2426 dma-names = "tx", 2427 "rx"; 2428 2429 pinctrl-0 = <&qup_i2c3_data_clk>; 2430 pinctrl-names = "default"; 2431 2432 #address-cells = <1>; 2433 #size-cells = <0>; 2434 2435 status = "disabled"; 2436 }; 2437 2438 spi3: spi@b8c000 { 2439 compatible = "qcom,geni-spi"; 2440 reg = <0 0x00b8c000 0 0x4000>; 2441 2442 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2443 2444 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2445 clock-names = "se"; 2446 2447 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2448 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2449 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2450 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2451 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2452 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2453 interconnect-names = "qup-core", 2454 "qup-config", 2455 "qup-memory"; 2456 2457 power-domains = <&rpmhpd RPMHPD_CX>; 2458 operating-points-v2 = <&qup_opp_table_100mhz>; 2459 2460 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2461 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2462 dma-names = "tx", 2463 "rx"; 2464 2465 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2466 pinctrl-names = "default"; 2467 2468 #address-cells = <1>; 2469 #size-cells = <0>; 2470 2471 status = "disabled"; 2472 }; 2473 2474 i2c4: i2c@b90000 { 2475 compatible = "qcom,geni-i2c"; 2476 reg = <0 0x00b90000 0 0x4000>; 2477 2478 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2479 2480 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2481 clock-names = "se"; 2482 2483 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2484 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2485 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2486 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2487 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2488 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2489 interconnect-names = "qup-core", 2490 "qup-config", 2491 "qup-memory"; 2492 2493 power-domains = <&rpmhpd RPMHPD_CX>; 2494 required-opps = <&rpmhpd_opp_low_svs>; 2495 2496 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2497 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2498 dma-names = "tx", 2499 "rx"; 2500 2501 pinctrl-0 = <&qup_i2c4_data_clk>; 2502 pinctrl-names = "default"; 2503 2504 #address-cells = <1>; 2505 #size-cells = <0>; 2506 2507 status = "disabled"; 2508 }; 2509 2510 spi4: spi@b90000 { 2511 compatible = "qcom,geni-spi"; 2512 reg = <0 0x00b90000 0 0x4000>; 2513 2514 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2515 2516 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2517 clock-names = "se"; 2518 2519 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2520 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2521 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2522 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2523 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2524 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2525 interconnect-names = "qup-core", 2526 "qup-config", 2527 "qup-memory"; 2528 2529 power-domains = <&rpmhpd RPMHPD_CX>; 2530 operating-points-v2 = <&qup_opp_table_100mhz>; 2531 2532 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2533 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2534 dma-names = "tx", 2535 "rx"; 2536 2537 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2538 pinctrl-names = "default"; 2539 2540 #address-cells = <1>; 2541 #size-cells = <0>; 2542 2543 status = "disabled"; 2544 }; 2545 2546 i2c5: i2c@b94000 { 2547 compatible = "qcom,geni-i2c"; 2548 reg = <0 0x00b94000 0 0x4000>; 2549 2550 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2551 2552 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2553 clock-names = "se"; 2554 2555 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2556 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2557 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2558 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2559 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2560 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2561 interconnect-names = "qup-core", 2562 "qup-config", 2563 "qup-memory"; 2564 2565 power-domains = <&rpmhpd RPMHPD_CX>; 2566 required-opps = <&rpmhpd_opp_low_svs>; 2567 2568 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2569 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2570 dma-names = "tx", 2571 "rx"; 2572 2573 pinctrl-0 = <&qup_i2c5_data_clk>; 2574 pinctrl-names = "default"; 2575 2576 #address-cells = <1>; 2577 #size-cells = <0>; 2578 2579 status = "disabled"; 2580 }; 2581 2582 spi5: spi@b94000 { 2583 compatible = "qcom,geni-spi"; 2584 reg = <0 0x00b94000 0 0x4000>; 2585 2586 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2587 2588 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2589 clock-names = "se"; 2590 2591 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2592 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2593 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2594 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2595 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2596 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2597 interconnect-names = "qup-core", 2598 "qup-config", 2599 "qup-memory"; 2600 2601 power-domains = <&rpmhpd RPMHPD_CX>; 2602 operating-points-v2 = <&qup_opp_table_100mhz>; 2603 2604 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2605 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2606 dma-names = "tx", 2607 "rx"; 2608 2609 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2610 pinctrl-names = "default"; 2611 2612 #address-cells = <1>; 2613 #size-cells = <0>; 2614 2615 status = "disabled"; 2616 }; 2617 2618 i2c6: i2c@b98000 { 2619 compatible = "qcom,geni-i2c"; 2620 reg = <0 0x00b98000 0 0x4000>; 2621 2622 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2623 2624 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2625 clock-names = "se"; 2626 2627 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2628 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2629 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2630 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2631 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2632 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2633 interconnect-names = "qup-core", 2634 "qup-config", 2635 "qup-memory"; 2636 2637 power-domains = <&rpmhpd RPMHPD_CX>; 2638 required-opps = <&rpmhpd_opp_low_svs>; 2639 2640 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2641 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2642 dma-names = "tx", 2643 "rx"; 2644 2645 pinctrl-0 = <&qup_i2c6_data_clk>; 2646 pinctrl-names = "default"; 2647 2648 #address-cells = <1>; 2649 #size-cells = <0>; 2650 2651 status = "disabled"; 2652 }; 2653 2654 spi6: spi@b98000 { 2655 compatible = "qcom,geni-spi"; 2656 reg = <0 0x00b98000 0 0x4000>; 2657 2658 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2659 2660 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2661 clock-names = "se"; 2662 2663 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2664 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2665 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2666 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2667 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2668 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2669 interconnect-names = "qup-core", 2670 "qup-config", 2671 "qup-memory"; 2672 2673 power-domains = <&rpmhpd RPMHPD_CX>; 2674 operating-points-v2 = <&qup_opp_table_100mhz>; 2675 2676 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2677 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2678 dma-names = "tx", 2679 "rx"; 2680 2681 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2682 pinctrl-names = "default"; 2683 2684 #address-cells = <1>; 2685 #size-cells = <0>; 2686 2687 status = "disabled"; 2688 }; 2689 2690 i2c7: i2c@b9c000 { 2691 compatible = "qcom,geni-i2c"; 2692 reg = <0 0x00b9c000 0 0x4000>; 2693 2694 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2695 2696 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2697 clock-names = "se"; 2698 2699 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2700 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2701 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2702 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2703 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2704 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2705 interconnect-names = "qup-core", 2706 "qup-config", 2707 "qup-memory"; 2708 2709 power-domains = <&rpmhpd RPMHPD_CX>; 2710 required-opps = <&rpmhpd_opp_low_svs>; 2711 2712 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2713 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2714 dma-names = "tx", 2715 "rx"; 2716 2717 pinctrl-0 = <&qup_i2c7_data_clk>; 2718 pinctrl-names = "default"; 2719 2720 #address-cells = <1>; 2721 #size-cells = <0>; 2722 2723 status = "disabled"; 2724 }; 2725 2726 spi7: spi@b9c000 { 2727 compatible = "qcom,geni-spi"; 2728 reg = <0 0x00b9c000 0 0x4000>; 2729 2730 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2731 2732 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2733 clock-names = "se"; 2734 2735 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2736 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2737 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2738 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 2739 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2740 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2741 interconnect-names = "qup-core", 2742 "qup-config", 2743 "qup-memory"; 2744 2745 power-domains = <&rpmhpd RPMHPD_CX>; 2746 operating-points-v2 = <&qup_opp_table_100mhz>; 2747 2748 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2749 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2750 dma-names = "tx", 2751 "rx"; 2752 2753 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2754 pinctrl-names = "default"; 2755 2756 #address-cells = <1>; 2757 #size-cells = <0>; 2758 2759 status = "disabled"; 2760 }; 2761 }; 2762 2763 tsens0: thermal-sensor@c271000 { 2764 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2765 reg = <0 0x0c271000 0 0x1000>, 2766 <0 0x0c222000 0 0x1000>; 2767 2768 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2769 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2770 interrupt-names = "uplow", 2771 "critical"; 2772 2773 #qcom,sensors = <16>; 2774 2775 #thermal-sensor-cells = <1>; 2776 }; 2777 2778 tsens1: thermal-sensor@c272000 { 2779 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2780 reg = <0 0x0c272000 0 0x1000>, 2781 <0 0x0c223000 0 0x1000>; 2782 2783 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2784 <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2785 interrupt-names = "uplow", 2786 "critical"; 2787 2788 #qcom,sensors = <16>; 2789 2790 #thermal-sensor-cells = <1>; 2791 }; 2792 2793 tsens2: thermal-sensor@c273000 { 2794 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2795 reg = <0 0x0c273000 0 0x1000>, 2796 <0 0x0c224000 0 0x1000>; 2797 2798 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>, 2799 <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 2800 interrupt-names = "uplow", 2801 "critical"; 2802 2803 #qcom,sensors = <16>; 2804 2805 #thermal-sensor-cells = <1>; 2806 }; 2807 2808 tsens3: thermal-sensor@c274000 { 2809 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2810 reg = <0 0x0c274000 0 0x1000>, 2811 <0 0x0c225000 0 0x1000>; 2812 2813 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>, 2814 <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; 2815 interrupt-names = "uplow", 2816 "critical"; 2817 2818 #qcom,sensors = <16>; 2819 2820 #thermal-sensor-cells = <1>; 2821 }; 2822 2823 usb_1_ss0_hsphy: phy@fd3000 { 2824 compatible = "qcom,x1e80100-snps-eusb2-phy", 2825 "qcom,sm8550-snps-eusb2-phy"; 2826 reg = <0 0x00fd3000 0 0x154>; 2827 #phy-cells = <0>; 2828 2829 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2830 clock-names = "ref"; 2831 2832 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2833 2834 status = "disabled"; 2835 }; 2836 2837 usb_1_ss0_qmpphy: phy@fd5000 { 2838 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2839 reg = <0 0x00fd5000 0 0x4000>; 2840 2841 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2842 <&rpmhcc RPMH_CXO_CLK>, 2843 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2844 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2845 clock-names = "aux", 2846 "ref", 2847 "com_aux", 2848 "usb3_pipe"; 2849 2850 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2851 2852 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2853 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; 2854 reset-names = "phy", 2855 "common"; 2856 2857 #clock-cells = <1>; 2858 #phy-cells = <1>; 2859 2860 mode-switch; 2861 orientation-switch; 2862 2863 status = "disabled"; 2864 2865 ports { 2866 #address-cells = <1>; 2867 #size-cells = <0>; 2868 2869 port@0 { 2870 reg = <0>; 2871 2872 usb_1_ss0_qmpphy_out: endpoint { 2873 }; 2874 }; 2875 2876 port@1 { 2877 reg = <1>; 2878 2879 usb_1_ss0_qmpphy_usb_ss_in: endpoint { 2880 remote-endpoint = <&usb_1_ss0_dwc3_ss>; 2881 }; 2882 }; 2883 2884 port@2 { 2885 reg = <2>; 2886 2887 usb_1_ss0_qmpphy_dp_in: endpoint { 2888 remote-endpoint = <&mdss_dp0_out>; 2889 }; 2890 }; 2891 }; 2892 }; 2893 2894 usb_1_ss1_hsphy: phy@fd9000 { 2895 compatible = "qcom,x1e80100-snps-eusb2-phy", 2896 "qcom,sm8550-snps-eusb2-phy"; 2897 reg = <0 0x00fd9000 0 0x154>; 2898 #phy-cells = <0>; 2899 2900 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2901 clock-names = "ref"; 2902 2903 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2904 2905 status = "disabled"; 2906 }; 2907 2908 usb_1_ss1_qmpphy: phy@fda000 { 2909 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2910 reg = <0 0x00fda000 0 0x4000>; 2911 2912 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2913 <&rpmhcc RPMH_CXO_CLK>, 2914 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2915 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2916 clock-names = "aux", 2917 "ref", 2918 "com_aux", 2919 "usb3_pipe"; 2920 2921 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2922 2923 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2924 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; 2925 reset-names = "phy", 2926 "common"; 2927 2928 #clock-cells = <1>; 2929 #phy-cells = <1>; 2930 2931 mode-switch; 2932 orientation-switch; 2933 2934 status = "disabled"; 2935 2936 ports { 2937 #address-cells = <1>; 2938 #size-cells = <0>; 2939 2940 port@0 { 2941 reg = <0>; 2942 2943 usb_1_ss1_qmpphy_out: endpoint { 2944 }; 2945 }; 2946 2947 port@1 { 2948 reg = <1>; 2949 2950 usb_1_ss1_qmpphy_usb_ss_in: endpoint { 2951 remote-endpoint = <&usb_1_ss1_dwc3_ss>; 2952 }; 2953 }; 2954 2955 port@2 { 2956 reg = <2>; 2957 2958 usb_1_ss1_qmpphy_dp_in: endpoint { 2959 remote-endpoint = <&mdss_dp1_out>; 2960 }; 2961 }; 2962 }; 2963 }; 2964 2965 usb_1_ss2_hsphy: phy@fde000 { 2966 compatible = "qcom,x1e80100-snps-eusb2-phy", 2967 "qcom,sm8550-snps-eusb2-phy"; 2968 reg = <0 0x00fde000 0 0x154>; 2969 #phy-cells = <0>; 2970 2971 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2972 clock-names = "ref"; 2973 2974 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 2975 2976 status = "disabled"; 2977 }; 2978 2979 usb_1_ss2_qmpphy: phy@fdf000 { 2980 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2981 reg = <0 0x00fdf000 0 0x4000>; 2982 2983 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 2984 <&rpmhcc RPMH_CXO_CLK>, 2985 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 2986 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 2987 clock-names = "aux", 2988 "ref", 2989 "com_aux", 2990 "usb3_pipe"; 2991 2992 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 2993 2994 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 2995 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; 2996 reset-names = "phy", 2997 "common"; 2998 2999 #clock-cells = <1>; 3000 #phy-cells = <1>; 3001 3002 mode-switch; 3003 orientation-switch; 3004 3005 status = "disabled"; 3006 3007 ports { 3008 #address-cells = <1>; 3009 #size-cells = <0>; 3010 3011 port@0 { 3012 reg = <0>; 3013 3014 usb_1_ss2_qmpphy_out: endpoint { 3015 }; 3016 }; 3017 3018 port@1 { 3019 reg = <1>; 3020 3021 usb_1_ss2_qmpphy_usb_ss_in: endpoint { 3022 remote-endpoint = <&usb_1_ss2_dwc3_ss>; 3023 }; 3024 }; 3025 3026 port@2 { 3027 reg = <2>; 3028 3029 usb_1_ss2_qmpphy_dp_in: endpoint { 3030 remote-endpoint = <&mdss_dp2_out>; 3031 }; 3032 }; 3033 }; 3034 }; 3035 3036 cnoc_main: interconnect@1500000 { 3037 compatible = "qcom,x1e80100-cnoc-main"; 3038 reg = <0 0x01500000 0 0x14400>; 3039 3040 qcom,bcm-voters = <&apps_bcm_voter>; 3041 3042 #interconnect-cells = <2>; 3043 }; 3044 3045 config_noc: interconnect@1600000 { 3046 compatible = "qcom,x1e80100-cnoc-cfg"; 3047 reg = <0 0x01600000 0 0x6600>; 3048 3049 qcom,bcm-voters = <&apps_bcm_voter>; 3050 3051 #interconnect-cells = <2>; 3052 }; 3053 3054 system_noc: interconnect@1680000 { 3055 compatible = "qcom,x1e80100-system-noc"; 3056 reg = <0 0x01680000 0 0x1c080>; 3057 3058 qcom,bcm-voters = <&apps_bcm_voter>; 3059 3060 #interconnect-cells = <2>; 3061 }; 3062 3063 pcie_south_anoc: interconnect@16c0000 { 3064 compatible = "qcom,x1e80100-pcie-south-anoc"; 3065 reg = <0 0x016c0000 0 0xd080>; 3066 3067 qcom,bcm-voters = <&apps_bcm_voter>; 3068 3069 #interconnect-cells = <2>; 3070 }; 3071 3072 pcie_center_anoc: interconnect@16d0000 { 3073 compatible = "qcom,x1e80100-pcie-center-anoc"; 3074 reg = <0 0x016d0000 0 0x7000>; 3075 3076 qcom,bcm-voters = <&apps_bcm_voter>; 3077 3078 #interconnect-cells = <2>; 3079 }; 3080 3081 aggre1_noc: interconnect@16e0000 { 3082 compatible = "qcom,x1e80100-aggre1-noc"; 3083 reg = <0 0x016e0000 0 0x14400>; 3084 3085 qcom,bcm-voters = <&apps_bcm_voter>; 3086 3087 #interconnect-cells = <2>; 3088 }; 3089 3090 aggre2_noc: interconnect@1700000 { 3091 compatible = "qcom,x1e80100-aggre2-noc"; 3092 reg = <0 0x01700000 0 0x1c400>; 3093 3094 qcom,bcm-voters = <&apps_bcm_voter>; 3095 3096 #interconnect-cells = <2>; 3097 }; 3098 3099 pcie_north_anoc: interconnect@1740000 { 3100 compatible = "qcom,x1e80100-pcie-north-anoc"; 3101 reg = <0 0x01740000 0 0x9080>; 3102 3103 qcom,bcm-voters = <&apps_bcm_voter>; 3104 3105 #interconnect-cells = <2>; 3106 }; 3107 3108 usb_center_anoc: interconnect@1750000 { 3109 compatible = "qcom,x1e80100-usb-center-anoc"; 3110 reg = <0 0x01750000 0 0x8800>; 3111 3112 qcom,bcm-voters = <&apps_bcm_voter>; 3113 3114 #interconnect-cells = <2>; 3115 }; 3116 3117 usb_north_anoc: interconnect@1760000 { 3118 compatible = "qcom,x1e80100-usb-north-anoc"; 3119 reg = <0 0x01760000 0 0x7080>; 3120 3121 qcom,bcm-voters = <&apps_bcm_voter>; 3122 3123 #interconnect-cells = <2>; 3124 }; 3125 3126 usb_south_anoc: interconnect@1770000 { 3127 compatible = "qcom,x1e80100-usb-south-anoc"; 3128 reg = <0 0x01770000 0 0xf080>; 3129 3130 qcom,bcm-voters = <&apps_bcm_voter>; 3131 3132 #interconnect-cells = <2>; 3133 }; 3134 3135 mmss_noc: interconnect@1780000 { 3136 compatible = "qcom,x1e80100-mmss-noc"; 3137 reg = <0 0x01780000 0 0x5B800>; 3138 3139 qcom,bcm-voters = <&apps_bcm_voter>; 3140 3141 #interconnect-cells = <2>; 3142 }; 3143 3144 pcie3: pcie@1bd0000 { 3145 device_type = "pci"; 3146 compatible = "qcom,pcie-x1e80100"; 3147 reg = <0x0 0x01bd0000 0x0 0x3000>, 3148 <0x0 0x78000000 0x0 0xf20>, 3149 <0x0 0x78000f40 0x0 0xa8>, 3150 <0x0 0x78001000 0x0 0x1000>, 3151 <0x0 0x78100000 0x0 0x100000>, 3152 <0x0 0x01bd3000 0x0 0x1000>; 3153 reg-names = "parf", 3154 "dbi", 3155 "elbi", 3156 "atu", 3157 "config", 3158 "mhi"; 3159 #address-cells = <3>; 3160 #size-cells = <2>; 3161 ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>, 3162 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>, 3163 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3164 bus-range = <0x00 0xff>; 3165 3166 dma-coherent; 3167 3168 linux,pci-domain = <3>; 3169 num-lanes = <8>; 3170 3171 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 3172 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 3176 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 3180 interrupt-names = "msi0", 3181 "msi1", 3182 "msi2", 3183 "msi3", 3184 "msi4", 3185 "msi5", 3186 "msi6", 3187 "msi7", 3188 "global"; 3189 3190 #interrupt-cells = <1>; 3191 interrupt-map-mask = <0 0 0 0x7>; 3192 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 3193 <0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 3194 <0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 3195 <0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3196 3197 clocks = <&gcc GCC_PCIE_3_AUX_CLK>, 3198 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3199 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 3200 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 3201 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, 3202 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3203 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3204 clock-names = "aux", 3205 "cfg", 3206 "bus_master", 3207 "bus_slave", 3208 "slave_q2a", 3209 "noc_aggr", 3210 "cnoc_sf_axi"; 3211 3212 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 3213 assigned-clock-rates = <19200000>; 3214 3215 interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS 3216 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3217 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3218 &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ACTIVE_ONLY>; 3219 interconnect-names = "pcie-mem", 3220 "cpu-pcie"; 3221 3222 resets = <&gcc GCC_PCIE_3_BCR>, 3223 <&gcc GCC_PCIE_3_LINK_DOWN_BCR>; 3224 reset-names = "pci", 3225 "link_down"; 3226 3227 power-domains = <&gcc GCC_PCIE_3_GDSC>; 3228 3229 phys = <&pcie3_phy>; 3230 phy-names = "pciephy"; 3231 3232 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 3233 0x5555 0x5555 0x5555 0x5555>; 3234 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; 3235 3236 operating-points-v2 = <&pcie3_opp_table>; 3237 3238 status = "disabled"; 3239 3240 pcie3_opp_table: opp-table { 3241 compatible = "operating-points-v2"; 3242 3243 /* GEN 1 x1 */ 3244 opp-2500000 { 3245 opp-hz = /bits/ 64 <2500000>; 3246 required-opps = <&rpmhpd_opp_low_svs>; 3247 opp-peak-kBps = <250000 1>; 3248 }; 3249 3250 /* GEN 1 x2 and GEN 2 x1 */ 3251 opp-5000000 { 3252 opp-hz = /bits/ 64 <5000000>; 3253 required-opps = <&rpmhpd_opp_low_svs>; 3254 opp-peak-kBps = <500000 1>; 3255 }; 3256 3257 /* GEN 1 x4 and GEN 2 x2 */ 3258 opp-10000000 { 3259 opp-hz = /bits/ 64 <10000000>; 3260 required-opps = <&rpmhpd_opp_low_svs>; 3261 opp-peak-kBps = <1000000 1>; 3262 }; 3263 3264 /* GEN 1 x8 and GEN 2 x4 */ 3265 opp-20000000 { 3266 opp-hz = /bits/ 64 <20000000>; 3267 required-opps = <&rpmhpd_opp_low_svs>; 3268 opp-peak-kBps = <2000000 1>; 3269 }; 3270 3271 /* GEN 2 x8 */ 3272 opp-40000000 { 3273 opp-hz = /bits/ 64 <40000000>; 3274 required-opps = <&rpmhpd_opp_low_svs>; 3275 opp-peak-kBps = <4000000 1>; 3276 }; 3277 3278 /* GEN 3 x1 */ 3279 opp-8000000 { 3280 opp-hz = /bits/ 64 <8000000>; 3281 required-opps = <&rpmhpd_opp_svs>; 3282 opp-peak-kBps = <984500 1>; 3283 }; 3284 3285 /* GEN 3 x2 and GEN 4 x1 */ 3286 opp-16000000 { 3287 opp-hz = /bits/ 64 <16000000>; 3288 required-opps = <&rpmhpd_opp_svs>; 3289 opp-peak-kBps = <1969000 1>; 3290 }; 3291 3292 /* GEN 3 x4 and GEN 4 x2 */ 3293 opp-32000000 { 3294 opp-hz = /bits/ 64 <32000000>; 3295 required-opps = <&rpmhpd_opp_svs>; 3296 opp-peak-kBps = <3938000 1>; 3297 }; 3298 3299 /* GEN 3 x8 and GEN 4 x4 */ 3300 opp-64000000 { 3301 opp-hz = /bits/ 64 <64000000>; 3302 required-opps = <&rpmhpd_opp_svs>; 3303 opp-peak-kBps = <7876000 1>; 3304 }; 3305 3306 /* GEN 4 x8 */ 3307 opp-128000000 { 3308 opp-hz = /bits/ 64 <128000000>; 3309 required-opps = <&rpmhpd_opp_svs>; 3310 opp-peak-kBps = <15753000 1>; 3311 }; 3312 }; 3313 3314 pcie3_port: pcie@0 { 3315 device_type = "pci"; 3316 compatible = "pciclass,0604"; 3317 reg = <0x0 0x0 0x0 0x0 0x0>; 3318 bus-range = <0x01 0xff>; 3319 3320 #address-cells = <3>; 3321 #size-cells = <2>; 3322 ranges; 3323 }; 3324 }; 3325 3326 pcie3_phy: phy@1be0000 { 3327 compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy"; 3328 reg = <0 0x01be0000 0 0x10000>; 3329 3330 clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>, 3331 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3332 <&tcsr TCSR_PCIE_8L_CLKREF_EN>, 3333 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>, 3334 <&gcc GCC_PCIE_3_PIPE_CLK>, 3335 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>; 3336 clock-names = "aux", 3337 "cfg_ahb", 3338 "ref", 3339 "rchng", 3340 "pipe", 3341 "pipediv2"; 3342 3343 resets = <&gcc GCC_PCIE_3_PHY_BCR>, 3344 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>; 3345 reset-names = "phy", 3346 "phy_nocsr"; 3347 3348 assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>; 3349 assigned-clock-rates = <100000000>; 3350 3351 power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>; 3352 3353 #clock-cells = <0>; 3354 clock-output-names = "pcie3_pipe_clk"; 3355 3356 #phy-cells = <0>; 3357 3358 status = "disabled"; 3359 }; 3360 3361 pcie6a: pci@1bf8000 { 3362 device_type = "pci"; 3363 compatible = "qcom,pcie-x1e80100"; 3364 reg = <0 0x01bf8000 0 0x3000>, 3365 <0 0x70000000 0 0xf20>, 3366 <0 0x70000f40 0 0xa8>, 3367 <0 0x70001000 0 0x1000>, 3368 <0 0x70100000 0 0x100000>, 3369 <0 0x01bfb000 0 0x1000>; 3370 reg-names = "parf", 3371 "dbi", 3372 "elbi", 3373 "atu", 3374 "config", 3375 "mhi"; 3376 #address-cells = <3>; 3377 #size-cells = <2>; 3378 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, 3379 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 3380 bus-range = <0x00 0xff>; 3381 3382 dma-coherent; 3383 3384 linux,pci-domain = <6>; 3385 num-lanes = <4>; 3386 3387 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3388 3389 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>; 3398 interrupt-names = "msi0", 3399 "msi1", 3400 "msi2", 3401 "msi3", 3402 "msi4", 3403 "msi5", 3404 "msi6", 3405 "msi7", 3406 "global"; 3407 3408 #interrupt-cells = <1>; 3409 interrupt-map-mask = <0 0 0 0x7>; 3410 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 3411 <0 0 0 2 &intc 0 0 GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 3412 <0 0 0 3 &intc 0 0 GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 3413 <0 0 0 4 &intc 0 0 GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>; 3414 3415 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, 3416 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3417 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, 3418 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, 3419 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, 3420 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>, 3421 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; 3422 clock-names = "aux", 3423 "cfg", 3424 "bus_master", 3425 "bus_slave", 3426 "slave_q2a", 3427 "noc_aggr", 3428 "cnoc_sf_axi"; 3429 3430 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; 3431 assigned-clock-rates = <19200000>; 3432 3433 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS 3434 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3435 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3436 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ACTIVE_ONLY>; 3437 interconnect-names = "pcie-mem", 3438 "cpu-pcie"; 3439 3440 resets = <&gcc GCC_PCIE_6A_BCR>, 3441 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; 3442 reset-names = "pci", 3443 "link_down"; 3444 3445 power-domains = <&gcc GCC_PCIE_6A_GDSC>; 3446 required-opps = <&rpmhpd_opp_nom>; 3447 3448 phys = <&pcie6a_phy>; 3449 phy-names = "pciephy"; 3450 3451 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3452 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3453 3454 status = "disabled"; 3455 }; 3456 3457 pcie6a_phy: phy@1bfc000 { 3458 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy"; 3459 reg = <0 0x01bfc000 0 0x2000>, 3460 <0 0x01bfe000 0 0x2000>; 3461 3462 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, 3463 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3464 <&tcsr TCSR_PCIE_4L_CLKREF_EN>, 3465 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, 3466 <&gcc GCC_PCIE_6A_PIPE_CLK>, 3467 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>; 3468 clock-names = "aux", 3469 "cfg_ahb", 3470 "ref", 3471 "rchng", 3472 "pipe", 3473 "pipediv2"; 3474 3475 resets = <&gcc GCC_PCIE_6A_PHY_BCR>, 3476 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; 3477 reset-names = "phy", 3478 "phy_nocsr"; 3479 3480 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; 3481 assigned-clock-rates = <100000000>; 3482 3483 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3484 3485 qcom,4ln-config-sel = <&tcsr 0x1a000 0>; 3486 3487 #clock-cells = <0>; 3488 clock-output-names = "pcie6a_pipe_clk"; 3489 3490 #phy-cells = <0>; 3491 3492 status = "disabled"; 3493 }; 3494 3495 pcie5: pci@1c00000 { 3496 device_type = "pci"; 3497 compatible = "qcom,pcie-x1e80100"; 3498 reg = <0 0x01c00000 0 0x3000>, 3499 <0 0x7e000000 0 0xf1d>, 3500 <0 0x7e000f40 0 0xa8>, 3501 <0 0x7e001000 0 0x1000>, 3502 <0 0x7e100000 0 0x100000>, 3503 <0 0x01c03000 0 0x1000>; 3504 reg-names = "parf", 3505 "dbi", 3506 "elbi", 3507 "atu", 3508 "config", 3509 "mhi"; 3510 #address-cells = <3>; 3511 #size-cells = <2>; 3512 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3513 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>; 3514 bus-range = <0x00 0xff>; 3515 3516 dma-coherent; 3517 3518 linux,pci-domain = <5>; 3519 num-lanes = <2>; 3520 3521 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3522 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3523 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3524 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3525 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3526 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 3527 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 3528 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 3529 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 3530 interrupt-names = "msi0", 3531 "msi1", 3532 "msi2", 3533 "msi3", 3534 "msi4", 3535 "msi5", 3536 "msi6", 3537 "msi7", 3538 "global"; 3539 3540 #interrupt-cells = <1>; 3541 interrupt-map-mask = <0 0 0 0x7>; 3542 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 3543 <0 0 0 2 &intc 0 0 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 3544 <0 0 0 3 &intc 0 0 GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 3545 <0 0 0 4 &intc 0 0 GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 3546 3547 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3548 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3549 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 3550 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 3551 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 3552 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3553 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3554 clock-names = "aux", 3555 "cfg", 3556 "bus_master", 3557 "bus_slave", 3558 "slave_q2a", 3559 "noc_aggr", 3560 "cnoc_sf_axi"; 3561 3562 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3563 assigned-clock-rates = <19200000>; 3564 3565 interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3566 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3567 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3568 &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ACTIVE_ONLY>; 3569 interconnect-names = "pcie-mem", 3570 "cpu-pcie"; 3571 3572 resets = <&gcc GCC_PCIE_5_BCR>, 3573 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3574 reset-names = "pci", 3575 "link_down"; 3576 3577 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3578 required-opps = <&rpmhpd_opp_nom>; 3579 3580 phys = <&pcie5_phy>; 3581 phy-names = "pciephy"; 3582 3583 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3584 3585 status = "disabled"; 3586 }; 3587 3588 pcie5_phy: phy@1c06000 { 3589 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3590 reg = <0 0x01c06000 0 0x2000>; 3591 3592 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3593 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3594 <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>, 3595 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3596 <&gcc GCC_PCIE_5_PIPE_CLK>, 3597 <&gcc GCC_PCIE_5_PIPEDIV2_CLK>; 3598 clock-names = "aux", 3599 "cfg_ahb", 3600 "ref", 3601 "rchng", 3602 "pipe", 3603 "pipediv2"; 3604 3605 resets = <&gcc GCC_PCIE_5_PHY_BCR>, 3606 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; 3607 reset-names = "phy", 3608 "phy_nocsr"; 3609 3610 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3611 assigned-clock-rates = <100000000>; 3612 3613 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3614 3615 #clock-cells = <0>; 3616 clock-output-names = "pcie5_pipe_clk"; 3617 3618 #phy-cells = <0>; 3619 3620 status = "disabled"; 3621 }; 3622 3623 pcie4: pci@1c08000 { 3624 device_type = "pci"; 3625 compatible = "qcom,pcie-x1e80100"; 3626 reg = <0 0x01c08000 0 0x3000>, 3627 <0 0x7c000000 0 0xf1d>, 3628 <0 0x7c000f40 0 0xa8>, 3629 <0 0x7c001000 0 0x1000>, 3630 <0 0x7c100000 0 0x100000>, 3631 <0 0x01c0b000 0 0x1000>; 3632 reg-names = "parf", 3633 "dbi", 3634 "elbi", 3635 "atu", 3636 "config", 3637 "mhi"; 3638 #address-cells = <3>; 3639 #size-cells = <2>; 3640 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>, 3641 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>; 3642 bus-range = <0x00 0xff>; 3643 3644 dma-coherent; 3645 3646 linux,pci-domain = <4>; 3647 num-lanes = <2>; 3648 3649 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 3650 3651 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3652 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 3653 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3654 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3656 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3657 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3658 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 3659 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 3660 interrupt-names = "msi0", 3661 "msi1", 3662 "msi2", 3663 "msi3", 3664 "msi4", 3665 "msi5", 3666 "msi6", 3667 "msi7", 3668 "global"; 3669 3670 #interrupt-cells = <1>; 3671 interrupt-map-mask = <0 0 0 0x7>; 3672 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 3673 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 3674 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 3675 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 3676 3677 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3678 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3679 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 3680 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 3681 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 3682 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3683 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3684 clock-names = "aux", 3685 "cfg", 3686 "bus_master", 3687 "bus_slave", 3688 "slave_q2a", 3689 "noc_aggr", 3690 "cnoc_sf_axi"; 3691 3692 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 3693 assigned-clock-rates = <19200000>; 3694 3695 interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 3696 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3697 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3698 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 3699 interconnect-names = "pcie-mem", 3700 "cpu-pcie"; 3701 3702 resets = <&gcc GCC_PCIE_4_BCR>, 3703 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 3704 reset-names = "pci", 3705 "link_down"; 3706 3707 power-domains = <&gcc GCC_PCIE_4_GDSC>; 3708 required-opps = <&rpmhpd_opp_nom>; 3709 3710 phys = <&pcie4_phy>; 3711 phy-names = "pciephy"; 3712 3713 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3714 3715 status = "disabled"; 3716 3717 pcie4_port0: pcie@0 { 3718 device_type = "pci"; 3719 reg = <0x0 0x0 0x0 0x0 0x0>; 3720 bus-range = <0x01 0xff>; 3721 3722 #address-cells = <3>; 3723 #size-cells = <2>; 3724 ranges; 3725 }; 3726 }; 3727 3728 pcie4_phy: phy@1c0e000 { 3729 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3730 reg = <0 0x01c0e000 0 0x2000>; 3731 3732 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3733 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3734 <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>, 3735 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 3736 <&gcc GCC_PCIE_4_PIPE_CLK>, 3737 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 3738 clock-names = "aux", 3739 "cfg_ahb", 3740 "ref", 3741 "rchng", 3742 "pipe", 3743 "pipediv2"; 3744 3745 resets = <&gcc GCC_PCIE_4_PHY_BCR>, 3746 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; 3747 reset-names = "phy", 3748 "phy_nocsr"; 3749 3750 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 3751 assigned-clock-rates = <100000000>; 3752 3753 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 3754 3755 #clock-cells = <0>; 3756 clock-output-names = "pcie4_pipe_clk"; 3757 3758 #phy-cells = <0>; 3759 3760 status = "disabled"; 3761 }; 3762 3763 tcsr_mutex: hwlock@1f40000 { 3764 compatible = "qcom,tcsr-mutex"; 3765 reg = <0 0x01f40000 0 0x20000>; 3766 #hwlock-cells = <1>; 3767 }; 3768 3769 tcsr: clock-controller@1fc0000 { 3770 compatible = "qcom,x1e80100-tcsr", "syscon"; 3771 reg = <0 0x01fc0000 0 0x30000>; 3772 clocks = <&rpmhcc RPMH_CXO_CLK>; 3773 #clock-cells = <1>; 3774 #reset-cells = <1>; 3775 }; 3776 3777 gpu: gpu@3d00000 { 3778 compatible = "qcom,adreno-43050c01", "qcom,adreno"; 3779 reg = <0x0 0x03d00000 0x0 0x40000>, 3780 <0x0 0x03d9e000 0x0 0x1000>, 3781 <0x0 0x03d61000 0x0 0x800>; 3782 3783 reg-names = "kgsl_3d0_reg_memory", 3784 "cx_mem", 3785 "cx_dbgc"; 3786 3787 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3788 3789 iommus = <&adreno_smmu 0 0x0>, 3790 <&adreno_smmu 1 0x0>; 3791 3792 operating-points-v2 = <&gpu_opp_table>; 3793 3794 qcom,gmu = <&gmu>; 3795 #cooling-cells = <2>; 3796 3797 nvmem-cells = <&gpu_speed_bin>; 3798 nvmem-cell-names = "speed_bin"; 3799 3800 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3801 interconnect-names = "gfx-mem"; 3802 3803 status = "disabled"; 3804 3805 gpu_zap_shader: zap-shader { 3806 memory-region = <&gpu_microcode_mem>; 3807 }; 3808 3809 gpu_opp_table: opp-table { 3810 compatible = "operating-points-v2-adreno", "operating-points-v2"; 3811 3812 opp-1500000000 { 3813 opp-hz = /bits/ 64 <1500000000>; 3814 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>; 3815 opp-peak-kBps = <16500000>; 3816 qcom,opp-acd-level = <0xa82a5ffd>; 3817 opp-supported-hw = <0x03>; 3818 }; 3819 3820 opp-1375000000 { 3821 opp-hz = /bits/ 64 <1375000000>; 3822 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 3823 opp-peak-kBps = <16500000>; 3824 qcom,opp-acd-level = <0xa82a5ffd>; 3825 opp-supported-hw = <0x03>; 3826 }; 3827 3828 opp-1250000000 { 3829 opp-hz = /bits/ 64 <1250000000>; 3830 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 3831 opp-peak-kBps = <16500000>; 3832 qcom,opp-acd-level = <0xa82a5ffd>; 3833 opp-supported-hw = <0x07>; 3834 }; 3835 3836 opp-1175000000 { 3837 opp-hz = /bits/ 64 <1175000000>; 3838 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 3839 opp-peak-kBps = <14398438>; 3840 qcom,opp-acd-level = <0xa82a5ffd>; 3841 opp-supported-hw = <0x07>; 3842 }; 3843 3844 opp-1100000000-0 { 3845 opp-hz = /bits/ 64 <1100000000>; 3846 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3847 opp-peak-kBps = <14398438>; 3848 qcom,opp-acd-level = <0xa82a5ffd>; 3849 opp-supported-hw = <0x07>; 3850 }; 3851 3852 /* Only applicable for SKUs which has 1100Mhz as Fmax */ 3853 opp-1100000000-1 { 3854 opp-hz = /bits/ 64 <1100000000>; 3855 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3856 opp-peak-kBps = <16500000>; 3857 qcom,opp-acd-level = <0xa82a5ffd>; 3858 opp-supported-hw = <0x08>; 3859 }; 3860 3861 opp-1000000000 { 3862 opp-hz = /bits/ 64 <1000000000>; 3863 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3864 opp-peak-kBps = <14398438>; 3865 qcom,opp-acd-level = <0xa82b5ffd>; 3866 opp-supported-hw = <0x0f>; 3867 }; 3868 3869 opp-925000000 { 3870 opp-hz = /bits/ 64 <925000000>; 3871 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3872 opp-peak-kBps = <14398438>; 3873 qcom,opp-acd-level = <0xa82b5ffd>; 3874 opp-supported-hw = <0x0f>; 3875 }; 3876 3877 opp-800000000 { 3878 opp-hz = /bits/ 64 <800000000>; 3879 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3880 opp-peak-kBps = <12449219>; 3881 qcom,opp-acd-level = <0xa82c5ffd>; 3882 opp-supported-hw = <0x0f>; 3883 }; 3884 3885 opp-744000000 { 3886 opp-hz = /bits/ 64 <744000000>; 3887 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3888 opp-peak-kBps = <10687500>; 3889 qcom,opp-acd-level = <0x882e5ffd>; 3890 opp-supported-hw = <0x0f>; 3891 }; 3892 3893 opp-687000000-0 { 3894 opp-hz = /bits/ 64 <687000000>; 3895 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3896 opp-peak-kBps = <8171875>; 3897 qcom,opp-acd-level = <0x882e5ffd>; 3898 opp-supported-hw = <0x0f>; 3899 }; 3900 3901 /* Only applicable for SKUs which has 687Mhz as Fmax */ 3902 opp-687000000-1 { 3903 opp-hz = /bits/ 64 <687000000>; 3904 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3905 opp-peak-kBps = <16500000>; 3906 qcom,opp-acd-level = <0x882e5ffd>; 3907 opp-supported-hw = <0x10>; 3908 }; 3909 3910 opp-550000000 { 3911 opp-hz = /bits/ 64 <550000000>; 3912 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3913 opp-peak-kBps = <6074219>; 3914 qcom,opp-acd-level = <0xc0285ffd>; 3915 opp-supported-hw = <0x1f>; 3916 }; 3917 3918 opp-390000000 { 3919 opp-hz = /bits/ 64 <390000000>; 3920 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3921 opp-peak-kBps = <3000000>; 3922 qcom,opp-acd-level = <0xc0285ffd>; 3923 opp-supported-hw = <0x1f>; 3924 }; 3925 3926 opp-300000000 { 3927 opp-hz = /bits/ 64 <300000000>; 3928 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3929 opp-peak-kBps = <2136719>; 3930 qcom,opp-acd-level = <0xc02b5ffd>; 3931 opp-supported-hw = <0x1f>; 3932 }; 3933 }; 3934 }; 3935 3936 gmu: gmu@3d6a000 { 3937 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; 3938 reg = <0x0 0x03d6a000 0x0 0x35000>, 3939 <0x0 0x03d50000 0x0 0x10000>, 3940 <0x0 0x0b280000 0x0 0x10000>; 3941 reg-names = "gmu", "rscc", "gmu_pdc"; 3942 3943 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3944 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3945 interrupt-names = "hfi", "gmu"; 3946 3947 clocks = <&gpucc GPU_CC_AHB_CLK>, 3948 <&gpucc GPU_CC_CX_GMU_CLK>, 3949 <&gpucc GPU_CC_CXO_CLK>, 3950 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3951 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3952 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3953 <&gpucc GPU_CC_DEMET_CLK>; 3954 clock-names = "ahb", 3955 "gmu", 3956 "cxo", 3957 "axi", 3958 "memnoc", 3959 "hub", 3960 "demet"; 3961 3962 power-domains = <&gpucc GPU_CX_GDSC>, 3963 <&gpucc GPU_GX_GDSC>; 3964 power-domain-names = "cx", 3965 "gx"; 3966 3967 iommus = <&adreno_smmu 5 0x0>; 3968 3969 qcom,qmp = <&aoss_qmp>; 3970 3971 operating-points-v2 = <&gmu_opp_table>; 3972 3973 gmu_opp_table: opp-table { 3974 compatible = "operating-points-v2"; 3975 3976 opp-550000000 { 3977 opp-hz = /bits/ 64 <550000000>; 3978 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3979 }; 3980 3981 opp-220000000 { 3982 opp-hz = /bits/ 64 <220000000>; 3983 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3984 }; 3985 }; 3986 }; 3987 3988 gpucc: clock-controller@3d90000 { 3989 compatible = "qcom,x1e80100-gpucc"; 3990 reg = <0 0x03d90000 0 0xa000>; 3991 clocks = <&bi_tcxo_div2>, 3992 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, 3993 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; 3994 #clock-cells = <1>; 3995 #reset-cells = <1>; 3996 #power-domain-cells = <1>; 3997 }; 3998 3999 adreno_smmu: iommu@3da0000 { 4000 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu", 4001 "qcom,smmu-500", "arm,mmu-500"; 4002 reg = <0x0 0x03da0000 0x0 0x40000>; 4003 #iommu-cells = <2>; 4004 #global-interrupts = <1>; 4005 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 4006 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4007 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4008 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4009 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4010 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4011 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4012 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4013 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4014 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4015 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 4016 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 4017 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4018 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 4019 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 4020 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 4021 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 4022 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 4023 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, 4024 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 4025 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 4026 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 4027 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 4028 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 4029 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 4030 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 4031 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4032 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4033 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4034 <&gpucc GPU_CC_AHB_CLK>; 4035 clock-names = "hlos", 4036 "bus", 4037 "iface", 4038 "ahb"; 4039 power-domains = <&gpucc GPU_CX_GDSC>; 4040 dma-coherent; 4041 }; 4042 4043 gem_noc: interconnect@26400000 { 4044 compatible = "qcom,x1e80100-gem-noc"; 4045 reg = <0 0x26400000 0 0x311200>; 4046 4047 qcom,bcm-voters = <&apps_bcm_voter>; 4048 4049 #interconnect-cells = <2>; 4050 }; 4051 4052 nsp_noc: interconnect@320c0000 { 4053 compatible = "qcom,x1e80100-nsp-noc"; 4054 reg = <0 0x320C0000 0 0xe080>; 4055 4056 qcom,bcm-voters = <&apps_bcm_voter>; 4057 4058 #interconnect-cells = <2>; 4059 }; 4060 4061 remoteproc_adsp: remoteproc@6800000 { 4062 compatible = "qcom,x1e80100-adsp-pas"; 4063 reg = <0x0 0x06800000 0x0 0x10000>; 4064 4065 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4066 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4067 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4068 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4069 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4070 interrupt-names = "wdog", 4071 "fatal", 4072 "ready", 4073 "handover", 4074 "stop-ack"; 4075 4076 clocks = <&rpmhcc RPMH_CXO_CLK>; 4077 clock-names = "xo"; 4078 4079 power-domains = <&rpmhpd RPMHPD_LCX>, 4080 <&rpmhpd RPMHPD_LMX>; 4081 power-domain-names = "lcx", 4082 "lmx"; 4083 4084 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 4085 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4086 4087 memory-region = <&adspslpi_mem>, 4088 <&q6_adsp_dtb_mem>; 4089 4090 qcom,qmp = <&aoss_qmp>; 4091 4092 qcom,smem-states = <&smp2p_adsp_out 0>; 4093 qcom,smem-state-names = "stop"; 4094 4095 status = "disabled"; 4096 4097 glink-edge { 4098 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4099 IPCC_MPROC_SIGNAL_GLINK_QMP 4100 IRQ_TYPE_EDGE_RISING>; 4101 mboxes = <&ipcc IPCC_CLIENT_LPASS 4102 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4103 4104 label = "lpass"; 4105 qcom,remote-pid = <2>; 4106 4107 fastrpc { 4108 compatible = "qcom,fastrpc"; 4109 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4110 label = "adsp"; 4111 qcom,non-secure-domain; 4112 #address-cells = <1>; 4113 #size-cells = <0>; 4114 4115 compute-cb@3 { 4116 compatible = "qcom,fastrpc-compute-cb"; 4117 reg = <3>; 4118 iommus = <&apps_smmu 0x1003 0x80>, 4119 <&apps_smmu 0x1063 0x0>; 4120 dma-coherent; 4121 }; 4122 4123 compute-cb@4 { 4124 compatible = "qcom,fastrpc-compute-cb"; 4125 reg = <4>; 4126 iommus = <&apps_smmu 0x1004 0x80>, 4127 <&apps_smmu 0x1064 0x0>; 4128 dma-coherent; 4129 }; 4130 4131 compute-cb@5 { 4132 compatible = "qcom,fastrpc-compute-cb"; 4133 reg = <5>; 4134 iommus = <&apps_smmu 0x1005 0x80>, 4135 <&apps_smmu 0x1065 0x0>; 4136 dma-coherent; 4137 }; 4138 4139 compute-cb@6 { 4140 compatible = "qcom,fastrpc-compute-cb"; 4141 reg = <6>; 4142 iommus = <&apps_smmu 0x1006 0x80>, 4143 <&apps_smmu 0x1066 0x0>; 4144 dma-coherent; 4145 }; 4146 4147 compute-cb@7 { 4148 compatible = "qcom,fastrpc-compute-cb"; 4149 reg = <7>; 4150 iommus = <&apps_smmu 0x1007 0x80>, 4151 <&apps_smmu 0x1067 0x0>; 4152 dma-coherent; 4153 }; 4154 }; 4155 4156 gpr { 4157 compatible = "qcom,gpr"; 4158 qcom,glink-channels = "adsp_apps"; 4159 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4160 qcom,intents = <512 20>; 4161 #address-cells = <1>; 4162 #size-cells = <0>; 4163 4164 q6apm: service@1 { 4165 compatible = "qcom,q6apm"; 4166 reg = <GPR_APM_MODULE_IID>; 4167 #sound-dai-cells = <0>; 4168 qcom,protection-domain = "avs/audio", 4169 "msm/adsp/audio_pd"; 4170 4171 q6apmbedai: bedais { 4172 compatible = "qcom,q6apm-lpass-dais"; 4173 #sound-dai-cells = <1>; 4174 }; 4175 4176 q6apmdai: dais { 4177 compatible = "qcom,q6apm-dais"; 4178 iommus = <&apps_smmu 0x1001 0x80>, 4179 <&apps_smmu 0x1061 0x0>; 4180 }; 4181 }; 4182 4183 q6prm: service@2 { 4184 compatible = "qcom,q6prm"; 4185 reg = <GPR_PRM_MODULE_IID>; 4186 qcom,protection-domain = "avs/audio", 4187 "msm/adsp/audio_pd"; 4188 4189 q6prmcc: clock-controller { 4190 compatible = "qcom,q6prm-lpass-clocks"; 4191 #clock-cells = <2>; 4192 }; 4193 }; 4194 }; 4195 }; 4196 }; 4197 4198 lpass_wsa2macro: codec@6aa0000 { 4199 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4200 reg = <0 0x06aa0000 0 0x1000>; 4201 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4202 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4203 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4204 <&lpass_vamacro>; 4205 clock-names = "mclk", 4206 "macro", 4207 "dcodec", 4208 "fsgen"; 4209 4210 #clock-cells = <0>; 4211 clock-output-names = "wsa2-mclk"; 4212 #sound-dai-cells = <1>; 4213 sound-name-prefix = "WSA2"; 4214 }; 4215 4216 swr3: soundwire@6ab0000 { 4217 compatible = "qcom,soundwire-v2.0.0"; 4218 reg = <0 0x06ab0000 0 0x10000>; 4219 clocks = <&lpass_wsa2macro>; 4220 clock-names = "iface"; 4221 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 4222 label = "WSA2"; 4223 4224 pinctrl-0 = <&wsa2_swr_active>; 4225 pinctrl-names = "default"; 4226 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>; 4227 reset-names = "swr_audio_cgcr"; 4228 4229 qcom,din-ports = <4>; 4230 qcom,dout-ports = <9>; 4231 4232 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4233 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4234 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4235 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4236 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4237 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4238 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4239 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4240 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4241 4242 #address-cells = <2>; 4243 #size-cells = <0>; 4244 #sound-dai-cells = <1>; 4245 status = "disabled"; 4246 }; 4247 4248 lpass_rxmacro: codec@6ac0000 { 4249 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 4250 reg = <0 0x06ac0000 0 0x1000>; 4251 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4252 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4253 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4254 <&lpass_vamacro>; 4255 clock-names = "mclk", 4256 "macro", 4257 "dcodec", 4258 "fsgen"; 4259 4260 #clock-cells = <0>; 4261 clock-output-names = "mclk"; 4262 #sound-dai-cells = <1>; 4263 }; 4264 4265 swr1: soundwire@6ad0000 { 4266 compatible = "qcom,soundwire-v2.0.0"; 4267 reg = <0 0x06ad0000 0 0x10000>; 4268 clocks = <&lpass_rxmacro>; 4269 clock-names = "iface"; 4270 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 4271 label = "RX"; 4272 4273 pinctrl-0 = <&rx_swr_active>; 4274 pinctrl-names = "default"; 4275 4276 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 4277 reset-names = "swr_audio_cgcr"; 4278 qcom,din-ports = <1>; 4279 qcom,dout-ports = <11>; 4280 4281 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4282 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4283 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4284 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4285 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4286 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4287 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4288 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4289 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4290 4291 #address-cells = <2>; 4292 #size-cells = <0>; 4293 #sound-dai-cells = <1>; 4294 status = "disabled"; 4295 }; 4296 4297 lpass_txmacro: codec@6ae0000 { 4298 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 4299 reg = <0 0x06ae0000 0 0x1000>; 4300 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4301 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4302 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4303 <&lpass_vamacro>; 4304 clock-names = "mclk", 4305 "macro", 4306 "dcodec", 4307 "fsgen"; 4308 4309 #clock-cells = <0>; 4310 clock-output-names = "mclk"; 4311 #sound-dai-cells = <1>; 4312 }; 4313 4314 lpass_wsamacro: codec@6b00000 { 4315 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4316 reg = <0 0x06b00000 0 0x1000>; 4317 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4318 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4319 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4320 <&lpass_vamacro>; 4321 clock-names = "mclk", 4322 "macro", 4323 "dcodec", 4324 "fsgen"; 4325 4326 #clock-cells = <0>; 4327 clock-output-names = "mclk"; 4328 #sound-dai-cells = <1>; 4329 sound-name-prefix = "WSA"; 4330 }; 4331 4332 swr0: soundwire@6b10000 { 4333 compatible = "qcom,soundwire-v2.0.0"; 4334 reg = <0 0x06b10000 0 0x10000>; 4335 clocks = <&lpass_wsamacro>; 4336 clock-names = "iface"; 4337 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 4338 label = "WSA"; 4339 4340 pinctrl-0 = <&wsa_swr_active>; 4341 pinctrl-names = "default"; 4342 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 4343 reset-names = "swr_audio_cgcr"; 4344 4345 qcom,din-ports = <4>; 4346 qcom,dout-ports = <9>; 4347 4348 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4349 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4350 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4351 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4352 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4353 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4354 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4355 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4356 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4357 4358 #address-cells = <2>; 4359 #size-cells = <0>; 4360 #sound-dai-cells = <1>; 4361 status = "disabled"; 4362 }; 4363 4364 lpass_audiocc: clock-controller@6b6c000 { 4365 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc"; 4366 reg = <0 0x06b6c000 0 0x1000>; 4367 #clock-cells = <1>; 4368 #reset-cells = <1>; 4369 }; 4370 4371 swr2: soundwire@6d30000 { 4372 compatible = "qcom,soundwire-v2.0.0"; 4373 reg = <0 0x06d30000 0 0x10000>; 4374 clocks = <&lpass_txmacro>; 4375 clock-names = "iface"; 4376 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 4377 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 4378 interrupt-names = "core", "wakeup"; 4379 label = "TX"; 4380 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 4381 reset-names = "swr_audio_cgcr"; 4382 4383 pinctrl-0 = <&tx_swr_active>; 4384 pinctrl-names = "default"; 4385 4386 qcom,din-ports = <4>; 4387 qcom,dout-ports = <1>; 4388 4389 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; 4390 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; 4391 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; 4392 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4393 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4394 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4395 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4396 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4397 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; 4398 4399 #address-cells = <2>; 4400 #size-cells = <0>; 4401 #sound-dai-cells = <1>; 4402 status = "disabled"; 4403 }; 4404 4405 lpass_vamacro: codec@6d44000 { 4406 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 4407 reg = <0 0x06d44000 0 0x1000>; 4408 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4409 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4410 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4411 clock-names = "mclk", 4412 "macro", 4413 "dcodec"; 4414 4415 #clock-cells = <0>; 4416 clock-output-names = "fsgen"; 4417 #sound-dai-cells = <1>; 4418 }; 4419 4420 lpass_tlmm: pinctrl@6e80000 { 4421 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl"; 4422 reg = <0 0x06e80000 0 0x20000>, 4423 <0 0x07250000 0 0x10000>; 4424 4425 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4426 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4427 clock-names = "core", "audio"; 4428 4429 gpio-controller; 4430 #gpio-cells = <2>; 4431 gpio-ranges = <&lpass_tlmm 0 0 23>; 4432 4433 tx_swr_active: tx-swr-active-state { 4434 clk-pins { 4435 pins = "gpio0"; 4436 function = "swr_tx_clk"; 4437 drive-strength = <2>; 4438 slew-rate = <1>; 4439 bias-disable; 4440 }; 4441 4442 data-pins { 4443 pins = "gpio1", "gpio2"; 4444 function = "swr_tx_data"; 4445 drive-strength = <2>; 4446 slew-rate = <1>; 4447 bias-bus-hold; 4448 }; 4449 }; 4450 4451 rx_swr_active: rx-swr-active-state { 4452 clk-pins { 4453 pins = "gpio3"; 4454 function = "swr_rx_clk"; 4455 drive-strength = <2>; 4456 slew-rate = <1>; 4457 bias-disable; 4458 }; 4459 4460 data-pins { 4461 pins = "gpio4", "gpio5"; 4462 function = "swr_rx_data"; 4463 drive-strength = <2>; 4464 slew-rate = <1>; 4465 bias-bus-hold; 4466 }; 4467 }; 4468 4469 dmic01_default: dmic01-default-state { 4470 clk-pins { 4471 pins = "gpio6"; 4472 function = "dmic1_clk"; 4473 drive-strength = <8>; 4474 output-high; 4475 }; 4476 4477 data-pins { 4478 pins = "gpio7"; 4479 function = "dmic1_data"; 4480 drive-strength = <8>; 4481 input-enable; 4482 }; 4483 }; 4484 4485 dmic23_default: dmic23-default-state { 4486 clk-pins { 4487 pins = "gpio8"; 4488 function = "dmic2_clk"; 4489 drive-strength = <8>; 4490 output-high; 4491 }; 4492 4493 data-pins { 4494 pins = "gpio9"; 4495 function = "dmic2_data"; 4496 drive-strength = <8>; 4497 input-enable; 4498 }; 4499 }; 4500 4501 wsa_swr_active: wsa-swr-active-state { 4502 clk-pins { 4503 pins = "gpio10"; 4504 function = "wsa_swr_clk"; 4505 drive-strength = <2>; 4506 slew-rate = <1>; 4507 bias-disable; 4508 }; 4509 4510 data-pins { 4511 pins = "gpio11"; 4512 function = "wsa_swr_data"; 4513 drive-strength = <2>; 4514 slew-rate = <1>; 4515 bias-bus-hold; 4516 }; 4517 }; 4518 4519 wsa2_swr_active: wsa2-swr-active-state { 4520 clk-pins { 4521 pins = "gpio15"; 4522 function = "wsa2_swr_clk"; 4523 drive-strength = <2>; 4524 slew-rate = <1>; 4525 bias-disable; 4526 }; 4527 4528 data-pins { 4529 pins = "gpio16"; 4530 function = "wsa2_swr_data"; 4531 drive-strength = <2>; 4532 slew-rate = <1>; 4533 bias-bus-hold; 4534 }; 4535 }; 4536 }; 4537 4538 lpasscc: clock-controller@6ea0000 { 4539 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc"; 4540 reg = <0 0x06ea0000 0 0x12000>; 4541 #clock-cells = <1>; 4542 #reset-cells = <1>; 4543 }; 4544 4545 lpass_ag_noc: interconnect@7e40000 { 4546 compatible = "qcom,x1e80100-lpass-ag-noc"; 4547 reg = <0 0x07e40000 0 0xe080>; 4548 4549 qcom,bcm-voters = <&apps_bcm_voter>; 4550 4551 #interconnect-cells = <2>; 4552 }; 4553 4554 lpass_lpiaon_noc: interconnect@7400000 { 4555 compatible = "qcom,x1e80100-lpass-lpiaon-noc"; 4556 reg = <0 0x07400000 0 0x19080>; 4557 4558 qcom,bcm-voters = <&apps_bcm_voter>; 4559 4560 #interconnect-cells = <2>; 4561 }; 4562 4563 lpass_lpicx_noc: interconnect@7430000 { 4564 compatible = "qcom,x1e80100-lpass-lpicx-noc"; 4565 reg = <0 0x07430000 0 0x3A200>; 4566 4567 qcom,bcm-voters = <&apps_bcm_voter>; 4568 4569 #interconnect-cells = <2>; 4570 }; 4571 4572 sdhc_2: mmc@8804000 { 4573 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4574 reg = <0 0x08804000 0 0x1000>; 4575 4576 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4577 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4578 interrupt-names = "hc_irq", "pwr_irq"; 4579 4580 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4581 <&gcc GCC_SDCC2_APPS_CLK>, 4582 <&rpmhcc RPMH_CXO_CLK>; 4583 clock-names = "iface", "core", "xo"; 4584 iommus = <&apps_smmu 0x520 0>; 4585 qcom,dll-config = <0x0007642c>; 4586 qcom,ddr-config = <0x80040868>; 4587 power-domains = <&rpmhpd RPMHPD_CX>; 4588 operating-points-v2 = <&sdhc2_opp_table>; 4589 4590 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 4591 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4592 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4593 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4594 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4595 bus-width = <4>; 4596 dma-coherent; 4597 4598 status = "disabled"; 4599 4600 sdhc2_opp_table: opp-table { 4601 compatible = "operating-points-v2"; 4602 4603 opp-19200000 { 4604 opp-hz = /bits/ 64 <19200000>; 4605 required-opps = <&rpmhpd_opp_min_svs>; 4606 }; 4607 4608 opp-50000000 { 4609 opp-hz = /bits/ 64 <50000000>; 4610 required-opps = <&rpmhpd_opp_low_svs>; 4611 }; 4612 4613 opp-100000000 { 4614 opp-hz = /bits/ 64 <100000000>; 4615 required-opps = <&rpmhpd_opp_svs>; 4616 }; 4617 4618 opp-202000000 { 4619 opp-hz = /bits/ 64 <202000000>; 4620 required-opps = <&rpmhpd_opp_svs_l1>; 4621 }; 4622 }; 4623 }; 4624 4625 sdhc_4: mmc@8844000 { 4626 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4627 reg = <0 0x08844000 0 0x1000>; 4628 4629 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4630 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 4631 interrupt-names = "hc_irq", "pwr_irq"; 4632 4633 clocks = <&gcc GCC_SDCC4_AHB_CLK>, 4634 <&gcc GCC_SDCC4_APPS_CLK>, 4635 <&rpmhcc RPMH_CXO_CLK>; 4636 clock-names = "iface", "core", "xo"; 4637 iommus = <&apps_smmu 0x160 0>; 4638 qcom,dll-config = <0x0007642c>; 4639 qcom,ddr-config = <0x80040868>; 4640 power-domains = <&rpmhpd RPMHPD_CX>; 4641 operating-points-v2 = <&sdhc4_opp_table>; 4642 4643 interconnects = <&aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS 4644 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4645 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4646 &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 4647 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4648 bus-width = <4>; 4649 dma-coherent; 4650 4651 status = "disabled"; 4652 4653 sdhc4_opp_table: opp-table { 4654 compatible = "operating-points-v2"; 4655 4656 opp-19200000 { 4657 opp-hz = /bits/ 64 <19200000>; 4658 required-opps = <&rpmhpd_opp_min_svs>; 4659 }; 4660 4661 opp-50000000 { 4662 opp-hz = /bits/ 64 <50000000>; 4663 required-opps = <&rpmhpd_opp_low_svs>; 4664 }; 4665 4666 opp-100000000 { 4667 opp-hz = /bits/ 64 <100000000>; 4668 required-opps = <&rpmhpd_opp_svs>; 4669 }; 4670 4671 opp-202000000 { 4672 opp-hz = /bits/ 64 <202000000>; 4673 required-opps = <&rpmhpd_opp_svs_l1>; 4674 }; 4675 }; 4676 }; 4677 4678 usb_2_hsphy: phy@88e0000 { 4679 compatible = "qcom,x1e80100-snps-eusb2-phy", 4680 "qcom,sm8550-snps-eusb2-phy"; 4681 reg = <0 0x088e0000 0 0x154>; 4682 #phy-cells = <0>; 4683 4684 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 4685 clock-names = "ref"; 4686 4687 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 4688 4689 status = "disabled"; 4690 }; 4691 4692 usb_mp_hsphy0: phy@88e1000 { 4693 compatible = "qcom,x1e80100-snps-eusb2-phy", 4694 "qcom,sm8550-snps-eusb2-phy"; 4695 reg = <0 0x088e1000 0 0x154>; 4696 #phy-cells = <0>; 4697 4698 clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>; 4699 clock-names = "ref"; 4700 4701 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 4702 4703 status = "disabled"; 4704 }; 4705 4706 usb_mp_hsphy1: phy@88e2000 { 4707 compatible = "qcom,x1e80100-snps-eusb2-phy", 4708 "qcom,sm8550-snps-eusb2-phy"; 4709 reg = <0 0x088e2000 0 0x154>; 4710 #phy-cells = <0>; 4711 4712 clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>; 4713 clock-names = "ref"; 4714 4715 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 4716 4717 status = "disabled"; 4718 }; 4719 4720 usb_mp_qmpphy0: phy@88e3000 { 4721 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4722 reg = <0 0x088e3000 0 0x2000>; 4723 4724 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4725 <&rpmhcc RPMH_CXO_CLK>, 4726 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4727 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 4728 clock-names = "aux", 4729 "ref", 4730 "com_aux", 4731 "pipe"; 4732 4733 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 4734 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 4735 reset-names = "phy", 4736 "phy_phy"; 4737 4738 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 4739 4740 #clock-cells = <0>; 4741 clock-output-names = "usb_mp_phy0_pipe_clk"; 4742 4743 #phy-cells = <0>; 4744 4745 status = "disabled"; 4746 }; 4747 4748 usb_mp_qmpphy1: phy@88e5000 { 4749 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4750 reg = <0 0x088e5000 0 0x2000>; 4751 4752 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4753 <&rpmhcc RPMH_CXO_CLK>, 4754 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4755 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 4756 clock-names = "aux", 4757 "ref", 4758 "com_aux", 4759 "pipe"; 4760 4761 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 4762 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 4763 reset-names = "phy", 4764 "phy_phy"; 4765 4766 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 4767 4768 #clock-cells = <0>; 4769 clock-output-names = "usb_mp_phy1_pipe_clk"; 4770 4771 #phy-cells = <0>; 4772 4773 status = "disabled"; 4774 }; 4775 4776 usb_1_ss2: usb@a0f8800 { 4777 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4778 reg = <0 0x0a0f8800 0 0x400>; 4779 4780 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 4781 <&gcc GCC_USB30_TERT_MASTER_CLK>, 4782 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 4783 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 4784 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4785 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4786 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4787 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4788 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4789 clock-names = "cfg_noc", 4790 "core", 4791 "iface", 4792 "sleep", 4793 "mock_utmi", 4794 "noc_aggr", 4795 "noc_aggr_north", 4796 "noc_aggr_south", 4797 "noc_sys"; 4798 4799 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4800 <&gcc GCC_USB30_TERT_MASTER_CLK>; 4801 assigned-clock-rates = <19200000>, 4802 <200000000>; 4803 4804 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 4805 <&pdc 58 IRQ_TYPE_EDGE_BOTH>, 4806 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 4807 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; 4808 interrupt-names = "pwr_event", 4809 "dp_hs_phy_irq", 4810 "dm_hs_phy_irq", 4811 "ss_phy_irq"; 4812 4813 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 4814 required-opps = <&rpmhpd_opp_nom>; 4815 4816 resets = <&gcc GCC_USB30_TERT_BCR>; 4817 4818 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS 4819 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4820 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4821 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4822 interconnect-names = "usb-ddr", 4823 "apps-usb"; 4824 4825 wakeup-source; 4826 4827 #address-cells = <2>; 4828 #size-cells = <2>; 4829 ranges; 4830 4831 status = "disabled"; 4832 4833 usb_1_ss2_dwc3: usb@a000000 { 4834 compatible = "snps,dwc3"; 4835 reg = <0 0x0a000000 0 0xcd00>; 4836 4837 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 4838 4839 iommus = <&apps_smmu 0x14a0 0x0>; 4840 4841 phys = <&usb_1_ss2_hsphy>, 4842 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; 4843 phy-names = "usb2-phy", 4844 "usb3-phy"; 4845 4846 snps,dis_u2_susphy_quirk; 4847 snps,dis_enblslpm_quirk; 4848 snps,usb3_lpm_capable; 4849 snps,dis-u1-entry-quirk; 4850 snps,dis-u2-entry-quirk; 4851 4852 dma-coherent; 4853 4854 ports { 4855 #address-cells = <1>; 4856 #size-cells = <0>; 4857 4858 port@0 { 4859 reg = <0>; 4860 4861 usb_1_ss2_dwc3_hs: endpoint { 4862 }; 4863 }; 4864 4865 port@1 { 4866 reg = <1>; 4867 4868 usb_1_ss2_dwc3_ss: endpoint { 4869 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; 4870 }; 4871 }; 4872 }; 4873 }; 4874 }; 4875 4876 usb_2: usb@a2f8800 { 4877 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4878 reg = <0 0x0a2f8800 0 0x400>; 4879 #address-cells = <2>; 4880 #size-cells = <2>; 4881 ranges; 4882 4883 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4884 <&gcc GCC_USB20_MASTER_CLK>, 4885 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4886 <&gcc GCC_USB20_SLEEP_CLK>, 4887 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4888 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4889 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4890 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4891 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4892 clock-names = "cfg_noc", 4893 "core", 4894 "iface", 4895 "sleep", 4896 "mock_utmi", 4897 "noc_aggr", 4898 "noc_aggr_north", 4899 "noc_aggr_south", 4900 "noc_sys"; 4901 4902 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4903 <&gcc GCC_USB20_MASTER_CLK>; 4904 assigned-clock-rates = <19200000>, <200000000>; 4905 4906 interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 4907 <&pdc 50 IRQ_TYPE_EDGE_BOTH>, 4908 <&pdc 49 IRQ_TYPE_EDGE_BOTH>; 4909 interrupt-names = "pwr_event", 4910 "dp_hs_phy_irq", 4911 "dm_hs_phy_irq"; 4912 4913 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4914 required-opps = <&rpmhpd_opp_nom>; 4915 4916 resets = <&gcc GCC_USB20_PRIM_BCR>; 4917 4918 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4919 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4920 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4921 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4922 interconnect-names = "usb-ddr", 4923 "apps-usb"; 4924 4925 wakeup-source; 4926 4927 status = "disabled"; 4928 4929 usb_2_dwc3: usb@a200000 { 4930 compatible = "snps,dwc3"; 4931 reg = <0 0x0a200000 0 0xcd00>; 4932 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 4933 iommus = <&apps_smmu 0x14e0 0x0>; 4934 phys = <&usb_2_hsphy>; 4935 phy-names = "usb2-phy"; 4936 maximum-speed = "high-speed"; 4937 snps,dis-u1-entry-quirk; 4938 snps,dis-u2-entry-quirk; 4939 4940 dma-coherent; 4941 4942 ports { 4943 #address-cells = <1>; 4944 #size-cells = <0>; 4945 4946 port@0 { 4947 reg = <0>; 4948 4949 usb_2_dwc3_hs: endpoint { 4950 }; 4951 }; 4952 }; 4953 }; 4954 }; 4955 4956 usb_mp: usb@a4f8800 { 4957 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3"; 4958 reg = <0 0x0a4f8800 0 0x400>; 4959 4960 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 4961 <&gcc GCC_USB30_MP_MASTER_CLK>, 4962 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 4963 <&gcc GCC_USB30_MP_SLEEP_CLK>, 4964 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4965 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4966 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4967 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4968 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4969 clock-names = "cfg_noc", 4970 "core", 4971 "iface", 4972 "sleep", 4973 "mock_utmi", 4974 "noc_aggr", 4975 "noc_aggr_north", 4976 "noc_aggr_south", 4977 "noc_sys"; 4978 4979 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4980 <&gcc GCC_USB30_MP_MASTER_CLK>; 4981 assigned-clock-rates = <19200000>, 4982 <200000000>; 4983 4984 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 4985 <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 4986 <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 4987 <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 4988 <&pdc 52 IRQ_TYPE_EDGE_BOTH>, 4989 <&pdc 51 IRQ_TYPE_EDGE_BOTH>, 4990 <&pdc 54 IRQ_TYPE_EDGE_BOTH>, 4991 <&pdc 53 IRQ_TYPE_EDGE_BOTH>, 4992 <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, 4993 <&pdc 56 IRQ_TYPE_LEVEL_HIGH>; 4994 interrupt-names = "pwr_event_1", "pwr_event_2", 4995 "hs_phy_1", "hs_phy_2", 4996 "dp_hs_phy_1", "dm_hs_phy_1", 4997 "dp_hs_phy_2", "dm_hs_phy_2", 4998 "ss_phy_1", "ss_phy_2"; 4999 5000 power-domains = <&gcc GCC_USB30_MP_GDSC>; 5001 required-opps = <&rpmhpd_opp_nom>; 5002 5003 resets = <&gcc GCC_USB30_MP_BCR>; 5004 5005 interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS 5006 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5007 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5008 &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ACTIVE_ONLY>; 5009 interconnect-names = "usb-ddr", 5010 "apps-usb"; 5011 5012 wakeup-source; 5013 5014 #address-cells = <2>; 5015 #size-cells = <2>; 5016 ranges; 5017 5018 status = "disabled"; 5019 5020 usb_mp_dwc3: usb@a400000 { 5021 compatible = "snps,dwc3"; 5022 reg = <0 0x0a400000 0 0xcd00>; 5023 5024 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 5025 5026 iommus = <&apps_smmu 0x1400 0x0>; 5027 5028 phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>, 5029 <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>; 5030 phy-names = "usb2-0", "usb3-0", 5031 "usb2-1", "usb3-1"; 5032 dr_mode = "host"; 5033 5034 snps,dis_u2_susphy_quirk; 5035 snps,dis_enblslpm_quirk; 5036 snps,usb3_lpm_capable; 5037 snps,dis-u1-entry-quirk; 5038 snps,dis-u2-entry-quirk; 5039 5040 dma-coherent; 5041 }; 5042 }; 5043 5044 usb_1_ss0: usb@a6f8800 { 5045 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 5046 reg = <0 0x0a6f8800 0 0x400>; 5047 5048 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5049 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5050 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5051 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5052 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5053 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5054 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>, 5055 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>, 5056 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5057 clock-names = "cfg_noc", 5058 "core", 5059 "iface", 5060 "sleep", 5061 "mock_utmi", 5062 "noc_aggr", 5063 "noc_aggr_north", 5064 "noc_aggr_south", 5065 "noc_sys"; 5066 5067 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5068 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5069 assigned-clock-rates = <19200000>, 5070 <200000000>; 5071 5072 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 5073 <&pdc 61 IRQ_TYPE_EDGE_BOTH>, 5074 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 5075 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 5076 interrupt-names = "pwr_event", 5077 "dp_hs_phy_irq", 5078 "dm_hs_phy_irq", 5079 "ss_phy_irq"; 5080 5081 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 5082 required-opps = <&rpmhpd_opp_nom>; 5083 5084 resets = <&gcc GCC_USB30_PRIM_BCR>; 5085 5086 wakeup-source; 5087 5088 #address-cells = <2>; 5089 #size-cells = <2>; 5090 ranges; 5091 5092 status = "disabled"; 5093 5094 usb_1_ss0_dwc3: usb@a600000 { 5095 compatible = "snps,dwc3"; 5096 reg = <0 0x0a600000 0 0xcd00>; 5097 5098 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 5099 5100 iommus = <&apps_smmu 0x1420 0x0>; 5101 5102 phys = <&usb_1_ss0_hsphy>, 5103 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; 5104 phy-names = "usb2-phy", 5105 "usb3-phy"; 5106 5107 snps,dis_u2_susphy_quirk; 5108 snps,dis_enblslpm_quirk; 5109 snps,usb3_lpm_capable; 5110 snps,dis-u1-entry-quirk; 5111 snps,dis-u2-entry-quirk; 5112 5113 dma-coherent; 5114 5115 ports { 5116 #address-cells = <1>; 5117 #size-cells = <0>; 5118 5119 port@0 { 5120 reg = <0>; 5121 5122 usb_1_ss0_dwc3_hs: endpoint { 5123 }; 5124 }; 5125 5126 port@1 { 5127 reg = <1>; 5128 5129 usb_1_ss0_dwc3_ss: endpoint { 5130 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; 5131 }; 5132 }; 5133 }; 5134 }; 5135 }; 5136 5137 usb_1_ss1: usb@a8f8800 { 5138 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 5139 reg = <0 0x0a8f8800 0 0x400>; 5140 5141 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 5142 <&gcc GCC_USB30_SEC_MASTER_CLK>, 5143 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 5144 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 5145 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5146 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5147 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5148 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5149 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5150 clock-names = "cfg_noc", 5151 "core", 5152 "iface", 5153 "sleep", 5154 "mock_utmi", 5155 "noc_aggr", 5156 "noc_aggr_north", 5157 "noc_aggr_south", 5158 "noc_sys"; 5159 5160 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5161 <&gcc GCC_USB30_SEC_MASTER_CLK>; 5162 assigned-clock-rates = <19200000>, 5163 <200000000>; 5164 5165 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 5166 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 5167 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 5168 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; 5169 interrupt-names = "pwr_event", 5170 "dp_hs_phy_irq", 5171 "dm_hs_phy_irq", 5172 "ss_phy_irq"; 5173 5174 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 5175 required-opps = <&rpmhpd_opp_nom>; 5176 5177 resets = <&gcc GCC_USB30_SEC_BCR>; 5178 5179 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS 5180 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5181 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5182 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5183 interconnect-names = "usb-ddr", 5184 "apps-usb"; 5185 5186 wakeup-source; 5187 5188 #address-cells = <2>; 5189 #size-cells = <2>; 5190 ranges; 5191 5192 status = "disabled"; 5193 5194 usb_1_ss1_dwc3: usb@a800000 { 5195 compatible = "snps,dwc3"; 5196 reg = <0 0x0a800000 0 0xcd00>; 5197 5198 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 5199 5200 iommus = <&apps_smmu 0x1460 0x0>; 5201 5202 phys = <&usb_1_ss1_hsphy>, 5203 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; 5204 phy-names = "usb2-phy", 5205 "usb3-phy"; 5206 5207 snps,dis_u2_susphy_quirk; 5208 snps,dis_enblslpm_quirk; 5209 snps,usb3_lpm_capable; 5210 snps,dis-u1-entry-quirk; 5211 snps,dis-u2-entry-quirk; 5212 5213 dma-coherent; 5214 5215 ports { 5216 #address-cells = <1>; 5217 #size-cells = <0>; 5218 5219 port@0 { 5220 reg = <0>; 5221 5222 usb_1_ss1_dwc3_hs: endpoint { 5223 }; 5224 }; 5225 5226 port@1 { 5227 reg = <1>; 5228 5229 usb_1_ss1_dwc3_ss: endpoint { 5230 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; 5231 }; 5232 }; 5233 }; 5234 }; 5235 }; 5236 5237 iris: video-codec@aa00000 { 5238 compatible = "qcom,x1e80100-iris", "qcom,sm8550-iris"; 5239 5240 reg = <0 0x0aa00000 0 0xf0000>; 5241 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 5242 5243 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 5244 <&videocc VIDEO_CC_MVS0_GDSC>, 5245 <&rpmhpd RPMHPD_MXC>, 5246 <&rpmhpd RPMHPD_MMCX>; 5247 power-domain-names = "venus", 5248 "vcodec0", 5249 "mxc", 5250 "mmcx"; 5251 operating-points-v2 = <&iris_opp_table>; 5252 5253 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 5254 <&videocc VIDEO_CC_MVS0C_CLK>, 5255 <&videocc VIDEO_CC_MVS0_CLK>; 5256 clock-names = "iface", 5257 "core", 5258 "vcodec0_core"; 5259 5260 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5261 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5262 <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS 5263 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5264 interconnect-names = "cpu-cfg", 5265 "video-mem"; 5266 5267 memory-region = <&video_mem>; 5268 5269 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 5270 reset-names = "bus"; 5271 5272 iommus = <&apps_smmu 0x1940 0>, 5273 <&apps_smmu 0x1947 0>; 5274 dma-coherent; 5275 5276 /* 5277 * IRIS firmware is signed by vendors, only 5278 * enable on boards where the proper signed firmware 5279 * is available. 5280 */ 5281 status = "disabled"; 5282 5283 iris_opp_table: opp-table { 5284 compatible = "operating-points-v2"; 5285 5286 opp-192000000 { 5287 opp-hz = /bits/ 64 <192000000>; 5288 required-opps = <&rpmhpd_opp_low_svs_d1>, 5289 <&rpmhpd_opp_low_svs_d1>; 5290 }; 5291 5292 opp-240000000 { 5293 opp-hz = /bits/ 64 <240000000>; 5294 required-opps = <&rpmhpd_opp_svs>, 5295 <&rpmhpd_opp_low_svs>; 5296 }; 5297 5298 opp-338000000 { 5299 opp-hz = /bits/ 64 <338000000>; 5300 required-opps = <&rpmhpd_opp_svs>, 5301 <&rpmhpd_opp_svs>; 5302 }; 5303 5304 opp-366000000 { 5305 opp-hz = /bits/ 64 <366000000>; 5306 required-opps = <&rpmhpd_opp_svs_l1>, 5307 <&rpmhpd_opp_svs_l1>; 5308 }; 5309 5310 opp-444000000 { 5311 opp-hz = /bits/ 64 <444000000>; 5312 required-opps = <&rpmhpd_opp_nom>, 5313 <&rpmhpd_opp_nom>; 5314 }; 5315 5316 opp-481000000 { 5317 opp-hz = /bits/ 64 <481000000>; 5318 required-opps = <&rpmhpd_opp_turbo>, 5319 <&rpmhpd_opp_turbo>; 5320 }; 5321 }; 5322 }; 5323 5324 videocc: clock-controller@aaf0000 { 5325 compatible = "qcom,x1e80100-videocc"; 5326 reg = <0 0x0aaf0000 0 0x10000>; 5327 clocks = <&bi_tcxo_div2>, 5328 <&gcc GCC_VIDEO_AHB_CLK>; 5329 power-domains = <&rpmhpd RPMHPD_MMCX>, 5330 <&rpmhpd RPMHPD_MXC>; 5331 required-opps = <&rpmhpd_opp_low_svs>, 5332 <&rpmhpd_opp_low_svs>; 5333 #clock-cells = <1>; 5334 #reset-cells = <1>; 5335 #power-domain-cells = <1>; 5336 }; 5337 5338 mdss: display-subsystem@ae00000 { 5339 compatible = "qcom,x1e80100-mdss"; 5340 reg = <0 0x0ae00000 0 0x1000>; 5341 reg-names = "mdss"; 5342 5343 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 5344 5345 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5346 <&gcc GCC_DISP_HF_AXI_CLK>, 5347 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5348 5349 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5350 5351 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 5352 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 5353 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 5354 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5355 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5356 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5357 interconnect-names = "mdp0-mem", 5358 "mdp1-mem", 5359 "cpu-cfg"; 5360 5361 power-domains = <&dispcc MDSS_GDSC>; 5362 5363 iommus = <&apps_smmu 0x1c00 0x2>; 5364 5365 interrupt-controller; 5366 #interrupt-cells = <1>; 5367 5368 #address-cells = <2>; 5369 #size-cells = <2>; 5370 ranges; 5371 5372 status = "disabled"; 5373 5374 mdss_mdp: display-controller@ae01000 { 5375 compatible = "qcom,x1e80100-dpu"; 5376 reg = <0 0x0ae01000 0 0x8f000>, 5377 <0 0x0aeb0000 0 0x2008>; 5378 reg-names = "mdp", 5379 "vbif"; 5380 5381 interrupts-extended = <&mdss 0>; 5382 5383 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5384 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5385 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5386 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5387 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5388 clock-names = "nrt_bus", 5389 "iface", 5390 "lut", 5391 "core", 5392 "vsync"; 5393 5394 operating-points-v2 = <&mdp_opp_table>; 5395 5396 power-domains = <&rpmhpd RPMHPD_MMCX>; 5397 5398 ports { 5399 #address-cells = <1>; 5400 #size-cells = <0>; 5401 5402 port@0 { 5403 reg = <0>; 5404 5405 mdss_intf0_out: endpoint { 5406 remote-endpoint = <&mdss_dp0_in>; 5407 }; 5408 }; 5409 5410 port@4 { 5411 reg = <4>; 5412 5413 mdss_intf4_out: endpoint { 5414 remote-endpoint = <&mdss_dp1_in>; 5415 }; 5416 }; 5417 5418 port@5 { 5419 reg = <5>; 5420 5421 mdss_intf5_out: endpoint { 5422 remote-endpoint = <&mdss_dp3_in>; 5423 }; 5424 }; 5425 5426 port@6 { 5427 reg = <6>; 5428 5429 mdss_intf6_out: endpoint { 5430 remote-endpoint = <&mdss_dp2_in>; 5431 }; 5432 }; 5433 }; 5434 5435 mdp_opp_table: opp-table { 5436 compatible = "operating-points-v2"; 5437 5438 opp-200000000 { 5439 opp-hz = /bits/ 64 <200000000>; 5440 required-opps = <&rpmhpd_opp_low_svs>; 5441 }; 5442 5443 opp-325000000 { 5444 opp-hz = /bits/ 64 <325000000>; 5445 required-opps = <&rpmhpd_opp_svs>; 5446 }; 5447 5448 opp-375000000 { 5449 opp-hz = /bits/ 64 <375000000>; 5450 required-opps = <&rpmhpd_opp_svs_l1>; 5451 }; 5452 5453 opp-514000000 { 5454 opp-hz = /bits/ 64 <514000000>; 5455 required-opps = <&rpmhpd_opp_nom>; 5456 }; 5457 5458 opp-575000000 { 5459 opp-hz = /bits/ 64 <575000000>; 5460 required-opps = <&rpmhpd_opp_nom_l1>; 5461 }; 5462 }; 5463 }; 5464 5465 mdss_dp0: displayport-controller@ae90000 { 5466 compatible = "qcom,x1e80100-dp"; 5467 reg = <0 0x0ae90000 0 0x200>, 5468 <0 0x0ae90200 0 0x200>, 5469 <0 0x0ae90400 0 0x600>, 5470 <0 0x0ae91000 0 0x400>, 5471 <0 0x0ae91400 0 0x400>; 5472 5473 interrupts-extended = <&mdss 12>; 5474 5475 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5476 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 5477 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 5478 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5479 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5480 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 5481 clock-names = "core_iface", 5482 "core_aux", 5483 "ctrl_link", 5484 "ctrl_link_iface", 5485 "stream_pixel", 5486 "stream_1_pixel"; 5487 5488 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5489 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5490 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 5491 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5492 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5493 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5494 5495 operating-points-v2 = <&mdss_dp0_opp_table>; 5496 5497 power-domains = <&rpmhpd RPMHPD_MMCX>; 5498 5499 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; 5500 phy-names = "dp"; 5501 5502 #sound-dai-cells = <0>; 5503 5504 status = "disabled"; 5505 5506 ports { 5507 #address-cells = <1>; 5508 #size-cells = <0>; 5509 5510 port@0 { 5511 reg = <0>; 5512 5513 mdss_dp0_in: endpoint { 5514 remote-endpoint = <&mdss_intf0_out>; 5515 }; 5516 }; 5517 5518 port@1 { 5519 reg = <1>; 5520 5521 mdss_dp0_out: endpoint { 5522 data-lanes = <0 1 2 3>; 5523 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; 5524 }; 5525 }; 5526 }; 5527 5528 mdss_dp0_opp_table: opp-table { 5529 compatible = "operating-points-v2"; 5530 5531 opp-160000000 { 5532 opp-hz = /bits/ 64 <160000000>; 5533 required-opps = <&rpmhpd_opp_low_svs>; 5534 }; 5535 5536 opp-270000000 { 5537 opp-hz = /bits/ 64 <270000000>; 5538 required-opps = <&rpmhpd_opp_svs>; 5539 }; 5540 5541 opp-540000000 { 5542 opp-hz = /bits/ 64 <540000000>; 5543 required-opps = <&rpmhpd_opp_svs_l1>; 5544 }; 5545 5546 opp-810000000 { 5547 opp-hz = /bits/ 64 <810000000>; 5548 required-opps = <&rpmhpd_opp_nom>; 5549 }; 5550 }; 5551 }; 5552 5553 mdss_dp1: displayport-controller@ae98000 { 5554 compatible = "qcom,x1e80100-dp"; 5555 reg = <0 0x0ae98000 0 0x200>, 5556 <0 0x0ae98200 0 0x200>, 5557 <0 0x0ae98400 0 0x600>, 5558 <0 0x0ae99000 0 0x400>, 5559 <0 0x0ae99400 0 0x400>; 5560 5561 interrupts-extended = <&mdss 13>; 5562 5563 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5564 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 5565 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 5566 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5567 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5568 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5569 clock-names = "core_iface", 5570 "core_aux", 5571 "ctrl_link", 5572 "ctrl_link_iface", 5573 "stream_pixel", 5574 "stream_1_pixel"; 5575 5576 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5577 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5578 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5579 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5580 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5581 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5582 5583 operating-points-v2 = <&mdss_dp1_opp_table>; 5584 5585 power-domains = <&rpmhpd RPMHPD_MMCX>; 5586 5587 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; 5588 phy-names = "dp"; 5589 5590 #sound-dai-cells = <0>; 5591 5592 status = "disabled"; 5593 5594 ports { 5595 #address-cells = <1>; 5596 #size-cells = <0>; 5597 5598 port@0 { 5599 reg = <0>; 5600 5601 mdss_dp1_in: endpoint { 5602 remote-endpoint = <&mdss_intf4_out>; 5603 }; 5604 }; 5605 5606 port@1 { 5607 reg = <1>; 5608 5609 mdss_dp1_out: endpoint { 5610 data-lanes = <0 1 2 3>; 5611 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; 5612 }; 5613 }; 5614 }; 5615 5616 mdss_dp1_opp_table: opp-table { 5617 compatible = "operating-points-v2"; 5618 5619 opp-160000000 { 5620 opp-hz = /bits/ 64 <160000000>; 5621 required-opps = <&rpmhpd_opp_low_svs>; 5622 }; 5623 5624 opp-270000000 { 5625 opp-hz = /bits/ 64 <270000000>; 5626 required-opps = <&rpmhpd_opp_svs>; 5627 }; 5628 5629 opp-540000000 { 5630 opp-hz = /bits/ 64 <540000000>; 5631 required-opps = <&rpmhpd_opp_svs_l1>; 5632 }; 5633 5634 opp-810000000 { 5635 opp-hz = /bits/ 64 <810000000>; 5636 required-opps = <&rpmhpd_opp_nom>; 5637 }; 5638 }; 5639 }; 5640 5641 mdss_dp2: displayport-controller@ae9a000 { 5642 compatible = "qcom,x1e80100-dp"; 5643 reg = <0 0x0ae9a000 0 0x200>, 5644 <0 0x0ae9a200 0 0x200>, 5645 <0 0x0ae9a400 0 0x600>, 5646 <0 0x0ae9b000 0 0x400>, 5647 <0 0x0ae9b400 0 0x400>; 5648 5649 interrupts-extended = <&mdss 14>; 5650 5651 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5652 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5653 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 5654 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5655 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 5656 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 5657 clock-names = "core_iface", 5658 "core_aux", 5659 "ctrl_link", 5660 "ctrl_link_iface", 5661 "stream_pixel", 5662 "stream_1_pixel"; 5663 5664 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5665 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 5666 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 5667 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5668 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5669 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5670 5671 operating-points-v2 = <&mdss_dp2_opp_table>; 5672 5673 power-domains = <&rpmhpd RPMHPD_MMCX>; 5674 5675 phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>; 5676 phy-names = "dp"; 5677 5678 #sound-dai-cells = <0>; 5679 5680 status = "disabled"; 5681 5682 ports { 5683 #address-cells = <1>; 5684 #size-cells = <0>; 5685 5686 port@0 { 5687 reg = <0>; 5688 mdss_dp2_in: endpoint { 5689 remote-endpoint = <&mdss_intf6_out>; 5690 }; 5691 }; 5692 5693 port@1 { 5694 reg = <1>; 5695 5696 mdss_dp2_out: endpoint { 5697 data-lanes = <0 1 2 3>; 5698 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; 5699 }; 5700 }; 5701 }; 5702 5703 mdss_dp2_opp_table: opp-table { 5704 compatible = "operating-points-v2"; 5705 5706 opp-160000000 { 5707 opp-hz = /bits/ 64 <160000000>; 5708 required-opps = <&rpmhpd_opp_low_svs>; 5709 }; 5710 5711 opp-270000000 { 5712 opp-hz = /bits/ 64 <270000000>; 5713 required-opps = <&rpmhpd_opp_svs>; 5714 }; 5715 5716 opp-540000000 { 5717 opp-hz = /bits/ 64 <540000000>; 5718 required-opps = <&rpmhpd_opp_svs_l1>; 5719 }; 5720 5721 opp-810000000 { 5722 opp-hz = /bits/ 64 <810000000>; 5723 required-opps = <&rpmhpd_opp_nom>; 5724 }; 5725 }; 5726 }; 5727 5728 mdss_dp3: displayport-controller@aea0000 { 5729 compatible = "qcom,x1e80100-dp"; 5730 reg = <0 0x0aea0000 0 0x200>, 5731 <0 0x0aea0200 0 0x200>, 5732 <0 0x0aea0400 0 0x600>, 5733 <0 0x0aea1000 0 0x400>, 5734 <0 0x0aea1400 0 0x400>; 5735 5736 interrupts-extended = <&mdss 15>; 5737 5738 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5739 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5740 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 5741 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5742 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5743 clock-names = "core_iface", 5744 "core_aux", 5745 "ctrl_link", 5746 "ctrl_link_iface", 5747 "stream_pixel"; 5748 5749 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5750 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5751 assigned-clock-parents = <&mdss_dp3_phy 0>, 5752 <&mdss_dp3_phy 1>; 5753 5754 operating-points-v2 = <&mdss_dp3_opp_table>; 5755 5756 power-domains = <&rpmhpd RPMHPD_MMCX>; 5757 5758 phys = <&mdss_dp3_phy>; 5759 phy-names = "dp"; 5760 5761 #sound-dai-cells = <0>; 5762 5763 status = "disabled"; 5764 5765 ports { 5766 #address-cells = <1>; 5767 #size-cells = <0>; 5768 5769 port@0 { 5770 reg = <0>; 5771 5772 mdss_dp3_in: endpoint { 5773 remote-endpoint = <&mdss_intf5_out>; 5774 }; 5775 }; 5776 5777 port@1 { 5778 reg = <1>; 5779 5780 mdss_dp3_out: endpoint { 5781 }; 5782 }; 5783 }; 5784 5785 mdss_dp3_opp_table: opp-table { 5786 compatible = "operating-points-v2"; 5787 5788 opp-160000000 { 5789 opp-hz = /bits/ 64 <160000000>; 5790 required-opps = <&rpmhpd_opp_low_svs>; 5791 }; 5792 5793 opp-270000000 { 5794 opp-hz = /bits/ 64 <270000000>; 5795 required-opps = <&rpmhpd_opp_svs>; 5796 }; 5797 5798 opp-540000000 { 5799 opp-hz = /bits/ 64 <540000000>; 5800 required-opps = <&rpmhpd_opp_svs_l1>; 5801 }; 5802 5803 opp-810000000 { 5804 opp-hz = /bits/ 64 <810000000>; 5805 required-opps = <&rpmhpd_opp_nom>; 5806 }; 5807 }; 5808 }; 5809 5810 }; 5811 5812 mdss_dp2_phy: phy@aec2a00 { 5813 compatible = "qcom,x1e80100-dp-phy"; 5814 reg = <0 0x0aec2a00 0 0x19c>, 5815 <0 0x0aec2200 0 0xec>, 5816 <0 0x0aec2600 0 0xec>, 5817 <0 0x0aec2000 0 0x1c8>; 5818 5819 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5820 <&dispcc DISP_CC_MDSS_AHB_CLK>; 5821 clock-names = "aux", 5822 "cfg_ahb"; 5823 5824 power-domains = <&rpmhpd RPMHPD_MX>; 5825 5826 #clock-cells = <1>; 5827 #phy-cells = <0>; 5828 5829 status = "disabled"; 5830 }; 5831 5832 mdss_dp3_phy: phy@aec5a00 { 5833 compatible = "qcom,x1e80100-dp-phy"; 5834 reg = <0 0x0aec5a00 0 0x19c>, 5835 <0 0x0aec5200 0 0xec>, 5836 <0 0x0aec5600 0 0xec>, 5837 <0 0x0aec5000 0 0x1c8>; 5838 5839 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5840 <&dispcc DISP_CC_MDSS_AHB_CLK>; 5841 clock-names = "aux", 5842 "cfg_ahb"; 5843 5844 power-domains = <&rpmhpd RPMHPD_MX>; 5845 5846 #clock-cells = <1>; 5847 #phy-cells = <0>; 5848 5849 status = "disabled"; 5850 }; 5851 5852 dispcc: clock-controller@af00000 { 5853 compatible = "qcom,x1e80100-dispcc"; 5854 reg = <0 0x0af00000 0 0x20000>; 5855 clocks = <&bi_tcxo_div2>, 5856 <&bi_tcxo_ao_div2>, 5857 <&gcc GCC_DISP_AHB_CLK>, 5858 <&sleep_clk>, 5859 <0>, /* dsi0 */ 5860 <0>, 5861 <0>, /* dsi1 */ 5862 <0>, 5863 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 5864 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5865 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 5866 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5867 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 5868 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5869 <&mdss_dp3_phy 0>, /* dp3 */ 5870 <&mdss_dp3_phy 1>; 5871 power-domains = <&rpmhpd RPMHPD_MMCX>; 5872 required-opps = <&rpmhpd_opp_low_svs>; 5873 #clock-cells = <1>; 5874 #reset-cells = <1>; 5875 #power-domain-cells = <1>; 5876 }; 5877 5878 pdc: interrupt-controller@b220000 { 5879 compatible = "qcom,x1e80100-pdc", "qcom,pdc"; 5880 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 5881 5882 qcom,pdc-ranges = <0 480 42>, <42 251 5>, 5883 <47 522 52>, <99 609 32>, 5884 <131 717 12>, <143 816 19>; 5885 #interrupt-cells = <2>; 5886 interrupt-parent = <&intc>; 5887 interrupt-controller; 5888 }; 5889 5890 aoss_qmp: power-management@c300000 { 5891 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp"; 5892 reg = <0 0x0c300000 0 0x400>; 5893 interrupt-parent = <&ipcc>; 5894 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 5895 IRQ_TYPE_EDGE_RISING>; 5896 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5897 5898 #clock-cells = <0>; 5899 }; 5900 5901 sram@c3f0000 { 5902 compatible = "qcom,rpmh-stats"; 5903 reg = <0 0x0c3f0000 0 0x400>; 5904 }; 5905 5906 spmi: arbiter@c400000 { 5907 compatible = "qcom,x1e80100-spmi-pmic-arb"; 5908 reg = <0 0x0c400000 0 0x3000>, 5909 <0 0x0c500000 0 0x400000>, 5910 <0 0x0c440000 0 0x80000>; 5911 reg-names = "core", "chnls", "obsrvr"; 5912 5913 qcom,ee = <0>; 5914 qcom,channel = <0>; 5915 5916 #address-cells = <2>; 5917 #size-cells = <2>; 5918 ranges; 5919 5920 spmi_bus0: spmi@c42d000 { 5921 reg = <0 0x0c42d000 0 0x4000>, 5922 <0 0x0c4c0000 0 0x10000>; 5923 reg-names = "cnfg", "intr"; 5924 5925 interrupt-names = "periph_irq"; 5926 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5927 interrupt-controller; 5928 #interrupt-cells = <4>; 5929 5930 #address-cells = <2>; 5931 #size-cells = <0>; 5932 }; 5933 5934 spmi_bus1: spmi@c432000 { 5935 reg = <0 0x0c432000 0 0x4000>, 5936 <0 0x0c4d0000 0 0x10000>; 5937 reg-names = "cnfg", "intr"; 5938 5939 interrupt-names = "periph_irq"; 5940 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 5941 interrupt-controller; 5942 #interrupt-cells = <4>; 5943 5944 #address-cells = <2>; 5945 #size-cells = <0>; 5946 }; 5947 }; 5948 5949 tlmm: pinctrl@f100000 { 5950 compatible = "qcom,x1e80100-tlmm"; 5951 reg = <0 0x0f100000 0 0xf00000>; 5952 5953 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5954 5955 gpio-controller; 5956 #gpio-cells = <2>; 5957 5958 interrupt-controller; 5959 #interrupt-cells = <2>; 5960 5961 gpio-ranges = <&tlmm 0 0 239>; 5962 wakeup-parent = <&pdc>; 5963 5964 edp0_hpd_default: edp0-hpd-default-state { 5965 pins = "gpio119"; 5966 function = "edp0_hot"; 5967 bias-disable; 5968 }; 5969 5970 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5971 /* SDA, SCL */ 5972 pins = "gpio0", "gpio1"; 5973 function = "qup0_se0"; 5974 drive-strength = <2>; 5975 bias-pull-up = <2200>; 5976 }; 5977 5978 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5979 /* SDA, SCL */ 5980 pins = "gpio4", "gpio5"; 5981 function = "qup0_se1"; 5982 drive-strength = <2>; 5983 bias-pull-up = <2200>; 5984 }; 5985 5986 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5987 /* SDA, SCL */ 5988 pins = "gpio8", "gpio9"; 5989 function = "qup0_se2"; 5990 drive-strength = <2>; 5991 bias-pull-up = <2200>; 5992 }; 5993 5994 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5995 /* SDA, SCL */ 5996 pins = "gpio12", "gpio13"; 5997 function = "qup0_se3"; 5998 drive-strength = <2>; 5999 bias-pull-up = <2200>; 6000 }; 6001 6002 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 6003 /* SDA, SCL */ 6004 pins = "gpio16", "gpio17"; 6005 function = "qup0_se4"; 6006 drive-strength = <2>; 6007 bias-pull-up = <2200>; 6008 }; 6009 6010 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 6011 /* SDA, SCL */ 6012 pins = "gpio20", "gpio21"; 6013 function = "qup0_se5"; 6014 drive-strength = <2>; 6015 bias-pull-up = <2200>; 6016 }; 6017 6018 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 6019 /* SDA, SCL */ 6020 pins = "gpio24", "gpio25"; 6021 function = "qup0_se6"; 6022 drive-strength = <2>; 6023 bias-pull-up = <2200>; 6024 }; 6025 6026 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 6027 /* SDA, SCL */ 6028 pins = "gpio14", "gpio15"; 6029 function = "qup0_se7"; 6030 drive-strength = <2>; 6031 bias-pull-up = <2200>; 6032 }; 6033 6034 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 6035 /* SDA, SCL */ 6036 pins = "gpio32", "gpio33"; 6037 function = "qup1_se0"; 6038 drive-strength = <2>; 6039 bias-pull-up = <2200>; 6040 }; 6041 6042 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 6043 /* SDA, SCL */ 6044 pins = "gpio36", "gpio37"; 6045 function = "qup1_se1"; 6046 drive-strength = <2>; 6047 bias-pull-up = <2200>; 6048 }; 6049 6050 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 6051 /* SDA, SCL */ 6052 pins = "gpio40", "gpio41"; 6053 function = "qup1_se2"; 6054 drive-strength = <2>; 6055 bias-pull-up = <2200>; 6056 }; 6057 6058 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 6059 /* SDA, SCL */ 6060 pins = "gpio44", "gpio45"; 6061 function = "qup1_se3"; 6062 drive-strength = <2>; 6063 bias-pull-up = <2200>; 6064 }; 6065 6066 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 6067 /* SDA, SCL */ 6068 pins = "gpio48", "gpio49"; 6069 function = "qup1_se4"; 6070 drive-strength = <2>; 6071 bias-pull-up = <2200>; 6072 }; 6073 6074 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 6075 /* SDA, SCL */ 6076 pins = "gpio52", "gpio53"; 6077 function = "qup1_se5"; 6078 drive-strength = <2>; 6079 bias-pull-up = <2200>; 6080 }; 6081 6082 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 6083 /* SDA, SCL */ 6084 pins = "gpio56", "gpio57"; 6085 function = "qup1_se6"; 6086 drive-strength = <2>; 6087 bias-pull-up = <2200>; 6088 }; 6089 6090 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 6091 /* SDA, SCL */ 6092 pins = "gpio54", "gpio55"; 6093 function = "qup1_se7"; 6094 drive-strength = <2>; 6095 bias-pull-up = <2200>; 6096 }; 6097 6098 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 6099 /* SDA, SCL */ 6100 pins = "gpio64", "gpio65"; 6101 function = "qup2_se0"; 6102 drive-strength = <2>; 6103 bias-pull-up = <2200>; 6104 }; 6105 6106 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 6107 /* SDA, SCL */ 6108 pins = "gpio68", "gpio69"; 6109 function = "qup2_se1"; 6110 drive-strength = <2>; 6111 bias-pull-up = <2200>; 6112 }; 6113 6114 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 6115 /* SDA, SCL */ 6116 pins = "gpio72", "gpio73"; 6117 function = "qup2_se2"; 6118 drive-strength = <2>; 6119 bias-pull-up = <2200>; 6120 }; 6121 6122 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 6123 /* SDA, SCL */ 6124 pins = "gpio76", "gpio77"; 6125 function = "qup2_se3"; 6126 drive-strength = <2>; 6127 bias-pull-up = <2200>; 6128 }; 6129 6130 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 6131 /* SDA, SCL */ 6132 pins = "gpio80", "gpio81"; 6133 function = "qup2_se4"; 6134 drive-strength = <2>; 6135 bias-pull-up = <2200>; 6136 }; 6137 6138 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 6139 /* SDA, SCL */ 6140 pins = "gpio84", "gpio85"; 6141 function = "qup2_se5"; 6142 drive-strength = <2>; 6143 bias-pull-up = <2200>; 6144 }; 6145 6146 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 6147 /* SDA, SCL */ 6148 pins = "gpio88", "gpio89"; 6149 function = "qup2_se6"; 6150 drive-strength = <2>; 6151 bias-pull-up = <2200>; 6152 }; 6153 6154 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 6155 /* SDA, SCL */ 6156 pins = "gpio86", "gpio87"; 6157 function = "qup2_se7"; 6158 drive-strength = <2>; 6159 bias-pull-up = <2200>; 6160 }; 6161 6162 qup_spi0_cs: qup-spi0-cs-state { 6163 pins = "gpio3"; 6164 function = "qup0_se0"; 6165 drive-strength = <6>; 6166 bias-disable; 6167 }; 6168 6169 qup_spi0_data_clk: qup-spi0-data-clk-state { 6170 /* MISO, MOSI, CLK */ 6171 pins = "gpio0", "gpio1", "gpio2"; 6172 function = "qup0_se0"; 6173 drive-strength = <6>; 6174 bias-disable; 6175 }; 6176 6177 qup_spi1_cs: qup-spi1-cs-state { 6178 pins = "gpio7"; 6179 function = "qup0_se1"; 6180 drive-strength = <6>; 6181 bias-disable; 6182 }; 6183 6184 qup_spi1_data_clk: qup-spi1-data-clk-state { 6185 /* MISO, MOSI, CLK */ 6186 pins = "gpio4", "gpio5", "gpio6"; 6187 function = "qup0_se1"; 6188 drive-strength = <6>; 6189 bias-disable; 6190 }; 6191 6192 qup_spi2_cs: qup-spi2-cs-state { 6193 pins = "gpio11"; 6194 function = "qup0_se2"; 6195 drive-strength = <6>; 6196 bias-disable; 6197 }; 6198 6199 qup_spi2_data_clk: qup-spi2-data-clk-state { 6200 /* MISO, MOSI, CLK */ 6201 pins = "gpio8", "gpio9", "gpio10"; 6202 function = "qup0_se2"; 6203 drive-strength = <6>; 6204 bias-disable; 6205 }; 6206 6207 qup_spi3_cs: qup-spi3-cs-state { 6208 pins = "gpio15"; 6209 function = "qup0_se3"; 6210 drive-strength = <6>; 6211 bias-disable; 6212 }; 6213 6214 qup_spi3_data_clk: qup-spi3-data-clk-state { 6215 /* MISO, MOSI, CLK */ 6216 pins = "gpio12", "gpio13", "gpio14"; 6217 function = "qup0_se3"; 6218 drive-strength = <6>; 6219 bias-disable; 6220 }; 6221 6222 qup_spi4_cs: qup-spi4-cs-state { 6223 pins = "gpio19"; 6224 function = "qup0_se4"; 6225 drive-strength = <6>; 6226 bias-disable; 6227 }; 6228 6229 qup_spi4_data_clk: qup-spi4-data-clk-state { 6230 /* MISO, MOSI, CLK */ 6231 pins = "gpio16", "gpio17", "gpio18"; 6232 function = "qup0_se4"; 6233 drive-strength = <6>; 6234 bias-disable; 6235 }; 6236 6237 qup_spi5_cs: qup-spi5-cs-state { 6238 pins = "gpio23"; 6239 function = "qup0_se5"; 6240 drive-strength = <6>; 6241 bias-disable; 6242 }; 6243 6244 qup_spi5_data_clk: qup-spi5-data-clk-state { 6245 /* MISO, MOSI, CLK */ 6246 pins = "gpio20", "gpio21", "gpio22"; 6247 function = "qup0_se5"; 6248 drive-strength = <6>; 6249 bias-disable; 6250 }; 6251 6252 qup_spi6_cs: qup-spi6-cs-state { 6253 pins = "gpio27"; 6254 function = "qup0_se6"; 6255 drive-strength = <6>; 6256 bias-disable; 6257 }; 6258 6259 qup_spi6_data_clk: qup-spi6-data-clk-state { 6260 /* MISO, MOSI, CLK */ 6261 pins = "gpio24", "gpio25", "gpio26"; 6262 function = "qup0_se6"; 6263 drive-strength = <6>; 6264 bias-disable; 6265 }; 6266 6267 qup_spi7_cs: qup-spi7-cs-state { 6268 pins = "gpio13"; 6269 function = "qup0_se7"; 6270 drive-strength = <6>; 6271 bias-disable; 6272 }; 6273 6274 qup_spi7_data_clk: qup-spi7-data-clk-state { 6275 /* MISO, MOSI, CLK */ 6276 pins = "gpio14", "gpio15", "gpio12"; 6277 function = "qup0_se7"; 6278 drive-strength = <6>; 6279 bias-disable; 6280 }; 6281 6282 qup_spi8_cs: qup-spi8-cs-state { 6283 pins = "gpio35"; 6284 function = "qup1_se0"; 6285 drive-strength = <6>; 6286 bias-disable; 6287 }; 6288 6289 qup_spi8_data_clk: qup-spi8-data-clk-state { 6290 /* MISO, MOSI, CLK */ 6291 pins = "gpio32", "gpio33", "gpio34"; 6292 function = "qup1_se0"; 6293 drive-strength = <6>; 6294 bias-disable; 6295 }; 6296 6297 qup_spi9_cs: qup-spi9-cs-state { 6298 pins = "gpio39"; 6299 function = "qup1_se1"; 6300 drive-strength = <6>; 6301 bias-disable; 6302 }; 6303 6304 qup_spi9_data_clk: qup-spi9-data-clk-state { 6305 /* MISO, MOSI, CLK */ 6306 pins = "gpio36", "gpio37", "gpio38"; 6307 function = "qup1_se1"; 6308 drive-strength = <6>; 6309 bias-disable; 6310 }; 6311 6312 qup_spi10_cs: qup-spi10-cs-state { 6313 pins = "gpio43"; 6314 function = "qup1_se2"; 6315 drive-strength = <6>; 6316 bias-disable; 6317 }; 6318 6319 qup_spi10_data_clk: qup-spi10-data-clk-state { 6320 /* MISO, MOSI, CLK */ 6321 pins = "gpio40", "gpio41", "gpio42"; 6322 function = "qup1_se2"; 6323 drive-strength = <6>; 6324 bias-disable; 6325 }; 6326 6327 qup_spi11_cs: qup-spi11-cs-state { 6328 pins = "gpio47"; 6329 function = "qup1_se3"; 6330 drive-strength = <6>; 6331 bias-disable; 6332 }; 6333 6334 qup_spi11_data_clk: qup-spi11-data-clk-state { 6335 /* MISO, MOSI, CLK */ 6336 pins = "gpio44", "gpio45", "gpio46"; 6337 function = "qup1_se3"; 6338 drive-strength = <6>; 6339 bias-disable; 6340 }; 6341 6342 qup_spi12_cs: qup-spi12-cs-state { 6343 pins = "gpio51"; 6344 function = "qup1_se4"; 6345 drive-strength = <6>; 6346 bias-disable; 6347 }; 6348 6349 qup_spi12_data_clk: qup-spi12-data-clk-state { 6350 /* MISO, MOSI, CLK */ 6351 pins = "gpio48", "gpio49", "gpio50"; 6352 function = "qup1_se4"; 6353 drive-strength = <6>; 6354 bias-disable; 6355 }; 6356 6357 qup_spi13_cs: qup-spi13-cs-state { 6358 pins = "gpio55"; 6359 function = "qup1_se5"; 6360 drive-strength = <6>; 6361 bias-disable; 6362 }; 6363 6364 qup_spi13_data_clk: qup-spi13-data-clk-state { 6365 /* MISO, MOSI, CLK */ 6366 pins = "gpio52", "gpio53", "gpio54"; 6367 function = "qup1_se5"; 6368 drive-strength = <6>; 6369 bias-disable; 6370 }; 6371 6372 qup_spi14_cs: qup-spi14-cs-state { 6373 pins = "gpio59"; 6374 function = "qup1_se6"; 6375 drive-strength = <6>; 6376 bias-disable; 6377 }; 6378 6379 qup_spi14_data_clk: qup-spi14-data-clk-state { 6380 /* MISO, MOSI, CLK */ 6381 pins = "gpio56", "gpio57", "gpio58"; 6382 function = "qup1_se6"; 6383 drive-strength = <6>; 6384 bias-disable; 6385 }; 6386 6387 qup_spi15_cs: qup-spi15-cs-state { 6388 pins = "gpio53"; 6389 function = "qup1_se7"; 6390 drive-strength = <6>; 6391 bias-disable; 6392 }; 6393 6394 qup_spi15_data_clk: qup-spi15-data-clk-state { 6395 /* MISO, MOSI, CLK */ 6396 pins = "gpio54", "gpio55", "gpio52"; 6397 function = "qup1_se7"; 6398 drive-strength = <6>; 6399 bias-disable; 6400 }; 6401 6402 qup_spi16_cs: qup-spi16-cs-state { 6403 pins = "gpio67"; 6404 function = "qup2_se0"; 6405 drive-strength = <6>; 6406 bias-disable; 6407 }; 6408 6409 qup_spi16_data_clk: qup-spi16-data-clk-state { 6410 /* MISO, MOSI, CLK */ 6411 pins = "gpio64", "gpio65", "gpio66"; 6412 function = "qup2_se0"; 6413 drive-strength = <6>; 6414 bias-disable; 6415 }; 6416 6417 qup_spi17_cs: qup-spi17-cs-state { 6418 pins = "gpio71"; 6419 function = "qup2_se1"; 6420 drive-strength = <6>; 6421 bias-disable; 6422 }; 6423 6424 qup_spi17_data_clk: qup-spi17-data-clk-state { 6425 /* MISO, MOSI, CLK */ 6426 pins = "gpio68", "gpio69", "gpio70"; 6427 function = "qup2_se1"; 6428 drive-strength = <6>; 6429 bias-disable; 6430 }; 6431 6432 qup_spi18_cs: qup-spi18-cs-state { 6433 pins = "gpio75"; 6434 function = "qup2_se2"; 6435 drive-strength = <6>; 6436 bias-disable; 6437 }; 6438 6439 qup_spi18_data_clk: qup-spi18-data-clk-state { 6440 /* MISO, MOSI, CLK */ 6441 pins = "gpio72", "gpio73", "gpio74"; 6442 function = "qup2_se2"; 6443 drive-strength = <6>; 6444 bias-disable; 6445 }; 6446 6447 qup_spi19_cs: qup-spi19-cs-state { 6448 pins = "gpio79"; 6449 function = "qup2_se3"; 6450 drive-strength = <6>; 6451 bias-disable; 6452 }; 6453 6454 qup_spi19_data_clk: qup-spi19-data-clk-state { 6455 /* MISO, MOSI, CLK */ 6456 pins = "gpio76", "gpio77", "gpio78"; 6457 function = "qup2_se3"; 6458 drive-strength = <6>; 6459 bias-disable; 6460 }; 6461 6462 qup_spi20_cs: qup-spi20-cs-state { 6463 pins = "gpio83"; 6464 function = "qup2_se4"; 6465 drive-strength = <6>; 6466 bias-disable; 6467 }; 6468 6469 qup_spi20_data_clk: qup-spi20-data-clk-state { 6470 /* MISO, MOSI, CLK */ 6471 pins = "gpio80", "gpio81", "gpio82"; 6472 function = "qup2_se4"; 6473 drive-strength = <6>; 6474 bias-disable; 6475 }; 6476 6477 qup_spi21_cs: qup-spi21-cs-state { 6478 pins = "gpio87"; 6479 function = "qup2_se5"; 6480 drive-strength = <6>; 6481 bias-disable; 6482 }; 6483 6484 qup_spi21_data_clk: qup-spi21-data-clk-state { 6485 /* MISO, MOSI, CLK */ 6486 pins = "gpio84", "gpio85", "gpio86"; 6487 function = "qup2_se5"; 6488 drive-strength = <6>; 6489 bias-disable; 6490 }; 6491 6492 qup_spi22_cs: qup-spi22-cs-state { 6493 pins = "gpio91"; 6494 function = "qup2_se6"; 6495 drive-strength = <6>; 6496 bias-disable; 6497 }; 6498 6499 qup_spi22_data_clk: qup-spi22-data-clk-state { 6500 /* MISO, MOSI, CLK */ 6501 pins = "gpio88", "gpio89", "gpio90"; 6502 function = "qup2_se6"; 6503 drive-strength = <6>; 6504 bias-disable; 6505 }; 6506 6507 qup_spi23_cs: qup-spi23-cs-state { 6508 pins = "gpio85"; 6509 function = "qup2_se7"; 6510 drive-strength = <6>; 6511 bias-disable; 6512 }; 6513 6514 qup_spi23_data_clk: qup-spi23-data-clk-state { 6515 /* MISO, MOSI, CLK */ 6516 pins = "gpio86", "gpio87", "gpio84"; 6517 function = "qup2_se7"; 6518 drive-strength = <6>; 6519 bias-disable; 6520 }; 6521 6522 qup_uart2_default: qup-uart2-default-state { 6523 cts-pins { 6524 pins = "gpio8"; 6525 function = "qup0_se2"; 6526 drive-strength = <2>; 6527 bias-disable; 6528 }; 6529 6530 rts-pins { 6531 pins = "gpio9"; 6532 function = "qup0_se2"; 6533 drive-strength = <2>; 6534 bias-disable; 6535 }; 6536 6537 tx-pins { 6538 pins = "gpio10"; 6539 function = "qup0_se2"; 6540 drive-strength = <2>; 6541 bias-disable; 6542 }; 6543 6544 rx-pins { 6545 pins = "gpio11"; 6546 function = "qup0_se2"; 6547 drive-strength = <2>; 6548 bias-disable; 6549 }; 6550 }; 6551 6552 qup_uart14_default: qup-uart14-default-state { 6553 cts-pins { 6554 pins = "gpio56"; 6555 function = "qup1_se6"; 6556 bias-bus-hold; 6557 }; 6558 6559 rts-pins { 6560 pins = "gpio57"; 6561 function = "qup1_se6"; 6562 drive-strength = <2>; 6563 bias-disable; 6564 }; 6565 6566 tx-pins { 6567 pins = "gpio58"; 6568 function = "qup1_se6"; 6569 drive-strength = <2>; 6570 bias-disable; 6571 }; 6572 6573 rx-pins { 6574 pins = "gpio59"; 6575 function = "qup1_se6"; 6576 bias-pull-up; 6577 }; 6578 }; 6579 6580 qup_uart21_default: qup-uart21-default-state { 6581 tx-pins { 6582 pins = "gpio86"; 6583 function = "qup2_se5"; 6584 drive-strength = <2>; 6585 bias-disable; 6586 }; 6587 6588 rx-pins { 6589 pins = "gpio87"; 6590 function = "qup2_se5"; 6591 drive-strength = <2>; 6592 bias-disable; 6593 }; 6594 }; 6595 6596 sdc2_default: sdc2-default-state { 6597 clk-pins { 6598 pins = "sdc2_clk"; 6599 drive-strength = <16>; 6600 bias-disable; 6601 }; 6602 6603 cmd-pins { 6604 pins = "sdc2_cmd"; 6605 drive-strength = <10>; 6606 bias-pull-up; 6607 }; 6608 6609 data-pins { 6610 pins = "sdc2_data"; 6611 drive-strength = <10>; 6612 bias-pull-up; 6613 }; 6614 }; 6615 6616 sdc2_sleep: sdc2-sleep-state { 6617 clk-pins { 6618 pins = "sdc2_clk"; 6619 drive-strength = <2>; 6620 bias-disable; 6621 }; 6622 6623 cmd-pins { 6624 pins = "sdc2_cmd"; 6625 drive-strength = <2>; 6626 bias-pull-up; 6627 }; 6628 6629 data-pins { 6630 pins = "sdc2_data"; 6631 drive-strength = <2>; 6632 bias-pull-up; 6633 }; 6634 }; 6635 }; 6636 6637 stm@10002000 { 6638 compatible = "arm,coresight-stm", "arm,primecell"; 6639 reg = <0x0 0x10002000 0x0 0x1000>, 6640 <0x0 0x16280000 0x0 0x180000>; 6641 reg-names = "stm-base", 6642 "stm-stimulus-base"; 6643 6644 clocks = <&aoss_qmp>; 6645 clock-names = "apb_pclk"; 6646 6647 out-ports { 6648 port { 6649 stm_out: endpoint { 6650 remote-endpoint = <&funnel0_in7>; 6651 }; 6652 }; 6653 }; 6654 }; 6655 6656 tpdm@10003000 { 6657 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6658 reg = <0x0 0x10003000 0x0 0x1000>; 6659 6660 clocks = <&aoss_qmp>; 6661 clock-names = "apb_pclk"; 6662 6663 qcom,cmb-element-bits = <32>; 6664 qcom,cmb-msrs-num = <32>; 6665 status = "disabled"; 6666 6667 out-ports { 6668 port { 6669 dcc_tpdm_out: endpoint { 6670 remote-endpoint = <&qdss_tpda_in0>; 6671 }; 6672 }; 6673 }; 6674 }; 6675 6676 tpda@10004000 { 6677 compatible = "qcom,coresight-tpda", "arm,primecell"; 6678 reg = <0x0 0x10004000 0x0 0x1000>; 6679 6680 clocks = <&aoss_qmp>; 6681 clock-names = "apb_pclk"; 6682 6683 in-ports { 6684 #address-cells = <1>; 6685 #size-cells = <0>; 6686 6687 port@0 { 6688 reg = <0>; 6689 6690 qdss_tpda_in0: endpoint { 6691 remote-endpoint = <&dcc_tpdm_out>; 6692 }; 6693 }; 6694 6695 port@1 { 6696 reg = <1>; 6697 6698 qdss_tpda_in1: endpoint { 6699 remote-endpoint = <&qdss_tpdm_out>; 6700 }; 6701 }; 6702 }; 6703 6704 out-ports { 6705 port { 6706 qdss_tpda_out: endpoint { 6707 remote-endpoint = <&funnel0_in6>; 6708 }; 6709 }; 6710 }; 6711 }; 6712 6713 tpdm@1000f000 { 6714 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6715 reg = <0x0 0x1000f000 0x0 0x1000>; 6716 6717 clocks = <&aoss_qmp>; 6718 clock-names = "apb_pclk"; 6719 6720 qcom,cmb-element-bits = <32>; 6721 qcom,cmb-msrs-num = <32>; 6722 6723 out-ports { 6724 port { 6725 qdss_tpdm_out: endpoint { 6726 remote-endpoint = <&qdss_tpda_in1>; 6727 }; 6728 }; 6729 }; 6730 }; 6731 6732 funnel@10041000 { 6733 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6734 reg = <0x0 0x10041000 0x0 0x1000>; 6735 6736 clocks = <&aoss_qmp>; 6737 clock-names = "apb_pclk"; 6738 6739 in-ports { 6740 #address-cells = <1>; 6741 #size-cells = <0>; 6742 6743 port@6 { 6744 reg = <6>; 6745 6746 funnel0_in6: endpoint { 6747 remote-endpoint = <&qdss_tpda_out>; 6748 }; 6749 }; 6750 6751 port@7 { 6752 reg = <7>; 6753 6754 funnel0_in7: endpoint { 6755 remote-endpoint = <&stm_out>; 6756 }; 6757 }; 6758 }; 6759 6760 out-ports { 6761 port { 6762 funnel0_out: endpoint { 6763 remote-endpoint = <&qdss_funnel_in0>; 6764 }; 6765 }; 6766 }; 6767 }; 6768 6769 funnel@10042000 { 6770 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6771 reg = <0x0 0x10042000 0x0 0x1000>; 6772 6773 clocks = <&aoss_qmp>; 6774 clock-names = "apb_pclk"; 6775 6776 in-ports { 6777 #address-cells = <1>; 6778 #size-cells = <0>; 6779 6780 port@2 { 6781 reg = <2>; 6782 6783 funnel1_in2: endpoint { 6784 remote-endpoint = <&tmess_funnel_out>; 6785 }; 6786 }; 6787 6788 port@5 { 6789 reg = <5>; 6790 6791 funnel1_in5: endpoint { 6792 remote-endpoint = <&dlst_funnel_out>; 6793 }; 6794 }; 6795 6796 port@6 { 6797 reg = <6>; 6798 6799 funnel1_in6: endpoint { 6800 remote-endpoint = <&dlct1_funnel_out>; 6801 }; 6802 }; 6803 }; 6804 6805 out-ports { 6806 port { 6807 funnel1_out: endpoint { 6808 remote-endpoint = <&qdss_funnel_in1>; 6809 }; 6810 }; 6811 }; 6812 }; 6813 6814 funnel@10045000 { 6815 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6816 reg = <0x0 0x10045000 0x0 0x1000>; 6817 6818 clocks = <&aoss_qmp>; 6819 clock-names = "apb_pclk"; 6820 6821 in-ports { 6822 #address-cells = <1>; 6823 #size-cells = <0>; 6824 6825 port@0 { 6826 reg = <0>; 6827 6828 qdss_funnel_in0: endpoint { 6829 remote-endpoint = <&funnel0_out>; 6830 }; 6831 }; 6832 6833 port@1 { 6834 reg = <1>; 6835 6836 qdss_funnel_in1: endpoint { 6837 remote-endpoint = <&funnel1_out>; 6838 }; 6839 }; 6840 }; 6841 6842 out-ports { 6843 port { 6844 qdss_funnel_out: endpoint { 6845 remote-endpoint = <&aoss_funnel_in7>; 6846 }; 6847 }; 6848 }; 6849 }; 6850 6851 tpdm@10800000 { 6852 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6853 reg = <0x0 0x10800000 0x0 0x1000>; 6854 6855 clocks = <&aoss_qmp>; 6856 clock-names = "apb_pclk"; 6857 6858 qcom,cmb-element-bits = <64>; 6859 qcom,cmb-msrs-num = <32>; 6860 6861 out-ports { 6862 port { 6863 mxa_tpdm_out: endpoint { 6864 remote-endpoint = <&dlct2_tpda_in15>; 6865 }; 6866 }; 6867 }; 6868 }; 6869 6870 tpdm@1082c000 { 6871 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6872 reg = <0x0 0x1082c000 0x0 0x1000>; 6873 6874 clocks = <&aoss_qmp>; 6875 clock-names = "apb_pclk"; 6876 6877 qcom,dsb-element-bits = <32>; 6878 qcom,dsb-msrs-num = <32>; 6879 6880 out-ports { 6881 port { 6882 gcc_tpdm_out: endpoint { 6883 remote-endpoint = <&dlct1_tpda_in21>; 6884 }; 6885 }; 6886 }; 6887 }; 6888 6889 tpdm@10841000 { 6890 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6891 reg = <0x0 0x10841000 0x0 0x1000>; 6892 6893 clocks = <&aoss_qmp>; 6894 clock-names = "apb_pclk"; 6895 6896 qcom,cmb-element-bits = <32>; 6897 qcom,cmb-msrs-num = <32>; 6898 6899 out-ports { 6900 port { 6901 prng_tpdm_out: endpoint { 6902 remote-endpoint = <&dlct1_tpda_in19>; 6903 }; 6904 }; 6905 }; 6906 }; 6907 6908 tpdm@10844000 { 6909 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6910 reg = <0x0 0x10844000 0x0 0x1000>; 6911 6912 clocks = <&aoss_qmp>; 6913 clock-names = "apb_pclk"; 6914 6915 qcom,dsb-element-bits = <32>; 6916 qcom,dsb-msrs-num = <32>; 6917 6918 out-ports { 6919 port { 6920 lpass_cx_tpdm_out: endpoint { 6921 remote-endpoint = <&lpass_cx_funnel_in0>; 6922 }; 6923 }; 6924 }; 6925 }; 6926 6927 funnel@10846000 { 6928 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6929 reg = <0x0 0x10846000 0x0 0x1000>; 6930 6931 clocks = <&aoss_qmp>; 6932 clock-names = "apb_pclk"; 6933 6934 in-ports { 6935 port { 6936 lpass_cx_funnel_in0: endpoint { 6937 remote-endpoint = <&lpass_cx_tpdm_out>; 6938 }; 6939 }; 6940 }; 6941 6942 out-ports { 6943 port { 6944 lpass_cx_funnel_out: endpoint { 6945 remote-endpoint = <&dlct1_tpda_in4>; 6946 }; 6947 }; 6948 }; 6949 }; 6950 6951 cti@1098b000 { 6952 compatible = "arm,coresight-cti", "arm,primecell"; 6953 reg = <0x0 0x1098b000 0x0 0x1000>; 6954 6955 clocks = <&aoss_qmp>; 6956 clock-names = "apb_pclk"; 6957 }; 6958 6959 tpdm@109d0000 { 6960 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6961 reg = <0x0 0x109d0000 0x0 0x1000>; 6962 6963 clocks = <&aoss_qmp>; 6964 clock-names = "apb_pclk"; 6965 6966 qcom,dsb-element-bits = <32>; 6967 qcom,dsb-msrs-num = <32>; 6968 status = "disabled"; 6969 6970 out-ports { 6971 port { 6972 qm_tpdm_out: endpoint { 6973 remote-endpoint = <&dlct1_tpda_in20>; 6974 }; 6975 }; 6976 }; 6977 }; 6978 6979 tpdm@10ac0000 { 6980 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6981 reg = <0x0 0x10ac0000 0x0 0x1000>; 6982 6983 clocks = <&aoss_qmp>; 6984 clock-names = "apb_pclk"; 6985 6986 qcom,dsb-element-bits = <32>; 6987 qcom,dsb-msrs-num = <32>; 6988 status = "disabled"; 6989 6990 out-ports { 6991 port { 6992 dlst_tpdm0_out: endpoint { 6993 remote-endpoint = <&dlst_tpda_in8>; 6994 }; 6995 }; 6996 }; 6997 }; 6998 6999 tpdm@10ac1000 { 7000 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7001 reg = <0x0 0x10ac1000 0x0 0x1000>; 7002 7003 clocks = <&aoss_qmp>; 7004 clock-names = "apb_pclk"; 7005 7006 qcom,cmb-element-bits = <64>; 7007 qcom,cmb-msrs-num = <32>; 7008 7009 out-ports { 7010 port { 7011 dlst_tpdm1_out: endpoint { 7012 remote-endpoint = <&dlst_tpda_in9>; 7013 }; 7014 }; 7015 }; 7016 }; 7017 7018 tpda@10ac4000 { 7019 compatible = "qcom,coresight-tpda", "arm,primecell"; 7020 reg = <0x0 0x10ac4000 0x0 0x1000>; 7021 7022 clocks = <&aoss_qmp>; 7023 clock-names = "apb_pclk"; 7024 7025 in-ports { 7026 #address-cells = <1>; 7027 #size-cells = <0>; 7028 7029 port@8 { 7030 reg = <8>; 7031 7032 dlst_tpda_in8: endpoint { 7033 remote-endpoint = <&dlst_tpdm0_out>; 7034 }; 7035 }; 7036 7037 port@9 { 7038 reg = <9>; 7039 7040 dlst_tpda_in9: endpoint { 7041 remote-endpoint = <&dlst_tpdm1_out>; 7042 }; 7043 }; 7044 }; 7045 7046 out-ports { 7047 port { 7048 dlst_tpda_out: endpoint { 7049 remote-endpoint = <&dlst_funnel_in0>; 7050 }; 7051 }; 7052 }; 7053 }; 7054 7055 funnel@10ac5000 { 7056 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7057 reg = <0x0 0x10ac5000 0x0 0x1000>; 7058 7059 clocks = <&aoss_qmp>; 7060 clock-names = "apb_pclk"; 7061 7062 in-ports { 7063 port { 7064 dlst_funnel_in0: endpoint { 7065 remote-endpoint = <&dlst_tpda_out>; 7066 }; 7067 }; 7068 }; 7069 7070 out-ports { 7071 port { 7072 dlst_funnel_out: endpoint { 7073 remote-endpoint = <&funnel1_in5>; 7074 }; 7075 }; 7076 }; 7077 }; 7078 7079 funnel@10b04000 { 7080 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7081 reg = <0x0 0x10b04000 0x0 0x1000>; 7082 7083 clocks = <&aoss_qmp>; 7084 clock-names = "apb_pclk"; 7085 7086 in-ports { 7087 #address-cells = <1>; 7088 #size-cells = <0>; 7089 7090 port@3 { 7091 reg = <3>; 7092 7093 aoss_funnel_in3: endpoint { 7094 remote-endpoint = <&ddr_lpi_funnel_out>; 7095 }; 7096 }; 7097 7098 port@6 { 7099 reg = <6>; 7100 7101 aoss_funnel_in6: endpoint { 7102 remote-endpoint = <&aoss_tpda_out>; 7103 }; 7104 }; 7105 7106 port@7 { 7107 reg = <7>; 7108 7109 aoss_funnel_in7: endpoint { 7110 remote-endpoint = <&qdss_funnel_out>; 7111 }; 7112 }; 7113 }; 7114 7115 out-ports { 7116 port { 7117 aoss_funnel_out: endpoint { 7118 remote-endpoint = <&etf0_in>; 7119 }; 7120 }; 7121 }; 7122 }; 7123 7124 etf0: tmc@10b05000 { 7125 compatible = "arm,coresight-tmc", "arm,primecell"; 7126 reg = <0x0 0x10b05000 0x0 0x1000>; 7127 7128 clocks = <&aoss_qmp>; 7129 clock-names = "apb_pclk"; 7130 7131 in-ports { 7132 port { 7133 etf0_in: endpoint { 7134 remote-endpoint = <&aoss_funnel_out>; 7135 }; 7136 }; 7137 }; 7138 7139 out-ports { 7140 port { 7141 etf0_out: endpoint { 7142 remote-endpoint = <&swao_rep_in>; 7143 }; 7144 }; 7145 }; 7146 }; 7147 7148 replicator@10b06000 { 7149 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 7150 reg = <0x0 0x10b06000 0x0 0x1000>; 7151 7152 clocks = <&aoss_qmp>; 7153 clock-names = "apb_pclk"; 7154 7155 in-ports { 7156 port { 7157 swao_rep_in: endpoint { 7158 remote-endpoint = <&etf0_out>; 7159 }; 7160 }; 7161 }; 7162 7163 out-ports { 7164 port { 7165 swao_rep_out1: endpoint { 7166 remote-endpoint = <&eud_in>; 7167 }; 7168 }; 7169 }; 7170 }; 7171 7172 tpda@10b08000 { 7173 compatible = "qcom,coresight-tpda", "arm,primecell"; 7174 reg = <0x0 0x10b08000 0x0 0x1000>; 7175 7176 clocks = <&aoss_qmp>; 7177 clock-names = "apb_pclk"; 7178 7179 in-ports { 7180 #address-cells = <1>; 7181 #size-cells = <0>; 7182 7183 port@0 { 7184 reg = <0>; 7185 7186 aoss_tpda_in0: endpoint { 7187 remote-endpoint = <&aoss_tpdm0_out>; 7188 }; 7189 }; 7190 7191 port@1 { 7192 reg = <1>; 7193 7194 aoss_tpda_in1: endpoint { 7195 remote-endpoint = <&aoss_tpdm1_out>; 7196 }; 7197 }; 7198 7199 port@2 { 7200 reg = <2>; 7201 7202 aoss_tpda_in2: endpoint { 7203 remote-endpoint = <&aoss_tpdm2_out>; 7204 }; 7205 }; 7206 7207 port@3 { 7208 reg = <3>; 7209 7210 aoss_tpda_in3: endpoint { 7211 remote-endpoint = <&aoss_tpdm3_out>; 7212 }; 7213 }; 7214 7215 port@4 { 7216 reg = <4>; 7217 7218 aoss_tpda_in4: endpoint { 7219 remote-endpoint = <&aoss_tpdm4_out>; 7220 }; 7221 }; 7222 }; 7223 7224 out-ports { 7225 port { 7226 aoss_tpda_out: endpoint { 7227 remote-endpoint = <&aoss_funnel_in6>; 7228 }; 7229 }; 7230 }; 7231 }; 7232 7233 tpdm@10b09000 { 7234 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7235 reg = <0x0 0x10b09000 0x0 0x1000>; 7236 7237 clocks = <&aoss_qmp>; 7238 clock-names = "apb_pclk"; 7239 7240 qcom,cmb-element-bits = <64>; 7241 qcom,cmb-msrs-num = <32>; 7242 7243 out-ports { 7244 port { 7245 aoss_tpdm0_out: endpoint { 7246 remote-endpoint = <&aoss_tpda_in0>; 7247 }; 7248 }; 7249 }; 7250 }; 7251 7252 tpdm@10b0a000 { 7253 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7254 reg = <0x0 0x10b0a000 0x0 0x1000>; 7255 7256 clocks = <&aoss_qmp>; 7257 clock-names = "apb_pclk"; 7258 7259 qcom,cmb-element-bits = <64>; 7260 qcom,cmb-msrs-num = <32>; 7261 7262 out-ports { 7263 port { 7264 aoss_tpdm1_out: endpoint { 7265 remote-endpoint = <&aoss_tpda_in1>; 7266 }; 7267 }; 7268 }; 7269 }; 7270 7271 tpdm@10b0b000 { 7272 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7273 reg = <0x0 0x10b0b000 0x0 0x1000>; 7274 7275 clocks = <&aoss_qmp>; 7276 clock-names = "apb_pclk"; 7277 7278 qcom,cmb-element-bits = <64>; 7279 qcom,cmb-msrs-num = <32>; 7280 7281 out-ports { 7282 port { 7283 aoss_tpdm2_out: endpoint { 7284 remote-endpoint = <&aoss_tpda_in2>; 7285 }; 7286 }; 7287 }; 7288 }; 7289 7290 tpdm@10b0c000 { 7291 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7292 reg = <0x0 0x10b0c000 0x0 0x1000>; 7293 7294 clocks = <&aoss_qmp>; 7295 clock-names = "apb_pclk"; 7296 7297 qcom,cmb-element-bits = <64>; 7298 qcom,cmb-msrs-num = <32>; 7299 7300 out-ports { 7301 port { 7302 aoss_tpdm3_out: endpoint { 7303 remote-endpoint = <&aoss_tpda_in3>; 7304 }; 7305 }; 7306 }; 7307 }; 7308 7309 tpdm@10b0d000 { 7310 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7311 reg = <0x0 0x10b0d000 0x0 0x1000>; 7312 7313 clocks = <&aoss_qmp>; 7314 clock-names = "apb_pclk"; 7315 7316 qcom,dsb-element-bits = <32>; 7317 qcom,dsb-msrs-num = <32>; 7318 7319 out-ports { 7320 port { 7321 aoss_tpdm4_out: endpoint { 7322 remote-endpoint = <&aoss_tpda_in4>; 7323 }; 7324 }; 7325 }; 7326 }; 7327 7328 tpdm@10b20000 { 7329 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7330 reg = <0x0 0x10b20000 0x0 0x1000>; 7331 7332 clocks = <&aoss_qmp>; 7333 clock-names = "apb_pclk"; 7334 7335 qcom,dsb-element-bits = <32>; 7336 qcom,dsb-msrs-num = <32>; 7337 status = "disabled"; 7338 7339 out-ports { 7340 port { 7341 lpicc_tpdm_out: endpoint { 7342 remote-endpoint = <&ddr_lpi_tpda_in>; 7343 }; 7344 }; 7345 }; 7346 }; 7347 7348 tpda@10b23000 { 7349 compatible = "qcom,coresight-tpda", "arm,primecell"; 7350 reg = <0x0 0x10b23000 0x0 0x1000>; 7351 7352 clocks = <&aoss_qmp>; 7353 clock-names = "apb_pclk"; 7354 status = "disabled"; 7355 7356 in-ports { 7357 port { 7358 ddr_lpi_tpda_in: endpoint { 7359 remote-endpoint = <&lpicc_tpdm_out>; 7360 }; 7361 }; 7362 }; 7363 7364 out-ports { 7365 port { 7366 ddr_lpi_tpda_out: endpoint { 7367 remote-endpoint = <&ddr_lpi_funnel_in0>; 7368 }; 7369 }; 7370 }; 7371 }; 7372 7373 funnel@10b24000 { 7374 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7375 reg = <0x0 0x10b24000 0x0 0x1000>; 7376 7377 clocks = <&aoss_qmp>; 7378 clock-names = "apb_pclk"; 7379 status = "disabled"; 7380 7381 in-ports { 7382 port { 7383 ddr_lpi_funnel_in0: endpoint { 7384 remote-endpoint = <&ddr_lpi_tpda_out>; 7385 }; 7386 }; 7387 }; 7388 7389 out-ports { 7390 port { 7391 ddr_lpi_funnel_out: endpoint { 7392 remote-endpoint = <&aoss_funnel_in3>; 7393 }; 7394 }; 7395 }; 7396 }; 7397 7398 tpdm@10c08000 { 7399 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7400 reg = <0x0 0x10c08000 0x0 0x1000>; 7401 7402 clocks = <&aoss_qmp>; 7403 clock-names = "apb_pclk"; 7404 7405 qcom,dsb-element-bits = <32>; 7406 qcom,dsb-msrs-num = <32>; 7407 7408 out-ports { 7409 port { 7410 mm_tpdm_out: endpoint { 7411 remote-endpoint = <&mm_funnel_in4>; 7412 }; 7413 }; 7414 }; 7415 }; 7416 7417 funnel@10c0b000 { 7418 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7419 reg = <0x0 0x10c0b000 0x0 0x1000>; 7420 7421 clocks = <&aoss_qmp>; 7422 clock-names = "apb_pclk"; 7423 7424 in-ports { 7425 #address-cells = <1>; 7426 #size-cells = <0>; 7427 7428 port@4 { 7429 reg = <4>; 7430 7431 mm_funnel_in4: endpoint { 7432 remote-endpoint = <&mm_tpdm_out>; 7433 }; 7434 }; 7435 }; 7436 7437 out-ports { 7438 port { 7439 mm_funnel_out: endpoint { 7440 remote-endpoint = <&dlct2_tpda_in4>; 7441 }; 7442 }; 7443 }; 7444 }; 7445 7446 tpdm@10c28000 { 7447 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7448 reg = <0x0 0x10c28000 0x0 0x1000>; 7449 7450 clocks = <&aoss_qmp>; 7451 clock-names = "apb_pclk"; 7452 7453 qcom,dsb-element-bits = <32>; 7454 qcom,dsb-msrs-num = <32>; 7455 7456 out-ports { 7457 port { 7458 dlct1_tpdm_out: endpoint { 7459 remote-endpoint = <&dlct1_tpda_in26>; 7460 }; 7461 }; 7462 }; 7463 }; 7464 7465 tpdm@10c29000 { 7466 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7467 reg = <0x0 0x10c29000 0x0 0x1000>; 7468 7469 clocks = <&aoss_qmp>; 7470 clock-names = "apb_pclk"; 7471 7472 qcom,cmb-element-bits = <64>; 7473 qcom,cmb-msrs-num = <32>; 7474 7475 out-ports { 7476 port { 7477 ipcc_tpdm_out: endpoint { 7478 remote-endpoint = <&dlct1_tpda_in27>; 7479 }; 7480 }; 7481 }; 7482 }; 7483 7484 tpda@10c2b000 { 7485 compatible = "qcom,coresight-tpda", "arm,primecell"; 7486 reg = <0x0 0x10c2b000 0x0 0x1000>; 7487 7488 clocks = <&aoss_qmp>; 7489 clock-names = "apb_pclk"; 7490 7491 in-ports { 7492 #address-cells = <1>; 7493 #size-cells = <0>; 7494 7495 port@4 { 7496 reg = <4>; 7497 7498 dlct1_tpda_in4: endpoint { 7499 remote-endpoint = <&lpass_cx_funnel_out>; 7500 }; 7501 }; 7502 7503 port@13 { 7504 reg = <19>; 7505 7506 dlct1_tpda_in19: endpoint { 7507 remote-endpoint = <&prng_tpdm_out>; 7508 }; 7509 }; 7510 7511 port@14 { 7512 reg = <20>; 7513 7514 dlct1_tpda_in20: endpoint { 7515 remote-endpoint = <&qm_tpdm_out>; 7516 }; 7517 }; 7518 7519 port@15 { 7520 reg = <21>; 7521 7522 dlct1_tpda_in21: endpoint { 7523 remote-endpoint = <&gcc_tpdm_out>; 7524 }; 7525 }; 7526 7527 port@1a { 7528 reg = <26>; 7529 7530 dlct1_tpda_in26: endpoint { 7531 remote-endpoint = <&dlct1_tpdm_out>; 7532 }; 7533 }; 7534 7535 port@1b { 7536 reg = <27>; 7537 7538 dlct1_tpda_in27: endpoint { 7539 remote-endpoint = <&ipcc_tpdm_out>; 7540 }; 7541 }; 7542 }; 7543 7544 out-ports { 7545 port { 7546 dlct1_tpda_out: endpoint { 7547 remote-endpoint = <&dlct1_funnel_in0>; 7548 }; 7549 }; 7550 }; 7551 }; 7552 7553 funnel@10c2c000 { 7554 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7555 reg = <0x0 0x10c2c000 0x0 0x1000>; 7556 7557 clocks = <&aoss_qmp>; 7558 clock-names = "apb_pclk"; 7559 7560 in-ports { 7561 #address-cells = <1>; 7562 #size-cells = <0>; 7563 7564 port@0 { 7565 reg = <0>; 7566 7567 dlct1_funnel_in0: endpoint { 7568 remote-endpoint = <&dlct1_tpda_out>; 7569 }; 7570 }; 7571 7572 port@4 { 7573 reg = <4>; 7574 7575 dlct1_funnel_in4: endpoint { 7576 remote-endpoint = <&dlct2_funnel_out>; 7577 }; 7578 }; 7579 7580 port@5 { 7581 reg = <5>; 7582 7583 dlct1_funnel_in5: endpoint { 7584 remote-endpoint = <&ddr_funnel0_out>; 7585 }; 7586 }; 7587 }; 7588 7589 out-ports { 7590 port { 7591 dlct1_funnel_out: endpoint { 7592 remote-endpoint = <&funnel1_in6>; 7593 }; 7594 }; 7595 }; 7596 }; 7597 7598 tpdm@10c38000 { 7599 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7600 reg = <0x0 0x10c38000 0x0 0x1000>; 7601 7602 clocks = <&aoss_qmp>; 7603 clock-names = "apb_pclk"; 7604 7605 qcom,cmb-element-bits = <64>; 7606 qcom,cmb-msrs-num = <32>; 7607 7608 out-ports { 7609 port { 7610 dlct2_tpdm0_out: endpoint { 7611 remote-endpoint = <&dlct2_tpda_in16>; 7612 }; 7613 }; 7614 }; 7615 }; 7616 7617 tpdm@10c39000 { 7618 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7619 reg = <0x0 0x10c39000 0x0 0x1000>; 7620 7621 clocks = <&aoss_qmp>; 7622 clock-names = "apb_pclk"; 7623 7624 qcom,cmb-element-bits = <64>; 7625 qcom,cmb-msrs-num = <32>; 7626 7627 out-ports { 7628 port { 7629 dlct2_tpdm1_out: endpoint { 7630 remote-endpoint = <&dlct2_tpda_in17>; 7631 }; 7632 }; 7633 }; 7634 }; 7635 7636 tpda@10c3c000 { 7637 compatible = "qcom,coresight-tpda", "arm,primecell"; 7638 reg = <0x0 0x10c3c000 0x0 0x1000>; 7639 7640 clocks = <&aoss_qmp>; 7641 clock-names = "apb_pclk"; 7642 7643 in-ports { 7644 #address-cells = <1>; 7645 #size-cells = <0>; 7646 7647 port@4 { 7648 reg = <4>; 7649 7650 dlct2_tpda_in4: endpoint { 7651 remote-endpoint = <&mm_funnel_out>; 7652 }; 7653 }; 7654 7655 port@f { 7656 reg = <15>; 7657 7658 dlct2_tpda_in15: endpoint { 7659 remote-endpoint = <&mxa_tpdm_out>; 7660 }; 7661 }; 7662 7663 port@10 { 7664 reg = <16>; 7665 7666 dlct2_tpda_in16: endpoint { 7667 remote-endpoint = <&dlct2_tpdm0_out>; 7668 }; 7669 }; 7670 7671 port@11 { 7672 reg = <17>; 7673 7674 dlct2_tpda_in17: endpoint { 7675 remote-endpoint = <&dlct2_tpdm1_out>; 7676 }; 7677 }; 7678 }; 7679 7680 out-ports { 7681 port { 7682 dlct2_tpda_out: endpoint { 7683 remote-endpoint = <&dlct2_funnel_in0>; 7684 }; 7685 }; 7686 }; 7687 }; 7688 7689 funnel@10c3d000 { 7690 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7691 reg = <0x0 0x10c3d000 0x0 0x1000>; 7692 7693 clocks = <&aoss_qmp>; 7694 clock-names = "apb_pclk"; 7695 7696 in-ports { 7697 port { 7698 dlct2_funnel_in0: endpoint { 7699 remote-endpoint = <&dlct2_tpda_out>; 7700 }; 7701 }; 7702 }; 7703 7704 out-ports { 7705 port { 7706 dlct2_funnel_out: endpoint { 7707 remote-endpoint = <&dlct1_funnel_in4>; 7708 }; 7709 }; 7710 }; 7711 }; 7712 7713 tpdm@10cc1000 { 7714 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7715 reg = <0x0 0x10cc1000 0x0 0x1000>; 7716 7717 clocks = <&aoss_qmp>; 7718 clock-names = "apb_pclk"; 7719 7720 qcom,cmb-element-bits = <64>; 7721 qcom,cmb-msrs-num = <32>; 7722 qcom,dsb-element-bits = <32>; 7723 qcom,dsb-msrs-num = <32>; 7724 status = "disabled"; 7725 7726 out-ports { 7727 port { 7728 tmess_tpdm1_out: endpoint { 7729 remote-endpoint = <&tmess_tpda_in2>; 7730 }; 7731 }; 7732 }; 7733 }; 7734 7735 tpda@10cc4000 { 7736 compatible = "qcom,coresight-tpda", "arm,primecell"; 7737 reg = <0x0 0x10cc4000 0x0 0x1000>; 7738 7739 clocks = <&aoss_qmp>; 7740 clock-names = "apb_pclk"; 7741 7742 in-ports { 7743 #address-cells = <1>; 7744 #size-cells = <0>; 7745 7746 port@2 { 7747 reg = <2>; 7748 7749 tmess_tpda_in2: endpoint { 7750 remote-endpoint = <&tmess_tpdm1_out>; 7751 }; 7752 }; 7753 }; 7754 7755 out-ports { 7756 port { 7757 tmess_tpda_out: endpoint { 7758 remote-endpoint = <&tmess_funnel_in0>; 7759 }; 7760 }; 7761 }; 7762 }; 7763 7764 funnel@10cc5000 { 7765 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7766 reg = <0x0 0x10cc5000 0x0 0x1000>; 7767 7768 clocks = <&aoss_qmp>; 7769 clock-names = "apb_pclk"; 7770 7771 in-ports { 7772 port { 7773 tmess_funnel_in0: endpoint { 7774 remote-endpoint = <&tmess_tpda_out>; 7775 }; 7776 }; 7777 }; 7778 7779 out-ports { 7780 port { 7781 tmess_funnel_out: endpoint { 7782 remote-endpoint = <&funnel1_in2>; 7783 }; 7784 }; 7785 }; 7786 }; 7787 7788 funnel@10d04000 { 7789 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7790 reg = <0x0 0x10d04000 0x0 0x1000>; 7791 7792 clocks = <&aoss_qmp>; 7793 clock-names = "apb_pclk"; 7794 7795 in-ports { 7796 #address-cells = <1>; 7797 #size-cells = <0>; 7798 7799 port@6 { 7800 reg = <6>; 7801 7802 ddr_funnel0_in6: endpoint { 7803 remote-endpoint = <&ddr_funnel1_out>; 7804 }; 7805 }; 7806 }; 7807 7808 out-ports { 7809 port { 7810 ddr_funnel0_out: endpoint { 7811 remote-endpoint = <&dlct1_funnel_in5>; 7812 }; 7813 }; 7814 }; 7815 }; 7816 7817 tpdm@10d08000 { 7818 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7819 reg = <0x0 0x10d08000 0x0 0x1000>; 7820 7821 clocks = <&aoss_qmp>; 7822 clock-names = "apb_pclk"; 7823 7824 qcom,cmb-element-bits = <32>; 7825 qcom,cmb-msrs-num = <32>; 7826 7827 out-ports { 7828 port { 7829 llcc0_tpdm_out: endpoint { 7830 remote-endpoint = <&llcc_tpda_in0>; 7831 }; 7832 }; 7833 }; 7834 }; 7835 7836 tpdm@10d09000 { 7837 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7838 reg = <0x0 0x10d09000 0x0 0x1000>; 7839 7840 clocks = <&aoss_qmp>; 7841 clock-names = "apb_pclk"; 7842 7843 qcom,cmb-element-bits = <32>; 7844 qcom,cmb-msrs-num = <32>; 7845 7846 out-ports { 7847 port { 7848 llcc1_tpdm_out: endpoint { 7849 remote-endpoint = <&llcc_tpda_in1>; 7850 }; 7851 }; 7852 }; 7853 }; 7854 7855 tpdm@10d0a000 { 7856 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7857 reg = <0x0 0x10d0a000 0x0 0x1000>; 7858 7859 clocks = <&aoss_qmp>; 7860 clock-names = "apb_pclk"; 7861 7862 qcom,cmb-element-bits = <32>; 7863 qcom,cmb-msrs-num = <32>; 7864 7865 out-ports { 7866 port { 7867 llcc2_tpdm_out: endpoint { 7868 remote-endpoint = <&llcc_tpda_in2>; 7869 }; 7870 }; 7871 }; 7872 }; 7873 7874 tpdm@10d0b000 { 7875 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7876 reg = <0x0 0x10d0b000 0x0 0x1000>; 7877 7878 clocks = <&aoss_qmp>; 7879 clock-names = "apb_pclk"; 7880 7881 qcom,cmb-element-bits = <32>; 7882 qcom,cmb-msrs-num = <32>; 7883 7884 out-ports { 7885 port { 7886 llcc3_tpdm_out: endpoint { 7887 remote-endpoint = <&llcc_tpda_in3>; 7888 }; 7889 }; 7890 }; 7891 }; 7892 7893 tpdm@10d0c000 { 7894 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7895 reg = <0x0 0x10d0c000 0x0 0x1000>; 7896 7897 clocks = <&aoss_qmp>; 7898 clock-names = "apb_pclk"; 7899 7900 qcom,cmb-element-bits = <32>; 7901 qcom,cmb-msrs-num = <32>; 7902 7903 out-ports { 7904 port { 7905 llcc4_tpdm_out: endpoint { 7906 remote-endpoint = <&llcc_tpda_in4>; 7907 }; 7908 }; 7909 }; 7910 }; 7911 7912 tpdm@10d0d000 { 7913 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7914 reg = <0x0 0x10d0d000 0x0 0x1000>; 7915 7916 clocks = <&aoss_qmp>; 7917 clock-names = "apb_pclk"; 7918 7919 qcom,cmb-element-bits = <32>; 7920 qcom,cmb-msrs-num = <32>; 7921 7922 out-ports { 7923 port { 7924 llcc5_tpdm_out: endpoint { 7925 remote-endpoint = <&llcc_tpda_in5>; 7926 }; 7927 }; 7928 }; 7929 }; 7930 7931 tpdm@10d0e000 { 7932 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7933 reg = <0x0 0x10d0e000 0x0 0x1000>; 7934 7935 clocks = <&aoss_qmp>; 7936 clock-names = "apb_pclk"; 7937 7938 qcom,cmb-element-bits = <32>; 7939 qcom,cmb-msrs-num = <32>; 7940 7941 out-ports { 7942 port { 7943 llcc6_tpdm_out: endpoint { 7944 remote-endpoint = <&llcc_tpda_in6>; 7945 }; 7946 }; 7947 }; 7948 }; 7949 7950 tpdm@10d0f000 { 7951 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7952 reg = <0x0 0x10d0f000 0x0 0x1000>; 7953 7954 clocks = <&aoss_qmp>; 7955 clock-names = "apb_pclk"; 7956 7957 qcom,cmb-element-bits = <32>; 7958 qcom,cmb-msrs-num = <32>; 7959 7960 out-ports { 7961 port { 7962 llcc7_tpdm_out: endpoint { 7963 remote-endpoint = <&llcc_tpda_in7>; 7964 }; 7965 }; 7966 }; 7967 }; 7968 7969 tpda@10d12000 { 7970 compatible = "qcom,coresight-tpda", "arm,primecell"; 7971 reg = <0x0 0x10d12000 0x0 0x1000>; 7972 7973 clocks = <&aoss_qmp>; 7974 clock-names = "apb_pclk"; 7975 7976 in-ports { 7977 #address-cells = <1>; 7978 #size-cells = <0>; 7979 7980 port@0 { 7981 reg = <0>; 7982 7983 llcc_tpda_in0: endpoint { 7984 remote-endpoint = <&llcc0_tpdm_out>; 7985 }; 7986 }; 7987 7988 port@1 { 7989 reg = <1>; 7990 7991 llcc_tpda_in1: endpoint { 7992 remote-endpoint = <&llcc1_tpdm_out>; 7993 }; 7994 }; 7995 7996 port@2 { 7997 reg = <2>; 7998 7999 llcc_tpda_in2: endpoint { 8000 remote-endpoint = <&llcc2_tpdm_out>; 8001 }; 8002 }; 8003 8004 port@3 { 8005 reg = <3>; 8006 8007 llcc_tpda_in3: endpoint { 8008 remote-endpoint = <&llcc3_tpdm_out>; 8009 }; 8010 }; 8011 8012 port@4 { 8013 reg = <4>; 8014 8015 llcc_tpda_in4: endpoint { 8016 remote-endpoint = <&llcc4_tpdm_out>; 8017 }; 8018 }; 8019 8020 port@5 { 8021 reg = <5>; 8022 8023 llcc_tpda_in5: endpoint { 8024 remote-endpoint = <&llcc5_tpdm_out>; 8025 }; 8026 }; 8027 8028 port@6 { 8029 reg = <6>; 8030 8031 llcc_tpda_in6: endpoint { 8032 remote-endpoint = <&llcc6_tpdm_out>; 8033 }; 8034 }; 8035 8036 port@7 { 8037 reg = <7>; 8038 8039 llcc_tpda_in7: endpoint { 8040 remote-endpoint = <&llcc7_tpdm_out>; 8041 }; 8042 }; 8043 }; 8044 8045 out-ports { 8046 port { 8047 llcc_tpda_out: endpoint { 8048 remote-endpoint = <&ddr_funnel1_in0>; 8049 }; 8050 }; 8051 }; 8052 }; 8053 8054 funnel@10d13000 { 8055 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 8056 reg = <0x0 0x10d13000 0x0 0x1000>; 8057 8058 clocks = <&aoss_qmp>; 8059 clock-names = "apb_pclk"; 8060 8061 in-ports { 8062 port { 8063 ddr_funnel1_in0: endpoint { 8064 remote-endpoint = <&llcc_tpda_out>; 8065 }; 8066 }; 8067 }; 8068 8069 out-ports { 8070 port { 8071 ddr_funnel1_out: endpoint { 8072 remote-endpoint = <&ddr_funnel0_in6>; 8073 }; 8074 }; 8075 }; 8076 }; 8077 8078 apps_smmu: iommu@15000000 { 8079 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 8080 reg = <0 0x15000000 0 0x100000>; 8081 8082 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 8083 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 8084 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 8085 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 8086 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 8087 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 8088 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 8089 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 8090 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 8091 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 8092 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 8093 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 8094 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 8095 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 8096 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 8097 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 8098 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 8099 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 8100 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 8101 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 8102 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 8103 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 8104 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 8105 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 8106 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 8107 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 8108 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 8109 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 8110 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 8111 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 8112 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 8113 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 8114 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 8115 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 8116 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 8117 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 8118 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 8119 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 8120 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 8121 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 8122 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 8123 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 8124 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 8125 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 8126 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 8127 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 8128 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 8129 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 8130 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 8131 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 8132 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 8133 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 8134 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 8135 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 8136 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 8137 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 8138 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 8139 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 8140 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 8141 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 8142 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 8143 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 8144 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 8145 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 8146 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 8147 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 8148 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 8149 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 8150 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 8151 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 8152 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 8153 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 8154 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 8155 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 8156 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 8157 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 8158 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 8159 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 8160 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 8161 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 8162 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 8163 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 8164 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 8165 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 8166 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 8167 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 8168 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 8169 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 8170 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 8171 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 8172 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 8173 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 8174 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 8175 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 8176 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 8177 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 8178 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 8179 8180 #iommu-cells = <2>; 8181 #global-interrupts = <1>; 8182 8183 dma-coherent; 8184 }; 8185 8186 pcie_smmu: iommu@15400000 { 8187 compatible = "arm,smmu-v3"; 8188 reg = <0 0x15400000 0 0x80000>; 8189 #iommu-cells = <1>; 8190 interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 8191 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 8192 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>; 8193 interrupt-names = "eventq", 8194 "gerror", 8195 "cmdq-sync"; 8196 dma-coherent; 8197 status = "reserved"; /* Controlled by Gunyah. */ 8198 }; 8199 8200 intc: interrupt-controller@17000000 { 8201 compatible = "arm,gic-v3"; 8202 reg = <0 0x17000000 0 0x10000>, /* GICD */ 8203 <0 0x17080000 0 0x300000>; /* GICR * 12 */ 8204 8205 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 8206 8207 #interrupt-cells = <3>; 8208 interrupt-controller; 8209 8210 #redistributor-regions = <1>; 8211 redistributor-stride = <0x0 0x40000>; 8212 8213 #address-cells = <2>; 8214 #size-cells = <2>; 8215 ranges; 8216 8217 gic_its: msi-controller@17040000 { 8218 compatible = "arm,gic-v3-its"; 8219 reg = <0 0x17040000 0 0x40000>; 8220 8221 msi-controller; 8222 #msi-cells = <1>; 8223 }; 8224 }; 8225 8226 cpucp_mbox: mailbox@17430000 { 8227 compatible = "qcom,x1e80100-cpucp-mbox"; 8228 reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>; 8229 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 8230 #mbox-cells = <1>; 8231 }; 8232 8233 apps_rsc: rsc@17500000 { 8234 compatible = "qcom,rpmh-rsc"; 8235 reg = <0 0x17500000 0 0x10000>, 8236 <0 0x17510000 0 0x10000>, 8237 <0 0x17520000 0 0x10000>; 8238 reg-names = "drv-0", "drv-1", "drv-2"; 8239 8240 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 8241 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 8242 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 8243 qcom,tcs-offset = <0xd00>; 8244 qcom,drv-id = <2>; 8245 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 8246 <WAKE_TCS 2>, <CONTROL_TCS 0>; 8247 8248 label = "apps_rsc"; 8249 power-domains = <&system_pd>; 8250 8251 apps_bcm_voter: bcm-voter { 8252 compatible = "qcom,bcm-voter"; 8253 }; 8254 8255 rpmhcc: clock-controller { 8256 compatible = "qcom,x1e80100-rpmh-clk"; 8257 8258 clocks = <&xo_board>; 8259 clock-names = "xo"; 8260 8261 #clock-cells = <1>; 8262 }; 8263 8264 rpmhpd: power-controller { 8265 compatible = "qcom,x1e80100-rpmhpd"; 8266 8267 operating-points-v2 = <&rpmhpd_opp_table>; 8268 8269 #power-domain-cells = <1>; 8270 8271 rpmhpd_opp_table: opp-table { 8272 compatible = "operating-points-v2"; 8273 8274 rpmhpd_opp_ret: opp-16 { 8275 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 8276 }; 8277 8278 rpmhpd_opp_min_svs: opp-48 { 8279 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 8280 }; 8281 8282 rpmhpd_opp_low_svs_d2: opp-52 { 8283 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 8284 }; 8285 8286 rpmhpd_opp_low_svs_d1: opp-56 { 8287 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 8288 }; 8289 8290 rpmhpd_opp_low_svs_d0: opp-60 { 8291 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 8292 }; 8293 8294 rpmhpd_opp_low_svs: opp-64 { 8295 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 8296 }; 8297 8298 rpmhpd_opp_low_svs_l1: opp-80 { 8299 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 8300 }; 8301 8302 rpmhpd_opp_svs: opp-128 { 8303 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 8304 }; 8305 8306 rpmhpd_opp_svs_l0: opp-144 { 8307 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 8308 }; 8309 8310 rpmhpd_opp_svs_l1: opp-192 { 8311 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 8312 }; 8313 8314 rpmhpd_opp_nom: opp-256 { 8315 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 8316 }; 8317 8318 rpmhpd_opp_nom_l1: opp-320 { 8319 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 8320 }; 8321 8322 rpmhpd_opp_nom_l2: opp-336 { 8323 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 8324 }; 8325 8326 rpmhpd_opp_turbo: opp-384 { 8327 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 8328 }; 8329 8330 rpmhpd_opp_turbo_l1: opp-416 { 8331 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 8332 }; 8333 }; 8334 }; 8335 }; 8336 8337 timer@17800000 { 8338 compatible = "arm,armv7-timer-mem"; 8339 reg = <0 0x17800000 0 0x1000>; 8340 8341 #address-cells = <2>; 8342 #size-cells = <1>; 8343 ranges = <0 0 0 0 0x20000000>; 8344 8345 frame@17801000 { 8346 reg = <0 0x17801000 0x1000>, 8347 <0 0x17802000 0x1000>; 8348 8349 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 8350 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 8351 8352 frame-number = <0>; 8353 }; 8354 8355 frame@17803000 { 8356 reg = <0 0x17803000 0x1000>; 8357 8358 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 8359 8360 frame-number = <1>; 8361 8362 status = "disabled"; 8363 }; 8364 8365 frame@17805000 { 8366 reg = <0 0x17805000 0x1000>; 8367 8368 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 8369 8370 frame-number = <2>; 8371 8372 status = "disabled"; 8373 }; 8374 8375 frame@17807000 { 8376 reg = <0 0x17807000 0x1000>; 8377 8378 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 8379 8380 frame-number = <3>; 8381 8382 status = "disabled"; 8383 }; 8384 8385 frame@17809000 { 8386 reg = <0 0x17809000 0x1000>; 8387 8388 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 8389 8390 frame-number = <4>; 8391 8392 status = "disabled"; 8393 }; 8394 8395 frame@1780b000 { 8396 reg = <0 0x1780b000 0x1000>; 8397 8398 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 8399 8400 frame-number = <5>; 8401 8402 status = "disabled"; 8403 }; 8404 8405 frame@1780d000 { 8406 reg = <0 0x1780d000 0x1000>; 8407 8408 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 8409 8410 frame-number = <6>; 8411 8412 status = "disabled"; 8413 }; 8414 }; 8415 8416 sram: sram@18b4e000 { 8417 compatible = "mmio-sram"; 8418 reg = <0x0 0x18b4e000 0x0 0x400>; 8419 8420 #address-cells = <1>; 8421 #size-cells = <1>; 8422 ranges = <0x0 0x0 0x18b4e000 0x400>; 8423 8424 cpu_scp_lpri0: scp-sram-section@0 { 8425 compatible = "arm,scmi-shmem"; 8426 reg = <0x0 0x200>; 8427 }; 8428 8429 cpu_scp_lpri1: scp-sram-section@200 { 8430 compatible = "arm,scmi-shmem"; 8431 reg = <0x200 0x200>; 8432 }; 8433 }; 8434 8435 sbsa_watchdog: watchdog@1c840000 { 8436 compatible = "arm,sbsa-gwdt"; 8437 reg = <0 0x1c840000 0 0x1000>, 8438 <0 0x1c850000 0 0x1000>; 8439 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 8440 }; 8441 8442 qfprom: efuse@221c8000 { 8443 compatible = "qcom,x1e80100-qfprom", "qcom,qfprom"; 8444 reg = <0 0x221c8000 0 0x1000>; 8445 #address-cells = <1>; 8446 #size-cells = <1>; 8447 8448 gpu_speed_bin: gpu-speed-bin@119 { 8449 reg = <0x119 0x2>; 8450 bits = <7 8>; 8451 }; 8452 }; 8453 8454 pmu@24091000 { 8455 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 8456 reg = <0 0x24091000 0 0x1000>; 8457 8458 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 8459 8460 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 8461 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 8462 8463 operating-points-v2 = <&llcc_bwmon_opp_table>; 8464 8465 llcc_bwmon_opp_table: opp-table { 8466 compatible = "operating-points-v2"; 8467 8468 opp-0 { 8469 opp-peak-kBps = <800000>; 8470 }; 8471 8472 opp-1 { 8473 opp-peak-kBps = <2188000>; 8474 }; 8475 8476 opp-2 { 8477 opp-peak-kBps = <3072000>; 8478 }; 8479 8480 opp-3 { 8481 opp-peak-kBps = <6220800>; 8482 }; 8483 8484 opp-4 { 8485 opp-peak-kBps = <6835200>; 8486 }; 8487 8488 opp-5 { 8489 opp-peak-kBps = <8371200>; 8490 }; 8491 8492 opp-6 { 8493 opp-peak-kBps = <10944000>; 8494 }; 8495 8496 opp-7 { 8497 opp-peak-kBps = <12748800>; 8498 }; 8499 8500 opp-8 { 8501 opp-peak-kBps = <14745600>; 8502 }; 8503 8504 opp-9 { 8505 opp-peak-kBps = <16896000>; 8506 }; 8507 }; 8508 }; 8509 8510 /* cluster0 */ 8511 bwmon_cluster0: pmu@240b3400 { 8512 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8513 reg = <0 0x240b3400 0 0x600>; 8514 8515 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8516 8517 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8518 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8519 8520 operating-points-v2 = <&cpu_bwmon_opp_table>; 8521 }; 8522 8523 /* cluster2 */ 8524 bwmon_cluster2: pmu@240b5400 { 8525 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8526 reg = <0 0x240b5400 0 0x600>; 8527 8528 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8529 8530 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8531 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8532 8533 operating-points-v2 = <&cpu_bwmon_opp_table>; 8534 8535 cpu_bwmon_opp_table: opp-table { 8536 compatible = "operating-points-v2"; 8537 8538 opp-0 { 8539 opp-peak-kBps = <4800000>; 8540 }; 8541 8542 opp-1 { 8543 opp-peak-kBps = <7464000>; 8544 }; 8545 8546 opp-2 { 8547 opp-peak-kBps = <9600000>; 8548 }; 8549 8550 opp-3 { 8551 opp-peak-kBps = <12896000>; 8552 }; 8553 8554 opp-4 { 8555 opp-peak-kBps = <14928000>; 8556 }; 8557 8558 opp-5 { 8559 opp-peak-kBps = <17064000>; 8560 }; 8561 }; 8562 }; 8563 8564 /* cluster1 */ 8565 pmu@240b6400 { 8566 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8567 reg = <0 0x240b6400 0 0x600>; 8568 8569 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8570 8571 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8572 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8573 8574 operating-points-v2 = <&cpu_bwmon_opp_table>; 8575 }; 8576 8577 system-cache-controller@25000000 { 8578 compatible = "qcom,x1e80100-llcc"; 8579 reg = <0 0x25000000 0 0x200000>, 8580 <0 0x25200000 0 0x200000>, 8581 <0 0x25400000 0 0x200000>, 8582 <0 0x25600000 0 0x200000>, 8583 <0 0x25800000 0 0x200000>, 8584 <0 0x25a00000 0 0x200000>, 8585 <0 0x25c00000 0 0x200000>, 8586 <0 0x25e00000 0 0x200000>, 8587 <0 0x26000000 0 0x200000>, 8588 <0 0x26200000 0 0x200000>; 8589 reg-names = "llcc0_base", 8590 "llcc1_base", 8591 "llcc2_base", 8592 "llcc3_base", 8593 "llcc4_base", 8594 "llcc5_base", 8595 "llcc6_base", 8596 "llcc7_base", 8597 "llcc_broadcast_base", 8598 "llcc_broadcast_and_base"; 8599 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 8600 }; 8601 8602 remoteproc_cdsp: remoteproc@32300000 { 8603 compatible = "qcom,x1e80100-cdsp-pas"; 8604 reg = <0x0 0x32300000 0x0 0x10000>; 8605 8606 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 8607 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 8608 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 8609 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 8610 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 8611 interrupt-names = "wdog", 8612 "fatal", 8613 "ready", 8614 "handover", 8615 "stop-ack"; 8616 8617 clocks = <&rpmhcc RPMH_CXO_CLK>; 8618 clock-names = "xo"; 8619 8620 power-domains = <&rpmhpd RPMHPD_CX>, 8621 <&rpmhpd RPMHPD_MXC>, 8622 <&rpmhpd RPMHPD_NSP>; 8623 power-domain-names = "cx", 8624 "mxc", 8625 "nsp"; 8626 8627 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 8628 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 8629 8630 memory-region = <&cdsp_mem>, 8631 <&q6_cdsp_dtb_mem>; 8632 8633 qcom,qmp = <&aoss_qmp>; 8634 8635 qcom,smem-states = <&smp2p_cdsp_out 0>; 8636 qcom,smem-state-names = "stop"; 8637 8638 status = "disabled"; 8639 8640 glink-edge { 8641 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 8642 IPCC_MPROC_SIGNAL_GLINK_QMP 8643 IRQ_TYPE_EDGE_RISING>; 8644 mboxes = <&ipcc IPCC_CLIENT_CDSP 8645 IPCC_MPROC_SIGNAL_GLINK_QMP>; 8646 8647 label = "cdsp"; 8648 qcom,remote-pid = <5>; 8649 8650 fastrpc { 8651 compatible = "qcom,fastrpc"; 8652 qcom,glink-channels = "fastrpcglink-apps-dsp"; 8653 label = "cdsp"; 8654 qcom,non-secure-domain; 8655 #address-cells = <1>; 8656 #size-cells = <0>; 8657 8658 compute-cb@1 { 8659 compatible = "qcom,fastrpc-compute-cb"; 8660 reg = <1>; 8661 iommus = <&apps_smmu 0x0c01 0x20>; 8662 dma-coherent; 8663 }; 8664 8665 compute-cb@2 { 8666 compatible = "qcom,fastrpc-compute-cb"; 8667 reg = <2>; 8668 iommus = <&apps_smmu 0x0c02 0x20>; 8669 dma-coherent; 8670 }; 8671 8672 compute-cb@3 { 8673 compatible = "qcom,fastrpc-compute-cb"; 8674 reg = <3>; 8675 iommus = <&apps_smmu 0x0c03 0x20>; 8676 dma-coherent; 8677 }; 8678 8679 compute-cb@4 { 8680 compatible = "qcom,fastrpc-compute-cb"; 8681 reg = <4>; 8682 iommus = <&apps_smmu 0x0c04 0x20>; 8683 dma-coherent; 8684 }; 8685 8686 compute-cb@5 { 8687 compatible = "qcom,fastrpc-compute-cb"; 8688 reg = <5>; 8689 iommus = <&apps_smmu 0x0c05 0x20>; 8690 dma-coherent; 8691 }; 8692 8693 compute-cb@6 { 8694 compatible = "qcom,fastrpc-compute-cb"; 8695 reg = <6>; 8696 iommus = <&apps_smmu 0x0c06 0x20>; 8697 dma-coherent; 8698 }; 8699 8700 compute-cb@7 { 8701 compatible = "qcom,fastrpc-compute-cb"; 8702 reg = <7>; 8703 iommus = <&apps_smmu 0x0c07 0x20>; 8704 dma-coherent; 8705 }; 8706 8707 compute-cb@8 { 8708 compatible = "qcom,fastrpc-compute-cb"; 8709 reg = <8>; 8710 iommus = <&apps_smmu 0x0c08 0x20>; 8711 dma-coherent; 8712 }; 8713 8714 /* note: compute-cb@9 is secure */ 8715 8716 compute-cb@10 { 8717 compatible = "qcom,fastrpc-compute-cb"; 8718 reg = <10>; 8719 iommus = <&apps_smmu 0x0c0c 0x20>; 8720 dma-coherent; 8721 }; 8722 8723 compute-cb@11 { 8724 compatible = "qcom,fastrpc-compute-cb"; 8725 reg = <11>; 8726 iommus = <&apps_smmu 0x0c0d 0x20>; 8727 dma-coherent; 8728 }; 8729 8730 compute-cb@12 { 8731 compatible = "qcom,fastrpc-compute-cb"; 8732 reg = <12>; 8733 iommus = <&apps_smmu 0x0c0e 0x20>; 8734 dma-coherent; 8735 }; 8736 8737 compute-cb@13 { 8738 compatible = "qcom,fastrpc-compute-cb"; 8739 reg = <13>; 8740 iommus = <&apps_smmu 0x0c0f 0x20>; 8741 dma-coherent; 8742 }; 8743 }; 8744 }; 8745 }; 8746 }; 8747 8748 timer { 8749 compatible = "arm,armv8-timer"; 8750 8751 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 8752 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 8753 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 8754 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 8755 }; 8756 8757 thermal_zones: thermal-zones { 8758 aoss0-thermal { 8759 thermal-sensors = <&tsens0 0>; 8760 8761 trips { 8762 trip-point0 { 8763 temperature = <90000>; 8764 hysteresis = <2000>; 8765 type = "hot"; 8766 }; 8767 8768 aoss0-critical { 8769 temperature = <115000>; 8770 hysteresis = <1000>; 8771 type = "critical"; 8772 }; 8773 }; 8774 }; 8775 8776 cpu0-0-top-thermal { 8777 thermal-sensors = <&tsens0 1>; 8778 8779 trips { 8780 cpu-critical { 8781 temperature = <115000>; 8782 hysteresis = <1000>; 8783 type = "critical"; 8784 }; 8785 }; 8786 }; 8787 8788 cpu0-0-btm-thermal { 8789 thermal-sensors = <&tsens0 2>; 8790 8791 trips { 8792 cpu-critical { 8793 temperature = <115000>; 8794 hysteresis = <1000>; 8795 type = "critical"; 8796 }; 8797 }; 8798 }; 8799 8800 cpu0-1-top-thermal { 8801 thermal-sensors = <&tsens0 3>; 8802 8803 trips { 8804 cpu-critical { 8805 temperature = <115000>; 8806 hysteresis = <1000>; 8807 type = "critical"; 8808 }; 8809 }; 8810 }; 8811 8812 cpu0-1-btm-thermal { 8813 thermal-sensors = <&tsens0 4>; 8814 8815 trips { 8816 cpu-critical { 8817 temperature = <115000>; 8818 hysteresis = <1000>; 8819 type = "critical"; 8820 }; 8821 }; 8822 }; 8823 8824 cpu0-2-top-thermal { 8825 thermal-sensors = <&tsens0 5>; 8826 8827 trips { 8828 cpu-critical { 8829 temperature = <115000>; 8830 hysteresis = <1000>; 8831 type = "critical"; 8832 }; 8833 }; 8834 }; 8835 8836 cpu0-2-btm-thermal { 8837 thermal-sensors = <&tsens0 6>; 8838 8839 trips { 8840 cpu-critical { 8841 temperature = <115000>; 8842 hysteresis = <1000>; 8843 type = "critical"; 8844 }; 8845 }; 8846 }; 8847 8848 cpu0-3-top-thermal { 8849 thermal-sensors = <&tsens0 7>; 8850 8851 trips { 8852 cpu-critical { 8853 temperature = <115000>; 8854 hysteresis = <1000>; 8855 type = "critical"; 8856 }; 8857 }; 8858 }; 8859 8860 cpu0-3-btm-thermal { 8861 thermal-sensors = <&tsens0 8>; 8862 8863 trips { 8864 cpu-critical { 8865 temperature = <115000>; 8866 hysteresis = <1000>; 8867 type = "critical"; 8868 }; 8869 }; 8870 }; 8871 8872 cpuss0-top-thermal { 8873 thermal-sensors = <&tsens0 9>; 8874 8875 trips { 8876 cpuss2-critical { 8877 temperature = <115000>; 8878 hysteresis = <1000>; 8879 type = "critical"; 8880 }; 8881 }; 8882 }; 8883 8884 cpuss0-btm-thermal { 8885 thermal-sensors = <&tsens0 10>; 8886 8887 trips { 8888 cpuss2-critical { 8889 temperature = <115000>; 8890 hysteresis = <1000>; 8891 type = "critical"; 8892 }; 8893 }; 8894 }; 8895 8896 mem-thermal { 8897 thermal-sensors = <&tsens0 11>; 8898 8899 trips { 8900 trip-point0 { 8901 temperature = <90000>; 8902 hysteresis = <2000>; 8903 type = "hot"; 8904 }; 8905 8906 mem-critical { 8907 temperature = <115000>; 8908 hysteresis = <0>; 8909 type = "critical"; 8910 }; 8911 }; 8912 }; 8913 8914 video-thermal { 8915 thermal-sensors = <&tsens0 12>; 8916 8917 trips { 8918 trip-point0 { 8919 temperature = <90000>; 8920 hysteresis = <2000>; 8921 type = "hot"; 8922 }; 8923 8924 video-critical { 8925 temperature = <115000>; 8926 hysteresis = <1000>; 8927 type = "critical"; 8928 }; 8929 }; 8930 }; 8931 8932 aoss1-thermal { 8933 thermal-sensors = <&tsens1 0>; 8934 8935 trips { 8936 trip-point0 { 8937 temperature = <90000>; 8938 hysteresis = <2000>; 8939 type = "hot"; 8940 }; 8941 8942 aoss0-critical { 8943 temperature = <115000>; 8944 hysteresis = <1000>; 8945 type = "critical"; 8946 }; 8947 }; 8948 }; 8949 8950 cpu1-0-top-thermal { 8951 thermal-sensors = <&tsens1 1>; 8952 8953 trips { 8954 cpu-critical { 8955 temperature = <115000>; 8956 hysteresis = <1000>; 8957 type = "critical"; 8958 }; 8959 }; 8960 }; 8961 8962 cpu1-0-btm-thermal { 8963 thermal-sensors = <&tsens1 2>; 8964 8965 trips { 8966 cpu-critical { 8967 temperature = <115000>; 8968 hysteresis = <1000>; 8969 type = "critical"; 8970 }; 8971 }; 8972 }; 8973 8974 cpu1-1-top-thermal { 8975 thermal-sensors = <&tsens1 3>; 8976 8977 trips { 8978 cpu-critical { 8979 temperature = <115000>; 8980 hysteresis = <1000>; 8981 type = "critical"; 8982 }; 8983 }; 8984 }; 8985 8986 cpu1-1-btm-thermal { 8987 thermal-sensors = <&tsens1 4>; 8988 8989 trips { 8990 cpu-critical { 8991 temperature = <115000>; 8992 hysteresis = <1000>; 8993 type = "critical"; 8994 }; 8995 }; 8996 }; 8997 8998 cpu1-2-top-thermal { 8999 thermal-sensors = <&tsens1 5>; 9000 9001 trips { 9002 cpu-critical { 9003 temperature = <115000>; 9004 hysteresis = <1000>; 9005 type = "critical"; 9006 }; 9007 }; 9008 }; 9009 9010 cpu1-2-btm-thermal { 9011 thermal-sensors = <&tsens1 6>; 9012 9013 trips { 9014 cpu-critical { 9015 temperature = <115000>; 9016 hysteresis = <1000>; 9017 type = "critical"; 9018 }; 9019 }; 9020 }; 9021 9022 cpu1-3-top-thermal { 9023 thermal-sensors = <&tsens1 7>; 9024 9025 trips { 9026 cpu-critical { 9027 temperature = <115000>; 9028 hysteresis = <1000>; 9029 type = "critical"; 9030 }; 9031 }; 9032 }; 9033 9034 cpu1-3-btm-thermal { 9035 thermal-sensors = <&tsens1 8>; 9036 9037 trips { 9038 cpu-critical { 9039 temperature = <115000>; 9040 hysteresis = <1000>; 9041 type = "critical"; 9042 }; 9043 }; 9044 }; 9045 9046 cpuss1-top-thermal { 9047 thermal-sensors = <&tsens1 9>; 9048 9049 trips { 9050 cpuss2-critical { 9051 temperature = <115000>; 9052 hysteresis = <1000>; 9053 type = "critical"; 9054 }; 9055 }; 9056 }; 9057 9058 cpuss1-btm-thermal { 9059 thermal-sensors = <&tsens1 10>; 9060 9061 trips { 9062 cpuss2-critical { 9063 temperature = <115000>; 9064 hysteresis = <1000>; 9065 type = "critical"; 9066 }; 9067 }; 9068 }; 9069 9070 aoss2-thermal { 9071 thermal-sensors = <&tsens2 0>; 9072 9073 trips { 9074 trip-point0 { 9075 temperature = <90000>; 9076 hysteresis = <2000>; 9077 type = "hot"; 9078 }; 9079 9080 aoss0-critical { 9081 temperature = <115000>; 9082 hysteresis = <1000>; 9083 type = "critical"; 9084 }; 9085 }; 9086 }; 9087 9088 cpu2-0-top-thermal { 9089 thermal-sensors = <&tsens2 1>; 9090 9091 trips { 9092 cpu-critical { 9093 temperature = <115000>; 9094 hysteresis = <1000>; 9095 type = "critical"; 9096 }; 9097 }; 9098 }; 9099 9100 cpu2-0-btm-thermal { 9101 thermal-sensors = <&tsens2 2>; 9102 9103 trips { 9104 cpu-critical { 9105 temperature = <115000>; 9106 hysteresis = <1000>; 9107 type = "critical"; 9108 }; 9109 }; 9110 }; 9111 9112 cpu2-1-top-thermal { 9113 thermal-sensors = <&tsens2 3>; 9114 9115 trips { 9116 cpu-critical { 9117 temperature = <115000>; 9118 hysteresis = <1000>; 9119 type = "critical"; 9120 }; 9121 }; 9122 }; 9123 9124 cpu2-1-btm-thermal { 9125 thermal-sensors = <&tsens2 4>; 9126 9127 trips { 9128 cpu-critical { 9129 temperature = <115000>; 9130 hysteresis = <1000>; 9131 type = "critical"; 9132 }; 9133 }; 9134 }; 9135 9136 cpu2-2-top-thermal { 9137 thermal-sensors = <&tsens2 5>; 9138 9139 trips { 9140 cpu-critical { 9141 temperature = <115000>; 9142 hysteresis = <1000>; 9143 type = "critical"; 9144 }; 9145 }; 9146 }; 9147 9148 cpu2-2-btm-thermal { 9149 thermal-sensors = <&tsens2 6>; 9150 9151 trips { 9152 cpu-critical { 9153 temperature = <115000>; 9154 hysteresis = <1000>; 9155 type = "critical"; 9156 }; 9157 }; 9158 }; 9159 9160 cpu2-3-top-thermal { 9161 thermal-sensors = <&tsens2 7>; 9162 9163 trips { 9164 cpu-critical { 9165 temperature = <115000>; 9166 hysteresis = <1000>; 9167 type = "critical"; 9168 }; 9169 }; 9170 }; 9171 9172 cpu2-3-btm-thermal { 9173 thermal-sensors = <&tsens2 8>; 9174 9175 trips { 9176 cpu-critical { 9177 temperature = <115000>; 9178 hysteresis = <1000>; 9179 type = "critical"; 9180 }; 9181 }; 9182 }; 9183 9184 cpuss2-top-thermal { 9185 thermal-sensors = <&tsens2 9>; 9186 9187 trips { 9188 cpuss2-critical { 9189 temperature = <115000>; 9190 hysteresis = <1000>; 9191 type = "critical"; 9192 }; 9193 }; 9194 }; 9195 9196 cpuss2-btm-thermal { 9197 thermal-sensors = <&tsens2 10>; 9198 9199 trips { 9200 cpuss2-critical { 9201 temperature = <115000>; 9202 hysteresis = <1000>; 9203 type = "critical"; 9204 }; 9205 }; 9206 }; 9207 9208 aoss3-thermal { 9209 thermal-sensors = <&tsens3 0>; 9210 9211 trips { 9212 trip-point0 { 9213 temperature = <90000>; 9214 hysteresis = <2000>; 9215 type = "hot"; 9216 }; 9217 9218 aoss0-critical { 9219 temperature = <115000>; 9220 hysteresis = <1000>; 9221 type = "critical"; 9222 }; 9223 }; 9224 }; 9225 9226 nsp0-thermal { 9227 thermal-sensors = <&tsens3 1>; 9228 9229 trips { 9230 trip-point0 { 9231 temperature = <90000>; 9232 hysteresis = <2000>; 9233 type = "hot"; 9234 }; 9235 9236 nsp0-critical { 9237 temperature = <115000>; 9238 hysteresis = <1000>; 9239 type = "critical"; 9240 }; 9241 }; 9242 }; 9243 9244 nsp1-thermal { 9245 thermal-sensors = <&tsens3 2>; 9246 9247 trips { 9248 trip-point0 { 9249 temperature = <90000>; 9250 hysteresis = <2000>; 9251 type = "hot"; 9252 }; 9253 9254 nsp1-critical { 9255 temperature = <115000>; 9256 hysteresis = <1000>; 9257 type = "critical"; 9258 }; 9259 }; 9260 }; 9261 9262 nsp2-thermal { 9263 thermal-sensors = <&tsens3 3>; 9264 9265 trips { 9266 trip-point0 { 9267 temperature = <90000>; 9268 hysteresis = <2000>; 9269 type = "hot"; 9270 }; 9271 9272 nsp2-critical { 9273 temperature = <115000>; 9274 hysteresis = <1000>; 9275 type = "critical"; 9276 }; 9277 }; 9278 }; 9279 9280 nsp3-thermal { 9281 thermal-sensors = <&tsens3 4>; 9282 9283 trips { 9284 trip-point0 { 9285 temperature = <90000>; 9286 hysteresis = <2000>; 9287 type = "hot"; 9288 }; 9289 9290 nsp3-critical { 9291 temperature = <115000>; 9292 hysteresis = <1000>; 9293 type = "critical"; 9294 }; 9295 }; 9296 }; 9297 9298 gpuss-0-thermal { 9299 polling-delay-passive = <200>; 9300 9301 thermal-sensors = <&tsens3 5>; 9302 9303 cooling-maps { 9304 map0 { 9305 trip = <&gpuss0_alert0>; 9306 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9307 }; 9308 }; 9309 9310 trips { 9311 gpuss0_alert0: trip-point0 { 9312 temperature = <95000>; 9313 hysteresis = <1000>; 9314 type = "passive"; 9315 }; 9316 9317 gpu-critical { 9318 temperature = <115000>; 9319 hysteresis = <1000>; 9320 type = "critical"; 9321 }; 9322 }; 9323 }; 9324 9325 gpuss-1-thermal { 9326 polling-delay-passive = <200>; 9327 9328 thermal-sensors = <&tsens3 6>; 9329 9330 cooling-maps { 9331 map0 { 9332 trip = <&gpuss1_alert0>; 9333 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9334 }; 9335 }; 9336 9337 trips { 9338 gpuss1_alert0: trip-point0 { 9339 temperature = <95000>; 9340 hysteresis = <1000>; 9341 type = "passive"; 9342 }; 9343 9344 gpu-critical { 9345 temperature = <115000>; 9346 hysteresis = <1000>; 9347 type = "critical"; 9348 }; 9349 }; 9350 }; 9351 9352 gpuss-2-thermal { 9353 polling-delay-passive = <200>; 9354 9355 thermal-sensors = <&tsens3 7>; 9356 9357 cooling-maps { 9358 map0 { 9359 trip = <&gpuss2_alert0>; 9360 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9361 }; 9362 }; 9363 9364 trips { 9365 gpuss2_alert0: trip-point0 { 9366 temperature = <95000>; 9367 hysteresis = <1000>; 9368 type = "passive"; 9369 }; 9370 9371 gpu-critical { 9372 temperature = <115000>; 9373 hysteresis = <1000>; 9374 type = "critical"; 9375 }; 9376 }; 9377 }; 9378 9379 gpuss-3-thermal { 9380 polling-delay-passive = <200>; 9381 9382 thermal-sensors = <&tsens3 8>; 9383 9384 cooling-maps { 9385 map0 { 9386 trip = <&gpuss3_alert0>; 9387 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9388 }; 9389 }; 9390 9391 trips { 9392 gpuss3_alert0: trip-point0 { 9393 temperature = <95000>; 9394 hysteresis = <1000>; 9395 type = "passive"; 9396 }; 9397 9398 gpu-critical { 9399 temperature = <115000>; 9400 hysteresis = <1000>; 9401 type = "critical"; 9402 }; 9403 }; 9404 }; 9405 9406 gpuss-4-thermal { 9407 polling-delay-passive = <200>; 9408 9409 thermal-sensors = <&tsens3 9>; 9410 9411 cooling-maps { 9412 map0 { 9413 trip = <&gpuss4_alert0>; 9414 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9415 }; 9416 }; 9417 9418 trips { 9419 gpuss4_alert0: trip-point0 { 9420 temperature = <95000>; 9421 hysteresis = <1000>; 9422 type = "passive"; 9423 }; 9424 9425 gpu-critical { 9426 temperature = <115000>; 9427 hysteresis = <1000>; 9428 type = "critical"; 9429 }; 9430 }; 9431 }; 9432 9433 gpuss-5-thermal { 9434 polling-delay-passive = <200>; 9435 9436 thermal-sensors = <&tsens3 10>; 9437 9438 cooling-maps { 9439 map0 { 9440 trip = <&gpuss5_alert0>; 9441 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9442 }; 9443 }; 9444 9445 trips { 9446 gpuss5_alert0: trip-point0 { 9447 temperature = <95000>; 9448 hysteresis = <1000>; 9449 type = "passive"; 9450 }; 9451 9452 gpu-critical { 9453 temperature = <115000>; 9454 hysteresis = <1000>; 9455 type = "critical"; 9456 }; 9457 }; 9458 }; 9459 9460 gpuss-6-thermal { 9461 polling-delay-passive = <200>; 9462 9463 thermal-sensors = <&tsens3 11>; 9464 9465 cooling-maps { 9466 map0 { 9467 trip = <&gpuss6_alert0>; 9468 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9469 }; 9470 }; 9471 9472 trips { 9473 gpuss6_alert0: trip-point0 { 9474 temperature = <95000>; 9475 hysteresis = <1000>; 9476 type = "passive"; 9477 }; 9478 9479 gpu-critical { 9480 temperature = <115000>; 9481 hysteresis = <1000>; 9482 type = "critical"; 9483 }; 9484 }; 9485 }; 9486 9487 gpuss-7-thermal { 9488 polling-delay-passive = <200>; 9489 9490 thermal-sensors = <&tsens3 12>; 9491 9492 cooling-maps { 9493 map0 { 9494 trip = <&gpuss7_alert0>; 9495 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9496 }; 9497 }; 9498 9499 trips { 9500 gpuss7_alert0: trip-point0 { 9501 temperature = <95000>; 9502 hysteresis = <1000>; 9503 type = "passive"; 9504 }; 9505 9506 gpu-critical { 9507 temperature = <115000>; 9508 hysteresis = <1000>; 9509 type = "critical"; 9510 }; 9511 }; 9512 }; 9513 9514 camera0-thermal { 9515 thermal-sensors = <&tsens3 13>; 9516 9517 trips { 9518 trip-point0 { 9519 temperature = <90000>; 9520 hysteresis = <2000>; 9521 type = "hot"; 9522 }; 9523 9524 camera0-critical { 9525 temperature = <115000>; 9526 hysteresis = <1000>; 9527 type = "critical"; 9528 }; 9529 }; 9530 }; 9531 9532 camera1-thermal { 9533 thermal-sensors = <&tsens3 14>; 9534 9535 trips { 9536 trip-point0 { 9537 temperature = <90000>; 9538 hysteresis = <2000>; 9539 type = "hot"; 9540 }; 9541 9542 camera0-critical { 9543 temperature = <115000>; 9544 hysteresis = <1000>; 9545 type = "critical"; 9546 }; 9547 }; 9548 }; 9549 }; 9550}; 9551