1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 8#include <dt-bindings/clock/qcom,x1e80100-gcc.h> 9#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> 10#include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/interconnect/qcom,icc.h> 13#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom,rpmhpd.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,gpr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 clocks { 32 xo_board: xo-board { 33 compatible = "fixed-clock"; 34 clock-frequency = <76800000>; 35 #clock-cells = <0>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 clock-frequency = <32000>; 41 #clock-cells = <0>; 42 }; 43 44 bi_tcxo_div2: bi-tcxo-div2-clk { 45 compatible = "fixed-factor-clock"; 46 #clock-cells = <0>; 47 48 clocks = <&rpmhcc RPMH_CXO_CLK>; 49 clock-mult = <1>; 50 clock-div = <2>; 51 }; 52 53 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 54 compatible = "fixed-factor-clock"; 55 #clock-cells = <0>; 56 57 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 58 clock-mult = <1>; 59 clock-div = <2>; 60 }; 61 }; 62 63 cpus { 64 #address-cells = <2>; 65 #size-cells = <0>; 66 67 CPU0: cpu@0 { 68 device_type = "cpu"; 69 compatible = "qcom,oryon"; 70 reg = <0x0 0x0>; 71 enable-method = "psci"; 72 next-level-cache = <&L2_0>; 73 power-domains = <&CPU_PD0>; 74 power-domain-names = "psci"; 75 cpu-idle-states = <&CLUSTER_C4>; 76 77 L2_0: l2-cache { 78 compatible = "cache"; 79 cache-level = <2>; 80 cache-unified; 81 }; 82 }; 83 84 CPU1: cpu@100 { 85 device_type = "cpu"; 86 compatible = "qcom,oryon"; 87 reg = <0x0 0x100>; 88 enable-method = "psci"; 89 next-level-cache = <&L2_0>; 90 power-domains = <&CPU_PD1>; 91 power-domain-names = "psci"; 92 cpu-idle-states = <&CLUSTER_C4>; 93 }; 94 95 CPU2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "qcom,oryon"; 98 reg = <0x0 0x200>; 99 enable-method = "psci"; 100 next-level-cache = <&L2_0>; 101 power-domains = <&CPU_PD2>; 102 power-domain-names = "psci"; 103 cpu-idle-states = <&CLUSTER_C4>; 104 }; 105 106 CPU3: cpu@300 { 107 device_type = "cpu"; 108 compatible = "qcom,oryon"; 109 reg = <0x0 0x300>; 110 enable-method = "psci"; 111 next-level-cache = <&L2_0>; 112 power-domains = <&CPU_PD3>; 113 power-domain-names = "psci"; 114 cpu-idle-states = <&CLUSTER_C4>; 115 }; 116 117 CPU4: cpu@10000 { 118 device_type = "cpu"; 119 compatible = "qcom,oryon"; 120 reg = <0x0 0x10000>; 121 enable-method = "psci"; 122 next-level-cache = <&L2_1>; 123 power-domains = <&CPU_PD4>; 124 power-domain-names = "psci"; 125 cpu-idle-states = <&CLUSTER_C4>; 126 127 L2_1: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 }; 132 }; 133 134 CPU5: cpu@10100 { 135 device_type = "cpu"; 136 compatible = "qcom,oryon"; 137 reg = <0x0 0x10100>; 138 enable-method = "psci"; 139 next-level-cache = <&L2_1>; 140 power-domains = <&CPU_PD5>; 141 power-domain-names = "psci"; 142 cpu-idle-states = <&CLUSTER_C4>; 143 }; 144 145 CPU6: cpu@10200 { 146 device_type = "cpu"; 147 compatible = "qcom,oryon"; 148 reg = <0x0 0x10200>; 149 enable-method = "psci"; 150 next-level-cache = <&L2_1>; 151 power-domains = <&CPU_PD6>; 152 power-domain-names = "psci"; 153 cpu-idle-states = <&CLUSTER_C4>; 154 }; 155 156 CPU7: cpu@10300 { 157 device_type = "cpu"; 158 compatible = "qcom,oryon"; 159 reg = <0x0 0x10300>; 160 enable-method = "psci"; 161 next-level-cache = <&L2_1>; 162 power-domains = <&CPU_PD7>; 163 power-domain-names = "psci"; 164 cpu-idle-states = <&CLUSTER_C4>; 165 }; 166 167 CPU8: cpu@20000 { 168 device_type = "cpu"; 169 compatible = "qcom,oryon"; 170 reg = <0x0 0x20000>; 171 enable-method = "psci"; 172 next-level-cache = <&L2_2>; 173 power-domains = <&CPU_PD8>; 174 power-domain-names = "psci"; 175 cpu-idle-states = <&CLUSTER_C4>; 176 177 L2_2: l2-cache { 178 compatible = "cache"; 179 cache-level = <2>; 180 cache-unified; 181 }; 182 }; 183 184 CPU9: cpu@20100 { 185 device_type = "cpu"; 186 compatible = "qcom,oryon"; 187 reg = <0x0 0x20100>; 188 enable-method = "psci"; 189 next-level-cache = <&L2_2>; 190 power-domains = <&CPU_PD9>; 191 power-domain-names = "psci"; 192 cpu-idle-states = <&CLUSTER_C4>; 193 }; 194 195 CPU10: cpu@20200 { 196 device_type = "cpu"; 197 compatible = "qcom,oryon"; 198 reg = <0x0 0x20200>; 199 enable-method = "psci"; 200 next-level-cache = <&L2_2>; 201 power-domains = <&CPU_PD10>; 202 power-domain-names = "psci"; 203 cpu-idle-states = <&CLUSTER_C4>; 204 }; 205 206 CPU11: cpu@20300 { 207 device_type = "cpu"; 208 compatible = "qcom,oryon"; 209 reg = <0x0 0x20300>; 210 enable-method = "psci"; 211 next-level-cache = <&L2_2>; 212 power-domains = <&CPU_PD11>; 213 power-domain-names = "psci"; 214 cpu-idle-states = <&CLUSTER_C4>; 215 }; 216 217 cpu-map { 218 cluster0 { 219 core0 { 220 cpu = <&CPU0>; 221 }; 222 223 core1 { 224 cpu = <&CPU1>; 225 }; 226 227 core2 { 228 cpu = <&CPU2>; 229 }; 230 231 core3 { 232 cpu = <&CPU3>; 233 }; 234 }; 235 236 cluster1 { 237 core0 { 238 cpu = <&CPU4>; 239 }; 240 241 core1 { 242 cpu = <&CPU5>; 243 }; 244 245 core2 { 246 cpu = <&CPU6>; 247 }; 248 249 core3 { 250 cpu = <&CPU7>; 251 }; 252 }; 253 254 cluster2 { 255 core0 { 256 cpu = <&CPU8>; 257 }; 258 259 core1 { 260 cpu = <&CPU9>; 261 }; 262 263 core2 { 264 cpu = <&CPU10>; 265 }; 266 267 core3 { 268 cpu = <&CPU11>; 269 }; 270 }; 271 }; 272 273 idle-states { 274 entry-method = "psci"; 275 276 CLUSTER_C4: cpu-sleep-0 { 277 compatible = "arm,idle-state"; 278 idle-state-name = "ret"; 279 arm,psci-suspend-param = <0x00000004>; 280 entry-latency-us = <180>; 281 exit-latency-us = <320>; 282 min-residency-us = <1000>; 283 }; 284 }; 285 286 domain-idle-states { 287 CLUSTER_CL4: cluster-sleep-0 { 288 compatible = "domain-idle-state"; 289 idle-state-name = "l2-ret"; 290 arm,psci-suspend-param = <0x01000044>; 291 entry-latency-us = <350>; 292 exit-latency-us = <500>; 293 min-residency-us = <2500>; 294 }; 295 296 CLUSTER_CL5: cluster-sleep-1 { 297 compatible = "domain-idle-state"; 298 idle-state-name = "ret-pll-off"; 299 arm,psci-suspend-param = <0x01000054>; 300 entry-latency-us = <2200>; 301 exit-latency-us = <2500>; 302 min-residency-us = <7000>; 303 }; 304 }; 305 }; 306 307 firmware { 308 scm: scm { 309 compatible = "qcom,scm-x1e80100", "qcom,scm"; 310 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 311 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 312 }; 313 }; 314 315 clk_virt: interconnect-0 { 316 compatible = "qcom,x1e80100-clk-virt"; 317 #interconnect-cells = <2>; 318 qcom,bcm-voters = <&apps_bcm_voter>; 319 }; 320 321 mc_virt: interconnect-1 { 322 compatible = "qcom,x1e80100-mc-virt"; 323 #interconnect-cells = <2>; 324 qcom,bcm-voters = <&apps_bcm_voter>; 325 }; 326 327 memory@80000000 { 328 device_type = "memory"; 329 /* We expect the bootloader to fill in the size */ 330 reg = <0 0x80000000 0 0>; 331 }; 332 333 pmu { 334 compatible = "arm,armv8-pmuv3"; 335 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 336 }; 337 338 psci { 339 compatible = "arm,psci-1.0"; 340 method = "smc"; 341 342 CPU_PD0: power-domain-cpu0 { 343 #power-domain-cells = <0>; 344 power-domains = <&CLUSTER_PD0>; 345 }; 346 347 CPU_PD1: power-domain-cpu1 { 348 #power-domain-cells = <0>; 349 power-domains = <&CLUSTER_PD0>; 350 }; 351 352 CPU_PD2: power-domain-cpu2 { 353 #power-domain-cells = <0>; 354 power-domains = <&CLUSTER_PD0>; 355 }; 356 357 CPU_PD3: power-domain-cpu3 { 358 #power-domain-cells = <0>; 359 power-domains = <&CLUSTER_PD0>; 360 }; 361 362 CPU_PD4: power-domain-cpu4 { 363 #power-domain-cells = <0>; 364 power-domains = <&CLUSTER_PD1>; 365 }; 366 367 CPU_PD5: power-domain-cpu5 { 368 #power-domain-cells = <0>; 369 power-domains = <&CLUSTER_PD1>; 370 }; 371 372 CPU_PD6: power-domain-cpu6 { 373 #power-domain-cells = <0>; 374 power-domains = <&CLUSTER_PD1>; 375 }; 376 377 CPU_PD7: power-domain-cpu7 { 378 #power-domain-cells = <0>; 379 power-domains = <&CLUSTER_PD1>; 380 }; 381 382 CPU_PD8: power-domain-cpu8 { 383 #power-domain-cells = <0>; 384 power-domains = <&CLUSTER_PD2>; 385 }; 386 387 CPU_PD9: power-domain-cpu9 { 388 #power-domain-cells = <0>; 389 power-domains = <&CLUSTER_PD2>; 390 }; 391 392 CPU_PD10: power-domain-cpu10 { 393 #power-domain-cells = <0>; 394 power-domains = <&CLUSTER_PD2>; 395 }; 396 397 CPU_PD11: power-domain-cpu11 { 398 #power-domain-cells = <0>; 399 power-domains = <&CLUSTER_PD2>; 400 }; 401 402 CLUSTER_PD0: power-domain-cpu-cluster0 { 403 #power-domain-cells = <0>; 404 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 405 power-domains = <&SYSTEM_PD>; 406 }; 407 408 CLUSTER_PD1: power-domain-cpu-cluster1 { 409 #power-domain-cells = <0>; 410 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 411 power-domains = <&SYSTEM_PD>; 412 }; 413 414 CLUSTER_PD2: power-domain-cpu-cluster2 { 415 #power-domain-cells = <0>; 416 domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; 417 power-domains = <&SYSTEM_PD>; 418 }; 419 420 SYSTEM_PD: power-domain-system { 421 #power-domain-cells = <0>; 422 /* TODO: system-wide idle states */ 423 }; 424 }; 425 426 reserved-memory { 427 #address-cells = <2>; 428 #size-cells = <2>; 429 ranges; 430 431 gunyah_hyp_mem: gunyah-hyp@80000000 { 432 reg = <0x0 0x80000000 0x0 0x800000>; 433 no-map; 434 }; 435 436 hyp_elf_package_mem: hyp-elf-package@80800000 { 437 reg = <0x0 0x80800000 0x0 0x200000>; 438 no-map; 439 }; 440 441 ncc_mem: ncc@80a00000 { 442 reg = <0x0 0x80a00000 0x0 0x400000>; 443 no-map; 444 }; 445 446 cpucp_log_mem: cpucp-log@80e00000 { 447 reg = <0x0 0x80e00000 0x0 0x40000>; 448 no-map; 449 }; 450 451 cpucp_mem: cpucp@80e40000 { 452 reg = <0x0 0x80e40000 0x0 0x540000>; 453 no-map; 454 }; 455 456 reserved-region@81380000 { 457 reg = <0x0 0x81380000 0x0 0x80000>; 458 no-map; 459 }; 460 461 tags_mem: tags-region@81400000 { 462 reg = <0x0 0x81400000 0x0 0x1a0000>; 463 no-map; 464 }; 465 466 xbl_dtlog_mem: xbl-dtlog@81a00000 { 467 reg = <0x0 0x81a00000 0x0 0x40000>; 468 no-map; 469 }; 470 471 xbl_ramdump_mem: xbl-ramdump@81a40000 { 472 reg = <0x0 0x81a40000 0x0 0x1c0000>; 473 no-map; 474 }; 475 476 aop_image_mem: aop-image@81c00000 { 477 reg = <0x0 0x81c00000 0x0 0x60000>; 478 no-map; 479 }; 480 481 aop_cmd_db_mem: aop-cmd-db@81c60000 { 482 compatible = "qcom,cmd-db"; 483 reg = <0x0 0x81c60000 0x0 0x20000>; 484 no-map; 485 }; 486 487 aop_config_mem: aop-config@81c80000 { 488 reg = <0x0 0x81c80000 0x0 0x20000>; 489 no-map; 490 }; 491 492 tme_crash_dump_mem: tme-crash-dump@81ca0000 { 493 reg = <0x0 0x81ca0000 0x0 0x40000>; 494 no-map; 495 }; 496 497 tme_log_mem: tme-log@81ce0000 { 498 reg = <0x0 0x81ce0000 0x0 0x4000>; 499 no-map; 500 }; 501 502 uefi_log_mem: uefi-log@81ce4000 { 503 reg = <0x0 0x81ce4000 0x0 0x10000>; 504 no-map; 505 }; 506 507 secdata_apss_mem: secdata-apss@81cff000 { 508 reg = <0x0 0x81cff000 0x0 0x1000>; 509 no-map; 510 }; 511 512 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 513 reg = <0x0 0x81e00000 0x0 0x100000>; 514 no-map; 515 }; 516 517 gpu_prr_mem: gpu-prr@81f00000 { 518 reg = <0x0 0x81f00000 0x0 0x10000>; 519 no-map; 520 }; 521 522 tpm_control_mem: tpm-control@81f10000 { 523 reg = <0x0 0x81f10000 0x0 0x10000>; 524 no-map; 525 }; 526 527 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 { 528 reg = <0x0 0x81f20000 0x0 0x10000>; 529 no-map; 530 }; 531 532 pld_pep_mem: pld-pep@81f30000 { 533 reg = <0x0 0x81f30000 0x0 0x6000>; 534 no-map; 535 }; 536 537 pld_gmu_mem: pld-gmu@81f36000 { 538 reg = <0x0 0x81f36000 0x0 0x1000>; 539 no-map; 540 }; 541 542 pld_pdp_mem: pld-pdp@81f37000 { 543 reg = <0x0 0x81f37000 0x0 0x1000>; 544 no-map; 545 }; 546 547 tz_stat_mem: tz-stat@82700000 { 548 reg = <0x0 0x82700000 0x0 0x100000>; 549 no-map; 550 }; 551 552 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 { 553 reg = <0x0 0x82800000 0x0 0xc00000>; 554 no-map; 555 }; 556 557 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 { 558 reg = <0x0 0x84b00000 0x0 0x800000>; 559 no-map; 560 }; 561 562 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 { 563 reg = <0x0 0x85300000 0x0 0x80000>; 564 no-map; 565 }; 566 567 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 { 568 reg = <0x0 0x866c0000 0x0 0x40000>; 569 no-map; 570 }; 571 572 spss_region_mem: spss-region@86700000 { 573 reg = <0x0 0x86700000 0x0 0x400000>; 574 no-map; 575 }; 576 577 adsp_boot_mem: adsp-boot@86b00000 { 578 reg = <0x0 0x86b00000 0x0 0xc00000>; 579 no-map; 580 }; 581 582 video_mem: video@87700000 { 583 reg = <0x0 0x87700000 0x0 0x700000>; 584 no-map; 585 }; 586 587 adspslpi_mem: adspslpi@87e00000 { 588 reg = <0x0 0x87e00000 0x0 0x3a00000>; 589 no-map; 590 }; 591 592 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 { 593 reg = <0x0 0x8b800000 0x0 0x80000>; 594 no-map; 595 }; 596 597 cdsp_mem: cdsp@8b900000 { 598 reg = <0x0 0x8b900000 0x0 0x2000000>; 599 no-map; 600 }; 601 602 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 { 603 reg = <0x0 0x8d900000 0x0 0x80000>; 604 no-map; 605 }; 606 607 gpu_microcode_mem: gpu-microcode@8d9fe000 { 608 reg = <0x0 0x8d9fe000 0x0 0x2000>; 609 no-map; 610 }; 611 612 cvp_mem: cvp@8da00000 { 613 reg = <0x0 0x8da00000 0x0 0x700000>; 614 no-map; 615 }; 616 617 camera_mem: camera@8e100000 { 618 reg = <0x0 0x8e100000 0x0 0x800000>; 619 no-map; 620 }; 621 622 av1_encoder_mem: av1-encoder@8e900000 { 623 reg = <0x0 0x8e900000 0x0 0x700000>; 624 no-map; 625 }; 626 627 reserved-region@8f000000 { 628 reg = <0x0 0x8f000000 0x0 0xa00000>; 629 no-map; 630 }; 631 632 wpss_mem: wpss@8fa00000 { 633 reg = <0x0 0x8fa00000 0x0 0x1900000>; 634 no-map; 635 }; 636 637 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 { 638 reg = <0x0 0x91300000 0x0 0x80000>; 639 no-map; 640 }; 641 642 xbl_sc_mem: xbl-sc@d8000000 { 643 reg = <0x0 0xd8000000 0x0 0x40000>; 644 no-map; 645 }; 646 647 reserved-region@d8040000 { 648 reg = <0x0 0xd8040000 0x0 0xa0000>; 649 no-map; 650 }; 651 652 qtee_mem: qtee@d80e0000 { 653 reg = <0x0 0xd80e0000 0x0 0x520000>; 654 no-map; 655 }; 656 657 ta_mem: ta@d8600000 { 658 reg = <0x0 0xd8600000 0x0 0x8a00000>; 659 no-map; 660 }; 661 662 tags_mem1: tags@e1000000 { 663 reg = <0x0 0xe1000000 0x0 0x26a0000>; 664 no-map; 665 }; 666 667 llcc_lpi_mem: llcc-lpi@ff800000 { 668 reg = <0x0 0xff800000 0x0 0x600000>; 669 no-map; 670 }; 671 672 smem_mem: smem@ffe00000 { 673 compatible = "qcom,smem"; 674 reg = <0x0 0xffe00000 0x0 0x200000>; 675 hwlocks = <&tcsr_mutex 3>; 676 no-map; 677 }; 678 }; 679 680 smp2p-adsp { 681 compatible = "qcom,smp2p"; 682 683 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 684 IPCC_MPROC_SIGNAL_SMP2P 685 IRQ_TYPE_EDGE_RISING>; 686 687 mboxes = <&ipcc IPCC_CLIENT_LPASS 688 IPCC_MPROC_SIGNAL_SMP2P>; 689 690 qcom,smem = <443>, <429>; 691 qcom,local-pid = <0>; 692 qcom,remote-pid = <2>; 693 694 smp2p_adsp_out: master-kernel { 695 qcom,entry-name = "master-kernel"; 696 #qcom,smem-state-cells = <1>; 697 }; 698 699 smp2p_adsp_in: slave-kernel { 700 qcom,entry-name = "slave-kernel"; 701 interrupt-controller; 702 #interrupt-cells = <2>; 703 }; 704 }; 705 706 smp2p-cdsp { 707 compatible = "qcom,smp2p"; 708 709 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 710 IPCC_MPROC_SIGNAL_SMP2P 711 IRQ_TYPE_EDGE_RISING>; 712 713 mboxes = <&ipcc IPCC_CLIENT_CDSP 714 IPCC_MPROC_SIGNAL_SMP2P>; 715 716 qcom,smem = <94>, <432>; 717 qcom,local-pid = <0>; 718 qcom,remote-pid = <5>; 719 720 smp2p_cdsp_out: master-kernel { 721 qcom,entry-name = "master-kernel"; 722 #qcom,smem-state-cells = <1>; 723 }; 724 725 smp2p_cdsp_in: slave-kernel { 726 qcom,entry-name = "slave-kernel"; 727 interrupt-controller; 728 #interrupt-cells = <2>; 729 }; 730 }; 731 732 soc: soc@0 { 733 compatible = "simple-bus"; 734 735 #address-cells = <2>; 736 #size-cells = <2>; 737 dma-ranges = <0 0 0 0 0x10 0>; 738 ranges = <0 0 0 0 0x10 0>; 739 740 gcc: clock-controller@100000 { 741 compatible = "qcom,x1e80100-gcc"; 742 reg = <0 0x00100000 0 0x200000>; 743 744 clocks = <&bi_tcxo_div2>, 745 <&sleep_clk>, 746 <0>, 747 <&pcie4_phy>, 748 <0>, 749 <&pcie6a_phy>, 750 <0>, 751 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 752 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 753 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 754 755 power-domains = <&rpmhpd RPMHPD_CX>; 756 #clock-cells = <1>; 757 #reset-cells = <1>; 758 #power-domain-cells = <1>; 759 }; 760 761 ipcc: mailbox@408000 { 762 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; 763 reg = <0 0x00408000 0 0x1000>; 764 765 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 766 interrupt-controller; 767 #interrupt-cells = <3>; 768 769 #mbox-cells = <2>; 770 }; 771 772 gpi_dma2: dma-controller@800000 { 773 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 774 reg = <0 0x00800000 0 0x60000>; 775 776 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 788 789 dma-channels = <12>; 790 dma-channel-mask = <0x3e>; 791 #dma-cells = <3>; 792 793 iommus = <&apps_smmu 0x436 0x0>; 794 795 status = "disabled"; 796 }; 797 798 qupv3_2: geniqup@8c0000 { 799 compatible = "qcom,geni-se-qup"; 800 reg = <0 0x008c0000 0 0x2000>; 801 802 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 803 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 804 clock-names = "m-ahb", 805 "s-ahb"; 806 807 iommus = <&apps_smmu 0x423 0x0>; 808 809 #address-cells = <2>; 810 #size-cells = <2>; 811 ranges; 812 813 status = "disabled"; 814 815 i2c16: i2c@880000 { 816 compatible = "qcom,geni-i2c"; 817 reg = <0 0x00880000 0 0x4000>; 818 819 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 820 821 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 822 clock-names = "se"; 823 824 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 825 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 826 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 827 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 828 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 829 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 830 interconnect-names = "qup-core", 831 "qup-config", 832 "qup-memory"; 833 834 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 835 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 836 dma-names = "tx", 837 "rx"; 838 839 pinctrl-0 = <&qup_i2c16_data_clk>; 840 pinctrl-names = "default"; 841 842 #address-cells = <1>; 843 #size-cells = <0>; 844 845 status = "disabled"; 846 }; 847 848 spi16: spi@880000 { 849 compatible = "qcom,geni-spi"; 850 reg = <0 0x00880000 0 0x4000>; 851 852 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 853 854 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 855 clock-names = "se"; 856 857 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 858 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 859 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 860 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 861 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 862 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 863 interconnect-names = "qup-core", 864 "qup-config", 865 "qup-memory"; 866 867 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 868 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 869 dma-names = "tx", 870 "rx"; 871 872 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 873 pinctrl-names = "default"; 874 875 #address-cells = <1>; 876 #size-cells = <0>; 877 878 status = "disabled"; 879 }; 880 881 i2c17: i2c@884000 { 882 compatible = "qcom,geni-i2c"; 883 reg = <0 0x00884000 0 0x4000>; 884 885 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 886 887 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 888 clock-names = "se"; 889 890 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 891 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 892 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 893 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 894 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 895 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 896 interconnect-names = "qup-core", 897 "qup-config", 898 "qup-memory"; 899 900 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 901 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 902 dma-names = "tx", 903 "rx"; 904 905 pinctrl-0 = <&qup_i2c17_data_clk>; 906 pinctrl-names = "default"; 907 908 #address-cells = <1>; 909 #size-cells = <0>; 910 911 status = "disabled"; 912 }; 913 914 spi17: spi@884000 { 915 compatible = "qcom,geni-spi"; 916 reg = <0 0x00884000 0 0x4000>; 917 918 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 919 920 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 921 clock-names = "se"; 922 923 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 924 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 925 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 926 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 927 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 928 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 929 interconnect-names = "qup-core", 930 "qup-config", 931 "qup-memory"; 932 933 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 934 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 935 dma-names = "tx", 936 "rx"; 937 938 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 939 pinctrl-names = "default"; 940 941 #address-cells = <1>; 942 #size-cells = <0>; 943 944 status = "disabled"; 945 }; 946 947 i2c18: i2c@888000 { 948 compatible = "qcom,geni-i2c"; 949 reg = <0 0x00888000 0 0x4000>; 950 951 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 952 953 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 954 clock-names = "se"; 955 956 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 957 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 958 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 959 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 960 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 961 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 962 interconnect-names = "qup-core", 963 "qup-config", 964 "qup-memory"; 965 966 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 967 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 968 dma-names = "tx", 969 "rx"; 970 971 pinctrl-0 = <&qup_i2c18_data_clk>; 972 pinctrl-names = "default"; 973 974 #address-cells = <1>; 975 #size-cells = <0>; 976 977 status = "disabled"; 978 }; 979 980 spi18: spi@888000 { 981 compatible = "qcom,geni-spi"; 982 reg = <0 0x00888000 0 0x4000>; 983 984 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 985 986 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 987 clock-names = "se"; 988 989 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 990 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 991 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 992 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 993 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 994 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 995 interconnect-names = "qup-core", 996 "qup-config", 997 "qup-memory"; 998 999 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1000 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1001 dma-names = "tx", 1002 "rx"; 1003 1004 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1005 pinctrl-names = "default"; 1006 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 1010 status = "disabled"; 1011 }; 1012 1013 i2c19: i2c@88c000 { 1014 compatible = "qcom,geni-i2c"; 1015 reg = <0 0x0088c000 0 0x4000>; 1016 1017 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1018 1019 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1020 clock-names = "se"; 1021 1022 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1023 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1024 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1025 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1026 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1027 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1028 interconnect-names = "qup-core", 1029 "qup-config", 1030 "qup-memory"; 1031 1032 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1033 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1034 dma-names = "tx", 1035 "rx"; 1036 1037 pinctrl-0 = <&qup_i2c19_data_clk>; 1038 pinctrl-names = "default"; 1039 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 1043 status = "disabled"; 1044 }; 1045 1046 spi19: spi@88c000 { 1047 compatible = "qcom,geni-spi"; 1048 reg = <0 0x0088c000 0 0x4000>; 1049 1050 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1051 1052 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1053 clock-names = "se"; 1054 1055 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1056 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1057 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1058 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1059 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1060 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1061 interconnect-names = "qup-core", 1062 "qup-config", 1063 "qup-memory"; 1064 1065 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1066 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1067 dma-names = "tx", 1068 "rx"; 1069 1070 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1071 pinctrl-names = "default"; 1072 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 1076 status = "disabled"; 1077 }; 1078 1079 i2c20: i2c@890000 { 1080 compatible = "qcom,geni-i2c"; 1081 reg = <0 0x00890000 0 0x4000>; 1082 1083 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1084 1085 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1086 clock-names = "se"; 1087 1088 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1089 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1090 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1091 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1092 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1093 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1094 interconnect-names = "qup-core", 1095 "qup-config", 1096 "qup-memory"; 1097 1098 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1099 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1100 dma-names = "tx", 1101 "rx"; 1102 1103 pinctrl-0 = <&qup_i2c20_data_clk>; 1104 pinctrl-names = "default"; 1105 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 1109 status = "disabled"; 1110 }; 1111 1112 spi20: spi@890000 { 1113 compatible = "qcom,geni-spi"; 1114 reg = <0 0x00890000 0 0x4000>; 1115 1116 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1117 1118 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1119 clock-names = "se"; 1120 1121 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1122 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1123 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1124 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1125 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1126 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1127 interconnect-names = "qup-core", 1128 "qup-config", 1129 "qup-memory"; 1130 1131 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1132 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1133 dma-names = "tx", 1134 "rx"; 1135 1136 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1137 pinctrl-names = "default"; 1138 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 1142 status = "disabled"; 1143 }; 1144 1145 i2c21: i2c@894000 { 1146 compatible = "qcom,geni-i2c"; 1147 reg = <0 0x00894000 0 0x4000>; 1148 1149 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1150 1151 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1152 clock-names = "se"; 1153 1154 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1155 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1156 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1157 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1158 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1159 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1160 interconnect-names = "qup-core", 1161 "qup-config", 1162 "qup-memory"; 1163 1164 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1165 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1166 dma-names = "tx", 1167 "rx"; 1168 1169 pinctrl-0 = <&qup_i2c21_data_clk>; 1170 pinctrl-names = "default"; 1171 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 1175 status = "disabled"; 1176 }; 1177 1178 spi21: spi@894000 { 1179 compatible = "qcom,geni-spi"; 1180 reg = <0 0x00894000 0 0x4000>; 1181 1182 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1183 1184 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1185 clock-names = "se"; 1186 1187 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1188 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1189 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1190 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1191 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1192 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1193 interconnect-names = "qup-core", 1194 "qup-config", 1195 "qup-memory"; 1196 1197 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1198 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1199 dma-names = "tx", 1200 "rx"; 1201 1202 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1203 pinctrl-names = "default"; 1204 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 1208 status = "disabled"; 1209 }; 1210 1211 uart21: serial@894000 { 1212 compatible = "qcom,geni-uart"; 1213 reg = <0 0x00894000 0 0x4000>; 1214 1215 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1216 1217 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1218 clock-names = "se"; 1219 1220 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1221 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1222 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1223 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1224 interconnect-names = "qup-core", 1225 "qup-config"; 1226 1227 pinctrl-0 = <&qup_uart21_default>; 1228 pinctrl-names = "default"; 1229 1230 status = "disabled"; 1231 }; 1232 1233 i2c22: i2c@898000 { 1234 compatible = "qcom,geni-i2c"; 1235 reg = <0 0x00898000 0 0x4000>; 1236 1237 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1238 1239 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1240 clock-names = "se"; 1241 1242 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1243 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1244 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1245 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1246 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1247 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1248 interconnect-names = "qup-core", 1249 "qup-config", 1250 "qup-memory"; 1251 1252 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1253 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1254 dma-names = "tx", 1255 "rx"; 1256 1257 pinctrl-0 = <&qup_i2c22_data_clk>; 1258 pinctrl-names = "default"; 1259 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 1263 status = "disabled"; 1264 }; 1265 1266 spi22: spi@898000 { 1267 compatible = "qcom,geni-spi"; 1268 reg = <0 0x00898000 0 0x4000>; 1269 1270 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1271 1272 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1273 clock-names = "se"; 1274 1275 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1276 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1277 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1278 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1279 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1280 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1281 interconnect-names = "qup-core", 1282 "qup-config", 1283 "qup-memory"; 1284 1285 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1286 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1287 dma-names = "tx", 1288 "rx"; 1289 1290 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1291 pinctrl-names = "default"; 1292 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 1296 status = "disabled"; 1297 }; 1298 1299 i2c23: i2c@89c000 { 1300 compatible = "qcom,geni-i2c"; 1301 reg = <0 0x0089c000 0 0x4000>; 1302 1303 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1304 1305 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1306 clock-names = "se"; 1307 1308 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1309 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1310 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1311 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1312 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1313 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1314 interconnect-names = "qup-core", 1315 "qup-config", 1316 "qup-memory"; 1317 1318 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1319 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1320 dma-names = "tx", 1321 "rx"; 1322 1323 pinctrl-0 = <&qup_i2c23_data_clk>; 1324 pinctrl-names = "default"; 1325 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 1329 status = "disabled"; 1330 }; 1331 1332 spi23: spi@89c000 { 1333 compatible = "qcom,geni-spi"; 1334 reg = <0 0x0089c000 0 0x4000>; 1335 1336 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1337 1338 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1339 clock-names = "se"; 1340 1341 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1342 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1343 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1344 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1345 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1346 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1347 interconnect-names = "qup-core", 1348 "qup-config", 1349 "qup-memory"; 1350 1351 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1352 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1353 dma-names = "tx", 1354 "rx"; 1355 1356 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1357 pinctrl-names = "default"; 1358 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 1362 status = "disabled"; 1363 }; 1364 }; 1365 1366 gpi_dma1: dma-controller@a00000 { 1367 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1368 reg = <0 0x00a00000 0 0x60000>; 1369 1370 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 1382 1383 dma-channels = <12>; 1384 dma-channel-mask = <0x3e>; 1385 #dma-cells = <3>; 1386 1387 iommus = <&apps_smmu 0x136 0x0>; 1388 1389 status = "disabled"; 1390 }; 1391 1392 qupv3_1: geniqup@ac0000 { 1393 compatible = "qcom,geni-se-qup"; 1394 reg = <0 0x00ac0000 0 0x2000>; 1395 1396 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1397 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1398 clock-names = "m-ahb", 1399 "s-ahb"; 1400 1401 iommus = <&apps_smmu 0x123 0x0>; 1402 1403 #address-cells = <2>; 1404 #size-cells = <2>; 1405 ranges; 1406 1407 status = "disabled"; 1408 1409 i2c8: i2c@a80000 { 1410 compatible = "qcom,geni-i2c"; 1411 reg = <0 0x00a80000 0 0x4000>; 1412 1413 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1414 1415 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1416 clock-names = "se"; 1417 1418 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1419 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1420 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1421 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1422 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1423 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1424 interconnect-names = "qup-core", 1425 "qup-config", 1426 "qup-memory"; 1427 1428 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1429 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1430 dma-names = "tx", 1431 "rx"; 1432 1433 pinctrl-0 = <&qup_i2c8_data_clk>; 1434 pinctrl-names = "default"; 1435 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 1439 status = "disabled"; 1440 }; 1441 1442 spi8: spi@a80000 { 1443 compatible = "qcom,geni-spi"; 1444 reg = <0 0x00a80000 0 0x4000>; 1445 1446 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1447 1448 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1449 clock-names = "se"; 1450 1451 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1452 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1453 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1454 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1455 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1456 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1457 interconnect-names = "qup-core", 1458 "qup-config", 1459 "qup-memory"; 1460 1461 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1462 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1463 dma-names = "tx", 1464 "rx"; 1465 1466 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1467 pinctrl-names = "default"; 1468 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 1472 status = "disabled"; 1473 }; 1474 1475 i2c9: i2c@a84000 { 1476 compatible = "qcom,geni-i2c"; 1477 reg = <0 0x00a84000 0 0x4000>; 1478 1479 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1480 1481 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1482 clock-names = "se"; 1483 1484 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1485 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1486 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1487 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1488 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1489 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1490 interconnect-names = "qup-core", 1491 "qup-config", 1492 "qup-memory"; 1493 1494 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1495 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1496 dma-names = "tx", 1497 "rx"; 1498 1499 pinctrl-0 = <&qup_i2c9_data_clk>; 1500 pinctrl-names = "default"; 1501 1502 #address-cells = <1>; 1503 #size-cells = <0>; 1504 1505 status = "disabled"; 1506 }; 1507 1508 spi9: spi@a84000 { 1509 compatible = "qcom,geni-spi"; 1510 reg = <0 0x00a84000 0 0x4000>; 1511 1512 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1513 1514 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1515 clock-names = "se"; 1516 1517 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1518 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1519 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1520 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1521 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1522 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1523 interconnect-names = "qup-core", 1524 "qup-config", 1525 "qup-memory"; 1526 1527 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1528 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1529 dma-names = "tx", 1530 "rx"; 1531 1532 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1533 pinctrl-names = "default"; 1534 1535 #address-cells = <1>; 1536 #size-cells = <0>; 1537 1538 status = "disabled"; 1539 }; 1540 1541 i2c10: i2c@a88000 { 1542 compatible = "qcom,geni-i2c"; 1543 reg = <0 0x00a88000 0 0x4000>; 1544 1545 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1546 1547 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1548 clock-names = "se"; 1549 1550 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1551 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1552 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1553 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1554 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1555 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1556 interconnect-names = "qup-core", 1557 "qup-config", 1558 "qup-memory"; 1559 1560 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1561 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1562 dma-names = "tx", 1563 "rx"; 1564 1565 pinctrl-0 = <&qup_i2c10_data_clk>; 1566 pinctrl-names = "default"; 1567 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 1571 status = "disabled"; 1572 }; 1573 1574 spi10: spi@a88000 { 1575 compatible = "qcom,geni-spi"; 1576 reg = <0 0x00a88000 0 0x4000>; 1577 1578 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1579 1580 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1581 clock-names = "se"; 1582 1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1584 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1585 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1586 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1587 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1588 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1589 interconnect-names = "qup-core", 1590 "qup-config", 1591 "qup-memory"; 1592 1593 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1594 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1595 dma-names = "tx", 1596 "rx"; 1597 1598 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1599 pinctrl-names = "default"; 1600 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 1604 status = "disabled"; 1605 }; 1606 1607 i2c11: i2c@a8c000 { 1608 compatible = "qcom,geni-i2c"; 1609 reg = <0 0x00a8c000 0 0x4000>; 1610 1611 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1612 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1614 clock-names = "se"; 1615 1616 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1617 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1618 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1619 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1620 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1621 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1622 interconnect-names = "qup-core", 1623 "qup-config", 1624 "qup-memory"; 1625 1626 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1627 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1628 dma-names = "tx", 1629 "rx"; 1630 1631 pinctrl-0 = <&qup_i2c11_data_clk>; 1632 pinctrl-names = "default"; 1633 1634 #address-cells = <1>; 1635 #size-cells = <0>; 1636 1637 status = "disabled"; 1638 }; 1639 1640 spi11: spi@a8c000 { 1641 compatible = "qcom,geni-spi"; 1642 reg = <0 0x00a8c000 0 0x4000>; 1643 1644 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1645 1646 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1647 clock-names = "se"; 1648 1649 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1650 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1651 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1652 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1653 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1654 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1655 interconnect-names = "qup-core", 1656 "qup-config", 1657 "qup-memory"; 1658 1659 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1660 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1661 dma-names = "tx", 1662 "rx"; 1663 1664 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1665 pinctrl-names = "default"; 1666 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 1670 status = "disabled"; 1671 }; 1672 1673 i2c12: i2c@a90000 { 1674 compatible = "qcom,geni-i2c"; 1675 reg = <0 0x00a90000 0 0x4000>; 1676 1677 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1678 1679 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1680 clock-names = "se"; 1681 1682 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1683 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1684 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1685 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1686 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1687 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1688 interconnect-names = "qup-core", 1689 "qup-config", 1690 "qup-memory"; 1691 1692 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1693 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1694 dma-names = "tx", 1695 "rx"; 1696 1697 pinctrl-0 = <&qup_i2c12_data_clk>; 1698 pinctrl-names = "default"; 1699 1700 #address-cells = <1>; 1701 #size-cells = <0>; 1702 1703 status = "disabled"; 1704 }; 1705 1706 spi12: spi@a90000 { 1707 compatible = "qcom,geni-spi"; 1708 reg = <0 0x00a90000 0 0x4000>; 1709 1710 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1711 1712 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1713 clock-names = "se"; 1714 1715 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1716 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1717 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1718 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1719 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1720 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1721 interconnect-names = "qup-core", 1722 "qup-config", 1723 "qup-memory"; 1724 1725 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1726 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1727 dma-names = "tx", 1728 "rx"; 1729 1730 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1731 pinctrl-names = "default"; 1732 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 1736 status = "disabled"; 1737 }; 1738 1739 i2c13: i2c@a94000 { 1740 compatible = "qcom,geni-i2c"; 1741 reg = <0 0x00a94000 0 0x4000>; 1742 1743 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1744 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1746 clock-names = "se"; 1747 1748 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1749 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1750 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1751 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1752 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1753 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1754 interconnect-names = "qup-core", 1755 "qup-config", 1756 "qup-memory"; 1757 1758 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1759 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1760 dma-names = "tx", 1761 "rx"; 1762 1763 pinctrl-0 = <&qup_i2c13_data_clk>; 1764 pinctrl-names = "default"; 1765 1766 #address-cells = <1>; 1767 #size-cells = <0>; 1768 1769 status = "disabled"; 1770 }; 1771 1772 spi13: spi@a94000 { 1773 compatible = "qcom,geni-spi"; 1774 reg = <0 0x00a94000 0 0x4000>; 1775 1776 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1777 1778 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1779 clock-names = "se"; 1780 1781 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1782 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1783 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1784 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1785 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1786 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1787 interconnect-names = "qup-core", 1788 "qup-config", 1789 "qup-memory"; 1790 1791 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1792 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1793 dma-names = "tx", 1794 "rx"; 1795 1796 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1797 pinctrl-names = "default"; 1798 1799 #address-cells = <1>; 1800 #size-cells = <0>; 1801 1802 status = "disabled"; 1803 }; 1804 1805 i2c14: i2c@a98000 { 1806 compatible = "qcom,geni-i2c"; 1807 reg = <0 0x00a98000 0 0x4000>; 1808 1809 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1810 1811 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1812 clock-names = "se"; 1813 1814 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1815 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1816 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1817 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1818 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1819 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1820 interconnect-names = "qup-core", 1821 "qup-config", 1822 "qup-memory"; 1823 1824 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1825 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1826 dma-names = "tx", 1827 "rx"; 1828 1829 pinctrl-0 = <&qup_i2c14_data_clk>; 1830 pinctrl-names = "default"; 1831 1832 #address-cells = <1>; 1833 #size-cells = <0>; 1834 1835 status = "disabled"; 1836 }; 1837 1838 spi14: spi@a98000 { 1839 compatible = "qcom,geni-spi"; 1840 reg = <0 0x00a98000 0 0x4000>; 1841 1842 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1843 1844 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1845 clock-names = "se"; 1846 1847 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1848 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1849 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1850 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1851 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1852 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1853 interconnect-names = "qup-core", 1854 "qup-config", 1855 "qup-memory"; 1856 1857 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1858 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1859 dma-names = "tx", 1860 "rx"; 1861 1862 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1863 pinctrl-names = "default"; 1864 1865 #address-cells = <1>; 1866 #size-cells = <0>; 1867 1868 status = "disabled"; 1869 }; 1870 1871 i2c15: i2c@a9c000 { 1872 compatible = "qcom,geni-i2c"; 1873 reg = <0 0x00a9c000 0 0x4000>; 1874 1875 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 1876 1877 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1878 clock-names = "se"; 1879 1880 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1881 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1882 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1883 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1884 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1885 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1886 interconnect-names = "qup-core", 1887 "qup-config", 1888 "qup-memory"; 1889 1890 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1891 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1892 dma-names = "tx", 1893 "rx"; 1894 1895 pinctrl-0 = <&qup_i2c15_data_clk>; 1896 pinctrl-names = "default"; 1897 1898 #address-cells = <1>; 1899 #size-cells = <0>; 1900 1901 status = "disabled"; 1902 }; 1903 1904 spi15: spi@a9c000 { 1905 compatible = "qcom,geni-spi"; 1906 reg = <0 0x00a9c000 0 0x4000>; 1907 1908 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 1909 1910 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1911 clock-names = "se"; 1912 1913 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1914 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1915 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1916 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1917 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1918 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1919 interconnect-names = "qup-core", 1920 "qup-config", 1921 "qup-memory"; 1922 1923 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1924 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1925 dma-names = "tx", 1926 "rx"; 1927 1928 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1929 pinctrl-names = "default"; 1930 1931 #address-cells = <1>; 1932 #size-cells = <0>; 1933 1934 status = "disabled"; 1935 }; 1936 }; 1937 1938 gpi_dma0: dma-controller@b00000 { 1939 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1940 reg = <0 0x00b00000 0 0x60000>; 1941 1942 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 1954 1955 dma-channels = <12>; 1956 dma-channel-mask = <0x3e>; 1957 #dma-cells = <3>; 1958 1959 iommus = <&apps_smmu 0x456 0x0>; 1960 1961 status = "disabled"; 1962 }; 1963 1964 qupv3_0: geniqup@bc0000 { 1965 compatible = "qcom,geni-se-qup"; 1966 reg = <0 0x00bc0000 0 0x2000>; 1967 1968 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1969 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1970 clock-names = "m-ahb", 1971 "s-ahb"; 1972 1973 iommus = <&apps_smmu 0x443 0x0>; 1974 #address-cells = <2>; 1975 #size-cells = <2>; 1976 ranges; 1977 1978 status = "disabled"; 1979 1980 i2c0: i2c@b80000 { 1981 compatible = "qcom,geni-i2c"; 1982 reg = <0 0xb80000 0 0x4000>; 1983 1984 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1985 1986 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1987 clock-names = "se"; 1988 1989 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1990 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1991 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1992 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1993 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1994 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1995 interconnect-names = "qup-core", 1996 "qup-config", 1997 "qup-memory"; 1998 1999 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 2000 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 2001 dma-names = "tx", 2002 "rx"; 2003 2004 pinctrl-0 = <&qup_i2c0_data_clk>; 2005 pinctrl-names = "default"; 2006 2007 #address-cells = <1>; 2008 #size-cells = <0>; 2009 2010 status = "disabled"; 2011 }; 2012 2013 spi0: spi@b80000 { 2014 compatible = "qcom,geni-spi"; 2015 reg = <0 0x00b80000 0 0x4000>; 2016 2017 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2018 2019 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2020 clock-names = "se"; 2021 2022 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2023 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2024 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2025 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2026 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2027 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2028 interconnect-names = "qup-core", 2029 "qup-config", 2030 "qup-memory"; 2031 2032 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 2033 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 2034 dma-names = "tx", 2035 "rx"; 2036 2037 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2038 pinctrl-names = "default"; 2039 2040 #address-cells = <1>; 2041 #size-cells = <0>; 2042 2043 status = "disabled"; 2044 }; 2045 2046 i2c1: i2c@b84000 { 2047 compatible = "qcom,geni-i2c"; 2048 reg = <0 0x00b84000 0 0x4000>; 2049 2050 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2051 2052 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2053 clock-names = "se"; 2054 2055 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2056 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2057 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2058 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2059 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2060 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2061 interconnect-names = "qup-core", 2062 "qup-config", 2063 "qup-memory"; 2064 2065 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 2066 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 2067 dma-names = "tx", 2068 "rx"; 2069 2070 pinctrl-0 = <&qup_i2c1_data_clk>; 2071 pinctrl-names = "default"; 2072 2073 #address-cells = <1>; 2074 #size-cells = <0>; 2075 2076 status = "disabled"; 2077 }; 2078 2079 spi1: spi@b84000 { 2080 compatible = "qcom,geni-spi"; 2081 reg = <0 0x00b84000 0 0x4000>; 2082 2083 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2084 2085 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2086 clock-names = "se"; 2087 2088 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2089 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2090 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2091 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2092 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2093 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2094 interconnect-names = "qup-core", 2095 "qup-config", 2096 "qup-memory"; 2097 2098 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 2099 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 2100 dma-names = "tx", 2101 "rx"; 2102 2103 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 2104 pinctrl-names = "default"; 2105 2106 #address-cells = <1>; 2107 #size-cells = <0>; 2108 2109 status = "disabled"; 2110 }; 2111 2112 i2c2: i2c@b88000 { 2113 compatible = "qcom,geni-i2c"; 2114 reg = <0 0x00b88000 0 0x4000>; 2115 2116 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2117 2118 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2119 clock-names = "se"; 2120 2121 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2122 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2123 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2124 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2125 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2126 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2127 interconnect-names = "qup-core", 2128 "qup-config", 2129 "qup-memory"; 2130 2131 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2132 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2133 dma-names = "tx", 2134 "rx"; 2135 2136 pinctrl-0 = <&qup_i2c2_data_clk>; 2137 pinctrl-names = "default"; 2138 2139 #address-cells = <1>; 2140 #size-cells = <0>; 2141 2142 status = "disabled"; 2143 }; 2144 2145 spi2: spi@b88000 { 2146 compatible = "qcom,geni-spi"; 2147 reg = <0 0xb88000 0 0x4000>; 2148 2149 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2150 2151 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2152 clock-names = "se"; 2153 2154 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2155 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2156 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2157 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2158 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2159 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2160 interconnect-names = "qup-core", 2161 "qup-config", 2162 "qup-memory"; 2163 2164 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2165 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2166 dma-names = "tx", 2167 "rx"; 2168 2169 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2170 pinctrl-names = "default"; 2171 2172 #address-cells = <1>; 2173 #size-cells = <0>; 2174 2175 status = "disabled"; 2176 }; 2177 2178 i2c3: i2c@b8c000 { 2179 compatible = "qcom,geni-i2c"; 2180 reg = <0 0x00b8c000 0 0x4000>; 2181 2182 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2183 2184 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2185 clock-names = "se"; 2186 2187 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2188 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2189 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2190 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2191 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2192 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2193 interconnect-names = "qup-core", 2194 "qup-config", 2195 "qup-memory"; 2196 2197 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2198 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2199 dma-names = "tx", 2200 "rx"; 2201 2202 pinctrl-0 = <&qup_i2c3_data_clk>; 2203 pinctrl-names = "default"; 2204 2205 #address-cells = <1>; 2206 #size-cells = <0>; 2207 2208 status = "disabled"; 2209 }; 2210 2211 spi3: spi@b8c000 { 2212 compatible = "qcom,geni-spi"; 2213 reg = <0 0x00b8c000 0 0x4000>; 2214 2215 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2216 2217 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2218 clock-names = "se"; 2219 2220 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2221 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2222 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2223 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2224 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2225 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2226 interconnect-names = "qup-core", 2227 "qup-config", 2228 "qup-memory"; 2229 2230 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2231 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2232 dma-names = "tx", 2233 "rx"; 2234 2235 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2236 pinctrl-names = "default"; 2237 2238 #address-cells = <1>; 2239 #size-cells = <0>; 2240 2241 status = "disabled"; 2242 }; 2243 2244 i2c4: i2c@b90000 { 2245 compatible = "qcom,geni-i2c"; 2246 reg = <0 0xb90000 0 0x4000>; 2247 2248 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2249 2250 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2251 clock-names = "se"; 2252 2253 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2254 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2255 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2256 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2257 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2258 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2259 interconnect-names = "qup-core", 2260 "qup-config", 2261 "qup-memory"; 2262 2263 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2264 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2265 dma-names = "tx", 2266 "rx"; 2267 2268 pinctrl-0 = <&qup_i2c4_data_clk>; 2269 pinctrl-names = "default"; 2270 2271 #address-cells = <1>; 2272 #size-cells = <0>; 2273 2274 status = "disabled"; 2275 }; 2276 2277 spi4: spi@b90000 { 2278 compatible = "qcom,geni-spi"; 2279 reg = <0 0x00b90000 0 0x4000>; 2280 2281 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2282 2283 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2284 clock-names = "se"; 2285 2286 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2287 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2288 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2289 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2290 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2291 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2292 interconnect-names = "qup-core", 2293 "qup-config", 2294 "qup-memory"; 2295 2296 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2297 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2298 dma-names = "tx", 2299 "rx"; 2300 2301 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2302 pinctrl-names = "default"; 2303 2304 #address-cells = <1>; 2305 #size-cells = <0>; 2306 2307 status = "disabled"; 2308 }; 2309 2310 i2c5: i2c@b94000 { 2311 compatible = "qcom,geni-i2c"; 2312 reg = <0 0x00b94000 0 0x4000>; 2313 2314 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2315 2316 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2317 clock-names = "se"; 2318 2319 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2320 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2321 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2322 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2323 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2324 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2325 interconnect-names = "qup-core", 2326 "qup-config", 2327 "qup-memory"; 2328 2329 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2330 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2331 dma-names = "tx", 2332 "rx"; 2333 2334 pinctrl-0 = <&qup_i2c5_data_clk>; 2335 pinctrl-names = "default"; 2336 2337 #address-cells = <1>; 2338 #size-cells = <0>; 2339 2340 status = "disabled"; 2341 }; 2342 2343 spi5: spi@b94000 { 2344 compatible = "qcom,geni-spi"; 2345 reg = <0 0x00b94000 0 0x4000>; 2346 2347 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2348 2349 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2350 clock-names = "se"; 2351 2352 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2353 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2354 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2355 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2356 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2357 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2358 interconnect-names = "qup-core", 2359 "qup-config", 2360 "qup-memory"; 2361 2362 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2363 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2364 dma-names = "tx", 2365 "rx"; 2366 2367 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2368 pinctrl-names = "default"; 2369 2370 #address-cells = <1>; 2371 #size-cells = <0>; 2372 2373 status = "disabled"; 2374 }; 2375 2376 i2c6: i2c@b98000 { 2377 compatible = "qcom,geni-i2c"; 2378 reg = <0 0x00b98000 0 0x4000>; 2379 2380 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2381 2382 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2383 clock-names = "se"; 2384 2385 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2386 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2387 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2388 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2389 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2390 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2391 interconnect-names = "qup-core", 2392 "qup-config", 2393 "qup-memory"; 2394 2395 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2396 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2397 dma-names = "tx", 2398 "rx"; 2399 2400 pinctrl-0 = <&qup_i2c6_data_clk>; 2401 pinctrl-names = "default"; 2402 2403 #address-cells = <1>; 2404 #size-cells = <0>; 2405 2406 status = "disabled"; 2407 }; 2408 2409 spi6: spi@b98000 { 2410 compatible = "qcom,geni-spi"; 2411 reg = <0 0x00b98000 0 0x4000>; 2412 2413 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2414 2415 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2416 clock-names = "se"; 2417 2418 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2419 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2420 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2421 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2422 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2423 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2424 interconnect-names = "qup-core", 2425 "qup-config", 2426 "qup-memory"; 2427 2428 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2429 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2430 dma-names = "tx", 2431 "rx"; 2432 2433 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2434 pinctrl-names = "default"; 2435 2436 #address-cells = <1>; 2437 #size-cells = <0>; 2438 2439 status = "disabled"; 2440 }; 2441 2442 i2c7: i2c@b9c000 { 2443 compatible = "qcom,geni-i2c"; 2444 reg = <0 0x00b9c000 0 0x4000>; 2445 2446 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2447 2448 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2449 clock-names = "se"; 2450 2451 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2452 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2453 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2454 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2455 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2456 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2457 interconnect-names = "qup-core", 2458 "qup-config", 2459 "qup-memory"; 2460 2461 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2462 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2463 dma-names = "tx", 2464 "rx"; 2465 2466 pinctrl-0 = <&qup_i2c7_data_clk>; 2467 pinctrl-names = "default"; 2468 2469 #address-cells = <1>; 2470 #size-cells = <0>; 2471 2472 status = "disabled"; 2473 }; 2474 2475 spi7: spi@b9c000 { 2476 compatible = "qcom,geni-spi"; 2477 reg = <0 0x00b9c000 0 0x4000>; 2478 2479 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2480 2481 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2482 clock-names = "se"; 2483 2484 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2485 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2486 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2487 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2488 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2489 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2490 interconnect-names = "qup-core", 2491 "qup-config", 2492 "qup-memory"; 2493 2494 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2495 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2496 dma-names = "tx", 2497 "rx"; 2498 2499 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2500 pinctrl-names = "default"; 2501 2502 #address-cells = <1>; 2503 #size-cells = <0>; 2504 2505 status = "disabled"; 2506 }; 2507 }; 2508 2509 tsens0: thermal-sensor@c271000 { 2510 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2511 reg = <0 0x0c271000 0 0x1000>, 2512 <0 0x0c222000 0 0x1000>; 2513 2514 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2515 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2516 interrupt-names = "uplow", 2517 "critical"; 2518 2519 #qcom,sensors = <16>; 2520 2521 #thermal-sensor-cells = <1>; 2522 }; 2523 2524 tsens1: thermal-sensor@c272000 { 2525 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2526 reg = <0 0x0c272000 0 0x1000>, 2527 <0 0x0c223000 0 0x1000>; 2528 2529 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2530 <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2531 interrupt-names = "uplow", 2532 "critical"; 2533 2534 #qcom,sensors = <16>; 2535 2536 #thermal-sensor-cells = <1>; 2537 }; 2538 2539 tsens2: thermal-sensor@c273000 { 2540 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2541 reg = <0 0x0c273000 0 0x1000>, 2542 <0 0x0c224000 0 0x1000>; 2543 2544 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>, 2545 <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 2546 interrupt-names = "uplow", 2547 "critical"; 2548 2549 #qcom,sensors = <16>; 2550 2551 #thermal-sensor-cells = <1>; 2552 }; 2553 2554 tsens3: thermal-sensor@c274000 { 2555 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2556 reg = <0 0x0c274000 0 0x1000>, 2557 <0 0x0c225000 0 0x1000>; 2558 2559 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>, 2560 <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; 2561 interrupt-names = "uplow", 2562 "critical"; 2563 2564 #qcom,sensors = <16>; 2565 2566 #thermal-sensor-cells = <1>; 2567 }; 2568 2569 usb_1_ss0_hsphy: phy@fd3000 { 2570 compatible = "qcom,x1e80100-snps-eusb2-phy", 2571 "qcom,sm8550-snps-eusb2-phy"; 2572 reg = <0 0x00fd3000 0 0x154>; 2573 #phy-cells = <0>; 2574 2575 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2576 clock-names = "ref"; 2577 2578 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2579 2580 status = "disabled"; 2581 }; 2582 2583 usb_1_ss0_qmpphy: phy@fd5000 { 2584 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2585 reg = <0 0x00fd5000 0 0x4000>; 2586 2587 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2588 <&rpmhcc RPMH_CXO_CLK>, 2589 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2590 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2591 clock-names = "aux", 2592 "ref", 2593 "com_aux", 2594 "usb3_pipe"; 2595 2596 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2597 2598 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2599 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; 2600 reset-names = "phy", 2601 "common"; 2602 2603 #clock-cells = <1>; 2604 #phy-cells = <1>; 2605 2606 status = "disabled"; 2607 2608 ports { 2609 #address-cells = <1>; 2610 #size-cells = <0>; 2611 2612 port@0 { 2613 reg = <0>; 2614 2615 usb_1_ss0_qmpphy_out: endpoint { 2616 }; 2617 }; 2618 2619 port@1 { 2620 reg = <1>; 2621 2622 usb_1_ss0_qmpphy_usb_ss_in: endpoint { 2623 remote-endpoint = <&usb_1_ss0_dwc3_ss>; 2624 }; 2625 }; 2626 2627 port@2 { 2628 reg = <2>; 2629 2630 usb_1_ss0_qmpphy_dp_in: endpoint { 2631 remote-endpoint = <&mdss_dp0_out>; 2632 }; 2633 }; 2634 }; 2635 }; 2636 2637 usb_1_ss1_hsphy: phy@fd9000 { 2638 compatible = "qcom,x1e80100-snps-eusb2-phy", 2639 "qcom,sm8550-snps-eusb2-phy"; 2640 reg = <0 0x00fd9000 0 0x154>; 2641 #phy-cells = <0>; 2642 2643 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2644 clock-names = "ref"; 2645 2646 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2647 2648 status = "disabled"; 2649 }; 2650 2651 usb_1_ss1_qmpphy: phy@fda000 { 2652 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2653 reg = <0 0x00fda000 0 0x4000>; 2654 2655 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2656 <&rpmhcc RPMH_CXO_CLK>, 2657 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2658 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2659 clock-names = "aux", 2660 "ref", 2661 "com_aux", 2662 "usb3_pipe"; 2663 2664 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2665 2666 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2667 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; 2668 reset-names = "phy", 2669 "common"; 2670 2671 #clock-cells = <1>; 2672 #phy-cells = <1>; 2673 2674 status = "disabled"; 2675 2676 ports { 2677 #address-cells = <1>; 2678 #size-cells = <0>; 2679 2680 port@0 { 2681 reg = <0>; 2682 2683 usb_1_ss1_qmpphy_out: endpoint { 2684 }; 2685 }; 2686 2687 port@1 { 2688 reg = <1>; 2689 2690 usb_1_ss1_qmpphy_usb_ss_in: endpoint { 2691 remote-endpoint = <&usb_1_ss1_dwc3_ss>; 2692 }; 2693 }; 2694 2695 port@2 { 2696 reg = <2>; 2697 2698 usb_1_ss1_qmpphy_dp_in: endpoint { 2699 remote-endpoint = <&mdss_dp1_out>; 2700 }; 2701 }; 2702 }; 2703 }; 2704 2705 usb_1_ss2_hsphy: phy@fde000 { 2706 compatible = "qcom,x1e80100-snps-eusb2-phy", 2707 "qcom,sm8550-snps-eusb2-phy"; 2708 reg = <0 0x00fde000 0 0x154>; 2709 #phy-cells = <0>; 2710 2711 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2712 clock-names = "ref"; 2713 2714 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 2715 2716 status = "disabled"; 2717 }; 2718 2719 usb_1_ss2_qmpphy: phy@fdf000 { 2720 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2721 reg = <0 0x00fdf000 0 0x4000>; 2722 2723 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 2724 <&rpmhcc RPMH_CXO_CLK>, 2725 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 2726 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 2727 clock-names = "aux", 2728 "ref", 2729 "com_aux", 2730 "usb3_pipe"; 2731 2732 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 2733 2734 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 2735 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; 2736 reset-names = "phy", 2737 "common"; 2738 2739 #clock-cells = <1>; 2740 #phy-cells = <1>; 2741 2742 status = "disabled"; 2743 2744 ports { 2745 #address-cells = <1>; 2746 #size-cells = <0>; 2747 2748 port@0 { 2749 reg = <0>; 2750 2751 usb_1_ss2_qmpphy_out: endpoint { 2752 }; 2753 }; 2754 2755 port@1 { 2756 reg = <1>; 2757 2758 usb_1_ss2_qmpphy_usb_ss_in: endpoint { 2759 remote-endpoint = <&usb_1_ss2_dwc3_ss>; 2760 }; 2761 }; 2762 2763 port@2 { 2764 reg = <2>; 2765 2766 usb_1_ss2_qmpphy_dp_in: endpoint { 2767 remote-endpoint = <&mdss_dp2_out>; 2768 }; 2769 }; 2770 }; 2771 }; 2772 2773 cnoc_main: interconnect@1500000 { 2774 compatible = "qcom,x1e80100-cnoc-main"; 2775 reg = <0 0x1500000 0 0x14400>; 2776 2777 qcom,bcm-voters = <&apps_bcm_voter>; 2778 2779 #interconnect-cells = <2>; 2780 }; 2781 2782 config_noc: interconnect@1600000 { 2783 compatible = "qcom,x1e80100-cnoc-cfg"; 2784 reg = <0 0x1600000 0 0x6600>; 2785 2786 qcom,bcm-voters = <&apps_bcm_voter>; 2787 2788 #interconnect-cells = <2>; 2789 }; 2790 2791 system_noc: interconnect@1680000 { 2792 compatible = "qcom,x1e80100-system-noc"; 2793 reg = <0 0x1680000 0 0x1c080>; 2794 2795 qcom,bcm-voters = <&apps_bcm_voter>; 2796 2797 #interconnect-cells = <2>; 2798 }; 2799 2800 pcie_south_anoc: interconnect@16c0000 { 2801 compatible = "qcom,x1e80100-pcie-south-anoc"; 2802 reg = <0 0x16c0000 0 0xd080>; 2803 2804 qcom,bcm-voters = <&apps_bcm_voter>; 2805 2806 #interconnect-cells = <2>; 2807 }; 2808 2809 pcie_center_anoc: interconnect@16d0000 { 2810 compatible = "qcom,x1e80100-pcie-center-anoc"; 2811 reg = <0 0x16d0000 0 0x7000>; 2812 2813 qcom,bcm-voters = <&apps_bcm_voter>; 2814 2815 #interconnect-cells = <2>; 2816 }; 2817 2818 aggre1_noc: interconnect@16e0000 { 2819 compatible = "qcom,x1e80100-aggre1-noc"; 2820 reg = <0 0x16E0000 0 0x14400>; 2821 2822 qcom,bcm-voters = <&apps_bcm_voter>; 2823 2824 #interconnect-cells = <2>; 2825 }; 2826 2827 aggre2_noc: interconnect@1700000 { 2828 compatible = "qcom,x1e80100-aggre2-noc"; 2829 reg = <0 0x1700000 0 0x1c400>; 2830 2831 qcom,bcm-voters = <&apps_bcm_voter>; 2832 2833 #interconnect-cells = <2>; 2834 }; 2835 2836 pcie_north_anoc: interconnect@1740000 { 2837 compatible = "qcom,x1e80100-pcie-north-anoc"; 2838 reg = <0 0x1740000 0 0x9080>; 2839 2840 qcom,bcm-voters = <&apps_bcm_voter>; 2841 2842 #interconnect-cells = <2>; 2843 }; 2844 2845 usb_center_anoc: interconnect@1750000 { 2846 compatible = "qcom,x1e80100-usb-center-anoc"; 2847 reg = <0 0x1750000 0 0x8800>; 2848 2849 qcom,bcm-voters = <&apps_bcm_voter>; 2850 2851 #interconnect-cells = <2>; 2852 }; 2853 2854 usb_north_anoc: interconnect@1760000 { 2855 compatible = "qcom,x1e80100-usb-north-anoc"; 2856 reg = <0 0x1760000 0 0x7080>; 2857 2858 qcom,bcm-voters = <&apps_bcm_voter>; 2859 2860 #interconnect-cells = <2>; 2861 }; 2862 2863 usb_south_anoc: interconnect@1770000 { 2864 compatible = "qcom,x1e80100-usb-south-anoc"; 2865 reg = <0 0x1770000 0 0xf080>; 2866 2867 qcom,bcm-voters = <&apps_bcm_voter>; 2868 2869 #interconnect-cells = <2>; 2870 }; 2871 2872 mmss_noc: interconnect@1780000 { 2873 compatible = "qcom,x1e80100-mmss-noc"; 2874 reg = <0 0x1780000 0 0x5B800>; 2875 2876 qcom,bcm-voters = <&apps_bcm_voter>; 2877 2878 #interconnect-cells = <2>; 2879 }; 2880 2881 pcie6a: pci@1bf8000 { 2882 device_type = "pci"; 2883 compatible = "qcom,pcie-x1e80100"; 2884 reg = <0 0x01bf8000 0 0x3000>, 2885 <0 0x70000000 0 0xf20>, 2886 <0 0x70000f40 0 0xa8>, 2887 <0 0x70001000 0 0x1000>, 2888 <0 0x70100000 0 0x100000>, 2889 <0 0x01bfb000 0 0x1000>; 2890 reg-names = "parf", 2891 "dbi", 2892 "elbi", 2893 "atu", 2894 "config", 2895 "mhi"; 2896 #address-cells = <3>; 2897 #size-cells = <2>; 2898 ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>, 2899 <0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>; 2900 bus-range = <0 0xff>; 2901 2902 dma-coherent; 2903 2904 linux,pci-domain = <6>; 2905 num-lanes = <2>; 2906 2907 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 2908 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 2909 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 2910 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 2911 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 2912 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 2913 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 2914 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>; 2915 interrupt-names = "msi0", 2916 "msi1", 2917 "msi2", 2918 "msi3", 2919 "msi4", 2920 "msi5", 2921 "msi6", 2922 "msi7"; 2923 2924 #interrupt-cells = <1>; 2925 interrupt-map-mask = <0 0 0 0x7>; 2926 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>, 2927 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>, 2928 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>, 2929 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>; 2930 2931 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, 2932 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 2933 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, 2934 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, 2935 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, 2936 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>, 2937 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; 2938 clock-names = "aux", 2939 "cfg", 2940 "bus_master", 2941 "bus_slave", 2942 "slave_q2a", 2943 "noc_aggr", 2944 "cnoc_sf_axi"; 2945 2946 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; 2947 assigned-clock-rates = <19200000>; 2948 2949 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS 2950 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2951 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2952 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>; 2953 interconnect-names = "pcie-mem", 2954 "cpu-pcie"; 2955 2956 resets = <&gcc GCC_PCIE_6A_BCR>, 2957 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; 2958 reset-names = "pci", 2959 "link_down"; 2960 2961 power-domains = <&gcc GCC_PCIE_6A_GDSC>; 2962 required-opps = <&rpmhpd_opp_nom>; 2963 2964 phys = <&pcie6a_phy>; 2965 phy-names = "pciephy"; 2966 2967 status = "disabled"; 2968 }; 2969 2970 pcie6a_phy: phy@1bfc000 { 2971 compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy"; 2972 reg = <0 0x01bfc000 0 0x2000>; 2973 2974 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, 2975 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 2976 <&rpmhcc RPMH_CXO_CLK>, 2977 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, 2978 <&gcc GCC_PCIE_6A_PIPE_CLK>; 2979 clock-names = "aux", 2980 "cfg_ahb", 2981 "ref", 2982 "rchng", 2983 "pipe"; 2984 2985 resets = <&gcc GCC_PCIE_6A_PHY_BCR>, 2986 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; 2987 reset-names = "phy", 2988 "phy_nocsr"; 2989 2990 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; 2991 assigned-clock-rates = <100000000>; 2992 2993 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 2994 2995 #clock-cells = <0>; 2996 clock-output-names = "pcie6a_pipe_clk"; 2997 2998 #phy-cells = <0>; 2999 3000 status = "disabled"; 3001 }; 3002 3003 pcie4: pci@1c08000 { 3004 device_type = "pci"; 3005 compatible = "qcom,pcie-x1e80100"; 3006 reg = <0 0x01c08000 0 0x3000>, 3007 <0 0x7c000000 0 0xf1d>, 3008 <0 0x7c000f40 0 0xa8>, 3009 <0 0x7c001000 0 0x1000>, 3010 <0 0x7c100000 0 0x100000>, 3011 <0 0x01c0b000 0 0x1000>; 3012 reg-names = "parf", 3013 "dbi", 3014 "elbi", 3015 "atu", 3016 "config", 3017 "mhi"; 3018 #address-cells = <3>; 3019 #size-cells = <2>; 3020 ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>, 3021 <0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>; 3022 bus-range = <0x00 0xff>; 3023 3024 dma-coherent; 3025 3026 linux,pci-domain = <4>; 3027 num-lanes = <2>; 3028 3029 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3030 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 3031 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3032 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3033 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3034 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3035 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3036 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 3037 interrupt-names = "msi0", 3038 "msi1", 3039 "msi2", 3040 "msi3", 3041 "msi4", 3042 "msi5", 3043 "msi6", 3044 "msi7"; 3045 3046 #interrupt-cells = <1>; 3047 interrupt-map-mask = <0 0 0 0x7>; 3048 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 3049 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 3050 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 3051 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 3052 3053 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3054 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3055 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 3056 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 3057 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 3058 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3059 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3060 clock-names = "aux", 3061 "cfg", 3062 "bus_master", 3063 "bus_slave", 3064 "slave_q2a", 3065 "noc_aggr", 3066 "cnoc_sf_axi"; 3067 3068 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 3069 assigned-clock-rates = <19200000>; 3070 3071 interconnects = <&pcie_south_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 3072 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3073 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3074 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; 3075 interconnect-names = "pcie-mem", 3076 "cpu-pcie"; 3077 3078 resets = <&gcc GCC_PCIE_4_BCR>, 3079 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 3080 reset-names = "pci", 3081 "link_down"; 3082 3083 power-domains = <&gcc GCC_PCIE_4_GDSC>; 3084 required-opps = <&rpmhpd_opp_nom>; 3085 3086 phys = <&pcie4_phy>; 3087 phy-names = "pciephy"; 3088 3089 status = "disabled"; 3090 3091 pcie4_port0: pcie@0 { 3092 device_type = "pci"; 3093 reg = <0x0 0x0 0x0 0x0 0x0>; 3094 bus-range = <0x01 0xff>; 3095 3096 #address-cells = <3>; 3097 #size-cells = <2>; 3098 ranges; 3099 }; 3100 }; 3101 3102 pcie4_phy: phy@1c0e000 { 3103 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3104 reg = <0 0x01c0e000 0 0x2000>; 3105 3106 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3107 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3108 <&rpmhcc RPMH_CXO_CLK>, 3109 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 3110 <&gcc GCC_PCIE_4_PIPE_CLK>; 3111 clock-names = "aux", 3112 "cfg_ahb", 3113 "ref", 3114 "rchng", 3115 "pipe"; 3116 3117 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 3118 reset-names = "phy"; 3119 3120 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 3121 assigned-clock-rates = <100000000>; 3122 3123 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 3124 3125 #clock-cells = <0>; 3126 clock-output-names = "pcie4_pipe_clk"; 3127 3128 #phy-cells = <0>; 3129 3130 status = "disabled"; 3131 }; 3132 3133 tcsr_mutex: hwlock@1f40000 { 3134 compatible = "qcom,tcsr-mutex"; 3135 reg = <0 0x01f40000 0 0x20000>; 3136 #hwlock-cells = <1>; 3137 }; 3138 3139 tcsr: clock-controller@1fc0000 { 3140 compatible = "qcom,x1e80100-tcsr", "syscon"; 3141 reg = <0 0x01fc0000 0 0x30000>; 3142 clocks = <&rpmhcc RPMH_CXO_CLK>; 3143 #clock-cells = <1>; 3144 #reset-cells = <1>; 3145 }; 3146 3147 gpu: gpu@3d00000 { 3148 compatible = "qcom,adreno-43050c01", "qcom,adreno"; 3149 reg = <0x0 0x03d00000 0x0 0x40000>, 3150 <0x0 0x03d9e000 0x0 0x1000>, 3151 <0x0 0x03d61000 0x0 0x800>; 3152 3153 reg-names = "kgsl_3d0_reg_memory", 3154 "cx_mem", 3155 "cx_dbgc"; 3156 3157 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3158 3159 iommus = <&adreno_smmu 0 0x0>, 3160 <&adreno_smmu 1 0x0>; 3161 3162 operating-points-v2 = <&gpu_opp_table>; 3163 3164 qcom,gmu = <&gmu>; 3165 #cooling-cells = <2>; 3166 3167 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3168 interconnect-names = "gfx-mem"; 3169 3170 status = "disabled"; 3171 3172 zap-shader { 3173 memory-region = <&gpu_microcode_mem>; 3174 }; 3175 3176 gpu_opp_table: opp-table { 3177 compatible = "operating-points-v2"; 3178 3179 opp-1100000000 { 3180 opp-hz = /bits/ 64 <1100000000>; 3181 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3182 opp-peak-kBps = <16500000>; 3183 }; 3184 3185 opp-1000000000 { 3186 opp-hz = /bits/ 64 <1000000000>; 3187 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3188 opp-peak-kBps = <14398438>; 3189 }; 3190 3191 opp-925000000 { 3192 opp-hz = /bits/ 64 <925000000>; 3193 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3194 opp-peak-kBps = <14398438>; 3195 }; 3196 3197 opp-800000000 { 3198 opp-hz = /bits/ 64 <800000000>; 3199 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3200 opp-peak-kBps = <12449219>; 3201 }; 3202 3203 opp-744000000 { 3204 opp-hz = /bits/ 64 <744000000>; 3205 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3206 opp-peak-kBps = <10687500>; 3207 }; 3208 3209 opp-687000000 { 3210 opp-hz = /bits/ 64 <687000000>; 3211 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3212 opp-peak-kBps = <8171875>; 3213 }; 3214 3215 opp-550000000 { 3216 opp-hz = /bits/ 64 <550000000>; 3217 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3218 opp-peak-kBps = <6074219>; 3219 }; 3220 3221 opp-390000000 { 3222 opp-hz = /bits/ 64 <390000000>; 3223 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3224 opp-peak-kBps = <3000000>; 3225 }; 3226 3227 opp-300000000 { 3228 opp-hz = /bits/ 64 <300000000>; 3229 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3230 opp-peak-kBps = <2136719>; 3231 }; 3232 }; 3233 }; 3234 3235 gmu: gmu@3d6a000 { 3236 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; 3237 reg = <0x0 0x03d6a000 0x0 0x35000>, 3238 <0x0 0x03d50000 0x0 0x10000>, 3239 <0x0 0x0b280000 0x0 0x10000>; 3240 reg-names = "gmu", "rscc", "gmu_pdc"; 3241 3242 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3243 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3244 interrupt-names = "hfi", "gmu"; 3245 3246 clocks = <&gpucc GPU_CC_AHB_CLK>, 3247 <&gpucc GPU_CC_CX_GMU_CLK>, 3248 <&gpucc GPU_CC_CXO_CLK>, 3249 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3250 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3251 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3252 <&gpucc GPU_CC_DEMET_CLK>; 3253 clock-names = "ahb", 3254 "gmu", 3255 "cxo", 3256 "axi", 3257 "memnoc", 3258 "hub", 3259 "demet"; 3260 3261 power-domains = <&gpucc GPU_CX_GDSC>, 3262 <&gpucc GPU_GX_GDSC>; 3263 power-domain-names = "cx", 3264 "gx"; 3265 3266 iommus = <&adreno_smmu 5 0x0>; 3267 3268 qcom,qmp = <&aoss_qmp>; 3269 3270 operating-points-v2 = <&gmu_opp_table>; 3271 3272 gmu_opp_table: opp-table { 3273 compatible = "operating-points-v2"; 3274 3275 opp-550000000 { 3276 opp-hz = /bits/ 64 <550000000>; 3277 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3278 }; 3279 3280 opp-220000000 { 3281 opp-hz = /bits/ 64 <220000000>; 3282 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3283 }; 3284 }; 3285 }; 3286 3287 gpucc: clock-controller@3d90000 { 3288 compatible = "qcom,x1e80100-gpucc"; 3289 reg = <0 0x03d90000 0 0xa000>; 3290 clocks = <&bi_tcxo_div2>, 3291 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, 3292 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; 3293 #clock-cells = <1>; 3294 #reset-cells = <1>; 3295 #power-domain-cells = <1>; 3296 }; 3297 3298 adreno_smmu: iommu@3da0000 { 3299 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu", 3300 "qcom,smmu-500", "arm,mmu-500"; 3301 reg = <0x0 0x03da0000 0x0 0x40000>; 3302 #iommu-cells = <2>; 3303 #global-interrupts = <1>; 3304 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 3330 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3331 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3332 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3333 <&gpucc GPU_CC_AHB_CLK>; 3334 clock-names = "hlos", 3335 "bus", 3336 "iface", 3337 "ahb"; 3338 power-domains = <&gpucc GPU_CX_GDSC>; 3339 dma-coherent; 3340 }; 3341 3342 gem_noc: interconnect@26400000 { 3343 compatible = "qcom,x1e80100-gem-noc"; 3344 reg = <0 0x26400000 0 0x311200>; 3345 3346 qcom,bcm-voters = <&apps_bcm_voter>; 3347 3348 #interconnect-cells = <2>; 3349 }; 3350 3351 nsp_noc: interconnect@320c0000 { 3352 compatible = "qcom,x1e80100-nsp-noc"; 3353 reg = <0 0x320C0000 0 0xE080>; 3354 3355 qcom,bcm-voters = <&apps_bcm_voter>; 3356 3357 #interconnect-cells = <2>; 3358 }; 3359 3360 lpass_wsa2macro: codec@6aa0000 { 3361 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 3362 reg = <0 0x06aa0000 0 0x1000>; 3363 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3364 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3365 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3366 <&lpass_vamacro>; 3367 clock-names = "mclk", 3368 "macro", 3369 "dcodec", 3370 "fsgen"; 3371 3372 #clock-cells = <0>; 3373 clock-output-names = "wsa2-mclk"; 3374 #sound-dai-cells = <1>; 3375 sound-name-prefix = "WSA2"; 3376 }; 3377 3378 swr3: soundwire@6ab0000 { 3379 compatible = "qcom,soundwire-v2.0.0"; 3380 reg = <0 0x06ab0000 0 0x10000>; 3381 clocks = <&lpass_wsa2macro>; 3382 clock-names = "iface"; 3383 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 3384 label = "WSA2"; 3385 3386 pinctrl-0 = <&wsa2_swr_active>; 3387 pinctrl-names = "default"; 3388 3389 qcom,din-ports = <4>; 3390 qcom,dout-ports = <9>; 3391 3392 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3393 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3394 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3395 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3396 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3397 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3398 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3399 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3400 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3401 3402 #address-cells = <2>; 3403 #size-cells = <0>; 3404 #sound-dai-cells = <1>; 3405 status = "disabled"; 3406 }; 3407 3408 lpass_rxmacro: codec@6ac0000 { 3409 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 3410 reg = <0 0x06ac0000 0 0x1000>; 3411 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3412 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3413 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3414 <&lpass_vamacro>; 3415 clock-names = "mclk", 3416 "macro", 3417 "dcodec", 3418 "fsgen"; 3419 3420 #clock-cells = <0>; 3421 clock-output-names = "mclk"; 3422 #sound-dai-cells = <1>; 3423 }; 3424 3425 swr1: soundwire@6ad0000 { 3426 compatible = "qcom,soundwire-v2.0.0"; 3427 reg = <0 0x06ad0000 0 0x10000>; 3428 clocks = <&lpass_rxmacro>; 3429 clock-names = "iface"; 3430 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 3431 label = "RX"; 3432 3433 pinctrl-0 = <&rx_swr_active>; 3434 pinctrl-names = "default"; 3435 3436 qcom,din-ports = <1>; 3437 qcom,dout-ports = <11>; 3438 3439 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3440 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3441 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3442 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3443 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3444 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3445 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3446 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3447 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3448 3449 #address-cells = <2>; 3450 #size-cells = <0>; 3451 #sound-dai-cells = <1>; 3452 status = "disabled"; 3453 }; 3454 3455 lpass_txmacro: codec@6ae0000 { 3456 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 3457 reg = <0 0x06ae0000 0 0x1000>; 3458 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3459 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3460 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3461 <&lpass_vamacro>; 3462 clock-names = "mclk", 3463 "macro", 3464 "dcodec", 3465 "fsgen"; 3466 3467 #clock-cells = <0>; 3468 clock-output-names = "mclk"; 3469 #sound-dai-cells = <1>; 3470 }; 3471 3472 lpass_wsamacro: codec@6b00000 { 3473 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 3474 reg = <0 0x06b00000 0 0x1000>; 3475 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3476 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3477 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3478 <&lpass_vamacro>; 3479 clock-names = "mclk", 3480 "macro", 3481 "dcodec", 3482 "fsgen"; 3483 3484 #clock-cells = <0>; 3485 clock-output-names = "mclk"; 3486 #sound-dai-cells = <1>; 3487 sound-name-prefix = "WSA"; 3488 }; 3489 3490 swr0: soundwire@6b10000 { 3491 compatible = "qcom,soundwire-v2.0.0"; 3492 reg = <0 0x06b10000 0 0x10000>; 3493 clocks = <&lpass_wsamacro>; 3494 clock-names = "iface"; 3495 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 3496 label = "WSA"; 3497 3498 pinctrl-0 = <&wsa_swr_active>; 3499 pinctrl-names = "default"; 3500 3501 qcom,din-ports = <4>; 3502 qcom,dout-ports = <9>; 3503 3504 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3505 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3506 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3507 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3508 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3509 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3510 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3511 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3512 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3513 3514 #address-cells = <2>; 3515 #size-cells = <0>; 3516 #sound-dai-cells = <1>; 3517 status = "disabled"; 3518 }; 3519 3520 swr2: soundwire@6d30000 { 3521 compatible = "qcom,soundwire-v2.0.0"; 3522 reg = <0 0x06d30000 0 0x10000>; 3523 clocks = <&lpass_txmacro>; 3524 clock-names = "iface"; 3525 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 3526 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 3527 interrupt-names = "core", "wakeup"; 3528 label = "TX"; 3529 3530 pinctrl-0 = <&tx_swr_active>; 3531 pinctrl-names = "default"; 3532 3533 qcom,din-ports = <4>; 3534 qcom,dout-ports = <1>; 3535 3536 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; 3537 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; 3538 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; 3539 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3540 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3541 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3542 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3543 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3544 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; 3545 3546 #address-cells = <2>; 3547 #size-cells = <0>; 3548 #sound-dai-cells = <1>; 3549 status = "disabled"; 3550 }; 3551 3552 lpass_vamacro: codec@6d44000 { 3553 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 3554 reg = <0 0x06d44000 0 0x1000>; 3555 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3556 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3557 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3558 clock-names = "mclk", 3559 "macro", 3560 "dcodec"; 3561 3562 #clock-cells = <0>; 3563 clock-output-names = "fsgen"; 3564 #sound-dai-cells = <1>; 3565 }; 3566 3567 lpass_tlmm: pinctrl@6e80000 { 3568 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl"; 3569 reg = <0 0x06e80000 0 0x20000>, 3570 <0 0x07250000 0 0x10000>; 3571 3572 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3573 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3574 clock-names = "core", "audio"; 3575 3576 gpio-controller; 3577 #gpio-cells = <2>; 3578 gpio-ranges = <&lpass_tlmm 0 0 23>; 3579 3580 tx_swr_active: tx-swr-active-state { 3581 clk-pins { 3582 pins = "gpio0"; 3583 function = "swr_tx_clk"; 3584 drive-strength = <2>; 3585 slew-rate = <1>; 3586 bias-disable; 3587 }; 3588 3589 data-pins { 3590 pins = "gpio1", "gpio2"; 3591 function = "swr_tx_data"; 3592 drive-strength = <2>; 3593 slew-rate = <1>; 3594 bias-bus-hold; 3595 }; 3596 }; 3597 3598 rx_swr_active: rx-swr-active-state { 3599 clk-pins { 3600 pins = "gpio3"; 3601 function = "swr_rx_clk"; 3602 drive-strength = <2>; 3603 slew-rate = <1>; 3604 bias-disable; 3605 }; 3606 3607 data-pins { 3608 pins = "gpio4", "gpio5"; 3609 function = "swr_rx_data"; 3610 drive-strength = <2>; 3611 slew-rate = <1>; 3612 bias-bus-hold; 3613 }; 3614 }; 3615 3616 dmic01_default: dmic01-default-state { 3617 clk-pins { 3618 pins = "gpio6"; 3619 function = "dmic1_clk"; 3620 drive-strength = <8>; 3621 output-high; 3622 }; 3623 3624 data-pins { 3625 pins = "gpio7"; 3626 function = "dmic1_data"; 3627 drive-strength = <8>; 3628 input-enable; 3629 }; 3630 }; 3631 3632 dmic23_default: dmic23-default-state { 3633 clk-pins { 3634 pins = "gpio8"; 3635 function = "dmic2_clk"; 3636 drive-strength = <8>; 3637 output-high; 3638 }; 3639 3640 data-pins { 3641 pins = "gpio9"; 3642 function = "dmic2_data"; 3643 drive-strength = <8>; 3644 input-enable; 3645 }; 3646 }; 3647 3648 wsa_swr_active: wsa-swr-active-state { 3649 clk-pins { 3650 pins = "gpio10"; 3651 function = "wsa_swr_clk"; 3652 drive-strength = <2>; 3653 slew-rate = <1>; 3654 bias-disable; 3655 }; 3656 3657 data-pins { 3658 pins = "gpio11"; 3659 function = "wsa_swr_data"; 3660 drive-strength = <2>; 3661 slew-rate = <1>; 3662 bias-bus-hold; 3663 }; 3664 }; 3665 3666 wsa2_swr_active: wsa2-swr-active-state { 3667 clk-pins { 3668 pins = "gpio15"; 3669 function = "wsa2_swr_clk"; 3670 drive-strength = <2>; 3671 slew-rate = <1>; 3672 bias-disable; 3673 }; 3674 3675 data-pins { 3676 pins = "gpio16"; 3677 function = "wsa2_swr_data"; 3678 drive-strength = <2>; 3679 slew-rate = <1>; 3680 bias-bus-hold; 3681 }; 3682 }; 3683 }; 3684 3685 lpass_ag_noc: interconnect@7e40000 { 3686 compatible = "qcom,x1e80100-lpass-ag-noc"; 3687 reg = <0 0x7e40000 0 0xE080>; 3688 3689 qcom,bcm-voters = <&apps_bcm_voter>; 3690 3691 #interconnect-cells = <2>; 3692 }; 3693 3694 lpass_lpiaon_noc: interconnect@7400000 { 3695 compatible = "qcom,x1e80100-lpass-lpiaon-noc"; 3696 reg = <0 0x7400000 0 0x19080>; 3697 3698 qcom,bcm-voters = <&apps_bcm_voter>; 3699 3700 #interconnect-cells = <2>; 3701 }; 3702 3703 lpass_lpicx_noc: interconnect@7430000 { 3704 compatible = "qcom,x1e80100-lpass-lpicx-noc"; 3705 reg = <0 0x7430000 0 0x3A200>; 3706 3707 qcom,bcm-voters = <&apps_bcm_voter>; 3708 3709 #interconnect-cells = <2>; 3710 }; 3711 3712 usb_2_hsphy: phy@88e0000 { 3713 compatible = "qcom,x1e80100-snps-eusb2-phy", 3714 "qcom,sm8550-snps-eusb2-phy"; 3715 reg = <0 0x088e0000 0 0x154>; 3716 #phy-cells = <0>; 3717 3718 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 3719 clock-names = "ref"; 3720 3721 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 3722 3723 status = "disabled"; 3724 }; 3725 3726 usb_1_ss2: usb@a0f8800 { 3727 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 3728 reg = <0 0x0a0f8800 0 0x400>; 3729 3730 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 3731 <&gcc GCC_USB30_TERT_MASTER_CLK>, 3732 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 3733 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 3734 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 3735 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3736 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 3737 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 3738 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3739 clock-names = "cfg_noc", 3740 "core", 3741 "iface", 3742 "sleep", 3743 "mock_utmi", 3744 "noc_aggr", 3745 "noc_aggr_north", 3746 "noc_aggr_south", 3747 "noc_sys"; 3748 3749 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 3750 <&gcc GCC_USB30_TERT_MASTER_CLK>; 3751 assigned-clock-rates = <19200000>, 3752 <200000000>; 3753 3754 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 3755 <&pdc 58 IRQ_TYPE_EDGE_BOTH>, 3756 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 3757 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; 3758 interrupt-names = "pwr_event", 3759 "dp_hs_phy_irq", 3760 "dm_hs_phy_irq", 3761 "ss_phy_irq"; 3762 3763 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 3764 required-opps = <&rpmhpd_opp_nom>; 3765 3766 resets = <&gcc GCC_USB30_TERT_BCR>; 3767 3768 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS 3769 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3770 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3771 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>; 3772 interconnect-names = "usb-ddr", 3773 "apps-usb"; 3774 3775 wakeup-source; 3776 3777 #address-cells = <2>; 3778 #size-cells = <2>; 3779 ranges; 3780 3781 status = "disabled"; 3782 3783 usb_1_ss2_dwc3: usb@a000000 { 3784 compatible = "snps,dwc3"; 3785 reg = <0 0x0a000000 0 0xcd00>; 3786 3787 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 3788 3789 iommus = <&apps_smmu 0x14a0 0x0>; 3790 3791 phys = <&usb_1_ss2_hsphy>, 3792 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; 3793 phy-names = "usb2-phy", 3794 "usb3-phy"; 3795 3796 snps,dis_u2_susphy_quirk; 3797 snps,dis_enblslpm_quirk; 3798 snps,usb3_lpm_capable; 3799 3800 dma-coherent; 3801 3802 ports { 3803 #address-cells = <1>; 3804 #size-cells = <0>; 3805 3806 port@0 { 3807 reg = <0>; 3808 3809 usb_1_ss2_dwc3_hs: endpoint { 3810 }; 3811 }; 3812 3813 port@1 { 3814 reg = <1>; 3815 3816 usb_1_ss2_dwc3_ss: endpoint { 3817 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; 3818 }; 3819 }; 3820 }; 3821 }; 3822 }; 3823 3824 usb_2: usb@a2f8800 { 3825 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 3826 reg = <0 0x0a2f8800 0 0x400>; 3827 #address-cells = <2>; 3828 #size-cells = <2>; 3829 ranges; 3830 3831 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 3832 <&gcc GCC_USB20_MASTER_CLK>, 3833 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 3834 <&gcc GCC_USB20_SLEEP_CLK>, 3835 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3836 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3837 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 3838 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 3839 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3840 clock-names = "cfg_noc", 3841 "core", 3842 "iface", 3843 "sleep", 3844 "mock_utmi", 3845 "noc_aggr", 3846 "noc_aggr_north", 3847 "noc_aggr_south", 3848 "noc_sys"; 3849 3850 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3851 <&gcc GCC_USB20_MASTER_CLK>; 3852 assigned-clock-rates = <19200000>, <200000000>; 3853 3854 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3855 <&pdc 50 IRQ_TYPE_EDGE_BOTH>, 3856 <&pdc 49 IRQ_TYPE_EDGE_BOTH>; 3857 interrupt-names = "pwr_event", 3858 "dp_hs_phy_irq", 3859 "dm_hs_phy_irq"; 3860 3861 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 3862 required-opps = <&rpmhpd_opp_nom>; 3863 3864 resets = <&gcc GCC_USB20_PRIM_BCR>; 3865 3866 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 3867 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3868 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3869 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; 3870 interconnect-names = "usb-ddr", 3871 "apps-usb"; 3872 3873 wakeup-source; 3874 3875 status = "disabled"; 3876 3877 usb_2_dwc3: usb@a200000 { 3878 compatible = "snps,dwc3"; 3879 reg = <0 0x0a200000 0 0xcd00>; 3880 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 3881 iommus = <&apps_smmu 0x14e0 0x0>; 3882 phys = <&usb_2_hsphy>; 3883 phy-names = "usb2-phy"; 3884 maximum-speed = "high-speed"; 3885 3886 ports { 3887 #address-cells = <1>; 3888 #size-cells = <0>; 3889 3890 port@0 { 3891 reg = <0>; 3892 3893 usb_2_dwc3_hs: endpoint { 3894 }; 3895 }; 3896 }; 3897 }; 3898 }; 3899 3900 usb_1_ss0: usb@a6f8800 { 3901 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 3902 reg = <0 0x0a6f8800 0 0x400>; 3903 3904 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3905 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3906 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3907 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3908 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3909 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3910 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>, 3911 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>, 3912 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3913 clock-names = "cfg_noc", 3914 "core", 3915 "iface", 3916 "sleep", 3917 "mock_utmi", 3918 "noc_aggr", 3919 "noc_aggr_north", 3920 "noc_aggr_south", 3921 "noc_sys"; 3922 3923 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3924 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3925 assigned-clock-rates = <19200000>, 3926 <200000000>; 3927 3928 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 3929 <&pdc 61 IRQ_TYPE_EDGE_BOTH>, 3930 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3931 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3932 interrupt-names = "pwr_event", 3933 "dp_hs_phy_irq", 3934 "dm_hs_phy_irq", 3935 "ss_phy_irq"; 3936 3937 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3938 required-opps = <&rpmhpd_opp_nom>; 3939 3940 resets = <&gcc GCC_USB30_PRIM_BCR>; 3941 3942 wakeup-source; 3943 3944 #address-cells = <2>; 3945 #size-cells = <2>; 3946 ranges; 3947 3948 status = "disabled"; 3949 3950 usb_1_ss0_dwc3: usb@a600000 { 3951 compatible = "snps,dwc3"; 3952 reg = <0 0x0a600000 0 0xcd00>; 3953 3954 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 3955 3956 iommus = <&apps_smmu 0x1420 0x0>; 3957 3958 phys = <&usb_1_ss0_hsphy>, 3959 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; 3960 phy-names = "usb2-phy", 3961 "usb3-phy"; 3962 3963 snps,dis_u2_susphy_quirk; 3964 snps,dis_enblslpm_quirk; 3965 snps,usb3_lpm_capable; 3966 3967 dma-coherent; 3968 3969 ports { 3970 #address-cells = <1>; 3971 #size-cells = <0>; 3972 3973 port@0 { 3974 reg = <0>; 3975 3976 usb_1_ss0_dwc3_hs: endpoint { 3977 }; 3978 }; 3979 3980 port@1 { 3981 reg = <1>; 3982 3983 usb_1_ss0_dwc3_ss: endpoint { 3984 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; 3985 }; 3986 }; 3987 }; 3988 }; 3989 }; 3990 3991 usb_1_ss1: usb@a8f8800 { 3992 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 3993 reg = <0 0x0a8f8800 0 0x400>; 3994 3995 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3996 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3997 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3998 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3999 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4000 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4001 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4002 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4003 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4004 clock-names = "cfg_noc", 4005 "core", 4006 "iface", 4007 "sleep", 4008 "mock_utmi", 4009 "noc_aggr", 4010 "noc_aggr_north", 4011 "noc_aggr_south", 4012 "noc_sys"; 4013 4014 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4015 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4016 assigned-clock-rates = <19200000>, 4017 <200000000>; 4018 4019 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 4020 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 4021 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 4022 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; 4023 interrupt-names = "pwr_event", 4024 "dp_hs_phy_irq", 4025 "dm_hs_phy_irq", 4026 "ss_phy_irq"; 4027 4028 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 4029 required-opps = <&rpmhpd_opp_nom>; 4030 4031 resets = <&gcc GCC_USB30_SEC_BCR>; 4032 4033 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS 4034 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4035 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4036 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>; 4037 interconnect-names = "usb-ddr", 4038 "apps-usb"; 4039 4040 wakeup-source; 4041 4042 #address-cells = <2>; 4043 #size-cells = <2>; 4044 ranges; 4045 4046 status = "disabled"; 4047 4048 usb_1_ss1_dwc3: usb@a800000 { 4049 compatible = "snps,dwc3"; 4050 reg = <0 0x0a800000 0 0xcd00>; 4051 4052 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 4053 4054 iommus = <&apps_smmu 0x1460 0x0>; 4055 4056 phys = <&usb_1_ss1_hsphy>, 4057 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; 4058 phy-names = "usb2-phy", 4059 "usb3-phy"; 4060 4061 snps,dis_u2_susphy_quirk; 4062 snps,dis_enblslpm_quirk; 4063 snps,usb3_lpm_capable; 4064 4065 dma-coherent; 4066 4067 ports { 4068 #address-cells = <1>; 4069 #size-cells = <0>; 4070 4071 port@0 { 4072 reg = <0>; 4073 4074 usb_1_ss1_dwc3_hs: endpoint { 4075 }; 4076 }; 4077 4078 port@1 { 4079 reg = <1>; 4080 4081 usb_1_ss1_dwc3_ss: endpoint { 4082 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; 4083 }; 4084 }; 4085 }; 4086 }; 4087 }; 4088 4089 mdss: display-subsystem@ae00000 { 4090 compatible = "qcom,x1e80100-mdss"; 4091 reg = <0 0x0ae00000 0 0x1000>; 4092 reg-names = "mdss"; 4093 4094 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4095 4096 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4097 <&gcc GCC_DISP_HF_AXI_CLK>, 4098 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4099 4100 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 4101 4102 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 4103 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 4104 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 4105 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4106 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4107 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4108 interconnect-names = "mdp0-mem", 4109 "mdp1-mem", 4110 "cpu-cfg"; 4111 4112 power-domains = <&dispcc MDSS_GDSC>; 4113 4114 iommus = <&apps_smmu 0x1c00 0x2>; 4115 4116 interrupt-controller; 4117 #interrupt-cells = <1>; 4118 4119 #address-cells = <2>; 4120 #size-cells = <2>; 4121 ranges; 4122 4123 status = "disabled"; 4124 4125 mdss_mdp: display-controller@ae01000 { 4126 compatible = "qcom,x1e80100-dpu"; 4127 reg = <0 0x0ae01000 0 0x8f000>, 4128 <0 0x0aeb0000 0 0x2008>; 4129 reg-names = "mdp", 4130 "vbif"; 4131 4132 interrupts-extended = <&mdss 0>; 4133 4134 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4135 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4136 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4137 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4138 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4139 clock-names = "nrt_bus", 4140 "iface", 4141 "lut", 4142 "core", 4143 "vsync"; 4144 4145 operating-points-v2 = <&mdp_opp_table>; 4146 4147 power-domains = <&rpmhpd RPMHPD_MMCX>; 4148 4149 ports { 4150 #address-cells = <1>; 4151 #size-cells = <0>; 4152 4153 port@0 { 4154 reg = <0>; 4155 4156 mdss_intf0_out: endpoint { 4157 remote-endpoint = <&mdss_dp0_in>; 4158 }; 4159 }; 4160 4161 port@4 { 4162 reg = <4>; 4163 4164 mdss_intf4_out: endpoint { 4165 remote-endpoint = <&mdss_dp1_in>; 4166 }; 4167 }; 4168 4169 port@5 { 4170 reg = <5>; 4171 4172 mdss_intf5_out: endpoint { 4173 remote-endpoint = <&mdss_dp3_in>; 4174 }; 4175 }; 4176 4177 port@6 { 4178 reg = <6>; 4179 4180 mdss_intf6_out: endpoint { 4181 remote-endpoint = <&mdss_dp2_in>; 4182 }; 4183 }; 4184 }; 4185 4186 mdp_opp_table: opp-table { 4187 compatible = "operating-points-v2"; 4188 4189 opp-200000000 { 4190 opp-hz = /bits/ 64 <200000000>; 4191 required-opps = <&rpmhpd_opp_low_svs>; 4192 }; 4193 4194 opp-325000000 { 4195 opp-hz = /bits/ 64 <325000000>; 4196 required-opps = <&rpmhpd_opp_svs>; 4197 }; 4198 4199 opp-375000000 { 4200 opp-hz = /bits/ 64 <375000000>; 4201 required-opps = <&rpmhpd_opp_svs_l1>; 4202 }; 4203 4204 opp-514000000 { 4205 opp-hz = /bits/ 64 <514000000>; 4206 required-opps = <&rpmhpd_opp_nom>; 4207 }; 4208 4209 opp-575000000 { 4210 opp-hz = /bits/ 64 <575000000>; 4211 required-opps = <&rpmhpd_opp_nom_l1>; 4212 }; 4213 }; 4214 }; 4215 4216 mdss_dp0: displayport-controller@ae90000 { 4217 compatible = "qcom,x1e80100-dp"; 4218 reg = <0 0xae90000 0 0x200>, 4219 <0 0xae90200 0 0x200>, 4220 <0 0xae90400 0 0x600>, 4221 <0 0xae91000 0 0x400>, 4222 <0 0xae91400 0 0x400>; 4223 4224 interrupts-extended = <&mdss 12>; 4225 4226 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4227 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 4228 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 4229 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4230 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4231 clock-names = "core_iface", 4232 "core_aux", 4233 "ctrl_link", 4234 "ctrl_link_iface", 4235 "stream_pixel"; 4236 4237 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4238 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4239 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4240 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4241 4242 operating-points-v2 = <&mdss_dp0_opp_table>; 4243 4244 power-domains = <&rpmhpd RPMHPD_MMCX>; 4245 4246 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; 4247 phy-names = "dp"; 4248 4249 #sound-dai-cells = <0>; 4250 4251 status = "disabled"; 4252 4253 ports { 4254 #address-cells = <1>; 4255 #size-cells = <0>; 4256 4257 port@0 { 4258 reg = <0>; 4259 4260 mdss_dp0_in: endpoint { 4261 remote-endpoint = <&mdss_intf0_out>; 4262 }; 4263 }; 4264 4265 port@1 { 4266 reg = <1>; 4267 4268 mdss_dp0_out: endpoint { 4269 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; 4270 }; 4271 }; 4272 }; 4273 4274 mdss_dp0_opp_table: opp-table { 4275 compatible = "operating-points-v2"; 4276 4277 opp-160000000 { 4278 opp-hz = /bits/ 64 <160000000>; 4279 required-opps = <&rpmhpd_opp_low_svs>; 4280 }; 4281 4282 opp-270000000 { 4283 opp-hz = /bits/ 64 <270000000>; 4284 required-opps = <&rpmhpd_opp_svs>; 4285 }; 4286 4287 opp-540000000 { 4288 opp-hz = /bits/ 64 <540000000>; 4289 required-opps = <&rpmhpd_opp_svs_l1>; 4290 }; 4291 4292 opp-810000000 { 4293 opp-hz = /bits/ 64 <810000000>; 4294 required-opps = <&rpmhpd_opp_nom>; 4295 }; 4296 }; 4297 }; 4298 4299 mdss_dp1: displayport-controller@ae98000 { 4300 compatible = "qcom,x1e80100-dp"; 4301 reg = <0 0xae98000 0 0x200>, 4302 <0 0xae98200 0 0x200>, 4303 <0 0xae98400 0 0x600>, 4304 <0 0xae99000 0 0x400>, 4305 <0 0xae99400 0 0x400>; 4306 4307 interrupts-extended = <&mdss 13>; 4308 4309 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4310 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 4311 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 4312 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4313 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4314 clock-names = "core_iface", 4315 "core_aux", 4316 "ctrl_link", 4317 "ctrl_link_iface", 4318 "stream_pixel"; 4319 4320 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4321 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4322 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4323 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4324 4325 operating-points-v2 = <&mdss_dp1_opp_table>; 4326 4327 power-domains = <&rpmhpd RPMHPD_MMCX>; 4328 4329 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; 4330 phy-names = "dp"; 4331 4332 #sound-dai-cells = <0>; 4333 4334 status = "disabled"; 4335 4336 ports { 4337 #address-cells = <1>; 4338 #size-cells = <0>; 4339 4340 port@0 { 4341 reg = <0>; 4342 4343 mdss_dp1_in: endpoint { 4344 remote-endpoint = <&mdss_intf4_out>; 4345 }; 4346 }; 4347 4348 port@1 { 4349 reg = <1>; 4350 4351 mdss_dp1_out: endpoint { 4352 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; 4353 }; 4354 }; 4355 }; 4356 4357 mdss_dp1_opp_table: opp-table { 4358 compatible = "operating-points-v2"; 4359 4360 opp-160000000 { 4361 opp-hz = /bits/ 64 <160000000>; 4362 required-opps = <&rpmhpd_opp_low_svs>; 4363 }; 4364 4365 opp-270000000 { 4366 opp-hz = /bits/ 64 <270000000>; 4367 required-opps = <&rpmhpd_opp_svs>; 4368 }; 4369 4370 opp-540000000 { 4371 opp-hz = /bits/ 64 <540000000>; 4372 required-opps = <&rpmhpd_opp_svs_l1>; 4373 }; 4374 4375 opp-810000000 { 4376 opp-hz = /bits/ 64 <810000000>; 4377 required-opps = <&rpmhpd_opp_nom>; 4378 }; 4379 }; 4380 }; 4381 4382 mdss_dp2: displayport-controller@ae9a000 { 4383 compatible = "qcom,x1e80100-dp"; 4384 reg = <0 0xae9a000 0 0x200>, 4385 <0 0xae9a200 0 0x200>, 4386 <0 0xae9a400 0 0x600>, 4387 <0 0xae9b000 0 0x400>, 4388 <0 0xae9b400 0 0x400>; 4389 4390 interrupts-extended = <&mdss 14>; 4391 4392 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4393 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 4394 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 4395 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4396 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4397 clock-names = "core_iface", 4398 "core_aux", 4399 "ctrl_link", 4400 "ctrl_link_iface", 4401 "stream_pixel"; 4402 4403 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4404 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4405 assigned-clock-parents = <&mdss_dp2_phy 0>, 4406 <&mdss_dp2_phy 1>; 4407 4408 operating-points-v2 = <&mdss_dp2_opp_table>; 4409 4410 power-domains = <&rpmhpd RPMHPD_MMCX>; 4411 4412 phys = <&mdss_dp2_phy>; 4413 phy-names = "dp"; 4414 4415 #sound-dai-cells = <0>; 4416 4417 status = "disabled"; 4418 4419 ports { 4420 #address-cells = <1>; 4421 #size-cells = <0>; 4422 4423 port@0 { 4424 reg = <0>; 4425 mdss_dp2_in: endpoint { 4426 remote-endpoint = <&mdss_intf6_out>; 4427 }; 4428 }; 4429 4430 port@1 { 4431 reg = <1>; 4432 4433 mdss_dp2_out: endpoint { 4434 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; 4435 }; 4436 }; 4437 }; 4438 4439 mdss_dp2_opp_table: opp-table { 4440 compatible = "operating-points-v2"; 4441 4442 opp-160000000 { 4443 opp-hz = /bits/ 64 <160000000>; 4444 required-opps = <&rpmhpd_opp_low_svs>; 4445 }; 4446 4447 opp-270000000 { 4448 opp-hz = /bits/ 64 <270000000>; 4449 required-opps = <&rpmhpd_opp_svs>; 4450 }; 4451 4452 opp-540000000 { 4453 opp-hz = /bits/ 64 <540000000>; 4454 required-opps = <&rpmhpd_opp_svs_l1>; 4455 }; 4456 4457 opp-810000000 { 4458 opp-hz = /bits/ 64 <810000000>; 4459 required-opps = <&rpmhpd_opp_nom>; 4460 }; 4461 }; 4462 }; 4463 4464 mdss_dp3: displayport-controller@aea0000 { 4465 compatible = "qcom,x1e80100-dp"; 4466 reg = <0 0xaea0000 0 0x200>, 4467 <0 0xaea0200 0 0x200>, 4468 <0 0xaea0400 0 0x600>, 4469 <0 0xaea1000 0 0x400>, 4470 <0 0xaea1400 0 0x400>; 4471 4472 interrupts-extended = <&mdss 15>; 4473 4474 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4475 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 4476 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 4477 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4478 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4479 clock-names = "core_iface", 4480 "core_aux", 4481 "ctrl_link", 4482 "ctrl_link_iface", 4483 "stream_pixel"; 4484 4485 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4486 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4487 assigned-clock-parents = <&mdss_dp3_phy 0>, 4488 <&mdss_dp3_phy 1>; 4489 4490 operating-points-v2 = <&mdss_dp3_opp_table>; 4491 4492 power-domains = <&rpmhpd RPMHPD_MMCX>; 4493 4494 phys = <&mdss_dp3_phy>; 4495 phy-names = "dp"; 4496 4497 #sound-dai-cells = <0>; 4498 4499 status = "disabled"; 4500 4501 ports { 4502 #address-cells = <1>; 4503 #size-cells = <0>; 4504 4505 port@0 { 4506 reg = <0>; 4507 4508 mdss_dp3_in: endpoint { 4509 remote-endpoint = <&mdss_intf5_out>; 4510 }; 4511 }; 4512 4513 port@1 { 4514 reg = <1>; 4515 }; 4516 }; 4517 4518 mdss_dp3_opp_table: opp-table { 4519 compatible = "operating-points-v2"; 4520 4521 opp-160000000 { 4522 opp-hz = /bits/ 64 <160000000>; 4523 required-opps = <&rpmhpd_opp_low_svs>; 4524 }; 4525 4526 opp-270000000 { 4527 opp-hz = /bits/ 64 <270000000>; 4528 required-opps = <&rpmhpd_opp_svs>; 4529 }; 4530 4531 opp-540000000 { 4532 opp-hz = /bits/ 64 <540000000>; 4533 required-opps = <&rpmhpd_opp_svs_l1>; 4534 }; 4535 4536 opp-810000000 { 4537 opp-hz = /bits/ 64 <810000000>; 4538 required-opps = <&rpmhpd_opp_nom>; 4539 }; 4540 }; 4541 }; 4542 4543 }; 4544 4545 mdss_dp2_phy: phy@aec2a00 { 4546 compatible = "qcom,x1e80100-dp-phy"; 4547 reg = <0 0x0aec2a00 0 0x19c>, 4548 <0 0x0aec2200 0 0xec>, 4549 <0 0x0aec2600 0 0xec>, 4550 <0 0x0aec2000 0 0x1c8>; 4551 4552 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 4553 <&dispcc DISP_CC_MDSS_AHB_CLK>; 4554 clock-names = "aux", 4555 "cfg_ahb"; 4556 4557 power-domains = <&rpmhpd RPMHPD_MX>; 4558 4559 #clock-cells = <1>; 4560 #phy-cells = <0>; 4561 4562 status = "disabled"; 4563 }; 4564 4565 mdss_dp3_phy: phy@aec5a00 { 4566 compatible = "qcom,x1e80100-dp-phy"; 4567 reg = <0 0x0aec5a00 0 0x19c>, 4568 <0 0x0aec5200 0 0xec>, 4569 <0 0x0aec5600 0 0xec>, 4570 <0 0x0aec5000 0 0x1c8>; 4571 4572 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 4573 <&dispcc DISP_CC_MDSS_AHB_CLK>; 4574 clock-names = "aux", 4575 "cfg_ahb"; 4576 4577 power-domains = <&rpmhpd RPMHPD_MX>; 4578 4579 #clock-cells = <1>; 4580 #phy-cells = <0>; 4581 4582 status = "disabled"; 4583 }; 4584 4585 dispcc: clock-controller@af00000 { 4586 compatible = "qcom,x1e80100-dispcc"; 4587 reg = <0 0x0af00000 0 0x20000>; 4588 clocks = <&bi_tcxo_div2>, 4589 <&bi_tcxo_ao_div2>, 4590 <&gcc GCC_DISP_AHB_CLK>, 4591 <&sleep_clk>, 4592 <0>, /* dsi0 */ 4593 <0>, 4594 <0>, /* dsi1 */ 4595 <0>, 4596 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 4597 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4598 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 4599 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4600 <&mdss_dp2_phy 0>, /* dp2 */ 4601 <&mdss_dp2_phy 1>, 4602 <&mdss_dp3_phy 0>, /* dp3 */ 4603 <&mdss_dp3_phy 1>; 4604 power-domains = <&rpmhpd RPMHPD_MMCX>; 4605 required-opps = <&rpmhpd_opp_low_svs>; 4606 #clock-cells = <1>; 4607 #reset-cells = <1>; 4608 #power-domain-cells = <1>; 4609 }; 4610 4611 pdc: interrupt-controller@b220000 { 4612 compatible = "qcom,x1e80100-pdc", "qcom,pdc"; 4613 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 4614 4615 qcom,pdc-ranges = <0 480 42>, <42 251 5>, 4616 <47 522 52>, <99 609 32>, 4617 <131 717 12>, <143 816 19>; 4618 #interrupt-cells = <2>; 4619 interrupt-parent = <&intc>; 4620 interrupt-controller; 4621 }; 4622 4623 aoss_qmp: power-management@c300000 { 4624 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp"; 4625 reg = <0 0x0c300000 0 0x400>; 4626 interrupt-parent = <&ipcc>; 4627 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4628 IRQ_TYPE_EDGE_RISING>; 4629 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4630 4631 #clock-cells = <0>; 4632 }; 4633 4634 spmi: arbiter@c400000 { 4635 compatible = "qcom,x1e80100-spmi-pmic-arb"; 4636 reg = <0 0x0c400000 0 0x3000>, 4637 <0 0x0c500000 0 0x400000>, 4638 <0 0x0c440000 0 0x80000>; 4639 reg-names = "core", "chnls", "obsrvr"; 4640 4641 qcom,ee = <0>; 4642 qcom,channel = <0>; 4643 4644 #address-cells = <2>; 4645 #size-cells = <2>; 4646 ranges; 4647 4648 spmi_bus0: spmi@c42d000 { 4649 reg = <0 0x0c42d000 0 0x4000>, 4650 <0 0x0c4c0000 0 0x10000>; 4651 reg-names = "cnfg", "intr"; 4652 4653 interrupt-names = "periph_irq"; 4654 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4655 interrupt-controller; 4656 #interrupt-cells = <4>; 4657 4658 #address-cells = <2>; 4659 #size-cells = <0>; 4660 }; 4661 4662 spmi_bus1: spmi@c432000 { 4663 reg = <0 0x0c432000 0 0x4000>, 4664 <0 0x0c4d0000 0 0x10000>; 4665 reg-names = "cnfg", "intr"; 4666 4667 interrupt-names = "periph_irq"; 4668 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 4669 interrupt-controller; 4670 #interrupt-cells = <4>; 4671 4672 #address-cells = <2>; 4673 #size-cells = <0>; 4674 }; 4675 }; 4676 4677 tlmm: pinctrl@f100000 { 4678 compatible = "qcom,x1e80100-tlmm"; 4679 reg = <0 0x0f100000 0 0xf00000>; 4680 4681 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4682 4683 gpio-controller; 4684 #gpio-cells = <2>; 4685 4686 interrupt-controller; 4687 #interrupt-cells = <2>; 4688 4689 gpio-ranges = <&tlmm 0 0 239>; 4690 wakeup-parent = <&pdc>; 4691 4692 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4693 /* SDA, SCL */ 4694 pins = "gpio0", "gpio1"; 4695 function = "qup0_se0"; 4696 drive-strength = <2>; 4697 bias-pull-up = <2200>; 4698 }; 4699 4700 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4701 /* SDA, SCL */ 4702 pins = "gpio4", "gpio5"; 4703 function = "qup0_se1"; 4704 drive-strength = <2>; 4705 bias-pull-up = <2200>; 4706 }; 4707 4708 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4709 /* SDA, SCL */ 4710 pins = "gpio8", "gpio9"; 4711 function = "qup0_se2"; 4712 drive-strength = <2>; 4713 bias-pull-up = <2200>; 4714 }; 4715 4716 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4717 /* SDA, SCL */ 4718 pins = "gpio12", "gpio13"; 4719 function = "qup0_se3"; 4720 drive-strength = <2>; 4721 bias-pull-up = <2200>; 4722 }; 4723 4724 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4725 /* SDA, SCL */ 4726 pins = "gpio16", "gpio17"; 4727 function = "qup0_se4"; 4728 drive-strength = <2>; 4729 bias-pull-up = <2200>; 4730 }; 4731 4732 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4733 /* SDA, SCL */ 4734 pins = "gpio20", "gpio21"; 4735 function = "qup0_se5"; 4736 drive-strength = <2>; 4737 bias-pull-up = <2200>; 4738 }; 4739 4740 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4741 /* SDA, SCL */ 4742 pins = "gpio24", "gpio25"; 4743 function = "qup0_se6"; 4744 drive-strength = <2>; 4745 bias-pull-up = <2200>; 4746 }; 4747 4748 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4749 /* SDA, SCL */ 4750 pins = "gpio14", "gpio15"; 4751 function = "qup0_se7"; 4752 drive-strength = <2>; 4753 bias-pull-up = <2200>; 4754 }; 4755 4756 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4757 /* SDA, SCL */ 4758 pins = "gpio32", "gpio33"; 4759 function = "qup1_se0"; 4760 drive-strength = <2>; 4761 bias-pull-up = <2200>; 4762 }; 4763 4764 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4765 /* SDA, SCL */ 4766 pins = "gpio36", "gpio37"; 4767 function = "qup1_se1"; 4768 drive-strength = <2>; 4769 bias-pull-up = <2200>; 4770 }; 4771 4772 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4773 /* SDA, SCL */ 4774 pins = "gpio40", "gpio41"; 4775 function = "qup1_se2"; 4776 drive-strength = <2>; 4777 bias-pull-up = <2200>; 4778 }; 4779 4780 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4781 /* SDA, SCL */ 4782 pins = "gpio44", "gpio45"; 4783 function = "qup1_se3"; 4784 drive-strength = <2>; 4785 bias-pull-up = <2200>; 4786 }; 4787 4788 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4789 /* SDA, SCL */ 4790 pins = "gpio48", "gpio49"; 4791 function = "qup1_se4"; 4792 drive-strength = <2>; 4793 bias-pull-up = <2200>; 4794 }; 4795 4796 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4797 /* SDA, SCL */ 4798 pins = "gpio52", "gpio53"; 4799 function = "qup1_se5"; 4800 drive-strength = <2>; 4801 bias-pull-up = <2200>; 4802 }; 4803 4804 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4805 /* SDA, SCL */ 4806 pins = "gpio56", "gpio57"; 4807 function = "qup1_se6"; 4808 drive-strength = <2>; 4809 bias-pull-up = <2200>; 4810 }; 4811 4812 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4813 /* SDA, SCL */ 4814 pins = "gpio54", "gpio55"; 4815 function = "qup1_se7"; 4816 drive-strength = <2>; 4817 bias-pull-up = <2200>; 4818 }; 4819 4820 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 4821 /* SDA, SCL */ 4822 pins = "gpio64", "gpio65"; 4823 function = "qup2_se0"; 4824 drive-strength = <2>; 4825 bias-pull-up = <2200>; 4826 }; 4827 4828 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 4829 /* SDA, SCL */ 4830 pins = "gpio68", "gpio69"; 4831 function = "qup2_se1"; 4832 drive-strength = <2>; 4833 bias-pull-up = <2200>; 4834 }; 4835 4836 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 4837 /* SDA, SCL */ 4838 pins = "gpio72", "gpio73"; 4839 function = "qup2_se2"; 4840 drive-strength = <2>; 4841 bias-pull-up = <2200>; 4842 }; 4843 4844 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 4845 /* SDA, SCL */ 4846 pins = "gpio76", "gpio77"; 4847 function = "qup2_se3"; 4848 drive-strength = <2>; 4849 bias-pull-up = <2200>; 4850 }; 4851 4852 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 4853 /* SDA, SCL */ 4854 pins = "gpio80", "gpio81"; 4855 function = "qup2_se4"; 4856 drive-strength = <2>; 4857 bias-pull-up = <2200>; 4858 }; 4859 4860 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 4861 /* SDA, SCL */ 4862 pins = "gpio84", "gpio85"; 4863 function = "qup2_se5"; 4864 drive-strength = <2>; 4865 bias-pull-up = <2200>; 4866 }; 4867 4868 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 4869 /* SDA, SCL */ 4870 pins = "gpio88", "gpio89"; 4871 function = "qup2_se6"; 4872 drive-strength = <2>; 4873 bias-pull-up = <2200>; 4874 }; 4875 4876 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 4877 /* SDA, SCL */ 4878 pins = "gpio86", "gpio87"; 4879 function = "qup2_se7"; 4880 drive-strength = <2>; 4881 bias-pull-up = <2200>; 4882 }; 4883 4884 qup_spi0_cs: qup-spi0-cs-state { 4885 pins = "gpio3"; 4886 function = "qup0_se0"; 4887 drive-strength = <6>; 4888 bias-disable; 4889 }; 4890 4891 qup_spi0_data_clk: qup-spi0-data-clk-state { 4892 /* MISO, MOSI, CLK */ 4893 pins = "gpio0", "gpio1", "gpio2"; 4894 function = "qup0_se0"; 4895 drive-strength = <6>; 4896 bias-disable; 4897 }; 4898 4899 qup_spi1_cs: qup-spi1-cs-state { 4900 pins = "gpio7"; 4901 function = "qup0_se1"; 4902 drive-strength = <6>; 4903 bias-disable; 4904 }; 4905 4906 qup_spi1_data_clk: qup-spi1-data-clk-state { 4907 /* MISO, MOSI, CLK */ 4908 pins = "gpio4", "gpio5", "gpio6"; 4909 function = "qup0_se1"; 4910 drive-strength = <6>; 4911 bias-disable; 4912 }; 4913 4914 qup_spi2_cs: qup-spi2-cs-state { 4915 pins = "gpio11"; 4916 function = "qup0_se2"; 4917 drive-strength = <6>; 4918 bias-disable; 4919 }; 4920 4921 qup_spi2_data_clk: qup-spi2-data-clk-state { 4922 /* MISO, MOSI, CLK */ 4923 pins = "gpio8", "gpio9", "gpio10"; 4924 function = "qup0_se2"; 4925 drive-strength = <6>; 4926 bias-disable; 4927 }; 4928 4929 qup_spi3_cs: qup-spi3-cs-state { 4930 pins = "gpio15"; 4931 function = "qup0_se3"; 4932 drive-strength = <6>; 4933 bias-disable; 4934 }; 4935 4936 qup_spi3_data_clk: qup-spi3-data-clk-state { 4937 /* MISO, MOSI, CLK */ 4938 pins = "gpio12", "gpio13", "gpio14"; 4939 function = "qup0_se3"; 4940 drive-strength = <6>; 4941 bias-disable; 4942 }; 4943 4944 qup_spi4_cs: qup-spi4-cs-state { 4945 pins = "gpio19"; 4946 function = "qup0_se4"; 4947 drive-strength = <6>; 4948 bias-disable; 4949 }; 4950 4951 qup_spi4_data_clk: qup-spi4-data-clk-state { 4952 /* MISO, MOSI, CLK */ 4953 pins = "gpio16", "gpio17", "gpio18"; 4954 function = "qup0_se4"; 4955 drive-strength = <6>; 4956 bias-disable; 4957 }; 4958 4959 qup_spi5_cs: qup-spi5-cs-state { 4960 pins = "gpio23"; 4961 function = "qup0_se5"; 4962 drive-strength = <6>; 4963 bias-disable; 4964 }; 4965 4966 qup_spi5_data_clk: qup-spi5-data-clk-state { 4967 /* MISO, MOSI, CLK */ 4968 pins = "gpio20", "gpio21", "gpio22"; 4969 function = "qup0_se5"; 4970 drive-strength = <6>; 4971 bias-disable; 4972 }; 4973 4974 qup_spi6_cs: qup-spi6-cs-state { 4975 pins = "gpio27"; 4976 function = "qup0_se6"; 4977 drive-strength = <6>; 4978 bias-disable; 4979 }; 4980 4981 qup_spi6_data_clk: qup-spi6-data-clk-state { 4982 /* MISO, MOSI, CLK */ 4983 pins = "gpio24", "gpio25", "gpio26"; 4984 function = "qup0_se6"; 4985 drive-strength = <6>; 4986 bias-disable; 4987 }; 4988 4989 qup_spi7_cs: qup-spi7-cs-state { 4990 pins = "gpio13"; 4991 function = "qup0_se7"; 4992 drive-strength = <6>; 4993 bias-disable; 4994 }; 4995 4996 qup_spi7_data_clk: qup-spi7-data-clk-state { 4997 /* MISO, MOSI, CLK */ 4998 pins = "gpio14", "gpio15", "gpio12"; 4999 function = "qup0_se7"; 5000 drive-strength = <6>; 5001 bias-disable; 5002 }; 5003 5004 qup_spi8_cs: qup-spi8-cs-state { 5005 pins = "gpio35"; 5006 function = "qup1_se0"; 5007 drive-strength = <6>; 5008 bias-disable; 5009 }; 5010 5011 qup_spi8_data_clk: qup-spi8-data-clk-state { 5012 /* MISO, MOSI, CLK */ 5013 pins = "gpio32", "gpio33", "gpio34"; 5014 function = "qup1_se0"; 5015 drive-strength = <6>; 5016 bias-disable; 5017 }; 5018 5019 qup_spi9_cs: qup-spi9-cs-state { 5020 pins = "gpio39"; 5021 function = "qup1_se1"; 5022 drive-strength = <6>; 5023 bias-disable; 5024 }; 5025 5026 qup_spi9_data_clk: qup-spi9-data-clk-state { 5027 /* MISO, MOSI, CLK */ 5028 pins = "gpio36", "gpio37", "gpio38"; 5029 function = "qup1_se1"; 5030 drive-strength = <6>; 5031 bias-disable; 5032 }; 5033 5034 qup_spi10_cs: qup-spi10-cs-state { 5035 pins = "gpio43"; 5036 function = "qup1_se2"; 5037 drive-strength = <6>; 5038 bias-disable; 5039 }; 5040 5041 qup_spi10_data_clk: qup-spi10-data-clk-state { 5042 /* MISO, MOSI, CLK */ 5043 pins = "gpio40", "gpio41", "gpio42"; 5044 function = "qup1_se2"; 5045 drive-strength = <6>; 5046 bias-disable; 5047 }; 5048 5049 qup_spi11_cs: qup-spi11-cs-state { 5050 pins = "gpio47"; 5051 function = "qup1_se3"; 5052 drive-strength = <6>; 5053 bias-disable; 5054 }; 5055 5056 qup_spi11_data_clk: qup-spi11-data-clk-state { 5057 /* MISO, MOSI, CLK */ 5058 pins = "gpio44", "gpio45", "gpio46"; 5059 function = "qup1_se3"; 5060 drive-strength = <6>; 5061 bias-disable; 5062 }; 5063 5064 qup_spi12_cs: qup-spi12-cs-state { 5065 pins = "gpio51"; 5066 function = "qup1_se4"; 5067 drive-strength = <6>; 5068 bias-disable; 5069 }; 5070 5071 qup_spi12_data_clk: qup-spi12-data-clk-state { 5072 /* MISO, MOSI, CLK */ 5073 pins = "gpio48", "gpio49", "gpio50"; 5074 function = "qup1_se4"; 5075 drive-strength = <6>; 5076 bias-disable; 5077 }; 5078 5079 qup_spi13_cs: qup-spi13-cs-state { 5080 pins = "gpio55"; 5081 function = "qup1_se5"; 5082 drive-strength = <6>; 5083 bias-disable; 5084 }; 5085 5086 qup_spi13_data_clk: qup-spi13-data-clk-state { 5087 /* MISO, MOSI, CLK */ 5088 pins = "gpio52", "gpio53", "gpio54"; 5089 function = "qup1_se5"; 5090 drive-strength = <6>; 5091 bias-disable; 5092 }; 5093 5094 qup_spi14_cs: qup-spi14-cs-state { 5095 pins = "gpio59"; 5096 function = "qup1_se6"; 5097 drive-strength = <6>; 5098 bias-disable; 5099 }; 5100 5101 qup_spi14_data_clk: qup-spi14-data-clk-state { 5102 /* MISO, MOSI, CLK */ 5103 pins = "gpio56", "gpio57", "gpio58"; 5104 function = "qup1_se6"; 5105 drive-strength = <6>; 5106 bias-disable; 5107 }; 5108 5109 qup_spi15_cs: qup-spi15-cs-state { 5110 pins = "gpio53"; 5111 function = "qup1_se7"; 5112 drive-strength = <6>; 5113 bias-disable; 5114 }; 5115 5116 qup_spi15_data_clk: qup-spi15-data-clk-state { 5117 /* MISO, MOSI, CLK */ 5118 pins = "gpio54", "gpio55", "gpio52"; 5119 function = "qup1_se7"; 5120 drive-strength = <6>; 5121 bias-disable; 5122 }; 5123 5124 qup_spi16_cs: qup-spi16-cs-state { 5125 pins = "gpio67"; 5126 function = "qup2_se0"; 5127 drive-strength = <6>; 5128 bias-disable; 5129 }; 5130 5131 qup_spi16_data_clk: qup-spi16-data-clk-state { 5132 /* MISO, MOSI, CLK */ 5133 pins = "gpio64", "gpio65", "gpio66"; 5134 function = "qup2_se0"; 5135 drive-strength = <6>; 5136 bias-disable; 5137 }; 5138 5139 qup_spi17_cs: qup-spi17-cs-state { 5140 pins = "gpio71"; 5141 function = "qup2_se1"; 5142 drive-strength = <6>; 5143 bias-disable; 5144 }; 5145 5146 qup_spi17_data_clk: qup-spi17-data-clk-state { 5147 /* MISO, MOSI, CLK */ 5148 pins = "gpio68", "gpio69", "gpio70"; 5149 function = "qup2_se1"; 5150 drive-strength = <6>; 5151 bias-disable; 5152 }; 5153 5154 qup_spi18_cs: qup-spi18-cs-state { 5155 pins = "gpio75"; 5156 function = "qup2_se2"; 5157 drive-strength = <6>; 5158 bias-disable; 5159 }; 5160 5161 qup_spi18_data_clk: qup-spi18-data-clk-state { 5162 /* MISO, MOSI, CLK */ 5163 pins = "gpio72", "gpio73", "gpio74"; 5164 function = "qup2_se2"; 5165 drive-strength = <6>; 5166 bias-disable; 5167 }; 5168 5169 qup_spi19_cs: qup-spi19-cs-state { 5170 pins = "gpio79"; 5171 function = "qup2_se3"; 5172 drive-strength = <6>; 5173 bias-disable; 5174 }; 5175 5176 qup_spi19_data_clk: qup-spi19-data-clk-state { 5177 /* MISO, MOSI, CLK */ 5178 pins = "gpio76", "gpio77", "gpio78"; 5179 function = "qup2_se3"; 5180 drive-strength = <6>; 5181 bias-disable; 5182 }; 5183 5184 qup_spi20_cs: qup-spi20-cs-state { 5185 pins = "gpio83"; 5186 function = "qup2_se4"; 5187 drive-strength = <6>; 5188 bias-disable; 5189 }; 5190 5191 qup_spi20_data_clk: qup-spi20-data-clk-state { 5192 /* MISO, MOSI, CLK */ 5193 pins = "gpio80", "gpio81", "gpio82"; 5194 function = "qup2_se4"; 5195 drive-strength = <6>; 5196 bias-disable; 5197 }; 5198 5199 qup_spi21_cs: qup-spi21-cs-state { 5200 pins = "gpio87"; 5201 function = "qup2_se5"; 5202 drive-strength = <6>; 5203 bias-disable; 5204 }; 5205 5206 qup_spi21_data_clk: qup-spi21-data-clk-state { 5207 /* MISO, MOSI, CLK */ 5208 pins = "gpio84", "gpio85", "gpio86"; 5209 function = "qup2_se5"; 5210 drive-strength = <6>; 5211 bias-disable; 5212 }; 5213 5214 qup_spi22_cs: qup-spi22-cs-state { 5215 pins = "gpio91"; 5216 function = "qup2_se6"; 5217 drive-strength = <6>; 5218 bias-disable; 5219 }; 5220 5221 qup_spi22_data_clk: qup-spi22-data-clk-state { 5222 /* MISO, MOSI, CLK */ 5223 pins = "gpio88", "gpio89", "gpio90"; 5224 function = "qup2_se6"; 5225 drive-strength = <6>; 5226 bias-disable; 5227 }; 5228 5229 qup_spi23_cs: qup-spi23-cs-state { 5230 pins = "gpio85"; 5231 function = "qup2_se7"; 5232 drive-strength = <6>; 5233 bias-disable; 5234 }; 5235 5236 qup_spi23_data_clk: qup-spi23-data-clk-state { 5237 /* MISO, MOSI, CLK */ 5238 pins = "gpio86", "gpio87", "gpio84"; 5239 function = "qup2_se7"; 5240 drive-strength = <6>; 5241 bias-disable; 5242 }; 5243 5244 qup_uart21_default: qup-uart21-default-state { 5245 /* TX, RX */ 5246 pins = "gpio86", "gpio87"; 5247 function = "qup2_se5"; 5248 drive-strength = <2>; 5249 bias-disable; 5250 }; 5251 }; 5252 5253 apps_smmu: iommu@15000000 { 5254 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5255 reg = <0 0x15000000 0 0x100000>; 5256 5257 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5258 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5259 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5260 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5261 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5262 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5263 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5264 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5265 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5266 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5267 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5268 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5269 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5270 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5271 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5272 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5273 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5274 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5275 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5276 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5277 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5278 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5279 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5280 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5281 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5282 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5283 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5284 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5285 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5286 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5287 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5288 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5289 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5290 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5291 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5292 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5293 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5294 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5295 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5296 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5297 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5298 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5299 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5300 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5301 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5302 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5303 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5304 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5305 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5306 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5307 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5308 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5309 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5310 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5311 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5312 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5313 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5314 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5315 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5316 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5317 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5318 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5319 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5320 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5321 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5322 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5323 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5324 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5325 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5326 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5327 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5328 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5329 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5330 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5331 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5332 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5333 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5334 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5335 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5336 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5337 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5338 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5339 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5340 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5341 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5342 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5343 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5344 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5345 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5346 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5347 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5348 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5349 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5350 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5351 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5352 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5353 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 5354 5355 #iommu-cells = <2>; 5356 #global-interrupts = <1>; 5357 }; 5358 5359 intc: interrupt-controller@17000000 { 5360 compatible = "arm,gic-v3"; 5361 reg = <0 0x17000000 0 0x10000>, /* GICD */ 5362 <0 0x17080000 0 0x480000>; /* GICR * 12 */ 5363 5364 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5365 5366 #interrupt-cells = <3>; 5367 interrupt-controller; 5368 5369 #redistributor-regions = <1>; 5370 redistributor-stride = <0x0 0x40000>; 5371 5372 #address-cells = <2>; 5373 #size-cells = <2>; 5374 ranges; 5375 5376 gic_its: msi-controller@17040000 { 5377 compatible = "arm,gic-v3-its"; 5378 reg = <0 0x17040000 0 0x40000>; 5379 5380 msi-controller; 5381 #msi-cells = <1>; 5382 5383 status = "disabled"; 5384 }; 5385 }; 5386 5387 apps_rsc: rsc@17500000 { 5388 compatible = "qcom,rpmh-rsc"; 5389 reg = <0 0x17500000 0 0x10000>, 5390 <0 0x17510000 0 0x10000>, 5391 <0 0x17520000 0 0x10000>; 5392 reg-names = "drv-0", "drv-1", "drv-2"; 5393 5394 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5395 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5396 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5397 qcom,tcs-offset = <0xd00>; 5398 qcom,drv-id = <2>; 5399 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 5400 <WAKE_TCS 2>, <CONTROL_TCS 0>; 5401 5402 label = "apps_rsc"; 5403 power-domains = <&SYSTEM_PD>; 5404 5405 apps_bcm_voter: bcm-voter { 5406 compatible = "qcom,bcm-voter"; 5407 }; 5408 5409 rpmhcc: clock-controller { 5410 compatible = "qcom,x1e80100-rpmh-clk"; 5411 5412 clocks = <&xo_board>; 5413 clock-names = "xo"; 5414 5415 #clock-cells = <1>; 5416 }; 5417 5418 rpmhpd: power-controller { 5419 compatible = "qcom,x1e80100-rpmhpd"; 5420 5421 operating-points-v2 = <&rpmhpd_opp_table>; 5422 5423 #power-domain-cells = <1>; 5424 5425 rpmhpd_opp_table: opp-table { 5426 compatible = "operating-points-v2"; 5427 5428 rpmhpd_opp_ret: opp-16 { 5429 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5430 }; 5431 5432 rpmhpd_opp_min_svs: opp-48 { 5433 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5434 }; 5435 5436 rpmhpd_opp_low_svs_d2: opp-52 { 5437 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5438 }; 5439 5440 rpmhpd_opp_low_svs_d1: opp-56 { 5441 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5442 }; 5443 5444 rpmhpd_opp_low_svs_d0: opp-60 { 5445 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5446 }; 5447 5448 rpmhpd_opp_low_svs: opp-64 { 5449 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5450 }; 5451 5452 rpmhpd_opp_low_svs_l1: opp-80 { 5453 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5454 }; 5455 5456 rpmhpd_opp_svs: opp-128 { 5457 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5458 }; 5459 5460 rpmhpd_opp_svs_l0: opp-144 { 5461 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5462 }; 5463 5464 rpmhpd_opp_svs_l1: opp-192 { 5465 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5466 }; 5467 5468 rpmhpd_opp_nom: opp-256 { 5469 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5470 }; 5471 5472 rpmhpd_opp_nom_l1: opp-320 { 5473 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5474 }; 5475 5476 rpmhpd_opp_nom_l2: opp-336 { 5477 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5478 }; 5479 5480 rpmhpd_opp_turbo: opp-384 { 5481 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5482 }; 5483 5484 rpmhpd_opp_turbo_l1: opp-416 { 5485 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5486 }; 5487 }; 5488 }; 5489 }; 5490 5491 timer@17800000 { 5492 compatible = "arm,armv7-timer-mem"; 5493 reg = <0 0x17800000 0 0x1000>; 5494 5495 #address-cells = <2>; 5496 #size-cells = <1>; 5497 ranges = <0 0 0 0 0x20000000>; 5498 5499 frame@17801000 { 5500 reg = <0 0x17801000 0x1000>, 5501 <0 0x17802000 0x1000>; 5502 5503 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5504 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5505 5506 frame-number = <0>; 5507 }; 5508 5509 frame@17803000 { 5510 reg = <0 0x17803000 0x1000>; 5511 5512 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5513 5514 frame-number = <1>; 5515 5516 status = "disabled"; 5517 }; 5518 5519 frame@17805000 { 5520 reg = <0 0x17805000 0x1000>; 5521 5522 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5523 5524 frame-number = <2>; 5525 5526 status = "disabled"; 5527 }; 5528 5529 frame@17807000 { 5530 reg = <0 0x17807000 0x1000>; 5531 5532 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5533 5534 frame-number = <3>; 5535 5536 status = "disabled"; 5537 }; 5538 5539 frame@17809000 { 5540 reg = <0 0x17809000 0x1000>; 5541 5542 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5543 5544 frame-number = <4>; 5545 5546 status = "disabled"; 5547 }; 5548 5549 frame@1780b000 { 5550 reg = <0 0x1780b000 0x1000>; 5551 5552 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5553 5554 frame-number = <5>; 5555 5556 status = "disabled"; 5557 }; 5558 5559 frame@1780d000 { 5560 reg = <0 0x1780d000 0x1000>; 5561 5562 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5563 5564 frame-number = <6>; 5565 5566 status = "disabled"; 5567 }; 5568 }; 5569 5570 pmu@24091000 { 5571 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 5572 reg = <0 0x24091000 0 0x1000>; 5573 5574 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 5575 5576 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 5577 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5578 5579 operating-points-v2 = <&llcc_bwmon_opp_table>; 5580 5581 llcc_bwmon_opp_table: opp-table { 5582 compatible = "operating-points-v2"; 5583 5584 opp-0 { 5585 opp-peak-kBps = <800000>; 5586 }; 5587 5588 opp-1 { 5589 opp-peak-kBps = <2188000>; 5590 }; 5591 5592 opp-2 { 5593 opp-peak-kBps = <3072000>; 5594 }; 5595 5596 opp-3 { 5597 opp-peak-kBps = <6220800>; 5598 }; 5599 5600 opp-4 { 5601 opp-peak-kBps = <6835200>; 5602 }; 5603 5604 opp-5 { 5605 opp-peak-kBps = <8371200>; 5606 }; 5607 5608 opp-6 { 5609 opp-peak-kBps = <10944000>; 5610 }; 5611 5612 opp-7 { 5613 opp-peak-kBps = <12748800>; 5614 }; 5615 5616 opp-8 { 5617 opp-peak-kBps = <14745600>; 5618 }; 5619 5620 opp-9 { 5621 opp-peak-kBps = <16896000>; 5622 }; 5623 }; 5624 }; 5625 5626 /* cluster0 */ 5627 pmu@240b3400 { 5628 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 5629 reg = <0 0x240b3400 0 0x600>; 5630 5631 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5632 5633 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5634 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5635 5636 operating-points-v2 = <&cpu_bwmon_opp_table>; 5637 5638 cpu_bwmon_opp_table: opp-table { 5639 compatible = "operating-points-v2"; 5640 5641 opp-0 { 5642 opp-peak-kBps = <4800000>; 5643 }; 5644 5645 opp-1 { 5646 opp-peak-kBps = <7464000>; 5647 }; 5648 5649 opp-2 { 5650 opp-peak-kBps = <9600000>; 5651 }; 5652 5653 opp-3 { 5654 opp-peak-kBps = <12896000>; 5655 }; 5656 5657 opp-4 { 5658 opp-peak-kBps = <14928000>; 5659 }; 5660 5661 opp-5 { 5662 opp-peak-kBps = <17064000>; 5663 }; 5664 }; 5665 }; 5666 5667 /* cluster2 */ 5668 pmu@240b5400 { 5669 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 5670 reg = <0 0x240b5400 0 0x600>; 5671 5672 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5673 5674 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5675 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5676 5677 operating-points-v2 = <&cpu_bwmon_opp_table>; 5678 }; 5679 5680 /* cluster1 */ 5681 pmu@240b6400 { 5682 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 5683 reg = <0 0x240b6400 0 0x600>; 5684 5685 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5686 5687 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5688 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5689 5690 operating-points-v2 = <&cpu_bwmon_opp_table>; 5691 }; 5692 5693 system-cache-controller@25000000 { 5694 compatible = "qcom,x1e80100-llcc"; 5695 reg = <0 0x25000000 0 0x200000>, 5696 <0 0x25200000 0 0x200000>, 5697 <0 0x25400000 0 0x200000>, 5698 <0 0x25600000 0 0x200000>, 5699 <0 0x25800000 0 0x200000>, 5700 <0 0x25a00000 0 0x200000>, 5701 <0 0x25c00000 0 0x200000>, 5702 <0 0x25e00000 0 0x200000>, 5703 <0 0x26000000 0 0x200000>; 5704 reg-names = "llcc0_base", 5705 "llcc1_base", 5706 "llcc2_base", 5707 "llcc3_base", 5708 "llcc4_base", 5709 "llcc5_base", 5710 "llcc6_base", 5711 "llcc7_base", 5712 "llcc_broadcast_base"; 5713 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 5714 }; 5715 5716 remoteproc_adsp: remoteproc@30000000 { 5717 compatible = "qcom,x1e80100-adsp-pas"; 5718 reg = <0 0x30000000 0 0x100>; 5719 5720 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 5721 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5722 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5723 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5724 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5725 interrupt-names = "wdog", 5726 "fatal", 5727 "ready", 5728 "handover", 5729 "stop-ack"; 5730 5731 clocks = <&rpmhcc RPMH_CXO_CLK>; 5732 clock-names = "xo"; 5733 5734 power-domains = <&rpmhpd RPMHPD_LCX>, 5735 <&rpmhpd RPMHPD_LMX>; 5736 power-domain-names = "lcx", 5737 "lmx"; 5738 5739 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 5740 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5741 5742 memory-region = <&adspslpi_mem>, 5743 <&q6_adsp_dtb_mem>; 5744 5745 qcom,qmp = <&aoss_qmp>; 5746 5747 qcom,smem-states = <&smp2p_adsp_out 0>; 5748 qcom,smem-state-names = "stop"; 5749 5750 status = "disabled"; 5751 5752 glink-edge { 5753 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5754 IPCC_MPROC_SIGNAL_GLINK_QMP 5755 IRQ_TYPE_EDGE_RISING>; 5756 mboxes = <&ipcc IPCC_CLIENT_LPASS 5757 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5758 5759 label = "lpass"; 5760 qcom,remote-pid = <2>; 5761 5762 fastrpc { 5763 compatible = "qcom,fastrpc"; 5764 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5765 label = "adsp"; 5766 qcom,non-secure-domain; 5767 #address-cells = <1>; 5768 #size-cells = <0>; 5769 5770 compute-cb@3 { 5771 compatible = "qcom,fastrpc-compute-cb"; 5772 reg = <3>; 5773 iommus = <&apps_smmu 0x1003 0x80>, 5774 <&apps_smmu 0x1063 0x0>; 5775 dma-coherent; 5776 }; 5777 5778 compute-cb@4 { 5779 compatible = "qcom,fastrpc-compute-cb"; 5780 reg = <4>; 5781 iommus = <&apps_smmu 0x1004 0x80>, 5782 <&apps_smmu 0x1064 0x0>; 5783 dma-coherent; 5784 }; 5785 5786 compute-cb@5 { 5787 compatible = "qcom,fastrpc-compute-cb"; 5788 reg = <5>; 5789 iommus = <&apps_smmu 0x1005 0x80>, 5790 <&apps_smmu 0x1065 0x0>; 5791 dma-coherent; 5792 }; 5793 5794 compute-cb@6 { 5795 compatible = "qcom,fastrpc-compute-cb"; 5796 reg = <6>; 5797 iommus = <&apps_smmu 0x1006 0x80>, 5798 <&apps_smmu 0x1066 0x0>; 5799 dma-coherent; 5800 }; 5801 5802 compute-cb@7 { 5803 compatible = "qcom,fastrpc-compute-cb"; 5804 reg = <7>; 5805 iommus = <&apps_smmu 0x1007 0x80>, 5806 <&apps_smmu 0x1067 0x0>; 5807 dma-coherent; 5808 }; 5809 }; 5810 5811 gpr { 5812 compatible = "qcom,gpr"; 5813 qcom,glink-channels = "adsp_apps"; 5814 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 5815 qcom,intents = <512 20>; 5816 #address-cells = <1>; 5817 #size-cells = <0>; 5818 5819 q6apm: service@1 { 5820 compatible = "qcom,q6apm"; 5821 reg = <GPR_APM_MODULE_IID>; 5822 #sound-dai-cells = <0>; 5823 qcom,protection-domain = "avs/audio", 5824 "msm/adsp/audio_pd"; 5825 5826 q6apmbedai: bedais { 5827 compatible = "qcom,q6apm-lpass-dais"; 5828 #sound-dai-cells = <1>; 5829 }; 5830 5831 q6apmdai: dais { 5832 compatible = "qcom,q6apm-dais"; 5833 iommus = <&apps_smmu 0x1001 0x80>, 5834 <&apps_smmu 0x1061 0x0>; 5835 }; 5836 }; 5837 5838 q6prm: service@2 { 5839 compatible = "qcom,q6prm"; 5840 reg = <GPR_PRM_MODULE_IID>; 5841 qcom,protection-domain = "avs/audio", 5842 "msm/adsp/audio_pd"; 5843 5844 q6prmcc: clock-controller { 5845 compatible = "qcom,q6prm-lpass-clocks"; 5846 #clock-cells = <2>; 5847 }; 5848 }; 5849 }; 5850 }; 5851 }; 5852 5853 remoteproc_cdsp: remoteproc@32300000 { 5854 compatible = "qcom,x1e80100-cdsp-pas"; 5855 reg = <0 0x32300000 0 0x1400000>; 5856 5857 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5858 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 5859 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 5860 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 5861 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 5862 interrupt-names = "wdog", 5863 "fatal", 5864 "ready", 5865 "handover", 5866 "stop-ack"; 5867 5868 clocks = <&rpmhcc RPMH_CXO_CLK>; 5869 clock-names = "xo"; 5870 5871 power-domains = <&rpmhpd RPMHPD_CX>, 5872 <&rpmhpd RPMHPD_MXC>, 5873 <&rpmhpd RPMHPD_NSP>; 5874 power-domain-names = "cx", 5875 "mxc", 5876 "nsp"; 5877 5878 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 5879 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5880 5881 memory-region = <&cdsp_mem>, 5882 <&q6_cdsp_dtb_mem>; 5883 5884 qcom,qmp = <&aoss_qmp>; 5885 5886 qcom,smem-states = <&smp2p_cdsp_out 0>; 5887 qcom,smem-state-names = "stop"; 5888 5889 status = "disabled"; 5890 5891 glink-edge { 5892 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5893 IPCC_MPROC_SIGNAL_GLINK_QMP 5894 IRQ_TYPE_EDGE_RISING>; 5895 mboxes = <&ipcc IPCC_CLIENT_CDSP 5896 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5897 5898 label = "cdsp"; 5899 qcom,remote-pid = <5>; 5900 5901 fastrpc { 5902 compatible = "qcom,fastrpc"; 5903 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5904 label = "cdsp"; 5905 qcom,non-secure-domain; 5906 #address-cells = <1>; 5907 #size-cells = <0>; 5908 5909 compute-cb@1 { 5910 compatible = "qcom,fastrpc-compute-cb"; 5911 reg = <1>; 5912 iommus = <&apps_smmu 0x0c01 0x20>; 5913 dma-coherent; 5914 }; 5915 5916 compute-cb@2 { 5917 compatible = "qcom,fastrpc-compute-cb"; 5918 reg = <2>; 5919 iommus = <&apps_smmu 0x0c02 0x20>; 5920 dma-coherent; 5921 }; 5922 5923 compute-cb@3 { 5924 compatible = "qcom,fastrpc-compute-cb"; 5925 reg = <3>; 5926 iommus = <&apps_smmu 0x0c03 0x20>; 5927 dma-coherent; 5928 }; 5929 5930 compute-cb@4 { 5931 compatible = "qcom,fastrpc-compute-cb"; 5932 reg = <4>; 5933 iommus = <&apps_smmu 0x0c04 0x20>; 5934 dma-coherent; 5935 }; 5936 5937 compute-cb@5 { 5938 compatible = "qcom,fastrpc-compute-cb"; 5939 reg = <5>; 5940 iommus = <&apps_smmu 0x0c05 0x20>; 5941 dma-coherent; 5942 }; 5943 5944 compute-cb@6 { 5945 compatible = "qcom,fastrpc-compute-cb"; 5946 reg = <6>; 5947 iommus = <&apps_smmu 0x0c06 0x20>; 5948 dma-coherent; 5949 }; 5950 5951 compute-cb@7 { 5952 compatible = "qcom,fastrpc-compute-cb"; 5953 reg = <7>; 5954 iommus = <&apps_smmu 0x0c07 0x20>; 5955 dma-coherent; 5956 }; 5957 5958 compute-cb@8 { 5959 compatible = "qcom,fastrpc-compute-cb"; 5960 reg = <8>; 5961 iommus = <&apps_smmu 0x0c08 0x20>; 5962 dma-coherent; 5963 }; 5964 5965 /* note: compute-cb@9 is secure */ 5966 5967 compute-cb@10 { 5968 compatible = "qcom,fastrpc-compute-cb"; 5969 reg = <10>; 5970 iommus = <&apps_smmu 0x0c0c 0x20>; 5971 dma-coherent; 5972 }; 5973 5974 compute-cb@11 { 5975 compatible = "qcom,fastrpc-compute-cb"; 5976 reg = <11>; 5977 iommus = <&apps_smmu 0x0c0d 0x20>; 5978 dma-coherent; 5979 }; 5980 5981 compute-cb@12 { 5982 compatible = "qcom,fastrpc-compute-cb"; 5983 reg = <12>; 5984 iommus = <&apps_smmu 0x0c0e 0x20>; 5985 dma-coherent; 5986 }; 5987 5988 compute-cb@13 { 5989 compatible = "qcom,fastrpc-compute-cb"; 5990 reg = <13>; 5991 iommus = <&apps_smmu 0x0c0f 0x20>; 5992 dma-coherent; 5993 }; 5994 }; 5995 }; 5996 }; 5997 }; 5998 5999 timer { 6000 compatible = "arm,armv8-timer"; 6001 6002 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6003 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6004 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6005 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6006 }; 6007 6008 thermal-zones { 6009 aoss0-thermal { 6010 thermal-sensors = <&tsens0 0>; 6011 6012 trips { 6013 trip-point0 { 6014 temperature = <90000>; 6015 hysteresis = <2000>; 6016 type = "hot"; 6017 }; 6018 6019 aoss0-critical { 6020 temperature = <125000>; 6021 hysteresis = <0>; 6022 type = "critical"; 6023 }; 6024 }; 6025 }; 6026 6027 cpu0-0-top-thermal { 6028 polling-delay-passive = <250>; 6029 6030 thermal-sensors = <&tsens0 1>; 6031 6032 trips { 6033 trip-point0 { 6034 temperature = <90000>; 6035 hysteresis = <2000>; 6036 type = "passive"; 6037 }; 6038 6039 trip-point1 { 6040 temperature = <95000>; 6041 hysteresis = <2000>; 6042 type = "passive"; 6043 }; 6044 6045 cpu-critical { 6046 temperature = <110000>; 6047 hysteresis = <1000>; 6048 type = "critical"; 6049 }; 6050 }; 6051 }; 6052 6053 cpu0-0-btm-thermal { 6054 polling-delay-passive = <250>; 6055 6056 thermal-sensors = <&tsens0 2>; 6057 6058 trips { 6059 trip-point0 { 6060 temperature = <90000>; 6061 hysteresis = <2000>; 6062 type = "passive"; 6063 }; 6064 6065 trip-point1 { 6066 temperature = <95000>; 6067 hysteresis = <2000>; 6068 type = "passive"; 6069 }; 6070 6071 cpu-critical { 6072 temperature = <110000>; 6073 hysteresis = <1000>; 6074 type = "critical"; 6075 }; 6076 }; 6077 }; 6078 6079 cpu0-1-top-thermal { 6080 polling-delay-passive = <250>; 6081 6082 thermal-sensors = <&tsens0 3>; 6083 6084 trips { 6085 trip-point0 { 6086 temperature = <90000>; 6087 hysteresis = <2000>; 6088 type = "passive"; 6089 }; 6090 6091 trip-point1 { 6092 temperature = <95000>; 6093 hysteresis = <2000>; 6094 type = "passive"; 6095 }; 6096 6097 cpu-critical { 6098 temperature = <110000>; 6099 hysteresis = <1000>; 6100 type = "critical"; 6101 }; 6102 }; 6103 }; 6104 6105 cpu0-1-btm-thermal { 6106 polling-delay-passive = <250>; 6107 6108 thermal-sensors = <&tsens0 4>; 6109 6110 trips { 6111 trip-point0 { 6112 temperature = <90000>; 6113 hysteresis = <2000>; 6114 type = "passive"; 6115 }; 6116 6117 trip-point1 { 6118 temperature = <95000>; 6119 hysteresis = <2000>; 6120 type = "passive"; 6121 }; 6122 6123 cpu-critical { 6124 temperature = <110000>; 6125 hysteresis = <1000>; 6126 type = "critical"; 6127 }; 6128 }; 6129 }; 6130 6131 cpu0-2-top-thermal { 6132 polling-delay-passive = <250>; 6133 6134 thermal-sensors = <&tsens0 5>; 6135 6136 trips { 6137 trip-point0 { 6138 temperature = <90000>; 6139 hysteresis = <2000>; 6140 type = "passive"; 6141 }; 6142 6143 trip-point1 { 6144 temperature = <95000>; 6145 hysteresis = <2000>; 6146 type = "passive"; 6147 }; 6148 6149 cpu-critical { 6150 temperature = <110000>; 6151 hysteresis = <1000>; 6152 type = "critical"; 6153 }; 6154 }; 6155 }; 6156 6157 cpu0-2-btm-thermal { 6158 polling-delay-passive = <250>; 6159 6160 thermal-sensors = <&tsens0 6>; 6161 6162 trips { 6163 trip-point0 { 6164 temperature = <90000>; 6165 hysteresis = <2000>; 6166 type = "passive"; 6167 }; 6168 6169 trip-point1 { 6170 temperature = <95000>; 6171 hysteresis = <2000>; 6172 type = "passive"; 6173 }; 6174 6175 cpu-critical { 6176 temperature = <110000>; 6177 hysteresis = <1000>; 6178 type = "critical"; 6179 }; 6180 }; 6181 }; 6182 6183 cpu0-3-top-thermal { 6184 polling-delay-passive = <250>; 6185 6186 thermal-sensors = <&tsens0 7>; 6187 6188 trips { 6189 trip-point0 { 6190 temperature = <90000>; 6191 hysteresis = <2000>; 6192 type = "passive"; 6193 }; 6194 6195 trip-point1 { 6196 temperature = <95000>; 6197 hysteresis = <2000>; 6198 type = "passive"; 6199 }; 6200 6201 cpu-critical { 6202 temperature = <110000>; 6203 hysteresis = <1000>; 6204 type = "critical"; 6205 }; 6206 }; 6207 }; 6208 6209 cpu0-3-btm-thermal { 6210 polling-delay-passive = <250>; 6211 6212 thermal-sensors = <&tsens0 8>; 6213 6214 trips { 6215 trip-point0 { 6216 temperature = <90000>; 6217 hysteresis = <2000>; 6218 type = "passive"; 6219 }; 6220 6221 trip-point1 { 6222 temperature = <95000>; 6223 hysteresis = <2000>; 6224 type = "passive"; 6225 }; 6226 6227 cpu-critical { 6228 temperature = <110000>; 6229 hysteresis = <1000>; 6230 type = "critical"; 6231 }; 6232 }; 6233 }; 6234 6235 cpuss0-top-thermal { 6236 thermal-sensors = <&tsens0 9>; 6237 6238 trips { 6239 trip-point0 { 6240 temperature = <90000>; 6241 hysteresis = <2000>; 6242 type = "hot"; 6243 }; 6244 6245 cpuss2-critical { 6246 temperature = <125000>; 6247 hysteresis = <0>; 6248 type = "critical"; 6249 }; 6250 }; 6251 }; 6252 6253 cpuss0-btm-thermal { 6254 thermal-sensors = <&tsens0 10>; 6255 6256 trips { 6257 trip-point0 { 6258 temperature = <90000>; 6259 hysteresis = <2000>; 6260 type = "hot"; 6261 }; 6262 6263 cpuss2-critical { 6264 temperature = <125000>; 6265 hysteresis = <0>; 6266 type = "critical"; 6267 }; 6268 }; 6269 }; 6270 6271 mem-thermal { 6272 thermal-sensors = <&tsens0 11>; 6273 6274 trips { 6275 trip-point0 { 6276 temperature = <90000>; 6277 hysteresis = <2000>; 6278 type = "hot"; 6279 }; 6280 6281 mem-critical { 6282 temperature = <125000>; 6283 hysteresis = <0>; 6284 type = "critical"; 6285 }; 6286 }; 6287 }; 6288 6289 video-thermal { 6290 polling-delay-passive = <250>; 6291 6292 thermal-sensors = <&tsens0 12>; 6293 6294 trips { 6295 trip-point0 { 6296 temperature = <125000>; 6297 hysteresis = <1000>; 6298 type = "passive"; 6299 }; 6300 }; 6301 }; 6302 6303 aoss1-thermal { 6304 thermal-sensors = <&tsens1 0>; 6305 6306 trips { 6307 trip-point0 { 6308 temperature = <90000>; 6309 hysteresis = <2000>; 6310 type = "hot"; 6311 }; 6312 6313 aoss0-critical { 6314 temperature = <125000>; 6315 hysteresis = <0>; 6316 type = "critical"; 6317 }; 6318 }; 6319 }; 6320 6321 cpu1-0-top-thermal { 6322 polling-delay-passive = <250>; 6323 6324 thermal-sensors = <&tsens1 1>; 6325 6326 trips { 6327 trip-point0 { 6328 temperature = <90000>; 6329 hysteresis = <2000>; 6330 type = "passive"; 6331 }; 6332 6333 trip-point1 { 6334 temperature = <95000>; 6335 hysteresis = <2000>; 6336 type = "passive"; 6337 }; 6338 6339 cpu-critical { 6340 temperature = <110000>; 6341 hysteresis = <1000>; 6342 type = "critical"; 6343 }; 6344 }; 6345 }; 6346 6347 cpu1-0-btm-thermal { 6348 polling-delay-passive = <250>; 6349 6350 thermal-sensors = <&tsens1 2>; 6351 6352 trips { 6353 trip-point0 { 6354 temperature = <90000>; 6355 hysteresis = <2000>; 6356 type = "passive"; 6357 }; 6358 6359 trip-point1 { 6360 temperature = <95000>; 6361 hysteresis = <2000>; 6362 type = "passive"; 6363 }; 6364 6365 cpu-critical { 6366 temperature = <110000>; 6367 hysteresis = <1000>; 6368 type = "critical"; 6369 }; 6370 }; 6371 }; 6372 6373 cpu1-1-top-thermal { 6374 polling-delay-passive = <250>; 6375 6376 thermal-sensors = <&tsens1 3>; 6377 6378 trips { 6379 trip-point0 { 6380 temperature = <90000>; 6381 hysteresis = <2000>; 6382 type = "passive"; 6383 }; 6384 6385 trip-point1 { 6386 temperature = <95000>; 6387 hysteresis = <2000>; 6388 type = "passive"; 6389 }; 6390 6391 cpu-critical { 6392 temperature = <110000>; 6393 hysteresis = <1000>; 6394 type = "critical"; 6395 }; 6396 }; 6397 }; 6398 6399 cpu1-1-btm-thermal { 6400 polling-delay-passive = <250>; 6401 6402 thermal-sensors = <&tsens1 4>; 6403 6404 trips { 6405 trip-point0 { 6406 temperature = <90000>; 6407 hysteresis = <2000>; 6408 type = "passive"; 6409 }; 6410 6411 trip-point1 { 6412 temperature = <95000>; 6413 hysteresis = <2000>; 6414 type = "passive"; 6415 }; 6416 6417 cpu-critical { 6418 temperature = <110000>; 6419 hysteresis = <1000>; 6420 type = "critical"; 6421 }; 6422 }; 6423 }; 6424 6425 cpu1-2-top-thermal { 6426 polling-delay-passive = <250>; 6427 6428 thermal-sensors = <&tsens1 5>; 6429 6430 trips { 6431 trip-point0 { 6432 temperature = <90000>; 6433 hysteresis = <2000>; 6434 type = "passive"; 6435 }; 6436 6437 trip-point1 { 6438 temperature = <95000>; 6439 hysteresis = <2000>; 6440 type = "passive"; 6441 }; 6442 6443 cpu-critical { 6444 temperature = <110000>; 6445 hysteresis = <1000>; 6446 type = "critical"; 6447 }; 6448 }; 6449 }; 6450 6451 cpu1-2-btm-thermal { 6452 polling-delay-passive = <250>; 6453 6454 thermal-sensors = <&tsens1 6>; 6455 6456 trips { 6457 trip-point0 { 6458 temperature = <90000>; 6459 hysteresis = <2000>; 6460 type = "passive"; 6461 }; 6462 6463 trip-point1 { 6464 temperature = <95000>; 6465 hysteresis = <2000>; 6466 type = "passive"; 6467 }; 6468 6469 cpu-critical { 6470 temperature = <110000>; 6471 hysteresis = <1000>; 6472 type = "critical"; 6473 }; 6474 }; 6475 }; 6476 6477 cpu1-3-top-thermal { 6478 polling-delay-passive = <250>; 6479 6480 thermal-sensors = <&tsens1 7>; 6481 6482 trips { 6483 trip-point0 { 6484 temperature = <90000>; 6485 hysteresis = <2000>; 6486 type = "passive"; 6487 }; 6488 6489 trip-point1 { 6490 temperature = <95000>; 6491 hysteresis = <2000>; 6492 type = "passive"; 6493 }; 6494 6495 cpu-critical { 6496 temperature = <110000>; 6497 hysteresis = <1000>; 6498 type = "critical"; 6499 }; 6500 }; 6501 }; 6502 6503 cpu1-3-btm-thermal { 6504 polling-delay-passive = <250>; 6505 6506 thermal-sensors = <&tsens1 8>; 6507 6508 trips { 6509 trip-point0 { 6510 temperature = <90000>; 6511 hysteresis = <2000>; 6512 type = "passive"; 6513 }; 6514 6515 trip-point1 { 6516 temperature = <95000>; 6517 hysteresis = <2000>; 6518 type = "passive"; 6519 }; 6520 6521 cpu-critical { 6522 temperature = <110000>; 6523 hysteresis = <1000>; 6524 type = "critical"; 6525 }; 6526 }; 6527 }; 6528 6529 cpuss1-top-thermal { 6530 thermal-sensors = <&tsens1 9>; 6531 6532 trips { 6533 trip-point0 { 6534 temperature = <90000>; 6535 hysteresis = <2000>; 6536 type = "hot"; 6537 }; 6538 6539 cpuss2-critical { 6540 temperature = <125000>; 6541 hysteresis = <0>; 6542 type = "critical"; 6543 }; 6544 }; 6545 }; 6546 6547 cpuss1-btm-thermal { 6548 thermal-sensors = <&tsens1 10>; 6549 6550 trips { 6551 trip-point0 { 6552 temperature = <90000>; 6553 hysteresis = <2000>; 6554 type = "hot"; 6555 }; 6556 6557 cpuss2-critical { 6558 temperature = <125000>; 6559 hysteresis = <0>; 6560 type = "critical"; 6561 }; 6562 }; 6563 }; 6564 6565 aoss2-thermal { 6566 thermal-sensors = <&tsens2 0>; 6567 6568 trips { 6569 trip-point0 { 6570 temperature = <90000>; 6571 hysteresis = <2000>; 6572 type = "hot"; 6573 }; 6574 6575 aoss0-critical { 6576 temperature = <125000>; 6577 hysteresis = <0>; 6578 type = "critical"; 6579 }; 6580 }; 6581 }; 6582 6583 cpu2-0-top-thermal { 6584 polling-delay-passive = <250>; 6585 6586 thermal-sensors = <&tsens2 1>; 6587 6588 trips { 6589 trip-point0 { 6590 temperature = <90000>; 6591 hysteresis = <2000>; 6592 type = "passive"; 6593 }; 6594 6595 trip-point1 { 6596 temperature = <95000>; 6597 hysteresis = <2000>; 6598 type = "passive"; 6599 }; 6600 6601 cpu-critical { 6602 temperature = <110000>; 6603 hysteresis = <1000>; 6604 type = "critical"; 6605 }; 6606 }; 6607 }; 6608 6609 cpu2-0-btm-thermal { 6610 polling-delay-passive = <250>; 6611 6612 thermal-sensors = <&tsens2 2>; 6613 6614 trips { 6615 trip-point0 { 6616 temperature = <90000>; 6617 hysteresis = <2000>; 6618 type = "passive"; 6619 }; 6620 6621 trip-point1 { 6622 temperature = <95000>; 6623 hysteresis = <2000>; 6624 type = "passive"; 6625 }; 6626 6627 cpu-critical { 6628 temperature = <110000>; 6629 hysteresis = <1000>; 6630 type = "critical"; 6631 }; 6632 }; 6633 }; 6634 6635 cpu2-1-top-thermal { 6636 polling-delay-passive = <250>; 6637 6638 thermal-sensors = <&tsens2 3>; 6639 6640 trips { 6641 trip-point0 { 6642 temperature = <90000>; 6643 hysteresis = <2000>; 6644 type = "passive"; 6645 }; 6646 6647 trip-point1 { 6648 temperature = <95000>; 6649 hysteresis = <2000>; 6650 type = "passive"; 6651 }; 6652 6653 cpu-critical { 6654 temperature = <110000>; 6655 hysteresis = <1000>; 6656 type = "critical"; 6657 }; 6658 }; 6659 }; 6660 6661 cpu2-1-btm-thermal { 6662 polling-delay-passive = <250>; 6663 6664 thermal-sensors = <&tsens2 4>; 6665 6666 trips { 6667 trip-point0 { 6668 temperature = <90000>; 6669 hysteresis = <2000>; 6670 type = "passive"; 6671 }; 6672 6673 trip-point1 { 6674 temperature = <95000>; 6675 hysteresis = <2000>; 6676 type = "passive"; 6677 }; 6678 6679 cpu-critical { 6680 temperature = <110000>; 6681 hysteresis = <1000>; 6682 type = "critical"; 6683 }; 6684 }; 6685 }; 6686 6687 cpu2-2-top-thermal { 6688 polling-delay-passive = <250>; 6689 6690 thermal-sensors = <&tsens2 5>; 6691 6692 trips { 6693 trip-point0 { 6694 temperature = <90000>; 6695 hysteresis = <2000>; 6696 type = "passive"; 6697 }; 6698 6699 trip-point1 { 6700 temperature = <95000>; 6701 hysteresis = <2000>; 6702 type = "passive"; 6703 }; 6704 6705 cpu-critical { 6706 temperature = <110000>; 6707 hysteresis = <1000>; 6708 type = "critical"; 6709 }; 6710 }; 6711 }; 6712 6713 cpu2-2-btm-thermal { 6714 polling-delay-passive = <250>; 6715 6716 thermal-sensors = <&tsens2 6>; 6717 6718 trips { 6719 trip-point0 { 6720 temperature = <90000>; 6721 hysteresis = <2000>; 6722 type = "passive"; 6723 }; 6724 6725 trip-point1 { 6726 temperature = <95000>; 6727 hysteresis = <2000>; 6728 type = "passive"; 6729 }; 6730 6731 cpu-critical { 6732 temperature = <110000>; 6733 hysteresis = <1000>; 6734 type = "critical"; 6735 }; 6736 }; 6737 }; 6738 6739 cpu2-3-top-thermal { 6740 polling-delay-passive = <250>; 6741 6742 thermal-sensors = <&tsens2 7>; 6743 6744 trips { 6745 trip-point0 { 6746 temperature = <90000>; 6747 hysteresis = <2000>; 6748 type = "passive"; 6749 }; 6750 6751 trip-point1 { 6752 temperature = <95000>; 6753 hysteresis = <2000>; 6754 type = "passive"; 6755 }; 6756 6757 cpu-critical { 6758 temperature = <110000>; 6759 hysteresis = <1000>; 6760 type = "critical"; 6761 }; 6762 }; 6763 }; 6764 6765 cpu2-3-btm-thermal { 6766 polling-delay-passive = <250>; 6767 6768 thermal-sensors = <&tsens2 8>; 6769 6770 trips { 6771 trip-point0 { 6772 temperature = <90000>; 6773 hysteresis = <2000>; 6774 type = "passive"; 6775 }; 6776 6777 trip-point1 { 6778 temperature = <95000>; 6779 hysteresis = <2000>; 6780 type = "passive"; 6781 }; 6782 6783 cpu-critical { 6784 temperature = <110000>; 6785 hysteresis = <1000>; 6786 type = "critical"; 6787 }; 6788 }; 6789 }; 6790 6791 cpuss2-top-thermal { 6792 thermal-sensors = <&tsens2 9>; 6793 6794 trips { 6795 trip-point0 { 6796 temperature = <90000>; 6797 hysteresis = <2000>; 6798 type = "hot"; 6799 }; 6800 6801 cpuss2-critical { 6802 temperature = <125000>; 6803 hysteresis = <0>; 6804 type = "critical"; 6805 }; 6806 }; 6807 }; 6808 6809 cpuss2-btm-thermal { 6810 thermal-sensors = <&tsens2 10>; 6811 6812 trips { 6813 trip-point0 { 6814 temperature = <90000>; 6815 hysteresis = <2000>; 6816 type = "hot"; 6817 }; 6818 6819 cpuss2-critical { 6820 temperature = <125000>; 6821 hysteresis = <0>; 6822 type = "critical"; 6823 }; 6824 }; 6825 }; 6826 6827 aoss3-thermal { 6828 thermal-sensors = <&tsens3 0>; 6829 6830 trips { 6831 trip-point0 { 6832 temperature = <90000>; 6833 hysteresis = <2000>; 6834 type = "hot"; 6835 }; 6836 6837 aoss0-critical { 6838 temperature = <125000>; 6839 hysteresis = <0>; 6840 type = "critical"; 6841 }; 6842 }; 6843 }; 6844 6845 nsp0-thermal { 6846 thermal-sensors = <&tsens3 1>; 6847 6848 trips { 6849 trip-point0 { 6850 temperature = <90000>; 6851 hysteresis = <2000>; 6852 type = "hot"; 6853 }; 6854 6855 nsp0-critical { 6856 temperature = <125000>; 6857 hysteresis = <0>; 6858 type = "critical"; 6859 }; 6860 }; 6861 }; 6862 6863 nsp1-thermal { 6864 thermal-sensors = <&tsens3 2>; 6865 6866 trips { 6867 trip-point0 { 6868 temperature = <90000>; 6869 hysteresis = <2000>; 6870 type = "hot"; 6871 }; 6872 6873 nsp1-critical { 6874 temperature = <125000>; 6875 hysteresis = <0>; 6876 type = "critical"; 6877 }; 6878 }; 6879 }; 6880 6881 nsp2-thermal { 6882 thermal-sensors = <&tsens3 3>; 6883 6884 trips { 6885 trip-point0 { 6886 temperature = <90000>; 6887 hysteresis = <2000>; 6888 type = "hot"; 6889 }; 6890 6891 nsp2-critical { 6892 temperature = <125000>; 6893 hysteresis = <0>; 6894 type = "critical"; 6895 }; 6896 }; 6897 }; 6898 6899 nsp3-thermal { 6900 thermal-sensors = <&tsens3 4>; 6901 6902 trips { 6903 trip-point0 { 6904 temperature = <90000>; 6905 hysteresis = <2000>; 6906 type = "hot"; 6907 }; 6908 6909 nsp3-critical { 6910 temperature = <125000>; 6911 hysteresis = <0>; 6912 type = "critical"; 6913 }; 6914 }; 6915 }; 6916 6917 gpuss-0-thermal { 6918 polling-delay-passive = <10>; 6919 6920 thermal-sensors = <&tsens3 5>; 6921 6922 trips { 6923 trip-point0 { 6924 temperature = <85000>; 6925 hysteresis = <1000>; 6926 type = "passive"; 6927 }; 6928 6929 trip-point1 { 6930 temperature = <90000>; 6931 hysteresis = <1000>; 6932 type = "hot"; 6933 }; 6934 6935 trip-point2 { 6936 temperature = <125000>; 6937 hysteresis = <1000>; 6938 type = "critical"; 6939 }; 6940 }; 6941 }; 6942 6943 gpuss-1-thermal { 6944 polling-delay-passive = <10>; 6945 6946 thermal-sensors = <&tsens3 6>; 6947 6948 trips { 6949 trip-point0 { 6950 temperature = <85000>; 6951 hysteresis = <1000>; 6952 type = "passive"; 6953 }; 6954 6955 trip-point1 { 6956 temperature = <90000>; 6957 hysteresis = <1000>; 6958 type = "hot"; 6959 }; 6960 6961 trip-point2 { 6962 temperature = <125000>; 6963 hysteresis = <1000>; 6964 type = "critical"; 6965 }; 6966 }; 6967 }; 6968 6969 gpuss-2-thermal { 6970 polling-delay-passive = <10>; 6971 6972 thermal-sensors = <&tsens3 7>; 6973 6974 trips { 6975 trip-point0 { 6976 temperature = <85000>; 6977 hysteresis = <1000>; 6978 type = "passive"; 6979 }; 6980 6981 trip-point1 { 6982 temperature = <90000>; 6983 hysteresis = <1000>; 6984 type = "hot"; 6985 }; 6986 6987 trip-point2 { 6988 temperature = <125000>; 6989 hysteresis = <1000>; 6990 type = "critical"; 6991 }; 6992 }; 6993 }; 6994 6995 gpuss-3-thermal { 6996 polling-delay-passive = <10>; 6997 6998 thermal-sensors = <&tsens3 8>; 6999 7000 trips { 7001 trip-point0 { 7002 temperature = <85000>; 7003 hysteresis = <1000>; 7004 type = "passive"; 7005 }; 7006 7007 trip-point1 { 7008 temperature = <90000>; 7009 hysteresis = <1000>; 7010 type = "hot"; 7011 }; 7012 7013 trip-point2 { 7014 temperature = <125000>; 7015 hysteresis = <1000>; 7016 type = "critical"; 7017 }; 7018 }; 7019 }; 7020 7021 gpuss-4-thermal { 7022 polling-delay-passive = <10>; 7023 7024 thermal-sensors = <&tsens3 9>; 7025 7026 trips { 7027 trip-point0 { 7028 temperature = <85000>; 7029 hysteresis = <1000>; 7030 type = "passive"; 7031 }; 7032 7033 trip-point1 { 7034 temperature = <90000>; 7035 hysteresis = <1000>; 7036 type = "hot"; 7037 }; 7038 7039 trip-point2 { 7040 temperature = <125000>; 7041 hysteresis = <1000>; 7042 type = "critical"; 7043 }; 7044 }; 7045 }; 7046 7047 gpuss-5-thermal { 7048 polling-delay-passive = <10>; 7049 7050 thermal-sensors = <&tsens3 10>; 7051 7052 trips { 7053 trip-point0 { 7054 temperature = <85000>; 7055 hysteresis = <1000>; 7056 type = "passive"; 7057 }; 7058 7059 trip-point1 { 7060 temperature = <90000>; 7061 hysteresis = <1000>; 7062 type = "hot"; 7063 }; 7064 7065 trip-point2 { 7066 temperature = <125000>; 7067 hysteresis = <1000>; 7068 type = "critical"; 7069 }; 7070 }; 7071 }; 7072 7073 gpuss-6-thermal { 7074 polling-delay-passive = <10>; 7075 7076 thermal-sensors = <&tsens3 11>; 7077 7078 trips { 7079 trip-point0 { 7080 temperature = <85000>; 7081 hysteresis = <1000>; 7082 type = "passive"; 7083 }; 7084 7085 trip-point1 { 7086 temperature = <90000>; 7087 hysteresis = <1000>; 7088 type = "hot"; 7089 }; 7090 7091 trip-point2 { 7092 temperature = <125000>; 7093 hysteresis = <1000>; 7094 type = "critical"; 7095 }; 7096 }; 7097 }; 7098 7099 gpuss-7-thermal { 7100 polling-delay-passive = <10>; 7101 7102 thermal-sensors = <&tsens3 12>; 7103 7104 trips { 7105 trip-point0 { 7106 temperature = <85000>; 7107 hysteresis = <1000>; 7108 type = "passive"; 7109 }; 7110 7111 trip-point1 { 7112 temperature = <90000>; 7113 hysteresis = <1000>; 7114 type = "hot"; 7115 }; 7116 7117 trip-point2 { 7118 temperature = <125000>; 7119 hysteresis = <1000>; 7120 type = "critical"; 7121 }; 7122 }; 7123 }; 7124 7125 camera0-thermal { 7126 thermal-sensors = <&tsens3 13>; 7127 7128 trips { 7129 trip-point0 { 7130 temperature = <90000>; 7131 hysteresis = <2000>; 7132 type = "hot"; 7133 }; 7134 7135 camera0-critical { 7136 temperature = <115000>; 7137 hysteresis = <0>; 7138 type = "critical"; 7139 }; 7140 }; 7141 }; 7142 7143 camera1-thermal { 7144 thermal-sensors = <&tsens3 14>; 7145 7146 trips { 7147 trip-point0 { 7148 temperature = <90000>; 7149 hysteresis = <2000>; 7150 type = "hot"; 7151 }; 7152 7153 camera0-critical { 7154 temperature = <115000>; 7155 hysteresis = <0>; 7156 type = "critical"; 7157 }; 7158 }; 7159 }; 7160 }; 7161}; 7162