xref: /linux/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e)
1*0d72ccaaSDale Whinham// SPDX-License-Identifier: BSD-3-Clause
2*0d72ccaaSDale Whinham/*
3*0d72ccaaSDale Whinham * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
4*0d72ccaaSDale Whinham * Copyright (c) 2025 Dale Whinham <daleyo@gmail.com>
5*0d72ccaaSDale Whinham */
6*0d72ccaaSDale Whinham
7*0d72ccaaSDale Whinham#include <dt-bindings/gpio/gpio.h>
8*0d72ccaaSDale Whinham#include <dt-bindings/input/gpio-keys.h>
9*0d72ccaaSDale Whinham#include <dt-bindings/input/input.h>
10*0d72ccaaSDale Whinham#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11*0d72ccaaSDale Whinham
12*0d72ccaaSDale Whinham#include "hamoa-pmics.dtsi"
13*0d72ccaaSDale Whinham
14*0d72ccaaSDale Whinham/ {
15*0d72ccaaSDale Whinham	aliases {
16*0d72ccaaSDale Whinham		serial0 = &uart2;
17*0d72ccaaSDale Whinham		serial1 = &uart14;
18*0d72ccaaSDale Whinham	};
19*0d72ccaaSDale Whinham
20*0d72ccaaSDale Whinham	gpio-keys {
21*0d72ccaaSDale Whinham		compatible = "gpio-keys";
22*0d72ccaaSDale Whinham
23*0d72ccaaSDale Whinham		pinctrl-0 = <&hall_int_n_default>;
24*0d72ccaaSDale Whinham		pinctrl-names = "default";
25*0d72ccaaSDale Whinham
26*0d72ccaaSDale Whinham		switch-lid {
27*0d72ccaaSDale Whinham			gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
28*0d72ccaaSDale Whinham			linux,input-type = <EV_SW>;
29*0d72ccaaSDale Whinham			linux,code = <SW_LID>;
30*0d72ccaaSDale Whinham			wakeup-source;
31*0d72ccaaSDale Whinham			wakeup-event-action = <EV_ACT_DEASSERTED>;
32*0d72ccaaSDale Whinham		};
33*0d72ccaaSDale Whinham	};
34*0d72ccaaSDale Whinham
35*0d72ccaaSDale Whinham	pmic-glink {
36*0d72ccaaSDale Whinham		compatible = "qcom,x1e80100-pmic-glink",
37*0d72ccaaSDale Whinham			     "qcom,sm8550-pmic-glink",
38*0d72ccaaSDale Whinham			     "qcom,pmic-glink";
39*0d72ccaaSDale Whinham		#address-cells = <1>;
40*0d72ccaaSDale Whinham		#size-cells = <0>;
41*0d72ccaaSDale Whinham		orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>,
42*0d72ccaaSDale Whinham				    <&tlmm 123 GPIO_ACTIVE_HIGH>;
43*0d72ccaaSDale Whinham
44*0d72ccaaSDale Whinham		/* Left-side bottom port */
45*0d72ccaaSDale Whinham		connector@0 {
46*0d72ccaaSDale Whinham			compatible = "usb-c-connector";
47*0d72ccaaSDale Whinham			reg = <0>;
48*0d72ccaaSDale Whinham			power-role = "dual";
49*0d72ccaaSDale Whinham			data-role = "dual";
50*0d72ccaaSDale Whinham
51*0d72ccaaSDale Whinham			ports {
52*0d72ccaaSDale Whinham				#address-cells = <1>;
53*0d72ccaaSDale Whinham				#size-cells = <0>;
54*0d72ccaaSDale Whinham
55*0d72ccaaSDale Whinham				port@0 {
56*0d72ccaaSDale Whinham					reg = <0>;
57*0d72ccaaSDale Whinham
58*0d72ccaaSDale Whinham					pmic_glink_ss0_hs_in: endpoint {
59*0d72ccaaSDale Whinham						remote-endpoint = <&usb_1_ss0_dwc3_hs>;
60*0d72ccaaSDale Whinham					};
61*0d72ccaaSDale Whinham				};
62*0d72ccaaSDale Whinham
63*0d72ccaaSDale Whinham				port@1 {
64*0d72ccaaSDale Whinham					reg = <1>;
65*0d72ccaaSDale Whinham
66*0d72ccaaSDale Whinham					pmic_glink_ss0_ss_in: endpoint {
67*0d72ccaaSDale Whinham						remote-endpoint = <&retimer_ss0_ss_out>;
68*0d72ccaaSDale Whinham					};
69*0d72ccaaSDale Whinham				};
70*0d72ccaaSDale Whinham
71*0d72ccaaSDale Whinham				port@2 {
72*0d72ccaaSDale Whinham					reg = <2>;
73*0d72ccaaSDale Whinham
74*0d72ccaaSDale Whinham					pmic_glink_ss0_con_sbu_in: endpoint {
75*0d72ccaaSDale Whinham						remote-endpoint = <&retimer_ss0_con_sbu_out>;
76*0d72ccaaSDale Whinham					};
77*0d72ccaaSDale Whinham				};
78*0d72ccaaSDale Whinham			};
79*0d72ccaaSDale Whinham		};
80*0d72ccaaSDale Whinham
81*0d72ccaaSDale Whinham		/* Left-side top port */
82*0d72ccaaSDale Whinham		connector@1 {
83*0d72ccaaSDale Whinham			compatible = "usb-c-connector";
84*0d72ccaaSDale Whinham			reg = <1>;
85*0d72ccaaSDale Whinham			power-role = "dual";
86*0d72ccaaSDale Whinham			data-role = "dual";
87*0d72ccaaSDale Whinham
88*0d72ccaaSDale Whinham			ports {
89*0d72ccaaSDale Whinham				#address-cells = <1>;
90*0d72ccaaSDale Whinham				#size-cells = <0>;
91*0d72ccaaSDale Whinham
92*0d72ccaaSDale Whinham				port@0 {
93*0d72ccaaSDale Whinham					reg = <0>;
94*0d72ccaaSDale Whinham
95*0d72ccaaSDale Whinham					pmic_glink_ss1_hs_in: endpoint {
96*0d72ccaaSDale Whinham						remote-endpoint = <&usb_1_ss1_dwc3_hs>;
97*0d72ccaaSDale Whinham					};
98*0d72ccaaSDale Whinham				};
99*0d72ccaaSDale Whinham
100*0d72ccaaSDale Whinham				port@1 {
101*0d72ccaaSDale Whinham					reg = <1>;
102*0d72ccaaSDale Whinham
103*0d72ccaaSDale Whinham					pmic_glink_ss1_ss_in: endpoint {
104*0d72ccaaSDale Whinham						remote-endpoint = <&retimer_ss1_ss_out>;
105*0d72ccaaSDale Whinham					};
106*0d72ccaaSDale Whinham				};
107*0d72ccaaSDale Whinham
108*0d72ccaaSDale Whinham				port@2 {
109*0d72ccaaSDale Whinham					reg = <2>;
110*0d72ccaaSDale Whinham
111*0d72ccaaSDale Whinham					pmic_glink_ss1_con_sbu_in: endpoint {
112*0d72ccaaSDale Whinham						remote-endpoint = <&retimer_ss1_con_sbu_out>;
113*0d72ccaaSDale Whinham					};
114*0d72ccaaSDale Whinham				};
115*0d72ccaaSDale Whinham			};
116*0d72ccaaSDale Whinham		};
117*0d72ccaaSDale Whinham	};
118*0d72ccaaSDale Whinham
119*0d72ccaaSDale Whinham	reserved-memory {
120*0d72ccaaSDale Whinham		linux,cma {
121*0d72ccaaSDale Whinham			compatible = "shared-dma-pool";
122*0d72ccaaSDale Whinham			size = <0x0 0x8000000>;
123*0d72ccaaSDale Whinham			reusable;
124*0d72ccaaSDale Whinham			linux,cma-default;
125*0d72ccaaSDale Whinham		};
126*0d72ccaaSDale Whinham	};
127*0d72ccaaSDale Whinham
128*0d72ccaaSDale Whinham	vreg_edp_3p3: regulator-edp-3p3 {
129*0d72ccaaSDale Whinham		compatible = "regulator-fixed";
130*0d72ccaaSDale Whinham
131*0d72ccaaSDale Whinham		regulator-name = "VREG_EDP_3P3";
132*0d72ccaaSDale Whinham		regulator-min-microvolt = <3300000>;
133*0d72ccaaSDale Whinham		regulator-max-microvolt = <3300000>;
134*0d72ccaaSDale Whinham
135*0d72ccaaSDale Whinham		gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
136*0d72ccaaSDale Whinham		enable-active-high;
137*0d72ccaaSDale Whinham
138*0d72ccaaSDale Whinham		pinctrl-0 = <&edp_reg_en>;
139*0d72ccaaSDale Whinham		pinctrl-names = "default";
140*0d72ccaaSDale Whinham
141*0d72ccaaSDale Whinham		regulator-boot-on;
142*0d72ccaaSDale Whinham	};
143*0d72ccaaSDale Whinham
144*0d72ccaaSDale Whinham	vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
145*0d72ccaaSDale Whinham		compatible = "regulator-fixed";
146*0d72ccaaSDale Whinham
147*0d72ccaaSDale Whinham		regulator-name = "VREG_RTMR0_1P15";
148*0d72ccaaSDale Whinham
149*0d72ccaaSDale Whinham		regulator-min-microvolt = <1150000>;
150*0d72ccaaSDale Whinham		regulator-max-microvolt = <1150000>;
151*0d72ccaaSDale Whinham
152*0d72ccaaSDale Whinham		gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
153*0d72ccaaSDale Whinham		enable-active-high;
154*0d72ccaaSDale Whinham
155*0d72ccaaSDale Whinham		pinctrl-0 = <&rtmr0_1p15_reg_en>;
156*0d72ccaaSDale Whinham		pinctrl-names = "default";
157*0d72ccaaSDale Whinham
158*0d72ccaaSDale Whinham		regulator-boot-on;
159*0d72ccaaSDale Whinham	};
160*0d72ccaaSDale Whinham
161*0d72ccaaSDale Whinham	vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
162*0d72ccaaSDale Whinham		compatible = "regulator-fixed";
163*0d72ccaaSDale Whinham
164*0d72ccaaSDale Whinham		regulator-name = "VREG_RTMR0_1P8";
165*0d72ccaaSDale Whinham
166*0d72ccaaSDale Whinham		regulator-min-microvolt = <1800000>;
167*0d72ccaaSDale Whinham		regulator-max-microvolt = <1800000>;
168*0d72ccaaSDale Whinham
169*0d72ccaaSDale Whinham		gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
170*0d72ccaaSDale Whinham		enable-active-high;
171*0d72ccaaSDale Whinham
172*0d72ccaaSDale Whinham		pinctrl-0 = <&rtmr0_1p8_reg_en>;
173*0d72ccaaSDale Whinham		pinctrl-names = "default";
174*0d72ccaaSDale Whinham
175*0d72ccaaSDale Whinham		regulator-boot-on;
176*0d72ccaaSDale Whinham	};
177*0d72ccaaSDale Whinham
178*0d72ccaaSDale Whinham	vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
179*0d72ccaaSDale Whinham		compatible = "regulator-fixed";
180*0d72ccaaSDale Whinham
181*0d72ccaaSDale Whinham		regulator-name = "VREG_RTMR0_3P3";
182*0d72ccaaSDale Whinham
183*0d72ccaaSDale Whinham		regulator-min-microvolt = <3300000>;
184*0d72ccaaSDale Whinham		regulator-max-microvolt = <3300000>;
185*0d72ccaaSDale Whinham
186*0d72ccaaSDale Whinham		gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
187*0d72ccaaSDale Whinham		enable-active-high;
188*0d72ccaaSDale Whinham
189*0d72ccaaSDale Whinham		pinctrl-0 = <&rtmr0_3p3_reg_en>;
190*0d72ccaaSDale Whinham		pinctrl-names = "default";
191*0d72ccaaSDale Whinham
192*0d72ccaaSDale Whinham		regulator-boot-on;
193*0d72ccaaSDale Whinham	};
194*0d72ccaaSDale Whinham
195*0d72ccaaSDale Whinham	vreg_rtmr1_1p15: regulator-rtmr1-1p15 {
196*0d72ccaaSDale Whinham		compatible = "regulator-fixed";
197*0d72ccaaSDale Whinham
198*0d72ccaaSDale Whinham		regulator-name = "VREG_RTMR1_1P15";
199*0d72ccaaSDale Whinham
200*0d72ccaaSDale Whinham		regulator-min-microvolt = <1150000>;
201*0d72ccaaSDale Whinham		regulator-max-microvolt = <1150000>;
202*0d72ccaaSDale Whinham
203*0d72ccaaSDale Whinham		gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>;
204*0d72ccaaSDale Whinham		enable-active-high;
205*0d72ccaaSDale Whinham
206*0d72ccaaSDale Whinham		pinctrl-0 = <&rtmr1_1p15_reg_en>;
207*0d72ccaaSDale Whinham		pinctrl-names = "default";
208*0d72ccaaSDale Whinham
209*0d72ccaaSDale Whinham		regulator-boot-on;
210*0d72ccaaSDale Whinham	};
211*0d72ccaaSDale Whinham
212*0d72ccaaSDale Whinham	vreg_rtmr1_1p8: regulator-rtmr1-1p8 {
213*0d72ccaaSDale Whinham		compatible = "regulator-fixed";
214*0d72ccaaSDale Whinham
215*0d72ccaaSDale Whinham		regulator-name = "VREG_RTMR1_1P8";
216*0d72ccaaSDale Whinham
217*0d72ccaaSDale Whinham		regulator-min-microvolt = <1800000>;
218*0d72ccaaSDale Whinham		regulator-max-microvolt = <1800000>;
219*0d72ccaaSDale Whinham
220*0d72ccaaSDale Whinham		gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>;
221*0d72ccaaSDale Whinham		enable-active-high;
222*0d72ccaaSDale Whinham
223*0d72ccaaSDale Whinham		pinctrl-0 = <&rtmr1_1p8_reg_en>;
224*0d72ccaaSDale Whinham		pinctrl-names = "default";
225*0d72ccaaSDale Whinham
226*0d72ccaaSDale Whinham		regulator-boot-on;
227*0d72ccaaSDale Whinham	};
228*0d72ccaaSDale Whinham
229*0d72ccaaSDale Whinham	vreg_rtmr1_3p3: regulator-rtmr1-3p3 {
230*0d72ccaaSDale Whinham		compatible = "regulator-fixed";
231*0d72ccaaSDale Whinham
232*0d72ccaaSDale Whinham		regulator-name = "VREG_RTMR1_3P3";
233*0d72ccaaSDale Whinham
234*0d72ccaaSDale Whinham		regulator-min-microvolt = <3300000>;
235*0d72ccaaSDale Whinham		regulator-max-microvolt = <3300000>;
236*0d72ccaaSDale Whinham
237*0d72ccaaSDale Whinham		gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>;
238*0d72ccaaSDale Whinham		enable-active-high;
239*0d72ccaaSDale Whinham
240*0d72ccaaSDale Whinham		pinctrl-0 = <&rtmr1_3p3_reg_en>;
241*0d72ccaaSDale Whinham		pinctrl-names = "default";
242*0d72ccaaSDale Whinham
243*0d72ccaaSDale Whinham		regulator-boot-on;
244*0d72ccaaSDale Whinham	};
245*0d72ccaaSDale Whinham
246*0d72ccaaSDale Whinham	vreg_nvme: regulator-nvme {
247*0d72ccaaSDale Whinham		compatible = "regulator-fixed";
248*0d72ccaaSDale Whinham
249*0d72ccaaSDale Whinham		regulator-name = "VREG_NVME_3P3";
250*0d72ccaaSDale Whinham		regulator-min-microvolt = <3300000>;
251*0d72ccaaSDale Whinham		regulator-max-microvolt = <3300000>;
252*0d72ccaaSDale Whinham
253*0d72ccaaSDale Whinham		gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>;
254*0d72ccaaSDale Whinham		enable-active-high;
255*0d72ccaaSDale Whinham
256*0d72ccaaSDale Whinham		pinctrl-0 = <&nvme_reg_en>;
257*0d72ccaaSDale Whinham		pinctrl-names = "default";
258*0d72ccaaSDale Whinham
259*0d72ccaaSDale Whinham		regulator-boot-on;
260*0d72ccaaSDale Whinham	};
261*0d72ccaaSDale Whinham
262*0d72ccaaSDale Whinham	vph_pwr: regulator-vph-pwr {
263*0d72ccaaSDale Whinham		compatible = "regulator-fixed";
264*0d72ccaaSDale Whinham
265*0d72ccaaSDale Whinham		regulator-name = "vph_pwr";
266*0d72ccaaSDale Whinham		regulator-min-microvolt = <3700000>;
267*0d72ccaaSDale Whinham		regulator-max-microvolt = <3700000>;
268*0d72ccaaSDale Whinham
269*0d72ccaaSDale Whinham		regulator-always-on;
270*0d72ccaaSDale Whinham		regulator-boot-on;
271*0d72ccaaSDale Whinham	};
272*0d72ccaaSDale Whinham
273*0d72ccaaSDale Whinham	vreg_wcn_3p3: regulator-wcn-3p3 {
274*0d72ccaaSDale Whinham		compatible = "regulator-fixed";
275*0d72ccaaSDale Whinham
276*0d72ccaaSDale Whinham		regulator-name = "VREG_WCN_3P3";
277*0d72ccaaSDale Whinham		regulator-min-microvolt = <3300000>;
278*0d72ccaaSDale Whinham		regulator-max-microvolt = <3300000>;
279*0d72ccaaSDale Whinham
280*0d72ccaaSDale Whinham		gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>;
281*0d72ccaaSDale Whinham		enable-active-high;
282*0d72ccaaSDale Whinham
283*0d72ccaaSDale Whinham		pinctrl-0 = <&wcn_sw_en>;
284*0d72ccaaSDale Whinham		pinctrl-names = "default";
285*0d72ccaaSDale Whinham
286*0d72ccaaSDale Whinham		regulator-boot-on;
287*0d72ccaaSDale Whinham	};
288*0d72ccaaSDale Whinham
289*0d72ccaaSDale Whinham	vreg_wcn_0p95: regulator-wcn-0p95 {
290*0d72ccaaSDale Whinham		compatible = "regulator-fixed";
291*0d72ccaaSDale Whinham
292*0d72ccaaSDale Whinham		regulator-name = "VREG_WCN_0P95";
293*0d72ccaaSDale Whinham		regulator-min-microvolt = <950000>;
294*0d72ccaaSDale Whinham		regulator-max-microvolt = <950000>;
295*0d72ccaaSDale Whinham
296*0d72ccaaSDale Whinham		vin-supply = <&vreg_wcn_3p3>;
297*0d72ccaaSDale Whinham	};
298*0d72ccaaSDale Whinham
299*0d72ccaaSDale Whinham	vreg_wcn_1p9: regulator-wcn-1p9 {
300*0d72ccaaSDale Whinham		compatible = "regulator-fixed";
301*0d72ccaaSDale Whinham
302*0d72ccaaSDale Whinham		regulator-name = "VREG_WCN_1P9";
303*0d72ccaaSDale Whinham		regulator-min-microvolt = <1900000>;
304*0d72ccaaSDale Whinham		regulator-max-microvolt = <1900000>;
305*0d72ccaaSDale Whinham
306*0d72ccaaSDale Whinham		vin-supply = <&vreg_wcn_3p3>;
307*0d72ccaaSDale Whinham	};
308*0d72ccaaSDale Whinham
309*0d72ccaaSDale Whinham	sound {
310*0d72ccaaSDale Whinham		compatible = "qcom,x1e80100-sndcard";
311*0d72ccaaSDale Whinham		model = "X1E80100-Microsoft-Surface-Pro-11";
312*0d72ccaaSDale Whinham		audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT",
313*0d72ccaaSDale Whinham				"SpkrRight IN", "WSA WSA_SPK2 OUT",
314*0d72ccaaSDale Whinham				"VA DMIC0", "vdd-micb",
315*0d72ccaaSDale Whinham				"VA DMIC1", "vdd-micb";
316*0d72ccaaSDale Whinham
317*0d72ccaaSDale Whinham		wsa-dai-link {
318*0d72ccaaSDale Whinham			link-name = "WSA Playback";
319*0d72ccaaSDale Whinham
320*0d72ccaaSDale Whinham			codec {
321*0d72ccaaSDale Whinham				sound-dai = <&left_spkr>, <&right_spkr>,
322*0d72ccaaSDale Whinham					    <&swr0 0>, <&lpass_wsamacro 0>;
323*0d72ccaaSDale Whinham			};
324*0d72ccaaSDale Whinham
325*0d72ccaaSDale Whinham			cpu {
326*0d72ccaaSDale Whinham				sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
327*0d72ccaaSDale Whinham			};
328*0d72ccaaSDale Whinham
329*0d72ccaaSDale Whinham			platform {
330*0d72ccaaSDale Whinham				sound-dai = <&q6apm>;
331*0d72ccaaSDale Whinham			};
332*0d72ccaaSDale Whinham		};
333*0d72ccaaSDale Whinham
334*0d72ccaaSDale Whinham		va-dai-link {
335*0d72ccaaSDale Whinham			link-name = "VA Capture";
336*0d72ccaaSDale Whinham
337*0d72ccaaSDale Whinham			codec {
338*0d72ccaaSDale Whinham				sound-dai = <&lpass_vamacro 0>;
339*0d72ccaaSDale Whinham			};
340*0d72ccaaSDale Whinham
341*0d72ccaaSDale Whinham			cpu {
342*0d72ccaaSDale Whinham				sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
343*0d72ccaaSDale Whinham			};
344*0d72ccaaSDale Whinham
345*0d72ccaaSDale Whinham			platform {
346*0d72ccaaSDale Whinham				sound-dai = <&q6apm>;
347*0d72ccaaSDale Whinham			};
348*0d72ccaaSDale Whinham		};
349*0d72ccaaSDale Whinham	};
350*0d72ccaaSDale Whinham
351*0d72ccaaSDale Whinham	wcn7850-pmu {
352*0d72ccaaSDale Whinham		compatible = "qcom,wcn7850-pmu";
353*0d72ccaaSDale Whinham
354*0d72ccaaSDale Whinham		vdd-supply = <&vreg_wcn_0p95>;
355*0d72ccaaSDale Whinham		vddio-supply = <&vreg_l15b_1p8>;
356*0d72ccaaSDale Whinham		vddaon-supply = <&vreg_wcn_0p95>;
357*0d72ccaaSDale Whinham		vdddig-supply = <&vreg_wcn_0p95>;
358*0d72ccaaSDale Whinham		vddrfa1p2-supply = <&vreg_wcn_1p9>;
359*0d72ccaaSDale Whinham		vddrfa1p8-supply = <&vreg_wcn_1p9>;
360*0d72ccaaSDale Whinham
361*0d72ccaaSDale Whinham		wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;
362*0d72ccaaSDale Whinham		bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
363*0d72ccaaSDale Whinham
364*0d72ccaaSDale Whinham		pinctrl-0 = <&wcn_wlan_bt_en>;
365*0d72ccaaSDale Whinham		pinctrl-names = "default";
366*0d72ccaaSDale Whinham
367*0d72ccaaSDale Whinham		regulators {
368*0d72ccaaSDale Whinham			vreg_pmu_rfa_cmn: ldo0 {
369*0d72ccaaSDale Whinham				regulator-name = "vreg_pmu_rfa_cmn";
370*0d72ccaaSDale Whinham			};
371*0d72ccaaSDale Whinham
372*0d72ccaaSDale Whinham			vreg_pmu_aon_0p59: ldo1 {
373*0d72ccaaSDale Whinham				regulator-name = "vreg_pmu_aon_0p59";
374*0d72ccaaSDale Whinham			};
375*0d72ccaaSDale Whinham
376*0d72ccaaSDale Whinham			vreg_pmu_wlcx_0p8: ldo2 {
377*0d72ccaaSDale Whinham				regulator-name = "vreg_pmu_wlcx_0p8";
378*0d72ccaaSDale Whinham			};
379*0d72ccaaSDale Whinham
380*0d72ccaaSDale Whinham			vreg_pmu_wlmx_0p85: ldo3 {
381*0d72ccaaSDale Whinham				regulator-name = "vreg_pmu_wlmx_0p85";
382*0d72ccaaSDale Whinham			};
383*0d72ccaaSDale Whinham
384*0d72ccaaSDale Whinham			vreg_pmu_btcmx_0p85: ldo4 {
385*0d72ccaaSDale Whinham				regulator-name = "vreg_pmu_btcmx_0p85";
386*0d72ccaaSDale Whinham			};
387*0d72ccaaSDale Whinham
388*0d72ccaaSDale Whinham			vreg_pmu_rfa_0p8: ldo5 {
389*0d72ccaaSDale Whinham				regulator-name = "vreg_pmu_rfa_0p8";
390*0d72ccaaSDale Whinham			};
391*0d72ccaaSDale Whinham
392*0d72ccaaSDale Whinham			vreg_pmu_rfa_1p2: ldo6 {
393*0d72ccaaSDale Whinham				regulator-name = "vreg_pmu_rfa_1p2";
394*0d72ccaaSDale Whinham			};
395*0d72ccaaSDale Whinham
396*0d72ccaaSDale Whinham			vreg_pmu_rfa_1p8: ldo7 {
397*0d72ccaaSDale Whinham				regulator-name = "vreg_pmu_rfa_1p8";
398*0d72ccaaSDale Whinham			};
399*0d72ccaaSDale Whinham
400*0d72ccaaSDale Whinham			vreg_pmu_pcie_0p9: ldo8 {
401*0d72ccaaSDale Whinham				regulator-name = "vreg_pmu_pcie_0p9";
402*0d72ccaaSDale Whinham			};
403*0d72ccaaSDale Whinham
404*0d72ccaaSDale Whinham			vreg_pmu_pcie_1p8: ldo9 {
405*0d72ccaaSDale Whinham				regulator-name = "vreg_pmu_pcie_1p8";
406*0d72ccaaSDale Whinham			};
407*0d72ccaaSDale Whinham		};
408*0d72ccaaSDale Whinham	};
409*0d72ccaaSDale Whinham};
410*0d72ccaaSDale Whinham
411*0d72ccaaSDale Whinham&apps_rsc {
412*0d72ccaaSDale Whinham	regulators-0 {
413*0d72ccaaSDale Whinham		compatible = "qcom,pm8550-rpmh-regulators";
414*0d72ccaaSDale Whinham		qcom,pmic-id = "b";
415*0d72ccaaSDale Whinham
416*0d72ccaaSDale Whinham		vdd-bob1-supply = <&vph_pwr>;
417*0d72ccaaSDale Whinham		vdd-bob2-supply = <&vph_pwr>;
418*0d72ccaaSDale Whinham		vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>;
419*0d72ccaaSDale Whinham		vdd-l2-l13-l14-supply = <&vreg_bob1>;
420*0d72ccaaSDale Whinham		vdd-l5-l16-supply = <&vreg_bob1>;
421*0d72ccaaSDale Whinham		vdd-l6-l7-supply = <&vreg_bob2>;
422*0d72ccaaSDale Whinham		vdd-l8-l9-supply = <&vreg_bob1>;
423*0d72ccaaSDale Whinham		vdd-l12-supply = <&vreg_s5j_1p2>;
424*0d72ccaaSDale Whinham		vdd-l15-supply = <&vreg_s4c_1p8>;
425*0d72ccaaSDale Whinham		vdd-l17-supply = <&vreg_bob2>;
426*0d72ccaaSDale Whinham
427*0d72ccaaSDale Whinham		vreg_bob1: bob1 {
428*0d72ccaaSDale Whinham			regulator-name = "vreg_bob1";
429*0d72ccaaSDale Whinham			regulator-min-microvolt = <3008000>;
430*0d72ccaaSDale Whinham			regulator-max-microvolt = <3960000>;
431*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
432*0d72ccaaSDale Whinham		};
433*0d72ccaaSDale Whinham
434*0d72ccaaSDale Whinham		vreg_bob2: bob2 {
435*0d72ccaaSDale Whinham			regulator-name = "vreg_bob2";
436*0d72ccaaSDale Whinham			regulator-min-microvolt = <2504000>;
437*0d72ccaaSDale Whinham			regulator-max-microvolt = <3008000>;
438*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
439*0d72ccaaSDale Whinham		};
440*0d72ccaaSDale Whinham
441*0d72ccaaSDale Whinham		vreg_l1b_1p8: ldo1 {
442*0d72ccaaSDale Whinham			regulator-name = "vreg_l1b_1p8";
443*0d72ccaaSDale Whinham			regulator-min-microvolt = <1800000>;
444*0d72ccaaSDale Whinham			regulator-max-microvolt = <1800000>;
445*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
446*0d72ccaaSDale Whinham		};
447*0d72ccaaSDale Whinham
448*0d72ccaaSDale Whinham		vreg_l2b_3p0: ldo2 {
449*0d72ccaaSDale Whinham			regulator-name = "vreg_l2b_3p0";
450*0d72ccaaSDale Whinham			regulator-min-microvolt = <3072000>;
451*0d72ccaaSDale Whinham			regulator-max-microvolt = <3072000>;
452*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
453*0d72ccaaSDale Whinham		};
454*0d72ccaaSDale Whinham
455*0d72ccaaSDale Whinham		vreg_l4b_1p8: ldo4 {
456*0d72ccaaSDale Whinham			regulator-name = "vreg_l4b_1p8";
457*0d72ccaaSDale Whinham			regulator-min-microvolt = <1800000>;
458*0d72ccaaSDale Whinham			regulator-max-microvolt = <1800000>;
459*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
460*0d72ccaaSDale Whinham		};
461*0d72ccaaSDale Whinham
462*0d72ccaaSDale Whinham		vreg_l6b_1p8: ldo6 {
463*0d72ccaaSDale Whinham			regulator-name = "vreg_l6b_1p8";
464*0d72ccaaSDale Whinham			regulator-min-microvolt = <1800000>;
465*0d72ccaaSDale Whinham			regulator-max-microvolt = <2960000>;
466*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
467*0d72ccaaSDale Whinham		};
468*0d72ccaaSDale Whinham
469*0d72ccaaSDale Whinham		vreg_l8b_3p0: ldo8 {
470*0d72ccaaSDale Whinham			regulator-name = "vreg_l8b_3p0";
471*0d72ccaaSDale Whinham			regulator-min-microvolt = <3072000>;
472*0d72ccaaSDale Whinham			regulator-max-microvolt = <3072000>;
473*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
474*0d72ccaaSDale Whinham		};
475*0d72ccaaSDale Whinham
476*0d72ccaaSDale Whinham		vreg_l9b_2p9: ldo9 {
477*0d72ccaaSDale Whinham			regulator-name = "vreg_l9b_2p9";
478*0d72ccaaSDale Whinham			regulator-min-microvolt = <2960000>;
479*0d72ccaaSDale Whinham			regulator-max-microvolt = <2960000>;
480*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
481*0d72ccaaSDale Whinham		};
482*0d72ccaaSDale Whinham
483*0d72ccaaSDale Whinham		vreg_l10b_1p8: ldo10 {
484*0d72ccaaSDale Whinham			regulator-name = "vreg_l10b_1p8";
485*0d72ccaaSDale Whinham			regulator-min-microvolt = <1800000>;
486*0d72ccaaSDale Whinham			regulator-max-microvolt = <1800000>;
487*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
488*0d72ccaaSDale Whinham		};
489*0d72ccaaSDale Whinham
490*0d72ccaaSDale Whinham		vreg_l12b_1p2: ldo12 {
491*0d72ccaaSDale Whinham			regulator-name = "vreg_l12b_1p2";
492*0d72ccaaSDale Whinham			regulator-min-microvolt = <1200000>;
493*0d72ccaaSDale Whinham			regulator-max-microvolt = <1200000>;
494*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
495*0d72ccaaSDale Whinham		};
496*0d72ccaaSDale Whinham
497*0d72ccaaSDale Whinham		vreg_l13b_3p0: ldo13 {
498*0d72ccaaSDale Whinham			regulator-name = "vreg_l13b_3p0";
499*0d72ccaaSDale Whinham			regulator-min-microvolt = <3072000>;
500*0d72ccaaSDale Whinham			regulator-max-microvolt = <3072000>;
501*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
502*0d72ccaaSDale Whinham		};
503*0d72ccaaSDale Whinham
504*0d72ccaaSDale Whinham		vreg_l14b_3p0: ldo14 {
505*0d72ccaaSDale Whinham			regulator-name = "vreg_l14b_3p0";
506*0d72ccaaSDale Whinham			regulator-min-microvolt = <3072000>;
507*0d72ccaaSDale Whinham			regulator-max-microvolt = <3072000>;
508*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
509*0d72ccaaSDale Whinham		};
510*0d72ccaaSDale Whinham
511*0d72ccaaSDale Whinham		vreg_l15b_1p8: ldo15 {
512*0d72ccaaSDale Whinham			regulator-name = "vreg_l15b_1p8";
513*0d72ccaaSDale Whinham			regulator-min-microvolt = <1800000>;
514*0d72ccaaSDale Whinham			regulator-max-microvolt = <1800000>;
515*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
516*0d72ccaaSDale Whinham		};
517*0d72ccaaSDale Whinham
518*0d72ccaaSDale Whinham		vreg_l17b_2p5: ldo17 {
519*0d72ccaaSDale Whinham			regulator-name = "vreg_l17b_2p5";
520*0d72ccaaSDale Whinham			regulator-min-microvolt = <2504000>;
521*0d72ccaaSDale Whinham			regulator-max-microvolt = <2504000>;
522*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
523*0d72ccaaSDale Whinham		};
524*0d72ccaaSDale Whinham	};
525*0d72ccaaSDale Whinham
526*0d72ccaaSDale Whinham	regulators-1 {
527*0d72ccaaSDale Whinham		compatible = "qcom,pm8550ve-rpmh-regulators";
528*0d72ccaaSDale Whinham		qcom,pmic-id = "c";
529*0d72ccaaSDale Whinham
530*0d72ccaaSDale Whinham		vdd-l1-supply = <&vreg_s5j_1p2>;
531*0d72ccaaSDale Whinham		vdd-l2-supply = <&vreg_s1f_0p7>;
532*0d72ccaaSDale Whinham		vdd-l3-supply = <&vreg_s1f_0p7>;
533*0d72ccaaSDale Whinham		vdd-s4-supply = <&vph_pwr>;
534*0d72ccaaSDale Whinham
535*0d72ccaaSDale Whinham		vreg_s4c_1p8: smps4 {
536*0d72ccaaSDale Whinham			regulator-name = "vreg_s4c_1p8";
537*0d72ccaaSDale Whinham			regulator-min-microvolt = <1856000>;
538*0d72ccaaSDale Whinham			regulator-max-microvolt = <2000000>;
539*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
540*0d72ccaaSDale Whinham		};
541*0d72ccaaSDale Whinham
542*0d72ccaaSDale Whinham		vreg_l1c_1p2: ldo1 {
543*0d72ccaaSDale Whinham			regulator-name = "vreg_l1c_1p2";
544*0d72ccaaSDale Whinham			regulator-min-microvolt = <1200000>;
545*0d72ccaaSDale Whinham			regulator-max-microvolt = <1200000>;
546*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
547*0d72ccaaSDale Whinham		};
548*0d72ccaaSDale Whinham
549*0d72ccaaSDale Whinham		vreg_l2c_0p8: ldo2 {
550*0d72ccaaSDale Whinham			regulator-name = "vreg_l2c_0p8";
551*0d72ccaaSDale Whinham			regulator-min-microvolt = <880000>;
552*0d72ccaaSDale Whinham			regulator-max-microvolt = <880000>;
553*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
554*0d72ccaaSDale Whinham		};
555*0d72ccaaSDale Whinham
556*0d72ccaaSDale Whinham		vreg_l3c_0p8: ldo3 {
557*0d72ccaaSDale Whinham			regulator-name = "vreg_l3c_0p8";
558*0d72ccaaSDale Whinham			regulator-min-microvolt = <912000>;
559*0d72ccaaSDale Whinham			regulator-max-microvolt = <912000>;
560*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
561*0d72ccaaSDale Whinham		};
562*0d72ccaaSDale Whinham	};
563*0d72ccaaSDale Whinham
564*0d72ccaaSDale Whinham	regulators-2 {
565*0d72ccaaSDale Whinham		compatible = "qcom,pmc8380-rpmh-regulators";
566*0d72ccaaSDale Whinham		qcom,pmic-id = "d";
567*0d72ccaaSDale Whinham
568*0d72ccaaSDale Whinham		vdd-l1-supply = <&vreg_s1f_0p7>;
569*0d72ccaaSDale Whinham		vdd-l2-supply = <&vreg_s1f_0p7>;
570*0d72ccaaSDale Whinham		vdd-l3-supply = <&vreg_s4c_1p8>;
571*0d72ccaaSDale Whinham		vdd-s1-supply = <&vph_pwr>;
572*0d72ccaaSDale Whinham
573*0d72ccaaSDale Whinham		vreg_l1d_0p8: ldo1 {
574*0d72ccaaSDale Whinham			regulator-name = "vreg_l1d_0p8";
575*0d72ccaaSDale Whinham			regulator-min-microvolt = <880000>;
576*0d72ccaaSDale Whinham			regulator-max-microvolt = <880000>;
577*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
578*0d72ccaaSDale Whinham		};
579*0d72ccaaSDale Whinham
580*0d72ccaaSDale Whinham		vreg_l2d_0p9: ldo2 {
581*0d72ccaaSDale Whinham			regulator-name = "vreg_l2d_0p9";
582*0d72ccaaSDale Whinham			regulator-min-microvolt = <912000>;
583*0d72ccaaSDale Whinham			regulator-max-microvolt = <912000>;
584*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
585*0d72ccaaSDale Whinham		};
586*0d72ccaaSDale Whinham
587*0d72ccaaSDale Whinham		vreg_l3d_1p8: ldo3 {
588*0d72ccaaSDale Whinham			regulator-name = "vreg_l3d_1p8";
589*0d72ccaaSDale Whinham			regulator-min-microvolt = <1800000>;
590*0d72ccaaSDale Whinham			regulator-max-microvolt = <1800000>;
591*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
592*0d72ccaaSDale Whinham		};
593*0d72ccaaSDale Whinham	};
594*0d72ccaaSDale Whinham
595*0d72ccaaSDale Whinham	regulators-3 {
596*0d72ccaaSDale Whinham		compatible = "qcom,pmc8380-rpmh-regulators";
597*0d72ccaaSDale Whinham		qcom,pmic-id = "e";
598*0d72ccaaSDale Whinham
599*0d72ccaaSDale Whinham		vdd-l2-supply = <&vreg_s1f_0p7>;
600*0d72ccaaSDale Whinham		vdd-l3-supply = <&vreg_s5j_1p2>;
601*0d72ccaaSDale Whinham
602*0d72ccaaSDale Whinham		vreg_l2e_0p8: ldo2 {
603*0d72ccaaSDale Whinham			regulator-name = "vreg_l2e_0p8";
604*0d72ccaaSDale Whinham			regulator-min-microvolt = <880000>;
605*0d72ccaaSDale Whinham			regulator-max-microvolt = <880000>;
606*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
607*0d72ccaaSDale Whinham		};
608*0d72ccaaSDale Whinham
609*0d72ccaaSDale Whinham		vreg_l3e_1p2: ldo3 {
610*0d72ccaaSDale Whinham			regulator-name = "vreg_l3e_1p2";
611*0d72ccaaSDale Whinham			regulator-min-microvolt = <1200000>;
612*0d72ccaaSDale Whinham			regulator-max-microvolt = <1200000>;
613*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
614*0d72ccaaSDale Whinham		};
615*0d72ccaaSDale Whinham	};
616*0d72ccaaSDale Whinham
617*0d72ccaaSDale Whinham	regulators-4 {
618*0d72ccaaSDale Whinham		compatible = "qcom,pmc8380-rpmh-regulators";
619*0d72ccaaSDale Whinham		qcom,pmic-id = "f";
620*0d72ccaaSDale Whinham
621*0d72ccaaSDale Whinham		vdd-l1-supply = <&vreg_s5j_1p2>;
622*0d72ccaaSDale Whinham		vdd-l2-supply = <&vreg_s5j_1p2>;
623*0d72ccaaSDale Whinham		vdd-l3-supply = <&vreg_s5j_1p2>;
624*0d72ccaaSDale Whinham		vdd-s1-supply = <&vph_pwr>;
625*0d72ccaaSDale Whinham
626*0d72ccaaSDale Whinham		vreg_s1f_0p7: smps1 {
627*0d72ccaaSDale Whinham			regulator-name = "vreg_s1f_0p7";
628*0d72ccaaSDale Whinham			regulator-min-microvolt = <700000>;
629*0d72ccaaSDale Whinham			regulator-max-microvolt = <1100000>;
630*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
631*0d72ccaaSDale Whinham		};
632*0d72ccaaSDale Whinham	};
633*0d72ccaaSDale Whinham
634*0d72ccaaSDale Whinham	regulators-6 {
635*0d72ccaaSDale Whinham		compatible = "qcom,pm8550ve-rpmh-regulators";
636*0d72ccaaSDale Whinham		qcom,pmic-id = "i";
637*0d72ccaaSDale Whinham
638*0d72ccaaSDale Whinham		vdd-l1-supply = <&vreg_s4c_1p8>;
639*0d72ccaaSDale Whinham		vdd-l2-supply = <&vreg_s5j_1p2>;
640*0d72ccaaSDale Whinham		vdd-l3-supply = <&vreg_s1f_0p7>;
641*0d72ccaaSDale Whinham		vdd-s1-supply = <&vph_pwr>;
642*0d72ccaaSDale Whinham		vdd-s2-supply = <&vph_pwr>;
643*0d72ccaaSDale Whinham
644*0d72ccaaSDale Whinham		vreg_s1i_0p9: smps1 {
645*0d72ccaaSDale Whinham			regulator-name = "vreg_s1i_0p9";
646*0d72ccaaSDale Whinham			regulator-min-microvolt = <900000>;
647*0d72ccaaSDale Whinham			regulator-max-microvolt = <920000>;
648*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
649*0d72ccaaSDale Whinham		};
650*0d72ccaaSDale Whinham
651*0d72ccaaSDale Whinham		vreg_s2i_1p0: smps2 {
652*0d72ccaaSDale Whinham			regulator-name = "vreg_s2i_1p0";
653*0d72ccaaSDale Whinham			regulator-min-microvolt = <1000000>;
654*0d72ccaaSDale Whinham			regulator-max-microvolt = <1100000>;
655*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
656*0d72ccaaSDale Whinham		};
657*0d72ccaaSDale Whinham
658*0d72ccaaSDale Whinham		vreg_l1i_1p8: ldo1 {
659*0d72ccaaSDale Whinham			regulator-name = "vreg_l1i_1p8";
660*0d72ccaaSDale Whinham			regulator-min-microvolt = <1800000>;
661*0d72ccaaSDale Whinham			regulator-max-microvolt = <1800000>;
662*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
663*0d72ccaaSDale Whinham		};
664*0d72ccaaSDale Whinham
665*0d72ccaaSDale Whinham		vreg_l2i_1p2: ldo2 {
666*0d72ccaaSDale Whinham			regulator-name = "vreg_l2i_1p2";
667*0d72ccaaSDale Whinham			regulator-min-microvolt = <1200000>;
668*0d72ccaaSDale Whinham			regulator-max-microvolt = <1200000>;
669*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
670*0d72ccaaSDale Whinham		};
671*0d72ccaaSDale Whinham
672*0d72ccaaSDale Whinham		vreg_l3i_0p8: ldo3 {
673*0d72ccaaSDale Whinham			regulator-name = "vreg_l3i_0p8";
674*0d72ccaaSDale Whinham			regulator-min-microvolt = <880000>;
675*0d72ccaaSDale Whinham			regulator-max-microvolt = <880000>;
676*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
677*0d72ccaaSDale Whinham		};
678*0d72ccaaSDale Whinham	};
679*0d72ccaaSDale Whinham
680*0d72ccaaSDale Whinham	regulators-7 {
681*0d72ccaaSDale Whinham		compatible = "qcom,pm8550ve-rpmh-regulators";
682*0d72ccaaSDale Whinham		qcom,pmic-id = "j";
683*0d72ccaaSDale Whinham
684*0d72ccaaSDale Whinham		vdd-l1-supply = <&vreg_s1f_0p7>;
685*0d72ccaaSDale Whinham		vdd-l2-supply = <&vreg_s5j_1p2>;
686*0d72ccaaSDale Whinham		vdd-l3-supply = <&vreg_s1f_0p7>;
687*0d72ccaaSDale Whinham		vdd-s5-supply = <&vph_pwr>;
688*0d72ccaaSDale Whinham
689*0d72ccaaSDale Whinham		vreg_s5j_1p2: smps5 {
690*0d72ccaaSDale Whinham			regulator-name = "vreg_s5j_1p2";
691*0d72ccaaSDale Whinham			regulator-min-microvolt = <1256000>;
692*0d72ccaaSDale Whinham			regulator-max-microvolt = <1304000>;
693*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
694*0d72ccaaSDale Whinham		};
695*0d72ccaaSDale Whinham
696*0d72ccaaSDale Whinham		vreg_l1j_0p8: ldo1 {
697*0d72ccaaSDale Whinham			regulator-name = "vreg_l1j_0p8";
698*0d72ccaaSDale Whinham			regulator-min-microvolt = <912000>;
699*0d72ccaaSDale Whinham			regulator-max-microvolt = <912000>;
700*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
701*0d72ccaaSDale Whinham		};
702*0d72ccaaSDale Whinham
703*0d72ccaaSDale Whinham		vreg_l2j_1p2: ldo2 {
704*0d72ccaaSDale Whinham			regulator-name = "vreg_l2j_1p2";
705*0d72ccaaSDale Whinham			regulator-min-microvolt = <1256000>;
706*0d72ccaaSDale Whinham			regulator-max-microvolt = <1256000>;
707*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
708*0d72ccaaSDale Whinham		};
709*0d72ccaaSDale Whinham
710*0d72ccaaSDale Whinham		vreg_l3j_0p8: ldo3 {
711*0d72ccaaSDale Whinham			regulator-name = "vreg_l3j_0p8";
712*0d72ccaaSDale Whinham			regulator-min-microvolt = <880000>;
713*0d72ccaaSDale Whinham			regulator-max-microvolt = <880000>;
714*0d72ccaaSDale Whinham			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
715*0d72ccaaSDale Whinham		};
716*0d72ccaaSDale Whinham	};
717*0d72ccaaSDale Whinham};
718*0d72ccaaSDale Whinham
719*0d72ccaaSDale Whinham&gpu {
720*0d72ccaaSDale Whinham	status = "okay";
721*0d72ccaaSDale Whinham
722*0d72ccaaSDale Whinham	zap-shader {
723*0d72ccaaSDale Whinham		memory-region = <&gpu_microcode_mem>;
724*0d72ccaaSDale Whinham		firmware-name = "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn";
725*0d72ccaaSDale Whinham	};
726*0d72ccaaSDale Whinham};
727*0d72ccaaSDale Whinham
728*0d72ccaaSDale Whinham&i2c0 {
729*0d72ccaaSDale Whinham	clock-frequency = <100000>;
730*0d72ccaaSDale Whinham
731*0d72ccaaSDale Whinham	status = "okay";
732*0d72ccaaSDale Whinham
733*0d72ccaaSDale Whinham	/* Something @39, @3e, @44 */
734*0d72ccaaSDale Whinham};
735*0d72ccaaSDale Whinham
736*0d72ccaaSDale Whinham&i2c3 {
737*0d72ccaaSDale Whinham	clock-frequency = <400000>;
738*0d72ccaaSDale Whinham
739*0d72ccaaSDale Whinham	status = "okay";
740*0d72ccaaSDale Whinham
741*0d72ccaaSDale Whinham	/* Left-side bottom port */
742*0d72ccaaSDale Whinham	typec-mux@8 {
743*0d72ccaaSDale Whinham		compatible = "parade,ps8830";
744*0d72ccaaSDale Whinham		reg = <0x8>;
745*0d72ccaaSDale Whinham
746*0d72ccaaSDale Whinham		reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>;
747*0d72ccaaSDale Whinham
748*0d72ccaaSDale Whinham		clocks = <&rpmhcc RPMH_RF_CLK3>;
749*0d72ccaaSDale Whinham
750*0d72ccaaSDale Whinham		vdd-supply = <&vreg_rtmr0_1p15>;
751*0d72ccaaSDale Whinham		vdd33-supply = <&vreg_rtmr0_3p3>;
752*0d72ccaaSDale Whinham		vdd33-cap-supply = <&vreg_rtmr0_3p3>;
753*0d72ccaaSDale Whinham		vddar-supply = <&vreg_rtmr0_1p15>;
754*0d72ccaaSDale Whinham		vddat-supply = <&vreg_rtmr0_1p15>;
755*0d72ccaaSDale Whinham		vddio-supply = <&vreg_rtmr0_1p8>;
756*0d72ccaaSDale Whinham
757*0d72ccaaSDale Whinham		pinctrl-0 = <&rtmr0_default>;
758*0d72ccaaSDale Whinham		pinctrl-names = "default";
759*0d72ccaaSDale Whinham
760*0d72ccaaSDale Whinham		retimer-switch;
761*0d72ccaaSDale Whinham		orientation-switch;
762*0d72ccaaSDale Whinham
763*0d72ccaaSDale Whinham		ports {
764*0d72ccaaSDale Whinham			#address-cells = <1>;
765*0d72ccaaSDale Whinham			#size-cells = <0>;
766*0d72ccaaSDale Whinham
767*0d72ccaaSDale Whinham			port@0 {
768*0d72ccaaSDale Whinham				reg = <0>;
769*0d72ccaaSDale Whinham
770*0d72ccaaSDale Whinham				retimer_ss0_ss_out: endpoint {
771*0d72ccaaSDale Whinham					remote-endpoint = <&pmic_glink_ss0_ss_in>;
772*0d72ccaaSDale Whinham				};
773*0d72ccaaSDale Whinham			};
774*0d72ccaaSDale Whinham
775*0d72ccaaSDale Whinham			port@1 {
776*0d72ccaaSDale Whinham				reg = <1>;
777*0d72ccaaSDale Whinham
778*0d72ccaaSDale Whinham				retimer_ss0_ss_in: endpoint {
779*0d72ccaaSDale Whinham					remote-endpoint = <&usb_1_ss0_qmpphy_out>;
780*0d72ccaaSDale Whinham				};
781*0d72ccaaSDale Whinham			};
782*0d72ccaaSDale Whinham
783*0d72ccaaSDale Whinham			port@2 {
784*0d72ccaaSDale Whinham				reg = <2>;
785*0d72ccaaSDale Whinham
786*0d72ccaaSDale Whinham				retimer_ss0_con_sbu_out: endpoint {
787*0d72ccaaSDale Whinham					remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
788*0d72ccaaSDale Whinham				};
789*0d72ccaaSDale Whinham			};
790*0d72ccaaSDale Whinham		};
791*0d72ccaaSDale Whinham	};
792*0d72ccaaSDale Whinham};
793*0d72ccaaSDale Whinham
794*0d72ccaaSDale Whinham&i2c4 {
795*0d72ccaaSDale Whinham	clock-frequency = <400000>;
796*0d72ccaaSDale Whinham
797*0d72ccaaSDale Whinham	status = "okay";
798*0d72ccaaSDale Whinham
799*0d72ccaaSDale Whinham	/* Something @12, @14, @16, @18, @1a */
800*0d72ccaaSDale Whinham};
801*0d72ccaaSDale Whinham
802*0d72ccaaSDale Whinham&i2c7 {
803*0d72ccaaSDale Whinham	clock-frequency = <400000>;
804*0d72ccaaSDale Whinham
805*0d72ccaaSDale Whinham	status = "okay";
806*0d72ccaaSDale Whinham
807*0d72ccaaSDale Whinham	/* Left-side top port */
808*0d72ccaaSDale Whinham	typec-mux@8 {
809*0d72ccaaSDale Whinham		compatible = "parade,ps8830";
810*0d72ccaaSDale Whinham		reg = <0x8>;
811*0d72ccaaSDale Whinham
812*0d72ccaaSDale Whinham		reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>;
813*0d72ccaaSDale Whinham
814*0d72ccaaSDale Whinham		clocks = <&rpmhcc RPMH_RF_CLK4>;
815*0d72ccaaSDale Whinham
816*0d72ccaaSDale Whinham		vdd-supply = <&vreg_rtmr1_1p15>;
817*0d72ccaaSDale Whinham		vdd33-supply = <&vreg_rtmr1_3p3>;
818*0d72ccaaSDale Whinham		vdd33-cap-supply = <&vreg_rtmr1_3p3>;
819*0d72ccaaSDale Whinham		vddar-supply = <&vreg_rtmr1_1p15>;
820*0d72ccaaSDale Whinham		vddat-supply = <&vreg_rtmr1_1p15>;
821*0d72ccaaSDale Whinham		vddio-supply = <&vreg_rtmr1_1p8>;
822*0d72ccaaSDale Whinham
823*0d72ccaaSDale Whinham		retimer-switch;
824*0d72ccaaSDale Whinham		orientation-switch;
825*0d72ccaaSDale Whinham
826*0d72ccaaSDale Whinham		ports {
827*0d72ccaaSDale Whinham			#address-cells = <1>;
828*0d72ccaaSDale Whinham			#size-cells = <0>;
829*0d72ccaaSDale Whinham
830*0d72ccaaSDale Whinham			port@0 {
831*0d72ccaaSDale Whinham				reg = <0>;
832*0d72ccaaSDale Whinham
833*0d72ccaaSDale Whinham				retimer_ss1_ss_out: endpoint {
834*0d72ccaaSDale Whinham					remote-endpoint = <&pmic_glink_ss1_ss_in>;
835*0d72ccaaSDale Whinham				};
836*0d72ccaaSDale Whinham			};
837*0d72ccaaSDale Whinham
838*0d72ccaaSDale Whinham			port@1 {
839*0d72ccaaSDale Whinham				reg = <1>;
840*0d72ccaaSDale Whinham
841*0d72ccaaSDale Whinham				retimer_ss1_ss_in: endpoint {
842*0d72ccaaSDale Whinham					remote-endpoint = <&usb_1_ss1_qmpphy_out>;
843*0d72ccaaSDale Whinham				};
844*0d72ccaaSDale Whinham			};
845*0d72ccaaSDale Whinham
846*0d72ccaaSDale Whinham			port@2 {
847*0d72ccaaSDale Whinham				reg = <2>;
848*0d72ccaaSDale Whinham
849*0d72ccaaSDale Whinham				retimer_ss1_con_sbu_out: endpoint {
850*0d72ccaaSDale Whinham					remote-endpoint = <&pmic_glink_ss1_con_sbu_in>;
851*0d72ccaaSDale Whinham				};
852*0d72ccaaSDale Whinham			};
853*0d72ccaaSDale Whinham		};
854*0d72ccaaSDale Whinham	};
855*0d72ccaaSDale Whinham};
856*0d72ccaaSDale Whinham
857*0d72ccaaSDale Whinham&lpass_tlmm {
858*0d72ccaaSDale Whinham	spkr_01_sd_n_active: spkr-01-sd-n-active-state {
859*0d72ccaaSDale Whinham		pins = "gpio12";
860*0d72ccaaSDale Whinham		function = "gpio";
861*0d72ccaaSDale Whinham		drive-strength = <16>;
862*0d72ccaaSDale Whinham		bias-disable;
863*0d72ccaaSDale Whinham	};
864*0d72ccaaSDale Whinham};
865*0d72ccaaSDale Whinham
866*0d72ccaaSDale Whinham&lpass_vamacro {
867*0d72ccaaSDale Whinham	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
868*0d72ccaaSDale Whinham	pinctrl-names = "default";
869*0d72ccaaSDale Whinham
870*0d72ccaaSDale Whinham	vdd-micb-supply = <&vreg_l1b_1p8>;
871*0d72ccaaSDale Whinham	qcom,dmic-sample-rate = <4800000>;
872*0d72ccaaSDale Whinham};
873*0d72ccaaSDale Whinham
874*0d72ccaaSDale Whinham&mdss {
875*0d72ccaaSDale Whinham	status = "okay";
876*0d72ccaaSDale Whinham};
877*0d72ccaaSDale Whinham
878*0d72ccaaSDale Whinham&mdss_dp0 {
879*0d72ccaaSDale Whinham	status = "okay";
880*0d72ccaaSDale Whinham};
881*0d72ccaaSDale Whinham
882*0d72ccaaSDale Whinham&mdss_dp0_out {
883*0d72ccaaSDale Whinham	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
884*0d72ccaaSDale Whinham};
885*0d72ccaaSDale Whinham
886*0d72ccaaSDale Whinham&mdss_dp1 {
887*0d72ccaaSDale Whinham	status = "okay";
888*0d72ccaaSDale Whinham};
889*0d72ccaaSDale Whinham
890*0d72ccaaSDale Whinham&mdss_dp1_out {
891*0d72ccaaSDale Whinham	link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
892*0d72ccaaSDale Whinham};
893*0d72ccaaSDale Whinham
894*0d72ccaaSDale Whinham&mdss_dp3 {
895*0d72ccaaSDale Whinham	compatible = "qcom,x1e80100-dp";
896*0d72ccaaSDale Whinham	/delete-property/ #sound-dai-cells;
897*0d72ccaaSDale Whinham
898*0d72ccaaSDale Whinham	status = "okay";
899*0d72ccaaSDale Whinham
900*0d72ccaaSDale Whinham	aux-bus {
901*0d72ccaaSDale Whinham		panel: panel {
902*0d72ccaaSDale Whinham			compatible = "edp-panel";
903*0d72ccaaSDale Whinham			enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
904*0d72ccaaSDale Whinham			power-supply = <&vreg_edp_3p3>;
905*0d72ccaaSDale Whinham
906*0d72ccaaSDale Whinham			pinctrl-0 = <&edp_bl_en>;
907*0d72ccaaSDale Whinham			pinctrl-names = "default";
908*0d72ccaaSDale Whinham
909*0d72ccaaSDale Whinham			port {
910*0d72ccaaSDale Whinham				edp_panel_in: endpoint {
911*0d72ccaaSDale Whinham					remote-endpoint = <&mdss_dp3_out>;
912*0d72ccaaSDale Whinham				};
913*0d72ccaaSDale Whinham			};
914*0d72ccaaSDale Whinham		};
915*0d72ccaaSDale Whinham	};
916*0d72ccaaSDale Whinham
917*0d72ccaaSDale Whinham	ports {
918*0d72ccaaSDale Whinham		port@1 {
919*0d72ccaaSDale Whinham			reg = <1>;
920*0d72ccaaSDale Whinham
921*0d72ccaaSDale Whinham			mdss_dp3_out: endpoint {
922*0d72ccaaSDale Whinham				data-lanes = <0 1 2 3>;
923*0d72ccaaSDale Whinham				link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
924*0d72ccaaSDale Whinham
925*0d72ccaaSDale Whinham				remote-endpoint = <&edp_panel_in>;
926*0d72ccaaSDale Whinham			};
927*0d72ccaaSDale Whinham		};
928*0d72ccaaSDale Whinham	};
929*0d72ccaaSDale Whinham};
930*0d72ccaaSDale Whinham
931*0d72ccaaSDale Whinham&mdss_dp3_phy {
932*0d72ccaaSDale Whinham	vdda-phy-supply = <&vreg_l3j_0p8>;
933*0d72ccaaSDale Whinham	vdda-pll-supply = <&vreg_l2j_1p2>;
934*0d72ccaaSDale Whinham
935*0d72ccaaSDale Whinham	status = "okay";
936*0d72ccaaSDale Whinham};
937*0d72ccaaSDale Whinham
938*0d72ccaaSDale Whinham&pcie4 {
939*0d72ccaaSDale Whinham	status = "okay";
940*0d72ccaaSDale Whinham};
941*0d72ccaaSDale Whinham
942*0d72ccaaSDale Whinham&pcie4_phy {
943*0d72ccaaSDale Whinham	vdda-phy-supply = <&vreg_l3i_0p8>;
944*0d72ccaaSDale Whinham	vdda-pll-supply = <&vreg_l3e_1p2>;
945*0d72ccaaSDale Whinham
946*0d72ccaaSDale Whinham	status = "okay";
947*0d72ccaaSDale Whinham};
948*0d72ccaaSDale Whinham
949*0d72ccaaSDale Whinham&pcie4_port0 {
950*0d72ccaaSDale Whinham	wifi@0 {
951*0d72ccaaSDale Whinham		compatible = "pci17cb,1107";
952*0d72ccaaSDale Whinham		reg = <0x10000 0x0 0x0 0x0 0x0>;
953*0d72ccaaSDale Whinham
954*0d72ccaaSDale Whinham		vddaon-supply = <&vreg_pmu_aon_0p59>;
955*0d72ccaaSDale Whinham		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
956*0d72ccaaSDale Whinham		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
957*0d72ccaaSDale Whinham		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
958*0d72ccaaSDale Whinham		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
959*0d72ccaaSDale Whinham		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
960*0d72ccaaSDale Whinham		vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
961*0d72ccaaSDale Whinham		vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
962*0d72ccaaSDale Whinham		vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
963*0d72ccaaSDale Whinham	};
964*0d72ccaaSDale Whinham};
965*0d72ccaaSDale Whinham
966*0d72ccaaSDale Whinham&pcie6a {
967*0d72ccaaSDale Whinham	perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
968*0d72ccaaSDale Whinham	wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
969*0d72ccaaSDale Whinham
970*0d72ccaaSDale Whinham	vddpe-3v3-supply = <&vreg_nvme>;
971*0d72ccaaSDale Whinham
972*0d72ccaaSDale Whinham	pinctrl-0 = <&pcie6a_default>;
973*0d72ccaaSDale Whinham	pinctrl-names = "default";
974*0d72ccaaSDale Whinham
975*0d72ccaaSDale Whinham	status = "okay";
976*0d72ccaaSDale Whinham};
977*0d72ccaaSDale Whinham
978*0d72ccaaSDale Whinham&pcie6a_phy {
979*0d72ccaaSDale Whinham	vdda-phy-supply = <&vreg_l1d_0p8>;
980*0d72ccaaSDale Whinham	vdda-pll-supply = <&vreg_l2j_1p2>;
981*0d72ccaaSDale Whinham
982*0d72ccaaSDale Whinham	status = "okay";
983*0d72ccaaSDale Whinham};
984*0d72ccaaSDale Whinham
985*0d72ccaaSDale Whinham&pm8550_gpios {
986*0d72ccaaSDale Whinham	rtmr0_default: rtmr0-reset-n-active-state {
987*0d72ccaaSDale Whinham		pins = "gpio10";
988*0d72ccaaSDale Whinham		function = "normal";
989*0d72ccaaSDale Whinham		power-source = <1>; /* 1.8V */
990*0d72ccaaSDale Whinham	};
991*0d72ccaaSDale Whinham
992*0d72ccaaSDale Whinham	rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state {
993*0d72ccaaSDale Whinham		pins = "gpio11";
994*0d72ccaaSDale Whinham		function = "normal";
995*0d72ccaaSDale Whinham		power-source = <1>; /* 1.8V */
996*0d72ccaaSDale Whinham	};
997*0d72ccaaSDale Whinham};
998*0d72ccaaSDale Whinham
999*0d72ccaaSDale Whinham&pm8550ve_9_gpios {
1000*0d72ccaaSDale Whinham	rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state {
1001*0d72ccaaSDale Whinham		pins = "gpio8";
1002*0d72ccaaSDale Whinham		function = "normal";
1003*0d72ccaaSDale Whinham		power-source = <1>; /* 1.8V */
1004*0d72ccaaSDale Whinham	};
1005*0d72ccaaSDale Whinham};
1006*0d72ccaaSDale Whinham
1007*0d72ccaaSDale Whinham&pmc8380_3_gpios {
1008*0d72ccaaSDale Whinham	edp_bl_en: edp-bl-en-state {
1009*0d72ccaaSDale Whinham		pins = "gpio4";
1010*0d72ccaaSDale Whinham		function = "normal";
1011*0d72ccaaSDale Whinham		power-source = <1>; /* 1.8V */
1012*0d72ccaaSDale Whinham		input-disable;
1013*0d72ccaaSDale Whinham		output-enable;
1014*0d72ccaaSDale Whinham	};
1015*0d72ccaaSDale Whinham};
1016*0d72ccaaSDale Whinham
1017*0d72ccaaSDale Whinham&pmc8380_5_gpios {
1018*0d72ccaaSDale Whinham	rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state {
1019*0d72ccaaSDale Whinham		pins = "gpio8";
1020*0d72ccaaSDale Whinham		function = "normal";
1021*0d72ccaaSDale Whinham		power-source = <1>; /* 1.8V */
1022*0d72ccaaSDale Whinham	};
1023*0d72ccaaSDale Whinham};
1024*0d72ccaaSDale Whinham
1025*0d72ccaaSDale Whinham&qupv3_0 {
1026*0d72ccaaSDale Whinham	status = "okay";
1027*0d72ccaaSDale Whinham};
1028*0d72ccaaSDale Whinham
1029*0d72ccaaSDale Whinham&qupv3_1 {
1030*0d72ccaaSDale Whinham	status = "okay";
1031*0d72ccaaSDale Whinham};
1032*0d72ccaaSDale Whinham
1033*0d72ccaaSDale Whinham&qupv3_2 {
1034*0d72ccaaSDale Whinham	status = "okay";
1035*0d72ccaaSDale Whinham};
1036*0d72ccaaSDale Whinham
1037*0d72ccaaSDale Whinham&remoteproc_adsp {
1038*0d72ccaaSDale Whinham	firmware-name = "qcom/x1e80100/microsoft/Denali/qcadsp8380.mbn",
1039*0d72ccaaSDale Whinham			"qcom/x1e80100/microsoft/Denali/adsp_dtb.mbn";
1040*0d72ccaaSDale Whinham
1041*0d72ccaaSDale Whinham	status = "okay";
1042*0d72ccaaSDale Whinham};
1043*0d72ccaaSDale Whinham
1044*0d72ccaaSDale Whinham&remoteproc_cdsp {
1045*0d72ccaaSDale Whinham	firmware-name = "qcom/x1e80100/microsoft/Denali/qccdsp8380.mbn",
1046*0d72ccaaSDale Whinham			"qcom/x1e80100/microsoft/Denali/cdsp_dtb.mbn";
1047*0d72ccaaSDale Whinham
1048*0d72ccaaSDale Whinham	status = "okay";
1049*0d72ccaaSDale Whinham};
1050*0d72ccaaSDale Whinham
1051*0d72ccaaSDale Whinham&smb2360_0 {
1052*0d72ccaaSDale Whinham	status = "okay";
1053*0d72ccaaSDale Whinham};
1054*0d72ccaaSDale Whinham
1055*0d72ccaaSDale Whinham&smb2360_0_eusb2_repeater {
1056*0d72ccaaSDale Whinham	vdd18-supply = <&vreg_l3d_1p8>;
1057*0d72ccaaSDale Whinham	vdd3-supply = <&vreg_l2b_3p0>;
1058*0d72ccaaSDale Whinham};
1059*0d72ccaaSDale Whinham
1060*0d72ccaaSDale Whinham&smb2360_1 {
1061*0d72ccaaSDale Whinham	status = "okay";
1062*0d72ccaaSDale Whinham};
1063*0d72ccaaSDale Whinham
1064*0d72ccaaSDale Whinham&smb2360_1_eusb2_repeater {
1065*0d72ccaaSDale Whinham	vdd18-supply = <&vreg_l3d_1p8>;
1066*0d72ccaaSDale Whinham	vdd3-supply = <&vreg_l14b_3p0>;
1067*0d72ccaaSDale Whinham};
1068*0d72ccaaSDale Whinham
1069*0d72ccaaSDale Whinham&smb2360_2 {
1070*0d72ccaaSDale Whinham	status = "okay";
1071*0d72ccaaSDale Whinham};
1072*0d72ccaaSDale Whinham
1073*0d72ccaaSDale Whinham&smb2360_2_eusb2_repeater {
1074*0d72ccaaSDale Whinham	vdd18-supply = <&vreg_l3d_1p8>;
1075*0d72ccaaSDale Whinham	vdd3-supply = <&vreg_l8b_3p0>;
1076*0d72ccaaSDale Whinham};
1077*0d72ccaaSDale Whinham
1078*0d72ccaaSDale Whinham&swr0 {
1079*0d72ccaaSDale Whinham	status = "okay";
1080*0d72ccaaSDale Whinham
1081*0d72ccaaSDale Whinham	pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
1082*0d72ccaaSDale Whinham	pinctrl-names = "default";
1083*0d72ccaaSDale Whinham
1084*0d72ccaaSDale Whinham	/* WSA8845, Left Speaker */
1085*0d72ccaaSDale Whinham	left_spkr: speaker@0,0 {
1086*0d72ccaaSDale Whinham		compatible = "sdw20217020400";
1087*0d72ccaaSDale Whinham		reg = <0 0>;
1088*0d72ccaaSDale Whinham		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
1089*0d72ccaaSDale Whinham		#sound-dai-cells = <0>;
1090*0d72ccaaSDale Whinham		sound-name-prefix = "SpkrLeft";
1091*0d72ccaaSDale Whinham		vdd-1p8-supply = <&vreg_l15b_1p8>;
1092*0d72ccaaSDale Whinham		vdd-io-supply = <&vreg_l12b_1p2>;
1093*0d72ccaaSDale Whinham		qcom,port-mapping = <1 2 3 7 10 13>;
1094*0d72ccaaSDale Whinham	};
1095*0d72ccaaSDale Whinham
1096*0d72ccaaSDale Whinham	/* WSA8845, Right Speaker */
1097*0d72ccaaSDale Whinham	right_spkr: speaker@0,1 {
1098*0d72ccaaSDale Whinham		compatible = "sdw20217020400";
1099*0d72ccaaSDale Whinham		reg = <0 1>;
1100*0d72ccaaSDale Whinham		reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
1101*0d72ccaaSDale Whinham		#sound-dai-cells = <0>;
1102*0d72ccaaSDale Whinham		sound-name-prefix = "SpkrRight";
1103*0d72ccaaSDale Whinham		vdd-1p8-supply = <&vreg_l15b_1p8>;
1104*0d72ccaaSDale Whinham		vdd-io-supply = <&vreg_l12b_1p2>;
1105*0d72ccaaSDale Whinham		qcom,port-mapping = <4 5 6 7 11 13>;
1106*0d72ccaaSDale Whinham	};
1107*0d72ccaaSDale Whinham};
1108*0d72ccaaSDale Whinham
1109*0d72ccaaSDale Whinham&tlmm {
1110*0d72ccaaSDale Whinham	gpio-reserved-ranges = <44 4>, /* SPI (TPM) */
1111*0d72ccaaSDale Whinham			       <238 1>; /* UFS Reset */
1112*0d72ccaaSDale Whinham
1113*0d72ccaaSDale Whinham	hall_int_n_default: hall-int-n-state {
1114*0d72ccaaSDale Whinham		pins = "gpio2";
1115*0d72ccaaSDale Whinham		function = "gpio";
1116*0d72ccaaSDale Whinham		bias-disable;
1117*0d72ccaaSDale Whinham	};
1118*0d72ccaaSDale Whinham
1119*0d72ccaaSDale Whinham	nvme_reg_en: nvme-reg-en-state {
1120*0d72ccaaSDale Whinham		pins = "gpio18";
1121*0d72ccaaSDale Whinham		function = "gpio";
1122*0d72ccaaSDale Whinham		drive-strength = <2>;
1123*0d72ccaaSDale Whinham		bias-disable;
1124*0d72ccaaSDale Whinham	};
1125*0d72ccaaSDale Whinham
1126*0d72ccaaSDale Whinham	edp_reg_en: edp-reg-en-state {
1127*0d72ccaaSDale Whinham		pins = "gpio70";
1128*0d72ccaaSDale Whinham		function = "gpio";
1129*0d72ccaaSDale Whinham		drive-strength = <16>;
1130*0d72ccaaSDale Whinham		bias-disable;
1131*0d72ccaaSDale Whinham	};
1132*0d72ccaaSDale Whinham
1133*0d72ccaaSDale Whinham	ssam_state: ssam-state-state {
1134*0d72ccaaSDale Whinham		pins = "gpio91";
1135*0d72ccaaSDale Whinham		function = "gpio";
1136*0d72ccaaSDale Whinham		bias-disable;
1137*0d72ccaaSDale Whinham	};
1138*0d72ccaaSDale Whinham
1139*0d72ccaaSDale Whinham	wcn_wlan_bt_en: wcn-wlan-bt-en-state {
1140*0d72ccaaSDale Whinham		pins = "gpio116", "gpio117";
1141*0d72ccaaSDale Whinham		function = "gpio";
1142*0d72ccaaSDale Whinham		drive-strength = <2>;
1143*0d72ccaaSDale Whinham		bias-disable;
1144*0d72ccaaSDale Whinham	};
1145*0d72ccaaSDale Whinham
1146*0d72ccaaSDale Whinham	pcie4_default: pcie4-default-state {
1147*0d72ccaaSDale Whinham		clkreq-n-pins {
1148*0d72ccaaSDale Whinham			pins = "gpio147";
1149*0d72ccaaSDale Whinham			function = "pcie4_clk";
1150*0d72ccaaSDale Whinham			drive-strength = <2>;
1151*0d72ccaaSDale Whinham			bias-pull-up;
1152*0d72ccaaSDale Whinham		};
1153*0d72ccaaSDale Whinham
1154*0d72ccaaSDale Whinham		perst-n-pins {
1155*0d72ccaaSDale Whinham			pins = "gpio146";
1156*0d72ccaaSDale Whinham			function = "gpio";
1157*0d72ccaaSDale Whinham			drive-strength = <2>;
1158*0d72ccaaSDale Whinham			bias-disable;
1159*0d72ccaaSDale Whinham		};
1160*0d72ccaaSDale Whinham
1161*0d72ccaaSDale Whinham		wake-n-pins {
1162*0d72ccaaSDale Whinham			pins = "gpio148";
1163*0d72ccaaSDale Whinham			function = "gpio";
1164*0d72ccaaSDale Whinham			drive-strength = <2>;
1165*0d72ccaaSDale Whinham			bias-pull-up;
1166*0d72ccaaSDale Whinham		};
1167*0d72ccaaSDale Whinham	};
1168*0d72ccaaSDale Whinham
1169*0d72ccaaSDale Whinham	pcie6a_default: pcie6a-default-state {
1170*0d72ccaaSDale Whinham		perst-n-pins {
1171*0d72ccaaSDale Whinham			pins = "gpio152";
1172*0d72ccaaSDale Whinham			function = "gpio";
1173*0d72ccaaSDale Whinham			drive-strength = <2>;
1174*0d72ccaaSDale Whinham			bias-disable;
1175*0d72ccaaSDale Whinham		};
1176*0d72ccaaSDale Whinham
1177*0d72ccaaSDale Whinham		clkreq-n-pins {
1178*0d72ccaaSDale Whinham			pins = "gpio153";
1179*0d72ccaaSDale Whinham			function = "pcie6a_clk";
1180*0d72ccaaSDale Whinham			drive-strength = <2>;
1181*0d72ccaaSDale Whinham			bias-pull-up;
1182*0d72ccaaSDale Whinham		};
1183*0d72ccaaSDale Whinham
1184*0d72ccaaSDale Whinham		wake-n-pins {
1185*0d72ccaaSDale Whinham			pins = "gpio154";
1186*0d72ccaaSDale Whinham			function = "gpio";
1187*0d72ccaaSDale Whinham			drive-strength = <2>;
1188*0d72ccaaSDale Whinham			bias-pull-up;
1189*0d72ccaaSDale Whinham		};
1190*0d72ccaaSDale Whinham	};
1191*0d72ccaaSDale Whinham
1192*0d72ccaaSDale Whinham	rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state {
1193*0d72ccaaSDale Whinham		pins = "gpio175";
1194*0d72ccaaSDale Whinham		function = "gpio";
1195*0d72ccaaSDale Whinham		drive-strength = <2>;
1196*0d72ccaaSDale Whinham		bias-disable;
1197*0d72ccaaSDale Whinham	};
1198*0d72ccaaSDale Whinham
1199*0d72ccaaSDale Whinham	rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state {
1200*0d72ccaaSDale Whinham		pins = "gpio186";
1201*0d72ccaaSDale Whinham		function = "gpio";
1202*0d72ccaaSDale Whinham		drive-strength = <2>;
1203*0d72ccaaSDale Whinham		bias-disable;
1204*0d72ccaaSDale Whinham	};
1205*0d72ccaaSDale Whinham
1206*0d72ccaaSDale Whinham	rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state {
1207*0d72ccaaSDale Whinham		pins = "gpio188";
1208*0d72ccaaSDale Whinham		function = "gpio";
1209*0d72ccaaSDale Whinham		drive-strength = <2>;
1210*0d72ccaaSDale Whinham		bias-disable;
1211*0d72ccaaSDale Whinham	};
1212*0d72ccaaSDale Whinham
1213*0d72ccaaSDale Whinham	wcn_sw_en: wcn-sw-en-state {
1214*0d72ccaaSDale Whinham		pins = "gpio214";
1215*0d72ccaaSDale Whinham		function = "gpio";
1216*0d72ccaaSDale Whinham		drive-strength = <2>;
1217*0d72ccaaSDale Whinham		bias-disable;
1218*0d72ccaaSDale Whinham	};
1219*0d72ccaaSDale Whinham
1220*0d72ccaaSDale Whinham	cam_indicator_en: cam-indicator-en-state {
1221*0d72ccaaSDale Whinham		pins = "gpio225";
1222*0d72ccaaSDale Whinham		function = "gpio";
1223*0d72ccaaSDale Whinham		drive-strength = <2>;
1224*0d72ccaaSDale Whinham		bias-disable;
1225*0d72ccaaSDale Whinham	};
1226*0d72ccaaSDale Whinham};
1227*0d72ccaaSDale Whinham
1228*0d72ccaaSDale Whinham&uart2 {
1229*0d72ccaaSDale Whinham	status = "okay";
1230*0d72ccaaSDale Whinham
1231*0d72ccaaSDale Whinham	embedded-controller {
1232*0d72ccaaSDale Whinham		compatible = "microsoft,surface-sam";
1233*0d72ccaaSDale Whinham
1234*0d72ccaaSDale Whinham		interrupts-extended = <&tlmm 91 IRQ_TYPE_EDGE_RISING>;
1235*0d72ccaaSDale Whinham
1236*0d72ccaaSDale Whinham		current-speed = <4000000>;
1237*0d72ccaaSDale Whinham
1238*0d72ccaaSDale Whinham		pinctrl-0 = <&ssam_state>;
1239*0d72ccaaSDale Whinham		pinctrl-names = "default";
1240*0d72ccaaSDale Whinham	};
1241*0d72ccaaSDale Whinham};
1242*0d72ccaaSDale Whinham
1243*0d72ccaaSDale Whinham&uart14 {
1244*0d72ccaaSDale Whinham	status = "okay";
1245*0d72ccaaSDale Whinham
1246*0d72ccaaSDale Whinham	bluetooth {
1247*0d72ccaaSDale Whinham		compatible = "qcom,wcn7850-bt";
1248*0d72ccaaSDale Whinham		max-speed = <3200000>;
1249*0d72ccaaSDale Whinham
1250*0d72ccaaSDale Whinham		vddaon-supply = <&vreg_pmu_aon_0p59>;
1251*0d72ccaaSDale Whinham		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
1252*0d72ccaaSDale Whinham		vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
1253*0d72ccaaSDale Whinham		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
1254*0d72ccaaSDale Whinham		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
1255*0d72ccaaSDale Whinham		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
1256*0d72ccaaSDale Whinham		vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
1257*0d72ccaaSDale Whinham	};
1258*0d72ccaaSDale Whinham};
1259*0d72ccaaSDale Whinham
1260*0d72ccaaSDale Whinham&usb_1_ss0_hsphy {
1261*0d72ccaaSDale Whinham	vdd-supply = <&vreg_l3j_0p8>;
1262*0d72ccaaSDale Whinham	vdda12-supply = <&vreg_l2j_1p2>;
1263*0d72ccaaSDale Whinham
1264*0d72ccaaSDale Whinham	phys = <&smb2360_0_eusb2_repeater>;
1265*0d72ccaaSDale Whinham
1266*0d72ccaaSDale Whinham	status = "okay";
1267*0d72ccaaSDale Whinham};
1268*0d72ccaaSDale Whinham
1269*0d72ccaaSDale Whinham&usb_1_ss0_qmpphy {
1270*0d72ccaaSDale Whinham	vdda-phy-supply = <&vreg_l2j_1p2>;
1271*0d72ccaaSDale Whinham	vdda-pll-supply = <&vreg_l1j_0p8>;
1272*0d72ccaaSDale Whinham
1273*0d72ccaaSDale Whinham	status = "okay";
1274*0d72ccaaSDale Whinham};
1275*0d72ccaaSDale Whinham
1276*0d72ccaaSDale Whinham&usb_1_ss0 {
1277*0d72ccaaSDale Whinham	status = "okay";
1278*0d72ccaaSDale Whinham};
1279*0d72ccaaSDale Whinham
1280*0d72ccaaSDale Whinham&usb_1_ss0_dwc3 {
1281*0d72ccaaSDale Whinham	dr_mode = "host";
1282*0d72ccaaSDale Whinham};
1283*0d72ccaaSDale Whinham
1284*0d72ccaaSDale Whinham&usb_1_ss0_dwc3_hs {
1285*0d72ccaaSDale Whinham	remote-endpoint = <&pmic_glink_ss0_hs_in>;
1286*0d72ccaaSDale Whinham};
1287*0d72ccaaSDale Whinham
1288*0d72ccaaSDale Whinham&usb_1_ss0_qmpphy_out {
1289*0d72ccaaSDale Whinham	remote-endpoint = <&retimer_ss0_ss_in>;
1290*0d72ccaaSDale Whinham};
1291*0d72ccaaSDale Whinham
1292*0d72ccaaSDale Whinham&usb_1_ss1_hsphy {
1293*0d72ccaaSDale Whinham	vdd-supply = <&vreg_l3j_0p8>;
1294*0d72ccaaSDale Whinham	vdda12-supply = <&vreg_l2j_1p2>;
1295*0d72ccaaSDale Whinham
1296*0d72ccaaSDale Whinham	phys = <&smb2360_1_eusb2_repeater>;
1297*0d72ccaaSDale Whinham
1298*0d72ccaaSDale Whinham	status = "okay";
1299*0d72ccaaSDale Whinham};
1300*0d72ccaaSDale Whinham
1301*0d72ccaaSDale Whinham&usb_1_ss1_qmpphy {
1302*0d72ccaaSDale Whinham	vdda-phy-supply = <&vreg_l2j_1p2>;
1303*0d72ccaaSDale Whinham	vdda-pll-supply = <&vreg_l2d_0p9>;
1304*0d72ccaaSDale Whinham
1305*0d72ccaaSDale Whinham	status = "okay";
1306*0d72ccaaSDale Whinham};
1307*0d72ccaaSDale Whinham
1308*0d72ccaaSDale Whinham&usb_1_ss1 {
1309*0d72ccaaSDale Whinham	status = "okay";
1310*0d72ccaaSDale Whinham};
1311*0d72ccaaSDale Whinham
1312*0d72ccaaSDale Whinham&usb_1_ss1_dwc3 {
1313*0d72ccaaSDale Whinham	dr_mode = "host";
1314*0d72ccaaSDale Whinham};
1315*0d72ccaaSDale Whinham
1316*0d72ccaaSDale Whinham&usb_1_ss1_dwc3_hs {
1317*0d72ccaaSDale Whinham	remote-endpoint = <&pmic_glink_ss1_hs_in>;
1318*0d72ccaaSDale Whinham};
1319*0d72ccaaSDale Whinham
1320*0d72ccaaSDale Whinham&usb_1_ss1_qmpphy_out {
1321*0d72ccaaSDale Whinham	remote-endpoint = <&retimer_ss1_ss_in>;
1322*0d72ccaaSDale Whinham};
1323