1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,qcs615-camcc.h> 8#include <dt-bindings/clock/qcom,qcs615-dispcc.h> 9#include <dt-bindings/clock/qcom,qcs615-gcc.h> 10#include <dt-bindings/clock/qcom,qcs615-gpucc.h> 11#include <dt-bindings/clock/qcom,qcs615-videocc.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 cpus { 30 #address-cells = <2>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a55"; 36 reg = <0x0 0x0>; 37 enable-method = "psci"; 38 power-domains = <&cpu_pd0>; 39 power-domain-names = "psci"; 40 capacity-dmips-mhz = <1024>; 41 dynamic-power-coefficient = <100>; 42 next-level-cache = <&l2_0>; 43 clocks = <&cpufreq_hw 0>; 44 qcom,freq-domain = <&cpufreq_hw 0>; 45 #cooling-cells = <2>; 46 operating-points-v2 = <&cpu0_opp_table>; 47 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 48 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 49 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 50 51 l2_0: l2-cache { 52 compatible = "cache"; 53 cache-level = <2>; 54 cache-unified; 55 next-level-cache = <&l3_0>; 56 }; 57 }; 58 59 cpu1: cpu@100 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a55"; 62 reg = <0x0 0x100>; 63 enable-method = "psci"; 64 power-domains = <&cpu_pd1>; 65 power-domain-names = "psci"; 66 capacity-dmips-mhz = <1024>; 67 dynamic-power-coefficient = <100>; 68 next-level-cache = <&l2_100>; 69 clocks = <&cpufreq_hw 0>; 70 qcom,freq-domain = <&cpufreq_hw 0>; 71 operating-points-v2 = <&cpu0_opp_table>; 72 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 73 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 74 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 75 76 l2_100: l2-cache { 77 compatible = "cache"; 78 cache-level = <2>; 79 cache-unified; 80 next-level-cache = <&l3_0>; 81 }; 82 }; 83 84 cpu2: cpu@200 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a55"; 87 reg = <0x0 0x200>; 88 enable-method = "psci"; 89 power-domains = <&cpu_pd2>; 90 power-domain-names = "psci"; 91 capacity-dmips-mhz = <1024>; 92 dynamic-power-coefficient = <100>; 93 next-level-cache = <&l2_200>; 94 clocks = <&cpufreq_hw 0>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 operating-points-v2 = <&cpu0_opp_table>; 97 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 98 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 99 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 100 101 l2_200: l2-cache { 102 compatible = "cache"; 103 cache-level = <2>; 104 cache-unified; 105 next-level-cache = <&l3_0>; 106 }; 107 }; 108 109 cpu3: cpu@300 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a55"; 112 reg = <0x0 0x300>; 113 enable-method = "psci"; 114 power-domains = <&cpu_pd3>; 115 power-domain-names = "psci"; 116 capacity-dmips-mhz = <1024>; 117 dynamic-power-coefficient = <100>; 118 next-level-cache = <&l2_300>; 119 clocks = <&cpufreq_hw 0>; 120 qcom,freq-domain = <&cpufreq_hw 0>; 121 operating-points-v2 = <&cpu0_opp_table>; 122 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 123 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 124 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 125 126 l2_300: l2-cache { 127 compatible = "cache"; 128 cache-level = <2>; 129 cache-unified; 130 next-level-cache = <&l3_0>; 131 }; 132 }; 133 134 cpu4: cpu@400 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a55"; 137 reg = <0x0 0x400>; 138 enable-method = "psci"; 139 power-domains = <&cpu_pd4>; 140 power-domain-names = "psci"; 141 capacity-dmips-mhz = <1024>; 142 dynamic-power-coefficient = <100>; 143 next-level-cache = <&l2_400>; 144 clocks = <&cpufreq_hw 0>; 145 qcom,freq-domain = <&cpufreq_hw 0>; 146 operating-points-v2 = <&cpu0_opp_table>; 147 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 148 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 149 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 150 151 l2_400: l2-cache { 152 compatible = "cache"; 153 cache-level = <2>; 154 cache-unified; 155 next-level-cache = <&l3_0>; 156 }; 157 }; 158 159 cpu5: cpu@500 { 160 device_type = "cpu"; 161 compatible = "arm,cortex-a55"; 162 reg = <0x0 0x500>; 163 enable-method = "psci"; 164 power-domains = <&cpu_pd5>; 165 power-domain-names = "psci"; 166 capacity-dmips-mhz = <1024>; 167 dynamic-power-coefficient = <100>; 168 next-level-cache = <&l2_500>; 169 clocks = <&cpufreq_hw 0>; 170 qcom,freq-domain = <&cpufreq_hw 0>; 171 operating-points-v2 = <&cpu0_opp_table>; 172 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 173 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 174 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 175 176 l2_500: l2-cache { 177 compatible = "cache"; 178 cache-level = <2>; 179 cache-unified; 180 next-level-cache = <&l3_0>; 181 }; 182 }; 183 184 cpu6: cpu@600 { 185 device_type = "cpu"; 186 compatible = "arm,cortex-a76"; 187 reg = <0x0 0x600>; 188 enable-method = "psci"; 189 power-domains = <&cpu_pd6>; 190 power-domain-names = "psci"; 191 capacity-dmips-mhz = <1740>; 192 dynamic-power-coefficient = <404>; 193 next-level-cache = <&l2_600>; 194 clocks = <&cpufreq_hw 1>; 195 qcom,freq-domain = <&cpufreq_hw 1>; 196 #cooling-cells = <2>; 197 operating-points-v2 = <&cpu6_opp_table>; 198 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 199 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 200 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 201 202 l2_600: l2-cache { 203 compatible = "cache"; 204 cache-level = <2>; 205 cache-unified; 206 next-level-cache = <&l3_0>; 207 }; 208 }; 209 210 cpu7: cpu@700 { 211 device_type = "cpu"; 212 compatible = "arm,cortex-a76"; 213 reg = <0x0 0x700>; 214 enable-method = "psci"; 215 power-domains = <&cpu_pd7>; 216 power-domain-names = "psci"; 217 capacity-dmips-mhz = <1740>; 218 dynamic-power-coefficient = <404>; 219 next-level-cache = <&l2_700>; 220 clocks = <&cpufreq_hw 1>; 221 qcom,freq-domain = <&cpufreq_hw 1>; 222 operating-points-v2 = <&cpu6_opp_table>; 223 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 224 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 225 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 226 227 l2_700: l2-cache { 228 compatible = "cache"; 229 cache-level = <2>; 230 cache-unified; 231 next-level-cache = <&l3_0>; 232 }; 233 }; 234 235 cpu-map { 236 cluster0 { 237 core0 { 238 cpu = <&cpu0>; 239 }; 240 241 core1 { 242 cpu = <&cpu1>; 243 }; 244 245 core2 { 246 cpu = <&cpu2>; 247 }; 248 249 core3 { 250 cpu = <&cpu3>; 251 }; 252 253 core4 { 254 cpu = <&cpu4>; 255 }; 256 257 core5 { 258 cpu = <&cpu5>; 259 }; 260 261 core6 { 262 cpu = <&cpu6>; 263 }; 264 265 core7 { 266 cpu = <&cpu7>; 267 }; 268 }; 269 }; 270 271 l3_0: l3-cache { 272 compatible = "cache"; 273 cache-level = <3>; 274 cache-unified; 275 }; 276 }; 277 278 cpu0_opp_table: opp-table-cpu0 { 279 compatible = "operating-points-v2"; 280 opp-shared; 281 282 opp-300000000 { 283 opp-hz = /bits/ 64 <300000000>; 284 opp-peak-kBps = <(300000 * 4) (300000 * 16)>; 285 }; 286 287 opp-576000000 { 288 opp-hz = /bits/ 64 <576000000>; 289 opp-peak-kBps = <(300000 * 4) (576000 * 16)>; 290 }; 291 292 opp-748800000 { 293 opp-hz = /bits/ 64 <748800000>; 294 opp-peak-kBps = <(300000 * 4) (576000 * 16)>; 295 }; 296 297 opp-998400000 { 298 opp-hz = /bits/ 64 <998400000>; 299 opp-peak-kBps = <(451000 * 4) (806400 * 16)>; 300 }; 301 302 opp-1209600000 { 303 opp-hz = /bits/ 64 <1209600000>; 304 opp-peak-kBps = <(547000 * 4) (1017600 * 16)>; 305 }; 306 307 opp-1363200000 { 308 opp-hz = /bits/ 64 <1363200000>; 309 opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; 310 }; 311 312 opp-1516800000 { 313 opp-hz = /bits/ 64 <1516800000>; 314 opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; 315 }; 316 317 opp-1593600000 { 318 opp-hz = /bits/ 64 <1593600000>; 319 opp-peak-kBps = <(1017000 * 4) (1363200 * 16)>; 320 }; 321 }; 322 323 cpu6_opp_table: opp-table-cpu6 { 324 compatible = "operating-points-v2"; 325 opp-shared; 326 327 opp-300000000 { 328 opp-hz = /bits/ 64 <300000000>; 329 opp-peak-kBps = <(451000 * 4) (300000 * 16)>; 330 }; 331 332 opp-652800000 { 333 opp-hz = /bits/ 64 <652800000>; 334 opp-peak-kBps = <(451000 * 4) (576000 * 16)>; 335 }; 336 337 opp-768000000 { 338 opp-hz = /bits/ 64 <768000000>; 339 opp-peak-kBps = <(451000 * 4) (576000 * 16)>; 340 }; 341 342 opp-979200000 { 343 opp-hz = /bits/ 64 <979200000>; 344 opp-peak-kBps = <(547000 * 4) (806400 * 16)>; 345 }; 346 347 opp-1017600000 { 348 opp-hz = /bits/ 64 <1017600000>; 349 opp-peak-kBps = <(547000 * 4) (806400 * 16)>; 350 }; 351 352 opp-1094400000 { 353 opp-hz = /bits/ 64 <109440000>; 354 opp-peak-kBps = <(1017600 * 4) (940800 * 16)>; 355 }; 356 357 opp-1209600000 { 358 opp-hz = /bits/ 64 <1209600000>; 359 opp-peak-kBps = <(1017600 * 4) (1017600 * 16)>; 360 }; 361 362 opp-1363200000 { 363 opp-hz = /bits/ 64 <1363200000>; 364 opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; 365 }; 366 367 opp-1516800000 { 368 opp-hz = /bits/ 64 <1516800000>; 369 opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; 370 }; 371 372 opp-1708800000 { 373 opp-hz = /bits/ 64 <1708800000>; 374 opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; 375 }; 376 377 opp-1900800000 { 378 opp-hz = /bits/ 64 <1900800000>; 379 opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; 380 }; 381 }; 382 383 dummy_eud: dummy-sink { 384 compatible = "arm,coresight-dummy-sink"; 385 386 in-ports { 387 port { 388 eud_in: endpoint { 389 remote-endpoint = <&replicator_swao_out1>; 390 }; 391 }; 392 }; 393 }; 394 395 idle-states { 396 entry-method = "psci"; 397 398 little_cpu_sleep_0: cpu-sleep-0-0 { 399 compatible = "arm,idle-state"; 400 idle-state-name = "silver-power-collapse"; 401 arm,psci-suspend-param = <0x40000003>; 402 entry-latency-us = <549>; 403 exit-latency-us = <901>; 404 min-residency-us = <1774>; 405 local-timer-stop; 406 }; 407 408 little_cpu_sleep_1: cpu-sleep-0-1 { 409 compatible = "arm,idle-state"; 410 idle-state-name = "silver-rail-power-collapse"; 411 arm,psci-suspend-param = <0x40000004>; 412 entry-latency-us = <702>; 413 exit-latency-us = <915>; 414 min-residency-us = <4001>; 415 local-timer-stop; 416 }; 417 418 big_cpu_sleep_0: cpu-sleep-1-0 { 419 compatible = "arm,idle-state"; 420 idle-state-name = "gold-power-collapse"; 421 arm,psci-suspend-param = <0x40000003>; 422 entry-latency-us = <523>; 423 exit-latency-us = <1244>; 424 min-residency-us = <2207>; 425 local-timer-stop; 426 }; 427 428 big_cpu_sleep_1: cpu-sleep-1-1 { 429 compatible = "arm,idle-state"; 430 idle-state-name = "gold-rail-power-collapse"; 431 arm,psci-suspend-param = <0x40000004>; 432 entry-latency-us = <526>; 433 exit-latency-us = <1854>; 434 min-residency-us = <5555>; 435 local-timer-stop; 436 }; 437 }; 438 439 domain-idle-states { 440 cluster_sleep_0: cluster-sleep-0 { 441 compatible = "domain-idle-state"; 442 arm,psci-suspend-param = <0x41000044>; 443 entry-latency-us = <2752>; 444 exit-latency-us = <3048>; 445 min-residency-us = <6118>; 446 }; 447 448 cluster_sleep_1: cluster-sleep-1 { 449 compatible = "domain-idle-state"; 450 arm,psci-suspend-param = <0x41001344>; 451 entry-latency-us = <3263>; 452 exit-latency-us = <4562>; 453 min-residency-us = <8467>; 454 }; 455 456 cluster_sleep_2: cluster-sleep-2 { 457 compatible = "domain-idle-state"; 458 arm,psci-suspend-param = <0x4100b344>; 459 entry-latency-us = <3638>; 460 exit-latency-us = <6562>; 461 min-residency-us = <9826>; 462 }; 463 }; 464 465 memory@80000000 { 466 device_type = "memory"; 467 /* We expect the bootloader to fill in the size */ 468 reg = <0 0x80000000 0 0>; 469 }; 470 471 firmware { 472 scm { 473 compatible = "qcom,scm-qcs615", "qcom,scm"; 474 qcom,dload-mode = <&tcsr 0x13000>; 475 }; 476 }; 477 478 camnoc_virt: interconnect-0 { 479 compatible = "qcom,qcs615-camnoc-virt"; 480 #interconnect-cells = <2>; 481 qcom,bcm-voters = <&apps_bcm_voter>; 482 }; 483 484 mc_virt: interconnect-2 { 485 compatible = "qcom,qcs615-mc-virt"; 486 #interconnect-cells = <2>; 487 qcom,bcm-voters = <&apps_bcm_voter>; 488 }; 489 490 smp2p-adsp { 491 compatible = "qcom,smp2p"; 492 qcom,smem = <443>, <429>; 493 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING 0>; 494 /* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */ 495 mboxes = <&apss_shared 26>; 496 497 qcom,local-pid = <0>; 498 qcom,remote-pid = <2>; 499 500 adsp_smp2p_out: master-kernel { 501 qcom,entry-name = "master-kernel"; 502 #qcom,smem-state-cells = <1>; 503 }; 504 505 adsp_smp2p_in: slave-kernel { 506 qcom,entry-name = "slave-kernel"; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 }; 510 }; 511 512 smp2p-cdsp { 513 compatible = "qcom,smp2p"; 514 qcom,smem = <94>, <432>; 515 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING 0>; 516 mboxes = <&apss_shared 6>; 517 518 qcom,local-pid = <0>; 519 qcom,remote-pid = <5>; 520 521 cdsp_smp2p_out: master-kernel { 522 qcom,entry-name = "master-kernel"; 523 #qcom,smem-state-cells = <1>; 524 }; 525 526 cdsp_smp2p_in: slave-kernel { 527 qcom,entry-name = "slave-kernel"; 528 interrupt-controller; 529 #interrupt-cells = <2>; 530 }; 531 532 }; 533 534 qup_opp_table: opp-table-qup { 535 compatible = "operating-points-v2"; 536 537 opp-75000000 { 538 opp-hz = /bits/ 64 <75000000>; 539 required-opps = <&rpmhpd_opp_low_svs>; 540 }; 541 542 opp-100000000 { 543 opp-hz = /bits/ 64 <100000000>; 544 required-opps = <&rpmhpd_opp_svs>; 545 }; 546 547 opp-128000000 { 548 opp-hz = /bits/ 64 <128000000>; 549 required-opps = <&rpmhpd_opp_nom>; 550 }; 551 }; 552 553 pmu-a55 { 554 compatible = "arm,cortex-a55-pmu"; 555 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 556 }; 557 558 pmu-a76 { 559 compatible = "arm,cortex-a76-pmu"; 560 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 561 }; 562 563 psci { 564 compatible = "arm,psci-1.0"; 565 method = "smc"; 566 567 cpu_pd0: power-domain-cpu0 { 568 #power-domain-cells = <0>; 569 power-domains = <&cluster_pd>; 570 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 571 }; 572 573 cpu_pd1: power-domain-cpu1 { 574 #power-domain-cells = <0>; 575 power-domains = <&cluster_pd>; 576 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 577 }; 578 579 cpu_pd2: power-domain-cpu2 { 580 #power-domain-cells = <0>; 581 power-domains = <&cluster_pd>; 582 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 583 }; 584 585 cpu_pd3: power-domain-cpu3 { 586 #power-domain-cells = <0>; 587 power-domains = <&cluster_pd>; 588 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 589 }; 590 591 cpu_pd4: power-domain-cpu4 { 592 #power-domain-cells = <0>; 593 power-domains = <&cluster_pd>; 594 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 595 }; 596 597 cpu_pd5: power-domain-cpu5 { 598 #power-domain-cells = <0>; 599 power-domains = <&cluster_pd>; 600 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 601 }; 602 603 cpu_pd6: power-domain-cpu6 { 604 #power-domain-cells = <0>; 605 power-domains = <&cluster_pd>; 606 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 607 }; 608 609 cpu_pd7: power-domain-cpu7 { 610 #power-domain-cells = <0>; 611 power-domains = <&cluster_pd>; 612 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 613 }; 614 615 cluster_pd: power-domain-cluster { 616 #power-domain-cells = <0>; 617 domain-idle-states = <&cluster_sleep_0 618 &cluster_sleep_1 619 &cluster_sleep_2>; 620 }; 621 }; 622 623 reserved-memory { 624 #address-cells = <2>; 625 #size-cells = <2>; 626 ranges; 627 628 aop_cmd_db_mem: aop-cmd-db@85f20000 { 629 compatible = "qcom,cmd-db"; 630 reg = <0x0 0x85f20000 0x0 0x20000>; 631 no-map; 632 }; 633 634 smem_region: smem@86000000 { 635 compatible = "qcom,smem"; 636 reg = <0x0 0x86000000 0x0 0x200000>; 637 no-map; 638 hwlocks = <&tcsr_mutex 3>; 639 }; 640 641 pil_video_mem: pil-video@93400000 { 642 reg = <0x0 0x93400000 0x0 0x500000>; 643 no-map; 644 }; 645 646 rproc_cdsp_mem: rproc-cdsp@93b00000 { 647 reg = <0x0 0x93b00000 0x0 0x1e00000>; 648 no-map; 649 }; 650 651 rproc_adsp_mem: rproc-adsp@95900000 { 652 reg = <0x0 0x95900000 0x0 0x1e00000>; 653 no-map; 654 }; 655 656 pil_gpu_mem: pil-gpu@97715000 { 657 reg = <0x0 0x97715000 0x0 0x2000>; 658 no-map; 659 }; 660 }; 661 662 soc: soc@0 { 663 compatible = "simple-bus"; 664 ranges = <0 0 0 0 0x10 0>; 665 dma-ranges = <0 0 0 0 0x10 0>; 666 #address-cells = <2>; 667 #size-cells = <2>; 668 669 gcc: clock-controller@100000 { 670 compatible = "qcom,qcs615-gcc"; 671 reg = <0 0x00100000 0 0x1f0000>; 672 clocks = <&rpmhcc RPMH_CXO_CLK>, 673 <&rpmhcc RPMH_CXO_CLK_A>, 674 <&sleep_clk>; 675 clock-names = "bi_tcxo", 676 "bi_tcxo_ao", 677 "sleep_clk"; 678 679 #clock-cells = <1>; 680 #reset-cells = <1>; 681 #power-domain-cells = <1>; 682 }; 683 684 qfprom: efuse@780000 { 685 compatible = "qcom,qcs615-qfprom", "qcom,qfprom"; 686 reg = <0x0 0x00780000 0x0 0x7000>; 687 #address-cells = <1>; 688 #size-cells = <1>; 689 690 qusb2_hstx_trim: hstx-trim@1f8 { 691 reg = <0x1fb 0x1>; 692 bits = <1 4>; 693 }; 694 }; 695 696 rng@793000 { 697 compatible = "qcom,qcs615-trng", "qcom,trng"; 698 reg = <0x0 0x00793000 0x0 0x1000>; 699 }; 700 701 sdhc_1: mmc@7c4000 { 702 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 703 reg = <0x0 0x007c4000 0x0 0x1000>, 704 <0x0 0x007c5000 0x0 0x1000>, 705 <0x0 0x007c8000 0x0 0x8000>; 706 reg-names = "hc", 707 "cqhci", 708 "ice"; 709 710 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>, 711 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 712 interrupt-names = "hc_irq", 713 "pwr_irq"; 714 715 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 716 <&gcc GCC_SDCC1_APPS_CLK>, 717 <&rpmhcc RPMH_CXO_CLK>, 718 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 719 clock-names = "iface", 720 "core", 721 "xo", 722 "ice"; 723 724 resets = <&gcc GCC_SDCC1_BCR>; 725 726 power-domains = <&rpmhpd RPMHPD_CX>; 727 operating-points-v2 = <&sdhc1_opp_table>; 728 iommus = <&apps_smmu 0x02c0 0x0>; 729 interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS 730 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 731 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 732 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 733 interconnect-names = "sdhc-ddr", 734 "cpu-sdhc"; 735 736 qcom,dll-config = <0x000f642c>; 737 qcom,ddr-config = <0x80040868>; 738 supports-cqe; 739 dma-coherent; 740 741 status = "disabled"; 742 743 sdhc1_opp_table: opp-table { 744 compatible = "operating-points-v2"; 745 746 opp-50000000 { 747 opp-hz = /bits/ 64 <50000000>; 748 required-opps = <&rpmhpd_opp_low_svs>; 749 }; 750 751 opp-100000000 { 752 opp-hz = /bits/ 64 <100000000>; 753 required-opps = <&rpmhpd_opp_svs>; 754 }; 755 756 opp-200000000 { 757 opp-hz = /bits/ 64 <200000000>; 758 required-opps = <&rpmhpd_opp_svs_l1>; 759 }; 760 761 opp-384000000 { 762 opp-hz = /bits/ 64 <384000000>; 763 required-opps = <&rpmhpd_opp_nom>; 764 }; 765 }; 766 }; 767 768 gpi_dma0: dma-controller@800000 { 769 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 770 reg = <0x0 0x800000 0x0 0x60000>; 771 #dma-cells = <3>; 772 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>, 773 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 774 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 775 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 776 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 777 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>, 778 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 779 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 780 dma-channels = <8>; 781 dma-channel-mask = <0xf>; 782 iommus = <&apps_smmu 0xd6 0x0>; 783 status = "disabled"; 784 }; 785 786 qupv3_id_0: geniqup@8c0000 { 787 compatible = "qcom,geni-se-qup"; 788 reg = <0x0 0x008c0000 0x0 0x6000>; 789 ranges; 790 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 791 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 792 clock-names = "m-ahb", 793 "s-ahb"; 794 iommus = <&apps_smmu 0xc3 0x0>; 795 #address-cells = <2>; 796 #size-cells = <2>; 797 status = "disabled"; 798 799 uart0: serial@880000 { 800 compatible = "qcom,geni-debug-uart"; 801 reg = <0x0 0x00880000 0x0 0x4000>; 802 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 803 clock-names = "se"; 804 pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>; 805 pinctrl-names = "default"; 806 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH 0>; 807 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 808 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 809 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 810 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 811 interconnect-names = "qup-core", 812 "qup-config"; 813 power-domains = <&rpmhpd RPMHPD_CX>; 814 operating-points-v2 = <&qup_opp_table>; 815 status = "disabled"; 816 }; 817 818 i2c1: i2c@884000 { 819 compatible = "qcom,geni-i2c"; 820 reg = <0x0 0x884000 0x0 0x4000>; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH 0>; 824 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 825 clock-names = "se"; 826 pinctrl-0 = <&qup_i2c1_data_clk>; 827 pinctrl-names = "default"; 828 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 829 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 830 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 831 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 832 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 833 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 834 interconnect-names = "qup-core", 835 "qup-config", 836 "qup-memory"; 837 power-domains = <&rpmhpd RPMHPD_CX>; 838 required-opps = <&rpmhpd_opp_low_svs>; 839 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 840 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 841 dma-names = "tx", 842 "rx"; 843 status = "disabled"; 844 }; 845 846 i2c2: i2c@888000 { 847 compatible = "qcom,geni-i2c"; 848 reg = <0x0 0x888000 0x0 0x4000>; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>; 852 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 853 clock-names = "se"; 854 pinctrl-0 = <&qup_i2c2_data_clk>; 855 pinctrl-names = "default"; 856 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 857 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 858 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 859 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 860 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 861 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 862 interconnect-names = "qup-core", 863 "qup-config", 864 "qup-memory"; 865 power-domains = <&rpmhpd RPMHPD_CX>; 866 required-opps = <&rpmhpd_opp_low_svs>; 867 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 868 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 869 dma-names = "tx", 870 "rx"; 871 status = "disabled"; 872 }; 873 874 spi2: spi@888000 { 875 compatible = "qcom,geni-spi"; 876 reg = <0x0 0x00888000 0x0 0x4000>; 877 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>; 878 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 879 clock-names = "se"; 880 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 881 pinctrl-names = "default"; 882 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 883 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 884 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 885 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 886 interconnect-names = "qup-core", 887 "qup-config"; 888 power-domains = <&rpmhpd RPMHPD_CX>; 889 operating-points-v2 = <&qup_opp_table>; 890 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 891 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 892 dma-names = "tx", 893 "rx"; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 status = "disabled"; 897 }; 898 899 uart2: serial@888000 { 900 compatible = "qcom,geni-uart"; 901 reg = <0x0 0x00888000 0x0 0x4000>; 902 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>; 903 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 904 clock-names = "se"; 905 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 906 <&qup_uart2_tx>, <&qup_uart2_rx>; 907 pinctrl-names = "default"; 908 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 909 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 910 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 911 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 912 interconnect-names = "qup-core", 913 "qup-config"; 914 power-domains = <&rpmhpd RPMHPD_CX>; 915 operating-points-v2 = <&qup_opp_table>; 916 status = "disabled"; 917 }; 918 919 i2c3: i2c@88c000 { 920 compatible = "qcom,geni-i2c"; 921 reg = <0x0 0x88c000 0x0 0x4000>; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>; 925 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 926 clock-names = "se"; 927 pinctrl-0 = <&qup_i2c3_data_clk>; 928 pinctrl-names = "default"; 929 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 930 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 931 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 932 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 933 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 934 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 935 interconnect-names = "qup-core", 936 "qup-config", 937 "qup-memory"; 938 power-domains = <&rpmhpd RPMHPD_CX>; 939 required-opps = <&rpmhpd_opp_low_svs>; 940 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 941 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 942 dma-names = "tx", 943 "rx"; 944 status = "disabled"; 945 }; 946 }; 947 948 gpi_dma1: dma-controller@a00000 { 949 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 950 reg = <0x0 0xa00000 0x0 0x60000>; 951 #dma-cells = <3>; 952 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>, 953 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>, 954 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>, 955 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>, 956 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>, 957 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>, 958 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>, 959 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 960 dma-channels = <8>; 961 dma-channel-mask = <0xf>; 962 iommus = <&apps_smmu 0x376 0x0>; 963 status = "disabled"; 964 }; 965 966 qupv3_id_1: geniqup@ac0000 { 967 compatible = "qcom,geni-se-qup"; 968 reg = <0x0 0xac0000 0x0 0x2000>; 969 ranges; 970 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 971 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 972 clock-names = "m-ahb", 973 "s-ahb"; 974 iommus = <&apps_smmu 0x363 0x0>; 975 #address-cells = <2>; 976 #size-cells = <2>; 977 status = "disabled"; 978 979 i2c4: i2c@a80000 { 980 compatible = "qcom,geni-i2c"; 981 reg = <0x0 0xa80000 0x0 0x4000>; 982 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 983 clock-names = "se"; 984 pinctrl-0 = <&qup_i2c4_data_clk>; 985 pinctrl-names = "default"; 986 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 990 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 991 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 992 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 993 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 994 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 995 interconnect-names = "qup-core", 996 "qup-config", 997 "qup-memory"; 998 power-domains = <&rpmhpd RPMHPD_CX>; 999 required-opps = <&rpmhpd_opp_low_svs>; 1000 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1001 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1002 dma-names = "tx", 1003 "rx"; 1004 status = "disabled"; 1005 }; 1006 1007 spi4: spi@a80000 { 1008 compatible = "qcom,geni-spi"; 1009 reg = <0x0 0xa80000 0x0 0x4000>; 1010 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1011 clock-names = "se"; 1012 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1013 pinctrl-names = "default"; 1014 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1018 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1019 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1020 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1021 interconnect-names = "qup-core", 1022 "qup-config"; 1023 power-domains = <&rpmhpd RPMHPD_CX>; 1024 operating-points-v2 = <&qup_opp_table>; 1025 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1026 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1027 dma-names = "tx", 1028 "rx"; 1029 status = "disabled"; 1030 }; 1031 1032 uart4: serial@a80000 { 1033 compatible = "qcom,geni-uart"; 1034 reg = <0x0 0xa80000 0x0 0x4000>; 1035 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1036 clock-names = "se"; 1037 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 1038 <&qup_uart4_tx>, <&qup_uart4_rx>; 1039 pinctrl-names = "default"; 1040 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1041 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1042 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1043 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1044 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1045 interconnect-names = "qup-core", 1046 "qup-config"; 1047 power-domains = <&rpmhpd RPMHPD_CX>; 1048 operating-points-v2 = <&qup_opp_table>; 1049 status = "disabled"; 1050 }; 1051 1052 i2c5: i2c@a84000 { 1053 compatible = "qcom,geni-i2c"; 1054 reg = <0x0 0xa84000 0x0 0x4000>; 1055 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1056 clock-names = "se"; 1057 pinctrl-0 = <&qup_i2c5_data_clk>; 1058 pinctrl-names = "default"; 1059 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1063 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1064 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1065 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1066 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1067 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1068 interconnect-names = "qup-core", 1069 "qup-config", 1070 "qup-memory"; 1071 power-domains = <&rpmhpd RPMHPD_CX>; 1072 required-opps = <&rpmhpd_opp_low_svs>; 1073 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1074 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1075 dma-names = "tx", 1076 "rx"; 1077 status = "disabled"; 1078 }; 1079 1080 i2c6: i2c@a88000 { 1081 compatible = "qcom,geni-i2c"; 1082 reg = <0x0 0xa88000 0x0 0x4000>; 1083 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1084 clock-names = "se"; 1085 pinctrl-0 = <&qup_i2c6_data_clk>; 1086 pinctrl-names = "default"; 1087 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1091 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1092 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1093 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1094 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1095 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1096 interconnect-names = "qup-core", 1097 "qup-config", 1098 "qup-memory"; 1099 power-domains = <&rpmhpd RPMHPD_CX>; 1100 required-opps = <&rpmhpd_opp_low_svs>; 1101 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1102 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1103 dma-names = "tx", 1104 "rx"; 1105 status = "disabled"; 1106 }; 1107 1108 spi6: spi@a88000 { 1109 compatible = "qcom,geni-spi"; 1110 reg = <0x0 0xa88000 0x0 0x4000>; 1111 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1112 clock-names = "se"; 1113 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1114 pinctrl-names = "default"; 1115 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1119 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1120 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1121 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1122 interconnect-names = "qup-core", 1123 "qup-config"; 1124 power-domains = <&rpmhpd RPMHPD_CX>; 1125 operating-points-v2 = <&qup_opp_table>; 1126 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1127 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1128 dma-names = "tx", 1129 "rx"; 1130 status = "disabled"; 1131 }; 1132 1133 uart6: serial@a88000 { 1134 compatible = "qcom,geni-uart"; 1135 reg = <0x0 0xa88000 0x0 0x4000>; 1136 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1137 clock-names = "se"; 1138 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 1139 <&qup_uart6_tx>, <&qup_uart6_rx>; 1140 pinctrl-names = "default"; 1141 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1142 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1143 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1144 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1145 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1146 interconnect-names = "qup-core", 1147 "qup-config"; 1148 power-domains = <&rpmhpd RPMHPD_CX>; 1149 operating-points-v2 = <&qup_opp_table>; 1150 status = "disabled"; 1151 }; 1152 1153 i2c7: i2c@a8c000 { 1154 compatible = "qcom,geni-i2c"; 1155 reg = <0x0 0xa8c000 0x0 0x4000>; 1156 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1157 clock-names = "se"; 1158 pinctrl-0 = <&qup_i2c7_data_clk>; 1159 pinctrl-names = "default"; 1160 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1164 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1165 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1166 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1167 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1168 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1169 interconnect-names = "qup-core", 1170 "qup-config", 1171 "qup-memory"; 1172 power-domains = <&rpmhpd RPMHPD_CX>; 1173 required-opps = <&rpmhpd_opp_low_svs>; 1174 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1175 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1176 dma-names = "tx", 1177 "rx"; 1178 status = "disabled"; 1179 }; 1180 1181 spi7: spi@a8c000 { 1182 compatible = "qcom,geni-spi"; 1183 reg = <0x0 0xa8c000 0x0 0x4000>; 1184 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1185 clock-names = "se"; 1186 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1187 pinctrl-names = "default"; 1188 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1192 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1193 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1194 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1195 interconnect-names = "qup-core", 1196 "qup-config"; 1197 power-domains = <&rpmhpd RPMHPD_CX>; 1198 operating-points-v2 = <&qup_opp_table>; 1199 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1200 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1201 dma-names = "tx", 1202 "rx"; 1203 status = "disabled"; 1204 }; 1205 1206 uart7: serial@a8c000 { 1207 compatible = "qcom,geni-uart"; 1208 reg = <0x0 0xa8c000 0x0 0x4000>; 1209 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1210 clock-names = "se"; 1211 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, 1212 <&qup_uart7_tx>, <&qup_uart7_rx>; 1213 pinctrl-names = "default"; 1214 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1215 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1216 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1217 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1218 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1219 interconnect-names = "qup-core", 1220 "qup-config"; 1221 power-domains = <&rpmhpd RPMHPD_CX>; 1222 operating-points-v2 = <&qup_opp_table>; 1223 status = "disabled"; 1224 }; 1225 }; 1226 1227 config_noc: interconnect@1500000 { 1228 reg = <0x0 0x01500000 0x0 0x5080>; 1229 compatible = "qcom,qcs615-config-noc"; 1230 #interconnect-cells = <2>; 1231 qcom,bcm-voters = <&apps_bcm_voter>; 1232 }; 1233 1234 system_noc: interconnect@1620000 { 1235 reg = <0x0 0x01620000 0x0 0x1f300>; 1236 compatible = "qcom,qcs615-system-noc"; 1237 #interconnect-cells = <2>; 1238 qcom,bcm-voters = <&apps_bcm_voter>; 1239 }; 1240 1241 aggre1_noc: interconnect@1700000 { 1242 reg = <0x0 0x01700000 0x0 0x3f200>; 1243 compatible = "qcom,qcs615-aggre1-noc"; 1244 #interconnect-cells = <2>; 1245 qcom,bcm-voters = <&apps_bcm_voter>; 1246 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1247 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, 1248 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1249 <&rpmhcc RPMH_IPA_CLK>; 1250 }; 1251 1252 mmss_noc: interconnect@1740000 { 1253 reg = <0x0 0x01740000 0x0 0x1c100>; 1254 compatible = "qcom,qcs615-mmss-noc"; 1255 #interconnect-cells = <2>; 1256 qcom,bcm-voters = <&apps_bcm_voter>; 1257 }; 1258 1259 pcie: pcie@1c08000 { 1260 device_type = "pci"; 1261 compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150"; 1262 reg = <0x0 0x01c08000 0x0 0x3000>, 1263 <0x0 0x40000000 0x0 0xf1d>, 1264 <0x0 0x40000f20 0x0 0xa8>, 1265 <0x0 0x40001000 0x0 0x1000>, 1266 <0x0 0x40100000 0x0 0x100000>, 1267 <0x0 0x01c0b000 0x0 0x1000>; 1268 reg-names = "parf", 1269 "dbi", 1270 "elbi", 1271 "atu", 1272 "config", 1273 "mhi"; 1274 #address-cells = <3>; 1275 #size-cells = <2>; 1276 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1277 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1278 bus-range = <0x00 0xff>; 1279 1280 dma-coherent; 1281 1282 linux,pci-domain = <0>; 1283 num-lanes = <1>; 1284 1285 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>, 1286 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>, 1287 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>, 1288 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>, 1289 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>, 1290 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>, 1291 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>, 1292 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>, 1293 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>; 1294 interrupt-names = "msi0", 1295 "msi1", 1296 "msi2", 1297 "msi3", 1298 "msi4", 1299 "msi5", 1300 "msi6", 1301 "msi7", 1302 "global"; 1303 1304 #interrupt-cells = <1>; 1305 interrupt-map-mask = <0 0 0 0x7>; 1306 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, 1307 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, 1308 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, 1309 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1310 1311 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1312 <&gcc GCC_PCIE_0_AUX_CLK>, 1313 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1314 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1315 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1316 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 1317 clock-names = "pipe", 1318 "aux", 1319 "cfg", 1320 "bus_master", 1321 "bus_slave", 1322 "slave_q2a"; 1323 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1324 assigned-clock-rates = <19200000>; 1325 1326 interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS 1327 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1328 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1329 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1330 interconnect-names = "pcie-mem", "cpu-pcie"; 1331 1332 iommu-map = <0x0 &apps_smmu 0x400 0x1>, 1333 <0x100 &apps_smmu 0x401 0x1>; 1334 1335 resets = <&gcc GCC_PCIE_0_BCR>; 1336 reset-names = "pci"; 1337 1338 power-domains = <&gcc PCIE_0_GDSC>; 1339 1340 phys = <&pcie_phy>; 1341 phy-names = "pciephy"; 1342 1343 max-link-speed = <2>; 1344 1345 operating-points-v2 = <&pcie_opp_table>; 1346 1347 status = "disabled"; 1348 1349 pcie_opp_table: opp-table { 1350 compatible = "operating-points-v2"; 1351 1352 /* GEN 1 x1 */ 1353 opp-2500000 { 1354 opp-hz = /bits/ 64 <2500000>; 1355 required-opps = <&rpmhpd_opp_low_svs>; 1356 opp-peak-kBps = <250000 1>; 1357 }; 1358 1359 /* GEN 2 x1 */ 1360 opp-5000000 { 1361 opp-hz = /bits/ 64 <5000000>; 1362 required-opps = <&rpmhpd_opp_low_svs>; 1363 opp-peak-kBps = <500000 1>; 1364 }; 1365 }; 1366 1367 pcie_port0: pcie@0 { 1368 device_type = "pci"; 1369 reg = <0x0 0x0 0x0 0x0 0x0>; 1370 #address-cells = <3>; 1371 #size-cells = <2>; 1372 ranges; 1373 bus-range = <0x01 0xff>; 1374 }; 1375 }; 1376 1377 pcie_phy: phy@1c0e000 { 1378 compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy"; 1379 reg = <0x0 0x01c0e000 0x0 0x1000>; 1380 1381 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1382 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1383 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1384 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1385 <&gcc GCC_PCIE_0_PIPE_CLK>; 1386 clock-names = "aux", 1387 "cfg_ahb", 1388 "ref", 1389 "refgen", 1390 "pipe"; 1391 1392 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1393 reset-names = "phy"; 1394 1395 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1396 assigned-clock-rates = <100000000>; 1397 1398 #clock-cells = <0>; 1399 clock-output-names = "pcie_0_pipe_clk"; 1400 1401 #phy-cells = <0>; 1402 1403 status = "disabled"; 1404 }; 1405 1406 ufs_mem_hc: ufshc@1d84000 { 1407 compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1408 reg = <0x0 0x01d84000 0x0 0x3000>, 1409 <0x0 0x01d90000 0x0 0x8000>; 1410 reg-names = "std", 1411 "ice"; 1412 1413 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 1414 1415 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1416 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1417 <&gcc GCC_UFS_PHY_AHB_CLK>, 1418 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1419 <&rpmhcc RPMH_CXO_CLK>, 1420 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1421 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1422 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1423 clock-names = "core_clk", 1424 "bus_aggr_clk", 1425 "iface_clk", 1426 "core_clk_unipro", 1427 "ref_clk", 1428 "tx_lane0_sync_clk", 1429 "rx_lane0_sync_clk", 1430 "ice_core_clk"; 1431 1432 resets = <&gcc GCC_UFS_PHY_BCR>; 1433 reset-names = "rst"; 1434 1435 operating-points-v2 = <&ufs_opp_table>; 1436 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1437 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1438 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1439 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 1440 interconnect-names = "ufs-ddr", 1441 "cpu-ufs"; 1442 1443 power-domains = <&gcc UFS_PHY_GDSC>; 1444 1445 iommus = <&apps_smmu 0x300 0x0>; 1446 dma-coherent; 1447 1448 lanes-per-direction = <1>; 1449 1450 phys = <&ufs_mem_phy>; 1451 phy-names = "ufsphy"; 1452 1453 #reset-cells = <1>; 1454 1455 status = "disabled"; 1456 1457 ufs_opp_table: opp-table { 1458 compatible = "operating-points-v2"; 1459 1460 opp-50000000 { 1461 opp-hz = /bits/ 64 <50000000>, 1462 /bits/ 64 <0>, 1463 /bits/ 64 <0>, 1464 /bits/ 64 <37500000>, 1465 /bits/ 64 <0>, 1466 /bits/ 64 <0>, 1467 /bits/ 64 <0>, 1468 /bits/ 64 <75000000>; 1469 required-opps = <&rpmhpd_opp_low_svs>; 1470 }; 1471 1472 opp-100000000 { 1473 opp-hz = /bits/ 64 <100000000>, 1474 /bits/ 64 <0>, 1475 /bits/ 64 <0>, 1476 /bits/ 64 <75000000>, 1477 /bits/ 64 <0>, 1478 /bits/ 64 <0>, 1479 /bits/ 64 <0>, 1480 /bits/ 64 <150000000>; 1481 required-opps = <&rpmhpd_opp_svs>; 1482 }; 1483 1484 opp-200000000 { 1485 opp-hz = /bits/ 64 <200000000>, 1486 /bits/ 64 <0>, 1487 /bits/ 64 <0>, 1488 /bits/ 64 <150000000>, 1489 /bits/ 64 <0>, 1490 /bits/ 64 <0>, 1491 /bits/ 64 <0>, 1492 /bits/ 64 <300000000>; 1493 required-opps = <&rpmhpd_opp_nom>; 1494 }; 1495 }; 1496 }; 1497 1498 ufs_mem_phy: phy@1d87000 { 1499 compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy"; 1500 reg = <0x0 0x01d87000 0x0 0xe00>; 1501 clocks = <&rpmhcc RPMH_CXO_CLK>, 1502 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1503 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1504 clock-names = "ref", 1505 "ref_aux", 1506 "qref"; 1507 1508 power-domains = <&gcc UFS_PHY_GDSC>; 1509 1510 resets = <&ufs_mem_hc 0>; 1511 reset-names = "ufsphy"; 1512 1513 #clock-cells = <1>; 1514 #phy-cells = <0>; 1515 1516 status = "disabled"; 1517 }; 1518 1519 cryptobam: dma-controller@1dc4000 { 1520 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1521 reg = <0x0 0x01dc4000 0x0 0x24000>; 1522 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; 1523 #dma-cells = <1>; 1524 qcom,ee = <0>; 1525 qcom,controlled-remotely; 1526 num-channels = <16>; 1527 qcom,num-ees = <4>; 1528 iommus = <&apps_smmu 0x0104 0x0011>; 1529 }; 1530 1531 crypto: crypto@1dfa000 { 1532 compatible = "qcom,qcs615-qce", "qcom,sm8150-qce", "qcom,qce"; 1533 reg = <0x0 0x01dfa000 0x0 0x6000>; 1534 dmas = <&cryptobam 4>, <&cryptobam 5>; 1535 dma-names = "rx", "tx"; 1536 iommus = <&apps_smmu 0x0104 0x0011>; 1537 interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 1538 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1539 interconnect-names = "memory"; 1540 }; 1541 1542 tcsr_mutex: hwlock@1f40000 { 1543 compatible = "qcom,tcsr-mutex"; 1544 reg = <0x0 0x01f40000 0x0 0x20000>; 1545 #hwlock-cells = <1>; 1546 }; 1547 1548 tcsr: syscon@1fc0000 { 1549 compatible = "qcom,qcs615-tcsr", "syscon"; 1550 reg = <0x0 0x01fc0000 0x0 0x30000>; 1551 }; 1552 1553 tlmm: pinctrl@3100000 { 1554 compatible = "qcom,qcs615-tlmm"; 1555 reg = <0x0 0x03100000 0x0 0x300000>, 1556 <0x0 0x03500000 0x0 0x300000>, 1557 <0x0 0x03d00000 0x0 0x300000>; 1558 reg-names = "east", 1559 "west", 1560 "south"; 1561 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; 1562 gpio-ranges = <&tlmm 0 0 124>; 1563 gpio-controller; 1564 #gpio-cells = <2>; 1565 interrupt-controller; 1566 #interrupt-cells = <2>; 1567 wakeup-parent = <&pdc>; 1568 1569 cam_mclk0_default: cam-mclk0-default-state { 1570 pins = "gpio28"; 1571 function = "cam_mclk"; 1572 drive-strength = <2>; 1573 bias-disable; 1574 }; 1575 1576 cam_mclk1_default: cam-mclk1-default-state { 1577 pins = "gpio29"; 1578 function = "cam_mclk"; 1579 drive-strength = <2>; 1580 bias-disable; 1581 }; 1582 1583 cam_mclk2_default: cam-mclk2-default-state { 1584 pins = "gpio30"; 1585 function = "cam_mclk"; 1586 drive-strength = <2>; 1587 bias-disable; 1588 }; 1589 1590 cam_mclk3_default: cam-mclk3-default-state { 1591 pins = "gpio31"; 1592 function = "cam_mclk"; 1593 drive-strength = <2>; 1594 bias-disable; 1595 }; 1596 1597 cci_i2c0_default: cci-i2c0-default-state { 1598 /* SDA, SCL */ 1599 pins = "gpio32", "gpio33"; 1600 function = "cci_i2c"; 1601 drive-strength = <2>; 1602 bias-pull-up; 1603 }; 1604 1605 cci_i2c1_default: cci-i2c1-default-state { 1606 /* SDA, SCL */ 1607 pins = "gpio34", "gpio35"; 1608 function = "cci_i2c"; 1609 drive-strength = <2>; 1610 bias-pull-up; 1611 }; 1612 1613 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 1614 pins = "gpio4", "gpio5"; 1615 function = "qup0"; 1616 1617 }; 1618 1619 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 1620 pins = "gpio0", "gpio1"; 1621 function = "qup0"; 1622 }; 1623 1624 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 1625 pins = "gpio18", "gpio19"; 1626 function = "qup0"; 1627 }; 1628 1629 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 1630 pins = "gpio20", "gpio21"; 1631 function = "qup1"; 1632 }; 1633 1634 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 1635 pins = "gpio14", "gpio15"; 1636 function = "qup1"; 1637 }; 1638 1639 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 1640 pins = "gpio6", "gpio7"; 1641 function = "qup1"; 1642 }; 1643 1644 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 1645 pins = "gpio10", "gpio11"; 1646 function = "qup1"; 1647 }; 1648 1649 qup_spi2_data_clk: qup-spi2-data-clk-state { 1650 pins = "gpio0", "gpio1", "gpio2"; 1651 function = "qup0"; 1652 }; 1653 1654 qup_spi2_cs: qup-spi2-cs-state { 1655 pins = "gpio3"; 1656 function = "qup0"; 1657 }; 1658 1659 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 1660 pins = "gpio3"; 1661 function = "gpio"; 1662 }; 1663 1664 qup_spi4_data_clk: qup-spi4-data-clk-state { 1665 pins = "gpio20", "gpio21", "gpio22"; 1666 function = "qup1"; 1667 }; 1668 1669 qup_spi4_cs: qup-spi4-cs-state { 1670 pins = "gpio23"; 1671 function = "qup1"; 1672 }; 1673 1674 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 1675 pins = "gpio23"; 1676 function = "gpio"; 1677 }; 1678 1679 qup_spi6_data_clk: qup-spi6-data-clk-state { 1680 pins = "gpio6", "gpio7", "gpio8"; 1681 function = "qup1"; 1682 }; 1683 1684 qup_spi6_cs: qup-spi6-cs-state { 1685 pins = "gpio9"; 1686 function = "qup1"; 1687 }; 1688 1689 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1690 pins = "gpio9"; 1691 function = "gpio"; 1692 }; 1693 1694 qup_spi7_data_clk: qup-spi7-data-clk-state { 1695 pins = "gpio10", "gpio11", "gpio12"; 1696 function = "qup1"; 1697 }; 1698 1699 qup_spi7_cs: qup-spi7-cs-state { 1700 pins = "gpio13"; 1701 function = "qup1"; 1702 }; 1703 1704 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 1705 pins = "gpio13"; 1706 function = "gpio"; 1707 }; 1708 1709 qup_uart0_tx: qup-uart0-tx-state { 1710 pins = "gpio16"; 1711 function = "qup0"; 1712 }; 1713 1714 qup_uart0_rx: qup-uart0-rx-state { 1715 pins = "gpio17"; 1716 function = "qup0"; 1717 }; 1718 1719 qup_uart2_cts: qup-uart2-cts-state { 1720 pins = "gpio0"; 1721 function = "qup0"; 1722 }; 1723 1724 qup_uart2_rts: qup-uart2-rts-state { 1725 pins = "gpio1"; 1726 function = "qup0"; 1727 }; 1728 1729 qup_uart2_tx: qup-uart2-tx-state { 1730 pins = "gpio2"; 1731 function = "qup0"; 1732 }; 1733 1734 qup_uart2_rx: qup-uart2-rx-state { 1735 pins = "gpio3"; 1736 function = "qup0"; 1737 }; 1738 1739 qup_uart4_cts: qup-uart4-cts-state { 1740 pins = "gpio20"; 1741 function = "qup1"; 1742 }; 1743 1744 qup_uart4_rts: qup-uart4-rts-state { 1745 pins = "gpio21"; 1746 function = "qup1"; 1747 }; 1748 1749 qup_uart4_tx: qup-uart4-tx-state { 1750 pins = "gpio22"; 1751 function = "qup1"; 1752 }; 1753 1754 qup_uart4_rx: qup-uart4-rx-state { 1755 pins = "gpio23"; 1756 function = "qup1"; 1757 }; 1758 1759 qup_uart6_cts: qup-uart6-cts-state { 1760 pins = "gpio6"; 1761 function = "qup1"; 1762 }; 1763 1764 qup_uart6_rts: qup-uart6-rts-state { 1765 pins = "gpio7"; 1766 function = "qup1"; 1767 }; 1768 1769 qup_uart6_tx: qup-uart6-tx-state { 1770 pins = "gpio8"; 1771 function = "qup1"; 1772 }; 1773 1774 qup_uart6_rx: qup-uart6-rx-state { 1775 pins = "gpio9"; 1776 function = "qup1"; 1777 }; 1778 1779 qup_uart7_cts: qup-uart7-cts-state { 1780 pins = "gpio10"; 1781 function = "qup1"; 1782 }; 1783 1784 qup_uart7_rts: qup-uart7-rts-state { 1785 pins = "gpio11"; 1786 function = "qup1"; 1787 }; 1788 1789 qup_uart7_tx: qup-uart7-tx-state { 1790 pins = "gpio12"; 1791 function = "qup1"; 1792 }; 1793 1794 qup_uart7_rx: qup-uart7-rx-state { 1795 pins = "gpio13"; 1796 function = "qup1"; 1797 }; 1798 1799 sdc1_state_on: sdc1-on-state { 1800 clk-pins { 1801 pins = "sdc1_clk"; 1802 bias-disable; 1803 drive-strength = <16>; 1804 }; 1805 1806 cmd-pins { 1807 pins = "sdc1_cmd"; 1808 bias-pull-up; 1809 drive-strength = <10>; 1810 }; 1811 1812 data-pins { 1813 pins = "sdc1_data"; 1814 bias-pull-up; 1815 drive-strength = <10>; 1816 }; 1817 1818 rclk-pins { 1819 pins = "sdc1_rclk"; 1820 bias-pull-down; 1821 }; 1822 }; 1823 1824 sdc1_state_off: sdc1-off-state { 1825 clk-pins { 1826 pins = "sdc1_clk"; 1827 bias-disable; 1828 drive-strength = <2>; 1829 }; 1830 1831 cmd-pins { 1832 pins = "sdc1_cmd"; 1833 bias-pull-up; 1834 drive-strength = <2>; 1835 }; 1836 1837 data-pins { 1838 pins = "sdc1_data"; 1839 bias-pull-up; 1840 drive-strength = <2>; 1841 }; 1842 1843 rclk-pins { 1844 pins = "sdc1_rclk"; 1845 bias-pull-down; 1846 }; 1847 }; 1848 1849 sdc2_state_on: sdc2-on-state { 1850 clk-pins { 1851 pins = "sdc2_clk"; 1852 bias-disable; 1853 drive-strength = <16>; 1854 }; 1855 1856 cmd-pins { 1857 pins = "sdc2_cmd"; 1858 bias-pull-up; 1859 drive-strength = <10>; 1860 }; 1861 1862 data-pins { 1863 pins = "sdc2_data"; 1864 bias-pull-up; 1865 drive-strength = <10>; 1866 }; 1867 }; 1868 1869 sdc2_state_off: sdc2-off-state { 1870 clk-pins { 1871 pins = "sdc2_clk"; 1872 bias-disable; 1873 drive-strength = <2>; 1874 }; 1875 1876 cmd-pins { 1877 pins = "sdc2_cmd"; 1878 bias-pull-up; 1879 drive-strength = <2>; 1880 }; 1881 1882 data-pins { 1883 pins = "sdc2_data"; 1884 bias-pull-up; 1885 drive-strength = <2>; 1886 }; 1887 }; 1888 }; 1889 1890 gpu: gpu@5000000 { 1891 compatible = "qcom,adreno-612.0", "qcom,adreno"; 1892 reg = <0x0 0x05000000 0x0 0x40000>, 1893 <0x0 0x0509e000 0x0 0x1000>, 1894 <0x0 0x05061000 0x0 0x800>; 1895 reg-names = "kgsl_3d0_reg_memory", 1896 "cx_mem", 1897 "cx_dbgc"; 1898 1899 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>; 1900 clock-names = "core"; 1901 1902 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; 1903 1904 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 1905 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1906 interconnect-names = "gfx-mem"; 1907 1908 iommus = <&adreno_smmu 0x0 0x401>; 1909 1910 operating-points-v2 = <&gpu_opp_table>; 1911 power-domains = <&rpmhpd RPMHPD_CX>; 1912 1913 qcom,gmu = <&gmu>; 1914 1915 #cooling-cells = <2>; 1916 1917 status = "disabled"; 1918 1919 gpu_zap_shader: zap-shader { 1920 memory-region = <&pil_gpu_mem>; 1921 }; 1922 1923 gpu_opp_table: opp-table { 1924 compatible = "operating-points-v2"; 1925 1926 opp-845000000 { 1927 opp-hz = /bits/ 64 <845000000>; 1928 required-opps = <&rpmhpd_opp_turbo>; 1929 opp-peak-kBps = <7050000>; 1930 }; 1931 1932 opp-745000000 { 1933 opp-hz = /bits/ 64 <745000000>; 1934 required-opps = <&rpmhpd_opp_nom_l1>; 1935 opp-peak-kBps = <6075000>; 1936 }; 1937 1938 opp-650000000 { 1939 opp-hz = /bits/ 64 <650000000>; 1940 required-opps = <&rpmhpd_opp_nom>; 1941 opp-peak-kBps = <5287500>; 1942 }; 1943 1944 opp-500000000 { 1945 opp-hz = /bits/ 64 <500000000>; 1946 required-opps = <&rpmhpd_opp_svs_l1>; 1947 opp-peak-kBps = <3975000>; 1948 }; 1949 1950 opp-435000000 { 1951 opp-hz = /bits/ 64 <435000000>; 1952 required-opps = <&rpmhpd_opp_svs>; 1953 opp-peak-kBps = <3000000>; 1954 }; 1955 }; 1956 }; 1957 1958 gmu: gmu@506a000 { 1959 compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu"; 1960 reg = <0x0 0x0506d000 0x0 0x2c000>; 1961 1962 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1963 <&gpucc GPU_CC_CXO_CLK>, 1964 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1965 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1966 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 1967 clock-names = "gmu", 1968 "cxo", 1969 "axi", 1970 "memnoc", 1971 "smmu_vote"; 1972 1973 power-domains = <&gpucc CX_GDSC>, 1974 <&gpucc GX_GDSC>; 1975 power-domain-names = "cx", 1976 "gx"; 1977 1978 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>, 1979 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 1980 interrupt-names = "oob", 1981 "gmu"; 1982 1983 operating-points-v2 = <&gmu_opp_table>; 1984 1985 gmu_opp_table: opp-table { 1986 compatible = "operating-points-v2"; 1987 1988 opp-200000000 { 1989 opp-hz = /bits/ 64 <200000000>; 1990 required-opps = <&rpmhpd_opp_low_svs>; 1991 }; 1992 }; 1993 }; 1994 1995 gpucc: clock-controller@5090000 { 1996 compatible = "qcom,qcs615-gpucc"; 1997 reg = <0 0x05090000 0 0x9000>; 1998 1999 clocks = <&rpmhcc RPMH_CXO_CLK>, 2000 <&gcc GPLL0>, 2001 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2002 2003 #clock-cells = <1>; 2004 #reset-cells = <1>; 2005 #power-domain-cells = <1>; 2006 }; 2007 2008 adreno_smmu: iommu@50a0000 { 2009 compatible = "qcom,qcs615-smmu-500", "qcom,adreno-smmu", 2010 "qcom,smmu-500", "arm,mmu-500"; 2011 reg = <0x0 0x050a0000 0x0 0x40000>; 2012 #iommu-cells = <2>; 2013 #global-interrupts = <1>; 2014 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>, 2015 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, 2016 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, 2017 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, 2018 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, 2019 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, 2020 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, 2021 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, 2022 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>; 2023 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2024 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2025 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2026 clock-names = "mem", 2027 "hlos", 2028 "iface"; 2029 power-domains = <&gpucc CX_GDSC>; 2030 dma-coherent; 2031 }; 2032 2033 stm@6002000 { 2034 compatible = "arm,coresight-stm", "arm,primecell"; 2035 reg = <0x0 0x06002000 0x0 0x1000>, 2036 <0x0 0x16280000 0x0 0x180000>; 2037 reg-names = "stm-base", 2038 "stm-stimulus-base"; 2039 2040 clocks = <&aoss_qmp>; 2041 clock-names = "apb_pclk"; 2042 2043 out-ports { 2044 port { 2045 stm_out: endpoint { 2046 remote-endpoint = <&funnel_in0_in7>; 2047 }; 2048 }; 2049 }; 2050 }; 2051 2052 tpda@6004000 { 2053 compatible = "qcom,coresight-tpda", "arm,primecell"; 2054 reg = <0x0 0x06004000 0x0 0x1000>; 2055 2056 clocks = <&aoss_qmp>; 2057 clock-names = "apb_pclk"; 2058 2059 in-ports { 2060 #address-cells = <1>; 2061 #size-cells = <0>; 2062 2063 port@0 { 2064 reg = <0>; 2065 2066 tpda_qdss_in0: endpoint { 2067 remote-endpoint = <&tpdm_center_out>; 2068 }; 2069 }; 2070 2071 port@4 { 2072 reg = <4>; 2073 2074 tpda_qdss_in4: endpoint { 2075 remote-endpoint = <&funnel_monaq_out>; 2076 }; 2077 }; 2078 2079 port@5 { 2080 reg = <5>; 2081 2082 tpda_qdss_in5: endpoint { 2083 remote-endpoint = <&funnel_ddr_0_out>; 2084 }; 2085 }; 2086 2087 port@6 { 2088 reg = <6>; 2089 2090 tpda_qdss_in6: endpoint { 2091 remote-endpoint = <&funnel_turing_out>; 2092 }; 2093 }; 2094 2095 port@7 { 2096 reg = <7>; 2097 2098 tpda_qdss_in7: endpoint { 2099 remote-endpoint = <&tpdm_vsense_out>; 2100 }; 2101 }; 2102 2103 port@8 { 2104 reg = <8>; 2105 2106 tpda_qdss_in8: endpoint { 2107 remote-endpoint = <&tpdm_dcc_out>; 2108 }; 2109 }; 2110 2111 port@9 { 2112 reg = <9>; 2113 2114 tpda_qdss_in9: endpoint { 2115 remote-endpoint = <&tpdm_prng_out>; 2116 }; 2117 }; 2118 2119 port@b { 2120 reg = <11>; 2121 2122 tpda_qdss_in11: endpoint { 2123 remote-endpoint = <&tpdm_qm_out>; 2124 }; 2125 }; 2126 2127 port@c { 2128 reg = <12>; 2129 2130 tpda_qdss_in12: endpoint { 2131 remote-endpoint = <&tpdm_west_out>; 2132 }; 2133 }; 2134 2135 port@d { 2136 reg = <13>; 2137 2138 tpda_qdss_in13: endpoint { 2139 remote-endpoint = <&tpdm_pimem_out>; 2140 }; 2141 }; 2142 }; 2143 2144 out-ports { 2145 port { 2146 tpda_qdss_out: endpoint { 2147 remote-endpoint = <&funnel_qatb_in>; 2148 }; 2149 }; 2150 }; 2151 }; 2152 2153 funnel@6005000 { 2154 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2155 reg = <0x0 0x06005000 0x0 0x1000>; 2156 2157 clocks = <&aoss_qmp>; 2158 clock-names = "apb_pclk"; 2159 2160 in-ports { 2161 port { 2162 funnel_qatb_in: endpoint { 2163 remote-endpoint = <&tpda_qdss_out>; 2164 }; 2165 }; 2166 }; 2167 2168 out-ports { 2169 port { 2170 funnel_qatb_out: endpoint { 2171 remote-endpoint = <&funnel_in0_in6>; 2172 }; 2173 }; 2174 }; 2175 }; 2176 2177 cti@6010000 { 2178 compatible = "arm,coresight-cti", "arm,primecell"; 2179 reg = <0x0 0x06010000 0x0 0x1000>; 2180 2181 clocks = <&aoss_qmp>; 2182 clock-names = "apb_pclk"; 2183 }; 2184 2185 cti@6011000 { 2186 compatible = "arm,coresight-cti", "arm,primecell"; 2187 reg = <0x0 0x06011000 0x0 0x1000>; 2188 2189 clocks = <&aoss_qmp>; 2190 clock-names = "apb_pclk"; 2191 }; 2192 2193 cti@6012000 { 2194 compatible = "arm,coresight-cti", "arm,primecell"; 2195 reg = <0x0 0x06012000 0x0 0x1000>; 2196 2197 clocks = <&aoss_qmp>; 2198 clock-names = "apb_pclk"; 2199 }; 2200 2201 cti@6013000 { 2202 compatible = "arm,coresight-cti", "arm,primecell"; 2203 reg = <0x0 0x06013000 0x0 0x1000>; 2204 2205 clocks = <&aoss_qmp>; 2206 clock-names = "apb_pclk"; 2207 }; 2208 2209 cti@6014000 { 2210 compatible = "arm,coresight-cti", "arm,primecell"; 2211 reg = <0x0 0x06014000 0x0 0x1000>; 2212 2213 clocks = <&aoss_qmp>; 2214 clock-names = "apb_pclk"; 2215 }; 2216 2217 cti@6015000 { 2218 compatible = "arm,coresight-cti", "arm,primecell"; 2219 reg = <0x0 0x06015000 0x0 0x1000>; 2220 2221 clocks = <&aoss_qmp>; 2222 clock-names = "apb_pclk"; 2223 }; 2224 2225 cti@6016000 { 2226 compatible = "arm,coresight-cti", "arm,primecell"; 2227 reg = <0x0 0x06016000 0x0 0x1000>; 2228 2229 clocks = <&aoss_qmp>; 2230 clock-names = "apb_pclk"; 2231 }; 2232 2233 cti@6017000 { 2234 compatible = "arm,coresight-cti", "arm,primecell"; 2235 reg = <0x0 0x06017000 0x0 0x1000>; 2236 2237 clocks = <&aoss_qmp>; 2238 clock-names = "apb_pclk"; 2239 }; 2240 2241 cti@6018000 { 2242 compatible = "arm,coresight-cti", "arm,primecell"; 2243 reg = <0x0 0x06018000 0x0 0x1000>; 2244 2245 clocks = <&aoss_qmp>; 2246 clock-names = "apb_pclk"; 2247 }; 2248 2249 cti@6019000 { 2250 compatible = "arm,coresight-cti", "arm,primecell"; 2251 reg = <0x0 0x06019000 0x0 0x1000>; 2252 2253 clocks = <&aoss_qmp>; 2254 clock-names = "apb_pclk"; 2255 }; 2256 2257 cti@601a000 { 2258 compatible = "arm,coresight-cti", "arm,primecell"; 2259 reg = <0x0 0x0601a000 0x0 0x1000>; 2260 2261 clocks = <&aoss_qmp>; 2262 clock-names = "apb_pclk"; 2263 }; 2264 2265 cti@601b000 { 2266 compatible = "arm,coresight-cti", "arm,primecell"; 2267 reg = <0x0 0x0601b000 0x0 0x1000>; 2268 2269 clocks = <&aoss_qmp>; 2270 clock-names = "apb_pclk"; 2271 }; 2272 2273 cti@601c000 { 2274 compatible = "arm,coresight-cti", "arm,primecell"; 2275 reg = <0x0 0x0601c000 0x0 0x1000>; 2276 2277 clocks = <&aoss_qmp>; 2278 clock-names = "apb_pclk"; 2279 }; 2280 2281 cti@601d000 { 2282 compatible = "arm,coresight-cti", "arm,primecell"; 2283 reg = <0x0 0x0601d000 0x0 0x1000>; 2284 2285 clocks = <&aoss_qmp>; 2286 clock-names = "apb_pclk"; 2287 }; 2288 2289 cti@601e000 { 2290 compatible = "arm,coresight-cti", "arm,primecell"; 2291 reg = <0x0 0x0601e000 0x0 0x1000>; 2292 2293 clocks = <&aoss_qmp>; 2294 clock-names = "apb_pclk"; 2295 }; 2296 2297 cti@601f000 { 2298 compatible = "arm,coresight-cti", "arm,primecell"; 2299 reg = <0x0 0x0601f000 0x0 0x1000>; 2300 2301 clocks = <&aoss_qmp>; 2302 clock-names = "apb_pclk"; 2303 }; 2304 2305 funnel@6041000 { 2306 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2307 reg = <0x0 0x06041000 0x0 0x1000>; 2308 2309 clocks = <&aoss_qmp>; 2310 clock-names = "apb_pclk"; 2311 2312 in-ports { 2313 #address-cells = <1>; 2314 #size-cells = <0>; 2315 2316 port@6 { 2317 reg = <6>; 2318 2319 funnel_in0_in6: endpoint { 2320 remote-endpoint = <&funnel_qatb_out>; 2321 }; 2322 }; 2323 2324 port@7 { 2325 reg = <7>; 2326 2327 funnel_in0_in7: endpoint { 2328 remote-endpoint = <&stm_out>; 2329 }; 2330 }; 2331 }; 2332 2333 out-ports { 2334 port { 2335 funnel_in0_out: endpoint { 2336 remote-endpoint = <&funnel_merg_in0>; 2337 }; 2338 }; 2339 }; 2340 }; 2341 2342 funnel@6042000 { 2343 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2344 reg = <0x0 0x06042000 0x0 0x1000>; 2345 2346 clocks = <&aoss_qmp>; 2347 clock-names = "apb_pclk"; 2348 2349 in-ports { 2350 #address-cells = <1>; 2351 #size-cells = <0>; 2352 2353 port@3 { 2354 reg = <3>; 2355 2356 funnel_in1_in3: endpoint { 2357 remote-endpoint = <&replicator_swao_out0>; 2358 }; 2359 }; 2360 2361 port@4 { 2362 reg = <4>; 2363 2364 funnel_in1_in4: endpoint { 2365 remote-endpoint = <&tpdm_wcss_out>; 2366 }; 2367 }; 2368 2369 port@7 { 2370 reg = <7>; 2371 2372 funnel_in1_in7: endpoint { 2373 remote-endpoint = <&funnel_apss_merg_out>; 2374 }; 2375 }; 2376 }; 2377 2378 out-ports { 2379 port { 2380 funnel_in1_out: endpoint { 2381 remote-endpoint = <&funnel_merg_in1>; 2382 }; 2383 }; 2384 }; 2385 }; 2386 2387 funnel@6045000 { 2388 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2389 reg = <0x0 0x06045000 0x0 0x1000>; 2390 2391 clocks = <&aoss_qmp>; 2392 clock-names = "apb_pclk"; 2393 2394 in-ports { 2395 #address-cells = <1>; 2396 #size-cells = <0>; 2397 2398 port@0 { 2399 reg = <0>; 2400 2401 funnel_merg_in0: endpoint { 2402 remote-endpoint = <&funnel_in0_out>; 2403 }; 2404 }; 2405 2406 port@1 { 2407 reg = <1>; 2408 2409 funnel_merg_in1: endpoint { 2410 remote-endpoint = <&funnel_in1_out>; 2411 }; 2412 }; 2413 }; 2414 2415 out-ports { 2416 port { 2417 funnel_merg_out: endpoint { 2418 remote-endpoint = <&tmc_etf_in>; 2419 }; 2420 }; 2421 }; 2422 }; 2423 2424 replicator@6046000 { 2425 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2426 reg = <0x0 0x06046000 0x0 0x1000>; 2427 2428 clocks = <&aoss_qmp>; 2429 clock-names = "apb_pclk"; 2430 2431 in-ports { 2432 port { 2433 replicator0_in: endpoint { 2434 remote-endpoint = <&tmc_etf_out>; 2435 }; 2436 }; 2437 }; 2438 2439 out-ports { 2440 #address-cells = <1>; 2441 #size-cells = <0>; 2442 2443 port@0 { 2444 reg = <0>; 2445 2446 replicator0_out0: endpoint { 2447 remote-endpoint = <&tmc_etr_in>; 2448 }; 2449 }; 2450 2451 port@1 { 2452 reg = <1>; 2453 2454 replicator0_out1: endpoint { 2455 remote-endpoint = <&replicator1_in>; 2456 }; 2457 }; 2458 }; 2459 }; 2460 2461 tmc@6047000 { 2462 compatible = "arm,coresight-tmc", "arm,primecell"; 2463 reg = <0x0 0x06047000 0x0 0x1000>; 2464 2465 clocks = <&aoss_qmp>; 2466 clock-names = "apb_pclk"; 2467 2468 in-ports { 2469 port { 2470 tmc_etf_in: endpoint { 2471 remote-endpoint = <&funnel_merg_out>; 2472 }; 2473 }; 2474 }; 2475 2476 out-ports { 2477 port { 2478 tmc_etf_out: endpoint { 2479 remote-endpoint = <&replicator0_in>; 2480 }; 2481 }; 2482 }; 2483 }; 2484 2485 tmc@6048000 { 2486 compatible = "arm,coresight-tmc", "arm,primecell"; 2487 reg = <0x0 0x06048000 0x0 0x1000>; 2488 2489 clocks = <&aoss_qmp>; 2490 clock-names = "apb_pclk"; 2491 2492 iommus = <&apps_smmu 0x01e0 0x0>; 2493 arm,scatter-gather; 2494 2495 in-ports { 2496 port { 2497 tmc_etr_in: endpoint { 2498 remote-endpoint = <&replicator0_out0>; 2499 }; 2500 }; 2501 }; 2502 }; 2503 2504 replicator@604a000 { 2505 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2506 reg = <0x0 0x0604a000 0x0 0x1000>; 2507 2508 clocks = <&aoss_qmp>; 2509 clock-names = "apb_pclk"; 2510 status = "disabled"; 2511 2512 in-ports { 2513 port { 2514 replicator1_in: endpoint { 2515 remote-endpoint = <&replicator0_out1>; 2516 }; 2517 }; 2518 }; 2519 2520 out-ports { 2521 port { 2522 replicator1_out: endpoint { 2523 remote-endpoint = <&funnel_swao_in6>; 2524 }; 2525 }; 2526 }; 2527 }; 2528 2529 cti@683b000 { 2530 compatible = "arm,coresight-cti", "arm,primecell"; 2531 reg = <0x0 0x0683b000 0x0 0x1000>; 2532 2533 clocks = <&aoss_qmp>; 2534 clock-names = "apb_pclk"; 2535 }; 2536 2537 tpdm@6840000 { 2538 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2539 reg = <0x0 0x06840000 0x0 0x1000>; 2540 2541 clocks = <&aoss_qmp>; 2542 clock-names = "apb_pclk"; 2543 2544 qcom,cmb-element-bits = <64>; 2545 qcom,cmb-msrs-num = <32>; 2546 status = "disabled"; 2547 2548 out-ports { 2549 port { 2550 tpdm_vsense_out: endpoint { 2551 remote-endpoint = <&tpda_qdss_in7>; 2552 }; 2553 }; 2554 }; 2555 }; 2556 2557 tpdm@684c000 { 2558 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2559 reg = <0x0 0x0684c000 0x0 0x1000>; 2560 2561 clocks = <&aoss_qmp>; 2562 clock-names = "apb_pclk"; 2563 2564 qcom,cmb-element-bits = <32>; 2565 qcom,cmb-msrs-num = <32>; 2566 2567 out-ports { 2568 port { 2569 tpdm_prng_out: endpoint { 2570 remote-endpoint = <&tpda_qdss_in9>; 2571 }; 2572 }; 2573 }; 2574 }; 2575 2576 tpdm@6850000 { 2577 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2578 reg = <0x0 0x06850000 0x0 0x1000>; 2579 2580 clocks = <&aoss_qmp>; 2581 clock-names = "apb_pclk"; 2582 2583 qcom,cmb-element-bits = <64>; 2584 qcom,cmb-msrs-num = <32>; 2585 qcom,dsb-element-bits = <32>; 2586 qcom,dsb-msrs-num = <32>; 2587 2588 out-ports { 2589 port { 2590 tpdm_pimem_out: endpoint { 2591 remote-endpoint = <&tpda_qdss_in13>; 2592 }; 2593 }; 2594 }; 2595 }; 2596 2597 tpdm@6860000 { 2598 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2599 reg = <0x0 0x06860000 0x0 0x1000>; 2600 2601 clocks = <&aoss_qmp>; 2602 clock-names = "apb_pclk"; 2603 2604 qcom,dsb-element-bits = <32>; 2605 qcom,dsb-msrs-num = <32>; 2606 2607 out-ports { 2608 port { 2609 tpdm_turing_out: endpoint { 2610 remote-endpoint = <&funnel_turing_in>; 2611 }; 2612 }; 2613 }; 2614 }; 2615 2616 funnel@6861000 { 2617 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2618 reg = <0x0 0x06861000 0x0 0x1000>; 2619 2620 clocks = <&aoss_qmp>; 2621 clock-names = "apb_pclk"; 2622 2623 in-ports { 2624 port { 2625 funnel_turing_in: endpoint { 2626 remote-endpoint = <&tpdm_turing_out>; 2627 }; 2628 }; 2629 }; 2630 2631 out-ports { 2632 port { 2633 funnel_turing_out: endpoint { 2634 remote-endpoint = <&tpda_qdss_in6>; 2635 }; 2636 }; 2637 }; 2638 }; 2639 2640 cti@6867000 { 2641 compatible = "arm,coresight-cti", "arm,primecell"; 2642 reg = <0x0 0x06867000 0x0 0x1000>; 2643 2644 clocks = <&aoss_qmp>; 2645 clock-names = "apb_pclk"; 2646 }; 2647 2648 tpdm@6870000 { 2649 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2650 reg = <0x0 0x06870000 0x0 0x1000>; 2651 2652 clocks = <&aoss_qmp>; 2653 clock-names = "apb_pclk"; 2654 2655 qcom,cmb-element-bits = <32>; 2656 qcom,cmb-msrs-num = <32>; 2657 status = "disabled"; 2658 2659 out-ports { 2660 port { 2661 tpdm_dcc_out: endpoint { 2662 remote-endpoint = <&tpda_qdss_in8>; 2663 }; 2664 }; 2665 }; 2666 }; 2667 2668 tpdm@699c000 { 2669 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2670 reg = <0x0 0x0699c000 0x0 0x1000>; 2671 2672 clocks = <&aoss_qmp>; 2673 clock-names = "apb_pclk"; 2674 2675 qcom,cmb-element-bits = <32>; 2676 qcom,cmb-msrs-num = <32>; 2677 qcom,dsb-element-bits = <32>; 2678 qcom,dsb-msrs-num = <32>; 2679 status = "disabled"; 2680 2681 out-ports { 2682 port { 2683 tpdm_wcss_out: endpoint { 2684 remote-endpoint = <&funnel_in1_in4>; 2685 }; 2686 }; 2687 }; 2688 }; 2689 2690 tpdm@69c0000 { 2691 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2692 reg = <0x0 0x069c0000 0x0 0x1000>; 2693 2694 clocks = <&aoss_qmp>; 2695 clock-names = "apb_pclk"; 2696 2697 qcom,dsb-element-bits = <32>; 2698 qcom,dsb-msrs-num = <32>; 2699 2700 out-ports { 2701 port { 2702 tpdm_monaq_out: endpoint { 2703 remote-endpoint = <&funnel_monaq_in>; 2704 }; 2705 }; 2706 }; 2707 }; 2708 2709 funnel@69c3000 { 2710 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2711 reg = <0x0 0x069c3000 0x0 0x1000>; 2712 2713 clocks = <&aoss_qmp>; 2714 clock-names = "apb_pclk"; 2715 2716 in-ports { 2717 port { 2718 funnel_monaq_in: endpoint { 2719 remote-endpoint = <&tpdm_monaq_out>; 2720 }; 2721 }; 2722 }; 2723 2724 out-ports { 2725 port { 2726 funnel_monaq_out: endpoint { 2727 remote-endpoint = <&tpda_qdss_in4>; 2728 }; 2729 }; 2730 }; 2731 }; 2732 2733 tpdm@69d0000 { 2734 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2735 reg = <0x0 0x069d0000 0x0 0x1000>; 2736 2737 clocks = <&aoss_qmp>; 2738 clock-names = "apb_pclk"; 2739 2740 qcom,dsb-element-bits = <32>; 2741 qcom,dsb-msrs-num = <32>; 2742 status = "disabled"; 2743 2744 out-ports { 2745 port { 2746 tpdm_qm_out: endpoint { 2747 remote-endpoint = <&tpda_qdss_in11>; 2748 }; 2749 }; 2750 }; 2751 }; 2752 2753 tpdm@6a00000 { 2754 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2755 reg = <0x0 0x06a00000 0x0 0x1000>; 2756 2757 clocks = <&aoss_qmp>; 2758 clock-names = "apb_pclk"; 2759 2760 qcom,dsb-element-bits = <32>; 2761 qcom,dsb-msrs-num = <32>; 2762 status = "disabled"; 2763 2764 out-ports { 2765 port { 2766 tpdm_ddr_out: endpoint { 2767 remote-endpoint = <&funnel_ddr_0_in>; 2768 }; 2769 }; 2770 }; 2771 }; 2772 2773 cti@6a02000 { 2774 compatible = "arm,coresight-cti", "arm,primecell"; 2775 reg = <0x0 0x06a02000 0x0 0x1000>; 2776 2777 clocks = <&aoss_qmp>; 2778 clock-names = "apb_pclk"; 2779 }; 2780 2781 cti@6a03000 { 2782 compatible = "arm,coresight-cti", "arm,primecell"; 2783 reg = <0x0 0x06a03000 0x0 0x1000>; 2784 2785 clocks = <&aoss_qmp>; 2786 clock-names = "apb_pclk"; 2787 }; 2788 2789 cti@6a10000 { 2790 compatible = "arm,coresight-cti", "arm,primecell"; 2791 reg = <0x0 0x06a10000 0x0 0x1000>; 2792 2793 clocks = <&aoss_qmp>; 2794 clock-names = "apb_pclk"; 2795 }; 2796 2797 cti@6a11000 { 2798 compatible = "arm,coresight-cti", "arm,primecell"; 2799 reg = <0x0 0x06a11000 0x0 0x1000>; 2800 2801 clocks = <&aoss_qmp>; 2802 clock-names = "apb_pclk"; 2803 }; 2804 2805 funnel@6a05000 { 2806 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2807 reg = <0x0 0x06a05000 0x0 0x1000>; 2808 2809 clocks = <&aoss_qmp>; 2810 clock-names = "apb_pclk"; 2811 2812 in-ports { 2813 port { 2814 funnel_ddr_0_in: endpoint { 2815 remote-endpoint = <&tpdm_ddr_out>; 2816 }; 2817 }; 2818 }; 2819 2820 out-ports { 2821 port { 2822 funnel_ddr_0_out: endpoint { 2823 remote-endpoint = <&tpda_qdss_in5>; 2824 }; 2825 }; 2826 }; 2827 }; 2828 2829 tpda@6b01000 { 2830 compatible = "qcom,coresight-tpda", "arm,primecell"; 2831 reg = <0x0 0x06b01000 0x0 0x1000>; 2832 2833 clocks = <&aoss_qmp>; 2834 clock-names = "apb_pclk"; 2835 2836 in-ports { 2837 #address-cells = <1>; 2838 #size-cells = <0>; 2839 2840 port@0 { 2841 reg = <0>; 2842 2843 tpda_swao_in0: endpoint { 2844 remote-endpoint = <&tpdm_swao0_out>; 2845 }; 2846 }; 2847 2848 port@1 { 2849 reg = <1>; 2850 2851 tpda_swao_in1: endpoint { 2852 remote-endpoint = <&tpdm_swao1_out>; 2853 }; 2854 2855 }; 2856 }; 2857 2858 out-ports { 2859 port { 2860 tpda_swao_out: endpoint { 2861 remote-endpoint = <&funnel_swao_in7>; 2862 }; 2863 }; 2864 }; 2865 }; 2866 2867 tpdm@6b02000 { 2868 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2869 reg = <0x0 0x06b02000 0x0 0x1000>; 2870 2871 clocks = <&aoss_qmp>; 2872 clock-names = "apb_pclk"; 2873 2874 qcom,cmb-element-bits = <64>; 2875 qcom,cmb-msrs-num = <32>; 2876 status = "disabled"; 2877 2878 out-ports { 2879 port { 2880 tpdm_swao0_out: endpoint { 2881 remote-endpoint = <&tpda_swao_in0>; 2882 }; 2883 }; 2884 }; 2885 }; 2886 2887 tpdm@6b03000 { 2888 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2889 reg = <0x0 0x06b03000 0x0 0x1000>; 2890 2891 clocks = <&aoss_qmp>; 2892 clock-names = "apb_pclk"; 2893 2894 qcom,dsb-element-bits = <32>; 2895 qcom,dsb-msrs-num = <32>; 2896 status = "disabled"; 2897 2898 out-ports { 2899 port { 2900 tpdm_swao1_out: endpoint { 2901 remote-endpoint = <&tpda_swao_in1>; 2902 }; 2903 }; 2904 }; 2905 }; 2906 2907 cti@6b04000 { 2908 compatible = "arm,coresight-cti", "arm,primecell"; 2909 reg = <0x0 0x06b04000 0x0 0x1000>; 2910 2911 clocks = <&aoss_qmp>; 2912 clock-names = "apb_pclk"; 2913 }; 2914 2915 cti@6b05000 { 2916 compatible = "arm,coresight-cti", "arm,primecell"; 2917 reg = <0x0 0x06b05000 0x0 0x1000>; 2918 2919 clocks = <&aoss_qmp>; 2920 clock-names = "apb_pclk"; 2921 }; 2922 2923 cti@6b06000 { 2924 compatible = "arm,coresight-cti", "arm,primecell"; 2925 reg = <0x0 0x06b06000 0x0 0x1000>; 2926 2927 clocks = <&aoss_qmp>; 2928 clock-names = "apb_pclk"; 2929 }; 2930 2931 cti@6b07000 { 2932 compatible = "arm,coresight-cti", "arm,primecell"; 2933 reg = <0x0 0x06b07000 0x0 0x1000>; 2934 2935 clocks = <&aoss_qmp>; 2936 clock-names = "apb_pclk"; 2937 }; 2938 2939 funnel@6b08000 { 2940 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2941 reg = <0x0 0x06b08000 0x0 0x1000>; 2942 2943 clocks = <&aoss_qmp>; 2944 clock-names = "apb_pclk"; 2945 2946 in-ports { 2947 #address-cells = <1>; 2948 #size-cells = <0>; 2949 2950 port@6 { 2951 reg = <6>; 2952 2953 funnel_swao_in6: endpoint { 2954 remote-endpoint = <&replicator1_out>; 2955 }; 2956 }; 2957 2958 port@7 { 2959 reg = <7>; 2960 2961 funnel_swao_in7: endpoint { 2962 remote-endpoint = <&tpda_swao_out>; 2963 }; 2964 }; 2965 }; 2966 2967 out-ports { 2968 port { 2969 funnel_swao_out: endpoint { 2970 remote-endpoint = <&tmc_etf_swao_in>; 2971 }; 2972 }; 2973 }; 2974 }; 2975 2976 tmc@6b09000 { 2977 compatible = "arm,coresight-tmc", "arm,primecell"; 2978 reg = <0x0 0x06b09000 0x0 0x1000>; 2979 2980 clocks = <&aoss_qmp>; 2981 clock-names = "apb_pclk"; 2982 2983 in-ports { 2984 port { 2985 tmc_etf_swao_in: endpoint { 2986 remote-endpoint = <&funnel_swao_out>; 2987 }; 2988 }; 2989 }; 2990 2991 out-ports { 2992 port { 2993 tmc_etf_swao_out: endpoint { 2994 remote-endpoint = <&replicator_swao_in>; 2995 }; 2996 }; 2997 }; 2998 }; 2999 3000 replicator@6b0a000 { 3001 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3002 reg = <0x0 0x06b0a000 0x0 0x1000>; 3003 3004 clocks = <&aoss_qmp>; 3005 clock-names = "apb_pclk"; 3006 3007 in-ports { 3008 port { 3009 replicator_swao_in: endpoint { 3010 remote-endpoint = <&tmc_etf_swao_out>; 3011 }; 3012 }; 3013 }; 3014 3015 out-ports { 3016 #address-cells = <1>; 3017 #size-cells = <0>; 3018 3019 port@0 { 3020 reg = <0>; 3021 3022 replicator_swao_out0: endpoint { 3023 remote-endpoint = <&funnel_in1_in3>; 3024 }; 3025 }; 3026 3027 port@1 { 3028 reg = <1>; 3029 3030 replicator_swao_out1: endpoint { 3031 remote-endpoint = <&eud_in>; 3032 }; 3033 }; 3034 }; 3035 }; 3036 3037 cti@6b21000 { 3038 compatible = "arm,coresight-cti", "arm,primecell"; 3039 reg = <0x0 0x06b21000 0x0 0x1000>; 3040 3041 clocks = <&aoss_qmp>; 3042 clock-names = "apb_pclk"; 3043 }; 3044 3045 tpdm@6b48000 { 3046 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3047 reg = <0x0 0x06b48000 0x0 0x1000>; 3048 3049 clocks = <&aoss_qmp>; 3050 clock-names = "apb_pclk"; 3051 3052 qcom,dsb-element-bits = <32>; 3053 qcom,dsb-msrs-num = <32>; 3054 3055 out-ports { 3056 port { 3057 tpdm_west_out: endpoint { 3058 remote-endpoint = <&tpda_qdss_in12>; 3059 }; 3060 }; 3061 }; 3062 }; 3063 3064 cti@6c13000 { 3065 compatible = "arm,coresight-cti", "arm,primecell"; 3066 reg = <0x0 0x06c13000 0x0 0x1000>; 3067 3068 clocks = <&aoss_qmp>; 3069 clock-names = "apb_pclk"; 3070 3071 /* Not all required clocks can be enabled from the OS */ 3072 status = "fail"; 3073 }; 3074 3075 cti@6c20000 { 3076 compatible = "arm,coresight-cti", "arm,primecell"; 3077 reg = <0x0 0x06c20000 0x0 0x1000>; 3078 3079 clocks = <&aoss_qmp>; 3080 clock-names = "apb_pclk"; 3081 status = "disabled"; 3082 }; 3083 3084 tpdm@6c28000 { 3085 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3086 reg = <0x0 0x06c28000 0x0 0x1000>; 3087 3088 clocks = <&aoss_qmp>; 3089 clock-names = "apb_pclk"; 3090 3091 qcom,dsb-element-bits = <32>; 3092 qcom,dsb-msrs-num = <32>; 3093 3094 out-ports { 3095 port { 3096 tpdm_center_out: endpoint { 3097 remote-endpoint = <&tpda_qdss_in0>; 3098 }; 3099 }; 3100 }; 3101 }; 3102 3103 cti@6c29000 { 3104 compatible = "arm,coresight-cti", "arm,primecell"; 3105 reg = <0x0 0x06c29000 0x0 0x1000>; 3106 3107 clocks = <&aoss_qmp>; 3108 clock-names = "apb_pclk"; 3109 }; 3110 3111 cti@6c2a000 { 3112 compatible = "arm,coresight-cti", "arm,primecell"; 3113 reg = <0x0 0x06c2a000 0x0 0x1000>; 3114 3115 clocks = <&aoss_qmp>; 3116 clock-names = "apb_pclk"; 3117 }; 3118 3119 cti@7020000 { 3120 compatible = "arm,coresight-cti", "arm,primecell"; 3121 reg = <0x0 0x07020000 0x0 0x1000>; 3122 3123 clocks = <&aoss_qmp>; 3124 clock-names = "apb_pclk"; 3125 }; 3126 3127 etm@7040000 { 3128 compatible = "arm,primecell"; 3129 reg = <0x0 0x07040000 0x0 0x1000>; 3130 cpu = <&cpu0>; 3131 3132 clocks = <&aoss_qmp>; 3133 clock-names = "apb_pclk"; 3134 3135 arm,coresight-loses-context-with-cpu; 3136 qcom,skip-power-up; 3137 3138 out-ports { 3139 port { 3140 etm0_out: endpoint { 3141 remote-endpoint = <&funnel_apss_in0>; 3142 }; 3143 }; 3144 }; 3145 }; 3146 3147 cti@7120000 { 3148 compatible = "arm,coresight-cti", "arm,primecell"; 3149 reg = <0x0 0x07120000 0x0 0x1000>; 3150 3151 clocks = <&aoss_qmp>; 3152 clock-names = "apb_pclk"; 3153 }; 3154 3155 etm@7140000 { 3156 compatible = "arm,primecell"; 3157 reg = <0x0 0x07140000 0x0 0x1000>; 3158 cpu = <&cpu1>; 3159 3160 clocks = <&aoss_qmp>; 3161 clock-names = "apb_pclk"; 3162 3163 arm,coresight-loses-context-with-cpu; 3164 qcom,skip-power-up; 3165 3166 out-ports { 3167 port { 3168 etm1_out: endpoint { 3169 remote-endpoint = <&funnel_apss_in1>; 3170 }; 3171 }; 3172 }; 3173 }; 3174 3175 cti@7220000 { 3176 compatible = "arm,coresight-cti", "arm,primecell"; 3177 reg = <0x0 0x07220000 0x0 0x1000>; 3178 3179 clocks = <&aoss_qmp>; 3180 clock-names = "apb_pclk"; 3181 }; 3182 3183 etm@7240000 { 3184 compatible = "arm,primecell"; 3185 reg = <0x0 0x07240000 0x0 0x1000>; 3186 cpu = <&cpu2>; 3187 3188 clocks = <&aoss_qmp>; 3189 clock-names = "apb_pclk"; 3190 3191 arm,coresight-loses-context-with-cpu; 3192 qcom,skip-power-up; 3193 3194 out-ports { 3195 port { 3196 etm2_out: endpoint { 3197 remote-endpoint = <&funnel_apss_in2>; 3198 }; 3199 }; 3200 }; 3201 }; 3202 3203 cti@7320000 { 3204 compatible = "arm,coresight-cti", "arm,primecell"; 3205 reg = <0x0 0x07320000 0x0 0x1000>; 3206 3207 clocks = <&aoss_qmp>; 3208 clock-names = "apb_pclk"; 3209 }; 3210 3211 etm@7340000 { 3212 compatible = "arm,primecell"; 3213 reg = <0x0 0x07340000 0x0 0x1000>; 3214 cpu = <&cpu3>; 3215 3216 clocks = <&aoss_qmp>; 3217 clock-names = "apb_pclk"; 3218 3219 arm,coresight-loses-context-with-cpu; 3220 qcom,skip-power-up; 3221 3222 out-ports { 3223 port { 3224 etm3_out: endpoint { 3225 remote-endpoint = <&funnel_apss_in3>; 3226 }; 3227 }; 3228 }; 3229 }; 3230 3231 cti@7420000 { 3232 compatible = "arm,coresight-cti", "arm,primecell"; 3233 reg = <0x0 0x07420000 0x0 0x1000>; 3234 3235 clocks = <&aoss_qmp>; 3236 clock-names = "apb_pclk"; 3237 }; 3238 3239 etm@7440000 { 3240 compatible = "arm,primecell"; 3241 reg = <0x0 0x07440000 0x0 0x1000>; 3242 cpu = <&cpu4>; 3243 3244 clocks = <&aoss_qmp>; 3245 clock-names = "apb_pclk"; 3246 3247 arm,coresight-loses-context-with-cpu; 3248 qcom,skip-power-up; 3249 3250 out-ports { 3251 port { 3252 etm4_out: endpoint { 3253 remote-endpoint = <&funnel_apss_in4>; 3254 }; 3255 }; 3256 }; 3257 }; 3258 3259 cti@7520000 { 3260 compatible = "arm,coresight-cti", "arm,primecell"; 3261 reg = <0x0 0x07520000 0x0 0x1000>; 3262 3263 clocks = <&aoss_qmp>; 3264 clock-names = "apb_pclk"; 3265 }; 3266 3267 etm@7540000 { 3268 compatible = "arm,primecell"; 3269 reg = <0x0 0x07540000 0x0 0x1000>; 3270 cpu = <&cpu5>; 3271 3272 clocks = <&aoss_qmp>; 3273 clock-names = "apb_pclk"; 3274 3275 arm,coresight-loses-context-with-cpu; 3276 qcom,skip-power-up; 3277 3278 out-ports { 3279 port { 3280 etm5_out: endpoint { 3281 remote-endpoint = <&funnel_apss_in5>; 3282 }; 3283 }; 3284 }; 3285 }; 3286 3287 cti@7620000 { 3288 compatible = "arm,coresight-cti", "arm,primecell"; 3289 reg = <0x0 0x07620000 0x0 0x1000>; 3290 3291 clocks = <&aoss_qmp>; 3292 clock-names = "apb_pclk"; 3293 }; 3294 3295 etm@7640000 { 3296 compatible = "arm,primecell"; 3297 reg = <0x0 0x07640000 0x0 0x1000>; 3298 cpu = <&cpu6>; 3299 3300 clocks = <&aoss_qmp>; 3301 clock-names = "apb_pclk"; 3302 3303 arm,coresight-loses-context-with-cpu; 3304 qcom,skip-power-up; 3305 3306 out-ports { 3307 port { 3308 etm6_out: endpoint { 3309 remote-endpoint = <&funnel_apss_in6>; 3310 }; 3311 }; 3312 }; 3313 }; 3314 3315 cti@7720000 { 3316 compatible = "arm,coresight-cti", "arm,primecell"; 3317 reg = <0x0 0x07720000 0x0 0x1000>; 3318 3319 clocks = <&aoss_qmp>; 3320 clock-names = "apb_pclk"; 3321 }; 3322 3323 etm@7740000 { 3324 compatible = "arm,primecell"; 3325 reg = <0x0 0x07740000 0x0 0x1000>; 3326 cpu = <&cpu7>; 3327 3328 clocks = <&aoss_qmp>; 3329 clock-names = "apb_pclk"; 3330 3331 arm,coresight-loses-context-with-cpu; 3332 qcom,skip-power-up; 3333 3334 out-ports { 3335 port { 3336 etm7_out: endpoint { 3337 remote-endpoint = <&funnel_apss_in7>; 3338 }; 3339 }; 3340 }; 3341 }; 3342 3343 funnel@7800000 { 3344 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3345 reg = <0x0 0x07800000 0x0 0x1000>; 3346 3347 clocks = <&aoss_qmp>; 3348 clock-names = "apb_pclk"; 3349 3350 in-ports { 3351 #address-cells = <1>; 3352 #size-cells = <0>; 3353 3354 port@0 { 3355 reg = <0>; 3356 3357 funnel_apss_in0: endpoint { 3358 remote-endpoint = <&etm0_out>; 3359 }; 3360 }; 3361 3362 port@1 { 3363 reg = <1>; 3364 3365 funnel_apss_in1: endpoint { 3366 remote-endpoint = <&etm1_out>; 3367 }; 3368 }; 3369 3370 port@2 { 3371 reg = <2>; 3372 3373 funnel_apss_in2: endpoint { 3374 remote-endpoint = <&etm2_out>; 3375 }; 3376 }; 3377 3378 port@3 { 3379 reg = <3>; 3380 3381 funnel_apss_in3: endpoint { 3382 remote-endpoint = <&etm3_out>; 3383 }; 3384 }; 3385 3386 port@4 { 3387 reg = <4>; 3388 3389 funnel_apss_in4: endpoint { 3390 remote-endpoint = <&etm4_out>; 3391 }; 3392 }; 3393 3394 port@5 { 3395 reg = <5>; 3396 3397 funnel_apss_in5: endpoint { 3398 remote-endpoint = <&etm5_out>; 3399 }; 3400 }; 3401 3402 port@6 { 3403 reg = <6>; 3404 3405 funnel_apss_in6: endpoint { 3406 remote-endpoint = <&etm6_out>; 3407 }; 3408 }; 3409 3410 port@7 { 3411 reg = <7>; 3412 3413 funnel_apss_in7: endpoint { 3414 remote-endpoint = <&etm7_out>; 3415 }; 3416 }; 3417 }; 3418 3419 out-ports { 3420 port { 3421 funnel_apss_out: endpoint { 3422 remote-endpoint = <&funnel_apss_merg_in0>; 3423 }; 3424 }; 3425 }; 3426 }; 3427 3428 funnel@7810000 { 3429 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3430 reg = <0x0 0x07810000 0x0 0x1000>; 3431 3432 clocks = <&aoss_qmp>; 3433 clock-names = "apb_pclk"; 3434 3435 in-ports { 3436 #address-cells = <1>; 3437 #size-cells = <0>; 3438 3439 port@0 { 3440 reg = <0>; 3441 3442 funnel_apss_merg_in0: endpoint { 3443 remote-endpoint = <&funnel_apss_out>; 3444 }; 3445 }; 3446 3447 port@2 { 3448 reg = <2>; 3449 3450 funnel_apss_merg_in2: endpoint { 3451 remote-endpoint = <&tpda_olc_out>; 3452 }; 3453 }; 3454 3455 port@3 { 3456 reg = <3>; 3457 3458 funnel_apss_merg_in3: endpoint { 3459 remote-endpoint = <&tpda_llm_silver_out>; 3460 }; 3461 }; 3462 3463 port@4 { 3464 reg = <4>; 3465 3466 funnel_apss_merg_in4: endpoint { 3467 remote-endpoint = <&tpda_llm_gold_out>; 3468 }; 3469 }; 3470 3471 port@5 { 3472 reg = <5>; 3473 3474 funnel_apss_merg_in5: endpoint { 3475 remote-endpoint = <&tpda_apss_out>; 3476 }; 3477 }; 3478 }; 3479 3480 out-ports { 3481 port { 3482 funnel_apss_merg_out: endpoint { 3483 remote-endpoint = <&funnel_in1_in7>; 3484 }; 3485 }; 3486 }; 3487 }; 3488 3489 tpdm@7830000 { 3490 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3491 reg = <0x0 0x07830000 0x0 0x1000>; 3492 3493 clocks = <&aoss_qmp>; 3494 clock-names = "apb_pclk"; 3495 3496 qcom,cmb-element-bits = <64>; 3497 qcom,cmb-msrs-num = <32>; 3498 3499 out-ports { 3500 port { 3501 tpdm_olc_out: endpoint { 3502 remote-endpoint = <&tpda_olc_in>; 3503 }; 3504 }; 3505 }; 3506 }; 3507 3508 tpda@7832000 { 3509 compatible = "qcom,coresight-tpda", "arm,primecell"; 3510 reg = <0x0 0x07832000 0x0 0x1000>; 3511 3512 clocks = <&aoss_qmp>; 3513 clock-names = "apb_pclk"; 3514 3515 in-ports { 3516 port { 3517 tpda_olc_in: endpoint { 3518 remote-endpoint = <&tpdm_olc_out>; 3519 }; 3520 }; 3521 }; 3522 3523 out-ports { 3524 port { 3525 tpda_olc_out: endpoint { 3526 remote-endpoint = <&funnel_apss_merg_in2>; 3527 }; 3528 }; 3529 }; 3530 }; 3531 3532 tpdm@7860000 { 3533 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3534 reg = <0x0 0x07860000 0x0 0x1000>; 3535 3536 clocks = <&aoss_qmp>; 3537 clock-names = "apb_pclk"; 3538 3539 qcom,dsb-element-bits = <32>; 3540 qcom,dsb-msrs-num = <32>; 3541 3542 out-ports { 3543 port { 3544 tpdm_apss_out: endpoint { 3545 remote-endpoint = <&tpda_apss_in>; 3546 }; 3547 }; 3548 }; 3549 }; 3550 3551 tpda@7862000 { 3552 compatible = "qcom,coresight-tpda", "arm,primecell"; 3553 reg = <0x0 0x07862000 0x0 0x1000>; 3554 3555 clocks = <&aoss_qmp>; 3556 clock-names = "apb_pclk"; 3557 3558 in-ports { 3559 port { 3560 tpda_apss_in: endpoint { 3561 remote-endpoint = <&tpdm_apss_out>; 3562 }; 3563 }; 3564 }; 3565 3566 out-ports { 3567 port { 3568 tpda_apss_out: endpoint { 3569 remote-endpoint = <&funnel_apss_merg_in5>; 3570 }; 3571 }; 3572 }; 3573 }; 3574 3575 tpdm@78a0000 { 3576 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3577 reg = <0x0 0x078a0000 0x0 0x1000>; 3578 3579 clocks = <&aoss_qmp>; 3580 clock-names = "apb_pclk"; 3581 3582 qcom,cmb-element-bits = <32>; 3583 qcom,cmb-msrs-num = <32>; 3584 3585 out-ports { 3586 port { 3587 tpdm_llm_silver_out: endpoint { 3588 remote-endpoint = <&tpda_llm_silver_in>; 3589 }; 3590 }; 3591 }; 3592 }; 3593 3594 tpdm@78b0000 { 3595 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3596 reg = <0x0 0x078b0000 0x0 0x1000>; 3597 3598 clocks = <&aoss_qmp>; 3599 clock-names = "apb_pclk"; 3600 3601 qcom,cmb-element-bits = <32>; 3602 qcom,cmb-msrs-num = <32>; 3603 3604 out-ports { 3605 port { 3606 tpdm_llm_gold_out: endpoint { 3607 remote-endpoint = <&tpda_llm_gold_in>; 3608 }; 3609 }; 3610 }; 3611 }; 3612 3613 tpda@78c0000 { 3614 compatible = "qcom,coresight-tpda", "arm,primecell"; 3615 reg = <0x0 0x078c0000 0x0 0x1000>; 3616 3617 clocks = <&aoss_qmp>; 3618 clock-names = "apb_pclk"; 3619 3620 in-ports { 3621 port { 3622 tpda_llm_silver_in: endpoint { 3623 remote-endpoint = <&tpdm_llm_silver_out>; 3624 }; 3625 }; 3626 }; 3627 3628 out-ports { 3629 port { 3630 tpda_llm_silver_out: endpoint { 3631 remote-endpoint = <&funnel_apss_merg_in3>; 3632 }; 3633 }; 3634 }; 3635 }; 3636 3637 tpda@78d0000 { 3638 compatible = "qcom,coresight-tpda", "arm,primecell"; 3639 reg = <0x0 0x078d0000 0x0 0x1000>; 3640 3641 clocks = <&aoss_qmp>; 3642 clock-names = "apb_pclk"; 3643 3644 in-ports { 3645 port { 3646 tpda_llm_gold_in: endpoint { 3647 remote-endpoint = <&tpdm_llm_gold_out>; 3648 }; 3649 }; 3650 }; 3651 3652 out-ports { 3653 port { 3654 tpda_llm_gold_out: endpoint { 3655 remote-endpoint = <&funnel_apss_merg_in4>; 3656 }; 3657 }; 3658 }; 3659 }; 3660 3661 cti@78e0000 { 3662 compatible = "arm,coresight-cti", "arm,primecell"; 3663 reg = <0x0 0x078e0000 0x0 0x1000>; 3664 3665 clocks = <&aoss_qmp>; 3666 clock-names = "apb_pclk"; 3667 }; 3668 3669 cti@78f0000 { 3670 compatible = "arm,coresight-cti", "arm,primecell"; 3671 reg = <0x0 0x078f0000 0x0 0x1000>; 3672 3673 clocks = <&aoss_qmp>; 3674 clock-names = "apb_pclk"; 3675 }; 3676 3677 cti@7900000 { 3678 compatible = "arm,coresight-cti", "arm,primecell"; 3679 reg = <0x0 0x07900000 0x0 0x1000>; 3680 3681 clocks = <&aoss_qmp>; 3682 clock-names = "apb_pclk"; 3683 }; 3684 3685 remoteproc_cdsp: remoteproc@8300000 { 3686 compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas"; 3687 reg = <0x0 0x08300000 0x0 0x4040>; 3688 3689 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, 3690 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3691 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3692 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3693 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3694 interrupt-names = "wdog", 3695 "fatal", 3696 "ready", 3697 "handover", 3698 "stop-ack"; 3699 3700 clocks = <&rpmhcc RPMH_CXO_CLK>; 3701 clock-names = "xo"; 3702 3703 power-domains = <&rpmhpd RPMHPD_CX>; 3704 power-domain-names = "cx"; 3705 3706 memory-region = <&rproc_cdsp_mem>; 3707 3708 qcom,qmp = <&aoss_qmp>; 3709 3710 qcom,smem-states = <&cdsp_smp2p_out 0>; 3711 qcom,smem-state-names = "stop"; 3712 3713 status = "disabled"; 3714 3715 glink-edge { 3716 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING 0>; 3717 mboxes = <&apss_shared 4>; 3718 label = "cdsp"; 3719 qcom,remote-pid = <5>; 3720 3721 fastrpc { 3722 compatible = "qcom,fastrpc"; 3723 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3724 label = "cdsp"; 3725 #address-cells = <1>; 3726 #size-cells = <0>; 3727 3728 compute-cb@1 { 3729 compatible = "qcom,fastrpc-compute-cb"; 3730 reg = <1>; 3731 iommus = <&apps_smmu 0x1081 0x0>; 3732 dma-coherent; 3733 }; 3734 3735 compute-cb@2 { 3736 compatible = "qcom,fastrpc-compute-cb"; 3737 reg = <2>; 3738 iommus = <&apps_smmu 0x1082 0x0>; 3739 dma-coherent; 3740 }; 3741 3742 compute-cb@3 { 3743 compatible = "qcom,fastrpc-compute-cb"; 3744 reg = <3>; 3745 iommus = <&apps_smmu 0x1083 0x0>; 3746 dma-coherent; 3747 }; 3748 3749 compute-cb@4 { 3750 compatible = "qcom,fastrpc-compute-cb"; 3751 reg = <4>; 3752 iommus = <&apps_smmu 0x1084 0x0>; 3753 dma-coherent; 3754 }; 3755 3756 compute-cb@5 { 3757 compatible = "qcom,fastrpc-compute-cb"; 3758 reg = <5>; 3759 iommus = <&apps_smmu 0x1085 0x0>; 3760 dma-coherent; 3761 }; 3762 3763 compute-cb@6 { 3764 compatible = "qcom,fastrpc-compute-cb"; 3765 reg = <6>; 3766 iommus = <&apps_smmu 0x1086 0x0>; 3767 dma-coherent; 3768 }; 3769 }; 3770 }; 3771 }; 3772 3773 pmu@90b6300 { 3774 compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon"; 3775 reg = <0x0 0x090b6300 0x0 0x600>; 3776 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>; 3777 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3778 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3779 3780 operating-points-v2 = <&cpu_bwmon_opp_table>; 3781 3782 cpu_bwmon_opp_table: opp-table { 3783 compatible = "operating-points-v2"; 3784 3785 opp-0 { 3786 opp-peak-kBps = <12896000>; 3787 }; 3788 3789 opp-1 { 3790 opp-peak-kBps = <14928000>; 3791 }; 3792 }; 3793 }; 3794 3795 pmu@90cd000 { 3796 compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3797 reg = <0x0 0x090cd000 0x0 0x1000>; 3798 interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH 0>; 3799 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 3800 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3801 3802 operating-points-v2 = <&llcc_bwmon_opp_table>; 3803 3804 llcc_bwmon_opp_table: opp-table { 3805 compatible = "operating-points-v2"; 3806 3807 opp-0 { 3808 opp-peak-kBps = <800000>; 3809 }; 3810 3811 opp-1 { 3812 opp-peak-kBps = <1200000>; 3813 }; 3814 3815 opp-2 { 3816 opp-peak-kBps = <1804800>; 3817 }; 3818 3819 opp-3 { 3820 opp-peak-kBps = <2188800>; 3821 }; 3822 3823 opp-4 { 3824 opp-peak-kBps = <2726400>; 3825 }; 3826 3827 opp-5 { 3828 opp-peak-kBps = <3072000>; 3829 }; 3830 3831 opp-6 { 3832 opp-peak-kBps = <4070400>; 3833 }; 3834 3835 opp-7 { 3836 opp-peak-kBps = <5414400>; 3837 }; 3838 3839 opp-8 { 3840 opp-peak-kBps = <6220800>; 3841 }; 3842 }; 3843 }; 3844 3845 sdhc_2: mmc@8804000 { 3846 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 3847 reg = <0x0 0x08804000 0x0 0x1000>; 3848 reg-names = "hc"; 3849 3850 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>, 3851 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; 3852 interrupt-names = "hc_irq", 3853 "pwr_irq"; 3854 3855 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3856 <&gcc GCC_SDCC2_APPS_CLK>, 3857 <&rpmhcc RPMH_CXO_CLK>; 3858 clock-names = "iface", 3859 "core", 3860 "xo"; 3861 3862 power-domains = <&rpmhpd RPMHPD_CX>; 3863 operating-points-v2 = <&sdhc2_opp_table>; 3864 iommus = <&apps_smmu 0x02a0 0x0>; 3865 resets = <&gcc GCC_SDCC2_BCR>; 3866 interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3867 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3868 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3869 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 3870 interconnect-names = "sdhc-ddr", 3871 "cpu-sdhc"; 3872 3873 qcom,dll-config = <0x0007642c>; 3874 qcom,ddr-config = <0x80040868>; 3875 dma-coherent; 3876 3877 status = "disabled"; 3878 3879 sdhc2_opp_table: opp-table { 3880 compatible = "operating-points-v2"; 3881 3882 opp-50000000 { 3883 opp-hz = /bits/ 64 <50000000>; 3884 required-opps = <&rpmhpd_opp_low_svs>; 3885 }; 3886 3887 opp-100000000 { 3888 opp-hz = /bits/ 64 <100000000>; 3889 required-opps = <&rpmhpd_opp_svs>; 3890 }; 3891 3892 opp-202000000 { 3893 opp-hz = /bits/ 64 <202000000>; 3894 required-opps = <&rpmhpd_opp_nom>; 3895 }; 3896 }; 3897 }; 3898 3899 dc_noc: interconnect@9160000 { 3900 reg = <0x0 0x09160000 0x0 0x3200>; 3901 compatible = "qcom,qcs615-dc-noc"; 3902 #interconnect-cells = <2>; 3903 qcom,bcm-voters = <&apps_bcm_voter>; 3904 }; 3905 3906 llcc: system-cache-controller@9200000 { 3907 compatible = "qcom,qcs615-llcc"; 3908 reg = <0x0 0x09200000 0x0 0x50000>, 3909 <0x0 0x09600000 0x0 0x50000>; 3910 reg-names = "llcc0_base", 3911 "llcc_broadcast_base"; 3912 }; 3913 3914 gem_noc: interconnect@9680000 { 3915 reg = <0x0 0x09680000 0x0 0x3e200>; 3916 compatible = "qcom,qcs615-gem-noc"; 3917 #interconnect-cells = <2>; 3918 qcom,bcm-voters = <&apps_bcm_voter>; 3919 }; 3920 3921 venus: video-codec@aa00000 { 3922 compatible = "qcom,qcs615-venus", "qcom,sc7180-venus"; 3923 reg = <0x0 0x0aa00000 0x0 0x100000>; 3924 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; 3925 3926 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3927 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3928 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3929 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3930 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 3931 clock-names = "core", 3932 "iface", 3933 "bus", 3934 "vcodec0_core", 3935 "vcodec0_bus"; 3936 3937 power-domains = <&videocc VENUS_GDSC>, 3938 <&videocc VCODEC0_GDSC>, 3939 <&rpmhpd RPMHPD_CX>; 3940 power-domain-names = "venus", 3941 "vcodec0", 3942 "cx"; 3943 3944 operating-points-v2 = <&venus_opp_table>; 3945 3946 interconnects = <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 3947 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3948 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3949 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3950 interconnect-names = "video-mem", 3951 "cpu-cfg"; 3952 3953 iommus = <&apps_smmu 0xe60 0x20>; 3954 3955 memory-region = <&pil_video_mem>; 3956 3957 status = "disabled"; 3958 3959 venus_opp_table: opp-table { 3960 compatible = "operating-points-v2"; 3961 3962 opp-133330000 { 3963 opp-hz = /bits/ 64 <133330000>; 3964 required-opps = <&rpmhpd_opp_low_svs>; 3965 }; 3966 3967 opp-240000000 { 3968 opp-hz = /bits/ 64 <240000000>; 3969 required-opps = <&rpmhpd_opp_svs>; 3970 }; 3971 3972 opp-300000000 { 3973 opp-hz = /bits/ 64 <300000000>; 3974 required-opps = <&rpmhpd_opp_svs_l1>; 3975 }; 3976 3977 opp-380000000 { 3978 opp-hz = /bits/ 64 <380000000>; 3979 required-opps = <&rpmhpd_opp_nom>; 3980 }; 3981 3982 opp-410000000 { 3983 opp-hz = /bits/ 64 <410000000>; 3984 required-opps = <&rpmhpd_opp_nom_l1>; 3985 }; 3986 3987 opp-460000000 { 3988 opp-hz = /bits/ 64 <460000000>; 3989 required-opps = <&rpmhpd_opp_turbo>; 3990 }; 3991 }; 3992 }; 3993 3994 videocc: clock-controller@ab00000 { 3995 compatible = "qcom,qcs615-videocc"; 3996 reg = <0 0x0ab00000 0 0x10000>; 3997 3998 clocks = <&rpmhcc RPMH_CXO_CLK>, 3999 <&sleep_clk>; 4000 4001 #clock-cells = <1>; 4002 #reset-cells = <1>; 4003 #power-domain-cells = <1>; 4004 }; 4005 4006 cci: cci@ac4a000 { 4007 compatible = "qcom,sm6150-cci", "qcom,msm8996-cci"; 4008 4009 reg = <0x0 0x0ac4a000 0x0 0x4000>; 4010 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING 0>; 4011 power-domains = <&camcc TITAN_TOP_GDSC>; 4012 clocks = <&camcc CAM_CC_SOC_AHB_CLK>, 4013 <&camcc CAM_CC_CPAS_AHB_CLK>, 4014 <&camcc CAM_CC_CCI_CLK>; 4015 clock-names = "camnoc_axi", 4016 "cpas_ahb", 4017 "cci"; 4018 pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>; 4019 pinctrl-names = "default"; 4020 4021 #address-cells = <1>; 4022 #size-cells = <0>; 4023 4024 status = "disabled"; 4025 4026 cci_i2c0: i2c-bus@0 { 4027 reg = <0>; 4028 clock-frequency = <1000000>; 4029 #address-cells = <1>; 4030 #size-cells = <0>; 4031 }; 4032 4033 cci_i2c1: i2c-bus@1 { 4034 reg = <1>; 4035 clock-frequency = <1000000>; 4036 #address-cells = <1>; 4037 #size-cells = <0>; 4038 }; 4039 }; 4040 4041 camss: isp@acb3000 { 4042 compatible = "qcom,sm6150-camss"; 4043 4044 reg = <0x0 0x0acb3000 0x0 0x1000>, 4045 <0x0 0x0acba000 0x0 0x1000>, 4046 <0x0 0x0acc8000 0x0 0x1000>, 4047 <0x0 0x0ac65000 0x0 0x1000>, 4048 <0x0 0x0ac66000 0x0 0x1000>, 4049 <0x0 0x0ac67000 0x0 0x1000>, 4050 <0x0 0x0acaf000 0x0 0x4000>, 4051 <0x0 0x0acb6000 0x0 0x4000>, 4052 <0x0 0x0acc4000 0x0 0x4000>, 4053 <0x0 0x0ac6f000 0x0 0x3000>, 4054 <0x0 0x0ac42000 0x0 0x5000>, 4055 <0x0 0x0ac48000 0x0 0x1000>, 4056 <0x0 0x0ac40000 0x0 0x1000>, 4057 <0x0 0x0ac18000 0x0 0x3000>, 4058 <0x0 0x0ac00000 0x0 0x6000>, 4059 <0x0 0x0ac10000 0x0 0x8000>, 4060 <0x0 0x0ac87000 0x0 0x3000>, 4061 <0x0 0x0ac52000 0x0 0x4000>, 4062 <0x0 0x0ac4e000 0x0 0x4000>, 4063 <0x0 0x0ac6b000 0x0 0x0a00>; 4064 reg-names = "csid0", 4065 "csid1", 4066 "csid_lite", 4067 "csiphy0", 4068 "csiphy1", 4069 "csiphy2", 4070 "vfe0", 4071 "vfe1", 4072 "vfe_lite", 4073 "bps", 4074 "camnoc", 4075 "cpas_cdm", 4076 "cpas_top", 4077 "icp_csr", 4078 "icp_qgic", 4079 "icp_sierra", 4080 "ipe0", 4081 "jpeg_dma", 4082 "jpeg_enc", 4083 "lrme"; 4084 4085 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4086 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4087 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4088 <&camcc CAM_CC_CPAS_AHB_CLK>, 4089 <&camcc CAM_CC_CSIPHY0_CLK>, 4090 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4091 <&camcc CAM_CC_CSIPHY1_CLK>, 4092 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4093 <&camcc CAM_CC_CSIPHY2_CLK>, 4094 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4095 <&camcc CAM_CC_SOC_AHB_CLK>, 4096 <&camcc CAM_CC_IFE_0_CLK>, 4097 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4098 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4099 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4100 <&camcc CAM_CC_IFE_1_CLK>, 4101 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4102 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4103 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4104 <&camcc CAM_CC_IFE_LITE_CLK>, 4105 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4106 <&camcc CAM_CC_IFE_LITE_CSID_CLK>, 4107 <&camcc CAM_CC_BPS_CLK>, 4108 <&camcc CAM_CC_BPS_AHB_CLK>, 4109 <&camcc CAM_CC_BPS_AXI_CLK>, 4110 <&camcc CAM_CC_BPS_AREG_CLK>, 4111 <&camcc CAM_CC_ICP_CLK>, 4112 <&camcc CAM_CC_IPE_0_CLK>, 4113 <&camcc CAM_CC_IPE_0_AHB_CLK>, 4114 <&camcc CAM_CC_IPE_0_AREG_CLK>, 4115 <&camcc CAM_CC_IPE_0_AXI_CLK>, 4116 <&camcc CAM_CC_JPEG_CLK>, 4117 <&camcc CAM_CC_LRME_CLK>; 4118 clock-names = "gcc_ahb", 4119 "gcc_axi_hf", 4120 "camnoc_axi", 4121 "cpas_ahb", 4122 "csiphy0", 4123 "csiphy0_timer", 4124 "csiphy1", 4125 "csiphy1_timer", 4126 "csiphy2", 4127 "csiphy2_timer", 4128 "soc_ahb", 4129 "vfe0", 4130 "vfe0_axi", 4131 "vfe0_cphy_rx", 4132 "vfe0_csid", 4133 "vfe1", 4134 "vfe1_axi", 4135 "vfe1_cphy_rx", 4136 "vfe1_csid", 4137 "vfe_lite", 4138 "vfe_lite_cphy_rx", 4139 "vfe_lite_csid", 4140 "bps", 4141 "bps_ahb", 4142 "bps_axi", 4143 "bps_areg", 4144 "icp", 4145 "ipe0", 4146 "ipe0_ahb", 4147 "ipe0_areg", 4148 "ipe0_axi", 4149 "jpeg", 4150 "lrme"; 4151 4152 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4153 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4154 <&mmss_noc MASTER_CAMNOC_HF0 QCOM_ICC_TAG_ALWAYS 4155 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4156 <&mmss_noc MASTER_CAMNOC_HF1 QCOM_ICC_TAG_ALWAYS 4157 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4158 <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS 4159 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4160 interconnect-names = "ahb", 4161 "hf_0", 4162 "hf_1", 4163 "sf_mnoc"; 4164 4165 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING 0>, 4166 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING 0>, 4167 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING 0>, 4168 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>, 4169 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>, 4170 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>, 4171 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING 0>, 4172 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING 0>, 4173 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING 0>, 4174 <GIC_SPI 459 IRQ_TYPE_EDGE_RISING 0>, 4175 <GIC_SPI 461 IRQ_TYPE_EDGE_RISING 0>, 4176 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING 0>, 4177 <GIC_SPI 475 IRQ_TYPE_EDGE_RISING 0>, 4178 <GIC_SPI 474 IRQ_TYPE_EDGE_RISING 0>, 4179 <GIC_SPI 476 IRQ_TYPE_EDGE_RISING 0>; 4180 interrupt-names = "csid0", 4181 "csid1", 4182 "csid_lite", 4183 "csiphy0", 4184 "csiphy1", 4185 "csiphy2", 4186 "vfe0", 4187 "vfe1", 4188 "vfe_lite", 4189 "camnoc", 4190 "cdm", 4191 "icp", 4192 "jpeg_dma", 4193 "jpeg_enc", 4194 "lrme"; 4195 4196 iommus = <&apps_smmu 0x0820 0x40>, 4197 <&apps_smmu 0x0840 0x00>, 4198 <&apps_smmu 0x0860 0x40>, 4199 <&apps_smmu 0x0c00 0x00>, 4200 <&apps_smmu 0x0cc0 0x00>, 4201 <&apps_smmu 0x0c80 0x00>, 4202 <&apps_smmu 0x0ca0 0x00>, 4203 <&apps_smmu 0x0d00 0x00>, 4204 <&apps_smmu 0x0d20 0x00>, 4205 <&apps_smmu 0x0d40 0x00>, 4206 <&apps_smmu 0x0d80 0x20>, 4207 <&apps_smmu 0x0da0 0x20>, 4208 <&apps_smmu 0x0de2 0x00>; 4209 4210 power-domains = <&camcc IFE_0_GDSC>, 4211 <&camcc IFE_1_GDSC>, 4212 <&camcc TITAN_TOP_GDSC>, 4213 <&camcc BPS_GDSC>, 4214 <&camcc IPE_0_GDSC>; 4215 power-domain-names = "ife0", 4216 "ife1", 4217 "top", 4218 "bps", 4219 "ipe"; 4220 4221 status = "disabled"; 4222 4223 ports { 4224 #address-cells = <1>; 4225 #size-cells = <0>; 4226 4227 port@0 { 4228 reg = <0>; 4229 }; 4230 4231 port@1 { 4232 reg = <1>; 4233 }; 4234 4235 port@2 { 4236 reg = <2>; 4237 }; 4238 }; 4239 }; 4240 4241 camcc: clock-controller@ad00000 { 4242 compatible = "qcom,qcs615-camcc"; 4243 reg = <0 0x0ad00000 0 0x10000>; 4244 4245 clocks = <&rpmhcc RPMH_CXO_CLK>; 4246 4247 #clock-cells = <1>; 4248 #reset-cells = <1>; 4249 #power-domain-cells = <1>; 4250 }; 4251 4252 mdss: display-subsystem@ae00000 { 4253 compatible = "qcom,sm6150-mdss"; 4254 reg = <0x0 0x0ae00000 0x0 0x1000>; 4255 reg-names = "mdss"; 4256 4257 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 4258 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4259 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4260 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4261 interconnect-names = "mdp0-mem", 4262 "cpu-cfg"; 4263 4264 power-domains = <&dispcc MDSS_CORE_GDSC>; 4265 4266 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4267 <&gcc GCC_DISP_HF_AXI_CLK>, 4268 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4269 4270 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>; 4271 interrupt-controller; 4272 #interrupt-cells = <1>; 4273 4274 iommus = <&apps_smmu 0x800 0x0>; 4275 4276 #address-cells = <2>; 4277 #size-cells = <2>; 4278 ranges; 4279 4280 status = "disabled"; 4281 4282 mdss_mdp: display-controller@ae01000 { 4283 compatible = "qcom,sm6150-dpu"; 4284 reg = <0x0 0x0ae01000 0x0 0x8f000>, 4285 <0x0 0x0aeb0000 0x0 0x2008>; 4286 reg-names = "mdp", 4287 "vbif"; 4288 4289 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4290 <&gcc GCC_DISP_HF_AXI_CLK>, 4291 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4292 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4293 clock-names = "iface", 4294 "bus", 4295 "core", 4296 "vsync"; 4297 4298 operating-points-v2 = <&mdp_opp_table>; 4299 power-domains = <&rpmhpd RPMHPD_CX>; 4300 4301 interrupts-extended = <&mdss 0>; 4302 4303 ports { 4304 #address-cells = <1>; 4305 #size-cells = <0>; 4306 4307 port@0 { 4308 reg = <0>; 4309 4310 dpu_intf0_out: endpoint { 4311 remote-endpoint = <&mdss_dp0_in>; 4312 }; 4313 }; 4314 4315 port@1 { 4316 reg = <1>; 4317 4318 dpu_intf1_out: endpoint { 4319 remote-endpoint = <&mdss_dsi0_in>; 4320 }; 4321 }; 4322 }; 4323 4324 mdp_opp_table: opp-table { 4325 compatible = "operating-points-v2"; 4326 4327 opp-192000000 { 4328 opp-hz = /bits/ 64 <192000000>; 4329 required-opps = <&rpmhpd_opp_low_svs>; 4330 }; 4331 4332 opp-256000000 { 4333 opp-hz = /bits/ 64 <256000000>; 4334 required-opps = <&rpmhpd_opp_svs>; 4335 }; 4336 4337 opp-307200000 { 4338 opp-hz = /bits/ 64 <307200000>; 4339 required-opps = <&rpmhpd_opp_nom>; 4340 }; 4341 }; 4342 }; 4343 4344 mdss_dp0: displayport-controller@ae90000 { 4345 compatible = "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp"; 4346 4347 reg = <0x0 0x0ae90000 0x0 0x200>, 4348 <0x0 0x0ae90200 0x0 0x200>, 4349 <0x0 0x0ae90400 0x0 0x600>, 4350 <0x0 0x0ae90a00 0x0 0x600>, 4351 <0x0 0x0ae91000 0x0 0x600>; 4352 4353 interrupt-parent = <&mdss>; 4354 interrupts = <12>; 4355 4356 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4357 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4358 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4359 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4360 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, 4361 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; 4362 clock-names = "core_iface", 4363 "core_aux", 4364 "ctrl_link", 4365 "ctrl_link_iface", 4366 "stream_pixel", 4367 "stream_1_pixel"; 4368 4369 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4370 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, 4371 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; 4372 assigned-clock-parents = <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, 4373 <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>, 4374 <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; 4375 4376 phys = <&usb_qmpphy_2 QMP_USB43DP_DP_PHY>; 4377 phy-names = "dp"; 4378 4379 operating-points-v2 = <&dp_opp_table>; 4380 power-domains = <&rpmhpd RPMHPD_CX>; 4381 4382 #sound-dai-cells = <0>; 4383 4384 status = "disabled"; 4385 4386 ports { 4387 #address-cells = <1>; 4388 #size-cells = <0>; 4389 4390 port@0 { 4391 reg = <0>; 4392 4393 mdss_dp0_in: endpoint { 4394 remote-endpoint = <&dpu_intf0_out>; 4395 }; 4396 }; 4397 4398 port@1 { 4399 reg = <1>; 4400 4401 mdss_dp0_out: endpoint { 4402 data-lanes = <3 2 0 1>; 4403 }; 4404 }; 4405 }; 4406 4407 dp_opp_table: opp-table { 4408 compatible = "operating-points-v2"; 4409 4410 opp-162000000 { 4411 opp-hz = /bits/ 64 <162000000>; 4412 required-opps = <&rpmhpd_opp_low_svs>; 4413 }; 4414 4415 opp-270000000 { 4416 opp-hz = /bits/ 64 <270000000>; 4417 required-opps = <&rpmhpd_opp_svs>; 4418 }; 4419 4420 opp-540000000 { 4421 opp-hz = /bits/ 64 <540000000>; 4422 required-opps = <&rpmhpd_opp_svs_l1>; 4423 }; 4424 }; 4425 }; 4426 4427 mdss_dsi0: dsi@ae94000 { 4428 compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 4429 reg = <0x0 0x0ae94000 0x0 0x400>; 4430 reg-names = "dsi_ctrl"; 4431 4432 interrupts-extended = <&mdss 4>; 4433 4434 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4435 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4436 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4437 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4438 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4439 <&gcc GCC_DISP_HF_AXI_CLK>; 4440 clock-names = "byte", 4441 "byte_intf", 4442 "pixel", 4443 "core", 4444 "iface", 4445 "bus"; 4446 4447 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 4448 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4449 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4450 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 4451 4452 operating-points-v2 = <&dsi0_opp_table>; 4453 power-domains = <&rpmhpd RPMHPD_CX>; 4454 4455 phys = <&mdss_dsi0_phy>; 4456 4457 #address-cells = <1>; 4458 #size-cells = <0>; 4459 4460 status = "disabled"; 4461 4462 dsi0_opp_table: opp-table { 4463 compatible = "operating-points-v2"; 4464 4465 opp-164000000 { 4466 opp-hz = /bits/ 64 <164000000>; 4467 required-opps = <&rpmhpd_opp_low_svs>; 4468 }; 4469 }; 4470 4471 ports { 4472 #address-cells = <1>; 4473 #size-cells = <0>; 4474 4475 port@0 { 4476 reg = <0>; 4477 4478 mdss_dsi0_in: endpoint { 4479 remote-endpoint = <&dpu_intf1_out>; 4480 }; 4481 }; 4482 4483 port@1 { 4484 reg = <1>; 4485 4486 mdss_dsi0_out: endpoint { 4487 }; 4488 }; 4489 }; 4490 }; 4491 4492 mdss_dsi0_phy: phy@ae94400 { 4493 compatible = "qcom,sm6150-dsi-phy-14nm"; 4494 reg = <0x0 0x0ae94400 0x0 0x100>, 4495 <0x0 0x0ae94500 0x0 0x300>, 4496 <0x0 0x0ae94800 0x0 0x124>; 4497 reg-names = "dsi_phy", 4498 "dsi_phy_lane", 4499 "dsi_pll"; 4500 4501 #clock-cells = <1>; 4502 #phy-cells = <0>; 4503 4504 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4505 <&rpmhcc RPMH_CXO_CLK>; 4506 clock-names = "iface", 4507 "ref"; 4508 4509 status = "disabled"; 4510 }; 4511 }; 4512 4513 dispcc: clock-controller@af00000 { 4514 compatible = "qcom,qcs615-dispcc"; 4515 reg = <0 0x0af00000 0 0x20000>; 4516 4517 clocks = <&rpmhcc RPMH_CXO_CLK>, 4518 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4519 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4520 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 4521 <0>, 4522 <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, 4523 <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; 4524 4525 #clock-cells = <1>; 4526 #reset-cells = <1>; 4527 #power-domain-cells = <1>; 4528 }; 4529 4530 pdc: interrupt-controller@b220000 { 4531 compatible = "qcom,qcs615-pdc", "qcom,pdc"; 4532 reg = <0x0 0x0b220000 0x0 0x30000>, 4533 <0x0 0x17c000f0 0x0 0x64>; 4534 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 4535 interrupt-parent = <&intc>; 4536 #interrupt-cells = <2>; 4537 interrupt-controller; 4538 }; 4539 4540 aoss_qmp: power-management@c300000 { 4541 compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp"; 4542 reg = <0x0 0x0c300000 0x0 0x400>; 4543 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING 0>; 4544 mboxes = <&apss_shared 0>; 4545 4546 #clock-cells = <0>; 4547 }; 4548 4549 sram@c3f0000 { 4550 compatible = "qcom,rpmh-stats"; 4551 reg = <0x0 0x0c3f0000 0x0 0x400>; 4552 }; 4553 4554 sram@14680000 { 4555 compatible = "qcom,qcs615-imem", "syscon", "simple-mfd"; 4556 reg = <0x0 0x14680000 0x0 0x2c000>; 4557 ranges = <0 0 0x14680000 0x2c000>; 4558 4559 #address-cells = <1>; 4560 #size-cells = <1>; 4561 4562 pil-reloc@2a94c { 4563 compatible = "qcom,pil-reloc-info"; 4564 reg = <0x2a94c 0xc8>; 4565 }; 4566 }; 4567 4568 apps_smmu: iommu@15000000 { 4569 compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4570 reg = <0x0 0x15000000 0x0 0x80000>; 4571 #iommu-cells = <2>; 4572 #global-interrupts = <1>; 4573 dma-coherent; 4574 4575 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, 4576 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>, 4577 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>, 4578 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>, 4579 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, 4580 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, 4581 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, 4582 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, 4583 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 4584 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, 4585 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 4586 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 4587 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, 4588 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, 4589 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 4590 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 4591 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 4592 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, 4593 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, 4594 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, 4595 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, 4596 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 4597 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, 4598 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, 4599 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, 4600 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, 4601 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, 4602 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, 4603 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, 4604 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, 4605 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, 4606 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, 4607 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, 4608 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, 4609 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, 4610 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, 4611 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, 4612 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, 4613 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, 4614 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, 4615 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, 4616 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, 4617 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, 4618 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, 4619 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, 4620 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, 4621 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, 4622 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, 4623 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, 4624 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, 4625 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, 4626 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, 4627 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, 4628 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, 4629 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, 4630 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, 4631 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, 4632 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, 4633 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, 4634 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, 4635 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, 4636 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, 4637 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, 4638 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, 4639 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 4640 }; 4641 4642 spmi_bus: spmi@c440000 { 4643 compatible = "qcom,spmi-pmic-arb"; 4644 reg = <0x0 0x0c440000 0x0 0x1100>, 4645 <0x0 0x0c600000 0x0 0x2000000>, 4646 <0x0 0x0e600000 0x0 0x100000>, 4647 <0x0 0x0e700000 0x0 0xa0000>, 4648 <0x0 0x0c40a000 0x0 0x26000>; 4649 reg-names = "core", 4650 "chnls", 4651 "obsrvr", 4652 "intr", 4653 "cnfg"; 4654 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4655 interrupt-names = "periph_irq"; 4656 interrupt-controller; 4657 #interrupt-cells = <4>; 4658 #address-cells = <2>; 4659 #size-cells = <0>; 4660 qcom,channel = <0>; 4661 qcom,ee = <0>; 4662 }; 4663 4664 intc: interrupt-controller@17a00000 { 4665 compatible = "arm,gic-v3"; 4666 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4667 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4668 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 4669 #address-cells = <0>; 4670 #interrupt-cells = <4>; 4671 interrupt-controller; 4672 #redistributor-regions = <1>; 4673 redistributor-stride = <0x0 0x20000>; 4674 4675 ppi-partitions { 4676 ppi_cluster0: interrupt-partition-0 { 4677 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 4678 }; 4679 4680 ppi_cluster1: interrupt-partition-1 { 4681 affinity = <&cpu6 &cpu7>; 4682 }; 4683 }; 4684 }; 4685 4686 apss_shared: mailbox@17c00000 { 4687 compatible = "qcom,qcs615-apss-shared", 4688 "qcom,sdm845-apss-shared"; 4689 reg = <0x0 0x17c00000 0x0 0x1000>; 4690 #mbox-cells = <1>; 4691 }; 4692 4693 watchdog: watchdog@17c10000 { 4694 compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt"; 4695 reg = <0x0 0x17c10000 0x0 0x1000>; 4696 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>; 4697 clocks = <&sleep_clk>; 4698 }; 4699 4700 timer@17c20000 { 4701 compatible = "arm,armv7-timer-mem"; 4702 reg = <0x0 0x17c20000 0x0 0x1000>; 4703 ranges = <0 0 0 0x20000000>; 4704 #address-cells = <1>; 4705 #size-cells = <1>; 4706 4707 frame@17c21000 { 4708 reg = <0x17c21000 0x1000>, 4709 <0x17c22000 0x1000>; 4710 frame-number = <0>; 4711 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, 4712 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 4713 }; 4714 4715 frame@17c23000 { 4716 reg = <0x17c23000 0x1000>; 4717 frame-number = <1>; 4718 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 4719 status = "disabled"; 4720 }; 4721 4722 frame@17c25000 { 4723 reg = <0x17c25000 0x1000>; 4724 frame-number = <2>; 4725 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 4726 status = "disabled"; 4727 }; 4728 4729 frame@17c27000 { 4730 reg = <0x17c27000 0x1000>; 4731 frame-number = <3>; 4732 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 4733 status = "disabled"; 4734 }; 4735 4736 frame@17c29000 { 4737 reg = <0x17c29000 0x1000>; 4738 frame-number = <4>; 4739 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 4740 status = "disabled"; 4741 }; 4742 4743 frame@17c2b000 { 4744 reg = <0x17c2b000 0x1000>; 4745 frame-number = <5>; 4746 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; 4747 status = "disabled"; 4748 }; 4749 4750 frame@17c2d000 { 4751 reg = <0x17c2d000 0x1000>; 4752 frame-number = <6>; 4753 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 4754 status = "disabled"; 4755 }; 4756 }; 4757 4758 apps_rsc: rsc@18200000 { 4759 compatible = "qcom,rpmh-rsc"; 4760 reg = <0x0 0x18200000 0x0 0x10000>, 4761 <0x0 0x18210000 0x0 0x10000>, 4762 <0x0 0x18220000 0x0 0x10000>; 4763 reg-names = "drv-0", 4764 "drv-1", 4765 "drv-2"; 4766 4767 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, 4768 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, 4769 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; 4770 4771 qcom,drv-id = <2>; 4772 qcom,tcs-offset = <0xd00>; 4773 qcom,tcs-config = <ACTIVE_TCS 2>, 4774 <SLEEP_TCS 3>, 4775 <WAKE_TCS 3>, 4776 <CONTROL_TCS 1>; 4777 4778 label = "apps_rsc"; 4779 power-domains = <&cluster_pd>; 4780 4781 apps_bcm_voter: bcm-voter { 4782 compatible = "qcom,bcm-voter"; 4783 }; 4784 4785 rpmhcc: clock-controller { 4786 compatible = "qcom,qcs615-rpmh-clk"; 4787 clocks = <&xo_board_clk>; 4788 clock-names = "xo"; 4789 4790 #clock-cells = <1>; 4791 }; 4792 4793 rpmhpd: power-controller { 4794 compatible = "qcom,qcs615-rpmhpd"; 4795 #power-domain-cells = <1>; 4796 operating-points-v2 = <&rpmhpd_opp_table>; 4797 4798 rpmhpd_opp_table: opp-table { 4799 compatible = "operating-points-v2"; 4800 4801 rpmhpd_opp_ret: opp-0 { 4802 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4803 }; 4804 4805 rpmhpd_opp_min_svs: opp-1 { 4806 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4807 }; 4808 4809 rpmhpd_opp_low_svs: opp-2 { 4810 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4811 }; 4812 4813 rpmhpd_opp_svs: opp-3 { 4814 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4815 }; 4816 4817 rpmhpd_opp_svs_l1: opp-4 { 4818 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4819 }; 4820 4821 rpmhpd_opp_nom: opp-5 { 4822 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4823 }; 4824 4825 rpmhpd_opp_nom_l1: opp-6 { 4826 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4827 }; 4828 4829 rpmhpd_opp_nom_l2: opp-7 { 4830 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4831 }; 4832 4833 rpmhpd_opp_turbo: opp-8 { 4834 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4835 }; 4836 4837 rpmhpd_opp_turbo_l1: opp-9 { 4838 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4839 }; 4840 }; 4841 }; 4842 }; 4843 4844 osm_l3: interconnect@18321000 { 4845 compatible = "qcom,qcs615-osm-l3", "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4846 reg = <0x0 0x18321000 0x0 0x1400>; 4847 4848 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4849 clock-names = "xo", "alternate"; 4850 4851 #interconnect-cells = <1>; 4852 }; 4853 4854 usb_1_hsphy: phy@88e2000 { 4855 compatible = "qcom,qcs615-qusb2-phy"; 4856 reg = <0x0 0x88e2000 0x0 0x180>; 4857 4858 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>; 4859 clock-names = "cfg_ahb", "ref"; 4860 4861 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4862 nvmem-cells = <&qusb2_hstx_trim>; 4863 4864 #phy-cells = <0>; 4865 4866 status = "disabled"; 4867 }; 4868 4869 usb_2_hsphy: phy@88e3000 { 4870 compatible = "qcom,qcs615-qusb2-phy"; 4871 reg = <0x0 0x088e3000 0x0 0x180>; 4872 4873 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, 4874 <&rpmhcc RPMH_CXO_CLK>; 4875 clock-names = "cfg_ahb", 4876 "ref"; 4877 4878 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 4879 4880 #phy-cells = <0>; 4881 4882 status = "disabled"; 4883 }; 4884 4885 usb_qmpphy: phy@88e6000 { 4886 compatible = "qcom,qcs615-qmp-usb3-phy"; 4887 reg = <0x0 0x88e6000 0x0 0x1000>; 4888 4889 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4890 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 4891 <&gcc GCC_AHB2PHY_WEST_CLK>, 4892 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4893 clock-names = "aux", 4894 "ref", 4895 "cfg_ahb", 4896 "pipe"; 4897 4898 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 4899 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 4900 reset-names = "phy", "phy_phy"; 4901 4902 qcom,tcsr-reg = <&tcsr 0xb244>; 4903 4904 clock-output-names = "usb3_phy_pipe_clk_src"; 4905 #clock-cells = <0>; 4906 4907 #phy-cells = <0>; 4908 4909 status = "disabled"; 4910 }; 4911 4912 usb_qmpphy_2: phy@88e8000 { 4913 compatible = "qcom,qcs615-qmp-usb3-dp-phy"; 4914 reg = <0x0 0x088e8000 0x0 0x2000>; 4915 4916 clocks = <&gcc GCC_USB2_SEC_PHY_AUX_CLK>, 4917 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 4918 <&gcc GCC_AHB2PHY_WEST_CLK>, 4919 <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>; 4920 clock-names = "aux", 4921 "ref", 4922 "cfg_ahb", 4923 "pipe"; 4924 4925 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >, 4926 <&gcc GCC_USB3_DP_PHY_SEC_BCR>; 4927 reset-names = "phy_phy", 4928 "dp_phy"; 4929 4930 #clock-cells = <1>; 4931 #phy-cells = <1>; 4932 4933 qcom,tcsr-reg = <&tcsr 0xbff0 0xb24c>; 4934 4935 status = "disabled"; 4936 }; 4937 4938 usb_1: usb@a600000 { 4939 compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; 4940 reg = <0x0 0x0a600000 0x0 0xfc100>; 4941 4942 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4943 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4944 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4945 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4946 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4947 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 4948 clock-names = "cfg_noc", 4949 "core", 4950 "iface", 4951 "sleep", 4952 "mock_utmi", 4953 "xo"; 4954 4955 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4956 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4957 assigned-clock-rates = <19200000>, <200000000>; 4958 4959 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, 4960 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, 4961 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, 4962 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 4963 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 4964 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 4965 interrupt-names = "dwc_usb3", 4966 "pwr_event", 4967 "hs_phy_irq", 4968 "dp_hs_phy_irq", 4969 "dm_hs_phy_irq", 4970 "ss_phy_irq"; 4971 4972 iommus = <&apps_smmu 0x140 0x0>; 4973 4974 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 4975 phy-names = "usb2-phy", "usb3-phy"; 4976 4977 power-domains = <&gcc USB30_PRIM_GDSC>; 4978 required-opps = <&rpmhpd_opp_nom>; 4979 4980 resets = <&gcc GCC_USB30_PRIM_BCR>; 4981 4982 snps,dis-u1-entry-quirk; 4983 snps,dis-u2-entry-quirk; 4984 snps,dis_u2_susphy_quirk; 4985 snps,dis_u3_susphy_quirk; 4986 snps,dis_enblslpm_quirk; 4987 snps,has-lpm-erratum; 4988 snps,hird-threshold = /bits/ 8 <0x10>; 4989 snps,usb3_lpm_capable; 4990 4991 wakeup-source; 4992 4993 status = "disabled"; 4994 }; 4995 4996 usb_2: usb@a800000 { 4997 compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; 4998 reg = <0x0 0x0a800000 0x0 0xfc100>; 4999 5000 clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, 5001 <&gcc GCC_USB20_SEC_MASTER_CLK>, 5002 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, 5003 <&gcc GCC_USB20_SEC_SLEEP_CLK>, 5004 <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 5005 <&gcc GCC_USB2_PRIM_CLKREF_CLK>; 5006 clock-names = "cfg_noc", 5007 "core", 5008 "iface", 5009 "sleep", 5010 "mock_utmi", 5011 "xo"; 5012 5013 assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 5014 <&gcc GCC_USB20_SEC_MASTER_CLK>; 5015 assigned-clock-rates = <19200000>, <200000000>; 5016 5017 interrupts-extended = <&intc GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, 5018 <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, 5019 <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>, 5020 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 5021 <&pdc 10 IRQ_TYPE_EDGE_BOTH>; 5022 interrupt-names = "dwc_usb3", 5023 "pwr_event", 5024 "hs_phy_irq", 5025 "dp_hs_phy_irq", 5026 "dm_hs_phy_irq"; 5027 5028 iommus = <&apps_smmu 0xe0 0x0>; 5029 5030 phys = <&usb_2_hsphy>; 5031 phy-names = "usb2-phy"; 5032 5033 power-domains = <&gcc USB20_SEC_GDSC>; 5034 required-opps = <&rpmhpd_opp_nom>; 5035 5036 resets = <&gcc GCC_USB20_SEC_BCR>; 5037 5038 qcom,select-utmi-as-pipe-clk; 5039 5040 snps,dis_u2_susphy_quirk; 5041 snps,dis_u3_susphy_quirk; 5042 snps,dis_enblslpm_quirk; 5043 snps,has-lpm-erratum; 5044 snps,hird-threshold = /bits/ 8 <0x10>; 5045 5046 maximum-speed = "high-speed"; 5047 wakeup-source; 5048 5049 status = "disabled"; 5050 }; 5051 5052 tsens0: thermal-sensor@c263000 { 5053 compatible = "qcom,qcs615-tsens", "qcom,tsens-v2"; 5054 reg = <0x0 0x0c263000 0x0 0x1000>, 5055 <0x0 0x0c222000 0x0 0x1000>; 5056 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>, 5057 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>; 5058 interrupt-names = "uplow", "critical"; 5059 #qcom,sensors = <16>; 5060 #thermal-sensor-cells = <1>; 5061 }; 5062 5063 remoteproc_adsp: remoteproc@62400000 { 5064 compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas"; 5065 reg = <0x0 0x62400000 0x0 0x4040>; 5066 5067 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING 0>, 5068 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 5069 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 5070 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 5071 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 5072 interrupt-names = "wdog", 5073 "fatal", 5074 "ready", 5075 "handover", 5076 "stop-ack"; 5077 5078 clocks = <&rpmhcc RPMH_CXO_CLK>; 5079 clock-names = "xo"; 5080 5081 power-domains = <&rpmhpd RPMHPD_CX>; 5082 power-domain-names = "cx"; 5083 5084 memory-region = <&rproc_adsp_mem>; 5085 5086 qcom,qmp = <&aoss_qmp>; 5087 5088 qcom,smem-states = <&adsp_smp2p_out 0>; 5089 qcom,smem-state-names = "stop"; 5090 5091 status = "disabled"; 5092 5093 glink_edge: glink-edge { 5094 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING 0>; 5095 mboxes = <&apss_shared 24>; 5096 label = "lpass"; 5097 qcom,remote-pid = <2>; 5098 5099 fastrpc { 5100 compatible = "qcom,fastrpc"; 5101 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5102 label = "adsp"; 5103 #address-cells = <1>; 5104 #size-cells = <0>; 5105 5106 compute-cb@3 { 5107 compatible = "qcom,fastrpc-compute-cb"; 5108 reg = <3>; 5109 iommus = <&apps_smmu 0x1723 0x0>; 5110 dma-coherent; 5111 }; 5112 5113 compute-cb@4 { 5114 compatible = "qcom,fastrpc-compute-cb"; 5115 reg = <4>; 5116 iommus = <&apps_smmu 0x1724 0x0>; 5117 dma-coherent; 5118 }; 5119 5120 compute-cb@5 { 5121 compatible = "qcom,fastrpc-compute-cb"; 5122 reg = <5>; 5123 iommus = <&apps_smmu 0x1725 0x0>; 5124 dma-coherent; 5125 }; 5126 5127 compute-cb@6 { 5128 compatible = "qcom,fastrpc-compute-cb"; 5129 reg = <6>; 5130 iommus = <&apps_smmu 0x1726 0x0>; 5131 qcom,nsessions = <5>; 5132 dma-coherent; 5133 }; 5134 }; 5135 }; 5136 }; 5137 5138 cpufreq_hw: cpufreq@18323000 { 5139 compatible = "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw"; 5140 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 5141 reg-names = "freq-domain0", "freq-domain1"; 5142 5143 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5144 clock-names = "xo", "alternate"; 5145 5146 #freq-domain-cells = <1>; 5147 #clock-cells = <1>; 5148 }; 5149 }; 5150 5151 arch_timer: timer { 5152 compatible = "arm,armv8-timer"; 5153 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW 0>, 5154 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>, 5155 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW 0>, 5156 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW 0>; 5157 }; 5158 5159 thermal-zones { 5160 aoss-thermal { 5161 thermal-sensors = <&tsens0 0>; 5162 5163 trips { 5164 aoss-critical { 5165 temperature = <115000>; 5166 hysteresis = <1000>; 5167 type = "critical"; 5168 }; 5169 }; 5170 }; 5171 5172 cpuss-0-thermal { 5173 thermal-sensors = <&tsens0 1>; 5174 5175 trips { 5176 cpuss0-critical { 5177 temperature = <115000>; 5178 hysteresis = <1000>; 5179 type = "critical"; 5180 }; 5181 }; 5182 }; 5183 5184 cpuss-1-thermal { 5185 thermal-sensors = <&tsens0 2>; 5186 5187 trips { 5188 cpuss1-critical { 5189 temperature = <115000>; 5190 hysteresis = <1000>; 5191 type = "critical"; 5192 }; 5193 }; 5194 }; 5195 5196 cpuss-2-thermal { 5197 thermal-sensors = <&tsens0 3>; 5198 5199 trips { 5200 cpuss2-critical { 5201 temperature = <115000>; 5202 hysteresis = <1000>; 5203 type = "critical"; 5204 }; 5205 }; 5206 }; 5207 5208 cpuss-3-thermal { 5209 thermal-sensors = <&tsens0 4>; 5210 5211 trips { 5212 cpuss3-critical { 5213 temperature = <115000>; 5214 hysteresis = <1000>; 5215 type = "critical"; 5216 }; 5217 }; 5218 }; 5219 5220 cpu-1-0-thermal { 5221 thermal-sensors = <&tsens0 5>; 5222 5223 trips { 5224 cpu-critical { 5225 temperature = <115000>; 5226 hysteresis = <1000>; 5227 type = "critical"; 5228 }; 5229 }; 5230 }; 5231 5232 cpu-1-1-thermal { 5233 thermal-sensors = <&tsens0 6>; 5234 5235 trips { 5236 cpu-critical { 5237 temperature = <115000>; 5238 hysteresis = <1000>; 5239 type = "critical"; 5240 }; 5241 }; 5242 }; 5243 5244 cpu-1-2-thermal { 5245 thermal-sensors = <&tsens0 7>; 5246 5247 trips { 5248 cpu-critical { 5249 temperature = <115000>; 5250 hysteresis = <1000>; 5251 type = "critical"; 5252 }; 5253 }; 5254 }; 5255 5256 cpu-1-3-thermal { 5257 thermal-sensors = <&tsens0 8>; 5258 5259 trips { 5260 cpu-critical { 5261 temperature = <115000>; 5262 hysteresis = <1000>; 5263 type = "critical"; 5264 }; 5265 }; 5266 }; 5267 5268 gpu-thermal { 5269 thermal-sensors = <&tsens0 9>; 5270 5271 trips { 5272 gpu_alert0: trip-point0 { 5273 temperature = <105000>; 5274 hysteresis = <5000>; 5275 type = "passive"; 5276 }; 5277 5278 gpu-critical { 5279 temperature = <115000>; 5280 hysteresis = <1000>; 5281 type = "critical"; 5282 }; 5283 }; 5284 5285 cooling-maps { 5286 map0 { 5287 trip = <&gpu_alert0>; 5288 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5289 }; 5290 }; 5291 }; 5292 5293 q6-hvx-thermal { 5294 thermal-sensors = <&tsens0 10>; 5295 5296 trips { 5297 q6-hvx-critical { 5298 temperature = <115000>; 5299 hysteresis = <1000>; 5300 type = "critical"; 5301 }; 5302 }; 5303 }; 5304 5305 mdm-core-thermal { 5306 thermal-sensors = <&tsens0 11>; 5307 5308 trips { 5309 mdm-core-critical { 5310 temperature = <115000>; 5311 hysteresis = <1000>; 5312 type = "critical"; 5313 }; 5314 }; 5315 }; 5316 5317 camera-thermal { 5318 thermal-sensors = <&tsens0 12>; 5319 5320 trips { 5321 camera-critical { 5322 temperature = <115000>; 5323 hysteresis = <1000>; 5324 type = "critical"; 5325 }; 5326 }; 5327 }; 5328 5329 wlan-thermal { 5330 thermal-sensors = <&tsens0 13>; 5331 5332 trips { 5333 wlan-critical { 5334 temperature = <115000>; 5335 hysteresis = <1000>; 5336 type = "critical"; 5337 }; 5338 }; 5339 }; 5340 5341 display-thermal { 5342 thermal-sensors = <&tsens0 14>; 5343 5344 trips { 5345 display-critical { 5346 temperature = <115000>; 5347 hysteresis = <1000>; 5348 type = "critical"; 5349 }; 5350 }; 5351 }; 5352 5353 video-thermal { 5354 thermal-sensors = <&tsens0 15>; 5355 5356 trips { 5357 video-critical { 5358 temperature = <115000>; 5359 hysteresis = <1000>; 5360 type = "critical"; 5361 }; 5362 }; 5363 }; 5364 }; 5365}; 5366