1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,qcs615-camcc.h> 8#include <dt-bindings/clock/qcom,qcs615-dispcc.h> 9#include <dt-bindings/clock/qcom,qcs615-gcc.h> 10#include <dt-bindings/clock/qcom,qcs615-gpucc.h> 11#include <dt-bindings/clock/qcom,qcs615-videocc.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 cpus { 31 #address-cells = <2>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a55"; 37 reg = <0x0 0x0>; 38 enable-method = "psci"; 39 power-domains = <&cpu_pd0>; 40 power-domain-names = "psci"; 41 capacity-dmips-mhz = <1024>; 42 dynamic-power-coefficient = <100>; 43 next-level-cache = <&l2_0>; 44 clocks = <&cpufreq_hw 0>; 45 qcom,freq-domain = <&cpufreq_hw 0>; 46 #cooling-cells = <2>; 47 operating-points-v2 = <&cpu0_opp_table>; 48 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 49 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 50 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 51 52 l2_0: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 cache-unified; 56 next-level-cache = <&l3_0>; 57 }; 58 }; 59 60 cpu1: cpu@100 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a55"; 63 reg = <0x0 0x100>; 64 enable-method = "psci"; 65 power-domains = <&cpu_pd1>; 66 power-domain-names = "psci"; 67 capacity-dmips-mhz = <1024>; 68 dynamic-power-coefficient = <100>; 69 next-level-cache = <&l2_100>; 70 clocks = <&cpufreq_hw 0>; 71 qcom,freq-domain = <&cpufreq_hw 0>; 72 operating-points-v2 = <&cpu0_opp_table>; 73 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 74 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 75 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 76 77 l2_100: l2-cache { 78 compatible = "cache"; 79 cache-level = <2>; 80 cache-unified; 81 next-level-cache = <&l3_0>; 82 }; 83 }; 84 85 cpu2: cpu@200 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a55"; 88 reg = <0x0 0x200>; 89 enable-method = "psci"; 90 power-domains = <&cpu_pd2>; 91 power-domain-names = "psci"; 92 capacity-dmips-mhz = <1024>; 93 dynamic-power-coefficient = <100>; 94 next-level-cache = <&l2_200>; 95 clocks = <&cpufreq_hw 0>; 96 qcom,freq-domain = <&cpufreq_hw 0>; 97 operating-points-v2 = <&cpu0_opp_table>; 98 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 99 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 100 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 101 102 l2_200: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 cache-unified; 106 next-level-cache = <&l3_0>; 107 }; 108 }; 109 110 cpu3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a55"; 113 reg = <0x0 0x300>; 114 enable-method = "psci"; 115 power-domains = <&cpu_pd3>; 116 power-domain-names = "psci"; 117 capacity-dmips-mhz = <1024>; 118 dynamic-power-coefficient = <100>; 119 next-level-cache = <&l2_300>; 120 clocks = <&cpufreq_hw 0>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 operating-points-v2 = <&cpu0_opp_table>; 123 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 124 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 125 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 126 127 l2_300: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 next-level-cache = <&l3_0>; 132 }; 133 }; 134 135 cpu4: cpu@400 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a55"; 138 reg = <0x0 0x400>; 139 enable-method = "psci"; 140 power-domains = <&cpu_pd4>; 141 power-domain-names = "psci"; 142 capacity-dmips-mhz = <1024>; 143 dynamic-power-coefficient = <100>; 144 next-level-cache = <&l2_400>; 145 clocks = <&cpufreq_hw 0>; 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 operating-points-v2 = <&cpu0_opp_table>; 148 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 149 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 150 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 151 152 l2_400: l2-cache { 153 compatible = "cache"; 154 cache-level = <2>; 155 cache-unified; 156 next-level-cache = <&l3_0>; 157 }; 158 }; 159 160 cpu5: cpu@500 { 161 device_type = "cpu"; 162 compatible = "arm,cortex-a55"; 163 reg = <0x0 0x500>; 164 enable-method = "psci"; 165 power-domains = <&cpu_pd5>; 166 power-domain-names = "psci"; 167 capacity-dmips-mhz = <1024>; 168 dynamic-power-coefficient = <100>; 169 next-level-cache = <&l2_500>; 170 clocks = <&cpufreq_hw 0>; 171 qcom,freq-domain = <&cpufreq_hw 0>; 172 operating-points-v2 = <&cpu0_opp_table>; 173 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 174 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 175 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 176 177 l2_500: l2-cache { 178 compatible = "cache"; 179 cache-level = <2>; 180 cache-unified; 181 next-level-cache = <&l3_0>; 182 }; 183 }; 184 185 cpu6: cpu@600 { 186 device_type = "cpu"; 187 compatible = "arm,cortex-a76"; 188 reg = <0x0 0x600>; 189 enable-method = "psci"; 190 power-domains = <&cpu_pd6>; 191 power-domain-names = "psci"; 192 capacity-dmips-mhz = <1740>; 193 dynamic-power-coefficient = <404>; 194 next-level-cache = <&l2_600>; 195 clocks = <&cpufreq_hw 1>; 196 qcom,freq-domain = <&cpufreq_hw 1>; 197 #cooling-cells = <2>; 198 operating-points-v2 = <&cpu6_opp_table>; 199 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 200 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 201 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 202 203 l2_600: l2-cache { 204 compatible = "cache"; 205 cache-level = <2>; 206 cache-unified; 207 next-level-cache = <&l3_0>; 208 }; 209 }; 210 211 cpu7: cpu@700 { 212 device_type = "cpu"; 213 compatible = "arm,cortex-a76"; 214 reg = <0x0 0x700>; 215 enable-method = "psci"; 216 power-domains = <&cpu_pd7>; 217 power-domain-names = "psci"; 218 capacity-dmips-mhz = <1740>; 219 dynamic-power-coefficient = <404>; 220 next-level-cache = <&l2_700>; 221 clocks = <&cpufreq_hw 1>; 222 qcom,freq-domain = <&cpufreq_hw 1>; 223 operating-points-v2 = <&cpu6_opp_table>; 224 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 225 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 226 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 227 228 l2_700: l2-cache { 229 compatible = "cache"; 230 cache-level = <2>; 231 cache-unified; 232 next-level-cache = <&l3_0>; 233 }; 234 }; 235 236 cpu-map { 237 cluster0 { 238 core0 { 239 cpu = <&cpu0>; 240 }; 241 242 core1 { 243 cpu = <&cpu1>; 244 }; 245 246 core2 { 247 cpu = <&cpu2>; 248 }; 249 250 core3 { 251 cpu = <&cpu3>; 252 }; 253 254 core4 { 255 cpu = <&cpu4>; 256 }; 257 258 core5 { 259 cpu = <&cpu5>; 260 }; 261 262 core6 { 263 cpu = <&cpu6>; 264 }; 265 266 core7 { 267 cpu = <&cpu7>; 268 }; 269 }; 270 }; 271 272 l3_0: l3-cache { 273 compatible = "cache"; 274 cache-level = <3>; 275 cache-unified; 276 }; 277 }; 278 279 cpu0_opp_table: opp-table-cpu0 { 280 compatible = "operating-points-v2"; 281 opp-shared; 282 283 opp-300000000 { 284 opp-hz = /bits/ 64 <300000000>; 285 opp-peak-kBps = <(300000 * 4) (300000 * 16)>; 286 }; 287 288 opp-576000000 { 289 opp-hz = /bits/ 64 <576000000>; 290 opp-peak-kBps = <(300000 * 4) (576000 * 16)>; 291 }; 292 293 opp-748800000 { 294 opp-hz = /bits/ 64 <748800000>; 295 opp-peak-kBps = <(300000 * 4) (576000 * 16)>; 296 }; 297 298 opp-998400000 { 299 opp-hz = /bits/ 64 <998400000>; 300 opp-peak-kBps = <(451000 * 4) (806400 * 16)>; 301 }; 302 303 opp-1209600000 { 304 opp-hz = /bits/ 64 <1209600000>; 305 opp-peak-kBps = <(547000 * 4) (1017600 * 16)>; 306 }; 307 308 opp-1363200000 { 309 opp-hz = /bits/ 64 <1363200000>; 310 opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; 311 }; 312 313 opp-1516800000 { 314 opp-hz = /bits/ 64 <1516800000>; 315 opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; 316 }; 317 318 opp-1593600000 { 319 opp-hz = /bits/ 64 <1593600000>; 320 opp-peak-kBps = <(1017000 * 4) (1363200 * 16)>; 321 }; 322 }; 323 324 cpu6_opp_table: opp-table-cpu6 { 325 compatible = "operating-points-v2"; 326 opp-shared; 327 328 opp-300000000 { 329 opp-hz = /bits/ 64 <300000000>; 330 opp-peak-kBps = <(451000 * 4) (300000 * 16)>; 331 }; 332 333 opp-652800000 { 334 opp-hz = /bits/ 64 <652800000>; 335 opp-peak-kBps = <(451000 * 4) (576000 * 16)>; 336 }; 337 338 opp-768000000 { 339 opp-hz = /bits/ 64 <768000000>; 340 opp-peak-kBps = <(451000 * 4) (576000 * 16)>; 341 }; 342 343 opp-979200000 { 344 opp-hz = /bits/ 64 <979200000>; 345 opp-peak-kBps = <(547000 * 4) (806400 * 16)>; 346 }; 347 348 opp-1017600000 { 349 opp-hz = /bits/ 64 <1017600000>; 350 opp-peak-kBps = <(547000 * 4) (806400 * 16)>; 351 }; 352 353 opp-1094400000 { 354 opp-hz = /bits/ 64 <109440000>; 355 opp-peak-kBps = <(1017600 * 4) (940800 * 16)>; 356 }; 357 358 opp-1209600000 { 359 opp-hz = /bits/ 64 <1209600000>; 360 opp-peak-kBps = <(1017600 * 4) (1017600 * 16)>; 361 }; 362 363 opp-1363200000 { 364 opp-hz = /bits/ 64 <1363200000>; 365 opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; 366 }; 367 368 opp-1516800000 { 369 opp-hz = /bits/ 64 <1516800000>; 370 opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; 371 }; 372 373 opp-1708800000 { 374 opp-hz = /bits/ 64 <1708800000>; 375 opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; 376 }; 377 378 opp-1900800000 { 379 opp-hz = /bits/ 64 <1900800000>; 380 opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; 381 }; 382 }; 383 384 dummy_eud: dummy-sink { 385 compatible = "arm,coresight-dummy-sink"; 386 387 in-ports { 388 port { 389 eud_in: endpoint { 390 remote-endpoint = <&replicator_swao_out1>; 391 }; 392 }; 393 }; 394 }; 395 396 idle-states { 397 entry-method = "psci"; 398 399 little_cpu_sleep_0: cpu-sleep-0-0 { 400 compatible = "arm,idle-state"; 401 idle-state-name = "silver-power-collapse"; 402 arm,psci-suspend-param = <0x40000003>; 403 entry-latency-us = <549>; 404 exit-latency-us = <901>; 405 min-residency-us = <1774>; 406 local-timer-stop; 407 }; 408 409 little_cpu_sleep_1: cpu-sleep-0-1 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "silver-rail-power-collapse"; 412 arm,psci-suspend-param = <0x40000004>; 413 entry-latency-us = <702>; 414 exit-latency-us = <915>; 415 min-residency-us = <4001>; 416 local-timer-stop; 417 }; 418 419 big_cpu_sleep_0: cpu-sleep-1-0 { 420 compatible = "arm,idle-state"; 421 idle-state-name = "gold-power-collapse"; 422 arm,psci-suspend-param = <0x40000003>; 423 entry-latency-us = <523>; 424 exit-latency-us = <1244>; 425 min-residency-us = <2207>; 426 local-timer-stop; 427 }; 428 429 big_cpu_sleep_1: cpu-sleep-1-1 { 430 compatible = "arm,idle-state"; 431 idle-state-name = "gold-rail-power-collapse"; 432 arm,psci-suspend-param = <0x40000004>; 433 entry-latency-us = <526>; 434 exit-latency-us = <1854>; 435 min-residency-us = <5555>; 436 local-timer-stop; 437 }; 438 }; 439 440 domain-idle-states { 441 cluster_sleep_0: cluster-sleep-0 { 442 compatible = "domain-idle-state"; 443 arm,psci-suspend-param = <0x41000044>; 444 entry-latency-us = <2752>; 445 exit-latency-us = <3048>; 446 min-residency-us = <6118>; 447 }; 448 449 cluster_sleep_1: cluster-sleep-1 { 450 compatible = "domain-idle-state"; 451 arm,psci-suspend-param = <0x41001344>; 452 entry-latency-us = <3263>; 453 exit-latency-us = <4562>; 454 min-residency-us = <8467>; 455 }; 456 457 cluster_sleep_2: cluster-sleep-2 { 458 compatible = "domain-idle-state"; 459 arm,psci-suspend-param = <0x4100b344>; 460 entry-latency-us = <3638>; 461 exit-latency-us = <6562>; 462 min-residency-us = <9826>; 463 }; 464 }; 465 466 memory@80000000 { 467 device_type = "memory"; 468 /* We expect the bootloader to fill in the size */ 469 reg = <0 0x80000000 0 0>; 470 }; 471 472 firmware { 473 scm { 474 compatible = "qcom,scm-qcs615", "qcom,scm"; 475 qcom,dload-mode = <&tcsr 0x13000>; 476 }; 477 }; 478 479 camnoc_virt: interconnect-0 { 480 compatible = "qcom,qcs615-camnoc-virt"; 481 #interconnect-cells = <2>; 482 qcom,bcm-voters = <&apps_bcm_voter>; 483 }; 484 485 mc_virt: interconnect-2 { 486 compatible = "qcom,qcs615-mc-virt"; 487 #interconnect-cells = <2>; 488 qcom,bcm-voters = <&apps_bcm_voter>; 489 }; 490 491 smp2p-adsp { 492 compatible = "qcom,smp2p"; 493 qcom,smem = <443>, <429>; 494 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING 0>; 495 /* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */ 496 mboxes = <&apss_shared 26>; 497 498 qcom,local-pid = <0>; 499 qcom,remote-pid = <2>; 500 501 adsp_smp2p_out: master-kernel { 502 qcom,entry-name = "master-kernel"; 503 #qcom,smem-state-cells = <1>; 504 }; 505 506 adsp_smp2p_in: slave-kernel { 507 qcom,entry-name = "slave-kernel"; 508 interrupt-controller; 509 #interrupt-cells = <2>; 510 }; 511 }; 512 513 smp2p-cdsp { 514 compatible = "qcom,smp2p"; 515 qcom,smem = <94>, <432>; 516 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING 0>; 517 mboxes = <&apss_shared 6>; 518 519 qcom,local-pid = <0>; 520 qcom,remote-pid = <5>; 521 522 cdsp_smp2p_out: master-kernel { 523 qcom,entry-name = "master-kernel"; 524 #qcom,smem-state-cells = <1>; 525 }; 526 527 cdsp_smp2p_in: slave-kernel { 528 qcom,entry-name = "slave-kernel"; 529 interrupt-controller; 530 #interrupt-cells = <2>; 531 }; 532 533 }; 534 535 qspi_opp_table: opp-table-qspi { 536 compatible = "operating-points-v2"; 537 538 opp-60000000 { 539 opp-hz = /bits/ 64 <60000000>; 540 required-opps = <&rpmhpd_opp_low_svs>; 541 }; 542 543 opp-133250000 { 544 opp-hz = /bits/ 64 <133250000>; 545 required-opps = <&rpmhpd_opp_svs>; 546 }; 547 548 opp-266500000 { 549 opp-hz = /bits/ 64 <266500000>; 550 required-opps = <&rpmhpd_opp_nom>; 551 }; 552 }; 553 554 qup_opp_table: opp-table-qup { 555 compatible = "operating-points-v2"; 556 557 opp-75000000 { 558 opp-hz = /bits/ 64 <75000000>; 559 required-opps = <&rpmhpd_opp_low_svs>; 560 }; 561 562 opp-100000000 { 563 opp-hz = /bits/ 64 <100000000>; 564 required-opps = <&rpmhpd_opp_svs>; 565 }; 566 567 opp-128000000 { 568 opp-hz = /bits/ 64 <128000000>; 569 required-opps = <&rpmhpd_opp_nom>; 570 }; 571 }; 572 573 pmu-a55 { 574 compatible = "arm,cortex-a55-pmu"; 575 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 576 }; 577 578 pmu-a76 { 579 compatible = "arm,cortex-a76-pmu"; 580 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 581 }; 582 583 psci { 584 compatible = "arm,psci-1.0"; 585 method = "smc"; 586 587 cpu_pd0: power-domain-cpu0 { 588 #power-domain-cells = <0>; 589 power-domains = <&cluster_pd>; 590 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 591 }; 592 593 cpu_pd1: power-domain-cpu1 { 594 #power-domain-cells = <0>; 595 power-domains = <&cluster_pd>; 596 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 597 }; 598 599 cpu_pd2: power-domain-cpu2 { 600 #power-domain-cells = <0>; 601 power-domains = <&cluster_pd>; 602 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 603 }; 604 605 cpu_pd3: power-domain-cpu3 { 606 #power-domain-cells = <0>; 607 power-domains = <&cluster_pd>; 608 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 609 }; 610 611 cpu_pd4: power-domain-cpu4 { 612 #power-domain-cells = <0>; 613 power-domains = <&cluster_pd>; 614 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 615 }; 616 617 cpu_pd5: power-domain-cpu5 { 618 #power-domain-cells = <0>; 619 power-domains = <&cluster_pd>; 620 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 621 }; 622 623 cpu_pd6: power-domain-cpu6 { 624 #power-domain-cells = <0>; 625 power-domains = <&cluster_pd>; 626 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 627 }; 628 629 cpu_pd7: power-domain-cpu7 { 630 #power-domain-cells = <0>; 631 power-domains = <&cluster_pd>; 632 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 633 }; 634 635 cluster_pd: power-domain-cluster { 636 #power-domain-cells = <0>; 637 domain-idle-states = <&cluster_sleep_0 638 &cluster_sleep_1 639 &cluster_sleep_2>; 640 }; 641 }; 642 643 reserved-memory { 644 #address-cells = <2>; 645 #size-cells = <2>; 646 ranges; 647 648 aop_cmd_db_mem: aop-cmd-db@85f20000 { 649 compatible = "qcom,cmd-db"; 650 reg = <0x0 0x85f20000 0x0 0x20000>; 651 no-map; 652 }; 653 654 smem_region: smem@86000000 { 655 compatible = "qcom,smem"; 656 reg = <0x0 0x86000000 0x0 0x200000>; 657 no-map; 658 hwlocks = <&tcsr_mutex 3>; 659 }; 660 661 pil_video_mem: pil-video@93400000 { 662 reg = <0x0 0x93400000 0x0 0x500000>; 663 no-map; 664 }; 665 666 rproc_cdsp_mem: rproc-cdsp@93b00000 { 667 reg = <0x0 0x93b00000 0x0 0x1e00000>; 668 no-map; 669 }; 670 671 rproc_adsp_mem: rproc-adsp@95900000 { 672 reg = <0x0 0x95900000 0x0 0x1e00000>; 673 no-map; 674 }; 675 676 pil_gpu_mem: pil-gpu@97715000 { 677 reg = <0x0 0x97715000 0x0 0x2000>; 678 no-map; 679 }; 680 }; 681 682 soc: soc@0 { 683 compatible = "simple-bus"; 684 ranges = <0 0 0 0 0x10 0>; 685 dma-ranges = <0 0 0 0 0x10 0>; 686 #address-cells = <2>; 687 #size-cells = <2>; 688 689 gcc: clock-controller@100000 { 690 compatible = "qcom,qcs615-gcc"; 691 reg = <0 0x00100000 0 0x1f0000>; 692 clocks = <&rpmhcc RPMH_CXO_CLK>, 693 <&rpmhcc RPMH_CXO_CLK_A>, 694 <&sleep_clk>; 695 clock-names = "bi_tcxo", 696 "bi_tcxo_ao", 697 "sleep_clk"; 698 699 #clock-cells = <1>; 700 #reset-cells = <1>; 701 #power-domain-cells = <1>; 702 }; 703 704 qfprom: efuse@780000 { 705 compatible = "qcom,qcs615-qfprom", "qcom,qfprom"; 706 reg = <0x0 0x00780000 0x0 0x7000>; 707 #address-cells = <1>; 708 #size-cells = <1>; 709 710 qusb2_hstx_trim: hstx-trim@1f8 { 711 reg = <0x1fb 0x1>; 712 bits = <1 4>; 713 }; 714 }; 715 716 rng@793000 { 717 compatible = "qcom,qcs615-trng", "qcom,trng"; 718 reg = <0x0 0x00793000 0x0 0x1000>; 719 }; 720 721 sdhc_1: mmc@7c4000 { 722 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 723 reg = <0x0 0x007c4000 0x0 0x1000>, 724 <0x0 0x007c5000 0x0 0x1000>, 725 <0x0 0x007c8000 0x0 0x8000>; 726 reg-names = "hc", 727 "cqhci", 728 "ice"; 729 730 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>, 731 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 732 interrupt-names = "hc_irq", 733 "pwr_irq"; 734 735 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 736 <&gcc GCC_SDCC1_APPS_CLK>, 737 <&rpmhcc RPMH_CXO_CLK>, 738 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 739 clock-names = "iface", 740 "core", 741 "xo", 742 "ice"; 743 744 resets = <&gcc GCC_SDCC1_BCR>; 745 746 power-domains = <&rpmhpd RPMHPD_CX>; 747 operating-points-v2 = <&sdhc1_opp_table>; 748 iommus = <&apps_smmu 0x02c0 0x0>; 749 interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS 750 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 751 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 752 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 753 interconnect-names = "sdhc-ddr", 754 "cpu-sdhc"; 755 756 qcom,dll-config = <0x000f642c>; 757 qcom,ddr-config = <0x80040868>; 758 supports-cqe; 759 dma-coherent; 760 761 status = "disabled"; 762 763 sdhc1_opp_table: opp-table { 764 compatible = "operating-points-v2"; 765 766 opp-50000000 { 767 opp-hz = /bits/ 64 <50000000>; 768 required-opps = <&rpmhpd_opp_low_svs>; 769 }; 770 771 opp-100000000 { 772 opp-hz = /bits/ 64 <100000000>; 773 required-opps = <&rpmhpd_opp_svs>; 774 }; 775 776 opp-200000000 { 777 opp-hz = /bits/ 64 <200000000>; 778 required-opps = <&rpmhpd_opp_svs_l1>; 779 }; 780 781 opp-384000000 { 782 opp-hz = /bits/ 64 <384000000>; 783 required-opps = <&rpmhpd_opp_nom>; 784 }; 785 }; 786 }; 787 788 gpi_dma0: dma-controller@800000 { 789 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 790 reg = <0x0 0x800000 0x0 0x60000>; 791 #dma-cells = <3>; 792 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>, 793 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 794 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 795 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 796 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 797 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>, 798 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 799 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 800 dma-channels = <8>; 801 dma-channel-mask = <0xf>; 802 iommus = <&apps_smmu 0xd6 0x0>; 803 status = "disabled"; 804 }; 805 806 qupv3_id_0: geniqup@8c0000 { 807 compatible = "qcom,geni-se-qup"; 808 reg = <0x0 0x008c0000 0x0 0x6000>; 809 ranges; 810 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 811 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 812 clock-names = "m-ahb", 813 "s-ahb"; 814 iommus = <&apps_smmu 0xc3 0x0>; 815 #address-cells = <2>; 816 #size-cells = <2>; 817 status = "disabled"; 818 819 uart0: serial@880000 { 820 compatible = "qcom,geni-debug-uart"; 821 reg = <0x0 0x00880000 0x0 0x4000>; 822 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 823 clock-names = "se"; 824 pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>; 825 pinctrl-names = "default"; 826 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH 0>; 827 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 828 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 829 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 830 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 831 interconnect-names = "qup-core", 832 "qup-config"; 833 power-domains = <&rpmhpd RPMHPD_CX>; 834 operating-points-v2 = <&qup_opp_table>; 835 status = "disabled"; 836 }; 837 838 i2c1: i2c@884000 { 839 compatible = "qcom,geni-i2c"; 840 reg = <0x0 0x884000 0x0 0x4000>; 841 #address-cells = <1>; 842 #size-cells = <0>; 843 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH 0>; 844 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 845 clock-names = "se"; 846 pinctrl-0 = <&qup_i2c1_data_clk>; 847 pinctrl-names = "default"; 848 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 849 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 850 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 851 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 852 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 853 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 854 interconnect-names = "qup-core", 855 "qup-config", 856 "qup-memory"; 857 power-domains = <&rpmhpd RPMHPD_CX>; 858 required-opps = <&rpmhpd_opp_low_svs>; 859 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 860 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 861 dma-names = "tx", 862 "rx"; 863 status = "disabled"; 864 }; 865 866 i2c2: i2c@888000 { 867 compatible = "qcom,geni-i2c"; 868 reg = <0x0 0x888000 0x0 0x4000>; 869 #address-cells = <1>; 870 #size-cells = <0>; 871 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>; 872 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 873 clock-names = "se"; 874 pinctrl-0 = <&qup_i2c2_data_clk>; 875 pinctrl-names = "default"; 876 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 877 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 878 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 879 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 880 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 881 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 882 interconnect-names = "qup-core", 883 "qup-config", 884 "qup-memory"; 885 power-domains = <&rpmhpd RPMHPD_CX>; 886 required-opps = <&rpmhpd_opp_low_svs>; 887 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 888 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 889 dma-names = "tx", 890 "rx"; 891 status = "disabled"; 892 }; 893 894 spi2: spi@888000 { 895 compatible = "qcom,geni-spi"; 896 reg = <0x0 0x00888000 0x0 0x4000>; 897 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>; 898 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 899 clock-names = "se"; 900 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 901 pinctrl-names = "default"; 902 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 903 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 904 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 905 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 906 interconnect-names = "qup-core", 907 "qup-config"; 908 power-domains = <&rpmhpd RPMHPD_CX>; 909 operating-points-v2 = <&qup_opp_table>; 910 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 911 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 912 dma-names = "tx", 913 "rx"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 status = "disabled"; 917 }; 918 919 uart2: serial@888000 { 920 compatible = "qcom,geni-uart"; 921 reg = <0x0 0x00888000 0x0 0x4000>; 922 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>; 923 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 924 clock-names = "se"; 925 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 926 <&qup_uart2_tx>, <&qup_uart2_rx>; 927 pinctrl-names = "default"; 928 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 929 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 930 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 931 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 932 interconnect-names = "qup-core", 933 "qup-config"; 934 power-domains = <&rpmhpd RPMHPD_CX>; 935 operating-points-v2 = <&qup_opp_table>; 936 status = "disabled"; 937 }; 938 939 i2c3: i2c@88c000 { 940 compatible = "qcom,geni-i2c"; 941 reg = <0x0 0x88c000 0x0 0x4000>; 942 #address-cells = <1>; 943 #size-cells = <0>; 944 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>; 945 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 946 clock-names = "se"; 947 pinctrl-0 = <&qup_i2c3_data_clk>; 948 pinctrl-names = "default"; 949 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 950 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 951 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 952 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 953 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 954 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 955 interconnect-names = "qup-core", 956 "qup-config", 957 "qup-memory"; 958 power-domains = <&rpmhpd RPMHPD_CX>; 959 required-opps = <&rpmhpd_opp_low_svs>; 960 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 961 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 962 dma-names = "tx", 963 "rx"; 964 status = "disabled"; 965 }; 966 }; 967 968 gpi_dma1: dma-controller@a00000 { 969 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 970 reg = <0x0 0xa00000 0x0 0x60000>; 971 #dma-cells = <3>; 972 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>, 973 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>, 974 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>, 975 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>, 976 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>, 977 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>, 978 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>, 979 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 980 dma-channels = <8>; 981 dma-channel-mask = <0xf>; 982 iommus = <&apps_smmu 0x376 0x0>; 983 status = "disabled"; 984 }; 985 986 qupv3_id_1: geniqup@ac0000 { 987 compatible = "qcom,geni-se-qup"; 988 reg = <0x0 0xac0000 0x0 0x2000>; 989 ranges; 990 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 991 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 992 clock-names = "m-ahb", 993 "s-ahb"; 994 iommus = <&apps_smmu 0x363 0x0>; 995 #address-cells = <2>; 996 #size-cells = <2>; 997 status = "disabled"; 998 999 i2c4: i2c@a80000 { 1000 compatible = "qcom,geni-i2c"; 1001 reg = <0x0 0xa80000 0x0 0x4000>; 1002 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1003 clock-names = "se"; 1004 pinctrl-0 = <&qup_i2c4_data_clk>; 1005 pinctrl-names = "default"; 1006 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1010 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1011 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1012 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1013 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1014 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1015 interconnect-names = "qup-core", 1016 "qup-config", 1017 "qup-memory"; 1018 power-domains = <&rpmhpd RPMHPD_CX>; 1019 required-opps = <&rpmhpd_opp_low_svs>; 1020 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1021 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1022 dma-names = "tx", 1023 "rx"; 1024 status = "disabled"; 1025 }; 1026 1027 spi4: spi@a80000 { 1028 compatible = "qcom,geni-spi"; 1029 reg = <0x0 0xa80000 0x0 0x4000>; 1030 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1031 clock-names = "se"; 1032 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1033 pinctrl-names = "default"; 1034 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1038 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1039 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1040 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1041 interconnect-names = "qup-core", 1042 "qup-config"; 1043 power-domains = <&rpmhpd RPMHPD_CX>; 1044 operating-points-v2 = <&qup_opp_table>; 1045 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1046 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1047 dma-names = "tx", 1048 "rx"; 1049 status = "disabled"; 1050 }; 1051 1052 uart4: serial@a80000 { 1053 compatible = "qcom,geni-uart"; 1054 reg = <0x0 0xa80000 0x0 0x4000>; 1055 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1056 clock-names = "se"; 1057 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 1058 <&qup_uart4_tx>, <&qup_uart4_rx>; 1059 pinctrl-names = "default"; 1060 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1061 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1062 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1063 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1064 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1065 interconnect-names = "qup-core", 1066 "qup-config"; 1067 power-domains = <&rpmhpd RPMHPD_CX>; 1068 operating-points-v2 = <&qup_opp_table>; 1069 status = "disabled"; 1070 }; 1071 1072 i2c5: i2c@a84000 { 1073 compatible = "qcom,geni-i2c"; 1074 reg = <0x0 0xa84000 0x0 0x4000>; 1075 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1076 clock-names = "se"; 1077 pinctrl-0 = <&qup_i2c5_data_clk>; 1078 pinctrl-names = "default"; 1079 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1083 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1084 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1085 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1086 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1087 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1088 interconnect-names = "qup-core", 1089 "qup-config", 1090 "qup-memory"; 1091 power-domains = <&rpmhpd RPMHPD_CX>; 1092 required-opps = <&rpmhpd_opp_low_svs>; 1093 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1094 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1095 dma-names = "tx", 1096 "rx"; 1097 status = "disabled"; 1098 }; 1099 1100 i2c6: i2c@a88000 { 1101 compatible = "qcom,geni-i2c"; 1102 reg = <0x0 0xa88000 0x0 0x4000>; 1103 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1104 clock-names = "se"; 1105 pinctrl-0 = <&qup_i2c6_data_clk>; 1106 pinctrl-names = "default"; 1107 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1111 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1112 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1113 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1114 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1115 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1116 interconnect-names = "qup-core", 1117 "qup-config", 1118 "qup-memory"; 1119 power-domains = <&rpmhpd RPMHPD_CX>; 1120 required-opps = <&rpmhpd_opp_low_svs>; 1121 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1122 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1123 dma-names = "tx", 1124 "rx"; 1125 status = "disabled"; 1126 }; 1127 1128 spi6: spi@a88000 { 1129 compatible = "qcom,geni-spi"; 1130 reg = <0x0 0xa88000 0x0 0x4000>; 1131 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1132 clock-names = "se"; 1133 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1134 pinctrl-names = "default"; 1135 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1139 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1140 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1141 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1142 interconnect-names = "qup-core", 1143 "qup-config"; 1144 power-domains = <&rpmhpd RPMHPD_CX>; 1145 operating-points-v2 = <&qup_opp_table>; 1146 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1147 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1148 dma-names = "tx", 1149 "rx"; 1150 status = "disabled"; 1151 }; 1152 1153 uart6: serial@a88000 { 1154 compatible = "qcom,geni-uart"; 1155 reg = <0x0 0xa88000 0x0 0x4000>; 1156 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1157 clock-names = "se"; 1158 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 1159 <&qup_uart6_tx>, <&qup_uart6_rx>; 1160 pinctrl-names = "default"; 1161 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1162 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1163 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1164 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1165 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1166 interconnect-names = "qup-core", 1167 "qup-config"; 1168 power-domains = <&rpmhpd RPMHPD_CX>; 1169 operating-points-v2 = <&qup_opp_table>; 1170 status = "disabled"; 1171 }; 1172 1173 i2c7: i2c@a8c000 { 1174 compatible = "qcom,geni-i2c"; 1175 reg = <0x0 0xa8c000 0x0 0x4000>; 1176 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1177 clock-names = "se"; 1178 pinctrl-0 = <&qup_i2c7_data_clk>; 1179 pinctrl-names = "default"; 1180 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1184 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1185 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1186 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1187 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1188 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1189 interconnect-names = "qup-core", 1190 "qup-config", 1191 "qup-memory"; 1192 power-domains = <&rpmhpd RPMHPD_CX>; 1193 required-opps = <&rpmhpd_opp_low_svs>; 1194 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1195 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1196 dma-names = "tx", 1197 "rx"; 1198 status = "disabled"; 1199 }; 1200 1201 spi7: spi@a8c000 { 1202 compatible = "qcom,geni-spi"; 1203 reg = <0x0 0xa8c000 0x0 0x4000>; 1204 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1205 clock-names = "se"; 1206 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1207 pinctrl-names = "default"; 1208 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1212 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1213 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1214 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1215 interconnect-names = "qup-core", 1216 "qup-config"; 1217 power-domains = <&rpmhpd RPMHPD_CX>; 1218 operating-points-v2 = <&qup_opp_table>; 1219 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1220 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1221 dma-names = "tx", 1222 "rx"; 1223 status = "disabled"; 1224 }; 1225 1226 uart7: serial@a8c000 { 1227 compatible = "qcom,geni-uart"; 1228 reg = <0x0 0xa8c000 0x0 0x4000>; 1229 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1230 clock-names = "se"; 1231 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, 1232 <&qup_uart7_tx>, <&qup_uart7_rx>; 1233 pinctrl-names = "default"; 1234 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1235 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1236 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1237 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1238 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1239 interconnect-names = "qup-core", 1240 "qup-config"; 1241 power-domains = <&rpmhpd RPMHPD_CX>; 1242 operating-points-v2 = <&qup_opp_table>; 1243 status = "disabled"; 1244 }; 1245 }; 1246 1247 config_noc: interconnect@1500000 { 1248 reg = <0x0 0x01500000 0x0 0x5080>; 1249 compatible = "qcom,qcs615-config-noc"; 1250 #interconnect-cells = <2>; 1251 qcom,bcm-voters = <&apps_bcm_voter>; 1252 }; 1253 1254 system_noc: interconnect@1620000 { 1255 reg = <0x0 0x01620000 0x0 0x1f300>; 1256 compatible = "qcom,qcs615-system-noc"; 1257 #interconnect-cells = <2>; 1258 qcom,bcm-voters = <&apps_bcm_voter>; 1259 }; 1260 1261 aggre1_noc: interconnect@1700000 { 1262 reg = <0x0 0x01700000 0x0 0x3f200>; 1263 compatible = "qcom,qcs615-aggre1-noc"; 1264 #interconnect-cells = <2>; 1265 qcom,bcm-voters = <&apps_bcm_voter>; 1266 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1267 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, 1268 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1269 <&rpmhcc RPMH_IPA_CLK>; 1270 }; 1271 1272 mmss_noc: interconnect@1740000 { 1273 reg = <0x0 0x01740000 0x0 0x1c100>; 1274 compatible = "qcom,qcs615-mmss-noc"; 1275 #interconnect-cells = <2>; 1276 qcom,bcm-voters = <&apps_bcm_voter>; 1277 }; 1278 1279 pcie: pcie@1c08000 { 1280 device_type = "pci"; 1281 compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150"; 1282 reg = <0x0 0x01c08000 0x0 0x3000>, 1283 <0x0 0x40000000 0x0 0xf1d>, 1284 <0x0 0x40000f20 0x0 0xa8>, 1285 <0x0 0x40001000 0x0 0x1000>, 1286 <0x0 0x40100000 0x0 0x100000>, 1287 <0x0 0x01c0b000 0x0 0x1000>; 1288 reg-names = "parf", 1289 "dbi", 1290 "elbi", 1291 "atu", 1292 "config", 1293 "mhi"; 1294 #address-cells = <3>; 1295 #size-cells = <2>; 1296 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1297 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1298 bus-range = <0x00 0xff>; 1299 1300 dma-coherent; 1301 1302 linux,pci-domain = <0>; 1303 num-lanes = <1>; 1304 1305 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>, 1306 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>, 1307 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>, 1308 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>, 1309 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>, 1310 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>, 1311 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>, 1312 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>, 1313 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>; 1314 interrupt-names = "msi0", 1315 "msi1", 1316 "msi2", 1317 "msi3", 1318 "msi4", 1319 "msi5", 1320 "msi6", 1321 "msi7", 1322 "global"; 1323 1324 #interrupt-cells = <1>; 1325 interrupt-map-mask = <0 0 0 0x7>; 1326 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, 1327 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, 1328 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, 1329 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1330 1331 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1332 <&gcc GCC_PCIE_0_AUX_CLK>, 1333 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1334 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1335 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1336 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 1337 clock-names = "pipe", 1338 "aux", 1339 "cfg", 1340 "bus_master", 1341 "bus_slave", 1342 "slave_q2a"; 1343 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1344 assigned-clock-rates = <19200000>; 1345 1346 interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS 1347 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1348 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1349 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1350 interconnect-names = "pcie-mem", "cpu-pcie"; 1351 1352 iommu-map = <0x0 &apps_smmu 0x400 0x1>, 1353 <0x100 &apps_smmu 0x401 0x1>; 1354 1355 resets = <&gcc GCC_PCIE_0_BCR>; 1356 reset-names = "pci"; 1357 1358 power-domains = <&gcc PCIE_0_GDSC>; 1359 1360 phys = <&pcie_phy>; 1361 phy-names = "pciephy"; 1362 1363 max-link-speed = <2>; 1364 1365 operating-points-v2 = <&pcie_opp_table>; 1366 1367 status = "disabled"; 1368 1369 pcie_opp_table: opp-table { 1370 compatible = "operating-points-v2"; 1371 1372 /* GEN 1 x1 */ 1373 opp-2500000 { 1374 opp-hz = /bits/ 64 <2500000>; 1375 required-opps = <&rpmhpd_opp_low_svs>; 1376 opp-peak-kBps = <250000 1>; 1377 }; 1378 1379 /* GEN 2 x1 */ 1380 opp-5000000 { 1381 opp-hz = /bits/ 64 <5000000>; 1382 required-opps = <&rpmhpd_opp_low_svs>; 1383 opp-peak-kBps = <500000 1>; 1384 }; 1385 }; 1386 1387 pcie_port0: pcie@0 { 1388 device_type = "pci"; 1389 reg = <0x0 0x0 0x0 0x0 0x0>; 1390 #address-cells = <3>; 1391 #size-cells = <2>; 1392 ranges; 1393 bus-range = <0x01 0xff>; 1394 }; 1395 }; 1396 1397 pcie_phy: phy@1c0e000 { 1398 compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy"; 1399 reg = <0x0 0x01c0e000 0x0 0x1000>; 1400 1401 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1402 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1403 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1404 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1405 <&gcc GCC_PCIE_0_PIPE_CLK>; 1406 clock-names = "aux", 1407 "cfg_ahb", 1408 "ref", 1409 "refgen", 1410 "pipe"; 1411 1412 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1413 reset-names = "phy"; 1414 1415 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1416 assigned-clock-rates = <100000000>; 1417 1418 #clock-cells = <0>; 1419 clock-output-names = "pcie_0_pipe_clk"; 1420 1421 #phy-cells = <0>; 1422 1423 status = "disabled"; 1424 }; 1425 1426 ufs_mem_hc: ufshc@1d84000 { 1427 compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1428 reg = <0x0 0x01d84000 0x0 0x3000>, 1429 <0x0 0x01d90000 0x0 0x8000>; 1430 reg-names = "std", 1431 "ice"; 1432 1433 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 1434 1435 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1436 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1437 <&gcc GCC_UFS_PHY_AHB_CLK>, 1438 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1439 <&rpmhcc RPMH_CXO_CLK>, 1440 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1441 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1442 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1443 clock-names = "core_clk", 1444 "bus_aggr_clk", 1445 "iface_clk", 1446 "core_clk_unipro", 1447 "ref_clk", 1448 "tx_lane0_sync_clk", 1449 "rx_lane0_sync_clk", 1450 "ice_core_clk"; 1451 1452 resets = <&gcc GCC_UFS_PHY_BCR>; 1453 reset-names = "rst"; 1454 1455 operating-points-v2 = <&ufs_opp_table>; 1456 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1457 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1458 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1459 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 1460 interconnect-names = "ufs-ddr", 1461 "cpu-ufs"; 1462 1463 power-domains = <&gcc UFS_PHY_GDSC>; 1464 1465 iommus = <&apps_smmu 0x300 0x0>; 1466 dma-coherent; 1467 1468 lanes-per-direction = <1>; 1469 1470 phys = <&ufs_mem_phy>; 1471 phy-names = "ufsphy"; 1472 1473 #reset-cells = <1>; 1474 1475 status = "disabled"; 1476 1477 ufs_opp_table: opp-table { 1478 compatible = "operating-points-v2"; 1479 1480 opp-50000000 { 1481 opp-hz = /bits/ 64 <50000000>, 1482 /bits/ 64 <0>, 1483 /bits/ 64 <0>, 1484 /bits/ 64 <37500000>, 1485 /bits/ 64 <0>, 1486 /bits/ 64 <0>, 1487 /bits/ 64 <0>, 1488 /bits/ 64 <75000000>; 1489 required-opps = <&rpmhpd_opp_low_svs>; 1490 }; 1491 1492 opp-100000000 { 1493 opp-hz = /bits/ 64 <100000000>, 1494 /bits/ 64 <0>, 1495 /bits/ 64 <0>, 1496 /bits/ 64 <75000000>, 1497 /bits/ 64 <0>, 1498 /bits/ 64 <0>, 1499 /bits/ 64 <0>, 1500 /bits/ 64 <150000000>; 1501 required-opps = <&rpmhpd_opp_svs>; 1502 }; 1503 1504 opp-200000000 { 1505 opp-hz = /bits/ 64 <200000000>, 1506 /bits/ 64 <0>, 1507 /bits/ 64 <0>, 1508 /bits/ 64 <150000000>, 1509 /bits/ 64 <0>, 1510 /bits/ 64 <0>, 1511 /bits/ 64 <0>, 1512 /bits/ 64 <300000000>; 1513 required-opps = <&rpmhpd_opp_nom>; 1514 }; 1515 }; 1516 }; 1517 1518 ufs_mem_phy: phy@1d87000 { 1519 compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy"; 1520 reg = <0x0 0x01d87000 0x0 0xe00>; 1521 clocks = <&rpmhcc RPMH_CXO_CLK>, 1522 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1523 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1524 clock-names = "ref", 1525 "ref_aux", 1526 "qref"; 1527 1528 power-domains = <&gcc UFS_PHY_GDSC>; 1529 1530 resets = <&ufs_mem_hc 0>; 1531 reset-names = "ufsphy"; 1532 1533 #clock-cells = <1>; 1534 #phy-cells = <0>; 1535 1536 status = "disabled"; 1537 }; 1538 1539 cryptobam: dma-controller@1dc4000 { 1540 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1541 reg = <0x0 0x01dc4000 0x0 0x24000>; 1542 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; 1543 #dma-cells = <1>; 1544 qcom,ee = <0>; 1545 qcom,controlled-remotely; 1546 num-channels = <16>; 1547 qcom,num-ees = <4>; 1548 iommus = <&apps_smmu 0x0104 0x0011>; 1549 }; 1550 1551 crypto: crypto@1dfa000 { 1552 compatible = "qcom,qcs615-qce", "qcom,sm8150-qce", "qcom,qce"; 1553 reg = <0x0 0x01dfa000 0x0 0x6000>; 1554 dmas = <&cryptobam 4>, <&cryptobam 5>; 1555 dma-names = "rx", "tx"; 1556 iommus = <&apps_smmu 0x0104 0x0011>; 1557 interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 1558 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1559 interconnect-names = "memory"; 1560 }; 1561 1562 tcsr_mutex: hwlock@1f40000 { 1563 compatible = "qcom,tcsr-mutex"; 1564 reg = <0x0 0x01f40000 0x0 0x20000>; 1565 #hwlock-cells = <1>; 1566 }; 1567 1568 tcsr: syscon@1fc0000 { 1569 compatible = "qcom,qcs615-tcsr", "syscon"; 1570 reg = <0x0 0x01fc0000 0x0 0x30000>; 1571 }; 1572 1573 tlmm: pinctrl@3100000 { 1574 compatible = "qcom,qcs615-tlmm"; 1575 reg = <0x0 0x03100000 0x0 0x300000>, 1576 <0x0 0x03500000 0x0 0x300000>, 1577 <0x0 0x03d00000 0x0 0x300000>; 1578 reg-names = "east", 1579 "west", 1580 "south"; 1581 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; 1582 gpio-ranges = <&tlmm 0 0 124>; 1583 gpio-controller; 1584 #gpio-cells = <2>; 1585 interrupt-controller; 1586 #interrupt-cells = <2>; 1587 wakeup-parent = <&pdc>; 1588 1589 cam_mclk0_default: cam-mclk0-default-state { 1590 pins = "gpio28"; 1591 function = "cam_mclk"; 1592 drive-strength = <2>; 1593 bias-disable; 1594 }; 1595 1596 cam_mclk1_default: cam-mclk1-default-state { 1597 pins = "gpio29"; 1598 function = "cam_mclk"; 1599 drive-strength = <2>; 1600 bias-disable; 1601 }; 1602 1603 cam_mclk2_default: cam-mclk2-default-state { 1604 pins = "gpio30"; 1605 function = "cam_mclk"; 1606 drive-strength = <2>; 1607 bias-disable; 1608 }; 1609 1610 cam_mclk3_default: cam-mclk3-default-state { 1611 pins = "gpio31"; 1612 function = "cam_mclk"; 1613 drive-strength = <2>; 1614 bias-disable; 1615 }; 1616 1617 cci_i2c0_default: cci-i2c0-default-state { 1618 /* SDA, SCL */ 1619 pins = "gpio32", "gpio33"; 1620 function = "cci_i2c"; 1621 drive-strength = <2>; 1622 bias-pull-up; 1623 }; 1624 1625 cci_i2c1_default: cci-i2c1-default-state { 1626 /* SDA, SCL */ 1627 pins = "gpio34", "gpio35"; 1628 function = "cci_i2c"; 1629 drive-strength = <2>; 1630 bias-pull-up; 1631 }; 1632 1633 qspi_cs0: qspi-cs0-state { 1634 pins = "gpio44"; 1635 function = "qspi"; 1636 bias-disable; 1637 drive-strength = <6>; 1638 }; 1639 1640 qspi_data0123: qspi-data0123-state { 1641 pins = "gpio45", "gpio46", "gpio47", "gpio49"; 1642 function = "qspi"; 1643 bias-pull-down; 1644 drive-strength = <6>; 1645 }; 1646 1647 qspi_clk: qspi-clk-state { 1648 pins = "gpio48"; 1649 function = "qspi"; 1650 bias-pull-down; 1651 drive-strength = <6>; 1652 }; 1653 1654 qspi_cs1: qspi-cs1-state { 1655 pins = "gpio50"; 1656 function = "qspi"; 1657 bias-pull-down; 1658 drive-strength = <6>; 1659 }; 1660 1661 mi2s1_pins: mi2s1-state { 1662 pins = "gpio108", "gpio109", "gpio110", "gpio111"; 1663 function = "mi2s_1"; 1664 drive-strength = <8>; 1665 bias-disable; 1666 }; 1667 1668 mi2s_mclk: mi2s-mclk-state { 1669 pins = "gpio122"; 1670 function = "mclk2"; 1671 drive-strength = <8>; 1672 bias-disable; 1673 }; 1674 1675 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 1676 pins = "gpio4", "gpio5"; 1677 function = "qup0"; 1678 1679 }; 1680 1681 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 1682 pins = "gpio0", "gpio1"; 1683 function = "qup0"; 1684 }; 1685 1686 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 1687 pins = "gpio18", "gpio19"; 1688 function = "qup0"; 1689 }; 1690 1691 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 1692 pins = "gpio20", "gpio21"; 1693 function = "qup1"; 1694 }; 1695 1696 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 1697 pins = "gpio14", "gpio15"; 1698 function = "qup1"; 1699 }; 1700 1701 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 1702 pins = "gpio6", "gpio7"; 1703 function = "qup1"; 1704 }; 1705 1706 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 1707 pins = "gpio10", "gpio11"; 1708 function = "qup1"; 1709 }; 1710 1711 qup_spi2_data_clk: qup-spi2-data-clk-state { 1712 pins = "gpio0", "gpio1", "gpio2"; 1713 function = "qup0"; 1714 }; 1715 1716 qup_spi2_cs: qup-spi2-cs-state { 1717 pins = "gpio3"; 1718 function = "qup0"; 1719 }; 1720 1721 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 1722 pins = "gpio3"; 1723 function = "gpio"; 1724 }; 1725 1726 qup_spi4_data_clk: qup-spi4-data-clk-state { 1727 pins = "gpio20", "gpio21", "gpio22"; 1728 function = "qup1"; 1729 }; 1730 1731 qup_spi4_cs: qup-spi4-cs-state { 1732 pins = "gpio23"; 1733 function = "qup1"; 1734 }; 1735 1736 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 1737 pins = "gpio23"; 1738 function = "gpio"; 1739 }; 1740 1741 qup_spi6_data_clk: qup-spi6-data-clk-state { 1742 pins = "gpio6", "gpio7", "gpio8"; 1743 function = "qup1"; 1744 }; 1745 1746 qup_spi6_cs: qup-spi6-cs-state { 1747 pins = "gpio9"; 1748 function = "qup1"; 1749 }; 1750 1751 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1752 pins = "gpio9"; 1753 function = "gpio"; 1754 }; 1755 1756 qup_spi7_data_clk: qup-spi7-data-clk-state { 1757 pins = "gpio10", "gpio11", "gpio12"; 1758 function = "qup1"; 1759 }; 1760 1761 qup_spi7_cs: qup-spi7-cs-state { 1762 pins = "gpio13"; 1763 function = "qup1"; 1764 }; 1765 1766 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 1767 pins = "gpio13"; 1768 function = "gpio"; 1769 }; 1770 1771 qup_uart0_tx: qup-uart0-tx-state { 1772 pins = "gpio16"; 1773 function = "qup0"; 1774 }; 1775 1776 qup_uart0_rx: qup-uart0-rx-state { 1777 pins = "gpio17"; 1778 function = "qup0"; 1779 }; 1780 1781 qup_uart2_cts: qup-uart2-cts-state { 1782 pins = "gpio0"; 1783 function = "qup0"; 1784 }; 1785 1786 qup_uart2_rts: qup-uart2-rts-state { 1787 pins = "gpio1"; 1788 function = "qup0"; 1789 }; 1790 1791 qup_uart2_tx: qup-uart2-tx-state { 1792 pins = "gpio2"; 1793 function = "qup0"; 1794 }; 1795 1796 qup_uart2_rx: qup-uart2-rx-state { 1797 pins = "gpio3"; 1798 function = "qup0"; 1799 }; 1800 1801 qup_uart4_cts: qup-uart4-cts-state { 1802 pins = "gpio20"; 1803 function = "qup1"; 1804 }; 1805 1806 qup_uart4_rts: qup-uart4-rts-state { 1807 pins = "gpio21"; 1808 function = "qup1"; 1809 }; 1810 1811 qup_uart4_tx: qup-uart4-tx-state { 1812 pins = "gpio22"; 1813 function = "qup1"; 1814 }; 1815 1816 qup_uart4_rx: qup-uart4-rx-state { 1817 pins = "gpio23"; 1818 function = "qup1"; 1819 }; 1820 1821 qup_uart6_cts: qup-uart6-cts-state { 1822 pins = "gpio6"; 1823 function = "qup1"; 1824 }; 1825 1826 qup_uart6_rts: qup-uart6-rts-state { 1827 pins = "gpio7"; 1828 function = "qup1"; 1829 }; 1830 1831 qup_uart6_tx: qup-uart6-tx-state { 1832 pins = "gpio8"; 1833 function = "qup1"; 1834 }; 1835 1836 qup_uart6_rx: qup-uart6-rx-state { 1837 pins = "gpio9"; 1838 function = "qup1"; 1839 }; 1840 1841 qup_uart7_cts: qup-uart7-cts-state { 1842 pins = "gpio10"; 1843 function = "qup1"; 1844 }; 1845 1846 qup_uart7_rts: qup-uart7-rts-state { 1847 pins = "gpio11"; 1848 function = "qup1"; 1849 }; 1850 1851 qup_uart7_tx: qup-uart7-tx-state { 1852 pins = "gpio12"; 1853 function = "qup1"; 1854 }; 1855 1856 qup_uart7_rx: qup-uart7-rx-state { 1857 pins = "gpio13"; 1858 function = "qup1"; 1859 }; 1860 1861 sdc1_state_on: sdc1-on-state { 1862 clk-pins { 1863 pins = "sdc1_clk"; 1864 bias-disable; 1865 drive-strength = <16>; 1866 }; 1867 1868 cmd-pins { 1869 pins = "sdc1_cmd"; 1870 bias-pull-up; 1871 drive-strength = <10>; 1872 }; 1873 1874 data-pins { 1875 pins = "sdc1_data"; 1876 bias-pull-up; 1877 drive-strength = <10>; 1878 }; 1879 1880 rclk-pins { 1881 pins = "sdc1_rclk"; 1882 bias-pull-down; 1883 }; 1884 }; 1885 1886 sdc1_state_off: sdc1-off-state { 1887 clk-pins { 1888 pins = "sdc1_clk"; 1889 bias-disable; 1890 drive-strength = <2>; 1891 }; 1892 1893 cmd-pins { 1894 pins = "sdc1_cmd"; 1895 bias-pull-up; 1896 drive-strength = <2>; 1897 }; 1898 1899 data-pins { 1900 pins = "sdc1_data"; 1901 bias-pull-up; 1902 drive-strength = <2>; 1903 }; 1904 1905 rclk-pins { 1906 pins = "sdc1_rclk"; 1907 bias-pull-down; 1908 }; 1909 }; 1910 1911 sdc2_state_on: sdc2-on-state { 1912 clk-pins { 1913 pins = "sdc2_clk"; 1914 bias-disable; 1915 drive-strength = <16>; 1916 }; 1917 1918 cmd-pins { 1919 pins = "sdc2_cmd"; 1920 bias-pull-up; 1921 drive-strength = <10>; 1922 }; 1923 1924 data-pins { 1925 pins = "sdc2_data"; 1926 bias-pull-up; 1927 drive-strength = <10>; 1928 }; 1929 }; 1930 1931 sdc2_state_off: sdc2-off-state { 1932 clk-pins { 1933 pins = "sdc2_clk"; 1934 bias-disable; 1935 drive-strength = <2>; 1936 }; 1937 1938 cmd-pins { 1939 pins = "sdc2_cmd"; 1940 bias-pull-up; 1941 drive-strength = <2>; 1942 }; 1943 1944 data-pins { 1945 pins = "sdc2_data"; 1946 bias-pull-up; 1947 drive-strength = <2>; 1948 }; 1949 }; 1950 }; 1951 1952 gpu: gpu@5000000 { 1953 compatible = "qcom,adreno-612.0", "qcom,adreno"; 1954 reg = <0x0 0x05000000 0x0 0x40000>, 1955 <0x0 0x0509e000 0x0 0x1000>, 1956 <0x0 0x05061000 0x0 0x800>; 1957 reg-names = "kgsl_3d0_reg_memory", 1958 "cx_mem", 1959 "cx_dbgc"; 1960 1961 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>; 1962 clock-names = "core"; 1963 1964 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; 1965 1966 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 1967 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1968 interconnect-names = "gfx-mem"; 1969 1970 iommus = <&adreno_smmu 0x0 0x401>; 1971 1972 operating-points-v2 = <&gpu_opp_table>; 1973 power-domains = <&rpmhpd RPMHPD_CX>; 1974 1975 qcom,gmu = <&gmu>; 1976 1977 #cooling-cells = <2>; 1978 1979 status = "disabled"; 1980 1981 gpu_zap_shader: zap-shader { 1982 memory-region = <&pil_gpu_mem>; 1983 }; 1984 1985 gpu_opp_table: opp-table { 1986 compatible = "operating-points-v2"; 1987 1988 opp-845000000 { 1989 opp-hz = /bits/ 64 <845000000>; 1990 required-opps = <&rpmhpd_opp_turbo>; 1991 opp-peak-kBps = <7050000>; 1992 }; 1993 1994 opp-745000000 { 1995 opp-hz = /bits/ 64 <745000000>; 1996 required-opps = <&rpmhpd_opp_nom_l1>; 1997 opp-peak-kBps = <6075000>; 1998 }; 1999 2000 opp-650000000 { 2001 opp-hz = /bits/ 64 <650000000>; 2002 required-opps = <&rpmhpd_opp_nom>; 2003 opp-peak-kBps = <5287500>; 2004 }; 2005 2006 opp-500000000 { 2007 opp-hz = /bits/ 64 <500000000>; 2008 required-opps = <&rpmhpd_opp_svs_l1>; 2009 opp-peak-kBps = <3975000>; 2010 }; 2011 2012 opp-435000000 { 2013 opp-hz = /bits/ 64 <435000000>; 2014 required-opps = <&rpmhpd_opp_svs>; 2015 opp-peak-kBps = <3000000>; 2016 }; 2017 }; 2018 }; 2019 2020 gmu: gmu@506a000 { 2021 compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu"; 2022 reg = <0x0 0x0506d000 0x0 0x2c000>; 2023 2024 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2025 <&gpucc GPU_CC_CXO_CLK>, 2026 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2027 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2028 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2029 clock-names = "gmu", 2030 "cxo", 2031 "axi", 2032 "memnoc", 2033 "smmu_vote"; 2034 2035 power-domains = <&gpucc CX_GDSC>, 2036 <&gpucc GX_GDSC>; 2037 power-domain-names = "cx", 2038 "gx"; 2039 2040 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>, 2041 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 2042 interrupt-names = "oob", 2043 "gmu"; 2044 2045 operating-points-v2 = <&gmu_opp_table>; 2046 2047 gmu_opp_table: opp-table { 2048 compatible = "operating-points-v2"; 2049 2050 opp-200000000 { 2051 opp-hz = /bits/ 64 <200000000>; 2052 required-opps = <&rpmhpd_opp_low_svs>; 2053 }; 2054 }; 2055 }; 2056 2057 gpucc: clock-controller@5090000 { 2058 compatible = "qcom,qcs615-gpucc"; 2059 reg = <0 0x05090000 0 0x9000>; 2060 2061 clocks = <&rpmhcc RPMH_CXO_CLK>, 2062 <&gcc GPLL0>, 2063 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2064 2065 #clock-cells = <1>; 2066 #reset-cells = <1>; 2067 #power-domain-cells = <1>; 2068 }; 2069 2070 adreno_smmu: iommu@50a0000 { 2071 compatible = "qcom,qcs615-smmu-500", "qcom,adreno-smmu", 2072 "qcom,smmu-500", "arm,mmu-500"; 2073 reg = <0x0 0x050a0000 0x0 0x40000>; 2074 #iommu-cells = <2>; 2075 #global-interrupts = <1>; 2076 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>, 2077 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, 2078 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, 2079 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, 2080 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, 2081 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, 2082 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, 2083 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, 2084 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>; 2085 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2086 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2087 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2088 clock-names = "mem", 2089 "hlos", 2090 "iface"; 2091 power-domains = <&gpucc CX_GDSC>; 2092 dma-coherent; 2093 }; 2094 2095 stm@6002000 { 2096 compatible = "arm,coresight-stm", "arm,primecell"; 2097 reg = <0x0 0x06002000 0x0 0x1000>, 2098 <0x0 0x16280000 0x0 0x180000>; 2099 reg-names = "stm-base", 2100 "stm-stimulus-base"; 2101 2102 clocks = <&aoss_qmp>; 2103 clock-names = "apb_pclk"; 2104 2105 out-ports { 2106 port { 2107 stm_out: endpoint { 2108 remote-endpoint = <&funnel_in0_in7>; 2109 }; 2110 }; 2111 }; 2112 }; 2113 2114 tpda@6004000 { 2115 compatible = "qcom,coresight-tpda", "arm,primecell"; 2116 reg = <0x0 0x06004000 0x0 0x1000>; 2117 2118 clocks = <&aoss_qmp>; 2119 clock-names = "apb_pclk"; 2120 2121 in-ports { 2122 #address-cells = <1>; 2123 #size-cells = <0>; 2124 2125 port@0 { 2126 reg = <0>; 2127 2128 tpda_qdss_in0: endpoint { 2129 remote-endpoint = <&tpdm_center_out>; 2130 }; 2131 }; 2132 2133 port@4 { 2134 reg = <4>; 2135 2136 tpda_qdss_in4: endpoint { 2137 remote-endpoint = <&funnel_monaq_out>; 2138 }; 2139 }; 2140 2141 port@5 { 2142 reg = <5>; 2143 2144 tpda_qdss_in5: endpoint { 2145 remote-endpoint = <&funnel_ddr_0_out>; 2146 }; 2147 }; 2148 2149 port@6 { 2150 reg = <6>; 2151 2152 tpda_qdss_in6: endpoint { 2153 remote-endpoint = <&funnel_turing_out>; 2154 }; 2155 }; 2156 2157 port@7 { 2158 reg = <7>; 2159 2160 tpda_qdss_in7: endpoint { 2161 remote-endpoint = <&tpdm_vsense_out>; 2162 }; 2163 }; 2164 2165 port@8 { 2166 reg = <8>; 2167 2168 tpda_qdss_in8: endpoint { 2169 remote-endpoint = <&tpdm_dcc_out>; 2170 }; 2171 }; 2172 2173 port@9 { 2174 reg = <9>; 2175 2176 tpda_qdss_in9: endpoint { 2177 remote-endpoint = <&tpdm_prng_out>; 2178 }; 2179 }; 2180 2181 port@b { 2182 reg = <11>; 2183 2184 tpda_qdss_in11: endpoint { 2185 remote-endpoint = <&tpdm_qm_out>; 2186 }; 2187 }; 2188 2189 port@c { 2190 reg = <12>; 2191 2192 tpda_qdss_in12: endpoint { 2193 remote-endpoint = <&tpdm_west_out>; 2194 }; 2195 }; 2196 2197 port@d { 2198 reg = <13>; 2199 2200 tpda_qdss_in13: endpoint { 2201 remote-endpoint = <&tpdm_pimem_out>; 2202 }; 2203 }; 2204 }; 2205 2206 out-ports { 2207 port { 2208 tpda_qdss_out: endpoint { 2209 remote-endpoint = <&funnel_qatb_in>; 2210 }; 2211 }; 2212 }; 2213 }; 2214 2215 funnel@6005000 { 2216 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2217 reg = <0x0 0x06005000 0x0 0x1000>; 2218 2219 clocks = <&aoss_qmp>; 2220 clock-names = "apb_pclk"; 2221 2222 in-ports { 2223 port { 2224 funnel_qatb_in: endpoint { 2225 remote-endpoint = <&tpda_qdss_out>; 2226 }; 2227 }; 2228 }; 2229 2230 out-ports { 2231 port { 2232 funnel_qatb_out: endpoint { 2233 remote-endpoint = <&funnel_in0_in6>; 2234 }; 2235 }; 2236 }; 2237 }; 2238 2239 cti@6010000 { 2240 compatible = "arm,coresight-cti", "arm,primecell"; 2241 reg = <0x0 0x06010000 0x0 0x1000>; 2242 2243 clocks = <&aoss_qmp>; 2244 clock-names = "apb_pclk"; 2245 }; 2246 2247 cti@6011000 { 2248 compatible = "arm,coresight-cti", "arm,primecell"; 2249 reg = <0x0 0x06011000 0x0 0x1000>; 2250 2251 clocks = <&aoss_qmp>; 2252 clock-names = "apb_pclk"; 2253 }; 2254 2255 cti@6012000 { 2256 compatible = "arm,coresight-cti", "arm,primecell"; 2257 reg = <0x0 0x06012000 0x0 0x1000>; 2258 2259 clocks = <&aoss_qmp>; 2260 clock-names = "apb_pclk"; 2261 }; 2262 2263 cti@6013000 { 2264 compatible = "arm,coresight-cti", "arm,primecell"; 2265 reg = <0x0 0x06013000 0x0 0x1000>; 2266 2267 clocks = <&aoss_qmp>; 2268 clock-names = "apb_pclk"; 2269 }; 2270 2271 cti@6014000 { 2272 compatible = "arm,coresight-cti", "arm,primecell"; 2273 reg = <0x0 0x06014000 0x0 0x1000>; 2274 2275 clocks = <&aoss_qmp>; 2276 clock-names = "apb_pclk"; 2277 }; 2278 2279 cti@6015000 { 2280 compatible = "arm,coresight-cti", "arm,primecell"; 2281 reg = <0x0 0x06015000 0x0 0x1000>; 2282 2283 clocks = <&aoss_qmp>; 2284 clock-names = "apb_pclk"; 2285 }; 2286 2287 cti@6016000 { 2288 compatible = "arm,coresight-cti", "arm,primecell"; 2289 reg = <0x0 0x06016000 0x0 0x1000>; 2290 2291 clocks = <&aoss_qmp>; 2292 clock-names = "apb_pclk"; 2293 }; 2294 2295 cti@6017000 { 2296 compatible = "arm,coresight-cti", "arm,primecell"; 2297 reg = <0x0 0x06017000 0x0 0x1000>; 2298 2299 clocks = <&aoss_qmp>; 2300 clock-names = "apb_pclk"; 2301 }; 2302 2303 cti@6018000 { 2304 compatible = "arm,coresight-cti", "arm,primecell"; 2305 reg = <0x0 0x06018000 0x0 0x1000>; 2306 2307 clocks = <&aoss_qmp>; 2308 clock-names = "apb_pclk"; 2309 }; 2310 2311 cti@6019000 { 2312 compatible = "arm,coresight-cti", "arm,primecell"; 2313 reg = <0x0 0x06019000 0x0 0x1000>; 2314 2315 clocks = <&aoss_qmp>; 2316 clock-names = "apb_pclk"; 2317 }; 2318 2319 cti@601a000 { 2320 compatible = "arm,coresight-cti", "arm,primecell"; 2321 reg = <0x0 0x0601a000 0x0 0x1000>; 2322 2323 clocks = <&aoss_qmp>; 2324 clock-names = "apb_pclk"; 2325 }; 2326 2327 cti@601b000 { 2328 compatible = "arm,coresight-cti", "arm,primecell"; 2329 reg = <0x0 0x0601b000 0x0 0x1000>; 2330 2331 clocks = <&aoss_qmp>; 2332 clock-names = "apb_pclk"; 2333 }; 2334 2335 cti@601c000 { 2336 compatible = "arm,coresight-cti", "arm,primecell"; 2337 reg = <0x0 0x0601c000 0x0 0x1000>; 2338 2339 clocks = <&aoss_qmp>; 2340 clock-names = "apb_pclk"; 2341 }; 2342 2343 cti@601d000 { 2344 compatible = "arm,coresight-cti", "arm,primecell"; 2345 reg = <0x0 0x0601d000 0x0 0x1000>; 2346 2347 clocks = <&aoss_qmp>; 2348 clock-names = "apb_pclk"; 2349 }; 2350 2351 cti@601e000 { 2352 compatible = "arm,coresight-cti", "arm,primecell"; 2353 reg = <0x0 0x0601e000 0x0 0x1000>; 2354 2355 clocks = <&aoss_qmp>; 2356 clock-names = "apb_pclk"; 2357 }; 2358 2359 cti@601f000 { 2360 compatible = "arm,coresight-cti", "arm,primecell"; 2361 reg = <0x0 0x0601f000 0x0 0x1000>; 2362 2363 clocks = <&aoss_qmp>; 2364 clock-names = "apb_pclk"; 2365 }; 2366 2367 funnel@6041000 { 2368 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2369 reg = <0x0 0x06041000 0x0 0x1000>; 2370 2371 clocks = <&aoss_qmp>; 2372 clock-names = "apb_pclk"; 2373 2374 in-ports { 2375 #address-cells = <1>; 2376 #size-cells = <0>; 2377 2378 port@6 { 2379 reg = <6>; 2380 2381 funnel_in0_in6: endpoint { 2382 remote-endpoint = <&funnel_qatb_out>; 2383 }; 2384 }; 2385 2386 port@7 { 2387 reg = <7>; 2388 2389 funnel_in0_in7: endpoint { 2390 remote-endpoint = <&stm_out>; 2391 }; 2392 }; 2393 }; 2394 2395 out-ports { 2396 port { 2397 funnel_in0_out: endpoint { 2398 remote-endpoint = <&funnel_merg_in0>; 2399 }; 2400 }; 2401 }; 2402 }; 2403 2404 funnel@6042000 { 2405 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2406 reg = <0x0 0x06042000 0x0 0x1000>; 2407 2408 clocks = <&aoss_qmp>; 2409 clock-names = "apb_pclk"; 2410 2411 in-ports { 2412 #address-cells = <1>; 2413 #size-cells = <0>; 2414 2415 port@3 { 2416 reg = <3>; 2417 2418 funnel_in1_in3: endpoint { 2419 remote-endpoint = <&replicator_swao_out0>; 2420 }; 2421 }; 2422 2423 port@4 { 2424 reg = <4>; 2425 2426 funnel_in1_in4: endpoint { 2427 remote-endpoint = <&tpdm_wcss_out>; 2428 }; 2429 }; 2430 2431 port@7 { 2432 reg = <7>; 2433 2434 funnel_in1_in7: endpoint { 2435 remote-endpoint = <&funnel_apss_merg_out>; 2436 }; 2437 }; 2438 }; 2439 2440 out-ports { 2441 port { 2442 funnel_in1_out: endpoint { 2443 remote-endpoint = <&funnel_merg_in1>; 2444 }; 2445 }; 2446 }; 2447 }; 2448 2449 funnel@6045000 { 2450 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2451 reg = <0x0 0x06045000 0x0 0x1000>; 2452 2453 clocks = <&aoss_qmp>; 2454 clock-names = "apb_pclk"; 2455 2456 in-ports { 2457 #address-cells = <1>; 2458 #size-cells = <0>; 2459 2460 port@0 { 2461 reg = <0>; 2462 2463 funnel_merg_in0: endpoint { 2464 remote-endpoint = <&funnel_in0_out>; 2465 }; 2466 }; 2467 2468 port@1 { 2469 reg = <1>; 2470 2471 funnel_merg_in1: endpoint { 2472 remote-endpoint = <&funnel_in1_out>; 2473 }; 2474 }; 2475 }; 2476 2477 out-ports { 2478 port { 2479 funnel_merg_out: endpoint { 2480 remote-endpoint = <&tmc_etf_in>; 2481 }; 2482 }; 2483 }; 2484 }; 2485 2486 replicator@6046000 { 2487 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2488 reg = <0x0 0x06046000 0x0 0x1000>; 2489 2490 clocks = <&aoss_qmp>; 2491 clock-names = "apb_pclk"; 2492 2493 in-ports { 2494 port { 2495 replicator0_in: endpoint { 2496 remote-endpoint = <&tmc_etf_out>; 2497 }; 2498 }; 2499 }; 2500 2501 out-ports { 2502 #address-cells = <1>; 2503 #size-cells = <0>; 2504 2505 port@0 { 2506 reg = <0>; 2507 2508 replicator0_out0: endpoint { 2509 remote-endpoint = <&tmc_etr_in>; 2510 }; 2511 }; 2512 2513 port@1 { 2514 reg = <1>; 2515 2516 replicator0_out1: endpoint { 2517 remote-endpoint = <&replicator1_in>; 2518 }; 2519 }; 2520 }; 2521 }; 2522 2523 tmc@6047000 { 2524 compatible = "arm,coresight-tmc", "arm,primecell"; 2525 reg = <0x0 0x06047000 0x0 0x1000>; 2526 2527 clocks = <&aoss_qmp>; 2528 clock-names = "apb_pclk"; 2529 2530 in-ports { 2531 port { 2532 tmc_etf_in: endpoint { 2533 remote-endpoint = <&funnel_merg_out>; 2534 }; 2535 }; 2536 }; 2537 2538 out-ports { 2539 port { 2540 tmc_etf_out: endpoint { 2541 remote-endpoint = <&replicator0_in>; 2542 }; 2543 }; 2544 }; 2545 }; 2546 2547 tmc@6048000 { 2548 compatible = "arm,coresight-tmc", "arm,primecell"; 2549 reg = <0x0 0x06048000 0x0 0x1000>; 2550 2551 clocks = <&aoss_qmp>; 2552 clock-names = "apb_pclk"; 2553 2554 iommus = <&apps_smmu 0x01e0 0x0>; 2555 arm,scatter-gather; 2556 2557 in-ports { 2558 port { 2559 tmc_etr_in: endpoint { 2560 remote-endpoint = <&replicator0_out0>; 2561 }; 2562 }; 2563 }; 2564 }; 2565 2566 replicator@604a000 { 2567 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2568 reg = <0x0 0x0604a000 0x0 0x1000>; 2569 2570 clocks = <&aoss_qmp>; 2571 clock-names = "apb_pclk"; 2572 status = "disabled"; 2573 2574 in-ports { 2575 port { 2576 replicator1_in: endpoint { 2577 remote-endpoint = <&replicator0_out1>; 2578 }; 2579 }; 2580 }; 2581 2582 out-ports { 2583 port { 2584 replicator1_out: endpoint { 2585 remote-endpoint = <&funnel_swao_in6>; 2586 }; 2587 }; 2588 }; 2589 }; 2590 2591 cti@683b000 { 2592 compatible = "arm,coresight-cti", "arm,primecell"; 2593 reg = <0x0 0x0683b000 0x0 0x1000>; 2594 2595 clocks = <&aoss_qmp>; 2596 clock-names = "apb_pclk"; 2597 }; 2598 2599 tpdm@6840000 { 2600 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2601 reg = <0x0 0x06840000 0x0 0x1000>; 2602 2603 clocks = <&aoss_qmp>; 2604 clock-names = "apb_pclk"; 2605 2606 qcom,cmb-element-bits = <64>; 2607 qcom,cmb-msrs-num = <32>; 2608 status = "disabled"; 2609 2610 out-ports { 2611 port { 2612 tpdm_vsense_out: endpoint { 2613 remote-endpoint = <&tpda_qdss_in7>; 2614 }; 2615 }; 2616 }; 2617 }; 2618 2619 tpdm@684c000 { 2620 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2621 reg = <0x0 0x0684c000 0x0 0x1000>; 2622 2623 clocks = <&aoss_qmp>; 2624 clock-names = "apb_pclk"; 2625 2626 qcom,cmb-element-bits = <32>; 2627 qcom,cmb-msrs-num = <32>; 2628 2629 out-ports { 2630 port { 2631 tpdm_prng_out: endpoint { 2632 remote-endpoint = <&tpda_qdss_in9>; 2633 }; 2634 }; 2635 }; 2636 }; 2637 2638 tpdm@6850000 { 2639 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2640 reg = <0x0 0x06850000 0x0 0x1000>; 2641 2642 clocks = <&aoss_qmp>; 2643 clock-names = "apb_pclk"; 2644 2645 qcom,cmb-element-bits = <64>; 2646 qcom,cmb-msrs-num = <32>; 2647 qcom,dsb-element-bits = <32>; 2648 qcom,dsb-msrs-num = <32>; 2649 2650 out-ports { 2651 port { 2652 tpdm_pimem_out: endpoint { 2653 remote-endpoint = <&tpda_qdss_in13>; 2654 }; 2655 }; 2656 }; 2657 }; 2658 2659 tpdm@6860000 { 2660 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2661 reg = <0x0 0x06860000 0x0 0x1000>; 2662 2663 clocks = <&aoss_qmp>; 2664 clock-names = "apb_pclk"; 2665 2666 qcom,dsb-element-bits = <32>; 2667 qcom,dsb-msrs-num = <32>; 2668 2669 out-ports { 2670 port { 2671 tpdm_turing_out: endpoint { 2672 remote-endpoint = <&funnel_turing_in>; 2673 }; 2674 }; 2675 }; 2676 }; 2677 2678 funnel@6861000 { 2679 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2680 reg = <0x0 0x06861000 0x0 0x1000>; 2681 2682 clocks = <&aoss_qmp>; 2683 clock-names = "apb_pclk"; 2684 2685 in-ports { 2686 port { 2687 funnel_turing_in: endpoint { 2688 remote-endpoint = <&tpdm_turing_out>; 2689 }; 2690 }; 2691 }; 2692 2693 out-ports { 2694 port { 2695 funnel_turing_out: endpoint { 2696 remote-endpoint = <&tpda_qdss_in6>; 2697 }; 2698 }; 2699 }; 2700 }; 2701 2702 cti@6867000 { 2703 compatible = "arm,coresight-cti", "arm,primecell"; 2704 reg = <0x0 0x06867000 0x0 0x1000>; 2705 2706 clocks = <&aoss_qmp>; 2707 clock-names = "apb_pclk"; 2708 }; 2709 2710 tpdm@6870000 { 2711 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2712 reg = <0x0 0x06870000 0x0 0x1000>; 2713 2714 clocks = <&aoss_qmp>; 2715 clock-names = "apb_pclk"; 2716 2717 qcom,cmb-element-bits = <32>; 2718 qcom,cmb-msrs-num = <32>; 2719 status = "disabled"; 2720 2721 out-ports { 2722 port { 2723 tpdm_dcc_out: endpoint { 2724 remote-endpoint = <&tpda_qdss_in8>; 2725 }; 2726 }; 2727 }; 2728 }; 2729 2730 tpdm@699c000 { 2731 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2732 reg = <0x0 0x0699c000 0x0 0x1000>; 2733 2734 clocks = <&aoss_qmp>; 2735 clock-names = "apb_pclk"; 2736 2737 qcom,cmb-element-bits = <32>; 2738 qcom,cmb-msrs-num = <32>; 2739 qcom,dsb-element-bits = <32>; 2740 qcom,dsb-msrs-num = <32>; 2741 status = "disabled"; 2742 2743 out-ports { 2744 port { 2745 tpdm_wcss_out: endpoint { 2746 remote-endpoint = <&funnel_in1_in4>; 2747 }; 2748 }; 2749 }; 2750 }; 2751 2752 tpdm@69c0000 { 2753 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2754 reg = <0x0 0x069c0000 0x0 0x1000>; 2755 2756 clocks = <&aoss_qmp>; 2757 clock-names = "apb_pclk"; 2758 2759 qcom,dsb-element-bits = <32>; 2760 qcom,dsb-msrs-num = <32>; 2761 2762 out-ports { 2763 port { 2764 tpdm_monaq_out: endpoint { 2765 remote-endpoint = <&funnel_monaq_in>; 2766 }; 2767 }; 2768 }; 2769 }; 2770 2771 funnel@69c3000 { 2772 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2773 reg = <0x0 0x069c3000 0x0 0x1000>; 2774 2775 clocks = <&aoss_qmp>; 2776 clock-names = "apb_pclk"; 2777 2778 in-ports { 2779 port { 2780 funnel_monaq_in: endpoint { 2781 remote-endpoint = <&tpdm_monaq_out>; 2782 }; 2783 }; 2784 }; 2785 2786 out-ports { 2787 port { 2788 funnel_monaq_out: endpoint { 2789 remote-endpoint = <&tpda_qdss_in4>; 2790 }; 2791 }; 2792 }; 2793 }; 2794 2795 tpdm@69d0000 { 2796 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2797 reg = <0x0 0x069d0000 0x0 0x1000>; 2798 2799 clocks = <&aoss_qmp>; 2800 clock-names = "apb_pclk"; 2801 2802 qcom,dsb-element-bits = <32>; 2803 qcom,dsb-msrs-num = <32>; 2804 status = "disabled"; 2805 2806 out-ports { 2807 port { 2808 tpdm_qm_out: endpoint { 2809 remote-endpoint = <&tpda_qdss_in11>; 2810 }; 2811 }; 2812 }; 2813 }; 2814 2815 tpdm@6a00000 { 2816 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2817 reg = <0x0 0x06a00000 0x0 0x1000>; 2818 2819 clocks = <&aoss_qmp>; 2820 clock-names = "apb_pclk"; 2821 2822 qcom,dsb-element-bits = <32>; 2823 qcom,dsb-msrs-num = <32>; 2824 status = "disabled"; 2825 2826 out-ports { 2827 port { 2828 tpdm_ddr_out: endpoint { 2829 remote-endpoint = <&funnel_ddr_0_in>; 2830 }; 2831 }; 2832 }; 2833 }; 2834 2835 cti@6a02000 { 2836 compatible = "arm,coresight-cti", "arm,primecell"; 2837 reg = <0x0 0x06a02000 0x0 0x1000>; 2838 2839 clocks = <&aoss_qmp>; 2840 clock-names = "apb_pclk"; 2841 }; 2842 2843 cti@6a03000 { 2844 compatible = "arm,coresight-cti", "arm,primecell"; 2845 reg = <0x0 0x06a03000 0x0 0x1000>; 2846 2847 clocks = <&aoss_qmp>; 2848 clock-names = "apb_pclk"; 2849 }; 2850 2851 cti@6a10000 { 2852 compatible = "arm,coresight-cti", "arm,primecell"; 2853 reg = <0x0 0x06a10000 0x0 0x1000>; 2854 2855 clocks = <&aoss_qmp>; 2856 clock-names = "apb_pclk"; 2857 }; 2858 2859 cti@6a11000 { 2860 compatible = "arm,coresight-cti", "arm,primecell"; 2861 reg = <0x0 0x06a11000 0x0 0x1000>; 2862 2863 clocks = <&aoss_qmp>; 2864 clock-names = "apb_pclk"; 2865 }; 2866 2867 funnel@6a05000 { 2868 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2869 reg = <0x0 0x06a05000 0x0 0x1000>; 2870 2871 clocks = <&aoss_qmp>; 2872 clock-names = "apb_pclk"; 2873 2874 in-ports { 2875 port { 2876 funnel_ddr_0_in: endpoint { 2877 remote-endpoint = <&tpdm_ddr_out>; 2878 }; 2879 }; 2880 }; 2881 2882 out-ports { 2883 port { 2884 funnel_ddr_0_out: endpoint { 2885 remote-endpoint = <&tpda_qdss_in5>; 2886 }; 2887 }; 2888 }; 2889 }; 2890 2891 tpda@6b01000 { 2892 compatible = "qcom,coresight-tpda", "arm,primecell"; 2893 reg = <0x0 0x06b01000 0x0 0x1000>; 2894 2895 clocks = <&aoss_qmp>; 2896 clock-names = "apb_pclk"; 2897 2898 in-ports { 2899 #address-cells = <1>; 2900 #size-cells = <0>; 2901 2902 port@0 { 2903 reg = <0>; 2904 2905 tpda_swao_in0: endpoint { 2906 remote-endpoint = <&tpdm_swao0_out>; 2907 }; 2908 }; 2909 2910 port@1 { 2911 reg = <1>; 2912 2913 tpda_swao_in1: endpoint { 2914 remote-endpoint = <&tpdm_swao1_out>; 2915 }; 2916 2917 }; 2918 }; 2919 2920 out-ports { 2921 port { 2922 tpda_swao_out: endpoint { 2923 remote-endpoint = <&funnel_swao_in7>; 2924 }; 2925 }; 2926 }; 2927 }; 2928 2929 tpdm@6b02000 { 2930 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2931 reg = <0x0 0x06b02000 0x0 0x1000>; 2932 2933 clocks = <&aoss_qmp>; 2934 clock-names = "apb_pclk"; 2935 2936 qcom,cmb-element-bits = <64>; 2937 qcom,cmb-msrs-num = <32>; 2938 status = "disabled"; 2939 2940 out-ports { 2941 port { 2942 tpdm_swao0_out: endpoint { 2943 remote-endpoint = <&tpda_swao_in0>; 2944 }; 2945 }; 2946 }; 2947 }; 2948 2949 tpdm@6b03000 { 2950 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2951 reg = <0x0 0x06b03000 0x0 0x1000>; 2952 2953 clocks = <&aoss_qmp>; 2954 clock-names = "apb_pclk"; 2955 2956 qcom,dsb-element-bits = <32>; 2957 qcom,dsb-msrs-num = <32>; 2958 status = "disabled"; 2959 2960 out-ports { 2961 port { 2962 tpdm_swao1_out: endpoint { 2963 remote-endpoint = <&tpda_swao_in1>; 2964 }; 2965 }; 2966 }; 2967 }; 2968 2969 cti@6b04000 { 2970 compatible = "arm,coresight-cti", "arm,primecell"; 2971 reg = <0x0 0x06b04000 0x0 0x1000>; 2972 2973 clocks = <&aoss_qmp>; 2974 clock-names = "apb_pclk"; 2975 }; 2976 2977 cti@6b05000 { 2978 compatible = "arm,coresight-cti", "arm,primecell"; 2979 reg = <0x0 0x06b05000 0x0 0x1000>; 2980 2981 clocks = <&aoss_qmp>; 2982 clock-names = "apb_pclk"; 2983 }; 2984 2985 cti@6b06000 { 2986 compatible = "arm,coresight-cti", "arm,primecell"; 2987 reg = <0x0 0x06b06000 0x0 0x1000>; 2988 2989 clocks = <&aoss_qmp>; 2990 clock-names = "apb_pclk"; 2991 }; 2992 2993 cti@6b07000 { 2994 compatible = "arm,coresight-cti", "arm,primecell"; 2995 reg = <0x0 0x06b07000 0x0 0x1000>; 2996 2997 clocks = <&aoss_qmp>; 2998 clock-names = "apb_pclk"; 2999 }; 3000 3001 funnel@6b08000 { 3002 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3003 reg = <0x0 0x06b08000 0x0 0x1000>; 3004 3005 clocks = <&aoss_qmp>; 3006 clock-names = "apb_pclk"; 3007 3008 in-ports { 3009 #address-cells = <1>; 3010 #size-cells = <0>; 3011 3012 port@6 { 3013 reg = <6>; 3014 3015 funnel_swao_in6: endpoint { 3016 remote-endpoint = <&replicator1_out>; 3017 }; 3018 }; 3019 3020 port@7 { 3021 reg = <7>; 3022 3023 funnel_swao_in7: endpoint { 3024 remote-endpoint = <&tpda_swao_out>; 3025 }; 3026 }; 3027 }; 3028 3029 out-ports { 3030 port { 3031 funnel_swao_out: endpoint { 3032 remote-endpoint = <&tmc_etf_swao_in>; 3033 }; 3034 }; 3035 }; 3036 }; 3037 3038 tmc@6b09000 { 3039 compatible = "arm,coresight-tmc", "arm,primecell"; 3040 reg = <0x0 0x06b09000 0x0 0x1000>; 3041 3042 clocks = <&aoss_qmp>; 3043 clock-names = "apb_pclk"; 3044 3045 in-ports { 3046 port { 3047 tmc_etf_swao_in: endpoint { 3048 remote-endpoint = <&funnel_swao_out>; 3049 }; 3050 }; 3051 }; 3052 3053 out-ports { 3054 port { 3055 tmc_etf_swao_out: endpoint { 3056 remote-endpoint = <&replicator_swao_in>; 3057 }; 3058 }; 3059 }; 3060 }; 3061 3062 replicator@6b0a000 { 3063 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3064 reg = <0x0 0x06b0a000 0x0 0x1000>; 3065 3066 clocks = <&aoss_qmp>; 3067 clock-names = "apb_pclk"; 3068 3069 in-ports { 3070 port { 3071 replicator_swao_in: endpoint { 3072 remote-endpoint = <&tmc_etf_swao_out>; 3073 }; 3074 }; 3075 }; 3076 3077 out-ports { 3078 #address-cells = <1>; 3079 #size-cells = <0>; 3080 3081 port@0 { 3082 reg = <0>; 3083 3084 replicator_swao_out0: endpoint { 3085 remote-endpoint = <&funnel_in1_in3>; 3086 }; 3087 }; 3088 3089 port@1 { 3090 reg = <1>; 3091 3092 replicator_swao_out1: endpoint { 3093 remote-endpoint = <&eud_in>; 3094 }; 3095 }; 3096 }; 3097 }; 3098 3099 cti@6b21000 { 3100 compatible = "arm,coresight-cti", "arm,primecell"; 3101 reg = <0x0 0x06b21000 0x0 0x1000>; 3102 3103 clocks = <&aoss_qmp>; 3104 clock-names = "apb_pclk"; 3105 }; 3106 3107 tpdm@6b48000 { 3108 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3109 reg = <0x0 0x06b48000 0x0 0x1000>; 3110 3111 clocks = <&aoss_qmp>; 3112 clock-names = "apb_pclk"; 3113 3114 qcom,dsb-element-bits = <32>; 3115 qcom,dsb-msrs-num = <32>; 3116 3117 out-ports { 3118 port { 3119 tpdm_west_out: endpoint { 3120 remote-endpoint = <&tpda_qdss_in12>; 3121 }; 3122 }; 3123 }; 3124 }; 3125 3126 cti@6c13000 { 3127 compatible = "arm,coresight-cti", "arm,primecell"; 3128 reg = <0x0 0x06c13000 0x0 0x1000>; 3129 3130 clocks = <&aoss_qmp>; 3131 clock-names = "apb_pclk"; 3132 3133 /* Not all required clocks can be enabled from the OS */ 3134 status = "fail"; 3135 }; 3136 3137 cti@6c20000 { 3138 compatible = "arm,coresight-cti", "arm,primecell"; 3139 reg = <0x0 0x06c20000 0x0 0x1000>; 3140 3141 clocks = <&aoss_qmp>; 3142 clock-names = "apb_pclk"; 3143 status = "disabled"; 3144 }; 3145 3146 tpdm@6c28000 { 3147 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3148 reg = <0x0 0x06c28000 0x0 0x1000>; 3149 3150 clocks = <&aoss_qmp>; 3151 clock-names = "apb_pclk"; 3152 3153 qcom,dsb-element-bits = <32>; 3154 qcom,dsb-msrs-num = <32>; 3155 3156 out-ports { 3157 port { 3158 tpdm_center_out: endpoint { 3159 remote-endpoint = <&tpda_qdss_in0>; 3160 }; 3161 }; 3162 }; 3163 }; 3164 3165 cti@6c29000 { 3166 compatible = "arm,coresight-cti", "arm,primecell"; 3167 reg = <0x0 0x06c29000 0x0 0x1000>; 3168 3169 clocks = <&aoss_qmp>; 3170 clock-names = "apb_pclk"; 3171 }; 3172 3173 cti@6c2a000 { 3174 compatible = "arm,coresight-cti", "arm,primecell"; 3175 reg = <0x0 0x06c2a000 0x0 0x1000>; 3176 3177 clocks = <&aoss_qmp>; 3178 clock-names = "apb_pclk"; 3179 }; 3180 3181 cti@7020000 { 3182 compatible = "arm,coresight-cti", "arm,primecell"; 3183 reg = <0x0 0x07020000 0x0 0x1000>; 3184 3185 clocks = <&aoss_qmp>; 3186 clock-names = "apb_pclk"; 3187 }; 3188 3189 etm@7040000 { 3190 compatible = "arm,primecell"; 3191 reg = <0x0 0x07040000 0x0 0x1000>; 3192 cpu = <&cpu0>; 3193 3194 clocks = <&aoss_qmp>; 3195 clock-names = "apb_pclk"; 3196 3197 arm,coresight-loses-context-with-cpu; 3198 qcom,skip-power-up; 3199 3200 out-ports { 3201 port { 3202 etm0_out: endpoint { 3203 remote-endpoint = <&funnel_apss_in0>; 3204 }; 3205 }; 3206 }; 3207 }; 3208 3209 cti@7120000 { 3210 compatible = "arm,coresight-cti", "arm,primecell"; 3211 reg = <0x0 0x07120000 0x0 0x1000>; 3212 3213 clocks = <&aoss_qmp>; 3214 clock-names = "apb_pclk"; 3215 }; 3216 3217 etm@7140000 { 3218 compatible = "arm,primecell"; 3219 reg = <0x0 0x07140000 0x0 0x1000>; 3220 cpu = <&cpu1>; 3221 3222 clocks = <&aoss_qmp>; 3223 clock-names = "apb_pclk"; 3224 3225 arm,coresight-loses-context-with-cpu; 3226 qcom,skip-power-up; 3227 3228 out-ports { 3229 port { 3230 etm1_out: endpoint { 3231 remote-endpoint = <&funnel_apss_in1>; 3232 }; 3233 }; 3234 }; 3235 }; 3236 3237 cti@7220000 { 3238 compatible = "arm,coresight-cti", "arm,primecell"; 3239 reg = <0x0 0x07220000 0x0 0x1000>; 3240 3241 clocks = <&aoss_qmp>; 3242 clock-names = "apb_pclk"; 3243 }; 3244 3245 etm@7240000 { 3246 compatible = "arm,primecell"; 3247 reg = <0x0 0x07240000 0x0 0x1000>; 3248 cpu = <&cpu2>; 3249 3250 clocks = <&aoss_qmp>; 3251 clock-names = "apb_pclk"; 3252 3253 arm,coresight-loses-context-with-cpu; 3254 qcom,skip-power-up; 3255 3256 out-ports { 3257 port { 3258 etm2_out: endpoint { 3259 remote-endpoint = <&funnel_apss_in2>; 3260 }; 3261 }; 3262 }; 3263 }; 3264 3265 cti@7320000 { 3266 compatible = "arm,coresight-cti", "arm,primecell"; 3267 reg = <0x0 0x07320000 0x0 0x1000>; 3268 3269 clocks = <&aoss_qmp>; 3270 clock-names = "apb_pclk"; 3271 }; 3272 3273 etm@7340000 { 3274 compatible = "arm,primecell"; 3275 reg = <0x0 0x07340000 0x0 0x1000>; 3276 cpu = <&cpu3>; 3277 3278 clocks = <&aoss_qmp>; 3279 clock-names = "apb_pclk"; 3280 3281 arm,coresight-loses-context-with-cpu; 3282 qcom,skip-power-up; 3283 3284 out-ports { 3285 port { 3286 etm3_out: endpoint { 3287 remote-endpoint = <&funnel_apss_in3>; 3288 }; 3289 }; 3290 }; 3291 }; 3292 3293 cti@7420000 { 3294 compatible = "arm,coresight-cti", "arm,primecell"; 3295 reg = <0x0 0x07420000 0x0 0x1000>; 3296 3297 clocks = <&aoss_qmp>; 3298 clock-names = "apb_pclk"; 3299 }; 3300 3301 etm@7440000 { 3302 compatible = "arm,primecell"; 3303 reg = <0x0 0x07440000 0x0 0x1000>; 3304 cpu = <&cpu4>; 3305 3306 clocks = <&aoss_qmp>; 3307 clock-names = "apb_pclk"; 3308 3309 arm,coresight-loses-context-with-cpu; 3310 qcom,skip-power-up; 3311 3312 out-ports { 3313 port { 3314 etm4_out: endpoint { 3315 remote-endpoint = <&funnel_apss_in4>; 3316 }; 3317 }; 3318 }; 3319 }; 3320 3321 cti@7520000 { 3322 compatible = "arm,coresight-cti", "arm,primecell"; 3323 reg = <0x0 0x07520000 0x0 0x1000>; 3324 3325 clocks = <&aoss_qmp>; 3326 clock-names = "apb_pclk"; 3327 }; 3328 3329 etm@7540000 { 3330 compatible = "arm,primecell"; 3331 reg = <0x0 0x07540000 0x0 0x1000>; 3332 cpu = <&cpu5>; 3333 3334 clocks = <&aoss_qmp>; 3335 clock-names = "apb_pclk"; 3336 3337 arm,coresight-loses-context-with-cpu; 3338 qcom,skip-power-up; 3339 3340 out-ports { 3341 port { 3342 etm5_out: endpoint { 3343 remote-endpoint = <&funnel_apss_in5>; 3344 }; 3345 }; 3346 }; 3347 }; 3348 3349 cti@7620000 { 3350 compatible = "arm,coresight-cti", "arm,primecell"; 3351 reg = <0x0 0x07620000 0x0 0x1000>; 3352 3353 clocks = <&aoss_qmp>; 3354 clock-names = "apb_pclk"; 3355 }; 3356 3357 etm@7640000 { 3358 compatible = "arm,primecell"; 3359 reg = <0x0 0x07640000 0x0 0x1000>; 3360 cpu = <&cpu6>; 3361 3362 clocks = <&aoss_qmp>; 3363 clock-names = "apb_pclk"; 3364 3365 arm,coresight-loses-context-with-cpu; 3366 qcom,skip-power-up; 3367 3368 out-ports { 3369 port { 3370 etm6_out: endpoint { 3371 remote-endpoint = <&funnel_apss_in6>; 3372 }; 3373 }; 3374 }; 3375 }; 3376 3377 cti@7720000 { 3378 compatible = "arm,coresight-cti", "arm,primecell"; 3379 reg = <0x0 0x07720000 0x0 0x1000>; 3380 3381 clocks = <&aoss_qmp>; 3382 clock-names = "apb_pclk"; 3383 }; 3384 3385 etm@7740000 { 3386 compatible = "arm,primecell"; 3387 reg = <0x0 0x07740000 0x0 0x1000>; 3388 cpu = <&cpu7>; 3389 3390 clocks = <&aoss_qmp>; 3391 clock-names = "apb_pclk"; 3392 3393 arm,coresight-loses-context-with-cpu; 3394 qcom,skip-power-up; 3395 3396 out-ports { 3397 port { 3398 etm7_out: endpoint { 3399 remote-endpoint = <&funnel_apss_in7>; 3400 }; 3401 }; 3402 }; 3403 }; 3404 3405 funnel@7800000 { 3406 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3407 reg = <0x0 0x07800000 0x0 0x1000>; 3408 3409 clocks = <&aoss_qmp>; 3410 clock-names = "apb_pclk"; 3411 3412 in-ports { 3413 #address-cells = <1>; 3414 #size-cells = <0>; 3415 3416 port@0 { 3417 reg = <0>; 3418 3419 funnel_apss_in0: endpoint { 3420 remote-endpoint = <&etm0_out>; 3421 }; 3422 }; 3423 3424 port@1 { 3425 reg = <1>; 3426 3427 funnel_apss_in1: endpoint { 3428 remote-endpoint = <&etm1_out>; 3429 }; 3430 }; 3431 3432 port@2 { 3433 reg = <2>; 3434 3435 funnel_apss_in2: endpoint { 3436 remote-endpoint = <&etm2_out>; 3437 }; 3438 }; 3439 3440 port@3 { 3441 reg = <3>; 3442 3443 funnel_apss_in3: endpoint { 3444 remote-endpoint = <&etm3_out>; 3445 }; 3446 }; 3447 3448 port@4 { 3449 reg = <4>; 3450 3451 funnel_apss_in4: endpoint { 3452 remote-endpoint = <&etm4_out>; 3453 }; 3454 }; 3455 3456 port@5 { 3457 reg = <5>; 3458 3459 funnel_apss_in5: endpoint { 3460 remote-endpoint = <&etm5_out>; 3461 }; 3462 }; 3463 3464 port@6 { 3465 reg = <6>; 3466 3467 funnel_apss_in6: endpoint { 3468 remote-endpoint = <&etm6_out>; 3469 }; 3470 }; 3471 3472 port@7 { 3473 reg = <7>; 3474 3475 funnel_apss_in7: endpoint { 3476 remote-endpoint = <&etm7_out>; 3477 }; 3478 }; 3479 }; 3480 3481 out-ports { 3482 port { 3483 funnel_apss_out: endpoint { 3484 remote-endpoint = <&funnel_apss_merg_in0>; 3485 }; 3486 }; 3487 }; 3488 }; 3489 3490 funnel@7810000 { 3491 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3492 reg = <0x0 0x07810000 0x0 0x1000>; 3493 3494 clocks = <&aoss_qmp>; 3495 clock-names = "apb_pclk"; 3496 3497 in-ports { 3498 #address-cells = <1>; 3499 #size-cells = <0>; 3500 3501 port@0 { 3502 reg = <0>; 3503 3504 funnel_apss_merg_in0: endpoint { 3505 remote-endpoint = <&funnel_apss_out>; 3506 }; 3507 }; 3508 3509 port@2 { 3510 reg = <2>; 3511 3512 funnel_apss_merg_in2: endpoint { 3513 remote-endpoint = <&tpda_olc_out>; 3514 }; 3515 }; 3516 3517 port@3 { 3518 reg = <3>; 3519 3520 funnel_apss_merg_in3: endpoint { 3521 remote-endpoint = <&tpda_llm_silver_out>; 3522 }; 3523 }; 3524 3525 port@4 { 3526 reg = <4>; 3527 3528 funnel_apss_merg_in4: endpoint { 3529 remote-endpoint = <&tpda_llm_gold_out>; 3530 }; 3531 }; 3532 3533 port@5 { 3534 reg = <5>; 3535 3536 funnel_apss_merg_in5: endpoint { 3537 remote-endpoint = <&tpda_apss_out>; 3538 }; 3539 }; 3540 }; 3541 3542 out-ports { 3543 port { 3544 funnel_apss_merg_out: endpoint { 3545 remote-endpoint = <&funnel_in1_in7>; 3546 }; 3547 }; 3548 }; 3549 }; 3550 3551 tpdm@7830000 { 3552 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3553 reg = <0x0 0x07830000 0x0 0x1000>; 3554 3555 clocks = <&aoss_qmp>; 3556 clock-names = "apb_pclk"; 3557 3558 qcom,cmb-element-bits = <64>; 3559 qcom,cmb-msrs-num = <32>; 3560 3561 out-ports { 3562 port { 3563 tpdm_olc_out: endpoint { 3564 remote-endpoint = <&tpda_olc_in>; 3565 }; 3566 }; 3567 }; 3568 }; 3569 3570 tpda@7832000 { 3571 compatible = "qcom,coresight-tpda", "arm,primecell"; 3572 reg = <0x0 0x07832000 0x0 0x1000>; 3573 3574 clocks = <&aoss_qmp>; 3575 clock-names = "apb_pclk"; 3576 3577 in-ports { 3578 port { 3579 tpda_olc_in: endpoint { 3580 remote-endpoint = <&tpdm_olc_out>; 3581 }; 3582 }; 3583 }; 3584 3585 out-ports { 3586 port { 3587 tpda_olc_out: endpoint { 3588 remote-endpoint = <&funnel_apss_merg_in2>; 3589 }; 3590 }; 3591 }; 3592 }; 3593 3594 tpdm@7860000 { 3595 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3596 reg = <0x0 0x07860000 0x0 0x1000>; 3597 3598 clocks = <&aoss_qmp>; 3599 clock-names = "apb_pclk"; 3600 3601 qcom,dsb-element-bits = <32>; 3602 qcom,dsb-msrs-num = <32>; 3603 3604 out-ports { 3605 port { 3606 tpdm_apss_out: endpoint { 3607 remote-endpoint = <&tpda_apss_in>; 3608 }; 3609 }; 3610 }; 3611 }; 3612 3613 tpda@7862000 { 3614 compatible = "qcom,coresight-tpda", "arm,primecell"; 3615 reg = <0x0 0x07862000 0x0 0x1000>; 3616 3617 clocks = <&aoss_qmp>; 3618 clock-names = "apb_pclk"; 3619 3620 in-ports { 3621 port { 3622 tpda_apss_in: endpoint { 3623 remote-endpoint = <&tpdm_apss_out>; 3624 }; 3625 }; 3626 }; 3627 3628 out-ports { 3629 port { 3630 tpda_apss_out: endpoint { 3631 remote-endpoint = <&funnel_apss_merg_in5>; 3632 }; 3633 }; 3634 }; 3635 }; 3636 3637 tpdm@78a0000 { 3638 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3639 reg = <0x0 0x078a0000 0x0 0x1000>; 3640 3641 clocks = <&aoss_qmp>; 3642 clock-names = "apb_pclk"; 3643 3644 qcom,cmb-element-bits = <32>; 3645 qcom,cmb-msrs-num = <32>; 3646 3647 out-ports { 3648 port { 3649 tpdm_llm_silver_out: endpoint { 3650 remote-endpoint = <&tpda_llm_silver_in>; 3651 }; 3652 }; 3653 }; 3654 }; 3655 3656 tpdm@78b0000 { 3657 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3658 reg = <0x0 0x078b0000 0x0 0x1000>; 3659 3660 clocks = <&aoss_qmp>; 3661 clock-names = "apb_pclk"; 3662 3663 qcom,cmb-element-bits = <32>; 3664 qcom,cmb-msrs-num = <32>; 3665 3666 out-ports { 3667 port { 3668 tpdm_llm_gold_out: endpoint { 3669 remote-endpoint = <&tpda_llm_gold_in>; 3670 }; 3671 }; 3672 }; 3673 }; 3674 3675 tpda@78c0000 { 3676 compatible = "qcom,coresight-tpda", "arm,primecell"; 3677 reg = <0x0 0x078c0000 0x0 0x1000>; 3678 3679 clocks = <&aoss_qmp>; 3680 clock-names = "apb_pclk"; 3681 3682 in-ports { 3683 port { 3684 tpda_llm_silver_in: endpoint { 3685 remote-endpoint = <&tpdm_llm_silver_out>; 3686 }; 3687 }; 3688 }; 3689 3690 out-ports { 3691 port { 3692 tpda_llm_silver_out: endpoint { 3693 remote-endpoint = <&funnel_apss_merg_in3>; 3694 }; 3695 }; 3696 }; 3697 }; 3698 3699 tpda@78d0000 { 3700 compatible = "qcom,coresight-tpda", "arm,primecell"; 3701 reg = <0x0 0x078d0000 0x0 0x1000>; 3702 3703 clocks = <&aoss_qmp>; 3704 clock-names = "apb_pclk"; 3705 3706 in-ports { 3707 port { 3708 tpda_llm_gold_in: endpoint { 3709 remote-endpoint = <&tpdm_llm_gold_out>; 3710 }; 3711 }; 3712 }; 3713 3714 out-ports { 3715 port { 3716 tpda_llm_gold_out: endpoint { 3717 remote-endpoint = <&funnel_apss_merg_in4>; 3718 }; 3719 }; 3720 }; 3721 }; 3722 3723 cti@78e0000 { 3724 compatible = "arm,coresight-cti", "arm,primecell"; 3725 reg = <0x0 0x078e0000 0x0 0x1000>; 3726 3727 clocks = <&aoss_qmp>; 3728 clock-names = "apb_pclk"; 3729 }; 3730 3731 cti@78f0000 { 3732 compatible = "arm,coresight-cti", "arm,primecell"; 3733 reg = <0x0 0x078f0000 0x0 0x1000>; 3734 3735 clocks = <&aoss_qmp>; 3736 clock-names = "apb_pclk"; 3737 }; 3738 3739 cti@7900000 { 3740 compatible = "arm,coresight-cti", "arm,primecell"; 3741 reg = <0x0 0x07900000 0x0 0x1000>; 3742 3743 clocks = <&aoss_qmp>; 3744 clock-names = "apb_pclk"; 3745 }; 3746 3747 remoteproc_cdsp: remoteproc@8300000 { 3748 compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas"; 3749 reg = <0x0 0x08300000 0x0 0x4040>; 3750 3751 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, 3752 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3753 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3754 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3755 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3756 interrupt-names = "wdog", 3757 "fatal", 3758 "ready", 3759 "handover", 3760 "stop-ack"; 3761 3762 clocks = <&rpmhcc RPMH_CXO_CLK>; 3763 clock-names = "xo"; 3764 3765 power-domains = <&rpmhpd RPMHPD_CX>; 3766 power-domain-names = "cx"; 3767 3768 memory-region = <&rproc_cdsp_mem>; 3769 3770 qcom,qmp = <&aoss_qmp>; 3771 3772 qcom,smem-states = <&cdsp_smp2p_out 0>; 3773 qcom,smem-state-names = "stop"; 3774 3775 status = "disabled"; 3776 3777 glink-edge { 3778 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING 0>; 3779 mboxes = <&apss_shared 4>; 3780 label = "cdsp"; 3781 qcom,remote-pid = <5>; 3782 3783 fastrpc { 3784 compatible = "qcom,fastrpc"; 3785 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3786 label = "cdsp"; 3787 #address-cells = <1>; 3788 #size-cells = <0>; 3789 3790 compute-cb@1 { 3791 compatible = "qcom,fastrpc-compute-cb"; 3792 reg = <1>; 3793 iommus = <&apps_smmu 0x1081 0x0>; 3794 dma-coherent; 3795 }; 3796 3797 compute-cb@2 { 3798 compatible = "qcom,fastrpc-compute-cb"; 3799 reg = <2>; 3800 iommus = <&apps_smmu 0x1082 0x0>; 3801 dma-coherent; 3802 }; 3803 3804 compute-cb@3 { 3805 compatible = "qcom,fastrpc-compute-cb"; 3806 reg = <3>; 3807 iommus = <&apps_smmu 0x1083 0x0>; 3808 dma-coherent; 3809 }; 3810 3811 compute-cb@4 { 3812 compatible = "qcom,fastrpc-compute-cb"; 3813 reg = <4>; 3814 iommus = <&apps_smmu 0x1084 0x0>; 3815 dma-coherent; 3816 }; 3817 3818 compute-cb@5 { 3819 compatible = "qcom,fastrpc-compute-cb"; 3820 reg = <5>; 3821 iommus = <&apps_smmu 0x1085 0x0>; 3822 dma-coherent; 3823 }; 3824 3825 compute-cb@6 { 3826 compatible = "qcom,fastrpc-compute-cb"; 3827 reg = <6>; 3828 iommus = <&apps_smmu 0x1086 0x0>; 3829 dma-coherent; 3830 }; 3831 }; 3832 }; 3833 }; 3834 3835 pmu@90b6300 { 3836 compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon"; 3837 reg = <0x0 0x090b6300 0x0 0x600>; 3838 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>; 3839 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3840 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3841 3842 operating-points-v2 = <&cpu_bwmon_opp_table>; 3843 3844 cpu_bwmon_opp_table: opp-table { 3845 compatible = "operating-points-v2"; 3846 3847 opp-0 { 3848 opp-peak-kBps = <12896000>; 3849 }; 3850 3851 opp-1 { 3852 opp-peak-kBps = <14928000>; 3853 }; 3854 }; 3855 }; 3856 3857 pmu@90cd000 { 3858 compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3859 reg = <0x0 0x090cd000 0x0 0x1000>; 3860 interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH 0>; 3861 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 3862 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3863 3864 operating-points-v2 = <&llcc_bwmon_opp_table>; 3865 3866 llcc_bwmon_opp_table: opp-table { 3867 compatible = "operating-points-v2"; 3868 3869 opp-0 { 3870 opp-peak-kBps = <800000>; 3871 }; 3872 3873 opp-1 { 3874 opp-peak-kBps = <1200000>; 3875 }; 3876 3877 opp-2 { 3878 opp-peak-kBps = <1804800>; 3879 }; 3880 3881 opp-3 { 3882 opp-peak-kBps = <2188800>; 3883 }; 3884 3885 opp-4 { 3886 opp-peak-kBps = <2726400>; 3887 }; 3888 3889 opp-5 { 3890 opp-peak-kBps = <3072000>; 3891 }; 3892 3893 opp-6 { 3894 opp-peak-kBps = <4070400>; 3895 }; 3896 3897 opp-7 { 3898 opp-peak-kBps = <5414400>; 3899 }; 3900 3901 opp-8 { 3902 opp-peak-kBps = <6220800>; 3903 }; 3904 }; 3905 }; 3906 3907 sdhc_2: mmc@8804000 { 3908 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 3909 reg = <0x0 0x08804000 0x0 0x1000>; 3910 reg-names = "hc"; 3911 3912 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>, 3913 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; 3914 interrupt-names = "hc_irq", 3915 "pwr_irq"; 3916 3917 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3918 <&gcc GCC_SDCC2_APPS_CLK>, 3919 <&rpmhcc RPMH_CXO_CLK>; 3920 clock-names = "iface", 3921 "core", 3922 "xo"; 3923 3924 power-domains = <&rpmhpd RPMHPD_CX>; 3925 operating-points-v2 = <&sdhc2_opp_table>; 3926 iommus = <&apps_smmu 0x02a0 0x0>; 3927 resets = <&gcc GCC_SDCC2_BCR>; 3928 interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3929 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3930 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3931 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 3932 interconnect-names = "sdhc-ddr", 3933 "cpu-sdhc"; 3934 3935 qcom,dll-config = <0x0007642c>; 3936 qcom,ddr-config = <0x80040868>; 3937 dma-coherent; 3938 3939 status = "disabled"; 3940 3941 sdhc2_opp_table: opp-table { 3942 compatible = "operating-points-v2"; 3943 3944 opp-50000000 { 3945 opp-hz = /bits/ 64 <50000000>; 3946 required-opps = <&rpmhpd_opp_low_svs>; 3947 }; 3948 3949 opp-100000000 { 3950 opp-hz = /bits/ 64 <100000000>; 3951 required-opps = <&rpmhpd_opp_svs>; 3952 }; 3953 3954 opp-202000000 { 3955 opp-hz = /bits/ 64 <202000000>; 3956 required-opps = <&rpmhpd_opp_nom>; 3957 }; 3958 }; 3959 }; 3960 3961 qspi: spi@88df000 { 3962 compatible = "qcom,qcs615-qspi", 3963 "qcom,qspi-v1"; 3964 reg = <0x0 0x088df000 0x0 0x1000>; 3965 3966 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH 0>; 3967 3968 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3969 <&gcc GCC_QSPI_CORE_CLK>; 3970 clock-names = "iface", 3971 "core"; 3972 3973 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3974 &config_noc SLAVE_QSPI QCOM_ICC_TAG_ACTIVE_ONLY>, 3975 <&aggre1_noc MASTER_QSPI QCOM_ICC_TAG_ALWAYS 3976 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3977 interconnect-names = "qspi-config", 3978 "qspi-memory"; 3979 3980 power-domains = <&rpmhpd RPMHPD_CX>; 3981 operating-points-v2 = <&qspi_opp_table>; 3982 3983 iommus = <&apps_smmu 0x160 0x0>; 3984 3985 pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0123>; 3986 pinctrl-names = "default"; 3987 3988 #address-cells = <1>; 3989 #size-cells = <0>; 3990 3991 status = "disabled"; 3992 }; 3993 3994 dc_noc: interconnect@9160000 { 3995 reg = <0x0 0x09160000 0x0 0x3200>; 3996 compatible = "qcom,qcs615-dc-noc"; 3997 #interconnect-cells = <2>; 3998 qcom,bcm-voters = <&apps_bcm_voter>; 3999 }; 4000 4001 llcc: system-cache-controller@9200000 { 4002 compatible = "qcom,qcs615-llcc"; 4003 reg = <0x0 0x09200000 0x0 0x50000>, 4004 <0x0 0x09600000 0x0 0x50000>; 4005 reg-names = "llcc0_base", 4006 "llcc_broadcast_base"; 4007 }; 4008 4009 gem_noc: interconnect@9680000 { 4010 reg = <0x0 0x09680000 0x0 0x3e200>; 4011 compatible = "qcom,qcs615-gem-noc"; 4012 #interconnect-cells = <2>; 4013 qcom,bcm-voters = <&apps_bcm_voter>; 4014 }; 4015 4016 venus: video-codec@aa00000 { 4017 compatible = "qcom,qcs615-venus", "qcom,sc7180-venus"; 4018 reg = <0x0 0x0aa00000 0x0 0x100000>; 4019 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; 4020 4021 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 4022 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4023 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 4024 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 4025 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 4026 clock-names = "core", 4027 "iface", 4028 "bus", 4029 "vcodec0_core", 4030 "vcodec0_bus"; 4031 4032 power-domains = <&videocc VENUS_GDSC>, 4033 <&videocc VCODEC0_GDSC>, 4034 <&rpmhpd RPMHPD_CX>; 4035 power-domain-names = "venus", 4036 "vcodec0", 4037 "cx"; 4038 4039 operating-points-v2 = <&venus_opp_table>; 4040 4041 interconnects = <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 4042 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4043 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4044 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4045 interconnect-names = "video-mem", 4046 "cpu-cfg"; 4047 4048 iommus = <&apps_smmu 0xe60 0x20>; 4049 4050 memory-region = <&pil_video_mem>; 4051 4052 status = "disabled"; 4053 4054 venus_opp_table: opp-table { 4055 compatible = "operating-points-v2"; 4056 4057 opp-133330000 { 4058 opp-hz = /bits/ 64 <133330000>; 4059 required-opps = <&rpmhpd_opp_low_svs>; 4060 }; 4061 4062 opp-240000000 { 4063 opp-hz = /bits/ 64 <240000000>; 4064 required-opps = <&rpmhpd_opp_svs>; 4065 }; 4066 4067 opp-300000000 { 4068 opp-hz = /bits/ 64 <300000000>; 4069 required-opps = <&rpmhpd_opp_svs_l1>; 4070 }; 4071 4072 opp-380000000 { 4073 opp-hz = /bits/ 64 <380000000>; 4074 required-opps = <&rpmhpd_opp_nom>; 4075 }; 4076 4077 opp-410000000 { 4078 opp-hz = /bits/ 64 <410000000>; 4079 required-opps = <&rpmhpd_opp_nom_l1>; 4080 }; 4081 4082 opp-460000000 { 4083 opp-hz = /bits/ 64 <460000000>; 4084 required-opps = <&rpmhpd_opp_turbo>; 4085 }; 4086 }; 4087 }; 4088 4089 videocc: clock-controller@ab00000 { 4090 compatible = "qcom,qcs615-videocc"; 4091 reg = <0 0x0ab00000 0 0x10000>; 4092 4093 clocks = <&rpmhcc RPMH_CXO_CLK>, 4094 <&sleep_clk>; 4095 4096 #clock-cells = <1>; 4097 #reset-cells = <1>; 4098 #power-domain-cells = <1>; 4099 }; 4100 4101 cci: cci@ac4a000 { 4102 compatible = "qcom,sm6150-cci", "qcom,msm8996-cci"; 4103 4104 reg = <0x0 0x0ac4a000 0x0 0x4000>; 4105 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING 0>; 4106 power-domains = <&camcc TITAN_TOP_GDSC>; 4107 clocks = <&camcc CAM_CC_SOC_AHB_CLK>, 4108 <&camcc CAM_CC_CPAS_AHB_CLK>, 4109 <&camcc CAM_CC_CCI_CLK>; 4110 clock-names = "camnoc_axi", 4111 "cpas_ahb", 4112 "cci"; 4113 pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>; 4114 pinctrl-names = "default"; 4115 4116 #address-cells = <1>; 4117 #size-cells = <0>; 4118 4119 status = "disabled"; 4120 4121 cci_i2c0: i2c-bus@0 { 4122 reg = <0>; 4123 clock-frequency = <1000000>; 4124 #address-cells = <1>; 4125 #size-cells = <0>; 4126 }; 4127 4128 cci_i2c1: i2c-bus@1 { 4129 reg = <1>; 4130 clock-frequency = <1000000>; 4131 #address-cells = <1>; 4132 #size-cells = <0>; 4133 }; 4134 }; 4135 4136 camss: isp@acb3000 { 4137 compatible = "qcom,sm6150-camss"; 4138 4139 reg = <0x0 0x0acb3000 0x0 0x1000>, 4140 <0x0 0x0acba000 0x0 0x1000>, 4141 <0x0 0x0acc8000 0x0 0x1000>, 4142 <0x0 0x0ac65000 0x0 0x1000>, 4143 <0x0 0x0ac66000 0x0 0x1000>, 4144 <0x0 0x0ac67000 0x0 0x1000>, 4145 <0x0 0x0acaf000 0x0 0x4000>, 4146 <0x0 0x0acb6000 0x0 0x4000>, 4147 <0x0 0x0acc4000 0x0 0x4000>, 4148 <0x0 0x0ac6f000 0x0 0x3000>, 4149 <0x0 0x0ac42000 0x0 0x5000>, 4150 <0x0 0x0ac48000 0x0 0x1000>, 4151 <0x0 0x0ac40000 0x0 0x1000>, 4152 <0x0 0x0ac18000 0x0 0x3000>, 4153 <0x0 0x0ac00000 0x0 0x6000>, 4154 <0x0 0x0ac10000 0x0 0x8000>, 4155 <0x0 0x0ac87000 0x0 0x3000>, 4156 <0x0 0x0ac52000 0x0 0x4000>, 4157 <0x0 0x0ac4e000 0x0 0x4000>, 4158 <0x0 0x0ac6b000 0x0 0x0a00>; 4159 reg-names = "csid0", 4160 "csid1", 4161 "csid_lite", 4162 "csiphy0", 4163 "csiphy1", 4164 "csiphy2", 4165 "vfe0", 4166 "vfe1", 4167 "vfe_lite", 4168 "bps", 4169 "camnoc", 4170 "cpas_cdm", 4171 "cpas_top", 4172 "icp_csr", 4173 "icp_qgic", 4174 "icp_sierra", 4175 "ipe0", 4176 "jpeg_dma", 4177 "jpeg_enc", 4178 "lrme"; 4179 4180 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4181 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4182 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4183 <&camcc CAM_CC_CPAS_AHB_CLK>, 4184 <&camcc CAM_CC_CSIPHY0_CLK>, 4185 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4186 <&camcc CAM_CC_CSIPHY1_CLK>, 4187 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4188 <&camcc CAM_CC_CSIPHY2_CLK>, 4189 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4190 <&camcc CAM_CC_SOC_AHB_CLK>, 4191 <&camcc CAM_CC_IFE_0_CLK>, 4192 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4193 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4194 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4195 <&camcc CAM_CC_IFE_1_CLK>, 4196 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4197 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4198 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4199 <&camcc CAM_CC_IFE_LITE_CLK>, 4200 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4201 <&camcc CAM_CC_IFE_LITE_CSID_CLK>, 4202 <&camcc CAM_CC_BPS_CLK>, 4203 <&camcc CAM_CC_BPS_AHB_CLK>, 4204 <&camcc CAM_CC_BPS_AXI_CLK>, 4205 <&camcc CAM_CC_BPS_AREG_CLK>, 4206 <&camcc CAM_CC_ICP_CLK>, 4207 <&camcc CAM_CC_IPE_0_CLK>, 4208 <&camcc CAM_CC_IPE_0_AHB_CLK>, 4209 <&camcc CAM_CC_IPE_0_AREG_CLK>, 4210 <&camcc CAM_CC_IPE_0_AXI_CLK>, 4211 <&camcc CAM_CC_JPEG_CLK>, 4212 <&camcc CAM_CC_LRME_CLK>; 4213 clock-names = "gcc_ahb", 4214 "gcc_axi_hf", 4215 "camnoc_axi", 4216 "cpas_ahb", 4217 "csiphy0", 4218 "csiphy0_timer", 4219 "csiphy1", 4220 "csiphy1_timer", 4221 "csiphy2", 4222 "csiphy2_timer", 4223 "soc_ahb", 4224 "vfe0", 4225 "vfe0_axi", 4226 "vfe0_cphy_rx", 4227 "vfe0_csid", 4228 "vfe1", 4229 "vfe1_axi", 4230 "vfe1_cphy_rx", 4231 "vfe1_csid", 4232 "vfe_lite", 4233 "vfe_lite_cphy_rx", 4234 "vfe_lite_csid", 4235 "bps", 4236 "bps_ahb", 4237 "bps_axi", 4238 "bps_areg", 4239 "icp", 4240 "ipe0", 4241 "ipe0_ahb", 4242 "ipe0_areg", 4243 "ipe0_axi", 4244 "jpeg", 4245 "lrme"; 4246 4247 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4248 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4249 <&mmss_noc MASTER_CAMNOC_HF0 QCOM_ICC_TAG_ALWAYS 4250 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4251 <&mmss_noc MASTER_CAMNOC_HF1 QCOM_ICC_TAG_ALWAYS 4252 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4253 <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS 4254 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4255 interconnect-names = "ahb", 4256 "hf_0", 4257 "hf_1", 4258 "sf_mnoc"; 4259 4260 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING 0>, 4261 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING 0>, 4262 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING 0>, 4263 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>, 4264 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>, 4265 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>, 4266 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING 0>, 4267 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING 0>, 4268 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING 0>, 4269 <GIC_SPI 459 IRQ_TYPE_EDGE_RISING 0>, 4270 <GIC_SPI 461 IRQ_TYPE_EDGE_RISING 0>, 4271 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING 0>, 4272 <GIC_SPI 475 IRQ_TYPE_EDGE_RISING 0>, 4273 <GIC_SPI 474 IRQ_TYPE_EDGE_RISING 0>, 4274 <GIC_SPI 476 IRQ_TYPE_EDGE_RISING 0>; 4275 interrupt-names = "csid0", 4276 "csid1", 4277 "csid_lite", 4278 "csiphy0", 4279 "csiphy1", 4280 "csiphy2", 4281 "vfe0", 4282 "vfe1", 4283 "vfe_lite", 4284 "camnoc", 4285 "cdm", 4286 "icp", 4287 "jpeg_dma", 4288 "jpeg_enc", 4289 "lrme"; 4290 4291 iommus = <&apps_smmu 0x0820 0x40>, 4292 <&apps_smmu 0x0840 0x00>, 4293 <&apps_smmu 0x0860 0x40>, 4294 <&apps_smmu 0x0c00 0x00>, 4295 <&apps_smmu 0x0cc0 0x00>, 4296 <&apps_smmu 0x0c80 0x00>, 4297 <&apps_smmu 0x0ca0 0x00>, 4298 <&apps_smmu 0x0d00 0x00>, 4299 <&apps_smmu 0x0d20 0x00>, 4300 <&apps_smmu 0x0d40 0x00>, 4301 <&apps_smmu 0x0d80 0x20>, 4302 <&apps_smmu 0x0da0 0x20>, 4303 <&apps_smmu 0x0de2 0x00>; 4304 4305 power-domains = <&camcc IFE_0_GDSC>, 4306 <&camcc IFE_1_GDSC>, 4307 <&camcc TITAN_TOP_GDSC>, 4308 <&camcc BPS_GDSC>, 4309 <&camcc IPE_0_GDSC>; 4310 power-domain-names = "ife0", 4311 "ife1", 4312 "top", 4313 "bps", 4314 "ipe"; 4315 4316 status = "disabled"; 4317 4318 ports { 4319 #address-cells = <1>; 4320 #size-cells = <0>; 4321 4322 port@0 { 4323 reg = <0>; 4324 }; 4325 4326 port@1 { 4327 reg = <1>; 4328 }; 4329 4330 port@2 { 4331 reg = <2>; 4332 }; 4333 }; 4334 }; 4335 4336 camcc: clock-controller@ad00000 { 4337 compatible = "qcom,qcs615-camcc"; 4338 reg = <0 0x0ad00000 0 0x10000>; 4339 4340 clocks = <&rpmhcc RPMH_CXO_CLK>; 4341 4342 #clock-cells = <1>; 4343 #reset-cells = <1>; 4344 #power-domain-cells = <1>; 4345 }; 4346 4347 mdss: display-subsystem@ae00000 { 4348 compatible = "qcom,sm6150-mdss"; 4349 reg = <0x0 0x0ae00000 0x0 0x1000>; 4350 reg-names = "mdss"; 4351 4352 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 4353 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4354 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4355 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4356 interconnect-names = "mdp0-mem", 4357 "cpu-cfg"; 4358 4359 power-domains = <&dispcc MDSS_CORE_GDSC>; 4360 4361 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4362 <&gcc GCC_DISP_HF_AXI_CLK>, 4363 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4364 4365 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>; 4366 interrupt-controller; 4367 #interrupt-cells = <1>; 4368 4369 iommus = <&apps_smmu 0x800 0x0>; 4370 4371 #address-cells = <2>; 4372 #size-cells = <2>; 4373 ranges; 4374 4375 status = "disabled"; 4376 4377 mdss_mdp: display-controller@ae01000 { 4378 compatible = "qcom,sm6150-dpu"; 4379 reg = <0x0 0x0ae01000 0x0 0x8f000>, 4380 <0x0 0x0aeb0000 0x0 0x2008>; 4381 reg-names = "mdp", 4382 "vbif"; 4383 4384 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4385 <&gcc GCC_DISP_HF_AXI_CLK>, 4386 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4387 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4388 clock-names = "iface", 4389 "bus", 4390 "core", 4391 "vsync"; 4392 4393 operating-points-v2 = <&mdp_opp_table>; 4394 power-domains = <&rpmhpd RPMHPD_CX>; 4395 4396 interrupts-extended = <&mdss 0>; 4397 4398 ports { 4399 #address-cells = <1>; 4400 #size-cells = <0>; 4401 4402 port@0 { 4403 reg = <0>; 4404 4405 dpu_intf0_out: endpoint { 4406 remote-endpoint = <&mdss_dp0_in>; 4407 }; 4408 }; 4409 4410 port@1 { 4411 reg = <1>; 4412 4413 dpu_intf1_out: endpoint { 4414 remote-endpoint = <&mdss_dsi0_in>; 4415 }; 4416 }; 4417 }; 4418 4419 mdp_opp_table: opp-table { 4420 compatible = "operating-points-v2"; 4421 4422 opp-192000000 { 4423 opp-hz = /bits/ 64 <192000000>; 4424 required-opps = <&rpmhpd_opp_low_svs>; 4425 }; 4426 4427 opp-256000000 { 4428 opp-hz = /bits/ 64 <256000000>; 4429 required-opps = <&rpmhpd_opp_svs>; 4430 }; 4431 4432 opp-307200000 { 4433 opp-hz = /bits/ 64 <307200000>; 4434 required-opps = <&rpmhpd_opp_nom>; 4435 }; 4436 }; 4437 }; 4438 4439 mdss_dp0: displayport-controller@ae90000 { 4440 compatible = "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp"; 4441 4442 reg = <0x0 0x0ae90000 0x0 0x200>, 4443 <0x0 0x0ae90200 0x0 0x200>, 4444 <0x0 0x0ae90400 0x0 0x600>, 4445 <0x0 0x0ae90a00 0x0 0x600>, 4446 <0x0 0x0ae91000 0x0 0x600>; 4447 4448 interrupt-parent = <&mdss>; 4449 interrupts = <12>; 4450 4451 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4452 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4453 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4454 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4455 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, 4456 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; 4457 clock-names = "core_iface", 4458 "core_aux", 4459 "ctrl_link", 4460 "ctrl_link_iface", 4461 "stream_pixel", 4462 "stream_1_pixel"; 4463 4464 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4465 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, 4466 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; 4467 assigned-clock-parents = <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, 4468 <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>, 4469 <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; 4470 4471 phys = <&usb_qmpphy_2 QMP_USB43DP_DP_PHY>; 4472 phy-names = "dp"; 4473 4474 operating-points-v2 = <&dp_opp_table>; 4475 power-domains = <&rpmhpd RPMHPD_CX>; 4476 4477 #sound-dai-cells = <0>; 4478 4479 status = "disabled"; 4480 4481 ports { 4482 #address-cells = <1>; 4483 #size-cells = <0>; 4484 4485 port@0 { 4486 reg = <0>; 4487 4488 mdss_dp0_in: endpoint { 4489 remote-endpoint = <&dpu_intf0_out>; 4490 }; 4491 }; 4492 4493 port@1 { 4494 reg = <1>; 4495 4496 mdss_dp0_out: endpoint { 4497 data-lanes = <3 2 0 1>; 4498 }; 4499 }; 4500 }; 4501 4502 dp_opp_table: opp-table { 4503 compatible = "operating-points-v2"; 4504 4505 opp-162000000 { 4506 opp-hz = /bits/ 64 <162000000>; 4507 required-opps = <&rpmhpd_opp_low_svs>; 4508 }; 4509 4510 opp-270000000 { 4511 opp-hz = /bits/ 64 <270000000>; 4512 required-opps = <&rpmhpd_opp_svs>; 4513 }; 4514 4515 opp-540000000 { 4516 opp-hz = /bits/ 64 <540000000>; 4517 required-opps = <&rpmhpd_opp_svs_l1>; 4518 }; 4519 }; 4520 }; 4521 4522 mdss_dsi0: dsi@ae94000 { 4523 compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 4524 reg = <0x0 0x0ae94000 0x0 0x400>; 4525 reg-names = "dsi_ctrl"; 4526 4527 interrupts-extended = <&mdss 4>; 4528 4529 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4530 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4531 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4532 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4533 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4534 <&gcc GCC_DISP_HF_AXI_CLK>; 4535 clock-names = "byte", 4536 "byte_intf", 4537 "pixel", 4538 "core", 4539 "iface", 4540 "bus"; 4541 4542 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 4543 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4544 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4545 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 4546 4547 operating-points-v2 = <&dsi0_opp_table>; 4548 power-domains = <&rpmhpd RPMHPD_CX>; 4549 4550 phys = <&mdss_dsi0_phy>; 4551 4552 #address-cells = <1>; 4553 #size-cells = <0>; 4554 4555 status = "disabled"; 4556 4557 dsi0_opp_table: opp-table { 4558 compatible = "operating-points-v2"; 4559 4560 opp-164000000 { 4561 opp-hz = /bits/ 64 <164000000>; 4562 required-opps = <&rpmhpd_opp_low_svs>; 4563 }; 4564 }; 4565 4566 ports { 4567 #address-cells = <1>; 4568 #size-cells = <0>; 4569 4570 port@0 { 4571 reg = <0>; 4572 4573 mdss_dsi0_in: endpoint { 4574 remote-endpoint = <&dpu_intf1_out>; 4575 }; 4576 }; 4577 4578 port@1 { 4579 reg = <1>; 4580 4581 mdss_dsi0_out: endpoint { 4582 }; 4583 }; 4584 }; 4585 }; 4586 4587 mdss_dsi0_phy: phy@ae94400 { 4588 compatible = "qcom,sm6150-dsi-phy-14nm"; 4589 reg = <0x0 0x0ae94400 0x0 0x100>, 4590 <0x0 0x0ae94500 0x0 0x300>, 4591 <0x0 0x0ae94800 0x0 0x124>; 4592 reg-names = "dsi_phy", 4593 "dsi_phy_lane", 4594 "dsi_pll"; 4595 4596 #clock-cells = <1>; 4597 #phy-cells = <0>; 4598 4599 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4600 <&rpmhcc RPMH_CXO_CLK>; 4601 clock-names = "iface", 4602 "ref"; 4603 4604 status = "disabled"; 4605 }; 4606 }; 4607 4608 dispcc: clock-controller@af00000 { 4609 compatible = "qcom,qcs615-dispcc"; 4610 reg = <0 0x0af00000 0 0x20000>; 4611 4612 clocks = <&rpmhcc RPMH_CXO_CLK>, 4613 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4614 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4615 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 4616 <0>, 4617 <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, 4618 <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; 4619 4620 #clock-cells = <1>; 4621 #reset-cells = <1>; 4622 #power-domain-cells = <1>; 4623 }; 4624 4625 pdc: interrupt-controller@b220000 { 4626 compatible = "qcom,qcs615-pdc", "qcom,pdc"; 4627 reg = <0x0 0x0b220000 0x0 0x30000>, 4628 <0x0 0x17c000f0 0x0 0x64>; 4629 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 4630 interrupt-parent = <&intc>; 4631 #interrupt-cells = <2>; 4632 interrupt-controller; 4633 }; 4634 4635 aoss_qmp: power-management@c300000 { 4636 compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp"; 4637 reg = <0x0 0x0c300000 0x0 0x400>; 4638 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING 0>; 4639 mboxes = <&apss_shared 0>; 4640 4641 #clock-cells = <0>; 4642 }; 4643 4644 sram@c3f0000 { 4645 compatible = "qcom,rpmh-stats"; 4646 reg = <0x0 0x0c3f0000 0x0 0x400>; 4647 }; 4648 4649 sram@14680000 { 4650 compatible = "qcom,qcs615-imem", "syscon", "simple-mfd"; 4651 reg = <0x0 0x14680000 0x0 0x2c000>; 4652 ranges = <0 0 0x14680000 0x2c000>; 4653 4654 #address-cells = <1>; 4655 #size-cells = <1>; 4656 4657 pil-reloc@2a94c { 4658 compatible = "qcom,pil-reloc-info"; 4659 reg = <0x2a94c 0xc8>; 4660 }; 4661 }; 4662 4663 apps_smmu: iommu@15000000 { 4664 compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4665 reg = <0x0 0x15000000 0x0 0x80000>; 4666 #iommu-cells = <2>; 4667 #global-interrupts = <1>; 4668 dma-coherent; 4669 4670 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, 4671 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>, 4672 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>, 4673 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>, 4674 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, 4675 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, 4676 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, 4677 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, 4678 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 4679 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, 4680 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 4681 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 4682 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, 4683 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, 4684 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 4685 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 4686 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 4687 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, 4688 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, 4689 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, 4690 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, 4691 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 4692 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, 4693 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, 4694 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, 4695 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, 4696 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, 4697 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, 4698 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, 4699 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, 4700 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, 4701 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, 4702 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, 4703 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, 4704 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, 4705 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, 4706 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, 4707 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, 4708 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, 4709 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, 4710 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, 4711 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, 4712 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, 4713 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, 4714 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, 4715 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, 4716 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, 4717 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, 4718 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, 4719 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, 4720 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, 4721 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, 4722 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, 4723 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, 4724 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, 4725 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, 4726 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, 4727 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, 4728 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, 4729 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, 4730 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, 4731 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, 4732 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, 4733 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, 4734 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 4735 }; 4736 4737 spmi_bus: spmi@c440000 { 4738 compatible = "qcom,spmi-pmic-arb"; 4739 reg = <0x0 0x0c440000 0x0 0x1100>, 4740 <0x0 0x0c600000 0x0 0x2000000>, 4741 <0x0 0x0e600000 0x0 0x100000>, 4742 <0x0 0x0e700000 0x0 0xa0000>, 4743 <0x0 0x0c40a000 0x0 0x26000>; 4744 reg-names = "core", 4745 "chnls", 4746 "obsrvr", 4747 "intr", 4748 "cnfg"; 4749 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4750 interrupt-names = "periph_irq"; 4751 interrupt-controller; 4752 #interrupt-cells = <4>; 4753 #address-cells = <2>; 4754 #size-cells = <0>; 4755 qcom,channel = <0>; 4756 qcom,ee = <0>; 4757 }; 4758 4759 intc: interrupt-controller@17a00000 { 4760 compatible = "arm,gic-v3"; 4761 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4762 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4763 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 4764 #address-cells = <0>; 4765 #interrupt-cells = <4>; 4766 interrupt-controller; 4767 #redistributor-regions = <1>; 4768 redistributor-stride = <0x0 0x20000>; 4769 4770 ppi-partitions { 4771 ppi_cluster0: interrupt-partition-0 { 4772 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 4773 }; 4774 4775 ppi_cluster1: interrupt-partition-1 { 4776 affinity = <&cpu6 &cpu7>; 4777 }; 4778 }; 4779 }; 4780 4781 apss_shared: mailbox@17c00000 { 4782 compatible = "qcom,qcs615-apss-shared", 4783 "qcom,sdm845-apss-shared"; 4784 reg = <0x0 0x17c00000 0x0 0x1000>; 4785 #mbox-cells = <1>; 4786 }; 4787 4788 watchdog: watchdog@17c10000 { 4789 compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt"; 4790 reg = <0x0 0x17c10000 0x0 0x1000>; 4791 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>; 4792 clocks = <&sleep_clk>; 4793 }; 4794 4795 timer@17c20000 { 4796 compatible = "arm,armv7-timer-mem"; 4797 reg = <0x0 0x17c20000 0x0 0x1000>; 4798 ranges = <0 0 0 0x20000000>; 4799 #address-cells = <1>; 4800 #size-cells = <1>; 4801 4802 frame@17c21000 { 4803 reg = <0x17c21000 0x1000>, 4804 <0x17c22000 0x1000>; 4805 frame-number = <0>; 4806 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, 4807 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 4808 }; 4809 4810 frame@17c23000 { 4811 reg = <0x17c23000 0x1000>; 4812 frame-number = <1>; 4813 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 4814 status = "disabled"; 4815 }; 4816 4817 frame@17c25000 { 4818 reg = <0x17c25000 0x1000>; 4819 frame-number = <2>; 4820 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 4821 status = "disabled"; 4822 }; 4823 4824 frame@17c27000 { 4825 reg = <0x17c27000 0x1000>; 4826 frame-number = <3>; 4827 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 4828 status = "disabled"; 4829 }; 4830 4831 frame@17c29000 { 4832 reg = <0x17c29000 0x1000>; 4833 frame-number = <4>; 4834 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 4835 status = "disabled"; 4836 }; 4837 4838 frame@17c2b000 { 4839 reg = <0x17c2b000 0x1000>; 4840 frame-number = <5>; 4841 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; 4842 status = "disabled"; 4843 }; 4844 4845 frame@17c2d000 { 4846 reg = <0x17c2d000 0x1000>; 4847 frame-number = <6>; 4848 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 4849 status = "disabled"; 4850 }; 4851 }; 4852 4853 apps_rsc: rsc@18200000 { 4854 compatible = "qcom,rpmh-rsc"; 4855 reg = <0x0 0x18200000 0x0 0x10000>, 4856 <0x0 0x18210000 0x0 0x10000>, 4857 <0x0 0x18220000 0x0 0x10000>; 4858 reg-names = "drv-0", 4859 "drv-1", 4860 "drv-2"; 4861 4862 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, 4863 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, 4864 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; 4865 4866 qcom,drv-id = <2>; 4867 qcom,tcs-offset = <0xd00>; 4868 qcom,tcs-config = <ACTIVE_TCS 2>, 4869 <SLEEP_TCS 3>, 4870 <WAKE_TCS 3>, 4871 <CONTROL_TCS 1>; 4872 4873 label = "apps_rsc"; 4874 power-domains = <&cluster_pd>; 4875 4876 apps_bcm_voter: bcm-voter { 4877 compatible = "qcom,bcm-voter"; 4878 }; 4879 4880 rpmhcc: clock-controller { 4881 compatible = "qcom,qcs615-rpmh-clk"; 4882 clocks = <&xo_board_clk>; 4883 clock-names = "xo"; 4884 4885 #clock-cells = <1>; 4886 }; 4887 4888 rpmhpd: power-controller { 4889 compatible = "qcom,qcs615-rpmhpd"; 4890 #power-domain-cells = <1>; 4891 operating-points-v2 = <&rpmhpd_opp_table>; 4892 4893 rpmhpd_opp_table: opp-table { 4894 compatible = "operating-points-v2"; 4895 4896 rpmhpd_opp_ret: opp-0 { 4897 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4898 }; 4899 4900 rpmhpd_opp_min_svs: opp-1 { 4901 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4902 }; 4903 4904 rpmhpd_opp_low_svs: opp-2 { 4905 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4906 }; 4907 4908 rpmhpd_opp_svs: opp-3 { 4909 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4910 }; 4911 4912 rpmhpd_opp_svs_l1: opp-4 { 4913 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4914 }; 4915 4916 rpmhpd_opp_nom: opp-5 { 4917 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4918 }; 4919 4920 rpmhpd_opp_nom_l1: opp-6 { 4921 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4922 }; 4923 4924 rpmhpd_opp_nom_l2: opp-7 { 4925 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4926 }; 4927 4928 rpmhpd_opp_turbo: opp-8 { 4929 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4930 }; 4931 4932 rpmhpd_opp_turbo_l1: opp-9 { 4933 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4934 }; 4935 }; 4936 }; 4937 }; 4938 4939 osm_l3: interconnect@18321000 { 4940 compatible = "qcom,qcs615-osm-l3", "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4941 reg = <0x0 0x18321000 0x0 0x1400>; 4942 4943 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4944 clock-names = "xo", "alternate"; 4945 4946 #interconnect-cells = <1>; 4947 }; 4948 4949 usb_1_hsphy: phy@88e2000 { 4950 compatible = "qcom,qcs615-qusb2-phy"; 4951 reg = <0x0 0x88e2000 0x0 0x180>; 4952 4953 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>; 4954 clock-names = "cfg_ahb", "ref"; 4955 4956 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4957 nvmem-cells = <&qusb2_hstx_trim>; 4958 4959 #phy-cells = <0>; 4960 4961 status = "disabled"; 4962 }; 4963 4964 usb_2_hsphy: phy@88e3000 { 4965 compatible = "qcom,qcs615-qusb2-phy"; 4966 reg = <0x0 0x088e3000 0x0 0x180>; 4967 4968 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, 4969 <&rpmhcc RPMH_CXO_CLK>; 4970 clock-names = "cfg_ahb", 4971 "ref"; 4972 4973 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 4974 4975 #phy-cells = <0>; 4976 4977 status = "disabled"; 4978 }; 4979 4980 usb_qmpphy: phy@88e6000 { 4981 compatible = "qcom,qcs615-qmp-usb3-phy"; 4982 reg = <0x0 0x88e6000 0x0 0x1000>; 4983 4984 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4985 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 4986 <&gcc GCC_AHB2PHY_WEST_CLK>, 4987 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4988 clock-names = "aux", 4989 "ref", 4990 "cfg_ahb", 4991 "pipe"; 4992 4993 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 4994 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 4995 reset-names = "phy", "phy_phy"; 4996 4997 qcom,tcsr-reg = <&tcsr 0xb244>; 4998 4999 clock-output-names = "usb3_phy_pipe_clk_src"; 5000 #clock-cells = <0>; 5001 5002 #phy-cells = <0>; 5003 5004 status = "disabled"; 5005 }; 5006 5007 usb_qmpphy_2: phy@88e8000 { 5008 compatible = "qcom,qcs615-qmp-usb3-dp-phy"; 5009 reg = <0x0 0x088e8000 0x0 0x2000>; 5010 5011 clocks = <&gcc GCC_USB2_SEC_PHY_AUX_CLK>, 5012 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 5013 <&gcc GCC_AHB2PHY_WEST_CLK>, 5014 <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>; 5015 clock-names = "aux", 5016 "ref", 5017 "cfg_ahb", 5018 "pipe"; 5019 5020 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >, 5021 <&gcc GCC_USB3_DP_PHY_SEC_BCR>; 5022 reset-names = "phy_phy", 5023 "dp_phy"; 5024 5025 #clock-cells = <1>; 5026 #phy-cells = <1>; 5027 5028 qcom,tcsr-reg = <&tcsr 0xbff0 0xb24c>; 5029 5030 status = "disabled"; 5031 }; 5032 5033 usb_1: usb@a600000 { 5034 compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; 5035 reg = <0x0 0x0a600000 0x0 0xfc100>; 5036 5037 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5038 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5039 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5040 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5041 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5042 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 5043 clock-names = "cfg_noc", 5044 "core", 5045 "iface", 5046 "sleep", 5047 "mock_utmi", 5048 "xo"; 5049 5050 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5051 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5052 assigned-clock-rates = <19200000>, <200000000>; 5053 5054 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, 5055 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, 5056 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, 5057 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 5058 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 5059 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 5060 interrupt-names = "dwc_usb3", 5061 "pwr_event", 5062 "hs_phy_irq", 5063 "dp_hs_phy_irq", 5064 "dm_hs_phy_irq", 5065 "ss_phy_irq"; 5066 5067 iommus = <&apps_smmu 0x140 0x0>; 5068 5069 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 5070 phy-names = "usb2-phy", "usb3-phy"; 5071 5072 power-domains = <&gcc USB30_PRIM_GDSC>; 5073 required-opps = <&rpmhpd_opp_nom>; 5074 5075 resets = <&gcc GCC_USB30_PRIM_BCR>; 5076 5077 snps,dis-u1-entry-quirk; 5078 snps,dis-u2-entry-quirk; 5079 snps,dis_u2_susphy_quirk; 5080 snps,dis_u3_susphy_quirk; 5081 snps,dis_enblslpm_quirk; 5082 snps,has-lpm-erratum; 5083 snps,hird-threshold = /bits/ 8 <0x10>; 5084 snps,usb3_lpm_capable; 5085 5086 wakeup-source; 5087 5088 status = "disabled"; 5089 }; 5090 5091 usb_2: usb@a800000 { 5092 compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; 5093 reg = <0x0 0x0a800000 0x0 0xfc100>; 5094 5095 clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, 5096 <&gcc GCC_USB20_SEC_MASTER_CLK>, 5097 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, 5098 <&gcc GCC_USB20_SEC_SLEEP_CLK>, 5099 <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 5100 <&gcc GCC_USB2_PRIM_CLKREF_CLK>; 5101 clock-names = "cfg_noc", 5102 "core", 5103 "iface", 5104 "sleep", 5105 "mock_utmi", 5106 "xo"; 5107 5108 assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 5109 <&gcc GCC_USB20_SEC_MASTER_CLK>; 5110 assigned-clock-rates = <19200000>, <200000000>; 5111 5112 interrupts-extended = <&intc GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, 5113 <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, 5114 <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>, 5115 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 5116 <&pdc 10 IRQ_TYPE_EDGE_BOTH>; 5117 interrupt-names = "dwc_usb3", 5118 "pwr_event", 5119 "hs_phy_irq", 5120 "dp_hs_phy_irq", 5121 "dm_hs_phy_irq"; 5122 5123 iommus = <&apps_smmu 0xe0 0x0>; 5124 5125 phys = <&usb_2_hsphy>; 5126 phy-names = "usb2-phy"; 5127 5128 power-domains = <&gcc USB20_SEC_GDSC>; 5129 required-opps = <&rpmhpd_opp_nom>; 5130 5131 resets = <&gcc GCC_USB20_SEC_BCR>; 5132 5133 qcom,select-utmi-as-pipe-clk; 5134 5135 snps,dis_u2_susphy_quirk; 5136 snps,dis_u3_susphy_quirk; 5137 snps,dis_enblslpm_quirk; 5138 snps,has-lpm-erratum; 5139 snps,hird-threshold = /bits/ 8 <0x10>; 5140 5141 maximum-speed = "high-speed"; 5142 wakeup-source; 5143 5144 status = "disabled"; 5145 }; 5146 5147 tsens0: thermal-sensor@c263000 { 5148 compatible = "qcom,qcs615-tsens", "qcom,tsens-v2"; 5149 reg = <0x0 0x0c263000 0x0 0x1000>, 5150 <0x0 0x0c222000 0x0 0x1000>; 5151 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>, 5152 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>; 5153 interrupt-names = "uplow", "critical"; 5154 #qcom,sensors = <16>; 5155 #thermal-sensor-cells = <1>; 5156 }; 5157 5158 remoteproc_adsp: remoteproc@62400000 { 5159 compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas"; 5160 reg = <0x0 0x62400000 0x0 0x4040>; 5161 5162 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING 0>, 5163 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 5164 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 5165 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 5166 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 5167 interrupt-names = "wdog", 5168 "fatal", 5169 "ready", 5170 "handover", 5171 "stop-ack"; 5172 5173 clocks = <&rpmhcc RPMH_CXO_CLK>; 5174 clock-names = "xo"; 5175 5176 power-domains = <&rpmhpd RPMHPD_CX>; 5177 power-domain-names = "cx"; 5178 5179 memory-region = <&rproc_adsp_mem>; 5180 5181 qcom,qmp = <&aoss_qmp>; 5182 5183 qcom,smem-states = <&adsp_smp2p_out 0>; 5184 qcom,smem-state-names = "stop"; 5185 5186 status = "disabled"; 5187 5188 glink_edge: glink-edge { 5189 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING 0>; 5190 mboxes = <&apss_shared 24>; 5191 label = "lpass"; 5192 qcom,remote-pid = <2>; 5193 5194 fastrpc { 5195 compatible = "qcom,fastrpc"; 5196 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5197 label = "adsp"; 5198 #address-cells = <1>; 5199 #size-cells = <0>; 5200 5201 compute-cb@3 { 5202 compatible = "qcom,fastrpc-compute-cb"; 5203 reg = <3>; 5204 iommus = <&apps_smmu 0x1723 0x0>; 5205 dma-coherent; 5206 }; 5207 5208 compute-cb@4 { 5209 compatible = "qcom,fastrpc-compute-cb"; 5210 reg = <4>; 5211 iommus = <&apps_smmu 0x1724 0x0>; 5212 dma-coherent; 5213 }; 5214 5215 compute-cb@5 { 5216 compatible = "qcom,fastrpc-compute-cb"; 5217 reg = <5>; 5218 iommus = <&apps_smmu 0x1725 0x0>; 5219 dma-coherent; 5220 }; 5221 5222 compute-cb@6 { 5223 compatible = "qcom,fastrpc-compute-cb"; 5224 reg = <6>; 5225 iommus = <&apps_smmu 0x1726 0x0>; 5226 qcom,nsessions = <5>; 5227 dma-coherent; 5228 }; 5229 }; 5230 5231 gpr: gpr { 5232 compatible = "qcom,gpr"; 5233 qcom,glink-channels = "adsp_apps"; 5234 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 5235 qcom,intents = <512 20>; 5236 #address-cells = <1>; 5237 #size-cells = <0>; 5238 5239 q6apm: service@1 { 5240 compatible = "qcom,q6apm"; 5241 reg = <GPR_APM_MODULE_IID>; 5242 #sound-dai-cells = <0>; 5243 qcom,protection-domain = "avs/audio", 5244 "msm/adsp/audio_pd"; 5245 5246 q6apmbedai: bedais { 5247 compatible = "qcom,q6apm-lpass-dais"; 5248 #sound-dai-cells = <1>; 5249 }; 5250 5251 q6apmdai: dais { 5252 compatible = "qcom,q6apm-dais"; 5253 iommus = <&apps_smmu 0x1721 0x0>; 5254 }; 5255 }; 5256 5257 q6prm: service@2 { 5258 compatible = "qcom,q6prm"; 5259 reg = <GPR_PRM_MODULE_IID>; 5260 qcom,protection-domain = "avs/audio", 5261 "msm/adsp/audio_pd"; 5262 5263 q6prmcc: clock-controller { 5264 compatible = "qcom,q6prm-lpass-clocks"; 5265 #clock-cells = <2>; 5266 }; 5267 }; 5268 }; 5269 }; 5270 }; 5271 5272 cpufreq_hw: cpufreq@18323000 { 5273 compatible = "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw"; 5274 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 5275 reg-names = "freq-domain0", "freq-domain1"; 5276 5277 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5278 clock-names = "xo", "alternate"; 5279 5280 #freq-domain-cells = <1>; 5281 #clock-cells = <1>; 5282 }; 5283 }; 5284 5285 arch_timer: timer { 5286 compatible = "arm,armv8-timer"; 5287 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW 0>, 5288 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>, 5289 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW 0>, 5290 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW 0>; 5291 }; 5292 5293 thermal-zones { 5294 aoss-thermal { 5295 thermal-sensors = <&tsens0 0>; 5296 5297 trips { 5298 aoss-critical { 5299 temperature = <115000>; 5300 hysteresis = <1000>; 5301 type = "critical"; 5302 }; 5303 }; 5304 }; 5305 5306 cpuss-0-thermal { 5307 thermal-sensors = <&tsens0 1>; 5308 5309 trips { 5310 cpuss0-critical { 5311 temperature = <115000>; 5312 hysteresis = <1000>; 5313 type = "critical"; 5314 }; 5315 }; 5316 }; 5317 5318 cpuss-1-thermal { 5319 thermal-sensors = <&tsens0 2>; 5320 5321 trips { 5322 cpuss1-critical { 5323 temperature = <115000>; 5324 hysteresis = <1000>; 5325 type = "critical"; 5326 }; 5327 }; 5328 }; 5329 5330 cpuss-2-thermal { 5331 thermal-sensors = <&tsens0 3>; 5332 5333 trips { 5334 cpuss2-critical { 5335 temperature = <115000>; 5336 hysteresis = <1000>; 5337 type = "critical"; 5338 }; 5339 }; 5340 }; 5341 5342 cpuss-3-thermal { 5343 thermal-sensors = <&tsens0 4>; 5344 5345 trips { 5346 cpuss3-critical { 5347 temperature = <115000>; 5348 hysteresis = <1000>; 5349 type = "critical"; 5350 }; 5351 }; 5352 }; 5353 5354 cpu-1-0-thermal { 5355 thermal-sensors = <&tsens0 5>; 5356 5357 trips { 5358 cpu-critical { 5359 temperature = <115000>; 5360 hysteresis = <1000>; 5361 type = "critical"; 5362 }; 5363 }; 5364 }; 5365 5366 cpu-1-1-thermal { 5367 thermal-sensors = <&tsens0 6>; 5368 5369 trips { 5370 cpu-critical { 5371 temperature = <115000>; 5372 hysteresis = <1000>; 5373 type = "critical"; 5374 }; 5375 }; 5376 }; 5377 5378 cpu-1-2-thermal { 5379 thermal-sensors = <&tsens0 7>; 5380 5381 trips { 5382 cpu-critical { 5383 temperature = <115000>; 5384 hysteresis = <1000>; 5385 type = "critical"; 5386 }; 5387 }; 5388 }; 5389 5390 cpu-1-3-thermal { 5391 thermal-sensors = <&tsens0 8>; 5392 5393 trips { 5394 cpu-critical { 5395 temperature = <115000>; 5396 hysteresis = <1000>; 5397 type = "critical"; 5398 }; 5399 }; 5400 }; 5401 5402 gpu-thermal { 5403 thermal-sensors = <&tsens0 9>; 5404 5405 trips { 5406 gpu_alert0: trip-point0 { 5407 temperature = <105000>; 5408 hysteresis = <5000>; 5409 type = "passive"; 5410 }; 5411 5412 gpu-critical { 5413 temperature = <115000>; 5414 hysteresis = <1000>; 5415 type = "critical"; 5416 }; 5417 }; 5418 5419 cooling-maps { 5420 map0 { 5421 trip = <&gpu_alert0>; 5422 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5423 }; 5424 }; 5425 }; 5426 5427 q6-hvx-thermal { 5428 thermal-sensors = <&tsens0 10>; 5429 5430 trips { 5431 q6-hvx-critical { 5432 temperature = <115000>; 5433 hysteresis = <1000>; 5434 type = "critical"; 5435 }; 5436 }; 5437 }; 5438 5439 mdm-core-thermal { 5440 thermal-sensors = <&tsens0 11>; 5441 5442 trips { 5443 mdm-core-critical { 5444 temperature = <115000>; 5445 hysteresis = <1000>; 5446 type = "critical"; 5447 }; 5448 }; 5449 }; 5450 5451 camera-thermal { 5452 thermal-sensors = <&tsens0 12>; 5453 5454 trips { 5455 camera-critical { 5456 temperature = <115000>; 5457 hysteresis = <1000>; 5458 type = "critical"; 5459 }; 5460 }; 5461 }; 5462 5463 wlan-thermal { 5464 thermal-sensors = <&tsens0 13>; 5465 5466 trips { 5467 wlan-critical { 5468 temperature = <115000>; 5469 hysteresis = <1000>; 5470 type = "critical"; 5471 }; 5472 }; 5473 }; 5474 5475 display-thermal { 5476 thermal-sensors = <&tsens0 14>; 5477 5478 trips { 5479 display-critical { 5480 temperature = <115000>; 5481 hysteresis = <1000>; 5482 type = "critical"; 5483 }; 5484 }; 5485 }; 5486 5487 video-thermal { 5488 thermal-sensors = <&tsens0 15>; 5489 5490 trips { 5491 video-critical { 5492 temperature = <115000>; 5493 hysteresis = <1000>; 5494 type = "critical"; 5495 }; 5496 }; 5497 }; 5498 }; 5499}; 5500