1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,qcs615-camcc.h> 8#include <dt-bindings/clock/qcom,qcs615-dispcc.h> 9#include <dt-bindings/clock/qcom,qcs615-gcc.h> 10#include <dt-bindings/clock/qcom,qcs615-gpucc.h> 11#include <dt-bindings/clock/qcom,qcs615-videocc.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,osm-l3.h> 17#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/power/qcom,rpmhpd.h> 22#include <dt-bindings/soc/qcom,gpr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/thermal/thermal.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 cpus { 32 #address-cells = <2>; 33 #size-cells = <0>; 34 35 cpu0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a55"; 38 reg = <0x0 0x0>; 39 enable-method = "psci"; 40 power-domains = <&cpu_pd0>; 41 power-domain-names = "psci"; 42 capacity-dmips-mhz = <1024>; 43 dynamic-power-coefficient = <100>; 44 next-level-cache = <&l2_0>; 45 clocks = <&cpufreq_hw 0>; 46 qcom,freq-domain = <&cpufreq_hw 0>; 47 #cooling-cells = <2>; 48 operating-points-v2 = <&cpu0_opp_table>; 49 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 50 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 51 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 52 53 l2_0: l2-cache { 54 compatible = "cache"; 55 cache-level = <2>; 56 cache-unified; 57 next-level-cache = <&l3_0>; 58 }; 59 }; 60 61 cpu1: cpu@100 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a55"; 64 reg = <0x0 0x100>; 65 enable-method = "psci"; 66 power-domains = <&cpu_pd1>; 67 power-domain-names = "psci"; 68 capacity-dmips-mhz = <1024>; 69 dynamic-power-coefficient = <100>; 70 next-level-cache = <&l2_100>; 71 clocks = <&cpufreq_hw 0>; 72 qcom,freq-domain = <&cpufreq_hw 0>; 73 operating-points-v2 = <&cpu0_opp_table>; 74 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 75 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 76 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 77 78 l2_100: l2-cache { 79 compatible = "cache"; 80 cache-level = <2>; 81 cache-unified; 82 next-level-cache = <&l3_0>; 83 }; 84 }; 85 86 cpu2: cpu@200 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a55"; 89 reg = <0x0 0x200>; 90 enable-method = "psci"; 91 power-domains = <&cpu_pd2>; 92 power-domain-names = "psci"; 93 capacity-dmips-mhz = <1024>; 94 dynamic-power-coefficient = <100>; 95 next-level-cache = <&l2_200>; 96 clocks = <&cpufreq_hw 0>; 97 qcom,freq-domain = <&cpufreq_hw 0>; 98 operating-points-v2 = <&cpu0_opp_table>; 99 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 100 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 101 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 102 103 l2_200: l2-cache { 104 compatible = "cache"; 105 cache-level = <2>; 106 cache-unified; 107 next-level-cache = <&l3_0>; 108 }; 109 }; 110 111 cpu3: cpu@300 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a55"; 114 reg = <0x0 0x300>; 115 enable-method = "psci"; 116 power-domains = <&cpu_pd3>; 117 power-domain-names = "psci"; 118 capacity-dmips-mhz = <1024>; 119 dynamic-power-coefficient = <100>; 120 next-level-cache = <&l2_300>; 121 clocks = <&cpufreq_hw 0>; 122 qcom,freq-domain = <&cpufreq_hw 0>; 123 operating-points-v2 = <&cpu0_opp_table>; 124 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 125 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 126 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 127 128 l2_300: l2-cache { 129 compatible = "cache"; 130 cache-level = <2>; 131 cache-unified; 132 next-level-cache = <&l3_0>; 133 }; 134 }; 135 136 cpu4: cpu@400 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a55"; 139 reg = <0x0 0x400>; 140 enable-method = "psci"; 141 power-domains = <&cpu_pd4>; 142 power-domain-names = "psci"; 143 capacity-dmips-mhz = <1024>; 144 dynamic-power-coefficient = <100>; 145 next-level-cache = <&l2_400>; 146 clocks = <&cpufreq_hw 0>; 147 qcom,freq-domain = <&cpufreq_hw 0>; 148 operating-points-v2 = <&cpu0_opp_table>; 149 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 150 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 151 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 152 153 l2_400: l2-cache { 154 compatible = "cache"; 155 cache-level = <2>; 156 cache-unified; 157 next-level-cache = <&l3_0>; 158 }; 159 }; 160 161 cpu5: cpu@500 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-a55"; 164 reg = <0x0 0x500>; 165 enable-method = "psci"; 166 power-domains = <&cpu_pd5>; 167 power-domain-names = "psci"; 168 capacity-dmips-mhz = <1024>; 169 dynamic-power-coefficient = <100>; 170 next-level-cache = <&l2_500>; 171 clocks = <&cpufreq_hw 0>; 172 qcom,freq-domain = <&cpufreq_hw 0>; 173 operating-points-v2 = <&cpu0_opp_table>; 174 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 176 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 177 178 l2_500: l2-cache { 179 compatible = "cache"; 180 cache-level = <2>; 181 cache-unified; 182 next-level-cache = <&l3_0>; 183 }; 184 }; 185 186 cpu6: cpu@600 { 187 device_type = "cpu"; 188 compatible = "arm,cortex-a76"; 189 reg = <0x0 0x600>; 190 enable-method = "psci"; 191 power-domains = <&cpu_pd6>; 192 power-domain-names = "psci"; 193 capacity-dmips-mhz = <1740>; 194 dynamic-power-coefficient = <404>; 195 next-level-cache = <&l2_600>; 196 clocks = <&cpufreq_hw 1>; 197 qcom,freq-domain = <&cpufreq_hw 1>; 198 #cooling-cells = <2>; 199 operating-points-v2 = <&cpu6_opp_table>; 200 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 201 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 202 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 203 204 l2_600: l2-cache { 205 compatible = "cache"; 206 cache-level = <2>; 207 cache-unified; 208 next-level-cache = <&l3_0>; 209 }; 210 }; 211 212 cpu7: cpu@700 { 213 device_type = "cpu"; 214 compatible = "arm,cortex-a76"; 215 reg = <0x0 0x700>; 216 enable-method = "psci"; 217 power-domains = <&cpu_pd7>; 218 power-domain-names = "psci"; 219 capacity-dmips-mhz = <1740>; 220 dynamic-power-coefficient = <404>; 221 next-level-cache = <&l2_700>; 222 clocks = <&cpufreq_hw 1>; 223 qcom,freq-domain = <&cpufreq_hw 1>; 224 operating-points-v2 = <&cpu6_opp_table>; 225 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 226 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 227 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 228 229 l2_700: l2-cache { 230 compatible = "cache"; 231 cache-level = <2>; 232 cache-unified; 233 next-level-cache = <&l3_0>; 234 }; 235 }; 236 237 cpu-map { 238 cluster0 { 239 core0 { 240 cpu = <&cpu0>; 241 }; 242 243 core1 { 244 cpu = <&cpu1>; 245 }; 246 247 core2 { 248 cpu = <&cpu2>; 249 }; 250 251 core3 { 252 cpu = <&cpu3>; 253 }; 254 255 core4 { 256 cpu = <&cpu4>; 257 }; 258 259 core5 { 260 cpu = <&cpu5>; 261 }; 262 263 core6 { 264 cpu = <&cpu6>; 265 }; 266 267 core7 { 268 cpu = <&cpu7>; 269 }; 270 }; 271 }; 272 273 l3_0: l3-cache { 274 compatible = "cache"; 275 cache-level = <3>; 276 cache-unified; 277 }; 278 }; 279 280 cpu0_opp_table: opp-table-cpu0 { 281 compatible = "operating-points-v2"; 282 opp-shared; 283 284 opp-300000000 { 285 opp-hz = /bits/ 64 <300000000>; 286 opp-peak-kBps = <(300000 * 4) (300000 * 16)>; 287 }; 288 289 opp-576000000 { 290 opp-hz = /bits/ 64 <576000000>; 291 opp-peak-kBps = <(300000 * 4) (576000 * 16)>; 292 }; 293 294 opp-748800000 { 295 opp-hz = /bits/ 64 <748800000>; 296 opp-peak-kBps = <(300000 * 4) (576000 * 16)>; 297 }; 298 299 opp-998400000 { 300 opp-hz = /bits/ 64 <998400000>; 301 opp-peak-kBps = <(451000 * 4) (806400 * 16)>; 302 }; 303 304 opp-1209600000 { 305 opp-hz = /bits/ 64 <1209600000>; 306 opp-peak-kBps = <(547000 * 4) (1017600 * 16)>; 307 }; 308 309 opp-1363200000 { 310 opp-hz = /bits/ 64 <1363200000>; 311 opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; 312 }; 313 314 opp-1516800000 { 315 opp-hz = /bits/ 64 <1516800000>; 316 opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; 317 }; 318 319 opp-1593600000 { 320 opp-hz = /bits/ 64 <1593600000>; 321 opp-peak-kBps = <(1017000 * 4) (1363200 * 16)>; 322 }; 323 }; 324 325 cpu6_opp_table: opp-table-cpu6 { 326 compatible = "operating-points-v2"; 327 opp-shared; 328 329 opp-300000000 { 330 opp-hz = /bits/ 64 <300000000>; 331 opp-peak-kBps = <(451000 * 4) (300000 * 16)>; 332 }; 333 334 opp-652800000 { 335 opp-hz = /bits/ 64 <652800000>; 336 opp-peak-kBps = <(451000 * 4) (576000 * 16)>; 337 }; 338 339 opp-768000000 { 340 opp-hz = /bits/ 64 <768000000>; 341 opp-peak-kBps = <(451000 * 4) (576000 * 16)>; 342 }; 343 344 opp-979200000 { 345 opp-hz = /bits/ 64 <979200000>; 346 opp-peak-kBps = <(547000 * 4) (806400 * 16)>; 347 }; 348 349 opp-1017600000 { 350 opp-hz = /bits/ 64 <1017600000>; 351 opp-peak-kBps = <(547000 * 4) (806400 * 16)>; 352 }; 353 354 opp-1094400000 { 355 opp-hz = /bits/ 64 <1094400000>; 356 opp-peak-kBps = <(1017600 * 4) (940800 * 16)>; 357 }; 358 359 opp-1209600000 { 360 opp-hz = /bits/ 64 <1209600000>; 361 opp-peak-kBps = <(1017600 * 4) (1017600 * 16)>; 362 }; 363 364 opp-1363200000 { 365 opp-hz = /bits/ 64 <1363200000>; 366 opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; 367 }; 368 369 opp-1516800000 { 370 opp-hz = /bits/ 64 <1516800000>; 371 opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; 372 }; 373 374 opp-1708800000 { 375 opp-hz = /bits/ 64 <1708800000>; 376 opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; 377 }; 378 379 opp-1900800000 { 380 opp-hz = /bits/ 64 <1900800000>; 381 opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; 382 }; 383 }; 384 385 dummy_eud: dummy-sink { 386 compatible = "arm,coresight-dummy-sink"; 387 388 in-ports { 389 port { 390 eud_in: endpoint { 391 remote-endpoint = <&replicator_swao_out1>; 392 }; 393 }; 394 }; 395 }; 396 397 idle-states { 398 entry-method = "psci"; 399 400 little_cpu_sleep_0: cpu-sleep-0-0 { 401 compatible = "arm,idle-state"; 402 idle-state-name = "silver-power-collapse"; 403 arm,psci-suspend-param = <0x40000003>; 404 entry-latency-us = <549>; 405 exit-latency-us = <901>; 406 min-residency-us = <1774>; 407 local-timer-stop; 408 }; 409 410 little_cpu_sleep_1: cpu-sleep-0-1 { 411 compatible = "arm,idle-state"; 412 idle-state-name = "silver-rail-power-collapse"; 413 arm,psci-suspend-param = <0x40000004>; 414 entry-latency-us = <702>; 415 exit-latency-us = <915>; 416 min-residency-us = <4001>; 417 local-timer-stop; 418 }; 419 420 big_cpu_sleep_0: cpu-sleep-1-0 { 421 compatible = "arm,idle-state"; 422 idle-state-name = "gold-power-collapse"; 423 arm,psci-suspend-param = <0x40000003>; 424 entry-latency-us = <523>; 425 exit-latency-us = <1244>; 426 min-residency-us = <2207>; 427 local-timer-stop; 428 }; 429 430 big_cpu_sleep_1: cpu-sleep-1-1 { 431 compatible = "arm,idle-state"; 432 idle-state-name = "gold-rail-power-collapse"; 433 arm,psci-suspend-param = <0x40000004>; 434 entry-latency-us = <526>; 435 exit-latency-us = <1854>; 436 min-residency-us = <5555>; 437 local-timer-stop; 438 }; 439 }; 440 441 domain-idle-states { 442 cluster_sleep_0: cluster-sleep-0 { 443 compatible = "domain-idle-state"; 444 arm,psci-suspend-param = <0x41000044>; 445 entry-latency-us = <2752>; 446 exit-latency-us = <3048>; 447 min-residency-us = <6118>; 448 }; 449 450 cluster_sleep_1: cluster-sleep-1 { 451 compatible = "domain-idle-state"; 452 arm,psci-suspend-param = <0x41001344>; 453 entry-latency-us = <3263>; 454 exit-latency-us = <4562>; 455 min-residency-us = <8467>; 456 }; 457 458 cluster_sleep_2: cluster-sleep-2 { 459 compatible = "domain-idle-state"; 460 arm,psci-suspend-param = <0x4100b344>; 461 entry-latency-us = <3638>; 462 exit-latency-us = <6562>; 463 min-residency-us = <9826>; 464 }; 465 }; 466 467 memory@80000000 { 468 device_type = "memory"; 469 /* We expect the bootloader to fill in the size */ 470 reg = <0 0x80000000 0 0>; 471 }; 472 473 firmware { 474 scm { 475 compatible = "qcom,scm-qcs615", "qcom,scm"; 476 qcom,dload-mode = <&tcsr 0x13000>; 477 sram = <&minidump_config>; 478 }; 479 }; 480 481 camnoc_virt: interconnect-0 { 482 compatible = "qcom,qcs615-camnoc-virt"; 483 #interconnect-cells = <2>; 484 qcom,bcm-voters = <&apps_bcm_voter>; 485 }; 486 487 mc_virt: interconnect-2 { 488 compatible = "qcom,qcs615-mc-virt"; 489 #interconnect-cells = <2>; 490 qcom,bcm-voters = <&apps_bcm_voter>; 491 }; 492 493 smp2p-adsp { 494 compatible = "qcom,smp2p"; 495 qcom,smem = <443>, <429>; 496 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING 0>; 497 /* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */ 498 mboxes = <&apss_shared 26>; 499 500 qcom,local-pid = <0>; 501 qcom,remote-pid = <2>; 502 503 adsp_smp2p_out: master-kernel { 504 qcom,entry-name = "master-kernel"; 505 #qcom,smem-state-cells = <1>; 506 }; 507 508 adsp_smp2p_in: slave-kernel { 509 qcom,entry-name = "slave-kernel"; 510 interrupt-controller; 511 #interrupt-cells = <2>; 512 }; 513 }; 514 515 smp2p-cdsp { 516 compatible = "qcom,smp2p"; 517 qcom,smem = <94>, <432>; 518 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING 0>; 519 mboxes = <&apss_shared 6>; 520 521 qcom,local-pid = <0>; 522 qcom,remote-pid = <5>; 523 524 cdsp_smp2p_out: master-kernel { 525 qcom,entry-name = "master-kernel"; 526 #qcom,smem-state-cells = <1>; 527 }; 528 529 cdsp_smp2p_in: slave-kernel { 530 qcom,entry-name = "slave-kernel"; 531 interrupt-controller; 532 #interrupt-cells = <2>; 533 }; 534 535 }; 536 537 qspi_opp_table: opp-table-qspi { 538 compatible = "operating-points-v2"; 539 540 opp-60000000 { 541 opp-hz = /bits/ 64 <60000000>; 542 required-opps = <&rpmhpd_opp_low_svs>; 543 }; 544 545 opp-133250000 { 546 opp-hz = /bits/ 64 <133250000>; 547 required-opps = <&rpmhpd_opp_svs>; 548 }; 549 550 opp-266500000 { 551 opp-hz = /bits/ 64 <266500000>; 552 required-opps = <&rpmhpd_opp_nom>; 553 }; 554 }; 555 556 qup_opp_table: opp-table-qup { 557 compatible = "operating-points-v2"; 558 559 opp-75000000 { 560 opp-hz = /bits/ 64 <75000000>; 561 required-opps = <&rpmhpd_opp_low_svs>; 562 }; 563 564 opp-100000000 { 565 opp-hz = /bits/ 64 <100000000>; 566 required-opps = <&rpmhpd_opp_svs>; 567 }; 568 569 opp-128000000 { 570 opp-hz = /bits/ 64 <128000000>; 571 required-opps = <&rpmhpd_opp_nom>; 572 }; 573 }; 574 575 pmu-a55 { 576 compatible = "arm,cortex-a55-pmu"; 577 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 578 }; 579 580 pmu-a76 { 581 compatible = "arm,cortex-a76-pmu"; 582 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 583 }; 584 585 psci { 586 compatible = "arm,psci-1.0"; 587 method = "smc"; 588 589 cpu_pd0: power-domain-cpu0 { 590 #power-domain-cells = <0>; 591 power-domains = <&cluster_pd>; 592 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 593 }; 594 595 cpu_pd1: power-domain-cpu1 { 596 #power-domain-cells = <0>; 597 power-domains = <&cluster_pd>; 598 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 599 }; 600 601 cpu_pd2: power-domain-cpu2 { 602 #power-domain-cells = <0>; 603 power-domains = <&cluster_pd>; 604 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 605 }; 606 607 cpu_pd3: power-domain-cpu3 { 608 #power-domain-cells = <0>; 609 power-domains = <&cluster_pd>; 610 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 611 }; 612 613 cpu_pd4: power-domain-cpu4 { 614 #power-domain-cells = <0>; 615 power-domains = <&cluster_pd>; 616 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 617 }; 618 619 cpu_pd5: power-domain-cpu5 { 620 #power-domain-cells = <0>; 621 power-domains = <&cluster_pd>; 622 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 623 }; 624 625 cpu_pd6: power-domain-cpu6 { 626 #power-domain-cells = <0>; 627 power-domains = <&cluster_pd>; 628 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 629 }; 630 631 cpu_pd7: power-domain-cpu7 { 632 #power-domain-cells = <0>; 633 power-domains = <&cluster_pd>; 634 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 635 }; 636 637 cluster_pd: power-domain-cluster { 638 #power-domain-cells = <0>; 639 domain-idle-states = <&cluster_sleep_0 640 &cluster_sleep_1 641 &cluster_sleep_2>; 642 }; 643 }; 644 645 reserved-memory { 646 #address-cells = <2>; 647 #size-cells = <2>; 648 ranges; 649 650 aop_cmd_db_mem: aop-cmd-db@85f20000 { 651 compatible = "qcom,cmd-db"; 652 reg = <0x0 0x85f20000 0x0 0x20000>; 653 no-map; 654 }; 655 656 smem_region: smem@86000000 { 657 compatible = "qcom,smem"; 658 reg = <0x0 0x86000000 0x0 0x200000>; 659 no-map; 660 hwlocks = <&tcsr_mutex 3>; 661 }; 662 663 pil_video_mem: pil-video@93400000 { 664 reg = <0x0 0x93400000 0x0 0x500000>; 665 no-map; 666 }; 667 668 rproc_cdsp_mem: rproc-cdsp@93b00000 { 669 reg = <0x0 0x93b00000 0x0 0x1e00000>; 670 no-map; 671 }; 672 673 rproc_adsp_mem: rproc-adsp@95900000 { 674 reg = <0x0 0x95900000 0x0 0x1e00000>; 675 no-map; 676 }; 677 678 pil_gpu_mem: pil-gpu@97715000 { 679 reg = <0x0 0x97715000 0x0 0x2000>; 680 no-map; 681 }; 682 683 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap { 684 compatible = "shared-dma-pool"; 685 alloc-ranges = <0x0 0x80000000 0x0 0x80000000>; 686 reusable; 687 alignment = <0x0 0x400000>; 688 size = <0x0 0x800000>; 689 }; 690 }; 691 692 soc: soc@0 { 693 compatible = "simple-bus"; 694 ranges = <0 0 0 0 0x10 0>; 695 dma-ranges = <0 0 0 0 0x10 0>; 696 #address-cells = <2>; 697 #size-cells = <2>; 698 699 gcc: clock-controller@100000 { 700 compatible = "qcom,qcs615-gcc"; 701 reg = <0 0x00100000 0 0x1f0000>; 702 clocks = <&rpmhcc RPMH_CXO_CLK>, 703 <&rpmhcc RPMH_CXO_CLK_A>, 704 <&sleep_clk>; 705 clock-names = "bi_tcxo", 706 "bi_tcxo_ao", 707 "sleep_clk"; 708 709 #clock-cells = <1>; 710 #reset-cells = <1>; 711 #power-domain-cells = <1>; 712 }; 713 714 qfprom: efuse@780000 { 715 compatible = "qcom,qcs615-qfprom", "qcom,qfprom"; 716 reg = <0x0 0x00780000 0x0 0x7000>; 717 #address-cells = <1>; 718 #size-cells = <1>; 719 720 qusb2_hstx_trim: hstx-trim@1f8 { 721 reg = <0x1fb 0x1>; 722 bits = <1 4>; 723 }; 724 }; 725 726 rng@793000 { 727 compatible = "qcom,qcs615-trng", "qcom,trng"; 728 reg = <0x0 0x00793000 0x0 0x1000>; 729 }; 730 731 sdhc_1: mmc@7c4000 { 732 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 733 reg = <0x0 0x007c4000 0x0 0x1000>, 734 <0x0 0x007c5000 0x0 0x1000>, 735 <0x0 0x007c8000 0x0 0x8000>; 736 reg-names = "hc", 737 "cqhci", 738 "ice"; 739 740 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>, 741 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 742 interrupt-names = "hc_irq", 743 "pwr_irq"; 744 745 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 746 <&gcc GCC_SDCC1_APPS_CLK>, 747 <&rpmhcc RPMH_CXO_CLK>, 748 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 749 clock-names = "iface", 750 "core", 751 "xo", 752 "ice"; 753 754 resets = <&gcc GCC_SDCC1_BCR>; 755 756 power-domains = <&rpmhpd RPMHPD_CX>; 757 operating-points-v2 = <&sdhc1_opp_table>; 758 iommus = <&apps_smmu 0x02c0 0x0>; 759 interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS 760 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 761 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 762 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 763 interconnect-names = "sdhc-ddr", 764 "cpu-sdhc"; 765 766 qcom,dll-config = <0x000f642c>; 767 qcom,ddr-config = <0x80040868>; 768 supports-cqe; 769 dma-coherent; 770 771 status = "disabled"; 772 773 sdhc1_opp_table: opp-table { 774 compatible = "operating-points-v2"; 775 776 opp-50000000 { 777 opp-hz = /bits/ 64 <50000000>; 778 required-opps = <&rpmhpd_opp_low_svs>; 779 }; 780 781 opp-100000000 { 782 opp-hz = /bits/ 64 <100000000>; 783 required-opps = <&rpmhpd_opp_svs>; 784 }; 785 786 opp-200000000 { 787 opp-hz = /bits/ 64 <200000000>; 788 required-opps = <&rpmhpd_opp_svs_l1>; 789 }; 790 791 opp-384000000 { 792 opp-hz = /bits/ 64 <384000000>; 793 required-opps = <&rpmhpd_opp_nom>; 794 }; 795 }; 796 }; 797 798 gpi_dma0: dma-controller@800000 { 799 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 800 reg = <0x0 0x800000 0x0 0x60000>; 801 #dma-cells = <3>; 802 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>, 803 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, 804 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, 805 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, 806 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, 807 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>, 808 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, 809 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 810 dma-channels = <8>; 811 dma-channel-mask = <0xf>; 812 iommus = <&apps_smmu 0xd6 0x0>; 813 status = "disabled"; 814 }; 815 816 qupv3_id_0: geniqup@8c0000 { 817 compatible = "qcom,geni-se-qup"; 818 reg = <0x0 0x008c0000 0x0 0x6000>; 819 ranges; 820 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 821 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 822 clock-names = "m-ahb", 823 "s-ahb"; 824 iommus = <&apps_smmu 0xc3 0x0>; 825 #address-cells = <2>; 826 #size-cells = <2>; 827 status = "disabled"; 828 829 uart0: serial@880000 { 830 compatible = "qcom,geni-debug-uart"; 831 reg = <0x0 0x00880000 0x0 0x4000>; 832 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 833 clock-names = "se"; 834 pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>; 835 pinctrl-names = "default"; 836 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH 0>; 837 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 838 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 839 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 840 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 841 interconnect-names = "qup-core", 842 "qup-config"; 843 power-domains = <&rpmhpd RPMHPD_CX>; 844 operating-points-v2 = <&qup_opp_table>; 845 status = "disabled"; 846 }; 847 848 i2c1: i2c@884000 { 849 compatible = "qcom,geni-i2c"; 850 reg = <0x0 0x884000 0x0 0x4000>; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH 0>; 854 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 855 clock-names = "se"; 856 pinctrl-0 = <&qup_i2c1_data_clk>; 857 pinctrl-names = "default"; 858 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 859 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 860 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 861 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 862 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 863 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 864 interconnect-names = "qup-core", 865 "qup-config", 866 "qup-memory"; 867 power-domains = <&rpmhpd RPMHPD_CX>; 868 required-opps = <&rpmhpd_opp_low_svs>; 869 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 870 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 871 dma-names = "tx", 872 "rx"; 873 status = "disabled"; 874 }; 875 876 i2c2: i2c@888000 { 877 compatible = "qcom,geni-i2c"; 878 reg = <0x0 0x888000 0x0 0x4000>; 879 #address-cells = <1>; 880 #size-cells = <0>; 881 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>; 882 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 883 clock-names = "se"; 884 pinctrl-0 = <&qup_i2c2_data_clk>; 885 pinctrl-names = "default"; 886 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 887 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 888 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 889 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 890 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 891 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 892 interconnect-names = "qup-core", 893 "qup-config", 894 "qup-memory"; 895 power-domains = <&rpmhpd RPMHPD_CX>; 896 required-opps = <&rpmhpd_opp_low_svs>; 897 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 898 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 899 dma-names = "tx", 900 "rx"; 901 status = "disabled"; 902 }; 903 904 spi2: spi@888000 { 905 compatible = "qcom,geni-spi"; 906 reg = <0x0 0x00888000 0x0 0x4000>; 907 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>; 908 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 909 clock-names = "se"; 910 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 911 pinctrl-names = "default"; 912 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 913 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 914 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 915 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 916 interconnect-names = "qup-core", 917 "qup-config"; 918 power-domains = <&rpmhpd RPMHPD_CX>; 919 operating-points-v2 = <&qup_opp_table>; 920 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 921 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 922 dma-names = "tx", 923 "rx"; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 status = "disabled"; 927 }; 928 929 uart2: serial@888000 { 930 compatible = "qcom,geni-uart"; 931 reg = <0x0 0x00888000 0x0 0x4000>; 932 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH 0>; 933 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 934 clock-names = "se"; 935 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 936 <&qup_uart2_tx>, <&qup_uart2_rx>; 937 pinctrl-names = "default"; 938 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 939 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 940 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 941 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 942 interconnect-names = "qup-core", 943 "qup-config"; 944 power-domains = <&rpmhpd RPMHPD_CX>; 945 operating-points-v2 = <&qup_opp_table>; 946 status = "disabled"; 947 }; 948 949 i2c3: i2c@88c000 { 950 compatible = "qcom,geni-i2c"; 951 reg = <0x0 0x88c000 0x0 0x4000>; 952 #address-cells = <1>; 953 #size-cells = <0>; 954 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>; 955 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 956 clock-names = "se"; 957 pinctrl-0 = <&qup_i2c3_data_clk>; 958 pinctrl-names = "default"; 959 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 960 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 961 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 962 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 963 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 964 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 965 interconnect-names = "qup-core", 966 "qup-config", 967 "qup-memory"; 968 power-domains = <&rpmhpd RPMHPD_CX>; 969 required-opps = <&rpmhpd_opp_low_svs>; 970 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 971 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 972 dma-names = "tx", 973 "rx"; 974 status = "disabled"; 975 }; 976 }; 977 978 gpi_dma1: dma-controller@a00000 { 979 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 980 reg = <0x0 0xa00000 0x0 0x60000>; 981 #dma-cells = <3>; 982 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>, 983 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>, 984 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>, 985 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>, 986 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>, 987 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>, 988 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>, 989 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 990 dma-channels = <8>; 991 dma-channel-mask = <0xf>; 992 iommus = <&apps_smmu 0x376 0x0>; 993 status = "disabled"; 994 }; 995 996 qupv3_id_1: geniqup@ac0000 { 997 compatible = "qcom,geni-se-qup"; 998 reg = <0x0 0xac0000 0x0 0x2000>; 999 ranges; 1000 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1001 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1002 clock-names = "m-ahb", 1003 "s-ahb"; 1004 iommus = <&apps_smmu 0x363 0x0>; 1005 #address-cells = <2>; 1006 #size-cells = <2>; 1007 status = "disabled"; 1008 1009 i2c4: i2c@a80000 { 1010 compatible = "qcom,geni-i2c"; 1011 reg = <0x0 0xa80000 0x0 0x4000>; 1012 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1013 clock-names = "se"; 1014 pinctrl-0 = <&qup_i2c4_data_clk>; 1015 pinctrl-names = "default"; 1016 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1020 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1021 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1022 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1023 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1024 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1025 interconnect-names = "qup-core", 1026 "qup-config", 1027 "qup-memory"; 1028 power-domains = <&rpmhpd RPMHPD_CX>; 1029 required-opps = <&rpmhpd_opp_low_svs>; 1030 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1031 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1032 dma-names = "tx", 1033 "rx"; 1034 status = "disabled"; 1035 }; 1036 1037 spi4: spi@a80000 { 1038 compatible = "qcom,geni-spi"; 1039 reg = <0x0 0xa80000 0x0 0x4000>; 1040 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1041 clock-names = "se"; 1042 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1043 pinctrl-names = "default"; 1044 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1048 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1049 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1050 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1051 interconnect-names = "qup-core", 1052 "qup-config"; 1053 power-domains = <&rpmhpd RPMHPD_CX>; 1054 operating-points-v2 = <&qup_opp_table>; 1055 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1056 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1057 dma-names = "tx", 1058 "rx"; 1059 status = "disabled"; 1060 }; 1061 1062 uart4: serial@a80000 { 1063 compatible = "qcom,geni-uart"; 1064 reg = <0x0 0xa80000 0x0 0x4000>; 1065 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1066 clock-names = "se"; 1067 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 1068 <&qup_uart4_tx>, <&qup_uart4_rx>; 1069 pinctrl-names = "default"; 1070 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1071 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1072 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1073 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1074 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1075 interconnect-names = "qup-core", 1076 "qup-config"; 1077 power-domains = <&rpmhpd RPMHPD_CX>; 1078 operating-points-v2 = <&qup_opp_table>; 1079 status = "disabled"; 1080 }; 1081 1082 i2c5: i2c@a84000 { 1083 compatible = "qcom,geni-i2c"; 1084 reg = <0x0 0xa84000 0x0 0x4000>; 1085 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1086 clock-names = "se"; 1087 pinctrl-0 = <&qup_i2c5_data_clk>; 1088 pinctrl-names = "default"; 1089 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1093 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1094 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1095 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1096 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1097 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1098 interconnect-names = "qup-core", 1099 "qup-config", 1100 "qup-memory"; 1101 power-domains = <&rpmhpd RPMHPD_CX>; 1102 required-opps = <&rpmhpd_opp_low_svs>; 1103 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1104 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1105 dma-names = "tx", 1106 "rx"; 1107 status = "disabled"; 1108 }; 1109 1110 i2c6: i2c@a88000 { 1111 compatible = "qcom,geni-i2c"; 1112 reg = <0x0 0xa88000 0x0 0x4000>; 1113 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1114 clock-names = "se"; 1115 pinctrl-0 = <&qup_i2c6_data_clk>; 1116 pinctrl-names = "default"; 1117 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1121 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1122 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1123 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1124 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1125 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1126 interconnect-names = "qup-core", 1127 "qup-config", 1128 "qup-memory"; 1129 power-domains = <&rpmhpd RPMHPD_CX>; 1130 required-opps = <&rpmhpd_opp_low_svs>; 1131 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1132 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1133 dma-names = "tx", 1134 "rx"; 1135 status = "disabled"; 1136 }; 1137 1138 spi6: spi@a88000 { 1139 compatible = "qcom,geni-spi"; 1140 reg = <0x0 0xa88000 0x0 0x4000>; 1141 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1142 clock-names = "se"; 1143 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1144 pinctrl-names = "default"; 1145 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1149 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1150 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1151 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1152 interconnect-names = "qup-core", 1153 "qup-config"; 1154 power-domains = <&rpmhpd RPMHPD_CX>; 1155 operating-points-v2 = <&qup_opp_table>; 1156 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1157 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1158 dma-names = "tx", 1159 "rx"; 1160 status = "disabled"; 1161 }; 1162 1163 uart6: serial@a88000 { 1164 compatible = "qcom,geni-uart"; 1165 reg = <0x0 0xa88000 0x0 0x4000>; 1166 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1167 clock-names = "se"; 1168 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 1169 <&qup_uart6_tx>, <&qup_uart6_rx>; 1170 pinctrl-names = "default"; 1171 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1172 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1173 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1174 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1175 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1176 interconnect-names = "qup-core", 1177 "qup-config"; 1178 power-domains = <&rpmhpd RPMHPD_CX>; 1179 operating-points-v2 = <&qup_opp_table>; 1180 status = "disabled"; 1181 }; 1182 1183 i2c7: i2c@a8c000 { 1184 compatible = "qcom,geni-i2c"; 1185 reg = <0x0 0xa8c000 0x0 0x4000>; 1186 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1187 clock-names = "se"; 1188 pinctrl-0 = <&qup_i2c7_data_clk>; 1189 pinctrl-names = "default"; 1190 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1194 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1195 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1196 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1197 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1198 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1199 interconnect-names = "qup-core", 1200 "qup-config", 1201 "qup-memory"; 1202 power-domains = <&rpmhpd RPMHPD_CX>; 1203 required-opps = <&rpmhpd_opp_low_svs>; 1204 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1205 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1206 dma-names = "tx", 1207 "rx"; 1208 status = "disabled"; 1209 }; 1210 1211 spi7: spi@a8c000 { 1212 compatible = "qcom,geni-spi"; 1213 reg = <0x0 0xa8c000 0x0 0x4000>; 1214 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1215 clock-names = "se"; 1216 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1217 pinctrl-names = "default"; 1218 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1222 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1223 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1224 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1225 interconnect-names = "qup-core", 1226 "qup-config"; 1227 power-domains = <&rpmhpd RPMHPD_CX>; 1228 operating-points-v2 = <&qup_opp_table>; 1229 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1230 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1231 dma-names = "tx", 1232 "rx"; 1233 status = "disabled"; 1234 }; 1235 1236 uart7: serial@a8c000 { 1237 compatible = "qcom,geni-uart"; 1238 reg = <0x0 0xa8c000 0x0 0x4000>; 1239 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1240 clock-names = "se"; 1241 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, 1242 <&qup_uart7_tx>, <&qup_uart7_rx>; 1243 pinctrl-names = "default"; 1244 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1245 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1246 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1247 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1248 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1249 interconnect-names = "qup-core", 1250 "qup-config"; 1251 power-domains = <&rpmhpd RPMHPD_CX>; 1252 operating-points-v2 = <&qup_opp_table>; 1253 status = "disabled"; 1254 }; 1255 }; 1256 1257 config_noc: interconnect@1500000 { 1258 reg = <0x0 0x01500000 0x0 0x5080>; 1259 compatible = "qcom,qcs615-config-noc"; 1260 #interconnect-cells = <2>; 1261 qcom,bcm-voters = <&apps_bcm_voter>; 1262 }; 1263 1264 system_noc: interconnect@1620000 { 1265 reg = <0x0 0x01620000 0x0 0x1f300>; 1266 compatible = "qcom,qcs615-system-noc"; 1267 #interconnect-cells = <2>; 1268 qcom,bcm-voters = <&apps_bcm_voter>; 1269 }; 1270 1271 aggre1_noc: interconnect@1700000 { 1272 reg = <0x0 0x01700000 0x0 0x3f200>; 1273 compatible = "qcom,qcs615-aggre1-noc"; 1274 #interconnect-cells = <2>; 1275 qcom,bcm-voters = <&apps_bcm_voter>; 1276 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1277 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, 1278 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1279 <&rpmhcc RPMH_IPA_CLK>; 1280 }; 1281 1282 mmss_noc: interconnect@1740000 { 1283 reg = <0x0 0x01740000 0x0 0x1c100>; 1284 compatible = "qcom,qcs615-mmss-noc"; 1285 #interconnect-cells = <2>; 1286 qcom,bcm-voters = <&apps_bcm_voter>; 1287 }; 1288 1289 pcie: pcie@1c08000 { 1290 device_type = "pci"; 1291 compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150"; 1292 reg = <0x0 0x01c08000 0x0 0x3000>, 1293 <0x0 0x40000000 0x0 0xf1d>, 1294 <0x0 0x40000f20 0x0 0xa8>, 1295 <0x0 0x40001000 0x0 0x1000>, 1296 <0x0 0x40100000 0x0 0x100000>, 1297 <0x0 0x01c0b000 0x0 0x1000>; 1298 reg-names = "parf", 1299 "dbi", 1300 "elbi", 1301 "atu", 1302 "config", 1303 "mhi"; 1304 #address-cells = <3>; 1305 #size-cells = <2>; 1306 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1307 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1308 bus-range = <0x00 0xff>; 1309 1310 dma-coherent; 1311 1312 linux,pci-domain = <0>; 1313 num-lanes = <1>; 1314 1315 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>, 1316 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>, 1317 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>, 1318 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>, 1319 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>, 1320 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>, 1321 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>, 1322 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>, 1323 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>; 1324 interrupt-names = "msi0", 1325 "msi1", 1326 "msi2", 1327 "msi3", 1328 "msi4", 1329 "msi5", 1330 "msi6", 1331 "msi7", 1332 "global"; 1333 1334 #interrupt-cells = <1>; 1335 interrupt-map-mask = <0 0 0 0x7>; 1336 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, 1337 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, 1338 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, 1339 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1340 1341 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1342 <&gcc GCC_PCIE_0_AUX_CLK>, 1343 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1344 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1345 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1346 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 1347 clock-names = "pipe", 1348 "aux", 1349 "cfg", 1350 "bus_master", 1351 "bus_slave", 1352 "slave_q2a"; 1353 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1354 assigned-clock-rates = <19200000>; 1355 1356 interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS 1357 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1358 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1359 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1360 interconnect-names = "pcie-mem", "cpu-pcie"; 1361 1362 iommu-map = <0x0 &apps_smmu 0x400 0x0 0x1>, 1363 <0x100 &apps_smmu 0x401 0x0 0x1>; 1364 1365 resets = <&gcc GCC_PCIE_0_BCR>; 1366 reset-names = "pci"; 1367 1368 power-domains = <&gcc PCIE_0_GDSC>; 1369 1370 phys = <&pcie_phy>; 1371 phy-names = "pciephy"; 1372 1373 max-link-speed = <2>; 1374 1375 operating-points-v2 = <&pcie_opp_table>; 1376 1377 status = "disabled"; 1378 1379 pcie_opp_table: opp-table { 1380 compatible = "operating-points-v2"; 1381 1382 /* GEN 1 x1 */ 1383 opp-2500000 { 1384 opp-hz = /bits/ 64 <2500000>; 1385 required-opps = <&rpmhpd_opp_low_svs>; 1386 opp-peak-kBps = <250000 1>; 1387 }; 1388 1389 /* GEN 2 x1 */ 1390 opp-5000000 { 1391 opp-hz = /bits/ 64 <5000000>; 1392 required-opps = <&rpmhpd_opp_low_svs>; 1393 opp-peak-kBps = <500000 1>; 1394 }; 1395 }; 1396 1397 pcie_port0: pcie@0 { 1398 device_type = "pci"; 1399 reg = <0x0 0x0 0x0 0x0 0x0>; 1400 #address-cells = <3>; 1401 #size-cells = <2>; 1402 ranges; 1403 bus-range = <0x01 0xff>; 1404 }; 1405 }; 1406 1407 pcie_phy: phy@1c0e000 { 1408 compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy"; 1409 reg = <0x0 0x01c0e000 0x0 0x1000>; 1410 1411 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1412 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1413 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1414 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1415 <&gcc GCC_PCIE_0_PIPE_CLK>; 1416 clock-names = "aux", 1417 "cfg_ahb", 1418 "ref", 1419 "refgen", 1420 "pipe"; 1421 1422 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1423 reset-names = "phy"; 1424 1425 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1426 assigned-clock-rates = <100000000>; 1427 1428 #clock-cells = <0>; 1429 clock-output-names = "pcie_0_pipe_clk"; 1430 1431 #phy-cells = <0>; 1432 1433 status = "disabled"; 1434 }; 1435 1436 ufs_mem_hc: ufshc@1d84000 { 1437 compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1438 reg = <0x0 0x01d84000 0x0 0x3000>, 1439 <0x0 0x01d90000 0x0 0x8000>; 1440 reg-names = "std", 1441 "ice"; 1442 1443 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 1444 1445 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1446 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1447 <&gcc GCC_UFS_PHY_AHB_CLK>, 1448 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1449 <&rpmhcc RPMH_CXO_CLK>, 1450 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1451 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1452 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1453 clock-names = "core_clk", 1454 "bus_aggr_clk", 1455 "iface_clk", 1456 "core_clk_unipro", 1457 "ref_clk", 1458 "tx_lane0_sync_clk", 1459 "rx_lane0_sync_clk", 1460 "ice_core_clk"; 1461 1462 resets = <&gcc GCC_UFS_PHY_BCR>; 1463 reset-names = "rst"; 1464 1465 operating-points-v2 = <&ufs_opp_table>; 1466 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1467 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1468 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1469 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 1470 interconnect-names = "ufs-ddr", 1471 "cpu-ufs"; 1472 1473 power-domains = <&gcc UFS_PHY_GDSC>; 1474 1475 iommus = <&apps_smmu 0x300 0x0>; 1476 dma-coherent; 1477 1478 lanes-per-direction = <1>; 1479 1480 phys = <&ufs_mem_phy>; 1481 phy-names = "ufsphy"; 1482 1483 #reset-cells = <1>; 1484 1485 status = "disabled"; 1486 1487 ufs_opp_table: opp-table { 1488 compatible = "operating-points-v2"; 1489 1490 opp-50000000 { 1491 opp-hz = /bits/ 64 <50000000>, 1492 /bits/ 64 <0>, 1493 /bits/ 64 <0>, 1494 /bits/ 64 <37500000>, 1495 /bits/ 64 <0>, 1496 /bits/ 64 <0>, 1497 /bits/ 64 <0>, 1498 /bits/ 64 <75000000>; 1499 required-opps = <&rpmhpd_opp_low_svs>; 1500 }; 1501 1502 opp-100000000 { 1503 opp-hz = /bits/ 64 <100000000>, 1504 /bits/ 64 <0>, 1505 /bits/ 64 <0>, 1506 /bits/ 64 <75000000>, 1507 /bits/ 64 <0>, 1508 /bits/ 64 <0>, 1509 /bits/ 64 <0>, 1510 /bits/ 64 <150000000>; 1511 required-opps = <&rpmhpd_opp_svs>; 1512 }; 1513 1514 opp-200000000 { 1515 opp-hz = /bits/ 64 <200000000>, 1516 /bits/ 64 <0>, 1517 /bits/ 64 <0>, 1518 /bits/ 64 <150000000>, 1519 /bits/ 64 <0>, 1520 /bits/ 64 <0>, 1521 /bits/ 64 <0>, 1522 /bits/ 64 <300000000>; 1523 required-opps = <&rpmhpd_opp_nom>; 1524 }; 1525 }; 1526 }; 1527 1528 ufs_mem_phy: phy@1d87000 { 1529 compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy"; 1530 reg = <0x0 0x01d87000 0x0 0xe00>; 1531 clocks = <&rpmhcc RPMH_CXO_CLK>, 1532 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1533 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1534 clock-names = "ref", 1535 "ref_aux", 1536 "qref"; 1537 1538 power-domains = <&gcc UFS_PHY_GDSC>; 1539 1540 resets = <&ufs_mem_hc 0>; 1541 reset-names = "ufsphy"; 1542 1543 #clock-cells = <1>; 1544 #phy-cells = <0>; 1545 1546 status = "disabled"; 1547 }; 1548 1549 cryptobam: dma-controller@1dc4000 { 1550 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1551 reg = <0x0 0x01dc4000 0x0 0x24000>; 1552 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; 1553 #dma-cells = <1>; 1554 qcom,ee = <0>; 1555 qcom,controlled-remotely; 1556 num-channels = <16>; 1557 qcom,num-ees = <4>; 1558 iommus = <&apps_smmu 0x0104 0x0011>; 1559 }; 1560 1561 crypto: crypto@1dfa000 { 1562 compatible = "qcom,qcs615-qce", "qcom,sm8150-qce", "qcom,qce"; 1563 reg = <0x0 0x01dfa000 0x0 0x6000>; 1564 dmas = <&cryptobam 4>, <&cryptobam 5>; 1565 dma-names = "rx", "tx"; 1566 iommus = <&apps_smmu 0x0104 0x0011>; 1567 interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 1568 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1569 interconnect-names = "memory"; 1570 }; 1571 1572 tcsr_mutex: hwlock@1f40000 { 1573 compatible = "qcom,tcsr-mutex"; 1574 reg = <0x0 0x01f40000 0x0 0x20000>; 1575 #hwlock-cells = <1>; 1576 }; 1577 1578 tcsr: syscon@1fc0000 { 1579 compatible = "qcom,qcs615-tcsr", "syscon"; 1580 reg = <0x0 0x01fc0000 0x0 0x30000>; 1581 }; 1582 1583 tlmm: pinctrl@3100000 { 1584 compatible = "qcom,qcs615-tlmm"; 1585 reg = <0x0 0x03100000 0x0 0x300000>, 1586 <0x0 0x03500000 0x0 0x300000>, 1587 <0x0 0x03d00000 0x0 0x300000>; 1588 reg-names = "east", 1589 "west", 1590 "south"; 1591 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; 1592 gpio-ranges = <&tlmm 0 0 124>; 1593 gpio-controller; 1594 #gpio-cells = <2>; 1595 interrupt-controller; 1596 #interrupt-cells = <2>; 1597 wakeup-parent = <&pdc>; 1598 1599 cam_mclk0_default: cam-mclk0-default-state { 1600 pins = "gpio28"; 1601 function = "cam_mclk"; 1602 drive-strength = <2>; 1603 bias-disable; 1604 }; 1605 1606 cam_mclk1_default: cam-mclk1-default-state { 1607 pins = "gpio29"; 1608 function = "cam_mclk"; 1609 drive-strength = <2>; 1610 bias-disable; 1611 }; 1612 1613 cam_mclk2_default: cam-mclk2-default-state { 1614 pins = "gpio30"; 1615 function = "cam_mclk"; 1616 drive-strength = <2>; 1617 bias-disable; 1618 }; 1619 1620 cam_mclk3_default: cam-mclk3-default-state { 1621 pins = "gpio31"; 1622 function = "cam_mclk"; 1623 drive-strength = <2>; 1624 bias-disable; 1625 }; 1626 1627 cci_i2c0_default: cci-i2c0-default-state { 1628 /* SDA, SCL */ 1629 pins = "gpio32", "gpio33"; 1630 function = "cci_i2c"; 1631 drive-strength = <2>; 1632 bias-pull-up; 1633 }; 1634 1635 cci_i2c1_default: cci-i2c1-default-state { 1636 /* SDA, SCL */ 1637 pins = "gpio34", "gpio35"; 1638 function = "cci_i2c"; 1639 drive-strength = <2>; 1640 bias-pull-up; 1641 }; 1642 1643 qspi_cs0: qspi-cs0-state { 1644 pins = "gpio44"; 1645 function = "qspi"; 1646 bias-disable; 1647 drive-strength = <6>; 1648 }; 1649 1650 qspi_data0123: qspi-data0123-state { 1651 pins = "gpio45", "gpio46", "gpio47", "gpio49"; 1652 function = "qspi"; 1653 bias-pull-down; 1654 drive-strength = <6>; 1655 }; 1656 1657 qspi_clk: qspi-clk-state { 1658 pins = "gpio48"; 1659 function = "qspi"; 1660 bias-pull-down; 1661 drive-strength = <6>; 1662 }; 1663 1664 qspi_cs1: qspi-cs1-state { 1665 pins = "gpio50"; 1666 function = "qspi"; 1667 bias-pull-down; 1668 drive-strength = <6>; 1669 }; 1670 1671 mi2s1_pins: mi2s1-state { 1672 pins = "gpio108", "gpio109", "gpio110", "gpio111"; 1673 function = "mi2s_1"; 1674 drive-strength = <8>; 1675 bias-disable; 1676 }; 1677 1678 mi2s_mclk: mi2s-mclk-state { 1679 pins = "gpio122"; 1680 function = "mclk2"; 1681 drive-strength = <8>; 1682 bias-disable; 1683 }; 1684 1685 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 1686 pins = "gpio4", "gpio5"; 1687 function = "qup0"; 1688 1689 }; 1690 1691 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 1692 pins = "gpio0", "gpio1"; 1693 function = "qup0"; 1694 }; 1695 1696 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 1697 pins = "gpio18", "gpio19"; 1698 function = "qup0"; 1699 }; 1700 1701 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 1702 pins = "gpio20", "gpio21"; 1703 function = "qup1"; 1704 }; 1705 1706 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 1707 pins = "gpio14", "gpio15"; 1708 function = "qup1"; 1709 }; 1710 1711 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 1712 pins = "gpio6", "gpio7"; 1713 function = "qup1"; 1714 }; 1715 1716 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 1717 pins = "gpio10", "gpio11"; 1718 function = "qup1"; 1719 }; 1720 1721 qup_spi2_data_clk: qup-spi2-data-clk-state { 1722 pins = "gpio0", "gpio1", "gpio2"; 1723 function = "qup0"; 1724 }; 1725 1726 qup_spi2_cs: qup-spi2-cs-state { 1727 pins = "gpio3"; 1728 function = "qup0"; 1729 }; 1730 1731 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 1732 pins = "gpio3"; 1733 function = "gpio"; 1734 }; 1735 1736 qup_spi4_data_clk: qup-spi4-data-clk-state { 1737 pins = "gpio20", "gpio21", "gpio22"; 1738 function = "qup1"; 1739 }; 1740 1741 qup_spi4_cs: qup-spi4-cs-state { 1742 pins = "gpio23"; 1743 function = "qup1"; 1744 }; 1745 1746 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 1747 pins = "gpio23"; 1748 function = "gpio"; 1749 }; 1750 1751 qup_spi6_data_clk: qup-spi6-data-clk-state { 1752 pins = "gpio6", "gpio7", "gpio8"; 1753 function = "qup1"; 1754 }; 1755 1756 qup_spi6_cs: qup-spi6-cs-state { 1757 pins = "gpio9"; 1758 function = "qup1"; 1759 }; 1760 1761 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1762 pins = "gpio9"; 1763 function = "gpio"; 1764 }; 1765 1766 qup_spi7_data_clk: qup-spi7-data-clk-state { 1767 pins = "gpio10", "gpio11", "gpio12"; 1768 function = "qup1"; 1769 }; 1770 1771 qup_spi7_cs: qup-spi7-cs-state { 1772 pins = "gpio13"; 1773 function = "qup1"; 1774 }; 1775 1776 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 1777 pins = "gpio13"; 1778 function = "gpio"; 1779 }; 1780 1781 qup_uart0_tx: qup-uart0-tx-state { 1782 pins = "gpio16"; 1783 function = "qup0"; 1784 }; 1785 1786 qup_uart0_rx: qup-uart0-rx-state { 1787 pins = "gpio17"; 1788 function = "qup0"; 1789 }; 1790 1791 qup_uart2_cts: qup-uart2-cts-state { 1792 pins = "gpio0"; 1793 function = "qup0"; 1794 }; 1795 1796 qup_uart2_rts: qup-uart2-rts-state { 1797 pins = "gpio1"; 1798 function = "qup0"; 1799 }; 1800 1801 qup_uart2_tx: qup-uart2-tx-state { 1802 pins = "gpio2"; 1803 function = "qup0"; 1804 }; 1805 1806 qup_uart2_rx: qup-uart2-rx-state { 1807 pins = "gpio3"; 1808 function = "qup0"; 1809 }; 1810 1811 qup_uart4_cts: qup-uart4-cts-state { 1812 pins = "gpio20"; 1813 function = "qup1"; 1814 }; 1815 1816 qup_uart4_rts: qup-uart4-rts-state { 1817 pins = "gpio21"; 1818 function = "qup1"; 1819 }; 1820 1821 qup_uart4_tx: qup-uart4-tx-state { 1822 pins = "gpio22"; 1823 function = "qup1"; 1824 }; 1825 1826 qup_uart4_rx: qup-uart4-rx-state { 1827 pins = "gpio23"; 1828 function = "qup1"; 1829 }; 1830 1831 qup_uart6_cts: qup-uart6-cts-state { 1832 pins = "gpio6"; 1833 function = "qup1"; 1834 }; 1835 1836 qup_uart6_rts: qup-uart6-rts-state { 1837 pins = "gpio7"; 1838 function = "qup1"; 1839 }; 1840 1841 qup_uart6_tx: qup-uart6-tx-state { 1842 pins = "gpio8"; 1843 function = "qup1"; 1844 }; 1845 1846 qup_uart6_rx: qup-uart6-rx-state { 1847 pins = "gpio9"; 1848 function = "qup1"; 1849 }; 1850 1851 qup_uart7_cts: qup-uart7-cts-state { 1852 pins = "gpio10"; 1853 function = "qup1"; 1854 }; 1855 1856 qup_uart7_rts: qup-uart7-rts-state { 1857 pins = "gpio11"; 1858 function = "qup1"; 1859 }; 1860 1861 qup_uart7_tx: qup-uart7-tx-state { 1862 pins = "gpio12"; 1863 function = "qup1"; 1864 }; 1865 1866 qup_uart7_rx: qup-uart7-rx-state { 1867 pins = "gpio13"; 1868 function = "qup1"; 1869 }; 1870 1871 sdc1_state_on: sdc1-on-state { 1872 clk-pins { 1873 pins = "sdc1_clk"; 1874 bias-disable; 1875 drive-strength = <16>; 1876 }; 1877 1878 cmd-pins { 1879 pins = "sdc1_cmd"; 1880 bias-pull-up; 1881 drive-strength = <10>; 1882 }; 1883 1884 data-pins { 1885 pins = "sdc1_data"; 1886 bias-pull-up; 1887 drive-strength = <10>; 1888 }; 1889 1890 rclk-pins { 1891 pins = "sdc1_rclk"; 1892 bias-pull-down; 1893 }; 1894 }; 1895 1896 sdc1_state_off: sdc1-off-state { 1897 clk-pins { 1898 pins = "sdc1_clk"; 1899 bias-disable; 1900 drive-strength = <2>; 1901 }; 1902 1903 cmd-pins { 1904 pins = "sdc1_cmd"; 1905 bias-pull-up; 1906 drive-strength = <2>; 1907 }; 1908 1909 data-pins { 1910 pins = "sdc1_data"; 1911 bias-pull-up; 1912 drive-strength = <2>; 1913 }; 1914 1915 rclk-pins { 1916 pins = "sdc1_rclk"; 1917 bias-pull-down; 1918 }; 1919 }; 1920 1921 sdc2_state_on: sdc2-on-state { 1922 clk-pins { 1923 pins = "sdc2_clk"; 1924 bias-disable; 1925 drive-strength = <16>; 1926 }; 1927 1928 cmd-pins { 1929 pins = "sdc2_cmd"; 1930 bias-pull-up; 1931 drive-strength = <10>; 1932 }; 1933 1934 data-pins { 1935 pins = "sdc2_data"; 1936 bias-pull-up; 1937 drive-strength = <10>; 1938 }; 1939 }; 1940 1941 sdc2_state_off: sdc2-off-state { 1942 clk-pins { 1943 pins = "sdc2_clk"; 1944 bias-disable; 1945 drive-strength = <2>; 1946 }; 1947 1948 cmd-pins { 1949 pins = "sdc2_cmd"; 1950 bias-pull-up; 1951 drive-strength = <2>; 1952 }; 1953 1954 data-pins { 1955 pins = "sdc2_data"; 1956 bias-pull-up; 1957 drive-strength = <2>; 1958 }; 1959 }; 1960 }; 1961 1962 gpu: gpu@5000000 { 1963 compatible = "qcom,adreno-612.0", "qcom,adreno"; 1964 reg = <0x0 0x05000000 0x0 0x40000>, 1965 <0x0 0x0509e000 0x0 0x1000>, 1966 <0x0 0x05061000 0x0 0x800>; 1967 reg-names = "kgsl_3d0_reg_memory", 1968 "cx_mem", 1969 "cx_dbgc"; 1970 1971 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>; 1972 clock-names = "core"; 1973 1974 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; 1975 1976 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 1977 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1978 interconnect-names = "gfx-mem"; 1979 1980 iommus = <&adreno_smmu 0x0 0x401>; 1981 1982 operating-points-v2 = <&gpu_opp_table>; 1983 power-domains = <&rpmhpd RPMHPD_CX>; 1984 1985 qcom,gmu = <&gmu>; 1986 1987 #cooling-cells = <2>; 1988 1989 status = "disabled"; 1990 1991 gpu_zap_shader: zap-shader { 1992 memory-region = <&pil_gpu_mem>; 1993 }; 1994 1995 gpu_opp_table: opp-table { 1996 compatible = "operating-points-v2"; 1997 1998 opp-845000000 { 1999 opp-hz = /bits/ 64 <845000000>; 2000 required-opps = <&rpmhpd_opp_turbo>; 2001 opp-peak-kBps = <7050000>; 2002 }; 2003 2004 opp-745000000 { 2005 opp-hz = /bits/ 64 <745000000>; 2006 required-opps = <&rpmhpd_opp_nom_l1>; 2007 opp-peak-kBps = <6075000>; 2008 }; 2009 2010 opp-650000000 { 2011 opp-hz = /bits/ 64 <650000000>; 2012 required-opps = <&rpmhpd_opp_nom>; 2013 opp-peak-kBps = <5287500>; 2014 }; 2015 2016 opp-500000000 { 2017 opp-hz = /bits/ 64 <500000000>; 2018 required-opps = <&rpmhpd_opp_svs_l1>; 2019 opp-peak-kBps = <3975000>; 2020 }; 2021 2022 opp-435000000 { 2023 opp-hz = /bits/ 64 <435000000>; 2024 required-opps = <&rpmhpd_opp_svs>; 2025 opp-peak-kBps = <3000000>; 2026 }; 2027 }; 2028 }; 2029 2030 gmu: gmu@506d000 { 2031 compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu"; 2032 reg = <0x0 0x0506d000 0x0 0x2c000>; 2033 2034 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2035 <&gpucc GPU_CC_CXO_CLK>, 2036 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2037 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2038 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2039 clock-names = "gmu", 2040 "cxo", 2041 "axi", 2042 "memnoc", 2043 "smmu_vote"; 2044 2045 power-domains = <&gpucc CX_GDSC>, 2046 <&gpucc GX_GDSC>; 2047 power-domain-names = "cx", 2048 "gx"; 2049 2050 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>, 2051 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 2052 interrupt-names = "oob", 2053 "gmu"; 2054 2055 operating-points-v2 = <&gmu_opp_table>; 2056 2057 gmu_opp_table: opp-table { 2058 compatible = "operating-points-v2"; 2059 2060 opp-200000000 { 2061 opp-hz = /bits/ 64 <200000000>; 2062 required-opps = <&rpmhpd_opp_low_svs>; 2063 }; 2064 }; 2065 }; 2066 2067 gpucc: clock-controller@5090000 { 2068 compatible = "qcom,qcs615-gpucc"; 2069 reg = <0 0x05090000 0 0x9000>; 2070 2071 clocks = <&rpmhcc RPMH_CXO_CLK>, 2072 <&gcc GPLL0>, 2073 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2074 2075 #clock-cells = <1>; 2076 #reset-cells = <1>; 2077 #power-domain-cells = <1>; 2078 }; 2079 2080 adreno_smmu: iommu@50a0000 { 2081 compatible = "qcom,qcs615-smmu-500", "qcom,adreno-smmu", 2082 "qcom,smmu-500", "arm,mmu-500"; 2083 reg = <0x0 0x050a0000 0x0 0x40000>; 2084 #iommu-cells = <2>; 2085 #global-interrupts = <1>; 2086 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>, 2087 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, 2088 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, 2089 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, 2090 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, 2091 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, 2092 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, 2093 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, 2094 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>; 2095 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2096 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2097 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2098 clock-names = "mem", 2099 "hlos", 2100 "iface"; 2101 power-domains = <&gpucc CX_GDSC>; 2102 dma-coherent; 2103 }; 2104 2105 stm@6002000 { 2106 compatible = "arm,coresight-stm", "arm,primecell"; 2107 reg = <0x0 0x06002000 0x0 0x1000>, 2108 <0x0 0x16280000 0x0 0x180000>; 2109 reg-names = "stm-base", 2110 "stm-stimulus-base"; 2111 2112 clocks = <&aoss_qmp>; 2113 clock-names = "apb_pclk"; 2114 2115 out-ports { 2116 port { 2117 stm_out: endpoint { 2118 remote-endpoint = <&funnel_in0_in7>; 2119 }; 2120 }; 2121 }; 2122 }; 2123 2124 tpda@6004000 { 2125 compatible = "qcom,coresight-tpda", "arm,primecell"; 2126 reg = <0x0 0x06004000 0x0 0x1000>; 2127 2128 clocks = <&aoss_qmp>; 2129 clock-names = "apb_pclk"; 2130 2131 in-ports { 2132 #address-cells = <1>; 2133 #size-cells = <0>; 2134 2135 port@0 { 2136 reg = <0>; 2137 2138 tpda_qdss_in0: endpoint { 2139 remote-endpoint = <&tpdm_center_out>; 2140 }; 2141 }; 2142 2143 port@4 { 2144 reg = <4>; 2145 2146 tpda_qdss_in4: endpoint { 2147 remote-endpoint = <&funnel_monaq_out>; 2148 }; 2149 }; 2150 2151 port@5 { 2152 reg = <5>; 2153 2154 tpda_qdss_in5: endpoint { 2155 remote-endpoint = <&funnel_ddr_0_out>; 2156 }; 2157 }; 2158 2159 port@6 { 2160 reg = <6>; 2161 2162 tpda_qdss_in6: endpoint { 2163 remote-endpoint = <&funnel_turing_out>; 2164 }; 2165 }; 2166 2167 port@7 { 2168 reg = <7>; 2169 2170 tpda_qdss_in7: endpoint { 2171 remote-endpoint = <&tpdm_vsense_out>; 2172 }; 2173 }; 2174 2175 port@8 { 2176 reg = <8>; 2177 2178 tpda_qdss_in8: endpoint { 2179 remote-endpoint = <&tpdm_dcc_out>; 2180 }; 2181 }; 2182 2183 port@9 { 2184 reg = <9>; 2185 2186 tpda_qdss_in9: endpoint { 2187 remote-endpoint = <&tpdm_prng_out>; 2188 }; 2189 }; 2190 2191 port@b { 2192 reg = <11>; 2193 2194 tpda_qdss_in11: endpoint { 2195 remote-endpoint = <&tpdm_qm_out>; 2196 }; 2197 }; 2198 2199 port@c { 2200 reg = <12>; 2201 2202 tpda_qdss_in12: endpoint { 2203 remote-endpoint = <&tpdm_west_out>; 2204 }; 2205 }; 2206 2207 port@d { 2208 reg = <13>; 2209 2210 tpda_qdss_in13: endpoint { 2211 remote-endpoint = <&tpdm_pimem_out>; 2212 }; 2213 }; 2214 }; 2215 2216 out-ports { 2217 port { 2218 tpda_qdss_out: endpoint { 2219 remote-endpoint = <&funnel_qatb_in>; 2220 }; 2221 }; 2222 }; 2223 }; 2224 2225 funnel@6005000 { 2226 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2227 reg = <0x0 0x06005000 0x0 0x1000>; 2228 2229 clocks = <&aoss_qmp>; 2230 clock-names = "apb_pclk"; 2231 2232 in-ports { 2233 port { 2234 funnel_qatb_in: endpoint { 2235 remote-endpoint = <&tpda_qdss_out>; 2236 }; 2237 }; 2238 }; 2239 2240 out-ports { 2241 port { 2242 funnel_qatb_out: endpoint { 2243 remote-endpoint = <&funnel_in0_in6>; 2244 }; 2245 }; 2246 }; 2247 }; 2248 2249 cti@6010000 { 2250 compatible = "arm,coresight-cti", "arm,primecell"; 2251 reg = <0x0 0x06010000 0x0 0x1000>; 2252 2253 clocks = <&aoss_qmp>; 2254 clock-names = "apb_pclk"; 2255 label = "cti_qdss"; 2256 }; 2257 2258 cti@6011000 { 2259 compatible = "arm,coresight-cti", "arm,primecell"; 2260 reg = <0x0 0x06011000 0x0 0x1000>; 2261 2262 clocks = <&aoss_qmp>; 2263 clock-names = "apb_pclk"; 2264 label = "cti_qdss_1"; 2265 }; 2266 2267 cti@6012000 { 2268 compatible = "arm,coresight-cti", "arm,primecell"; 2269 reg = <0x0 0x06012000 0x0 0x1000>; 2270 2271 clocks = <&aoss_qmp>; 2272 clock-names = "apb_pclk"; 2273 label = "cti_qdss_2"; 2274 }; 2275 2276 cti@6013000 { 2277 compatible = "arm,coresight-cti", "arm,primecell"; 2278 reg = <0x0 0x06013000 0x0 0x1000>; 2279 2280 clocks = <&aoss_qmp>; 2281 clock-names = "apb_pclk"; 2282 label = "cti_qdss_3"; 2283 }; 2284 2285 cti@6014000 { 2286 compatible = "arm,coresight-cti", "arm,primecell"; 2287 reg = <0x0 0x06014000 0x0 0x1000>; 2288 2289 clocks = <&aoss_qmp>; 2290 clock-names = "apb_pclk"; 2291 label = "cti_qdss_4"; 2292 }; 2293 2294 cti@6015000 { 2295 compatible = "arm,coresight-cti", "arm,primecell"; 2296 reg = <0x0 0x06015000 0x0 0x1000>; 2297 2298 clocks = <&aoss_qmp>; 2299 clock-names = "apb_pclk"; 2300 label = "cti_qdss_5"; 2301 }; 2302 2303 cti@6016000 { 2304 compatible = "arm,coresight-cti", "arm,primecell"; 2305 reg = <0x0 0x06016000 0x0 0x1000>; 2306 2307 clocks = <&aoss_qmp>; 2308 clock-names = "apb_pclk"; 2309 label = "cti_qdss_6"; 2310 }; 2311 2312 cti@6017000 { 2313 compatible = "arm,coresight-cti", "arm,primecell"; 2314 reg = <0x0 0x06017000 0x0 0x1000>; 2315 2316 clocks = <&aoss_qmp>; 2317 clock-names = "apb_pclk"; 2318 label = "cti_qdss_7"; 2319 }; 2320 2321 cti@6018000 { 2322 compatible = "arm,coresight-cti", "arm,primecell"; 2323 reg = <0x0 0x06018000 0x0 0x1000>; 2324 2325 clocks = <&aoss_qmp>; 2326 clock-names = "apb_pclk"; 2327 label = "cti_qdss_8"; 2328 }; 2329 2330 cti@6019000 { 2331 compatible = "arm,coresight-cti", "arm,primecell"; 2332 reg = <0x0 0x06019000 0x0 0x1000>; 2333 2334 clocks = <&aoss_qmp>; 2335 clock-names = "apb_pclk"; 2336 label = "cti_qdss_9"; 2337 }; 2338 2339 cti@601a000 { 2340 compatible = "arm,coresight-cti", "arm,primecell"; 2341 reg = <0x0 0x0601a000 0x0 0x1000>; 2342 2343 clocks = <&aoss_qmp>; 2344 clock-names = "apb_pclk"; 2345 label = "cti_qdss_10"; 2346 }; 2347 2348 cti@601b000 { 2349 compatible = "arm,coresight-cti", "arm,primecell"; 2350 reg = <0x0 0x0601b000 0x0 0x1000>; 2351 2352 clocks = <&aoss_qmp>; 2353 clock-names = "apb_pclk"; 2354 label = "cti_qdss_11"; 2355 }; 2356 2357 cti@601c000 { 2358 compatible = "arm,coresight-cti", "arm,primecell"; 2359 reg = <0x0 0x0601c000 0x0 0x1000>; 2360 2361 clocks = <&aoss_qmp>; 2362 clock-names = "apb_pclk"; 2363 label = "cti_qdss_12"; 2364 }; 2365 2366 cti@601d000 { 2367 compatible = "arm,coresight-cti", "arm,primecell"; 2368 reg = <0x0 0x0601d000 0x0 0x1000>; 2369 2370 clocks = <&aoss_qmp>; 2371 clock-names = "apb_pclk"; 2372 label = "cti_qdss_13"; 2373 }; 2374 2375 cti@601e000 { 2376 compatible = "arm,coresight-cti", "arm,primecell"; 2377 reg = <0x0 0x0601e000 0x0 0x1000>; 2378 2379 clocks = <&aoss_qmp>; 2380 clock-names = "apb_pclk"; 2381 label = "cti_qdss_14"; 2382 }; 2383 2384 cti@601f000 { 2385 compatible = "arm,coresight-cti", "arm,primecell"; 2386 reg = <0x0 0x0601f000 0x0 0x1000>; 2387 2388 clocks = <&aoss_qmp>; 2389 clock-names = "apb_pclk"; 2390 label = "cti_qdss_15"; 2391 }; 2392 2393 funnel@6041000 { 2394 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2395 reg = <0x0 0x06041000 0x0 0x1000>; 2396 2397 clocks = <&aoss_qmp>; 2398 clock-names = "apb_pclk"; 2399 2400 in-ports { 2401 #address-cells = <1>; 2402 #size-cells = <0>; 2403 2404 port@6 { 2405 reg = <6>; 2406 2407 funnel_in0_in6: endpoint { 2408 remote-endpoint = <&funnel_qatb_out>; 2409 }; 2410 }; 2411 2412 port@7 { 2413 reg = <7>; 2414 2415 funnel_in0_in7: endpoint { 2416 remote-endpoint = <&stm_out>; 2417 }; 2418 }; 2419 }; 2420 2421 out-ports { 2422 port { 2423 funnel_in0_out: endpoint { 2424 remote-endpoint = <&funnel_merg_in0>; 2425 }; 2426 }; 2427 }; 2428 }; 2429 2430 funnel@6042000 { 2431 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2432 reg = <0x0 0x06042000 0x0 0x1000>; 2433 2434 clocks = <&aoss_qmp>; 2435 clock-names = "apb_pclk"; 2436 2437 in-ports { 2438 #address-cells = <1>; 2439 #size-cells = <0>; 2440 2441 port@3 { 2442 reg = <3>; 2443 2444 funnel_in1_in3: endpoint { 2445 remote-endpoint = <&replicator_swao_out0>; 2446 }; 2447 }; 2448 2449 port@4 { 2450 reg = <4>; 2451 2452 funnel_in1_in4: endpoint { 2453 remote-endpoint = <&tpdm_wcss_out>; 2454 }; 2455 }; 2456 2457 port@7 { 2458 reg = <7>; 2459 2460 funnel_in1_in7: endpoint { 2461 remote-endpoint = <&funnel_apss_merg_out>; 2462 }; 2463 }; 2464 }; 2465 2466 out-ports { 2467 port { 2468 funnel_in1_out: endpoint { 2469 remote-endpoint = <&funnel_merg_in1>; 2470 }; 2471 }; 2472 }; 2473 }; 2474 2475 funnel@6045000 { 2476 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2477 reg = <0x0 0x06045000 0x0 0x1000>; 2478 2479 clocks = <&aoss_qmp>; 2480 clock-names = "apb_pclk"; 2481 2482 in-ports { 2483 #address-cells = <1>; 2484 #size-cells = <0>; 2485 2486 port@0 { 2487 reg = <0>; 2488 2489 funnel_merg_in0: endpoint { 2490 remote-endpoint = <&funnel_in0_out>; 2491 }; 2492 }; 2493 2494 port@1 { 2495 reg = <1>; 2496 2497 funnel_merg_in1: endpoint { 2498 remote-endpoint = <&funnel_in1_out>; 2499 }; 2500 }; 2501 }; 2502 2503 out-ports { 2504 port { 2505 funnel_merg_out: endpoint { 2506 remote-endpoint = <&tmc_etf_in>; 2507 }; 2508 }; 2509 }; 2510 }; 2511 2512 replicator@6046000 { 2513 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2514 reg = <0x0 0x06046000 0x0 0x1000>; 2515 2516 clocks = <&aoss_qmp>; 2517 clock-names = "apb_pclk"; 2518 2519 in-ports { 2520 port { 2521 replicator0_in: endpoint { 2522 remote-endpoint = <&tmc_etf_out>; 2523 }; 2524 }; 2525 }; 2526 2527 out-ports { 2528 #address-cells = <1>; 2529 #size-cells = <0>; 2530 2531 port@0 { 2532 reg = <0>; 2533 2534 replicator0_out0: endpoint { 2535 remote-endpoint = <&tmc_etr_in>; 2536 }; 2537 }; 2538 2539 port@1 { 2540 reg = <1>; 2541 2542 replicator0_out1: endpoint { 2543 remote-endpoint = <&replicator1_in>; 2544 }; 2545 }; 2546 }; 2547 }; 2548 2549 tmc@6047000 { 2550 compatible = "arm,coresight-tmc", "arm,primecell"; 2551 reg = <0x0 0x06047000 0x0 0x1000>; 2552 2553 clocks = <&aoss_qmp>; 2554 clock-names = "apb_pclk"; 2555 2556 in-ports { 2557 port { 2558 tmc_etf_in: endpoint { 2559 remote-endpoint = <&funnel_merg_out>; 2560 }; 2561 }; 2562 }; 2563 2564 out-ports { 2565 port { 2566 tmc_etf_out: endpoint { 2567 remote-endpoint = <&replicator0_in>; 2568 }; 2569 }; 2570 }; 2571 }; 2572 2573 tmc@6048000 { 2574 compatible = "arm,coresight-tmc", "arm,primecell"; 2575 reg = <0x0 0x06048000 0x0 0x1000>; 2576 2577 clocks = <&aoss_qmp>; 2578 clock-names = "apb_pclk"; 2579 2580 iommus = <&apps_smmu 0x01e0 0x0>; 2581 arm,scatter-gather; 2582 2583 in-ports { 2584 port { 2585 tmc_etr_in: endpoint { 2586 remote-endpoint = <&replicator0_out0>; 2587 }; 2588 }; 2589 }; 2590 }; 2591 2592 replicator@604a000 { 2593 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2594 reg = <0x0 0x0604a000 0x0 0x1000>; 2595 2596 clocks = <&aoss_qmp>; 2597 clock-names = "apb_pclk"; 2598 status = "disabled"; 2599 2600 in-ports { 2601 port { 2602 replicator1_in: endpoint { 2603 remote-endpoint = <&replicator0_out1>; 2604 }; 2605 }; 2606 }; 2607 2608 out-ports { 2609 port { 2610 replicator1_out: endpoint { 2611 remote-endpoint = <&funnel_swao_in6>; 2612 }; 2613 }; 2614 }; 2615 }; 2616 2617 cti@683b000 { 2618 compatible = "arm,coresight-cti", "arm,primecell"; 2619 reg = <0x0 0x0683b000 0x0 0x1000>; 2620 2621 clocks = <&aoss_qmp>; 2622 clock-names = "apb_pclk"; 2623 label = "cti_qdsp6"; 2624 }; 2625 2626 tpdm@6840000 { 2627 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2628 reg = <0x0 0x06840000 0x0 0x1000>; 2629 2630 clocks = <&aoss_qmp>; 2631 clock-names = "apb_pclk"; 2632 label = "tpdm_vsense"; 2633 2634 qcom,cmb-element-bits = <64>; 2635 qcom,cmb-msrs-num = <32>; 2636 status = "disabled"; 2637 2638 out-ports { 2639 port { 2640 tpdm_vsense_out: endpoint { 2641 remote-endpoint = <&tpda_qdss_in7>; 2642 }; 2643 }; 2644 }; 2645 }; 2646 2647 tpdm@684c000 { 2648 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2649 reg = <0x0 0x0684c000 0x0 0x1000>; 2650 2651 clocks = <&aoss_qmp>; 2652 clock-names = "apb_pclk"; 2653 label = "tpdm_prng"; 2654 2655 qcom,cmb-element-bits = <32>; 2656 qcom,cmb-msrs-num = <32>; 2657 2658 out-ports { 2659 port { 2660 tpdm_prng_out: endpoint { 2661 remote-endpoint = <&tpda_qdss_in9>; 2662 }; 2663 }; 2664 }; 2665 }; 2666 2667 tpdm@6850000 { 2668 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2669 reg = <0x0 0x06850000 0x0 0x1000>; 2670 2671 clocks = <&aoss_qmp>; 2672 clock-names = "apb_pclk"; 2673 label = "tpdm_pimem"; 2674 2675 qcom,cmb-element-bits = <64>; 2676 qcom,cmb-msrs-num = <32>; 2677 qcom,dsb-element-bits = <32>; 2678 qcom,dsb-msrs-num = <32>; 2679 2680 out-ports { 2681 port { 2682 tpdm_pimem_out: endpoint { 2683 remote-endpoint = <&tpda_qdss_in13>; 2684 }; 2685 }; 2686 }; 2687 }; 2688 2689 tpdm@6860000 { 2690 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2691 reg = <0x0 0x06860000 0x0 0x1000>; 2692 2693 clocks = <&aoss_qmp>; 2694 clock-names = "apb_pclk"; 2695 label = "tpdm_cdsp"; 2696 2697 qcom,dsb-element-bits = <32>; 2698 qcom,dsb-msrs-num = <32>; 2699 2700 out-ports { 2701 port { 2702 tpdm_turing_out: endpoint { 2703 remote-endpoint = <&funnel_turing_in>; 2704 }; 2705 }; 2706 }; 2707 }; 2708 2709 funnel@6861000 { 2710 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2711 reg = <0x0 0x06861000 0x0 0x1000>; 2712 2713 clocks = <&aoss_qmp>; 2714 clock-names = "apb_pclk"; 2715 2716 in-ports { 2717 port { 2718 funnel_turing_in: endpoint { 2719 remote-endpoint = <&tpdm_turing_out>; 2720 }; 2721 }; 2722 }; 2723 2724 out-ports { 2725 port { 2726 funnel_turing_out: endpoint { 2727 remote-endpoint = <&tpda_qdss_in6>; 2728 }; 2729 }; 2730 }; 2731 }; 2732 2733 cti@6867000 { 2734 compatible = "arm,coresight-cti", "arm,primecell"; 2735 reg = <0x0 0x06867000 0x0 0x1000>; 2736 2737 clocks = <&aoss_qmp>; 2738 clock-names = "apb_pclk"; 2739 label = "cti_cdsp"; 2740 }; 2741 2742 tpdm@6870000 { 2743 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2744 reg = <0x0 0x06870000 0x0 0x1000>; 2745 2746 clocks = <&aoss_qmp>; 2747 clock-names = "apb_pclk"; 2748 label = "tpdm_dcc"; 2749 2750 qcom,cmb-element-bits = <32>; 2751 qcom,cmb-msrs-num = <32>; 2752 status = "disabled"; 2753 2754 out-ports { 2755 port { 2756 tpdm_dcc_out: endpoint { 2757 remote-endpoint = <&tpda_qdss_in8>; 2758 }; 2759 }; 2760 }; 2761 }; 2762 2763 tpdm@699c000 { 2764 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2765 reg = <0x0 0x0699c000 0x0 0x1000>; 2766 2767 clocks = <&aoss_qmp>; 2768 clock-names = "apb_pclk"; 2769 label = "tpdm_wcss"; 2770 2771 qcom,cmb-element-bits = <32>; 2772 qcom,cmb-msrs-num = <32>; 2773 qcom,dsb-element-bits = <32>; 2774 qcom,dsb-msrs-num = <32>; 2775 status = "disabled"; 2776 2777 out-ports { 2778 port { 2779 tpdm_wcss_out: endpoint { 2780 remote-endpoint = <&funnel_in1_in4>; 2781 }; 2782 }; 2783 }; 2784 }; 2785 2786 tpdm@69c0000 { 2787 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2788 reg = <0x0 0x069c0000 0x0 0x1000>; 2789 2790 clocks = <&aoss_qmp>; 2791 clock-names = "apb_pclk"; 2792 label = "tpdm_monaq"; 2793 2794 qcom,dsb-element-bits = <32>; 2795 qcom,dsb-msrs-num = <32>; 2796 2797 out-ports { 2798 port { 2799 tpdm_monaq_out: endpoint { 2800 remote-endpoint = <&funnel_monaq_in>; 2801 }; 2802 }; 2803 }; 2804 }; 2805 2806 funnel@69c3000 { 2807 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2808 reg = <0x0 0x069c3000 0x0 0x1000>; 2809 2810 clocks = <&aoss_qmp>; 2811 clock-names = "apb_pclk"; 2812 2813 in-ports { 2814 port { 2815 funnel_monaq_in: endpoint { 2816 remote-endpoint = <&tpdm_monaq_out>; 2817 }; 2818 }; 2819 }; 2820 2821 out-ports { 2822 port { 2823 funnel_monaq_out: endpoint { 2824 remote-endpoint = <&tpda_qdss_in4>; 2825 }; 2826 }; 2827 }; 2828 }; 2829 2830 tpdm@69d0000 { 2831 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2832 reg = <0x0 0x069d0000 0x0 0x1000>; 2833 2834 clocks = <&aoss_qmp>; 2835 clock-names = "apb_pclk"; 2836 label = "tpdm_qm"; 2837 2838 qcom,dsb-element-bits = <32>; 2839 qcom,dsb-msrs-num = <32>; 2840 status = "disabled"; 2841 2842 out-ports { 2843 port { 2844 tpdm_qm_out: endpoint { 2845 remote-endpoint = <&tpda_qdss_in11>; 2846 }; 2847 }; 2848 }; 2849 }; 2850 2851 tpdm@6a00000 { 2852 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2853 reg = <0x0 0x06a00000 0x0 0x1000>; 2854 2855 clocks = <&aoss_qmp>; 2856 clock-names = "apb_pclk"; 2857 label = "tpdm_ddr"; 2858 2859 qcom,dsb-element-bits = <32>; 2860 qcom,dsb-msrs-num = <32>; 2861 status = "disabled"; 2862 2863 out-ports { 2864 port { 2865 tpdm_ddr_out: endpoint { 2866 remote-endpoint = <&funnel_ddr_0_in>; 2867 }; 2868 }; 2869 }; 2870 }; 2871 2872 cti@6a02000 { 2873 compatible = "arm,coresight-cti", "arm,primecell"; 2874 reg = <0x0 0x06a02000 0x0 0x1000>; 2875 2876 clocks = <&aoss_qmp>; 2877 clock-names = "apb_pclk"; 2878 label = "cti_ddr_dl0"; 2879 }; 2880 2881 cti@6a03000 { 2882 compatible = "arm,coresight-cti", "arm,primecell"; 2883 reg = <0x0 0x06a03000 0x0 0x1000>; 2884 2885 clocks = <&aoss_qmp>; 2886 clock-names = "apb_pclk"; 2887 label = "cti_ddr_dl0_1"; 2888 }; 2889 2890 cti@6a10000 { 2891 compatible = "arm,coresight-cti", "arm,primecell"; 2892 reg = <0x0 0x06a10000 0x0 0x1000>; 2893 2894 clocks = <&aoss_qmp>; 2895 clock-names = "apb_pclk"; 2896 label = "cti_ddr_dl1"; 2897 }; 2898 2899 cti@6a11000 { 2900 compatible = "arm,coresight-cti", "arm,primecell"; 2901 reg = <0x0 0x06a11000 0x0 0x1000>; 2902 2903 clocks = <&aoss_qmp>; 2904 clock-names = "apb_pclk"; 2905 label = "cti_ddr_dl1_1"; 2906 }; 2907 2908 funnel@6a05000 { 2909 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2910 reg = <0x0 0x06a05000 0x0 0x1000>; 2911 2912 clocks = <&aoss_qmp>; 2913 clock-names = "apb_pclk"; 2914 2915 in-ports { 2916 port { 2917 funnel_ddr_0_in: endpoint { 2918 remote-endpoint = <&tpdm_ddr_out>; 2919 }; 2920 }; 2921 }; 2922 2923 out-ports { 2924 port { 2925 funnel_ddr_0_out: endpoint { 2926 remote-endpoint = <&tpda_qdss_in5>; 2927 }; 2928 }; 2929 }; 2930 }; 2931 2932 tpda@6b01000 { 2933 compatible = "qcom,coresight-tpda", "arm,primecell"; 2934 reg = <0x0 0x06b01000 0x0 0x1000>; 2935 2936 clocks = <&aoss_qmp>; 2937 clock-names = "apb_pclk"; 2938 2939 in-ports { 2940 #address-cells = <1>; 2941 #size-cells = <0>; 2942 2943 port@0 { 2944 reg = <0>; 2945 2946 tpda_swao_in0: endpoint { 2947 remote-endpoint = <&tpdm_swao0_out>; 2948 }; 2949 }; 2950 2951 port@1 { 2952 reg = <1>; 2953 2954 tpda_swao_in1: endpoint { 2955 remote-endpoint = <&tpdm_swao1_out>; 2956 }; 2957 2958 }; 2959 }; 2960 2961 out-ports { 2962 port { 2963 tpda_swao_out: endpoint { 2964 remote-endpoint = <&funnel_swao_in7>; 2965 }; 2966 }; 2967 }; 2968 }; 2969 2970 tpdm@6b02000 { 2971 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2972 reg = <0x0 0x06b02000 0x0 0x1000>; 2973 2974 clocks = <&aoss_qmp>; 2975 clock-names = "apb_pclk"; 2976 label = "tpdm_swao_0"; 2977 2978 qcom,cmb-element-bits = <64>; 2979 qcom,cmb-msrs-num = <32>; 2980 status = "disabled"; 2981 2982 out-ports { 2983 port { 2984 tpdm_swao0_out: endpoint { 2985 remote-endpoint = <&tpda_swao_in0>; 2986 }; 2987 }; 2988 }; 2989 }; 2990 2991 tpdm@6b03000 { 2992 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2993 reg = <0x0 0x06b03000 0x0 0x1000>; 2994 2995 clocks = <&aoss_qmp>; 2996 clock-names = "apb_pclk"; 2997 label = "tpdm_swao_1"; 2998 2999 qcom,dsb-element-bits = <32>; 3000 qcom,dsb-msrs-num = <32>; 3001 status = "disabled"; 3002 3003 out-ports { 3004 port { 3005 tpdm_swao1_out: endpoint { 3006 remote-endpoint = <&tpda_swao_in1>; 3007 }; 3008 }; 3009 }; 3010 }; 3011 3012 cti@6b04000 { 3013 compatible = "arm,coresight-cti", "arm,primecell"; 3014 reg = <0x0 0x06b04000 0x0 0x1000>; 3015 3016 clocks = <&aoss_qmp>; 3017 clock-names = "apb_pclk"; 3018 label = "cti_swao"; 3019 }; 3020 3021 cti@6b05000 { 3022 compatible = "arm,coresight-cti", "arm,primecell"; 3023 reg = <0x0 0x06b05000 0x0 0x1000>; 3024 3025 clocks = <&aoss_qmp>; 3026 clock-names = "apb_pclk"; 3027 label = "cti_swao_1"; 3028 }; 3029 3030 cti@6b06000 { 3031 compatible = "arm,coresight-cti", "arm,primecell"; 3032 reg = <0x0 0x06b06000 0x0 0x1000>; 3033 3034 clocks = <&aoss_qmp>; 3035 clock-names = "apb_pclk"; 3036 label = "cti_swao_2"; 3037 }; 3038 3039 cti@6b07000 { 3040 compatible = "arm,coresight-cti", "arm,primecell"; 3041 reg = <0x0 0x06b07000 0x0 0x1000>; 3042 3043 clocks = <&aoss_qmp>; 3044 clock-names = "apb_pclk"; 3045 label = "cti_swao_3"; 3046 }; 3047 3048 funnel@6b08000 { 3049 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3050 reg = <0x0 0x06b08000 0x0 0x1000>; 3051 3052 clocks = <&aoss_qmp>; 3053 clock-names = "apb_pclk"; 3054 3055 in-ports { 3056 #address-cells = <1>; 3057 #size-cells = <0>; 3058 3059 port@6 { 3060 reg = <6>; 3061 3062 funnel_swao_in6: endpoint { 3063 remote-endpoint = <&replicator1_out>; 3064 }; 3065 }; 3066 3067 port@7 { 3068 reg = <7>; 3069 3070 funnel_swao_in7: endpoint { 3071 remote-endpoint = <&tpda_swao_out>; 3072 }; 3073 }; 3074 }; 3075 3076 out-ports { 3077 port { 3078 funnel_swao_out: endpoint { 3079 remote-endpoint = <&tmc_etf_swao_in>; 3080 }; 3081 }; 3082 }; 3083 }; 3084 3085 tmc@6b09000 { 3086 compatible = "arm,coresight-tmc", "arm,primecell"; 3087 reg = <0x0 0x06b09000 0x0 0x1000>; 3088 3089 clocks = <&aoss_qmp>; 3090 clock-names = "apb_pclk"; 3091 3092 in-ports { 3093 port { 3094 tmc_etf_swao_in: endpoint { 3095 remote-endpoint = <&funnel_swao_out>; 3096 }; 3097 }; 3098 }; 3099 3100 out-ports { 3101 port { 3102 tmc_etf_swao_out: endpoint { 3103 remote-endpoint = <&replicator_swao_in>; 3104 }; 3105 }; 3106 }; 3107 }; 3108 3109 replicator@6b0a000 { 3110 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3111 reg = <0x0 0x06b0a000 0x0 0x1000>; 3112 3113 clocks = <&aoss_qmp>; 3114 clock-names = "apb_pclk"; 3115 3116 in-ports { 3117 port { 3118 replicator_swao_in: endpoint { 3119 remote-endpoint = <&tmc_etf_swao_out>; 3120 }; 3121 }; 3122 }; 3123 3124 out-ports { 3125 #address-cells = <1>; 3126 #size-cells = <0>; 3127 3128 port@0 { 3129 reg = <0>; 3130 3131 replicator_swao_out0: endpoint { 3132 remote-endpoint = <&funnel_in1_in3>; 3133 }; 3134 }; 3135 3136 port@1 { 3137 reg = <1>; 3138 3139 replicator_swao_out1: endpoint { 3140 remote-endpoint = <&eud_in>; 3141 }; 3142 }; 3143 }; 3144 }; 3145 3146 cti@6b21000 { 3147 compatible = "arm,coresight-cti", "arm,primecell"; 3148 reg = <0x0 0x06b21000 0x0 0x1000>; 3149 3150 clocks = <&aoss_qmp>; 3151 clock-names = "apb_pclk"; 3152 label = "cti_aop_m3"; 3153 }; 3154 3155 tpdm@6b48000 { 3156 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3157 reg = <0x0 0x06b48000 0x0 0x1000>; 3158 3159 clocks = <&aoss_qmp>; 3160 clock-names = "apb_pclk"; 3161 label = "tpdm_west"; 3162 3163 qcom,dsb-element-bits = <32>; 3164 qcom,dsb-msrs-num = <32>; 3165 3166 out-ports { 3167 port { 3168 tpdm_west_out: endpoint { 3169 remote-endpoint = <&tpda_qdss_in12>; 3170 }; 3171 }; 3172 }; 3173 }; 3174 3175 cti@6c13000 { 3176 compatible = "arm,coresight-cti", "arm,primecell"; 3177 reg = <0x0 0x06c13000 0x0 0x1000>; 3178 3179 clocks = <&aoss_qmp>; 3180 clock-names = "apb_pclk"; 3181 label = "cti_titan"; 3182 3183 /* Not all required clocks can be enabled from the OS */ 3184 status = "fail"; 3185 }; 3186 3187 cti@6c20000 { 3188 compatible = "arm,coresight-cti", "arm,primecell"; 3189 reg = <0x0 0x06c20000 0x0 0x1000>; 3190 3191 clocks = <&aoss_qmp>; 3192 clock-names = "apb_pclk"; 3193 label = "cti_venus"; 3194 status = "disabled"; 3195 }; 3196 3197 tpdm@6c28000 { 3198 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3199 reg = <0x0 0x06c28000 0x0 0x1000>; 3200 3201 clocks = <&aoss_qmp>; 3202 clock-names = "apb_pclk"; 3203 label = "tpdm_center"; 3204 3205 qcom,dsb-element-bits = <32>; 3206 qcom,dsb-msrs-num = <32>; 3207 3208 out-ports { 3209 port { 3210 tpdm_center_out: endpoint { 3211 remote-endpoint = <&tpda_qdss_in0>; 3212 }; 3213 }; 3214 }; 3215 }; 3216 3217 cti@6c29000 { 3218 compatible = "arm,coresight-cti", "arm,primecell"; 3219 reg = <0x0 0x06c29000 0x0 0x1000>; 3220 3221 clocks = <&aoss_qmp>; 3222 clock-names = "apb_pclk"; 3223 label = "cti_dlct"; 3224 }; 3225 3226 cti@6c2a000 { 3227 compatible = "arm,coresight-cti", "arm,primecell"; 3228 reg = <0x0 0x06c2a000 0x0 0x1000>; 3229 3230 clocks = <&aoss_qmp>; 3231 clock-names = "apb_pclk"; 3232 label = "cti_dlct_1"; 3233 }; 3234 3235 cti@7020000 { 3236 compatible = "arm,coresight-cti", "arm,primecell"; 3237 reg = <0x0 0x07020000 0x0 0x1000>; 3238 3239 clocks = <&aoss_qmp>; 3240 clock-names = "apb_pclk"; 3241 label = "cti_apss_apb_2"; 3242 }; 3243 3244 etm@7040000 { 3245 compatible = "arm,primecell"; 3246 reg = <0x0 0x07040000 0x0 0x1000>; 3247 cpu = <&cpu0>; 3248 3249 clocks = <&aoss_qmp>; 3250 clock-names = "apb_pclk"; 3251 3252 arm,coresight-loses-context-with-cpu; 3253 qcom,skip-power-up; 3254 3255 out-ports { 3256 port { 3257 etm0_out: endpoint { 3258 remote-endpoint = <&funnel_apss_in0>; 3259 }; 3260 }; 3261 }; 3262 }; 3263 3264 cti@7120000 { 3265 compatible = "arm,coresight-cti", "arm,primecell"; 3266 reg = <0x0 0x07120000 0x0 0x1000>; 3267 3268 clocks = <&aoss_qmp>; 3269 clock-names = "apb_pclk"; 3270 label = "cti_apss_apb_3"; 3271 }; 3272 3273 etm@7140000 { 3274 compatible = "arm,primecell"; 3275 reg = <0x0 0x07140000 0x0 0x1000>; 3276 cpu = <&cpu1>; 3277 3278 clocks = <&aoss_qmp>; 3279 clock-names = "apb_pclk"; 3280 3281 arm,coresight-loses-context-with-cpu; 3282 qcom,skip-power-up; 3283 3284 out-ports { 3285 port { 3286 etm1_out: endpoint { 3287 remote-endpoint = <&funnel_apss_in1>; 3288 }; 3289 }; 3290 }; 3291 }; 3292 3293 cti@7220000 { 3294 compatible = "arm,coresight-cti", "arm,primecell"; 3295 reg = <0x0 0x07220000 0x0 0x1000>; 3296 3297 clocks = <&aoss_qmp>; 3298 clock-names = "apb_pclk"; 3299 label = "cti_apss_apb_4"; 3300 }; 3301 3302 etm@7240000 { 3303 compatible = "arm,primecell"; 3304 reg = <0x0 0x07240000 0x0 0x1000>; 3305 cpu = <&cpu2>; 3306 3307 clocks = <&aoss_qmp>; 3308 clock-names = "apb_pclk"; 3309 3310 arm,coresight-loses-context-with-cpu; 3311 qcom,skip-power-up; 3312 3313 out-ports { 3314 port { 3315 etm2_out: endpoint { 3316 remote-endpoint = <&funnel_apss_in2>; 3317 }; 3318 }; 3319 }; 3320 }; 3321 3322 cti@7320000 { 3323 compatible = "arm,coresight-cti", "arm,primecell"; 3324 reg = <0x0 0x07320000 0x0 0x1000>; 3325 3326 clocks = <&aoss_qmp>; 3327 clock-names = "apb_pclk"; 3328 label = "cti_apss_apb_5"; 3329 }; 3330 3331 etm@7340000 { 3332 compatible = "arm,primecell"; 3333 reg = <0x0 0x07340000 0x0 0x1000>; 3334 cpu = <&cpu3>; 3335 3336 clocks = <&aoss_qmp>; 3337 clock-names = "apb_pclk"; 3338 3339 arm,coresight-loses-context-with-cpu; 3340 qcom,skip-power-up; 3341 3342 out-ports { 3343 port { 3344 etm3_out: endpoint { 3345 remote-endpoint = <&funnel_apss_in3>; 3346 }; 3347 }; 3348 }; 3349 }; 3350 3351 cti@7420000 { 3352 compatible = "arm,coresight-cti", "arm,primecell"; 3353 reg = <0x0 0x07420000 0x0 0x1000>; 3354 3355 clocks = <&aoss_qmp>; 3356 clock-names = "apb_pclk"; 3357 label = "cti_apss_apb_6"; 3358 }; 3359 3360 etm@7440000 { 3361 compatible = "arm,primecell"; 3362 reg = <0x0 0x07440000 0x0 0x1000>; 3363 cpu = <&cpu4>; 3364 3365 clocks = <&aoss_qmp>; 3366 clock-names = "apb_pclk"; 3367 3368 arm,coresight-loses-context-with-cpu; 3369 qcom,skip-power-up; 3370 3371 out-ports { 3372 port { 3373 etm4_out: endpoint { 3374 remote-endpoint = <&funnel_apss_in4>; 3375 }; 3376 }; 3377 }; 3378 }; 3379 3380 cti@7520000 { 3381 compatible = "arm,coresight-cti", "arm,primecell"; 3382 reg = <0x0 0x07520000 0x0 0x1000>; 3383 3384 clocks = <&aoss_qmp>; 3385 clock-names = "apb_pclk"; 3386 label = "cti_apss_apb_7"; 3387 }; 3388 3389 etm@7540000 { 3390 compatible = "arm,primecell"; 3391 reg = <0x0 0x07540000 0x0 0x1000>; 3392 cpu = <&cpu5>; 3393 3394 clocks = <&aoss_qmp>; 3395 clock-names = "apb_pclk"; 3396 3397 arm,coresight-loses-context-with-cpu; 3398 qcom,skip-power-up; 3399 3400 out-ports { 3401 port { 3402 etm5_out: endpoint { 3403 remote-endpoint = <&funnel_apss_in5>; 3404 }; 3405 }; 3406 }; 3407 }; 3408 3409 cti@7620000 { 3410 compatible = "arm,coresight-cti", "arm,primecell"; 3411 reg = <0x0 0x07620000 0x0 0x1000>; 3412 3413 clocks = <&aoss_qmp>; 3414 clock-names = "apb_pclk"; 3415 label = "cti_apss_apb_8"; 3416 }; 3417 3418 etm@7640000 { 3419 compatible = "arm,primecell"; 3420 reg = <0x0 0x07640000 0x0 0x1000>; 3421 cpu = <&cpu6>; 3422 3423 clocks = <&aoss_qmp>; 3424 clock-names = "apb_pclk"; 3425 3426 arm,coresight-loses-context-with-cpu; 3427 qcom,skip-power-up; 3428 3429 out-ports { 3430 port { 3431 etm6_out: endpoint { 3432 remote-endpoint = <&funnel_apss_in6>; 3433 }; 3434 }; 3435 }; 3436 }; 3437 3438 cti@7720000 { 3439 compatible = "arm,coresight-cti", "arm,primecell"; 3440 reg = <0x0 0x07720000 0x0 0x1000>; 3441 3442 clocks = <&aoss_qmp>; 3443 clock-names = "apb_pclk"; 3444 label = "cti_apss_apb_9"; 3445 }; 3446 3447 etm@7740000 { 3448 compatible = "arm,primecell"; 3449 reg = <0x0 0x07740000 0x0 0x1000>; 3450 cpu = <&cpu7>; 3451 3452 clocks = <&aoss_qmp>; 3453 clock-names = "apb_pclk"; 3454 3455 arm,coresight-loses-context-with-cpu; 3456 qcom,skip-power-up; 3457 3458 out-ports { 3459 port { 3460 etm7_out: endpoint { 3461 remote-endpoint = <&funnel_apss_in7>; 3462 }; 3463 }; 3464 }; 3465 }; 3466 3467 funnel@7800000 { 3468 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3469 reg = <0x0 0x07800000 0x0 0x1000>; 3470 3471 clocks = <&aoss_qmp>; 3472 clock-names = "apb_pclk"; 3473 3474 in-ports { 3475 #address-cells = <1>; 3476 #size-cells = <0>; 3477 3478 port@0 { 3479 reg = <0>; 3480 3481 funnel_apss_in0: endpoint { 3482 remote-endpoint = <&etm0_out>; 3483 }; 3484 }; 3485 3486 port@1 { 3487 reg = <1>; 3488 3489 funnel_apss_in1: endpoint { 3490 remote-endpoint = <&etm1_out>; 3491 }; 3492 }; 3493 3494 port@2 { 3495 reg = <2>; 3496 3497 funnel_apss_in2: endpoint { 3498 remote-endpoint = <&etm2_out>; 3499 }; 3500 }; 3501 3502 port@3 { 3503 reg = <3>; 3504 3505 funnel_apss_in3: endpoint { 3506 remote-endpoint = <&etm3_out>; 3507 }; 3508 }; 3509 3510 port@4 { 3511 reg = <4>; 3512 3513 funnel_apss_in4: endpoint { 3514 remote-endpoint = <&etm4_out>; 3515 }; 3516 }; 3517 3518 port@5 { 3519 reg = <5>; 3520 3521 funnel_apss_in5: endpoint { 3522 remote-endpoint = <&etm5_out>; 3523 }; 3524 }; 3525 3526 port@6 { 3527 reg = <6>; 3528 3529 funnel_apss_in6: endpoint { 3530 remote-endpoint = <&etm6_out>; 3531 }; 3532 }; 3533 3534 port@7 { 3535 reg = <7>; 3536 3537 funnel_apss_in7: endpoint { 3538 remote-endpoint = <&etm7_out>; 3539 }; 3540 }; 3541 }; 3542 3543 out-ports { 3544 port { 3545 funnel_apss_out: endpoint { 3546 remote-endpoint = <&funnel_apss_merg_in0>; 3547 }; 3548 }; 3549 }; 3550 }; 3551 3552 funnel@7810000 { 3553 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3554 reg = <0x0 0x07810000 0x0 0x1000>; 3555 3556 clocks = <&aoss_qmp>; 3557 clock-names = "apb_pclk"; 3558 3559 in-ports { 3560 #address-cells = <1>; 3561 #size-cells = <0>; 3562 3563 port@0 { 3564 reg = <0>; 3565 3566 funnel_apss_merg_in0: endpoint { 3567 remote-endpoint = <&funnel_apss_out>; 3568 }; 3569 }; 3570 3571 port@2 { 3572 reg = <2>; 3573 3574 funnel_apss_merg_in2: endpoint { 3575 remote-endpoint = <&tpda_olc_out>; 3576 }; 3577 }; 3578 3579 port@3 { 3580 reg = <3>; 3581 3582 funnel_apss_merg_in3: endpoint { 3583 remote-endpoint = <&tpda_llm_silver_out>; 3584 }; 3585 }; 3586 3587 port@4 { 3588 reg = <4>; 3589 3590 funnel_apss_merg_in4: endpoint { 3591 remote-endpoint = <&tpda_llm_gold_out>; 3592 }; 3593 }; 3594 3595 port@5 { 3596 reg = <5>; 3597 3598 funnel_apss_merg_in5: endpoint { 3599 remote-endpoint = <&tpda_apss_out>; 3600 }; 3601 }; 3602 }; 3603 3604 out-ports { 3605 port { 3606 funnel_apss_merg_out: endpoint { 3607 remote-endpoint = <&funnel_in1_in7>; 3608 }; 3609 }; 3610 }; 3611 }; 3612 3613 tpdm@7830000 { 3614 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3615 reg = <0x0 0x07830000 0x0 0x1000>; 3616 3617 clocks = <&aoss_qmp>; 3618 clock-names = "apb_pclk"; 3619 label = "tpdm_olc"; 3620 3621 qcom,cmb-element-bits = <64>; 3622 qcom,cmb-msrs-num = <32>; 3623 3624 out-ports { 3625 port { 3626 tpdm_olc_out: endpoint { 3627 remote-endpoint = <&tpda_olc_in>; 3628 }; 3629 }; 3630 }; 3631 }; 3632 3633 tpda@7832000 { 3634 compatible = "qcom,coresight-tpda", "arm,primecell"; 3635 reg = <0x0 0x07832000 0x0 0x1000>; 3636 3637 clocks = <&aoss_qmp>; 3638 clock-names = "apb_pclk"; 3639 3640 in-ports { 3641 port { 3642 tpda_olc_in: endpoint { 3643 remote-endpoint = <&tpdm_olc_out>; 3644 }; 3645 }; 3646 }; 3647 3648 out-ports { 3649 port { 3650 tpda_olc_out: endpoint { 3651 remote-endpoint = <&funnel_apss_merg_in2>; 3652 }; 3653 }; 3654 }; 3655 }; 3656 3657 tpdm@7860000 { 3658 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3659 reg = <0x0 0x07860000 0x0 0x1000>; 3660 3661 clocks = <&aoss_qmp>; 3662 clock-names = "apb_pclk"; 3663 label = "tpdm_apss"; 3664 3665 qcom,dsb-element-bits = <32>; 3666 qcom,dsb-msrs-num = <32>; 3667 3668 out-ports { 3669 port { 3670 tpdm_apss_out: endpoint { 3671 remote-endpoint = <&tpda_apss_in>; 3672 }; 3673 }; 3674 }; 3675 }; 3676 3677 tpda@7862000 { 3678 compatible = "qcom,coresight-tpda", "arm,primecell"; 3679 reg = <0x0 0x07862000 0x0 0x1000>; 3680 3681 clocks = <&aoss_qmp>; 3682 clock-names = "apb_pclk"; 3683 3684 in-ports { 3685 port { 3686 tpda_apss_in: endpoint { 3687 remote-endpoint = <&tpdm_apss_out>; 3688 }; 3689 }; 3690 }; 3691 3692 out-ports { 3693 port { 3694 tpda_apss_out: endpoint { 3695 remote-endpoint = <&funnel_apss_merg_in5>; 3696 }; 3697 }; 3698 }; 3699 }; 3700 3701 tpdm@78a0000 { 3702 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3703 reg = <0x0 0x078a0000 0x0 0x1000>; 3704 3705 clocks = <&aoss_qmp>; 3706 clock-names = "apb_pclk"; 3707 label = "tpdm_llm_silver"; 3708 3709 qcom,cmb-element-bits = <32>; 3710 qcom,cmb-msrs-num = <32>; 3711 3712 out-ports { 3713 port { 3714 tpdm_llm_silver_out: endpoint { 3715 remote-endpoint = <&tpda_llm_silver_in>; 3716 }; 3717 }; 3718 }; 3719 }; 3720 3721 tpdm@78b0000 { 3722 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3723 reg = <0x0 0x078b0000 0x0 0x1000>; 3724 3725 clocks = <&aoss_qmp>; 3726 clock-names = "apb_pclk"; 3727 label = "tpdm_llm_gold"; 3728 3729 qcom,cmb-element-bits = <32>; 3730 qcom,cmb-msrs-num = <32>; 3731 3732 out-ports { 3733 port { 3734 tpdm_llm_gold_out: endpoint { 3735 remote-endpoint = <&tpda_llm_gold_in>; 3736 }; 3737 }; 3738 }; 3739 }; 3740 3741 tpda@78c0000 { 3742 compatible = "qcom,coresight-tpda", "arm,primecell"; 3743 reg = <0x0 0x078c0000 0x0 0x1000>; 3744 3745 clocks = <&aoss_qmp>; 3746 clock-names = "apb_pclk"; 3747 3748 in-ports { 3749 port { 3750 tpda_llm_silver_in: endpoint { 3751 remote-endpoint = <&tpdm_llm_silver_out>; 3752 }; 3753 }; 3754 }; 3755 3756 out-ports { 3757 port { 3758 tpda_llm_silver_out: endpoint { 3759 remote-endpoint = <&funnel_apss_merg_in3>; 3760 }; 3761 }; 3762 }; 3763 }; 3764 3765 tpda@78d0000 { 3766 compatible = "qcom,coresight-tpda", "arm,primecell"; 3767 reg = <0x0 0x078d0000 0x0 0x1000>; 3768 3769 clocks = <&aoss_qmp>; 3770 clock-names = "apb_pclk"; 3771 3772 in-ports { 3773 port { 3774 tpda_llm_gold_in: endpoint { 3775 remote-endpoint = <&tpdm_llm_gold_out>; 3776 }; 3777 }; 3778 }; 3779 3780 out-ports { 3781 port { 3782 tpda_llm_gold_out: endpoint { 3783 remote-endpoint = <&funnel_apss_merg_in4>; 3784 }; 3785 }; 3786 }; 3787 }; 3788 3789 cti@78e0000 { 3790 compatible = "arm,coresight-cti", "arm,primecell"; 3791 reg = <0x0 0x078e0000 0x0 0x1000>; 3792 3793 clocks = <&aoss_qmp>; 3794 clock-names = "apb_pclk"; 3795 label = "cti_apss"; 3796 }; 3797 3798 cti@78f0000 { 3799 compatible = "arm,coresight-cti", "arm,primecell"; 3800 reg = <0x0 0x078f0000 0x0 0x1000>; 3801 3802 clocks = <&aoss_qmp>; 3803 clock-names = "apb_pclk"; 3804 label = "cti_apss_1"; 3805 }; 3806 3807 cti@7900000 { 3808 compatible = "arm,coresight-cti", "arm,primecell"; 3809 reg = <0x0 0x07900000 0x0 0x1000>; 3810 3811 clocks = <&aoss_qmp>; 3812 clock-names = "apb_pclk"; 3813 label = "cti_apss_2"; 3814 }; 3815 3816 remoteproc_cdsp: remoteproc@8300000 { 3817 compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas"; 3818 reg = <0x0 0x08300000 0x0 0x4040>; 3819 3820 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, 3821 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3822 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3823 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3824 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3825 interrupt-names = "wdog", 3826 "fatal", 3827 "ready", 3828 "handover", 3829 "stop-ack"; 3830 3831 clocks = <&rpmhcc RPMH_CXO_CLK>; 3832 clock-names = "xo"; 3833 3834 power-domains = <&rpmhpd RPMHPD_CX>; 3835 power-domain-names = "cx"; 3836 3837 memory-region = <&rproc_cdsp_mem>; 3838 3839 qcom,qmp = <&aoss_qmp>; 3840 3841 qcom,smem-states = <&cdsp_smp2p_out 0>; 3842 qcom,smem-state-names = "stop"; 3843 3844 status = "disabled"; 3845 3846 glink-edge { 3847 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING 0>; 3848 mboxes = <&apss_shared 4>; 3849 label = "cdsp"; 3850 qcom,remote-pid = <5>; 3851 3852 fastrpc { 3853 compatible = "qcom,fastrpc"; 3854 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3855 label = "cdsp"; 3856 #address-cells = <1>; 3857 #size-cells = <0>; 3858 3859 compute-cb@1 { 3860 compatible = "qcom,fastrpc-compute-cb"; 3861 reg = <1>; 3862 iommus = <&apps_smmu 0x1081 0x0>; 3863 dma-coherent; 3864 }; 3865 3866 compute-cb@2 { 3867 compatible = "qcom,fastrpc-compute-cb"; 3868 reg = <2>; 3869 iommus = <&apps_smmu 0x1082 0x0>; 3870 dma-coherent; 3871 }; 3872 3873 compute-cb@3 { 3874 compatible = "qcom,fastrpc-compute-cb"; 3875 reg = <3>; 3876 iommus = <&apps_smmu 0x1083 0x0>; 3877 dma-coherent; 3878 }; 3879 3880 compute-cb@4 { 3881 compatible = "qcom,fastrpc-compute-cb"; 3882 reg = <4>; 3883 iommus = <&apps_smmu 0x1084 0x0>; 3884 dma-coherent; 3885 }; 3886 3887 compute-cb@5 { 3888 compatible = "qcom,fastrpc-compute-cb"; 3889 reg = <5>; 3890 iommus = <&apps_smmu 0x1085 0x0>; 3891 dma-coherent; 3892 }; 3893 3894 compute-cb@6 { 3895 compatible = "qcom,fastrpc-compute-cb"; 3896 reg = <6>; 3897 iommus = <&apps_smmu 0x1086 0x0>; 3898 dma-coherent; 3899 }; 3900 }; 3901 }; 3902 }; 3903 3904 pmu@90b6300 { 3905 compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon"; 3906 reg = <0x0 0x090b6300 0x0 0x600>; 3907 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>; 3908 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3909 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3910 3911 operating-points-v2 = <&cpu_bwmon_opp_table>; 3912 3913 cpu_bwmon_opp_table: opp-table { 3914 compatible = "operating-points-v2"; 3915 3916 opp-0 { 3917 opp-peak-kBps = <12896000>; 3918 }; 3919 3920 opp-1 { 3921 opp-peak-kBps = <14928000>; 3922 }; 3923 }; 3924 }; 3925 3926 pmu@90cd000 { 3927 compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3928 reg = <0x0 0x090cd000 0x0 0x1000>; 3929 interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH 0>; 3930 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 3931 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3932 3933 operating-points-v2 = <&llcc_bwmon_opp_table>; 3934 3935 llcc_bwmon_opp_table: opp-table { 3936 compatible = "operating-points-v2"; 3937 3938 opp-0 { 3939 opp-peak-kBps = <800000>; 3940 }; 3941 3942 opp-1 { 3943 opp-peak-kBps = <1200000>; 3944 }; 3945 3946 opp-2 { 3947 opp-peak-kBps = <1804800>; 3948 }; 3949 3950 opp-3 { 3951 opp-peak-kBps = <2188800>; 3952 }; 3953 3954 opp-4 { 3955 opp-peak-kBps = <2726400>; 3956 }; 3957 3958 opp-5 { 3959 opp-peak-kBps = <3072000>; 3960 }; 3961 3962 opp-6 { 3963 opp-peak-kBps = <4070400>; 3964 }; 3965 3966 opp-7 { 3967 opp-peak-kBps = <5414400>; 3968 }; 3969 3970 opp-8 { 3971 opp-peak-kBps = <6220800>; 3972 }; 3973 }; 3974 }; 3975 3976 sdhc_2: mmc@8804000 { 3977 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 3978 reg = <0x0 0x08804000 0x0 0x1000>; 3979 reg-names = "hc"; 3980 3981 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>, 3982 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; 3983 interrupt-names = "hc_irq", 3984 "pwr_irq"; 3985 3986 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3987 <&gcc GCC_SDCC2_APPS_CLK>, 3988 <&rpmhcc RPMH_CXO_CLK>; 3989 clock-names = "iface", 3990 "core", 3991 "xo"; 3992 3993 power-domains = <&rpmhpd RPMHPD_CX>; 3994 operating-points-v2 = <&sdhc2_opp_table>; 3995 iommus = <&apps_smmu 0x02a0 0x0>; 3996 resets = <&gcc GCC_SDCC2_BCR>; 3997 interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3998 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3999 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4000 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4001 interconnect-names = "sdhc-ddr", 4002 "cpu-sdhc"; 4003 4004 qcom,dll-config = <0x0007642c>; 4005 qcom,ddr-config = <0x80040868>; 4006 dma-coherent; 4007 4008 status = "disabled"; 4009 4010 sdhc2_opp_table: opp-table { 4011 compatible = "operating-points-v2"; 4012 4013 opp-50000000 { 4014 opp-hz = /bits/ 64 <50000000>; 4015 required-opps = <&rpmhpd_opp_low_svs>; 4016 }; 4017 4018 opp-100000000 { 4019 opp-hz = /bits/ 64 <100000000>; 4020 required-opps = <&rpmhpd_opp_svs>; 4021 }; 4022 4023 opp-202000000 { 4024 opp-hz = /bits/ 64 <202000000>; 4025 required-opps = <&rpmhpd_opp_nom>; 4026 }; 4027 }; 4028 }; 4029 4030 qspi: spi@88df000 { 4031 compatible = "qcom,qcs615-qspi", 4032 "qcom,qspi-v1"; 4033 reg = <0x0 0x088df000 0x0 0x1000>; 4034 4035 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH 0>; 4036 4037 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 4038 <&gcc GCC_QSPI_CORE_CLK>; 4039 clock-names = "iface", 4040 "core"; 4041 4042 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4043 &config_noc SLAVE_QSPI QCOM_ICC_TAG_ACTIVE_ONLY>, 4044 <&aggre1_noc MASTER_QSPI QCOM_ICC_TAG_ALWAYS 4045 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4046 interconnect-names = "qspi-config", 4047 "qspi-memory"; 4048 4049 power-domains = <&rpmhpd RPMHPD_CX>; 4050 operating-points-v2 = <&qspi_opp_table>; 4051 4052 iommus = <&apps_smmu 0x160 0x0>; 4053 4054 pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0123>; 4055 pinctrl-names = "default"; 4056 4057 #address-cells = <1>; 4058 #size-cells = <0>; 4059 4060 status = "disabled"; 4061 }; 4062 4063 dc_noc: interconnect@9160000 { 4064 reg = <0x0 0x09160000 0x0 0x3200>; 4065 compatible = "qcom,qcs615-dc-noc"; 4066 #interconnect-cells = <2>; 4067 qcom,bcm-voters = <&apps_bcm_voter>; 4068 }; 4069 4070 llcc: system-cache-controller@9200000 { 4071 compatible = "qcom,qcs615-llcc"; 4072 reg = <0x0 0x09200000 0x0 0x50000>, 4073 <0x0 0x09600000 0x0 0x50000>; 4074 reg-names = "llcc0_base", 4075 "llcc_broadcast_base"; 4076 }; 4077 4078 gem_noc: interconnect@9680000 { 4079 reg = <0x0 0x09680000 0x0 0x3e200>; 4080 compatible = "qcom,qcs615-gem-noc"; 4081 #interconnect-cells = <2>; 4082 qcom,bcm-voters = <&apps_bcm_voter>; 4083 }; 4084 4085 venus: video-codec@aa00000 { 4086 compatible = "qcom,qcs615-venus", "qcom,sc7180-venus"; 4087 reg = <0x0 0x0aa00000 0x0 0x100000>; 4088 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; 4089 4090 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 4091 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4092 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 4093 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 4094 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 4095 clock-names = "core", 4096 "iface", 4097 "bus", 4098 "vcodec0_core", 4099 "vcodec0_bus"; 4100 4101 power-domains = <&videocc VENUS_GDSC>, 4102 <&videocc VCODEC0_GDSC>, 4103 <&rpmhpd RPMHPD_CX>; 4104 power-domain-names = "venus", 4105 "vcodec0", 4106 "cx"; 4107 4108 operating-points-v2 = <&venus_opp_table>; 4109 4110 interconnects = <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 4111 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4112 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4113 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4114 interconnect-names = "video-mem", 4115 "cpu-cfg"; 4116 4117 iommus = <&apps_smmu 0xe60 0x20>; 4118 4119 memory-region = <&pil_video_mem>; 4120 4121 status = "disabled"; 4122 4123 venus_opp_table: opp-table { 4124 compatible = "operating-points-v2"; 4125 4126 opp-133330000 { 4127 opp-hz = /bits/ 64 <133330000>; 4128 required-opps = <&rpmhpd_opp_low_svs>; 4129 }; 4130 4131 opp-240000000 { 4132 opp-hz = /bits/ 64 <240000000>; 4133 required-opps = <&rpmhpd_opp_svs>; 4134 }; 4135 4136 opp-300000000 { 4137 opp-hz = /bits/ 64 <300000000>; 4138 required-opps = <&rpmhpd_opp_svs_l1>; 4139 }; 4140 4141 opp-380000000 { 4142 opp-hz = /bits/ 64 <380000000>; 4143 required-opps = <&rpmhpd_opp_nom>; 4144 }; 4145 4146 opp-410000000 { 4147 opp-hz = /bits/ 64 <410000000>; 4148 required-opps = <&rpmhpd_opp_nom_l1>; 4149 }; 4150 4151 opp-460000000 { 4152 opp-hz = /bits/ 64 <460000000>; 4153 required-opps = <&rpmhpd_opp_turbo>; 4154 }; 4155 }; 4156 }; 4157 4158 videocc: clock-controller@ab00000 { 4159 compatible = "qcom,qcs615-videocc"; 4160 reg = <0 0x0ab00000 0 0x10000>; 4161 4162 clocks = <&rpmhcc RPMH_CXO_CLK>, 4163 <&sleep_clk>; 4164 4165 #clock-cells = <1>; 4166 #reset-cells = <1>; 4167 #power-domain-cells = <1>; 4168 }; 4169 4170 cci: cci@ac4a000 { 4171 compatible = "qcom,sm6150-cci", "qcom,msm8996-cci"; 4172 4173 reg = <0x0 0x0ac4a000 0x0 0x4000>; 4174 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING 0>; 4175 power-domains = <&camcc TITAN_TOP_GDSC>; 4176 clocks = <&camcc CAM_CC_SOC_AHB_CLK>, 4177 <&camcc CAM_CC_CPAS_AHB_CLK>, 4178 <&camcc CAM_CC_CCI_CLK>; 4179 clock-names = "camnoc_axi", 4180 "cpas_ahb", 4181 "cci"; 4182 pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>; 4183 pinctrl-names = "default"; 4184 4185 #address-cells = <1>; 4186 #size-cells = <0>; 4187 4188 status = "disabled"; 4189 4190 cci_i2c0: i2c-bus@0 { 4191 reg = <0>; 4192 clock-frequency = <1000000>; 4193 #address-cells = <1>; 4194 #size-cells = <0>; 4195 }; 4196 4197 cci_i2c1: i2c-bus@1 { 4198 reg = <1>; 4199 clock-frequency = <1000000>; 4200 #address-cells = <1>; 4201 #size-cells = <0>; 4202 }; 4203 }; 4204 4205 camss: isp@acb3000 { 4206 compatible = "qcom,sm6150-camss"; 4207 4208 reg = <0x0 0x0acb3000 0x0 0x1000>, 4209 <0x0 0x0acba000 0x0 0x1000>, 4210 <0x0 0x0acc8000 0x0 0x1000>, 4211 <0x0 0x0ac65000 0x0 0x1000>, 4212 <0x0 0x0ac66000 0x0 0x1000>, 4213 <0x0 0x0ac67000 0x0 0x1000>, 4214 <0x0 0x0acaf000 0x0 0x4000>, 4215 <0x0 0x0acb6000 0x0 0x4000>, 4216 <0x0 0x0acc4000 0x0 0x4000>, 4217 <0x0 0x0ac6f000 0x0 0x3000>, 4218 <0x0 0x0ac42000 0x0 0x5000>, 4219 <0x0 0x0ac48000 0x0 0x1000>, 4220 <0x0 0x0ac40000 0x0 0x1000>, 4221 <0x0 0x0ac18000 0x0 0x3000>, 4222 <0x0 0x0ac00000 0x0 0x6000>, 4223 <0x0 0x0ac10000 0x0 0x8000>, 4224 <0x0 0x0ac87000 0x0 0x3000>, 4225 <0x0 0x0ac52000 0x0 0x4000>, 4226 <0x0 0x0ac4e000 0x0 0x4000>, 4227 <0x0 0x0ac6b000 0x0 0x0a00>; 4228 reg-names = "csid0", 4229 "csid1", 4230 "csid_lite", 4231 "csiphy0", 4232 "csiphy1", 4233 "csiphy2", 4234 "vfe0", 4235 "vfe1", 4236 "vfe_lite", 4237 "bps", 4238 "camnoc", 4239 "cpas_cdm", 4240 "cpas_top", 4241 "icp_csr", 4242 "icp_qgic", 4243 "icp_sierra", 4244 "ipe0", 4245 "jpeg_dma", 4246 "jpeg_enc", 4247 "lrme"; 4248 4249 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4250 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4251 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4252 <&camcc CAM_CC_CPAS_AHB_CLK>, 4253 <&camcc CAM_CC_CSIPHY0_CLK>, 4254 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4255 <&camcc CAM_CC_CSIPHY1_CLK>, 4256 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4257 <&camcc CAM_CC_CSIPHY2_CLK>, 4258 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4259 <&camcc CAM_CC_SOC_AHB_CLK>, 4260 <&camcc CAM_CC_IFE_0_CLK>, 4261 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4262 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4263 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4264 <&camcc CAM_CC_IFE_1_CLK>, 4265 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4266 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4267 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4268 <&camcc CAM_CC_IFE_LITE_CLK>, 4269 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4270 <&camcc CAM_CC_IFE_LITE_CSID_CLK>, 4271 <&camcc CAM_CC_BPS_CLK>, 4272 <&camcc CAM_CC_BPS_AHB_CLK>, 4273 <&camcc CAM_CC_BPS_AXI_CLK>, 4274 <&camcc CAM_CC_BPS_AREG_CLK>, 4275 <&camcc CAM_CC_ICP_CLK>, 4276 <&camcc CAM_CC_IPE_0_CLK>, 4277 <&camcc CAM_CC_IPE_0_AHB_CLK>, 4278 <&camcc CAM_CC_IPE_0_AREG_CLK>, 4279 <&camcc CAM_CC_IPE_0_AXI_CLK>, 4280 <&camcc CAM_CC_JPEG_CLK>, 4281 <&camcc CAM_CC_LRME_CLK>; 4282 clock-names = "gcc_ahb", 4283 "gcc_axi_hf", 4284 "camnoc_axi", 4285 "cpas_ahb", 4286 "csiphy0", 4287 "csiphy0_timer", 4288 "csiphy1", 4289 "csiphy1_timer", 4290 "csiphy2", 4291 "csiphy2_timer", 4292 "soc_ahb", 4293 "vfe0", 4294 "vfe0_axi", 4295 "vfe0_cphy_rx", 4296 "vfe0_csid", 4297 "vfe1", 4298 "vfe1_axi", 4299 "vfe1_cphy_rx", 4300 "vfe1_csid", 4301 "vfe_lite", 4302 "vfe_lite_cphy_rx", 4303 "vfe_lite_csid", 4304 "bps", 4305 "bps_ahb", 4306 "bps_axi", 4307 "bps_areg", 4308 "icp", 4309 "ipe0", 4310 "ipe0_ahb", 4311 "ipe0_areg", 4312 "ipe0_axi", 4313 "jpeg", 4314 "lrme"; 4315 4316 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4317 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4318 <&mmss_noc MASTER_CAMNOC_HF0 QCOM_ICC_TAG_ALWAYS 4319 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4320 <&mmss_noc MASTER_CAMNOC_HF1 QCOM_ICC_TAG_ALWAYS 4321 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4322 <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS 4323 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4324 interconnect-names = "ahb", 4325 "hf_0", 4326 "hf_1", 4327 "sf_mnoc"; 4328 4329 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING 0>, 4330 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING 0>, 4331 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING 0>, 4332 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>, 4333 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>, 4334 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>, 4335 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING 0>, 4336 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING 0>, 4337 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING 0>, 4338 <GIC_SPI 459 IRQ_TYPE_EDGE_RISING 0>, 4339 <GIC_SPI 461 IRQ_TYPE_EDGE_RISING 0>, 4340 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING 0>, 4341 <GIC_SPI 475 IRQ_TYPE_EDGE_RISING 0>, 4342 <GIC_SPI 474 IRQ_TYPE_EDGE_RISING 0>, 4343 <GIC_SPI 476 IRQ_TYPE_EDGE_RISING 0>; 4344 interrupt-names = "csid0", 4345 "csid1", 4346 "csid_lite", 4347 "csiphy0", 4348 "csiphy1", 4349 "csiphy2", 4350 "vfe0", 4351 "vfe1", 4352 "vfe_lite", 4353 "camnoc", 4354 "cdm", 4355 "icp", 4356 "jpeg_dma", 4357 "jpeg_enc", 4358 "lrme"; 4359 4360 iommus = <&apps_smmu 0x0820 0x40>, 4361 <&apps_smmu 0x0840 0x00>, 4362 <&apps_smmu 0x0860 0x40>, 4363 <&apps_smmu 0x0c00 0x00>, 4364 <&apps_smmu 0x0cc0 0x00>, 4365 <&apps_smmu 0x0c80 0x00>, 4366 <&apps_smmu 0x0ca0 0x00>, 4367 <&apps_smmu 0x0d00 0x00>, 4368 <&apps_smmu 0x0d20 0x00>, 4369 <&apps_smmu 0x0d40 0x00>, 4370 <&apps_smmu 0x0d80 0x20>, 4371 <&apps_smmu 0x0da0 0x20>, 4372 <&apps_smmu 0x0de2 0x00>; 4373 4374 power-domains = <&camcc IFE_0_GDSC>, 4375 <&camcc IFE_1_GDSC>, 4376 <&camcc TITAN_TOP_GDSC>, 4377 <&camcc BPS_GDSC>, 4378 <&camcc IPE_0_GDSC>; 4379 power-domain-names = "ife0", 4380 "ife1", 4381 "top", 4382 "bps", 4383 "ipe"; 4384 4385 status = "disabled"; 4386 4387 ports { 4388 #address-cells = <1>; 4389 #size-cells = <0>; 4390 4391 port@0 { 4392 reg = <0>; 4393 }; 4394 4395 port@1 { 4396 reg = <1>; 4397 }; 4398 4399 port@2 { 4400 reg = <2>; 4401 }; 4402 }; 4403 }; 4404 4405 camcc: clock-controller@ad00000 { 4406 compatible = "qcom,qcs615-camcc"; 4407 reg = <0 0x0ad00000 0 0x10000>; 4408 4409 clocks = <&rpmhcc RPMH_CXO_CLK>; 4410 4411 #clock-cells = <1>; 4412 #reset-cells = <1>; 4413 #power-domain-cells = <1>; 4414 }; 4415 4416 mdss: display-subsystem@ae00000 { 4417 compatible = "qcom,sm6150-mdss"; 4418 reg = <0x0 0x0ae00000 0x0 0x1000>; 4419 reg-names = "mdss"; 4420 4421 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 4422 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4423 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4424 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4425 interconnect-names = "mdp0-mem", 4426 "cpu-cfg"; 4427 4428 power-domains = <&dispcc MDSS_CORE_GDSC>; 4429 4430 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4431 <&gcc GCC_DISP_HF_AXI_CLK>, 4432 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4433 4434 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>; 4435 interrupt-controller; 4436 #interrupt-cells = <1>; 4437 4438 iommus = <&apps_smmu 0x800 0x0>; 4439 4440 #address-cells = <2>; 4441 #size-cells = <2>; 4442 ranges; 4443 4444 status = "disabled"; 4445 4446 mdss_mdp: display-controller@ae01000 { 4447 compatible = "qcom,sm6150-dpu"; 4448 reg = <0x0 0x0ae01000 0x0 0x8f000>, 4449 <0x0 0x0aeb0000 0x0 0x2008>; 4450 reg-names = "mdp", 4451 "vbif"; 4452 4453 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4454 <&gcc GCC_DISP_HF_AXI_CLK>, 4455 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4456 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4457 clock-names = "iface", 4458 "bus", 4459 "core", 4460 "vsync"; 4461 4462 operating-points-v2 = <&mdp_opp_table>; 4463 power-domains = <&rpmhpd RPMHPD_CX>; 4464 4465 interrupts-extended = <&mdss 0>; 4466 4467 ports { 4468 #address-cells = <1>; 4469 #size-cells = <0>; 4470 4471 port@0 { 4472 reg = <0>; 4473 4474 dpu_intf0_out: endpoint { 4475 remote-endpoint = <&mdss_dp0_in>; 4476 }; 4477 }; 4478 4479 port@1 { 4480 reg = <1>; 4481 4482 dpu_intf1_out: endpoint { 4483 remote-endpoint = <&mdss_dsi0_in>; 4484 }; 4485 }; 4486 }; 4487 4488 mdp_opp_table: opp-table { 4489 compatible = "operating-points-v2"; 4490 4491 opp-192000000 { 4492 opp-hz = /bits/ 64 <192000000>; 4493 required-opps = <&rpmhpd_opp_low_svs>; 4494 }; 4495 4496 opp-256000000 { 4497 opp-hz = /bits/ 64 <256000000>; 4498 required-opps = <&rpmhpd_opp_svs>; 4499 }; 4500 4501 opp-307200000 { 4502 opp-hz = /bits/ 64 <307200000>; 4503 required-opps = <&rpmhpd_opp_nom>; 4504 }; 4505 }; 4506 }; 4507 4508 mdss_dp0: displayport-controller@ae90000 { 4509 compatible = "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp"; 4510 4511 reg = <0x0 0x0ae90000 0x0 0x200>, 4512 <0x0 0x0ae90200 0x0 0x200>, 4513 <0x0 0x0ae90400 0x0 0x600>, 4514 <0x0 0x0ae90a00 0x0 0x600>, 4515 <0x0 0x0ae91000 0x0 0x600>; 4516 4517 interrupt-parent = <&mdss>; 4518 interrupts = <12>; 4519 4520 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4521 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4522 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4523 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4524 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, 4525 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; 4526 clock-names = "core_iface", 4527 "core_aux", 4528 "ctrl_link", 4529 "ctrl_link_iface", 4530 "stream_pixel", 4531 "stream_1_pixel"; 4532 4533 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4534 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, 4535 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; 4536 assigned-clock-parents = <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, 4537 <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>, 4538 <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; 4539 4540 phys = <&usb_qmpphy_2 QMP_USB43DP_DP_PHY>; 4541 phy-names = "dp"; 4542 4543 operating-points-v2 = <&dp_opp_table>; 4544 power-domains = <&rpmhpd RPMHPD_CX>; 4545 4546 #sound-dai-cells = <0>; 4547 4548 status = "disabled"; 4549 4550 ports { 4551 #address-cells = <1>; 4552 #size-cells = <0>; 4553 4554 port@0 { 4555 reg = <0>; 4556 4557 mdss_dp0_in: endpoint { 4558 remote-endpoint = <&dpu_intf0_out>; 4559 }; 4560 }; 4561 4562 port@1 { 4563 reg = <1>; 4564 4565 mdss_dp0_out: endpoint { 4566 data-lanes = <3 2 0 1>; 4567 }; 4568 }; 4569 }; 4570 4571 dp_opp_table: opp-table { 4572 compatible = "operating-points-v2"; 4573 4574 opp-162000000 { 4575 opp-hz = /bits/ 64 <162000000>; 4576 required-opps = <&rpmhpd_opp_low_svs>; 4577 }; 4578 4579 opp-270000000 { 4580 opp-hz = /bits/ 64 <270000000>; 4581 required-opps = <&rpmhpd_opp_svs>; 4582 }; 4583 4584 opp-540000000 { 4585 opp-hz = /bits/ 64 <540000000>; 4586 required-opps = <&rpmhpd_opp_svs_l1>; 4587 }; 4588 }; 4589 }; 4590 4591 mdss_dsi0: dsi@ae94000 { 4592 compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 4593 reg = <0x0 0x0ae94000 0x0 0x400>; 4594 reg-names = "dsi_ctrl"; 4595 4596 interrupts-extended = <&mdss 4>; 4597 4598 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4599 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4600 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4601 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4602 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4603 <&gcc GCC_DISP_HF_AXI_CLK>; 4604 clock-names = "byte", 4605 "byte_intf", 4606 "pixel", 4607 "core", 4608 "iface", 4609 "bus"; 4610 4611 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 4612 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4613 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4614 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 4615 4616 operating-points-v2 = <&dsi0_opp_table>; 4617 power-domains = <&rpmhpd RPMHPD_CX>; 4618 4619 phys = <&mdss_dsi0_phy>; 4620 4621 #address-cells = <1>; 4622 #size-cells = <0>; 4623 4624 status = "disabled"; 4625 4626 dsi0_opp_table: opp-table { 4627 compatible = "operating-points-v2"; 4628 4629 opp-164000000 { 4630 opp-hz = /bits/ 64 <164000000>; 4631 required-opps = <&rpmhpd_opp_low_svs>; 4632 }; 4633 }; 4634 4635 ports { 4636 #address-cells = <1>; 4637 #size-cells = <0>; 4638 4639 port@0 { 4640 reg = <0>; 4641 4642 mdss_dsi0_in: endpoint { 4643 remote-endpoint = <&dpu_intf1_out>; 4644 }; 4645 }; 4646 4647 port@1 { 4648 reg = <1>; 4649 4650 mdss_dsi0_out: endpoint { 4651 }; 4652 }; 4653 }; 4654 }; 4655 4656 mdss_dsi0_phy: phy@ae94400 { 4657 compatible = "qcom,sm6150-dsi-phy-14nm"; 4658 reg = <0x0 0x0ae94400 0x0 0x100>, 4659 <0x0 0x0ae94500 0x0 0x300>, 4660 <0x0 0x0ae94800 0x0 0x124>; 4661 reg-names = "dsi_phy", 4662 "dsi_phy_lane", 4663 "dsi_pll"; 4664 4665 #clock-cells = <1>; 4666 #phy-cells = <0>; 4667 4668 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4669 <&rpmhcc RPMH_CXO_CLK>; 4670 clock-names = "iface", 4671 "ref"; 4672 4673 status = "disabled"; 4674 }; 4675 }; 4676 4677 dispcc: clock-controller@af00000 { 4678 compatible = "qcom,qcs615-dispcc"; 4679 reg = <0 0x0af00000 0 0x20000>; 4680 4681 clocks = <&rpmhcc RPMH_CXO_CLK>, 4682 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 4683 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4684 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 4685 <0>, 4686 <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, 4687 <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; 4688 4689 #clock-cells = <1>; 4690 #reset-cells = <1>; 4691 #power-domain-cells = <1>; 4692 }; 4693 4694 pdc: interrupt-controller@b220000 { 4695 compatible = "qcom,qcs615-pdc", "qcom,pdc"; 4696 reg = <0x0 0x0b220000 0x0 0x10000>, 4697 <0x0 0x17c000f0 0x0 0x64>; 4698 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 4699 interrupt-parent = <&intc>; 4700 #interrupt-cells = <2>; 4701 interrupt-controller; 4702 }; 4703 4704 aoss_qmp: power-management@c300000 { 4705 compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp"; 4706 reg = <0x0 0x0c300000 0x0 0x400>; 4707 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING 0>; 4708 mboxes = <&apss_shared 0>; 4709 4710 #clock-cells = <0>; 4711 }; 4712 4713 sram@c3f0000 { 4714 compatible = "qcom,rpmh-stats"; 4715 reg = <0x0 0x0c3f0000 0x0 0x400>; 4716 }; 4717 4718 sram@14680000 { 4719 compatible = "qcom,qcs615-imem", "syscon", "simple-mfd"; 4720 reg = <0x0 0x14680000 0x0 0x2c000>; 4721 ranges = <0 0 0x14680000 0x2c000>; 4722 4723 #address-cells = <1>; 4724 #size-cells = <1>; 4725 4726 minidump_config: minidump-sram@1c { 4727 reg = <0x1c 0x4>; 4728 }; 4729 4730 pil-reloc@2a94c { 4731 compatible = "qcom,pil-reloc-info"; 4732 reg = <0x2a94c 0xc8>; 4733 }; 4734 }; 4735 4736 apps_smmu: iommu@15000000 { 4737 compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4738 reg = <0x0 0x15000000 0x0 0x80000>; 4739 #iommu-cells = <2>; 4740 #global-interrupts = <1>; 4741 dma-coherent; 4742 4743 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, 4744 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>, 4745 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>, 4746 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>, 4747 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, 4748 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, 4749 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, 4750 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, 4751 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 4752 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, 4753 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 4754 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 4755 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, 4756 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, 4757 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 4758 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 4759 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 4760 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, 4761 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, 4762 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, 4763 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, 4764 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 4765 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, 4766 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, 4767 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, 4768 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, 4769 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, 4770 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, 4771 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, 4772 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, 4773 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, 4774 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, 4775 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, 4776 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, 4777 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, 4778 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, 4779 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, 4780 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, 4781 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, 4782 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, 4783 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, 4784 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, 4785 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, 4786 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, 4787 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, 4788 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, 4789 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, 4790 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, 4791 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, 4792 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, 4793 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, 4794 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, 4795 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, 4796 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, 4797 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, 4798 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, 4799 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, 4800 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, 4801 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, 4802 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, 4803 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, 4804 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, 4805 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, 4806 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, 4807 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 4808 }; 4809 4810 spmi_bus: spmi@c440000 { 4811 compatible = "qcom,spmi-pmic-arb"; 4812 reg = <0x0 0x0c440000 0x0 0x1100>, 4813 <0x0 0x0c600000 0x0 0x2000000>, 4814 <0x0 0x0e600000 0x0 0x100000>, 4815 <0x0 0x0e700000 0x0 0xa0000>, 4816 <0x0 0x0c40a000 0x0 0x26000>; 4817 reg-names = "core", 4818 "chnls", 4819 "obsrvr", 4820 "intr", 4821 "cnfg"; 4822 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4823 interrupt-names = "periph_irq"; 4824 interrupt-controller; 4825 #interrupt-cells = <4>; 4826 #address-cells = <2>; 4827 #size-cells = <0>; 4828 qcom,channel = <0>; 4829 qcom,ee = <0>; 4830 }; 4831 4832 intc: interrupt-controller@17a00000 { 4833 compatible = "arm,gic-v3"; 4834 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4835 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4836 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 4837 #address-cells = <0>; 4838 #interrupt-cells = <4>; 4839 interrupt-controller; 4840 #redistributor-regions = <1>; 4841 redistributor-stride = <0x0 0x20000>; 4842 4843 ppi-partitions { 4844 ppi_cluster0: interrupt-partition-0 { 4845 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 4846 }; 4847 4848 ppi_cluster1: interrupt-partition-1 { 4849 affinity = <&cpu6 &cpu7>; 4850 }; 4851 }; 4852 }; 4853 4854 apss_shared: mailbox@17c00000 { 4855 compatible = "qcom,qcs615-apss-shared", 4856 "qcom,sdm845-apss-shared"; 4857 reg = <0x0 0x17c00000 0x0 0x1000>; 4858 #mbox-cells = <1>; 4859 }; 4860 4861 watchdog: watchdog@17c10000 { 4862 compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt"; 4863 reg = <0x0 0x17c10000 0x0 0x1000>; 4864 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>; 4865 clocks = <&sleep_clk>; 4866 }; 4867 4868 timer@17c20000 { 4869 compatible = "arm,armv7-timer-mem"; 4870 reg = <0x0 0x17c20000 0x0 0x1000>; 4871 ranges = <0 0 0 0x20000000>; 4872 #address-cells = <1>; 4873 #size-cells = <1>; 4874 4875 frame@17c21000 { 4876 reg = <0x17c21000 0x1000>, 4877 <0x17c22000 0x1000>; 4878 frame-number = <0>; 4879 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, 4880 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 4881 }; 4882 4883 frame@17c23000 { 4884 reg = <0x17c23000 0x1000>; 4885 frame-number = <1>; 4886 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 4887 status = "disabled"; 4888 }; 4889 4890 frame@17c25000 { 4891 reg = <0x17c25000 0x1000>; 4892 frame-number = <2>; 4893 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 4894 status = "disabled"; 4895 }; 4896 4897 frame@17c27000 { 4898 reg = <0x17c27000 0x1000>; 4899 frame-number = <3>; 4900 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 4901 status = "disabled"; 4902 }; 4903 4904 frame@17c29000 { 4905 reg = <0x17c29000 0x1000>; 4906 frame-number = <4>; 4907 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 4908 status = "disabled"; 4909 }; 4910 4911 frame@17c2b000 { 4912 reg = <0x17c2b000 0x1000>; 4913 frame-number = <5>; 4914 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; 4915 status = "disabled"; 4916 }; 4917 4918 frame@17c2d000 { 4919 reg = <0x17c2d000 0x1000>; 4920 frame-number = <6>; 4921 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 4922 status = "disabled"; 4923 }; 4924 }; 4925 4926 apps_rsc: rsc@18200000 { 4927 compatible = "qcom,rpmh-rsc"; 4928 reg = <0x0 0x18200000 0x0 0x10000>, 4929 <0x0 0x18210000 0x0 0x10000>, 4930 <0x0 0x18220000 0x0 0x10000>; 4931 reg-names = "drv-0", 4932 "drv-1", 4933 "drv-2"; 4934 4935 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, 4936 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, 4937 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; 4938 4939 qcom,drv-id = <2>; 4940 qcom,tcs-offset = <0xd00>; 4941 qcom,tcs-config = <ACTIVE_TCS 2>, 4942 <SLEEP_TCS 3>, 4943 <WAKE_TCS 3>, 4944 <CONTROL_TCS 1>; 4945 4946 label = "apps_rsc"; 4947 power-domains = <&cluster_pd>; 4948 4949 apps_bcm_voter: bcm-voter { 4950 compatible = "qcom,bcm-voter"; 4951 }; 4952 4953 rpmhcc: clock-controller { 4954 compatible = "qcom,qcs615-rpmh-clk"; 4955 clocks = <&xo_board_clk>; 4956 clock-names = "xo"; 4957 4958 #clock-cells = <1>; 4959 }; 4960 4961 rpmhpd: power-controller { 4962 compatible = "qcom,qcs615-rpmhpd"; 4963 #power-domain-cells = <1>; 4964 operating-points-v2 = <&rpmhpd_opp_table>; 4965 4966 rpmhpd_opp_table: opp-table { 4967 compatible = "operating-points-v2"; 4968 4969 rpmhpd_opp_ret: opp-0 { 4970 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4971 }; 4972 4973 rpmhpd_opp_min_svs: opp-1 { 4974 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4975 }; 4976 4977 rpmhpd_opp_low_svs: opp-2 { 4978 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4979 }; 4980 4981 rpmhpd_opp_svs: opp-3 { 4982 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4983 }; 4984 4985 rpmhpd_opp_svs_l1: opp-4 { 4986 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4987 }; 4988 4989 rpmhpd_opp_nom: opp-5 { 4990 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4991 }; 4992 4993 rpmhpd_opp_nom_l1: opp-6 { 4994 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4995 }; 4996 4997 rpmhpd_opp_nom_l2: opp-7 { 4998 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4999 }; 5000 5001 rpmhpd_opp_turbo: opp-8 { 5002 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5003 }; 5004 5005 rpmhpd_opp_turbo_l1: opp-9 { 5006 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5007 }; 5008 }; 5009 }; 5010 }; 5011 5012 osm_l3: interconnect@18321000 { 5013 compatible = "qcom,qcs615-osm-l3", "qcom,sm8150-osm-l3", "qcom,osm-l3"; 5014 reg = <0x0 0x18321000 0x0 0x1400>; 5015 5016 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5017 clock-names = "xo", "alternate"; 5018 5019 #interconnect-cells = <1>; 5020 }; 5021 5022 usb_1_hsphy: phy@88e2000 { 5023 compatible = "qcom,qcs615-qusb2-phy"; 5024 reg = <0x0 0x88e2000 0x0 0x180>; 5025 5026 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>; 5027 clock-names = "cfg_ahb", "ref"; 5028 5029 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 5030 nvmem-cells = <&qusb2_hstx_trim>; 5031 5032 #phy-cells = <0>; 5033 5034 status = "disabled"; 5035 }; 5036 5037 usb_2_hsphy: phy@88e3000 { 5038 compatible = "qcom,qcs615-qusb2-phy"; 5039 reg = <0x0 0x088e3000 0x0 0x180>; 5040 5041 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, 5042 <&rpmhcc RPMH_CXO_CLK>; 5043 clock-names = "cfg_ahb", 5044 "ref"; 5045 5046 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 5047 5048 #phy-cells = <0>; 5049 5050 status = "disabled"; 5051 }; 5052 5053 usb_qmpphy: phy@88e6000 { 5054 compatible = "qcom,qcs615-qmp-usb3-phy"; 5055 reg = <0x0 0x88e6000 0x0 0x1000>; 5056 5057 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 5058 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 5059 <&gcc GCC_AHB2PHY_WEST_CLK>, 5060 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 5061 clock-names = "aux", 5062 "ref", 5063 "cfg_ahb", 5064 "pipe"; 5065 5066 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 5067 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 5068 reset-names = "phy", "phy_phy"; 5069 5070 qcom,tcsr-reg = <&tcsr 0xb244>; 5071 5072 clock-output-names = "usb3_phy_pipe_clk_src"; 5073 #clock-cells = <0>; 5074 5075 #phy-cells = <0>; 5076 5077 status = "disabled"; 5078 }; 5079 5080 usb_qmpphy_2: phy@88e8000 { 5081 compatible = "qcom,qcs615-qmp-usb3-dp-phy"; 5082 reg = <0x0 0x088e8000 0x0 0x2000>; 5083 5084 clocks = <&gcc GCC_USB2_SEC_PHY_AUX_CLK>, 5085 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 5086 <&gcc GCC_AHB2PHY_WEST_CLK>, 5087 <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>; 5088 clock-names = "aux", 5089 "ref", 5090 "cfg_ahb", 5091 "pipe"; 5092 5093 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >, 5094 <&gcc GCC_USB3_DP_PHY_SEC_BCR>; 5095 reset-names = "phy_phy", 5096 "dp_phy"; 5097 5098 #clock-cells = <1>; 5099 #phy-cells = <1>; 5100 5101 qcom,tcsr-reg = <&tcsr 0xbff0 0xb24c>; 5102 5103 status = "disabled"; 5104 }; 5105 5106 usb_1: usb@a600000 { 5107 compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; 5108 reg = <0x0 0x0a600000 0x0 0xfc100>; 5109 5110 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5111 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5112 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5113 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5114 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5115 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 5116 clock-names = "cfg_noc", 5117 "core", 5118 "iface", 5119 "sleep", 5120 "mock_utmi", 5121 "xo"; 5122 5123 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5124 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5125 assigned-clock-rates = <19200000>, <200000000>; 5126 5127 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, 5128 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, 5129 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, 5130 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 5131 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 5132 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 5133 interrupt-names = "dwc_usb3", 5134 "pwr_event", 5135 "hs_phy_irq", 5136 "dp_hs_phy_irq", 5137 "dm_hs_phy_irq", 5138 "ss_phy_irq"; 5139 5140 iommus = <&apps_smmu 0x140 0x0>; 5141 5142 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 5143 phy-names = "usb2-phy", "usb3-phy"; 5144 5145 power-domains = <&gcc USB30_PRIM_GDSC>; 5146 required-opps = <&rpmhpd_opp_nom>; 5147 5148 resets = <&gcc GCC_USB30_PRIM_BCR>; 5149 5150 snps,dis-u1-entry-quirk; 5151 snps,dis-u2-entry-quirk; 5152 snps,dis_u2_susphy_quirk; 5153 snps,dis_u3_susphy_quirk; 5154 snps,dis_enblslpm_quirk; 5155 snps,has-lpm-erratum; 5156 snps,hird-threshold = /bits/ 8 <0x10>; 5157 snps,usb3_lpm_capable; 5158 5159 wakeup-source; 5160 5161 status = "disabled"; 5162 }; 5163 5164 usb_2: usb@a800000 { 5165 compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; 5166 reg = <0x0 0x0a800000 0x0 0xfc100>; 5167 5168 clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, 5169 <&gcc GCC_USB20_SEC_MASTER_CLK>, 5170 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, 5171 <&gcc GCC_USB20_SEC_SLEEP_CLK>, 5172 <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 5173 <&gcc GCC_USB2_PRIM_CLKREF_CLK>; 5174 clock-names = "cfg_noc", 5175 "core", 5176 "iface", 5177 "sleep", 5178 "mock_utmi", 5179 "xo"; 5180 5181 assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 5182 <&gcc GCC_USB20_SEC_MASTER_CLK>; 5183 assigned-clock-rates = <19200000>, <200000000>; 5184 5185 interrupts-extended = <&intc GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, 5186 <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, 5187 <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>, 5188 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 5189 <&pdc 10 IRQ_TYPE_EDGE_BOTH>; 5190 interrupt-names = "dwc_usb3", 5191 "pwr_event", 5192 "hs_phy_irq", 5193 "dp_hs_phy_irq", 5194 "dm_hs_phy_irq"; 5195 5196 iommus = <&apps_smmu 0xe0 0x0>; 5197 5198 phys = <&usb_2_hsphy>; 5199 phy-names = "usb2-phy"; 5200 5201 power-domains = <&gcc USB20_SEC_GDSC>; 5202 required-opps = <&rpmhpd_opp_nom>; 5203 5204 resets = <&gcc GCC_USB20_SEC_BCR>; 5205 5206 qcom,select-utmi-as-pipe-clk; 5207 5208 snps,dis_u2_susphy_quirk; 5209 snps,dis_u3_susphy_quirk; 5210 snps,dis_enblslpm_quirk; 5211 snps,has-lpm-erratum; 5212 snps,hird-threshold = /bits/ 8 <0x10>; 5213 5214 maximum-speed = "high-speed"; 5215 wakeup-source; 5216 5217 status = "disabled"; 5218 }; 5219 5220 tsens0: thermal-sensor@c263000 { 5221 compatible = "qcom,qcs615-tsens", "qcom,tsens-v2"; 5222 reg = <0x0 0x0c263000 0x0 0x1000>, 5223 <0x0 0x0c222000 0x0 0x1000>; 5224 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>, 5225 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>; 5226 interrupt-names = "uplow", "critical"; 5227 #qcom,sensors = <16>; 5228 #thermal-sensor-cells = <1>; 5229 }; 5230 5231 remoteproc_adsp: remoteproc@62400000 { 5232 compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas"; 5233 reg = <0x0 0x62400000 0x0 0x4040>; 5234 5235 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING 0>, 5236 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 5237 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 5238 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 5239 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 5240 interrupt-names = "wdog", 5241 "fatal", 5242 "ready", 5243 "handover", 5244 "stop-ack"; 5245 5246 clocks = <&rpmhcc RPMH_CXO_CLK>; 5247 clock-names = "xo"; 5248 5249 power-domains = <&rpmhpd RPMHPD_CX>; 5250 power-domain-names = "cx"; 5251 5252 memory-region = <&rproc_adsp_mem>; 5253 5254 qcom,qmp = <&aoss_qmp>; 5255 5256 qcom,smem-states = <&adsp_smp2p_out 0>; 5257 qcom,smem-state-names = "stop"; 5258 5259 status = "disabled"; 5260 5261 glink_edge: glink-edge { 5262 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING 0>; 5263 mboxes = <&apss_shared 24>; 5264 label = "lpass"; 5265 qcom,remote-pid = <2>; 5266 5267 fastrpc { 5268 compatible = "qcom,fastrpc"; 5269 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5270 label = "adsp"; 5271 memory-region = <&adsp_rpc_remote_heap_mem>; 5272 qcom,vmids = <QCOM_SCM_VMID_LPASS 5273 QCOM_SCM_VMID_ADSP_HEAP>; 5274 #address-cells = <1>; 5275 #size-cells = <0>; 5276 5277 compute-cb@3 { 5278 compatible = "qcom,fastrpc-compute-cb"; 5279 reg = <3>; 5280 iommus = <&apps_smmu 0x1723 0x0>; 5281 dma-coherent; 5282 }; 5283 5284 compute-cb@4 { 5285 compatible = "qcom,fastrpc-compute-cb"; 5286 reg = <4>; 5287 iommus = <&apps_smmu 0x1724 0x0>; 5288 dma-coherent; 5289 }; 5290 5291 compute-cb@5 { 5292 compatible = "qcom,fastrpc-compute-cb"; 5293 reg = <5>; 5294 iommus = <&apps_smmu 0x1725 0x0>; 5295 dma-coherent; 5296 }; 5297 5298 compute-cb@6 { 5299 compatible = "qcom,fastrpc-compute-cb"; 5300 reg = <6>; 5301 iommus = <&apps_smmu 0x1726 0x0>; 5302 qcom,nsessions = <5>; 5303 dma-coherent; 5304 }; 5305 }; 5306 5307 gpr: gpr { 5308 compatible = "qcom,gpr"; 5309 qcom,glink-channels = "adsp_apps"; 5310 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 5311 qcom,intents = <512 20>; 5312 #address-cells = <1>; 5313 #size-cells = <0>; 5314 5315 q6apm: service@1 { 5316 compatible = "qcom,q6apm"; 5317 reg = <GPR_APM_MODULE_IID>; 5318 #sound-dai-cells = <0>; 5319 qcom,protection-domain = "avs/audio", 5320 "msm/adsp/audio_pd"; 5321 5322 q6apmbedai: bedais { 5323 compatible = "qcom,q6apm-lpass-dais"; 5324 #sound-dai-cells = <1>; 5325 }; 5326 5327 q6apmdai: dais { 5328 compatible = "qcom,q6apm-dais"; 5329 iommus = <&apps_smmu 0x1721 0x0>; 5330 }; 5331 }; 5332 5333 q6prm: service@2 { 5334 compatible = "qcom,q6prm"; 5335 reg = <GPR_PRM_MODULE_IID>; 5336 qcom,protection-domain = "avs/audio", 5337 "msm/adsp/audio_pd"; 5338 5339 q6prmcc: clock-controller { 5340 compatible = "qcom,q6prm-lpass-clocks"; 5341 #clock-cells = <2>; 5342 }; 5343 }; 5344 }; 5345 }; 5346 }; 5347 5348 cpufreq_hw: cpufreq@18323000 { 5349 compatible = "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw"; 5350 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 5351 reg-names = "freq-domain0", "freq-domain1"; 5352 5353 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5354 clock-names = "xo", "alternate"; 5355 5356 #freq-domain-cells = <1>; 5357 #clock-cells = <1>; 5358 }; 5359 }; 5360 5361 arch_timer: timer { 5362 compatible = "arm,armv8-timer"; 5363 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW 0>, 5364 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>, 5365 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW 0>, 5366 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW 0>; 5367 }; 5368 5369 thermal-zones { 5370 aoss-thermal { 5371 thermal-sensors = <&tsens0 0>; 5372 5373 trips { 5374 aoss-critical { 5375 temperature = <115000>; 5376 hysteresis = <1000>; 5377 type = "critical"; 5378 }; 5379 }; 5380 }; 5381 5382 cpuss-0-thermal { 5383 thermal-sensors = <&tsens0 1>; 5384 5385 trips { 5386 cpuss0-critical { 5387 temperature = <115000>; 5388 hysteresis = <1000>; 5389 type = "critical"; 5390 }; 5391 }; 5392 }; 5393 5394 cpuss-1-thermal { 5395 thermal-sensors = <&tsens0 2>; 5396 5397 trips { 5398 cpuss1-critical { 5399 temperature = <115000>; 5400 hysteresis = <1000>; 5401 type = "critical"; 5402 }; 5403 }; 5404 }; 5405 5406 cpuss-2-thermal { 5407 thermal-sensors = <&tsens0 3>; 5408 5409 trips { 5410 cpuss2-critical { 5411 temperature = <115000>; 5412 hysteresis = <1000>; 5413 type = "critical"; 5414 }; 5415 }; 5416 }; 5417 5418 cpuss-3-thermal { 5419 thermal-sensors = <&tsens0 4>; 5420 5421 trips { 5422 cpuss3-critical { 5423 temperature = <115000>; 5424 hysteresis = <1000>; 5425 type = "critical"; 5426 }; 5427 }; 5428 }; 5429 5430 cpu-1-0-thermal { 5431 thermal-sensors = <&tsens0 5>; 5432 5433 trips { 5434 cpu-critical { 5435 temperature = <115000>; 5436 hysteresis = <1000>; 5437 type = "critical"; 5438 }; 5439 }; 5440 }; 5441 5442 cpu-1-1-thermal { 5443 thermal-sensors = <&tsens0 6>; 5444 5445 trips { 5446 cpu-critical { 5447 temperature = <115000>; 5448 hysteresis = <1000>; 5449 type = "critical"; 5450 }; 5451 }; 5452 }; 5453 5454 cpu-1-2-thermal { 5455 thermal-sensors = <&tsens0 7>; 5456 5457 trips { 5458 cpu-critical { 5459 temperature = <115000>; 5460 hysteresis = <1000>; 5461 type = "critical"; 5462 }; 5463 }; 5464 }; 5465 5466 cpu-1-3-thermal { 5467 thermal-sensors = <&tsens0 8>; 5468 5469 trips { 5470 cpu-critical { 5471 temperature = <115000>; 5472 hysteresis = <1000>; 5473 type = "critical"; 5474 }; 5475 }; 5476 }; 5477 5478 gpu-thermal { 5479 thermal-sensors = <&tsens0 9>; 5480 polling-delay-passive = <200>; 5481 5482 trips { 5483 gpu_alert0: trip-point0 { 5484 temperature = <105000>; 5485 hysteresis = <5000>; 5486 type = "passive"; 5487 }; 5488 5489 gpu-critical { 5490 temperature = <115000>; 5491 hysteresis = <1000>; 5492 type = "critical"; 5493 }; 5494 }; 5495 5496 cooling-maps { 5497 map0 { 5498 trip = <&gpu_alert0>; 5499 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5500 }; 5501 }; 5502 }; 5503 5504 q6-hvx-thermal { 5505 thermal-sensors = <&tsens0 10>; 5506 5507 trips { 5508 q6-hvx-critical { 5509 temperature = <115000>; 5510 hysteresis = <1000>; 5511 type = "critical"; 5512 }; 5513 }; 5514 }; 5515 5516 mdm-core-thermal { 5517 thermal-sensors = <&tsens0 11>; 5518 5519 trips { 5520 mdm-core-critical { 5521 temperature = <115000>; 5522 hysteresis = <1000>; 5523 type = "critical"; 5524 }; 5525 }; 5526 }; 5527 5528 camera-thermal { 5529 thermal-sensors = <&tsens0 12>; 5530 5531 trips { 5532 camera-critical { 5533 temperature = <115000>; 5534 hysteresis = <1000>; 5535 type = "critical"; 5536 }; 5537 }; 5538 }; 5539 5540 wlan-thermal { 5541 thermal-sensors = <&tsens0 13>; 5542 5543 trips { 5544 wlan-critical { 5545 temperature = <115000>; 5546 hysteresis = <1000>; 5547 type = "critical"; 5548 }; 5549 }; 5550 }; 5551 5552 display-thermal { 5553 thermal-sensors = <&tsens0 14>; 5554 5555 trips { 5556 display-critical { 5557 temperature = <115000>; 5558 hysteresis = <1000>; 5559 type = "critical"; 5560 }; 5561 }; 5562 }; 5563 5564 video-thermal { 5565 thermal-sensors = <&tsens0 15>; 5566 5567 trips { 5568 video-critical { 5569 temperature = <115000>; 5570 hysteresis = <1000>; 5571 type = "critical"; 5572 }; 5573 }; 5574 }; 5575 }; 5576}; 5577