1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sm8750-dispcc.h> 9#include <dt-bindings/clock/qcom,sm8750-gcc.h> 10#include <dt-bindings/clock/qcom,sm8750-tcsr.h> 11#include <dt-bindings/clock/qcom,sm8750-videocc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,gpr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "qcom,oryon"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42 next-level-cache = <&l2_0>; 43 power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; 44 power-domain-names = "psci", "perf"; 45 46 l2_0: l2-cache { 47 compatible = "cache"; 48 cache-level = <2>; 49 cache-unified; 50 }; 51 }; 52 53 cpu1: cpu@100 { 54 device_type = "cpu"; 55 compatible = "qcom,oryon"; 56 reg = <0x0 0x100>; 57 enable-method = "psci"; 58 next-level-cache = <&l2_0>; 59 power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; 60 power-domain-names = "psci", "perf"; 61 }; 62 63 cpu2: cpu@200 { 64 device_type = "cpu"; 65 compatible = "qcom,oryon"; 66 reg = <0x0 0x200>; 67 enable-method = "psci"; 68 next-level-cache = <&l2_0>; 69 power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; 70 power-domain-names = "psci", "perf"; 71 }; 72 73 cpu3: cpu@300 { 74 device_type = "cpu"; 75 compatible = "qcom,oryon"; 76 reg = <0x0 0x300>; 77 enable-method = "psci"; 78 next-level-cache = <&l2_0>; 79 power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; 80 power-domain-names = "psci", "perf"; 81 }; 82 83 cpu4: cpu@400 { 84 device_type = "cpu"; 85 compatible = "qcom,oryon"; 86 reg = <0x0 0x400>; 87 enable-method = "psci"; 88 next-level-cache = <&l2_0>; 89 power-domains = <&cpu_pd4>, <&scmi_dvfs 0>; 90 power-domain-names = "psci", "perf"; 91 }; 92 93 cpu5: cpu@500 { 94 device_type = "cpu"; 95 compatible = "qcom,oryon"; 96 reg = <0x0 0x500>; 97 enable-method = "psci"; 98 next-level-cache = <&l2_0>; 99 power-domains = <&cpu_pd5>, <&scmi_dvfs 0>; 100 power-domain-names = "psci", "perf"; 101 }; 102 103 cpu6: cpu@10000 { 104 device_type = "cpu"; 105 compatible = "qcom,oryon"; 106 reg = <0x0 0x10000>; 107 enable-method = "psci"; 108 next-level-cache = <&l2_1>; 109 power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; 110 power-domain-names = "psci", "perf"; 111 112 l2_1: l2-cache { 113 compatible = "cache"; 114 cache-level = <2>; 115 cache-unified; 116 }; 117 }; 118 119 cpu7: cpu@10100 { 120 device_type = "cpu"; 121 compatible = "qcom,oryon"; 122 reg = <0x0 0x10100>; 123 enable-method = "psci"; 124 next-level-cache = <&l2_1>; 125 power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; 126 power-domain-names = "psci", "perf"; 127 }; 128 129 cpu-map { 130 cluster0 { 131 core0 { 132 cpu = <&cpu0>; 133 }; 134 135 core1 { 136 cpu = <&cpu1>; 137 }; 138 139 core2 { 140 cpu = <&cpu2>; 141 }; 142 143 core3 { 144 cpu = <&cpu3>; 145 }; 146 147 core4 { 148 cpu = <&cpu4>; 149 }; 150 151 core5 { 152 cpu = <&cpu5>; 153 }; 154 }; 155 156 cluster1 { 157 core0 { 158 cpu = <&cpu6>; 159 }; 160 161 core1 { 162 cpu = <&cpu7>; 163 }; 164 }; 165 }; 166 167 idle-states { 168 entry-method = "psci"; 169 170 cluster0_c4: cpu-sleep-0 { 171 compatible = "arm,idle-state"; 172 idle-state-name = "ret"; 173 arm,psci-suspend-param = <0x00000004>; 174 entry-latency-us = <93>; 175 exit-latency-us = <129>; 176 min-residency-us = <560>; 177 }; 178 179 cluster1_c4: cpu-sleep-1 { 180 compatible = "arm,idle-state"; 181 idle-state-name = "ret"; 182 arm,psci-suspend-param = <0x00000004>; 183 entry-latency-us = <172>; 184 exit-latency-us = <130>; 185 min-residency-us = <686>; 186 }; 187 }; 188 189 domain-idle-states { 190 cluster_cl5: cluster-sleep-0 { 191 compatible = "domain-idle-state"; 192 arm,psci-suspend-param = <0x01000054>; 193 entry-latency-us = <2150>; 194 exit-latency-us = <1983>; 195 min-residency-us = <9144>; 196 }; 197 198 domain_ss3: domain-sleep-0 { 199 compatible = "domain-idle-state"; 200 arm,psci-suspend-param = <0x0200c354>; 201 entry-latency-us = <2800>; 202 exit-latency-us = <4400>; 203 min-residency-us = <10150>; 204 }; 205 }; 206 }; 207 208 firmware { 209 scm: scm { 210 compatible = "qcom,scm-sm8750", "qcom,scm"; 211 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 212 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 213 }; 214 215 scmi { 216 compatible = "arm,scmi"; 217 mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>; 218 mbox-names = "tx", "rx"; 219 shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; 220 221 #address-cells = <1>; 222 #size-cells = <0>; 223 224 scmi_dvfs: protocol@13 { 225 reg = <0x13>; 226 #power-domain-cells = <1>; 227 }; 228 }; 229 }; 230 231 clk_virt: interconnect-0 { 232 compatible = "qcom,sm8750-clk-virt"; 233 #interconnect-cells = <2>; 234 qcom,bcm-voters = <&apps_bcm_voter>; 235 }; 236 237 mc_virt: interconnect-1 { 238 compatible = "qcom,sm8750-mc-virt"; 239 #interconnect-cells = <2>; 240 qcom,bcm-voters = <&apps_bcm_voter>; 241 }; 242 243 memory@a0000000 { 244 device_type = "memory"; 245 /* We expect the bootloader to fill in the size */ 246 reg = <0x0 0xa0000000 0x0 0x0>; 247 }; 248 249 pmu { 250 compatible = "arm,armv8-pmuv3"; 251 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 252 }; 253 254 psci { 255 compatible = "arm,psci-1.0"; 256 method = "smc"; 257 258 cpu_pd0: power-domain-cpu0 { 259 #power-domain-cells = <0>; 260 power-domains = <&cluster0_pd>; 261 domain-idle-states = <&cluster0_c4>; 262 }; 263 264 cpu_pd1: power-domain-cpu1 { 265 #power-domain-cells = <0>; 266 power-domains = <&cluster0_pd>; 267 domain-idle-states = <&cluster0_c4>; 268 }; 269 270 cpu_pd2: power-domain-cpu2 { 271 #power-domain-cells = <0>; 272 power-domains = <&cluster0_pd>; 273 domain-idle-states = <&cluster0_c4>; 274 }; 275 276 cpu_pd3: power-domain-cpu3 { 277 #power-domain-cells = <0>; 278 power-domains = <&cluster0_pd>; 279 domain-idle-states = <&cluster0_c4>; 280 }; 281 282 cpu_pd4: power-domain-cpu4 { 283 #power-domain-cells = <0>; 284 power-domains = <&cluster0_pd>; 285 domain-idle-states = <&cluster0_c4>; 286 }; 287 288 cpu_pd5: power-domain-cpu5 { 289 #power-domain-cells = <0>; 290 power-domains = <&cluster0_pd>; 291 domain-idle-states = <&cluster0_c4>; 292 }; 293 294 cpu_pd6: power-domain-cpu6 { 295 #power-domain-cells = <0>; 296 power-domains = <&cluster1_pd>; 297 domain-idle-states = <&cluster1_c4>; 298 }; 299 300 cpu_pd7: power-domain-cpu7 { 301 #power-domain-cells = <0>; 302 power-domains = <&cluster1_pd>; 303 domain-idle-states = <&cluster1_c4>; 304 }; 305 306 cluster0_pd: power-domain-cluster0 { 307 #power-domain-cells = <0>; 308 domain-idle-states = <&cluster_cl5>; 309 power-domains = <&system_pd>; 310 }; 311 312 cluster1_pd: power-domain-cluster1 { 313 #power-domain-cells = <0>; 314 domain-idle-states = <&cluster_cl5>; 315 power-domains = <&system_pd>; 316 }; 317 318 system_pd: power-domain-system { 319 #power-domain-cells = <0>; 320 domain-idle-states = <&domain_ss3>; 321 }; 322 }; 323 324 reserved-memory { 325 #address-cells = <2>; 326 #size-cells = <2>; 327 ranges; 328 329 gunyah_hyp_mem: gunyah-hyp@80000000 { 330 reg = <0x0 0x80000000 0x0 0xe00000>; 331 no-map; 332 }; 333 334 cpusys_vm_mem: cpusys-vm-mem@80e00000 { 335 reg = <0x0 0x80e00000 0x0 0x40000>; 336 no-map; 337 }; 338 339 cpucp_mem: cpucp@81200000 { 340 reg = <0x0 0x81200000 0x0 0x200000>; 341 no-map; 342 }; 343 344 xbl_dtlog_mem: xbl-dtlog@81a00000 { 345 reg = <0x0 0x81a00000 0x0 0x40000>; 346 no-map; 347 }; 348 349 aop_image_mem: aop-image@81c00000 { 350 reg = <0x0 0x81c00000 0x0 0x60000>; 351 no-map; 352 }; 353 354 aop_cmd_db_mem: aop-cmd-db@81c60000 { 355 compatible = "qcom,cmd-db"; 356 reg = <0x0 0x81c60000 0x0 0x20000>; 357 no-map; 358 }; 359 360 /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ 361 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 362 reg = <0x0 0x81c80000 0x0 0x74000>; 363 no-map; 364 }; 365 366 /* Secdata region can be reused by apps */ 367 368 smem_mem: smem@81d00000 { 369 compatible = "qcom,smem"; 370 reg = <0x0 0x81d00000 0x0 0x200000>; 371 hwlocks = <&tcsr_mutex 3>; 372 no-map; 373 }; 374 375 pdp_ns_shared_mem: pdp-ns-shared@81f00000 { 376 reg = <0x0 0x81f00000 0x0 0x100000>; 377 no-map; 378 }; 379 380 cpucp_scandump_mem: cpucp-scandump@82000000 { 381 reg = <0x0 0x82000000 0x0 0x380000>; 382 no-map; 383 }; 384 385 adsp_mhi_mem: adsp-mhi@82380000 { 386 reg = <0x0 0x82380000 0x0 0x20000>; 387 no-map; 388 }; 389 390 soccp_sdi_mem: soccp-sdi@823a0000 { 391 reg = <0x0 0x823a0000 0x0 0x40000>; 392 no-map; 393 }; 394 395 pmic_minii_dump_mem: pmic-minii-dump@823e0000 { 396 reg = <0x0 0x823e0000 0x0 0x80000>; 397 no-map; 398 }; 399 400 pvmfw_mem: pvmfw@824a0000 { 401 reg = <0x0 0x824a0000 0x0 0x100000>; 402 no-map; 403 }; 404 405 global_sync_mem: global-sync@82600000 { 406 reg = <0x0 0x82600000 0x0 0x100000>; 407 no-map; 408 }; 409 410 tz_stat_mem: tz-stat@82700000 { 411 reg = <0x0 0x82700000 0x0 0x100000>; 412 no-map; 413 }; 414 415 qdss_mem: qdss@82800000 { 416 reg = <0x0 0x82800000 0x0 0x2000000>; 417 no-map; 418 }; 419 420 dsm_partition_1_mem: dsm-partition-1@84a00000 { 421 reg = <0x0 0x84a00000 0x0 0x4900000>; 422 no-map; 423 }; 424 425 dsm_partition_2_mem: dsm-partition-2@89300000 { 426 reg = <0x0 0x89300000 0x0 0xa80000>; 427 no-map; 428 }; 429 430 mpss_mem: mpss@8ba00000 { 431 reg = <0x0 0x8ba00000 0x0 0xf600000>; 432 no-map; 433 }; 434 435 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { 436 reg = <0x0 0x9b000000 0x0 0x80000>; 437 no-map; 438 }; 439 440 ipa_fw_mem: ipa-fw@9b080000 { 441 reg = <0x0 0x9b080000 0x0 0x10000>; 442 no-map; 443 }; 444 445 ipa_gsi_mem: ipa-gsi@9b090000 { 446 reg = <0x0 0x9b090000 0x0 0xa000>; 447 no-map; 448 }; 449 450 gpu_micro_code_mem: gpu-micro-code@9b09a000 { 451 reg = <0x0 0x9b09a000 0x0 0x2000>; 452 no-map; 453 }; 454 455 spss_region_mem: spss@9b0a0000 { 456 reg = <0x0 0x9b0a0000 0x0 0x1e0000>; 457 no-map; 458 }; 459 460 /* First part of the "SPU secure shared memory" region */ 461 spu_tz_shared_mem: spu-tz-shared@9b280000 { 462 reg = <0x0 0x9b280000 0x0 0x40000>; 463 no-map; 464 }; 465 466 /* Second part of the "SPU secure shared memory" region */ 467 spu_modem_shared_mem: spu-modem-shared@9b2c0000 { 468 reg = <0x0 0x9b2c0000 0x0 0x40000>; 469 no-map; 470 }; 471 472 camera_mem: camera@9b300000 { 473 reg = <0x0 0x9b300000 0x0 0x800000>; 474 no-map; 475 }; 476 477 camera_2_mem: camera-2@9bb00000 { 478 reg = <0x0 0x9bb00000 0x0 0x800000>; 479 no-map; 480 }; 481 482 video_mem: video@9c300000 { 483 reg = <0x0 0x9c300000 0x0 0x800000>; 484 no-map; 485 }; 486 487 cvp_mem: cvp@9cb00000 { 488 reg = <0x0 0x9cb00000 0x0 0x700000>; 489 no-map; 490 }; 491 492 cdsp_mem: cdsp@9d200000 { 493 reg = <0x0 0x9d200000 0x0 0x1900000>; 494 no-map; 495 }; 496 497 q6_cdsp_dtb_mem: q6-cdsp-dtb@9eb00000 { 498 reg = <0x0 0x9eb00000 0x0 0x80000>; 499 no-map; 500 }; 501 502 soccp_mem: soccp@9ec00000 { 503 reg = <0x0 0x9ec00000 0x0 0x180000>; 504 no-map; 505 }; 506 507 q6_adsp_dtb_mem: q6-adsp-dtb@9ed80000 { 508 reg = <0x0 0x9ed80000 0x0 0x80000>; 509 no-map; 510 }; 511 512 adspslpi_mem: adspslpi@9ee00000 { 513 reg = <0x0 0x9ee00000 0x0 0x3a80000>; 514 no-map; 515 }; 516 517 xbl_ramdump_mem: xbl-ramdump@b8000000 { 518 reg = <0x0 0xb8000000 0x0 0x1c0000>; 519 no-map; 520 }; 521 522 hwfence_shbuf: hwfence-shbuf@d4e23000 { 523 no-map; 524 reg = <0x0 0xd4e23000 0x0 0x2dd000>; 525 }; 526 527 /* Merged tz_reserved, xbl_sc, and qtee regions */ 528 tz_merged_mem: tz-merged@d8000000 { 529 reg = <0x0 0xd8000000 0x0 0x600000>; 530 no-map; 531 }; 532 533 trust_ui_vm_mem: trust-ui-vm@f3800000 { 534 reg = <0x0 0xf3800000 0x0 0x4400000>; 535 no-map; 536 }; 537 538 oem_vm_mem: oem-vm@f7c00000 { 539 reg = <0x0 0xf7c00000 0x0 0x4c00000>; 540 no-map; 541 }; 542 543 llcc_lpi_mem: llcc-lpi@ff800000 { 544 reg = <0x0 0xff800000 0x0 0x800000>; 545 no-map; 546 }; 547 548 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap { 549 compatible = "shared-dma-pool"; 550 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; 551 alignment = <0x0 0x400000>; 552 size = <0x0 0xc00000>; 553 reusable; 554 }; 555 }; 556 557 smp2p-adsp { 558 compatible = "qcom,smp2p"; 559 560 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 561 IPCC_MPROC_SIGNAL_SMP2P 562 IRQ_TYPE_EDGE_RISING>; 563 564 mboxes = <&ipcc IPCC_CLIENT_LPASS 565 IPCC_MPROC_SIGNAL_SMP2P>; 566 567 qcom,smem = <443>, <429>; 568 qcom,local-pid = <0>; 569 qcom,remote-pid = <2>; 570 571 smp2p_adsp_out: master-kernel { 572 qcom,entry-name = "master-kernel"; 573 #qcom,smem-state-cells = <1>; 574 }; 575 576 smp2p_adsp_in: slave-kernel { 577 qcom,entry-name = "slave-kernel"; 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 }; 581 }; 582 583 smp2p-cdsp { 584 compatible = "qcom,smp2p"; 585 586 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 587 IPCC_MPROC_SIGNAL_SMP2P 588 IRQ_TYPE_EDGE_RISING>; 589 590 mboxes = <&ipcc IPCC_CLIENT_CDSP 591 IPCC_MPROC_SIGNAL_SMP2P>; 592 593 qcom,smem = <94>, <432>; 594 qcom,local-pid = <0>; 595 qcom,remote-pid = <5>; 596 597 smp2p_cdsp_out: master-kernel { 598 qcom,entry-name = "master-kernel"; 599 #qcom,smem-state-cells = <1>; 600 }; 601 602 smp2p_cdsp_in: slave-kernel { 603 qcom,entry-name = "slave-kernel"; 604 interrupt-controller; 605 #interrupt-cells = <2>; 606 }; 607 }; 608 609 smp2p-modem { 610 compatible = "qcom,smp2p"; 611 612 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 613 IPCC_MPROC_SIGNAL_SMP2P 614 IRQ_TYPE_EDGE_RISING>; 615 616 mboxes = <&ipcc IPCC_CLIENT_MPSS 617 IPCC_MPROC_SIGNAL_SMP2P>; 618 619 qcom,smem = <435>, <428>; 620 qcom,local-pid = <0>; 621 qcom,remote-pid = <1>; 622 623 smp2p_modem_out: master-kernel { 624 qcom,entry-name = "master-kernel"; 625 #qcom,smem-state-cells = <1>; 626 }; 627 628 smp2p_modem_in: slave-kernel { 629 qcom,entry-name = "slave-kernel"; 630 interrupt-controller; 631 #interrupt-cells = <2>; 632 }; 633 634 ipa_smp2p_out: ipa-ap-to-modem { 635 qcom,entry-name = "ipa"; 636 #qcom,smem-state-cells = <1>; 637 }; 638 639 ipa_smp2p_in: ipa-modem-to-ap { 640 qcom,entry-name = "ipa"; 641 interrupt-controller; 642 #interrupt-cells = <2>; 643 }; 644 645 /* TODO: smem mailbox in and out */ 646 }; 647 648 soc: soc@0 { 649 compatible = "simple-bus"; 650 651 #address-cells = <2>; 652 #size-cells = <2>; 653 dma-ranges = <0 0 0 0 0x10 0>; 654 ranges = <0 0 0 0 0x10 0>; 655 656 gcc: clock-controller@100000 { 657 compatible = "qcom,sm8750-gcc"; 658 reg = <0x0 0x00100000 0x0 0x1f4200>; 659 660 clocks = <&bi_tcxo_div2>, 661 <0>, 662 <&sleep_clk>, 663 <&pcie0_phy>, 664 <0>, 665 <0>, 666 <0>, 667 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 668 669 #clock-cells = <1>; 670 #reset-cells = <1>; 671 #power-domain-cells = <1>; 672 }; 673 674 ipcc: mailbox@406000 { 675 compatible = "qcom,sm8750-ipcc", "qcom,ipcc"; 676 reg = <0x0 0x00406000 0x0 0x1000>; 677 678 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 679 interrupt-controller; 680 #interrupt-cells = <3>; 681 682 #mbox-cells = <2>; 683 }; 684 685 gpi_dma2: dma-controller@800000 { 686 compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma"; 687 reg = <0x0 0x00800000 0x0 0x60000>; 688 689 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 701 702 dma-channels = <12>; 703 dma-channel-mask = <0x1e>; 704 #dma-cells = <3>; 705 706 iommus = <&apps_smmu 0x436 0x0>; 707 708 status = "disabled"; 709 }; 710 711 qupv3_2: geniqup@8c0000 { 712 compatible = "qcom,geni-se-qup"; 713 reg = <0x0 0x008c0000 0x0 0x2000>; 714 715 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 716 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 717 clock-names = "m-ahb", 718 "s-ahb"; 719 720 iommus = <&apps_smmu 0x423 0x0>; 721 722 #address-cells = <2>; 723 #size-cells = <2>; 724 ranges; 725 726 status = "disabled"; 727 728 i2c8: i2c@880000 { 729 compatible = "qcom,geni-i2c"; 730 reg = <0x0 0x00880000 0x0 0x4000>; 731 732 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 733 734 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 735 clock-names = "se"; 736 737 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 738 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 739 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 740 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 741 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 742 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 743 interconnect-names = "qup-core", 744 "qup-config", 745 "qup-memory"; 746 747 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 748 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 749 dma-names = "tx", 750 "rx"; 751 752 pinctrl-0 = <&qup_i2c8_data_clk>; 753 pinctrl-names = "default"; 754 755 #address-cells = <1>; 756 #size-cells = <0>; 757 758 status = "disabled"; 759 }; 760 761 spi8: spi@880000 { 762 compatible = "qcom,geni-spi"; 763 reg = <0x0 0x00880000 0x0 0x4000>; 764 765 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 766 767 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 768 clock-names = "se"; 769 770 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 771 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 772 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 773 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 774 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 775 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 776 interconnect-names = "qup-core", 777 "qup-config", 778 "qup-memory"; 779 780 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 781 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 782 dma-names = "tx", 783 "rx"; 784 785 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 786 pinctrl-names = "default"; 787 788 #address-cells = <1>; 789 #size-cells = <0>; 790 791 status = "disabled"; 792 }; 793 794 i2c9: i2c@884000 { 795 compatible = "qcom,geni-i2c"; 796 reg = <0x0 0x00884000 0x0 0x4000>; 797 798 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 799 800 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 801 clock-names = "se"; 802 803 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 804 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 805 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 806 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 807 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 808 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 809 interconnect-names = "qup-core", 810 "qup-config", 811 "qup-memory"; 812 813 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 814 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 815 dma-names = "tx", 816 "rx"; 817 818 pinctrl-0 = <&qup_i2c9_data_clk>; 819 pinctrl-names = "default"; 820 821 #address-cells = <1>; 822 #size-cells = <0>; 823 824 status = "disabled"; 825 }; 826 827 spi9: spi@884000 { 828 compatible = "qcom,geni-spi"; 829 reg = <0x0 0x00884000 0x0 0x4000>; 830 831 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 832 833 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 834 clock-names = "se"; 835 836 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 837 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 838 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 839 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 840 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 841 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 842 interconnect-names = "qup-core", 843 "qup-config", 844 "qup-memory"; 845 846 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 847 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 848 dma-names = "tx", 849 "rx"; 850 851 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 852 pinctrl-names = "default"; 853 854 #address-cells = <1>; 855 #size-cells = <0>; 856 857 status = "disabled"; 858 }; 859 860 i2c10: i2c@888000 { 861 compatible = "qcom,geni-i2c"; 862 reg = <0x0 0x00888000 0x0 0x4000>; 863 864 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 865 866 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 867 clock-names = "se"; 868 869 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 870 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 871 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 872 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 873 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 874 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 875 interconnect-names = "qup-core", 876 "qup-config", 877 "qup-memory"; 878 879 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 880 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 881 dma-names = "tx", 882 "rx"; 883 884 pinctrl-0 = <&qup_i2c10_data_clk>; 885 pinctrl-names = "default"; 886 887 #address-cells = <1>; 888 #size-cells = <0>; 889 890 status = "disabled"; 891 }; 892 893 spi10: spi@888000 { 894 compatible = "qcom,geni-spi"; 895 reg = <0x0 0x00888000 0x0 0x4000>; 896 897 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 898 899 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 900 clock-names = "se"; 901 902 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 903 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 904 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 905 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 906 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 907 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 908 interconnect-names = "qup-core", 909 "qup-config", 910 "qup-memory"; 911 912 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 913 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 914 dma-names = "tx", 915 "rx"; 916 917 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 918 pinctrl-names = "default"; 919 920 #address-cells = <1>; 921 #size-cells = <0>; 922 923 status = "disabled"; 924 }; 925 926 i2c11: i2c@88c000 { 927 compatible = "qcom,geni-i2c"; 928 reg = <0x0 0x0088c000 0x0 0x4000>; 929 930 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 931 932 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 933 clock-names = "se"; 934 935 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 936 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 937 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 938 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 939 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 940 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 941 interconnect-names = "qup-core", 942 "qup-config", 943 "qup-memory"; 944 945 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 946 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 947 dma-names = "tx", 948 "rx"; 949 950 pinctrl-0 = <&qup_i2c11_data_clk>; 951 pinctrl-names = "default"; 952 953 #address-cells = <1>; 954 #size-cells = <0>; 955 956 status = "disabled"; 957 }; 958 959 spi11: spi@88c000 { 960 compatible = "qcom,geni-spi"; 961 reg = <0x0 0x0088c000 0x0 0x4000>; 962 963 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 964 965 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 966 clock-names = "se"; 967 968 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 969 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 970 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 971 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 972 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 973 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 974 interconnect-names = "qup-core", 975 "qup-config", 976 "qup-memory"; 977 978 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 979 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 980 dma-names = "tx", 981 "rx"; 982 983 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 984 pinctrl-names = "default"; 985 986 #address-cells = <1>; 987 #size-cells = <0>; 988 989 status = "disabled"; 990 }; 991 992 i2c12: i2c@890000 { 993 compatible = "qcom,geni-i2c"; 994 reg = <0x0 0x00890000 0x0 0x4000>; 995 996 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 997 998 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 999 clock-names = "se"; 1000 1001 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1002 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1003 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1004 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1005 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1006 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1007 interconnect-names = "qup-core", 1008 "qup-config", 1009 "qup-memory"; 1010 1011 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1012 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1013 dma-names = "tx", 1014 "rx"; 1015 1016 pinctrl-0 = <&qup_i2c12_data_clk>; 1017 pinctrl-names = "default"; 1018 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 1022 status = "disabled"; 1023 }; 1024 1025 spi12: spi@890000 { 1026 compatible = "qcom,geni-spi"; 1027 reg = <0x0 0x00890000 0x0 0x4000>; 1028 1029 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1030 1031 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1032 clock-names = "se"; 1033 1034 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1035 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1036 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1037 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1038 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1039 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1040 interconnect-names = "qup-core", 1041 "qup-config", 1042 "qup-memory"; 1043 1044 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1045 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1046 dma-names = "tx", 1047 "rx"; 1048 1049 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1050 pinctrl-names = "default"; 1051 1052 #address-cells = <1>; 1053 #size-cells = <0>; 1054 1055 status = "disabled"; 1056 }; 1057 1058 i2c13: i2c@894000 { 1059 compatible = "qcom,geni-i2c"; 1060 reg = <0x0 0x00894000 0x0 0x4000>; 1061 1062 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1063 1064 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1065 clock-names = "se"; 1066 1067 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1068 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1069 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1070 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1071 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1072 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1073 interconnect-names = "qup-core", 1074 "qup-config", 1075 "qup-memory"; 1076 1077 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1078 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1079 dma-names = "tx", 1080 "rx"; 1081 1082 pinctrl-0 = <&qup_i2c13_data_clk>; 1083 pinctrl-names = "default"; 1084 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 1088 status = "disabled"; 1089 }; 1090 1091 spi13: spi@894000 { 1092 compatible = "qcom,geni-spi"; 1093 reg = <0x0 0x00894000 0x0 0x4000>; 1094 1095 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1096 1097 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1098 clock-names = "se"; 1099 1100 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1101 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1102 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1103 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1104 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1105 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1106 interconnect-names = "qup-core", 1107 "qup-config", 1108 "qup-memory"; 1109 1110 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1111 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1112 dma-names = "tx", 1113 "rx"; 1114 1115 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1116 pinctrl-names = "default"; 1117 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 1121 status = "disabled"; 1122 }; 1123 1124 uart14: serial@898000 { 1125 compatible = "qcom,geni-uart"; 1126 reg = <0x0 0x00898000 0x0 0x4000>; 1127 1128 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1129 1130 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1131 clock-names = "se"; 1132 1133 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1134 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1135 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1136 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1137 interconnect-names = "qup-core", 1138 "qup-config"; 1139 1140 pinctrl-0 = <&qup_uart14_default>; 1141 pinctrl-names = "default"; 1142 1143 status = "disabled"; 1144 }; 1145 1146 i2c15: i2c@89c000 { 1147 compatible = "qcom,geni-i2c"; 1148 reg = <0x0 0x0089c000 0x0 0x4000>; 1149 1150 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1151 1152 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1153 clock-names = "se"; 1154 1155 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1156 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1157 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1158 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1159 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1160 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1161 interconnect-names = "qup-core", 1162 "qup-config", 1163 "qup-memory"; 1164 1165 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1166 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1167 dma-names = "tx", 1168 "rx"; 1169 1170 pinctrl-0 = <&qup_i2c15_data_clk>; 1171 pinctrl-names = "default"; 1172 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 1176 status = "disabled"; 1177 }; 1178 1179 spi15: spi@89c000 { 1180 compatible = "qcom,geni-spi"; 1181 reg = <0x0 0x0089c000 0x0 0x4000>; 1182 1183 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1184 1185 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1186 clock-names = "se"; 1187 1188 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1189 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1190 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1191 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1192 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1193 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1194 interconnect-names = "qup-core", 1195 "qup-config", 1196 "qup-memory"; 1197 1198 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1199 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1200 dma-names = "tx", 1201 "rx"; 1202 1203 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1204 pinctrl-names = "default"; 1205 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 1209 status = "disabled"; 1210 }; 1211 }; 1212 1213 i2c_master_hub_0: geniqup@9c0000 { 1214 compatible = "qcom,geni-se-i2c-master-hub"; 1215 reg = <0x0 0x009c0000 0x0 0x2000>; 1216 1217 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1218 clock-names = "s-ahb"; 1219 1220 #address-cells = <2>; 1221 #size-cells = <2>; 1222 ranges; 1223 1224 status = "disabled"; 1225 1226 i2c_hub_0: i2c@980000 { 1227 compatible = "qcom,geni-i2c-master-hub"; 1228 reg = <0x0 0x00980000 0x0 0x4000>; 1229 1230 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1231 1232 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1233 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1234 clock-names = "se", 1235 "core"; 1236 1237 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1238 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1239 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1240 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1241 interconnect-names = "qup-core", 1242 "qup-config"; 1243 1244 pinctrl-0 = <&hub_i2c0_data_clk>; 1245 pinctrl-names = "default"; 1246 1247 #address-cells = <1>; 1248 #size-cells = <0>; 1249 1250 status = "disabled"; 1251 }; 1252 1253 i2c_hub_1: i2c@984000 { 1254 compatible = "qcom,geni-i2c-master-hub"; 1255 reg = <0x0 0x00984000 0x0 0x4000>; 1256 1257 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1258 1259 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1260 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1261 clock-names = "se", 1262 "core"; 1263 1264 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1265 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1266 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1267 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1268 interconnect-names = "qup-core", 1269 "qup-config"; 1270 1271 pinctrl-0 = <&hub_i2c1_data_clk>; 1272 pinctrl-names = "default"; 1273 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 1277 status = "disabled"; 1278 }; 1279 1280 i2c_hub_2: i2c@988000 { 1281 compatible = "qcom,geni-i2c-master-hub"; 1282 reg = <0x0 0x00988000 0x0 0x4000>; 1283 1284 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1285 1286 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1287 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1288 clock-names = "se", 1289 "core"; 1290 1291 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1292 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1293 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1294 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1295 interconnect-names = "qup-core", 1296 "qup-config"; 1297 1298 pinctrl-0 = <&hub_i2c2_data_clk>; 1299 pinctrl-names = "default"; 1300 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 1304 status = "disabled"; 1305 }; 1306 1307 i2c_hub_3: i2c@98c000 { 1308 compatible = "qcom,geni-i2c-master-hub"; 1309 reg = <0x0 0x0098c000 0x0 0x4000>; 1310 1311 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1312 1313 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1314 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1315 clock-names = "se", 1316 "core"; 1317 1318 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1319 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1320 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1321 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1322 interconnect-names = "qup-core", 1323 "qup-config"; 1324 1325 pinctrl-0 = <&hub_i2c3_data_clk>; 1326 pinctrl-names = "default"; 1327 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 1331 status = "disabled"; 1332 }; 1333 1334 i2c_hub_4: i2c@990000 { 1335 compatible = "qcom,geni-i2c-master-hub"; 1336 reg = <0x0 0x00990000 0x0 0x4000>; 1337 1338 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1339 1340 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1341 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1342 clock-names = "se", 1343 "core"; 1344 1345 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1346 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1347 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1348 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1349 interconnect-names = "qup-core", 1350 "qup-config"; 1351 1352 pinctrl-0 = <&hub_i2c4_data_clk>; 1353 pinctrl-names = "default"; 1354 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 1358 status = "disabled"; 1359 }; 1360 1361 i2c_hub_5: i2c@994000 { 1362 compatible = "qcom,geni-i2c-master-hub"; 1363 reg = <0x0 0x00994000 0x0 0x4000>; 1364 1365 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1366 1367 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1368 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1369 clock-names = "se", 1370 "core"; 1371 1372 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1373 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1374 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1375 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1376 interconnect-names = "qup-core", 1377 "qup-config"; 1378 1379 pinctrl-0 = <&hub_i2c5_data_clk>; 1380 pinctrl-names = "default"; 1381 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 1385 status = "disabled"; 1386 }; 1387 1388 i2c_hub_6: i2c@998000 { 1389 compatible = "qcom,geni-i2c-master-hub"; 1390 reg = <0x0 0x00998000 0x0 0x4000>; 1391 1392 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1393 1394 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1395 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1396 clock-names = "se", 1397 "core"; 1398 1399 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1400 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1401 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1402 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1403 interconnect-names = "qup-core", 1404 "qup-config"; 1405 1406 pinctrl-0 = <&hub_i2c6_data_clk>; 1407 pinctrl-names = "default"; 1408 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 1412 status = "disabled"; 1413 }; 1414 1415 i2c_hub_7: i2c@99c000 { 1416 compatible = "qcom,geni-i2c-master-hub"; 1417 reg = <0x0 0x0099c000 0x0 0x4000>; 1418 1419 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1420 1421 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1422 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1423 clock-names = "se", 1424 "core"; 1425 1426 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1427 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1428 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1429 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1430 interconnect-names = "qup-core", 1431 "qup-config"; 1432 1433 pinctrl-0 = <&hub_i2c7_data_clk>; 1434 pinctrl-names = "default"; 1435 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 1439 status = "disabled"; 1440 }; 1441 1442 i2c_hub_8: i2c@9a0000 { 1443 compatible = "qcom,geni-i2c-master-hub"; 1444 reg = <0x0 0x009a0000 0x0 0x4000>; 1445 1446 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1447 1448 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1449 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1450 clock-names = "se", 1451 "core"; 1452 1453 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1454 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1455 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1456 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1457 interconnect-names = "qup-core", 1458 "qup-config"; 1459 1460 pinctrl-0 = <&hub_i2c8_data_clk>; 1461 pinctrl-names = "default"; 1462 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 1466 status = "disabled"; 1467 }; 1468 1469 i2c_hub_9: i2c@9a4000 { 1470 compatible = "qcom,geni-i2c-master-hub"; 1471 reg = <0x0 0x009a4000 0x0 0x4000>; 1472 1473 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1474 1475 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1476 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1477 clock-names = "se", 1478 "core"; 1479 1480 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1481 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1482 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1483 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1484 interconnect-names = "qup-core", 1485 "qup-config"; 1486 1487 pinctrl-0 = <&hub_i2c9_data_clk>; 1488 pinctrl-names = "default"; 1489 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 1493 status = "disabled"; 1494 }; 1495 }; 1496 1497 gpi_dma1: dma-controller@a00000 { 1498 compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma"; 1499 reg = <0x0 0x00a00000 0x0 0x60000>; 1500 1501 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1513 1514 dma-channels = <12>; 1515 dma-channel-mask = <0x1e>; 1516 #dma-cells = <3>; 1517 1518 iommus = <&apps_smmu 0xb6 0x0>; 1519 1520 status = "disabled"; 1521 }; 1522 1523 qupv3_1: geniqup@ac0000 { 1524 compatible = "qcom,geni-se-qup"; 1525 reg = <0x0 0x00ac0000 0x0 0x2000>; 1526 1527 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1528 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1529 clock-names = "m-ahb", 1530 "s-ahb"; 1531 1532 iommus = <&apps_smmu 0xa3 0x0>; 1533 1534 #address-cells = <2>; 1535 #size-cells = <2>; 1536 ranges; 1537 1538 status = "disabled"; 1539 1540 i2c0: i2c@a80000 { 1541 compatible = "qcom,geni-i2c"; 1542 reg = <0x0 0x00a80000 0x0 0x4000>; 1543 1544 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1545 1546 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1547 clock-names = "se"; 1548 1549 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1550 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1551 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1552 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1553 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1554 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1555 interconnect-names = "qup-core", 1556 "qup-config", 1557 "qup-memory"; 1558 1559 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1560 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1561 dma-names = "tx", 1562 "rx"; 1563 1564 pinctrl-0 = <&qup_i2c0_data_clk>; 1565 pinctrl-names = "default"; 1566 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 1570 status = "disabled"; 1571 }; 1572 1573 spi0: spi@a80000 { 1574 compatible = "qcom,geni-spi"; 1575 reg = <0x0 0x00a80000 0x0 0x4000>; 1576 1577 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1578 1579 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1580 clock-names = "se"; 1581 1582 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1583 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1584 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1585 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1586 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1587 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1588 interconnect-names = "qup-core", 1589 "qup-config", 1590 "qup-memory"; 1591 1592 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1593 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1594 dma-names = "tx", 1595 "rx"; 1596 1597 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1598 pinctrl-names = "default"; 1599 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 1603 status = "disabled"; 1604 }; 1605 1606 i2c1: i2c@a84000 { 1607 compatible = "qcom,geni-i2c"; 1608 reg = <0x0 0x00a84000 0x0 0x4000>; 1609 1610 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1611 1612 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1613 clock-names = "se"; 1614 1615 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1616 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1617 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1618 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1619 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1620 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1621 interconnect-names = "qup-core", 1622 "qup-config", 1623 "qup-memory"; 1624 1625 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1626 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1627 dma-names = "tx", 1628 "rx"; 1629 1630 pinctrl-0 = <&qup_i2c1_data_clk>; 1631 pinctrl-names = "default"; 1632 1633 #address-cells = <1>; 1634 #size-cells = <0>; 1635 1636 status = "disabled"; 1637 }; 1638 1639 spi1: spi@a84000 { 1640 compatible = "qcom,geni-spi"; 1641 reg = <0x0 0x00a84000 0x0 0x4000>; 1642 1643 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1644 1645 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1646 clock-names = "se"; 1647 1648 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1649 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1650 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1651 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1652 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1653 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1654 interconnect-names = "qup-core", 1655 "qup-config", 1656 "qup-memory"; 1657 1658 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1659 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1660 dma-names = "tx", 1661 "rx"; 1662 1663 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1664 pinctrl-names = "default"; 1665 1666 #address-cells = <1>; 1667 #size-cells = <0>; 1668 1669 status = "disabled"; 1670 }; 1671 1672 i2c2: i2c@a88000 { 1673 compatible = "qcom,geni-i2c"; 1674 reg = <0x0 0x00a88000 0x0 0x4000>; 1675 1676 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1677 1678 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1679 clock-names = "se"; 1680 1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1682 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1683 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1684 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1685 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1686 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1687 interconnect-names = "qup-core", 1688 "qup-config", 1689 "qup-memory"; 1690 1691 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1692 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1693 dma-names = "tx", 1694 "rx"; 1695 1696 pinctrl-0 = <&qup_i2c2_data_clk>; 1697 pinctrl-names = "default"; 1698 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 1702 status = "disabled"; 1703 }; 1704 1705 spi2: spi@a88000 { 1706 compatible = "qcom,geni-spi"; 1707 reg = <0x0 0x00a88000 0x0 0x4000>; 1708 1709 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1710 1711 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1712 clock-names = "se"; 1713 1714 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1715 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1716 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1717 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1718 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1719 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1720 interconnect-names = "qup-core", 1721 "qup-config", 1722 "qup-memory"; 1723 1724 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1725 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1726 dma-names = "tx", 1727 "rx"; 1728 1729 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1730 pinctrl-names = "default"; 1731 1732 #address-cells = <1>; 1733 #size-cells = <0>; 1734 1735 status = "disabled"; 1736 }; 1737 1738 i2c3: i2c@a8c000 { 1739 compatible = "qcom,geni-i2c"; 1740 reg = <0x0 0x00a8c000 0x0 0x4000>; 1741 1742 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1743 1744 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1745 clock-names = "se"; 1746 1747 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1748 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1749 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1750 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1751 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1752 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1753 interconnect-names = "qup-core", 1754 "qup-config", 1755 "qup-memory"; 1756 1757 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1758 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1759 dma-names = "tx", 1760 "rx"; 1761 1762 pinctrl-0 = <&qup_i2c3_data_clk>; 1763 pinctrl-names = "default"; 1764 1765 #address-cells = <1>; 1766 #size-cells = <0>; 1767 1768 status = "disabled"; 1769 }; 1770 1771 spi3: spi@a8c000 { 1772 compatible = "qcom,geni-spi"; 1773 reg = <0x0 0x00a8c000 0x0 0x4000>; 1774 1775 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1776 1777 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1778 clock-names = "se"; 1779 1780 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1781 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1782 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1783 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1784 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1785 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1786 interconnect-names = "qup-core", 1787 "qup-config", 1788 "qup-memory"; 1789 1790 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1791 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1792 dma-names = "tx", 1793 "rx"; 1794 1795 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1796 pinctrl-names = "default"; 1797 1798 #address-cells = <1>; 1799 #size-cells = <0>; 1800 1801 status = "disabled"; 1802 }; 1803 1804 i2c4: i2c@a90000 { 1805 compatible = "qcom,geni-i2c"; 1806 reg = <0x0 0x00a90000 0x0 0x4000>; 1807 1808 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1809 1810 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1811 clock-names = "se"; 1812 1813 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1814 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1815 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1816 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1817 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1818 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1819 interconnect-names = "qup-core", 1820 "qup-config", 1821 "qup-memory"; 1822 1823 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1824 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1825 dma-names = "tx", 1826 "rx"; 1827 1828 pinctrl-0 = <&qup_i2c4_data_clk>; 1829 pinctrl-names = "default"; 1830 1831 #address-cells = <1>; 1832 #size-cells = <0>; 1833 1834 status = "disabled"; 1835 }; 1836 1837 spi4: spi@a90000 { 1838 compatible = "qcom,geni-spi"; 1839 reg = <0x0 0x00a90000 0x0 0x4000>; 1840 1841 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1842 1843 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1844 clock-names = "se"; 1845 1846 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1847 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1848 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1849 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1850 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1851 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1852 interconnect-names = "qup-core", 1853 "qup-config", 1854 "qup-memory"; 1855 1856 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1857 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1858 dma-names = "tx", 1859 "rx"; 1860 1861 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1862 pinctrl-names = "default"; 1863 1864 #address-cells = <1>; 1865 #size-cells = <0>; 1866 1867 status = "disabled"; 1868 }; 1869 1870 i2c5: i2c@a94000 { 1871 compatible = "qcom,geni-i2c"; 1872 reg = <0x0 0x00a94000 0x0 0x4000>; 1873 1874 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1875 1876 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1877 clock-names = "se"; 1878 1879 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1880 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1881 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1882 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1883 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1884 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1885 interconnect-names = "qup-core", 1886 "qup-config", 1887 "qup-memory"; 1888 1889 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1890 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1891 dma-names = "tx", 1892 "rx"; 1893 1894 pinctrl-0 = <&qup_i2c5_data_clk>; 1895 pinctrl-names = "default"; 1896 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 1900 status = "disabled"; 1901 }; 1902 1903 spi5: spi@a94000 { 1904 compatible = "qcom,geni-spi"; 1905 reg = <0x0 0x00a94000 0x0 0x4000>; 1906 1907 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1908 1909 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1910 clock-names = "se"; 1911 1912 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1913 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1914 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1915 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1916 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1917 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1918 interconnect-names = "qup-core", 1919 "qup-config", 1920 "qup-memory"; 1921 1922 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1923 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1924 dma-names = "tx", 1925 "rx"; 1926 1927 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1928 pinctrl-names = "default"; 1929 1930 #address-cells = <1>; 1931 #size-cells = <0>; 1932 1933 status = "disabled"; 1934 }; 1935 1936 i2c6: i2c@a98000 { 1937 compatible = "qcom,geni-i2c"; 1938 reg = <0x0 0x00a98000 0x0 0x4000>; 1939 1940 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1941 1942 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1943 clock-names = "se"; 1944 1945 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1946 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1947 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1948 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1949 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1950 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1951 interconnect-names = "qup-core", 1952 "qup-config", 1953 "qup-memory"; 1954 1955 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1956 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1957 dma-names = "tx", 1958 "rx"; 1959 1960 pinctrl-0 = <&qup_i2c6_data_clk>; 1961 pinctrl-names = "default"; 1962 1963 #address-cells = <1>; 1964 #size-cells = <0>; 1965 1966 status = "disabled"; 1967 }; 1968 1969 spi6: spi@a98000 { 1970 compatible = "qcom,geni-spi"; 1971 reg = <0x0 0x00a98000 0x0 0x4000>; 1972 1973 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1974 1975 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1976 clock-names = "se"; 1977 1978 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1979 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1980 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1981 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1982 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1983 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1984 interconnect-names = "qup-core", 1985 "qup-config", 1986 "qup-memory"; 1987 1988 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1989 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1990 dma-names = "tx", 1991 "rx"; 1992 1993 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1994 pinctrl-names = "default"; 1995 1996 #address-cells = <1>; 1997 #size-cells = <0>; 1998 1999 status = "disabled"; 2000 }; 2001 2002 uart7: serial@a9c000 { 2003 compatible = "qcom,geni-debug-uart"; 2004 reg = <0x0 0x00a9c000 0x0 0x4000>; 2005 2006 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 2007 2008 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2009 clock-names = "se"; 2010 2011 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2012 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2013 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2014 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2015 interconnect-names = "qup-core", 2016 "qup-config"; 2017 2018 pinctrl-0 = <&qup_uart7_default>; 2019 pinctrl-names = "default"; 2020 2021 status = "disabled"; 2022 }; 2023 }; 2024 2025 rng: rng@10c3000 { 2026 compatible = "qcom,sm8750-trng", "qcom,trng"; 2027 reg = <0x0 0x010c3000 0x0 0x1000>; 2028 }; 2029 2030 cnoc_main: interconnect@1500000 { 2031 compatible = "qcom,sm8750-cnoc-main"; 2032 reg = <0x0 0x01500000 0x0 0x16080>; 2033 qcom,bcm-voters = <&apps_bcm_voter>; 2034 #interconnect-cells = <2>; 2035 }; 2036 2037 config_noc: interconnect@1600000 { 2038 compatible = "qcom,sm8750-config-noc"; 2039 reg = <0x0 0x01600000 0x0 0x6200>; 2040 qcom,bcm-voters = <&apps_bcm_voter>; 2041 #interconnect-cells = <2>; 2042 }; 2043 2044 system_noc: interconnect@1680000 { 2045 compatible = "qcom,sm8750-system-noc"; 2046 reg = <0x0 0x01680000 0x0 0x1d080>; 2047 qcom,bcm-voters = <&apps_bcm_voter>; 2048 #interconnect-cells = <2>; 2049 }; 2050 2051 pcie_noc: interconnect@16c0000 { 2052 compatible = "qcom,sm8750-pcie-anoc"; 2053 reg = <0x0 0x016c0000 0x0 0x11400>; 2054 qcom,bcm-voters = <&apps_bcm_voter>; 2055 #interconnect-cells = <2>; 2056 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2057 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2058 }; 2059 2060 aggre1_noc: interconnect@16e0000 { 2061 compatible = "qcom,sm8750-aggre1-noc"; 2062 reg = <0x0 0x016e0000 0x0 0x16400>; 2063 qcom,bcm-voters = <&apps_bcm_voter>; 2064 #interconnect-cells = <2>; 2065 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2066 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2067 }; 2068 2069 aggre2_noc: interconnect@1700000 { 2070 compatible = "qcom,sm8750-aggre2-noc"; 2071 reg = <0x0 0x01700000 0x0 0x1f400>; 2072 qcom,bcm-voters = <&apps_bcm_voter>; 2073 #interconnect-cells = <2>; 2074 clocks = <&rpmhcc RPMH_IPA_CLK>; 2075 }; 2076 2077 mmss_noc: interconnect@1780000 { 2078 compatible = "qcom,sm8750-mmss-noc"; 2079 reg = <0x0 0x01780000 0x0 0x5b800>; 2080 qcom,bcm-voters = <&apps_bcm_voter>; 2081 #interconnect-cells = <2>; 2082 }; 2083 2084 ice: crypto@1d88000 { 2085 compatible = "qcom,sm8750-inline-crypto-engine", 2086 "qcom,inline-crypto-engine"; 2087 reg = <0x0 0x01d88000 0x0 0x18000>; 2088 2089 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2090 }; 2091 2092 cryptobam: dma-controller@1dc4000 { 2093 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2094 reg = <0x0 0x01dc4000 0x0 0x28000>; 2095 2096 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2097 2098 #dma-cells = <1>; 2099 2100 iommus = <&apps_smmu 0x480 0>, 2101 <&apps_smmu 0x481 0>; 2102 2103 qcom,ee = <0>; 2104 qcom,num-ees = <4>; 2105 num-channels = <20>; 2106 qcom,controlled-remotely; 2107 }; 2108 2109 crypto: crypto@1dfa000 { 2110 compatible = "qcom,sm8750-qce", "qcom,sm8150-qce", "qcom,qce"; 2111 reg = <0x0 0x01dfa000 0x0 0x6000>; 2112 2113 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 2114 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2115 interconnect-names = "memory"; 2116 2117 dmas = <&cryptobam 4>, <&cryptobam 5>; 2118 dma-names = "rx", "tx"; 2119 2120 iommus = <&apps_smmu 0x480 0>, 2121 <&apps_smmu 0x481 0>; 2122 }; 2123 2124 tcsr_mutex: hwlock@1f40000 { 2125 compatible = "qcom,tcsr-mutex"; 2126 reg = <0x0 0x01f40000 0x0 0x20000>; 2127 #hwlock-cells = <1>; 2128 }; 2129 2130 remoteproc_mpss: remoteproc@4080000 { 2131 compatible = "qcom,sm8750-mpss-pas"; 2132 reg = <0x0 0x04080000 0x0 0x10000>; 2133 2134 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2135 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2136 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2137 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2138 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2139 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2140 interrupt-names = "wdog", 2141 "fatal", 2142 "ready", 2143 "handover", 2144 "stop-ack", 2145 "shutdown-ack"; 2146 2147 clocks = <&rpmhcc RPMH_CXO_CLK>; 2148 clock-names = "xo"; 2149 2150 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 2151 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2152 2153 power-domains = <&rpmhpd RPMHPD_CX>, 2154 <&rpmhpd RPMHPD_MSS>; 2155 power-domain-names = "cx", 2156 "mss"; 2157 2158 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, 2159 <&dsm_partition_1_mem>, 2160 <&dsm_partition_2_mem>; 2161 2162 qcom,qmp = <&aoss_qmp>; 2163 2164 qcom,smem-states = <&smp2p_modem_out 0>; 2165 qcom,smem-state-names = "stop"; 2166 2167 status = "disabled"; 2168 2169 glink-edge { 2170 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2171 IPCC_MPROC_SIGNAL_GLINK_QMP 2172 IRQ_TYPE_EDGE_RISING>; 2173 2174 mboxes = <&ipcc IPCC_CLIENT_MPSS 2175 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2176 2177 qcom,remote-pid = <1>; 2178 2179 label = "mpss"; 2180 }; 2181 }; 2182 2183 remoteproc_adsp: remoteproc@6800000 { 2184 compatible = "qcom,sm8750-adsp-pas", "qcom,sm8550-adsp-pas"; 2185 reg = <0x0 0x06800000 0x0 0x10000>; 2186 2187 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2188 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2189 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2190 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2191 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2192 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2193 interrupt-names = "wdog", 2194 "fatal", 2195 "ready", 2196 "handover", 2197 "stop-ack", 2198 "shutdown-ack"; 2199 2200 clocks = <&rpmhcc RPMH_CXO_CLK>; 2201 clock-names = "xo"; 2202 2203 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 2204 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2205 2206 power-domains = <&rpmhpd RPMHPD_LCX>, 2207 <&rpmhpd RPMHPD_LMX>; 2208 power-domain-names = "lcx", 2209 "lmx"; 2210 2211 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2212 2213 qcom,qmp = <&aoss_qmp>; 2214 2215 qcom,smem-states = <&smp2p_adsp_out 0>; 2216 qcom,smem-state-names = "stop"; 2217 2218 status = "disabled"; 2219 2220 remoteproc_adsp_glink: glink-edge { 2221 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2222 IPCC_MPROC_SIGNAL_GLINK_QMP 2223 IRQ_TYPE_EDGE_RISING>; 2224 mboxes = <&ipcc IPCC_CLIENT_LPASS 2225 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2226 qcom,remote-pid = <2>; 2227 label = "lpass"; 2228 2229 fastrpc { 2230 compatible = "qcom,fastrpc"; 2231 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2232 label = "adsp"; 2233 memory-region = <&adsp_rpc_remote_heap_mem>; 2234 qcom,vmids = <QCOM_SCM_VMID_LPASS 2235 QCOM_SCM_VMID_ADSP_HEAP>; 2236 #address-cells = <1>; 2237 #size-cells = <0>; 2238 2239 compute-cb@3 { 2240 compatible = "qcom,fastrpc-compute-cb"; 2241 reg = <3>; 2242 iommus = <&apps_smmu 0x1003 0x80>, 2243 <&apps_smmu 0x1043 0x20>; 2244 dma-coherent; 2245 }; 2246 2247 compute-cb@4 { 2248 compatible = "qcom,fastrpc-compute-cb"; 2249 reg = <4>; 2250 iommus = <&apps_smmu 0x1004 0x80>, 2251 <&apps_smmu 0x1044 0x20>; 2252 dma-coherent; 2253 }; 2254 2255 compute-cb@5 { 2256 compatible = "qcom,fastrpc-compute-cb"; 2257 reg = <5>; 2258 iommus = <&apps_smmu 0x1005 0x80>, 2259 <&apps_smmu 0x1045 0x20>; 2260 dma-coherent; 2261 }; 2262 2263 compute-cb@6 { 2264 compatible = "qcom,fastrpc-compute-cb"; 2265 reg = <6>; 2266 iommus = <&apps_smmu 0x1006 0x80>, 2267 <&apps_smmu 0x1046 0x20>; 2268 dma-coherent; 2269 }; 2270 2271 compute-cb@7 { 2272 compatible = "qcom,fastrpc-compute-cb"; 2273 reg = <7>; 2274 iommus = <&apps_smmu 0x1007 0x40>, 2275 <&apps_smmu 0x1067 0x0>, 2276 <&apps_smmu 0x1087 0x0>; 2277 dma-coherent; 2278 }; 2279 2280 compute-cb@8 { 2281 compatible = "qcom,fastrpc-compute-cb"; 2282 reg = <8>; 2283 iommus = <&apps_smmu 0x1008 0x80>, 2284 <&apps_smmu 0x1048 0x20>; 2285 dma-coherent; 2286 }; 2287 }; 2288 2289 gpr { 2290 compatible = "qcom,gpr"; 2291 qcom,glink-channels = "adsp_apps"; 2292 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2293 qcom,intents = <512 20>; 2294 #address-cells = <1>; 2295 #size-cells = <0>; 2296 2297 q6apm: service@1 { 2298 compatible = "qcom,q6apm"; 2299 reg = <GPR_APM_MODULE_IID>; 2300 #sound-dai-cells = <0>; 2301 qcom,protection-domain = "avs/audio", 2302 "msm/adsp/audio_pd"; 2303 2304 q6apmbedai: bedais { 2305 compatible = "qcom,q6apm-lpass-dais"; 2306 #sound-dai-cells = <1>; 2307 }; 2308 2309 q6apmdai: dais { 2310 compatible = "qcom,q6apm-dais"; 2311 iommus = <&apps_smmu 0x1001 0x80>, 2312 <&apps_smmu 0x1041 0x20>; 2313 }; 2314 }; 2315 2316 q6prm: service@2 { 2317 compatible = "qcom,q6prm"; 2318 reg = <GPR_PRM_MODULE_IID>; 2319 qcom,protection-domain = "avs/audio", 2320 "msm/adsp/audio_pd"; 2321 2322 q6prmcc: clock-controller { 2323 compatible = "qcom,q6prm-lpass-clocks"; 2324 #clock-cells = <2>; 2325 }; 2326 }; 2327 }; 2328 }; 2329 }; 2330 2331 lpass_wsa2macro: codec@6aa0000 { 2332 compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 2333 reg = <0x0 0x06aa0000 0x0 0x1000>; 2334 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2335 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2336 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2337 <&lpass_vamacro>; 2338 clock-names = "mclk", 2339 "macro", 2340 "dcodec", 2341 "fsgen"; 2342 2343 #clock-cells = <0>; 2344 clock-output-names = "wsa2-mclk"; 2345 #sound-dai-cells = <1>; 2346 }; 2347 2348 swr3: soundwire@6ab0000 { 2349 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0"; 2350 reg = <0x0 0x06ab0000 0x0 0x10000>; 2351 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2352 clocks = <&lpass_wsa2macro>; 2353 clock-names = "iface"; 2354 label = "WSA2"; 2355 2356 pinctrl-0 = <&wsa2_swr_active>; 2357 pinctrl-names = "default"; 2358 2359 qcom,din-ports = <4>; 2360 qcom,dout-ports = <9>; 2361 2362 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>; 2363 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>; 2364 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2365 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; 2366 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; 2367 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>; 2368 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00 0x00>; 2369 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2370 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2371 2372 #address-cells = <2>; 2373 #size-cells = <0>; 2374 #sound-dai-cells = <1>; 2375 status = "disabled"; 2376 }; 2377 2378 lpass_rxmacro: codec@6ac0000 { 2379 compatible = "qcom,sm8750-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 2380 reg = <0x0 0x06ac0000 0x0 0x1000>; 2381 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2382 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2383 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2384 <&lpass_vamacro>; 2385 clock-names = "mclk", 2386 "macro", 2387 "dcodec", 2388 "fsgen"; 2389 2390 #clock-cells = <0>; 2391 clock-output-names = "mclk"; 2392 #sound-dai-cells = <1>; 2393 }; 2394 2395 swr1: soundwire@6ad0000 { 2396 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0"; 2397 reg = <0x0 0x06ad0000 0x0 0x10000>; 2398 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2399 clocks = <&lpass_rxmacro>; 2400 clock-names = "iface"; 2401 label = "RX"; 2402 2403 pinctrl-0 = <&rx_swr_active>; 2404 pinctrl-names = "default"; 2405 2406 qcom,din-ports = <1>; 2407 qcom,dout-ports = <11>; 2408 2409 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0x31 0xff 0xff 0xff>; 2410 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 2411 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 2412 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0x00 0xff 0xff 0xff>; 2413 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0x0f 0xff 0xff 0xff>; 2414 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0x18 0xff 0xff 0xff>; 2415 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; 2416 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 2417 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; 2418 2419 #address-cells = <2>; 2420 #size-cells = <0>; 2421 #sound-dai-cells = <1>; 2422 status = "disabled"; 2423 }; 2424 2425 lpass_txmacro: codec@6ae0000 { 2426 compatible = "qcom,sm8750-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 2427 reg = <0x0 0x06ae0000 0x0 0x1000>; 2428 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2429 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2430 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2431 <&lpass_vamacro>; 2432 clock-names = "mclk", 2433 "macro", 2434 "dcodec", 2435 "fsgen"; 2436 2437 #clock-cells = <0>; 2438 clock-output-names = "mclk"; 2439 #sound-dai-cells = <1>; 2440 }; 2441 2442 lpass_wsamacro: codec@6b00000 { 2443 compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 2444 reg = <0x0 0x06b00000 0x0 0x1000>; 2445 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2446 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2447 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2448 <&lpass_vamacro>; 2449 clock-names = "mclk", 2450 "macro", 2451 "dcodec", 2452 "fsgen"; 2453 2454 #clock-cells = <0>; 2455 clock-output-names = "mclk"; 2456 #sound-dai-cells = <1>; 2457 }; 2458 2459 swr0: soundwire@6b10000 { 2460 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0"; 2461 reg = <0x0 0x06b10000 0x0 0x10000>; 2462 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2463 clocks = <&lpass_wsamacro>; 2464 clock-names = "iface"; 2465 label = "WSA"; 2466 2467 pinctrl-0 = <&wsa_swr_active>; 2468 pinctrl-names = "default"; 2469 2470 qcom,din-ports = <4>; 2471 qcom,dout-ports = <9>; 2472 2473 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>; 2474 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>; 2475 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2476 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; 2477 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; 2478 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>; 2479 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00 0x00>; 2480 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2481 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2482 2483 #address-cells = <2>; 2484 #size-cells = <0>; 2485 #sound-dai-cells = <1>; 2486 status = "disabled"; 2487 }; 2488 2489 lpass_ag_noc: interconnect@7e40000 { 2490 compatible = "qcom,sm8750-lpass-ag-noc"; 2491 reg = <0x0 0x07e40000 0x0 0xe080>; 2492 qcom,bcm-voters = <&apps_bcm_voter>; 2493 #interconnect-cells = <2>; 2494 }; 2495 2496 lpass_lpiaon_noc: interconnect@7400000 { 2497 compatible = "qcom,sm8750-lpass-lpiaon-noc"; 2498 reg = <0x0 0x07400000 0x0 0x19080>; 2499 qcom,bcm-voters = <&apps_bcm_voter>; 2500 #interconnect-cells = <2>; 2501 }; 2502 2503 lpass_lpicx_noc: interconnect@7420000 { 2504 compatible = "qcom,sm8750-lpass-lpicx-noc"; 2505 reg = <0x0 0x07420000 0x0 0x44080>; 2506 qcom,bcm-voters = <&apps_bcm_voter>; 2507 #interconnect-cells = <2>; 2508 }; 2509 2510 swr2: soundwire@7630000 { 2511 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0"; 2512 reg = <0x0 0x07630000 0x0 0x10000>; 2513 interrupts = <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, 2514 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 2515 interrupt-names = "core", "wakeup"; 2516 clocks = <&lpass_txmacro>; 2517 clock-names = "iface"; 2518 label = "TX"; 2519 2520 pinctrl-0 = <&tx_swr_active>; 2521 pinctrl-names = "default"; 2522 2523 qcom,din-ports = <4>; 2524 qcom,dout-ports = <0>; 2525 2526 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2527 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2528 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2529 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2530 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2531 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2532 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2533 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2534 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2535 2536 #address-cells = <2>; 2537 #size-cells = <0>; 2538 #sound-dai-cells = <1>; 2539 status = "disabled"; 2540 }; 2541 2542 lpass_vamacro: codec@7660000 { 2543 compatible = "qcom,sm8750-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 2544 reg = <0x0 0x07660000 0x0 0x2000>; 2545 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2546 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2547 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2548 clock-names = "mclk", 2549 "macro", 2550 "dcodec"; 2551 2552 #clock-cells = <0>; 2553 clock-output-names = "fsgen"; 2554 #sound-dai-cells = <1>; 2555 }; 2556 2557 lpass_tlmm: pinctrl@7760000 { 2558 compatible = "qcom,sm8750-lpass-lpi-pinctrl", 2559 "qcom,sm8650-lpass-lpi-pinctrl"; 2560 reg = <0x0 0x07760000 0x0 0x20000>; 2561 2562 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2563 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2564 clock-names = "core", "audio"; 2565 2566 gpio-controller; 2567 #gpio-cells = <2>; 2568 gpio-ranges = <&lpass_tlmm 0 0 23>; 2569 2570 tx_swr_active: tx-swr-active-state { 2571 clk-pins { 2572 pins = "gpio0"; 2573 function = "swr_tx_clk"; 2574 drive-strength = <2>; 2575 slew-rate = <1>; 2576 bias-disable; 2577 }; 2578 2579 data-pins { 2580 pins = "gpio1", "gpio2", "gpio14"; 2581 function = "swr_tx_data"; 2582 drive-strength = <2>; 2583 slew-rate = <1>; 2584 bias-bus-hold; 2585 }; 2586 }; 2587 2588 rx_swr_active: rx-swr-active-state { 2589 clk-pins { 2590 pins = "gpio3"; 2591 function = "swr_rx_clk"; 2592 drive-strength = <2>; 2593 slew-rate = <1>; 2594 bias-disable; 2595 }; 2596 2597 data-pins { 2598 pins = "gpio4", "gpio5"; 2599 function = "swr_rx_data"; 2600 drive-strength = <2>; 2601 slew-rate = <1>; 2602 bias-bus-hold; 2603 }; 2604 }; 2605 2606 dmic01_default: dmic01-default-state { 2607 clk-pins { 2608 pins = "gpio6"; 2609 function = "dmic1_clk"; 2610 drive-strength = <8>; 2611 output-high; 2612 }; 2613 2614 data-pins { 2615 pins = "gpio7"; 2616 function = "dmic1_data"; 2617 drive-strength = <8>; 2618 input-enable; 2619 }; 2620 }; 2621 2622 dmic23_default: dmic23-default-state { 2623 clk-pins { 2624 pins = "gpio8"; 2625 function = "dmic2_clk"; 2626 drive-strength = <8>; 2627 output-high; 2628 }; 2629 2630 data-pins { 2631 pins = "gpio9"; 2632 function = "dmic2_data"; 2633 drive-strength = <8>; 2634 input-enable; 2635 }; 2636 }; 2637 2638 wsa_swr_active: wsa-swr-active-state { 2639 clk-pins { 2640 pins = "gpio10"; 2641 function = "wsa_swr_clk"; 2642 drive-strength = <2>; 2643 slew-rate = <1>; 2644 bias-disable; 2645 }; 2646 2647 data-pins { 2648 pins = "gpio11"; 2649 function = "wsa_swr_data"; 2650 drive-strength = <2>; 2651 slew-rate = <1>; 2652 bias-bus-hold; 2653 }; 2654 }; 2655 2656 wsa2_swr_active: wsa2-swr-active-state { 2657 clk-pins { 2658 pins = "gpio15"; 2659 function = "wsa2_swr_clk"; 2660 drive-strength = <2>; 2661 slew-rate = <1>; 2662 bias-disable; 2663 }; 2664 2665 data-pins { 2666 pins = "gpio16"; 2667 function = "wsa2_swr_data"; 2668 drive-strength = <2>; 2669 slew-rate = <1>; 2670 bias-bus-hold; 2671 }; 2672 }; 2673 }; 2674 2675 sdhc_2: mmc@8804000 { 2676 compatible = "qcom,sm8750-sdhci", "qcom,sdhci-msm-v5"; 2677 reg = <0x0 0x08804000 0x0 0x1000>; 2678 2679 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2680 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2681 interrupt-names = "hc_irq", 2682 "pwr_irq"; 2683 2684 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2685 <&gcc GCC_SDCC2_APPS_CLK>, 2686 <&rpmhcc RPMH_CXO_CLK>; 2687 clock-names = "iface", 2688 "core", 2689 "xo"; 2690 2691 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 2692 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2693 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2694 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 2695 interconnect-names = "sdhc-ddr", 2696 "cpu-sdhc"; 2697 2698 power-domains = <&rpmhpd RPMHPD_CX>; 2699 operating-points-v2 = <&sdhc2_opp_table>; 2700 2701 qcom,dll-config = <0x0007442c>; 2702 qcom,ddr-config = <0x80040868>; 2703 2704 iommus = <&apps_smmu 0x540 0x0>; 2705 dma-coherent; 2706 2707 bus-width = <4>; 2708 max-sd-hs-hz = <37500000>; 2709 2710 resets = <&gcc GCC_SDCC2_BCR>; 2711 2712 status = "disabled"; 2713 2714 sdhc2_opp_table: opp-table { 2715 compatible = "operating-points-v2"; 2716 2717 opp-100000000 { 2718 opp-hz = /bits/ 64 <100000000>; 2719 required-opps = <&rpmhpd_opp_low_svs>; 2720 }; 2721 2722 opp-202000000 { 2723 opp-hz = /bits/ 64 <202000000>; 2724 required-opps = <&rpmhpd_opp_svs_l1>; 2725 }; 2726 }; 2727 }; 2728 2729 usb_hsphy: phy@88e3000 { 2730 compatible = "qcom,sm8750-m31-eusb2-phy"; 2731 reg = <0x0 0x88e3000 0x0 0x29c>; 2732 2733 clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>; 2734 clock-names = "ref"; 2735 2736 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2737 2738 #phy-cells = <0>; 2739 2740 status = "disabled"; 2741 }; 2742 2743 usb_dp_qmpphy: phy@88e8000 { 2744 compatible = "qcom,sm8750-qmp-usb3-dp-phy"; 2745 reg = <0x0 0x088e8000 0x0 0x4000>; 2746 2747 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2748 <&tcsrcc TCSR_USB3_CLKREF_EN>, 2749 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2750 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2751 clock-names = "aux", 2752 "ref", 2753 "com_aux", 2754 "usb3_pipe"; 2755 2756 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2757 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2758 reset-names = "phy", 2759 "common"; 2760 2761 power-domains = <&gcc GCC_USB3_PHY_GDSC>; 2762 2763 #clock-cells = <1>; 2764 #phy-cells = <1>; 2765 2766 orientation-switch; 2767 2768 status = "disabled"; 2769 2770 ports { 2771 #address-cells = <1>; 2772 #size-cells = <0>; 2773 2774 port@0 { 2775 reg = <0>; 2776 2777 usb_dp_qmpphy_out: endpoint { 2778 }; 2779 }; 2780 2781 port@1 { 2782 reg = <1>; 2783 2784 usb_dp_qmpphy_usb_ss_in: endpoint { 2785 remote-endpoint = <&usb_dwc3_ss>; 2786 }; 2787 }; 2788 2789 port@2 { 2790 reg = <2>; 2791 2792 usb_dp_qmpphy_dp_in: endpoint { 2793 remote-endpoint = <&mdss_dp0_out>; 2794 }; 2795 }; 2796 }; 2797 }; 2798 2799 usb: usb@a600000 { 2800 compatible = "qcom,sm8750-dwc3", "qcom,snps-dwc3"; 2801 reg = <0x0 0x0a600000 0x0 0xfc100>; 2802 2803 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2804 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2805 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2806 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2807 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2808 clock-names = "cfg_noc", 2809 "core", 2810 "iface", 2811 "sleep", 2812 "mock_utmi"; 2813 2814 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2815 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2816 assigned-clock-rates = <19200000>, 2817 <200000000>; 2818 2819 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2820 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2821 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2822 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2823 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2824 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2825 interrupt-names = "dwc_usb3", 2826 "pwr_event", 2827 "hs_phy_irq", 2828 "dp_hs_phy_irq", 2829 "dm_hs_phy_irq", 2830 "ss_phy_irq"; 2831 2832 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2833 required-opps = <&rpmhpd_opp_nom>; 2834 2835 resets = <&gcc GCC_USB30_PRIM_BCR>; 2836 2837 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 2838 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2839 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2840 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2841 interconnect-names = "usb-ddr", "apps-usb"; 2842 2843 iommus = <&apps_smmu 0x40 0x0>; 2844 2845 phys = <&usb_hsphy>, 2846 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 2847 phy-names = "usb2-phy", 2848 "usb3-phy"; 2849 2850 snps,hird-threshold = /bits/ 8 <0x0>; 2851 snps,usb2-gadget-lpm-disable; 2852 snps,dis_u2_susphy_quirk; 2853 snps,dis_enblslpm_quirk; 2854 snps,dis-u1-entry-quirk; 2855 snps,dis-u2-entry-quirk; 2856 snps,is-utmi-l1-suspend; 2857 snps,usb3_lpm_capable; 2858 snps,usb2-lpm-disable; 2859 snps,has-lpm-erratum; 2860 tx-fifo-resize; 2861 2862 dma-coherent; 2863 usb-role-switch; 2864 2865 status = "disabled"; 2866 2867 ports { 2868 #address-cells = <1>; 2869 #size-cells = <0>; 2870 2871 port@0 { 2872 reg = <0>; 2873 2874 usb_dwc3_hs: endpoint { 2875 }; 2876 }; 2877 2878 port@1 { 2879 reg = <1>; 2880 2881 usb_dwc3_ss: endpoint { 2882 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 2883 }; 2884 }; 2885 }; 2886 }; 2887 2888 iris: video-codec@aa00000 { 2889 compatible = "qcom,sm8750-iris"; 2890 reg = <0x0 0x0aa00000 0x0 0xf0000>; 2891 2892 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 2893 <&videocc VIDEO_CC_MVS0C_CLK>, 2894 <&videocc VIDEO_CC_MVS0_CLK>, 2895 <&gcc GCC_VIDEO_AXI1_CLK>, 2896 <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, 2897 <&videocc VIDEO_CC_MVS0_FREERUN_CLK>; 2898 clock-names = "iface", 2899 "core", 2900 "vcodec0_core", 2901 "iface1", 2902 "core_freerun", 2903 "vcodec0_core_freerun"; 2904 2905 dma-coherent; 2906 iommus = <&apps_smmu 0x1940 0>, 2907 <&apps_smmu 0x1947 0>; 2908 2909 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2910 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 2911 <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS 2912 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2913 interconnect-names = "cpu-cfg", 2914 "video-mem"; 2915 2916 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2917 2918 memory-region = <&video_mem>; 2919 2920 operating-points-v2 = <&iris_opp_table>; 2921 2922 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 2923 <&videocc VIDEO_CC_MVS0_GDSC>, 2924 <&rpmhpd RPMHPD_MXC>, 2925 <&rpmhpd RPMHPD_MMCX>; 2926 power-domain-names = "venus", 2927 "vcodec0", 2928 "mxc", 2929 "mmcx"; 2930 2931 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 2932 <&gcc GCC_VIDEO_AXI1_CLK_ARES>, 2933 <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, 2934 <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>; 2935 reset-names = "bus0", 2936 "bus1", 2937 "core", 2938 "vcodec0_core"; 2939 2940 /* 2941 * IRIS firmware is signed by vendors, only 2942 * enable in boards where the proper signed firmware 2943 * is available. 2944 */ 2945 status = "disabled"; 2946 2947 iris_opp_table: opp-table { 2948 compatible = "operating-points-v2"; 2949 2950 opp-240000000 { 2951 opp-hz = /bits/ 64 <240000000>; 2952 required-opps = <&rpmhpd_opp_svs>, 2953 <&rpmhpd_opp_low_svs_d1>; 2954 }; 2955 2956 opp-338000000 { 2957 opp-hz = /bits/ 64 <338000000>; 2958 required-opps = <&rpmhpd_opp_svs>, 2959 <&rpmhpd_opp_low_svs>; 2960 }; 2961 2962 opp-420000000 { 2963 opp-hz = /bits/ 64 <420000000>; 2964 required-opps = <&rpmhpd_opp_svs_l1>, 2965 <&rpmhpd_opp_svs>; 2966 }; 2967 2968 opp-444000000 { 2969 opp-hz = /bits/ 64 <444000000>; 2970 required-opps = <&rpmhpd_opp_svs_l1>, 2971 <&rpmhpd_opp_svs_l1>; 2972 }; 2973 2974 opp-533333334 { 2975 opp-hz = /bits/ 64 <533333334>; 2976 required-opps = <&rpmhpd_opp_svs_l1>, 2977 <&rpmhpd_opp_nom>; 2978 }; 2979 2980 opp-570000000 { 2981 opp-hz = /bits/ 64 <570000000>; 2982 required-opps = <&rpmhpd_opp_nom>, 2983 <&rpmhpd_opp_nom_l1>; 2984 }; 2985 2986 opp-630000000 { 2987 opp-hz = /bits/ 64 <630000000>; 2988 required-opps = <&rpmhpd_opp_nom>, 2989 <&rpmhpd_opp_turbo>; 2990 }; 2991 }; 2992 }; 2993 2994 videocc: clock-controller@aaf0000 { 2995 compatible = "qcom,sm8750-videocc"; 2996 reg = <0x0 0x0aaf0000 0x0 0x10000>; 2997 clocks = <&bi_tcxo_div2>, 2998 <&gcc GCC_VIDEO_AHB_CLK>; 2999 power-domains = <&rpmhpd RPMHPD_MMCX>, 3000 <&rpmhpd RPMHPD_MXC>; 3001 required-opps = <&rpmhpd_opp_low_svs>, 3002 <&rpmhpd_opp_low_svs>; 3003 #clock-cells = <1>; 3004 #reset-cells = <1>; 3005 #power-domain-cells = <1>; 3006 }; 3007 3008 mdss: display-subsystem@ae00000 { 3009 compatible = "qcom,sm8750-mdss"; 3010 reg = <0x0 0x0ae00000 0x0 0x1000>; 3011 reg-names = "mdss"; 3012 3013 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3014 3015 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3016 <&gcc GCC_DISP_HF_AXI_CLK>, 3017 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3018 3019 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3020 3021 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 3022 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3023 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3024 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3025 interconnect-names = "mdp0-mem", 3026 "cpu-cfg"; 3027 3028 power-domains = <&dispcc MDSS_GDSC>; 3029 3030 iommus = <&apps_smmu 0x800 0x2>; 3031 3032 interrupt-controller; 3033 #interrupt-cells = <1>; 3034 3035 #address-cells = <2>; 3036 #size-cells = <2>; 3037 ranges; 3038 3039 status = "disabled"; 3040 3041 mdss_mdp: display-controller@ae01000 { 3042 compatible = "qcom,sm8750-dpu"; 3043 reg = <0x0 0x0ae01000 0x0 0x93000>, 3044 <0x0 0x0aeb0000 0x0 0x2008>; 3045 reg-names = "mdp", 3046 "vbif"; 3047 3048 interrupts-extended = <&mdss 0>; 3049 3050 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3051 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3052 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3053 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3054 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3055 clock-names = "nrt_bus", 3056 "iface", 3057 "lut", 3058 "core", 3059 "vsync"; 3060 3061 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3062 assigned-clock-rates = <19200000>; 3063 3064 operating-points-v2 = <&mdp_opp_table>; 3065 3066 power-domains = <&rpmhpd RPMHPD_MMCX>; 3067 3068 ports { 3069 #address-cells = <1>; 3070 #size-cells = <0>; 3071 3072 port@0 { 3073 reg = <0>; 3074 3075 dpu_intf1_out: endpoint { 3076 remote-endpoint = <&mdss_dsi0_in>; 3077 }; 3078 }; 3079 3080 port@1 { 3081 reg = <1>; 3082 3083 dpu_intf2_out: endpoint { 3084 remote-endpoint = <&mdss_dsi1_in>; 3085 }; 3086 }; 3087 3088 port@2 { 3089 reg = <2>; 3090 3091 dpu_intf0_out: endpoint { 3092 remote-endpoint = <&mdss_dp0_in>; 3093 }; 3094 }; 3095 }; 3096 3097 mdp_opp_table: opp-table { 3098 compatible = "operating-points-v2"; 3099 3100 opp-156000000 { 3101 opp-hz = /bits/ 64 <156000000>; 3102 required-opps = <&rpmhpd_opp_low_svs_d1>; 3103 }; 3104 3105 opp-207000000 { 3106 opp-hz = /bits/ 64 <207000000>; 3107 required-opps = <&rpmhpd_opp_low_svs>; 3108 }; 3109 3110 opp-337000000 { 3111 opp-hz = /bits/ 64 <337000000>; 3112 required-opps = <&rpmhpd_opp_svs>; 3113 }; 3114 3115 opp-417000000 { 3116 opp-hz = /bits/ 64 <417000000>; 3117 required-opps = <&rpmhpd_opp_svs_l1>; 3118 }; 3119 3120 opp-532000000 { 3121 opp-hz = /bits/ 64 <532000000>; 3122 required-opps = <&rpmhpd_opp_nom>; 3123 }; 3124 3125 opp-575000000 { 3126 opp-hz = /bits/ 64 <575000000>; 3127 required-opps = <&rpmhpd_opp_nom_l1>; 3128 }; 3129 }; 3130 }; 3131 3132 mdss_dsi0: dsi@ae94000 { 3133 compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3134 reg = <0x0 0x0ae94000 0x0 0x400>; 3135 reg-names = "dsi_ctrl"; 3136 3137 interrupts-extended = <&mdss 4>; 3138 3139 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3140 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3141 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3142 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3143 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3144 <&gcc GCC_DISP_HF_AXI_CLK>, 3145 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3146 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3147 <&dispcc DISP_CC_ESYNC0_CLK>, 3148 <&dispcc DISP_CC_OSC_CLK>, 3149 <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3150 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3151 clock-names = "byte", 3152 "byte_intf", 3153 "pixel", 3154 "core", 3155 "iface", 3156 "bus", 3157 "dsi_pll_pixel", 3158 "dsi_pll_byte", 3159 "esync", 3160 "osc", 3161 "byte_src", 3162 "pixel_src"; 3163 3164 operating-points-v2 = <&mdss_dsi_opp_table>; 3165 3166 power-domains = <&rpmhpd RPMHPD_MMCX>; 3167 3168 phys = <&mdss_dsi0_phy>; 3169 phy-names = "dsi"; 3170 3171 #address-cells = <1>; 3172 #size-cells = <0>; 3173 3174 status = "disabled"; 3175 3176 ports { 3177 #address-cells = <1>; 3178 #size-cells = <0>; 3179 3180 port@0 { 3181 reg = <0>; 3182 3183 mdss_dsi0_in: endpoint { 3184 remote-endpoint = <&dpu_intf1_out>; 3185 }; 3186 }; 3187 3188 port@1 { 3189 reg = <1>; 3190 3191 mdss_dsi0_out: endpoint { 3192 }; 3193 }; 3194 }; 3195 3196 mdss_dsi_opp_table: opp-table { 3197 compatible = "operating-points-v2"; 3198 3199 opp-140630000 { 3200 opp-hz = /bits/ 64 <140630000>; 3201 required-opps = <&rpmhpd_opp_low_svs_d1>; 3202 }; 3203 3204 opp-187500000 { 3205 opp-hz = /bits/ 64 <187500000>; 3206 required-opps = <&rpmhpd_opp_low_svs>; 3207 }; 3208 3209 opp-300000000 { 3210 opp-hz = /bits/ 64 <300000000>; 3211 required-opps = <&rpmhpd_opp_svs>; 3212 }; 3213 3214 opp-358000000 { 3215 opp-hz = /bits/ 64 <358000000>; 3216 required-opps = <&rpmhpd_opp_svs_l1>; 3217 }; 3218 }; 3219 }; 3220 3221 mdss_dsi0_phy: phy@ae95000 { 3222 compatible = "qcom,sm8750-dsi-phy-3nm"; 3223 reg = <0x0 0x0ae95000 0x0 0x200>, 3224 <0x0 0x0ae95200 0x0 0x280>, 3225 <0x0 0x0ae95500 0x0 0x400>; 3226 reg-names = "dsi_phy", 3227 "dsi_phy_lane", 3228 "dsi_pll"; 3229 3230 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3231 <&bi_tcxo_div2>; 3232 clock-names = "iface", 3233 "ref"; 3234 3235 #clock-cells = <1>; 3236 #phy-cells = <0>; 3237 3238 status = "disabled"; 3239 }; 3240 3241 mdss_dsi1: dsi@ae96000 { 3242 compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3243 reg = <0x0 0x0ae96000 0x0 0x400>; 3244 reg-names = "dsi_ctrl"; 3245 3246 interrupts-extended = <&mdss 5>; 3247 3248 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3249 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3250 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3251 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3252 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3253 <&gcc GCC_DISP_HF_AXI_CLK>, 3254 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 3255 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3256 <&dispcc DISP_CC_ESYNC1_CLK>, 3257 <&dispcc DISP_CC_OSC_CLK>, 3258 <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3259 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3260 clock-names = "byte", 3261 "byte_intf", 3262 "pixel", 3263 "core", 3264 "iface", 3265 "bus", 3266 "dsi_pll_pixel", 3267 "dsi_pll_byte", 3268 "esync", 3269 "osc", 3270 "byte_src", 3271 "pixel_src"; 3272 3273 operating-points-v2 = <&mdss_dsi_opp_table>; 3274 3275 power-domains = <&rpmhpd RPMHPD_MMCX>; 3276 3277 phys = <&mdss_dsi1_phy>; 3278 phy-names = "dsi"; 3279 3280 #address-cells = <1>; 3281 #size-cells = <0>; 3282 3283 status = "disabled"; 3284 3285 ports { 3286 #address-cells = <1>; 3287 #size-cells = <0>; 3288 3289 port@0 { 3290 reg = <0>; 3291 3292 mdss_dsi1_in: endpoint { 3293 remote-endpoint = <&dpu_intf2_out>; 3294 }; 3295 }; 3296 3297 port@1 { 3298 reg = <1>; 3299 3300 mdss_dsi1_out: endpoint { 3301 }; 3302 }; 3303 }; 3304 }; 3305 3306 mdss_dsi1_phy: phy@ae97000 { 3307 compatible = "qcom,sm8750-dsi-phy-3nm"; 3308 reg = <0x0 0x0ae97000 0x0 0x200>, 3309 <0x0 0x0ae97200 0x0 0x280>, 3310 <0x0 0x0ae97500 0x0 0x400>; 3311 reg-names = "dsi_phy", 3312 "dsi_phy_lane", 3313 "dsi_pll"; 3314 3315 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3316 <&rpmhcc RPMH_CXO_CLK>; 3317 clock-names = "iface", 3318 "ref"; 3319 3320 #clock-cells = <1>; 3321 #phy-cells = <0>; 3322 3323 status = "disabled"; 3324 }; 3325 3326 mdss_dp0: displayport-controller@af54000 { 3327 compatible = "qcom,sm8750-dp", "qcom,sm8650-dp"; 3328 reg = <0x0 0xaf54000 0x0 0x104>, 3329 <0x0 0xaf54200 0x0 0xc0>, 3330 <0x0 0xaf55000 0x0 0x770>, 3331 <0x0 0xaf56000 0x0 0x9c>, 3332 <0x0 0xaf57000 0x0 0x9c>; 3333 3334 interrupts-extended = <&mdss 12>; 3335 3336 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3337 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3338 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3339 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3340 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 3341 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 3342 clock-names = "core_iface", 3343 "core_aux", 3344 "ctrl_link", 3345 "ctrl_link_iface", 3346 "stream_pixel", 3347 "stream_1_pixel"; 3348 3349 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3350 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 3351 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 3352 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3353 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3354 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3355 3356 operating-points-v2 = <&dp_opp_table>; 3357 3358 power-domains = <&rpmhpd RPMHPD_MMCX>; 3359 3360 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 3361 phy-names = "dp"; 3362 3363 #sound-dai-cells = <0>; 3364 3365 status = "disabled"; 3366 3367 dp_opp_table: opp-table { 3368 compatible = "operating-points-v2"; 3369 3370 opp-270000000 { 3371 opp-hz = /bits/ 64 <270000000>; 3372 required-opps = <&rpmhpd_opp_low_svs>; 3373 }; 3374 3375 opp-540000000 { 3376 opp-hz = /bits/ 64 <540000000>; 3377 required-opps = <&rpmhpd_opp_svs_l1>; 3378 }; 3379 3380 opp-810000000 { 3381 opp-hz = /bits/ 64 <810000000>; 3382 required-opps = <&rpmhpd_opp_nom>; 3383 }; 3384 }; 3385 3386 ports { 3387 #address-cells = <1>; 3388 #size-cells = <0>; 3389 3390 port@0 { 3391 reg = <0>; 3392 3393 mdss_dp0_in: endpoint { 3394 remote-endpoint = <&dpu_intf0_out>; 3395 }; 3396 }; 3397 3398 port@1 { 3399 reg = <1>; 3400 3401 mdss_dp0_out: endpoint { 3402 data-lanes = <0 1 2 3>; 3403 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 3404 }; 3405 }; 3406 }; 3407 }; 3408 }; 3409 3410 dispcc: clock-controller@af00000 { 3411 compatible = "qcom,sm8750-dispcc"; 3412 reg = <0x0 0x0af00000 0x0 0x20000>; 3413 3414 clocks = <&bi_tcxo_div2>, 3415 <&bi_tcxo_ao_div2>, 3416 <&gcc GCC_DISP_AHB_CLK>, 3417 <&sleep_clk>, 3418 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3419 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3420 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3421 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 3422 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3423 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3424 <0>, /* dp1 */ 3425 <0>, 3426 <0>, /* dp2 */ 3427 <0>, 3428 <0>, /* dp3 */ 3429 <0>; 3430 3431 power-domains = <&rpmhpd RPMHPD_MMCX>; 3432 required-opps = <&rpmhpd_opp_low_svs>; 3433 3434 #clock-cells = <1>; 3435 #reset-cells = <1>; 3436 #power-domain-cells = <1>; 3437 }; 3438 3439 pdc: interrupt-controller@b220000 { 3440 compatible = "qcom,sm8750-pdc", "qcom,pdc"; 3441 reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; 3442 3443 qcom,pdc-ranges = <0 745 51>, <51 527 47>, 3444 <98 609 32>, <130 717 12>, 3445 <142 251 5>, <147 796 16>; 3446 #interrupt-cells = <2>; 3447 interrupt-parent = <&intc>; 3448 interrupt-controller; 3449 }; 3450 3451 tsens0: thermal-sensor@c228000 { 3452 compatible = "qcom,sm8750-tsens", "qcom,tsens-v2"; 3453 reg = <0x0 0x0c228000 0x0 0x1000>, 3454 <0x0 0x0c222000 0x0 0x1000>; 3455 interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>; 3457 interrupt-names = "uplow", 3458 "critical"; 3459 #qcom,sensors = <15>; 3460 #thermal-sensor-cells = <1>; 3461 }; 3462 3463 tsens1: thermal-sensor@c229000 { 3464 compatible = "qcom,sm8750-tsens", "qcom,tsens-v2"; 3465 reg = <0x0 0x0c229000 0x0 0x1000>, 3466 <0x0 0x0c223000 0x0 0x1000>; 3467 interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>; 3469 interrupt-names = "uplow", 3470 "critical"; 3471 #qcom,sensors = <7>; 3472 #thermal-sensor-cells = <1>; 3473 }; 3474 3475 tsens2: thermal-sensor@c22a000 { 3476 compatible = "qcom,sm8750-tsens", "qcom,tsens-v2"; 3477 reg = <0x0 0x0c22a000 0x0 0x1000>, 3478 <0x0 0x0c224000 0x0 0x1000>; 3479 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>; 3481 interrupt-names = "uplow", 3482 "critical"; 3483 #qcom,sensors = <16>; 3484 #thermal-sensor-cells = <1>; 3485 }; 3486 3487 tsens3: thermal-sensor@c22b000 { 3488 compatible = "qcom,sm8750-tsens", "qcom,tsens-v2"; 3489 reg = <0x0 0x0c22b000 0x0 0x1000>, 3490 <0x0 0x0c225000 0x0 0x1000>; 3491 interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>; 3493 interrupt-names = "uplow", 3494 "critical"; 3495 #qcom,sensors = <9>; 3496 #thermal-sensor-cells = <1>; 3497 }; 3498 3499 aoss_qmp: power-management@c300000 { 3500 compatible = "qcom,sm8750-aoss-qmp", "qcom,aoss-qmp"; 3501 reg = <0x0 0x0c300000 0x0 0x400>; 3502 3503 interrupt-parent = <&ipcc>; 3504 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3505 IRQ_TYPE_EDGE_RISING>; 3506 3507 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3508 3509 #clock-cells = <0>; 3510 }; 3511 3512 sram@c3f0000 { 3513 compatible = "qcom,rpmh-stats"; 3514 reg = <0x0 0x0c3f0000 0x0 0x400>; 3515 qcom,qmp = <&aoss_qmp>; 3516 }; 3517 3518 spmi_bus: spmi@c400000 { 3519 compatible = "qcom,spmi-pmic-arb"; 3520 reg = <0x0 0x0c400000 0x0 0x3000>, 3521 <0x0 0x0c500000 0x0 0x400000>, 3522 <0x0 0x0c440000 0x0 0x80000>, 3523 <0x0 0x0c4c0000 0x0 0x10000>, 3524 <0x0 0x0c42d000 0x0 0x4000>; 3525 reg-names = "core", 3526 "chnls", 3527 "obsrvr", 3528 "intr", 3529 "cnfg"; 3530 3531 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3532 interrupt-names = "periph_irq"; 3533 3534 qcom,ee = <0>; 3535 qcom,channel = <0>; 3536 qcom,bus-id = <0>; 3537 3538 interrupt-controller; 3539 #interrupt-cells = <4>; 3540 3541 #address-cells = <2>; 3542 #size-cells = <0>; 3543 }; 3544 3545 tlmm: pinctrl@f100000 { 3546 compatible = "qcom,sm8750-tlmm"; 3547 reg = <0x0 0x0f100000 0x0 0x102000>; 3548 3549 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3550 3551 gpio-controller; 3552 #gpio-cells = <2>; 3553 3554 interrupt-controller; 3555 #interrupt-cells = <2>; 3556 3557 gpio-ranges = <&tlmm 0 0 216>; 3558 wakeup-parent = <&pdc>; 3559 3560 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3561 /* SDA, SCL */ 3562 pins = "gpio64", "gpio65"; 3563 function = "i2chub0_se0"; 3564 drive-strength = <2>; 3565 bias-pull-up; 3566 }; 3567 3568 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 3569 /* SDA, SCL */ 3570 pins = "gpio66", "gpio67"; 3571 function = "i2chub0_se1"; 3572 drive-strength = <2>; 3573 bias-pull-up; 3574 }; 3575 3576 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 3577 /* SDA, SCL */ 3578 pins = "gpio68", "gpio69"; 3579 function = "i2chub0_se2"; 3580 drive-strength = <2>; 3581 bias-pull-up; 3582 }; 3583 3584 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 3585 /* SDA, SCL */ 3586 pins = "gpio70", "gpio71"; 3587 function = "i2chub0_se3"; 3588 drive-strength = <2>; 3589 bias-pull-up; 3590 }; 3591 3592 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 3593 /* SDA, SCL */ 3594 pins = "gpio72", "gpio73"; 3595 function = "i2chub0_se4"; 3596 drive-strength = <2>; 3597 bias-pull-up; 3598 }; 3599 3600 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 3601 /* SDA, SCL */ 3602 pins = "gpio74", "gpio75"; 3603 function = "i2chub0_se5"; 3604 drive-strength = <2>; 3605 bias-pull-up; 3606 }; 3607 3608 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 3609 /* SDA, SCL */ 3610 pins = "gpio76", "gpio77"; 3611 function = "i2chub0_se6"; 3612 drive-strength = <2>; 3613 bias-pull-up; 3614 }; 3615 3616 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 3617 /* SDA, SCL */ 3618 pins = "gpio82", "gpio83"; 3619 function = "i2chub0_se7"; 3620 drive-strength = <2>; 3621 bias-pull-up; 3622 }; 3623 3624 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 3625 /* SDA, SCL */ 3626 pins = "gpio206", "gpio207"; 3627 function = "i2chub0_se8"; 3628 drive-strength = <2>; 3629 bias-pull-up; 3630 }; 3631 3632 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 3633 /* SDA, SCL */ 3634 pins = "gpio80", "gpio81"; 3635 function = "i2chub0_se9"; 3636 drive-strength = <2>; 3637 bias-pull-up; 3638 }; 3639 3640 pcie0_default_state: pcie0-default-state { 3641 perst-pins { 3642 pins = "gpio102"; 3643 function = "gpio"; 3644 drive-strength = <2>; 3645 bias-pull-down; 3646 }; 3647 3648 clkreq-pins { 3649 pins = "gpio103"; 3650 function = "pcie0_clk_req_n"; 3651 drive-strength = <2>; 3652 bias-pull-up; 3653 }; 3654 3655 wake-pins { 3656 pins = "gpio104"; 3657 function = "gpio"; 3658 drive-strength = <2>; 3659 bias-pull-up; 3660 }; 3661 }; 3662 3663 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3664 /* SDA, SCL */ 3665 pins = "gpio32", "gpio33"; 3666 function = "qup1_se0"; 3667 drive-strength = <2>; 3668 bias-pull-up; 3669 }; 3670 3671 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3672 /* SDA, SCL */ 3673 pins = "gpio36", "gpio37"; 3674 function = "qup1_se1"; 3675 drive-strength = <2>; 3676 bias-pull-up; 3677 }; 3678 3679 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3680 /* SDA, SCL */ 3681 pins = "gpio40", "gpio41"; 3682 function = "qup1_se2"; 3683 drive-strength = <2>; 3684 bias-pull-up; 3685 }; 3686 3687 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3688 /* SDA, SCL */ 3689 pins = "gpio44", "gpio45"; 3690 function = "qup1_se3"; 3691 drive-strength = <2>; 3692 bias-pull-up; 3693 }; 3694 3695 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3696 /* SDA, SCL */ 3697 pins = "gpio48", "gpio49"; 3698 function = "qup1_se4"; 3699 drive-strength = <2>; 3700 bias-pull-up; 3701 }; 3702 3703 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3704 /* SDA, SCL */ 3705 pins = "gpio52", "gpio53"; 3706 function = "qup1_se5"; 3707 drive-strength = <2>; 3708 bias-pull-up; 3709 }; 3710 3711 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3712 /* SDA, SCL */ 3713 pins = "gpio56", "gpio57"; 3714 function = "qup1_se6"; 3715 drive-strength = <2>; 3716 bias-pull-up; 3717 }; 3718 3719 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3720 /* SDA, SCL */ 3721 pins = "gpio0", "gpio1"; 3722 function = "qup2_se0"; 3723 drive-strength = <2>; 3724 bias-pull-up; 3725 }; 3726 3727 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3728 /* SDA, SCL */ 3729 pins = "gpio4", "gpio5"; 3730 function = "qup2_se1"; 3731 drive-strength = <2>; 3732 bias-pull-up; 3733 }; 3734 3735 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3736 /* SDA, SCL */ 3737 pins = "gpio8", "gpio9"; 3738 function = "qup2_se2"; 3739 drive-strength = <2>; 3740 bias-pull-up; 3741 }; 3742 3743 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3744 /* SDA, SCL */ 3745 pins = "gpio12", "gpio13"; 3746 function = "qup2_se3"; 3747 drive-strength = <2>; 3748 bias-pull-up; 3749 }; 3750 3751 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3752 /* SDA, SCL */ 3753 pins = "gpio16", "gpio17"; 3754 function = "qup2_se4"; 3755 drive-strength = <2>; 3756 bias-pull-up; 3757 }; 3758 3759 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3760 /* SDA, SCL */ 3761 pins = "gpio20", "gpio21"; 3762 function = "qup2_se5"; 3763 drive-strength = <2>; 3764 bias-pull-up; 3765 }; 3766 3767 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3768 /* SDA, SCL */ 3769 pins = "gpio28", "gpio29"; 3770 function = "qup2_se7"; 3771 drive-strength = <2>; 3772 bias-pull-up; 3773 }; 3774 3775 qup_spi0_cs: qup-spi0-cs-state { 3776 pins = "gpio35"; 3777 function = "qup1_se0"; 3778 drive-strength = <6>; 3779 bias-disable; 3780 }; 3781 3782 qup_spi0_data_clk: qup-spi0-data-clk-state { 3783 /* MISO, MOSI, CLK */ 3784 pins = "gpio32", "gpio33", "gpio34"; 3785 function = "qup1_se0"; 3786 drive-strength = <6>; 3787 bias-disable; 3788 }; 3789 3790 qup_spi1_cs: qup-spi1-cs-state { 3791 pins = "gpio39"; 3792 function = "qup1_se1"; 3793 drive-strength = <6>; 3794 bias-disable; 3795 }; 3796 3797 qup_spi1_data_clk: qup-spi1-data-clk-state { 3798 /* MISO, MOSI, CLK */ 3799 pins = "gpio36", "gpio37", "gpio38"; 3800 function = "qup1_se1"; 3801 drive-strength = <6>; 3802 bias-disable; 3803 }; 3804 3805 qup_spi2_cs: qup-spi2-cs-state { 3806 pins = "gpio43"; 3807 function = "qup1_se2"; 3808 drive-strength = <6>; 3809 bias-disable; 3810 }; 3811 3812 qup_spi2_data_clk: qup-spi2-data-clk-state { 3813 /* MISO, MOSI, CLK */ 3814 pins = "gpio40", "gpio41", "gpio42"; 3815 function = "qup1_se2"; 3816 drive-strength = <6>; 3817 bias-disable; 3818 }; 3819 3820 qup_spi3_cs: qup-spi3-cs-state { 3821 pins = "gpio47"; 3822 function = "qup1_se3"; 3823 drive-strength = <6>; 3824 bias-disable; 3825 }; 3826 3827 qup_spi3_data_clk: qup-spi3-data-clk-state { 3828 /* MISO, MOSI, CLK */ 3829 pins = "gpio44", "gpio45", "gpio46"; 3830 function = "qup1_se3"; 3831 drive-strength = <6>; 3832 bias-disable; 3833 }; 3834 3835 qup_spi4_cs: qup-spi4-cs-state { 3836 pins = "gpio51"; 3837 function = "qup1_se4"; 3838 drive-strength = <6>; 3839 bias-disable; 3840 }; 3841 3842 qup_spi4_data_clk: qup-spi4-data-clk-state { 3843 /* MISO, MOSI, CLK */ 3844 pins = "gpio48", "gpio49", "gpio50"; 3845 function = "qup1_se4"; 3846 drive-strength = <6>; 3847 bias-disable; 3848 }; 3849 3850 qup_spi5_cs: qup-spi5-cs-state { 3851 pins = "gpio55"; 3852 function = "qup1_se5"; 3853 drive-strength = <6>; 3854 bias-disable; 3855 }; 3856 3857 qup_spi5_data_clk: qup-spi5-data-clk-state { 3858 /* MISO, MOSI, CLK */ 3859 pins = "gpio52", "gpio53", "gpio54"; 3860 function = "qup1_se5"; 3861 drive-strength = <6>; 3862 bias-disable; 3863 }; 3864 3865 qup_spi6_cs: qup-spi6-cs-state { 3866 pins = "gpio59"; 3867 function = "qup1_se6"; 3868 drive-strength = <6>; 3869 bias-disable; 3870 }; 3871 3872 qup_spi6_data_clk: qup-spi6-data-clk-state { 3873 /* MISO, MOSI, CLK */ 3874 pins = "gpio56", "gpio57", "gpio58"; 3875 function = "qup1_se6"; 3876 drive-strength = <6>; 3877 bias-disable; 3878 }; 3879 3880 qup_spi8_cs: qup-spi8-cs-state { 3881 pins = "gpio3"; 3882 function = "qup2_se0"; 3883 drive-strength = <6>; 3884 bias-disable; 3885 }; 3886 3887 qup_spi8_data_clk: qup-spi8-data-clk-state { 3888 /* MISO, MOSI, CLK */ 3889 pins = "gpio0", "gpio1", "gpio2"; 3890 function = "qup2_se0"; 3891 drive-strength = <6>; 3892 bias-disable; 3893 }; 3894 3895 qup_spi9_cs: qup-spi9-cs-state { 3896 pins = "gpio7"; 3897 function = "qup2_se1"; 3898 drive-strength = <6>; 3899 bias-disable; 3900 }; 3901 3902 qup_spi9_data_clk: qup-spi9-data-clk-state { 3903 /* MISO, MOSI, CLK */ 3904 pins = "gpio4", "gpio5", "gpio6"; 3905 function = "qup2_se1"; 3906 drive-strength = <6>; 3907 bias-disable; 3908 }; 3909 3910 qup_spi10_cs: qup-spi10-cs-state { 3911 pins = "gpio11"; 3912 function = "qup2_se2"; 3913 drive-strength = <6>; 3914 bias-disable; 3915 }; 3916 3917 qup_spi10_data_clk: qup-spi10-data-clk-state { 3918 /* MISO, MOSI, CLK */ 3919 pins = "gpio8", "gpio9", "gpio10"; 3920 function = "qup2_se2"; 3921 drive-strength = <6>; 3922 bias-disable; 3923 }; 3924 3925 qup_spi11_cs: qup-spi11-cs-state { 3926 pins = "gpio15"; 3927 function = "qup2_se3"; 3928 drive-strength = <6>; 3929 bias-disable; 3930 }; 3931 3932 qup_spi11_data_clk: qup-spi11-data-clk-state { 3933 /* MISO, MOSI, CLK */ 3934 pins = "gpio12", "gpio13", "gpio14"; 3935 function = "qup2_se3"; 3936 drive-strength = <6>; 3937 bias-disable; 3938 }; 3939 3940 qup_spi12_cs: qup-spi12-cs-state { 3941 pins = "gpio19"; 3942 function = "qup2_se4"; 3943 drive-strength = <6>; 3944 bias-disable; 3945 }; 3946 3947 qup_spi12_data_clk: qup-spi12-data-clk-state { 3948 /* MISO, MOSI, CLK */ 3949 pins = "gpio16", "gpio17", "gpio18"; 3950 function = "qup2_se4"; 3951 drive-strength = <6>; 3952 bias-disable; 3953 }; 3954 3955 qup_spi13_cs: qup-spi13-cs-state { 3956 pins = "gpio23"; 3957 function = "qup2_se5"; 3958 drive-strength = <6>; 3959 bias-pull-up; 3960 }; 3961 3962 qup_spi13_data_clk: qup-spi13-data-clk-state { 3963 /* MISO, MOSI, CLK */ 3964 pins = "gpio20", "gpio21", "gpio22"; 3965 function = "qup2_se5"; 3966 drive-strength = <6>; 3967 bias-disable; 3968 }; 3969 3970 qup_spi15_cs: qup-spi15-cs-state { 3971 pins = "gpio31"; 3972 function = "qup2_se7"; 3973 drive-strength = <6>; 3974 bias-disable; 3975 }; 3976 3977 qup_spi15_data_clk: qup-spi15-data-clk-state { 3978 /* MISO, MOSI, CLK */ 3979 pins = "gpio28", "gpio29", "gpio30"; 3980 function = "qup2_se7"; 3981 drive-strength = <6>; 3982 bias-disable; 3983 }; 3984 3985 qup_uart7_default: qup-uart7-default-state { 3986 /* TX, RX */ 3987 pins = "gpio62", "gpio63"; 3988 function = "qup1_se7"; 3989 drive-strength = <2>; 3990 bias-disable; 3991 }; 3992 3993 qup_uart14_default: qup-uart14-default-state { 3994 /* TX, RX */ 3995 pins = "gpio26", "gpio27"; 3996 function = "qup2_se6"; 3997 drive-strength = <2>; 3998 bias-pull-up; 3999 }; 4000 4001 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 4002 /* CTS, RTS */ 4003 pins = "gpio24", "gpio25"; 4004 function = "qup2_se6"; 4005 drive-strength = <2>; 4006 bias-pull-down; 4007 }; 4008 4009 sdc2_sleep: sdc2-sleep-state { 4010 clk-pins { 4011 pins = "sdc2_clk"; 4012 drive-strength = <2>; 4013 bias-disable; 4014 }; 4015 4016 cmd-pins { 4017 pins = "sdc2_cmd"; 4018 drive-strength = <2>; 4019 bias-pull-up; 4020 }; 4021 4022 data-pins { 4023 pins = "sdc2_data"; 4024 drive-strength = <2>; 4025 bias-pull-up; 4026 }; 4027 }; 4028 4029 sdc2_default: sdc2-default-state { 4030 clk-pins { 4031 pins = "sdc2_clk"; 4032 drive-strength = <16>; 4033 bias-disable; 4034 }; 4035 4036 cmd-pins { 4037 pins = "sdc2_cmd"; 4038 drive-strength = <10>; 4039 bias-pull-up; 4040 }; 4041 4042 data-pins { 4043 pins = "sdc2_data"; 4044 drive-strength = <10>; 4045 bias-pull-up; 4046 }; 4047 }; 4048 }; 4049 4050 tcsrcc: clock-controller@f204008 { 4051 compatible = "qcom,sm8750-tcsr", "syscon"; 4052 reg = <0x0 0x0f204008 0x0 0x3004>; 4053 4054 clocks = <&rpmhcc RPMH_CXO_CLK>; 4055 4056 #clock-cells = <1>; 4057 #reset-cells = <1>; 4058 }; 4059 4060 stm@10002000 { 4061 compatible = "arm,coresight-stm", "arm,primecell"; 4062 reg = <0x0 0x10002000 0x0 0x1000>, 4063 <0x0 0x37280000 0x0 0x180000>; 4064 reg-names = "stm-base", 4065 "stm-stimulus-base"; 4066 4067 clocks = <&aoss_qmp>; 4068 clock-names = "apb_pclk"; 4069 4070 out-ports { 4071 port { 4072 stm_out: endpoint { 4073 remote-endpoint = <&funnel_in0_in7>; 4074 }; 4075 }; 4076 }; 4077 }; 4078 4079 tpda@10004000 { 4080 compatible = "qcom,coresight-tpda", "arm,primecell"; 4081 reg = <0x0 0x10004000 0x0 0x1000>; 4082 4083 clocks = <&aoss_qmp>; 4084 clock-names = "apb_pclk"; 4085 4086 in-ports { 4087 #address-cells = <1>; 4088 #size-cells = <0>; 4089 4090 port@1 { 4091 reg = <1>; 4092 4093 tpda_qdss_in1: endpoint { 4094 remote-endpoint = <&tpdm_spdm_out>; 4095 }; 4096 }; 4097 4098 }; 4099 4100 out-ports { 4101 port { 4102 tpda_qdss_out: endpoint { 4103 remote-endpoint = <&funnel_in0_in6>; 4104 }; 4105 }; 4106 }; 4107 }; 4108 4109 tpdm@1000f000 { 4110 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4111 reg = <0x0 0x1000f000 0x0 0x1000>; 4112 4113 clocks = <&aoss_qmp>; 4114 clock-names = "apb_pclk"; 4115 4116 qcom,cmb-element-bits = <64>; 4117 qcom,cmb-msrs-num = <32>; 4118 4119 out-ports { 4120 port { 4121 tpdm_spdm_out: endpoint { 4122 remote-endpoint = <&tpda_qdss_in1>; 4123 }; 4124 }; 4125 }; 4126 }; 4127 4128 funnel@10041000 { 4129 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4130 reg = <0x0 0x10041000 0x0 0x1000>; 4131 4132 clocks = <&aoss_qmp>; 4133 clock-names = "apb_pclk"; 4134 4135 in-ports { 4136 #address-cells = <1>; 4137 #size-cells = <0>; 4138 4139 port@0 { 4140 reg = <0>; 4141 4142 funnel_in0_in0: endpoint { 4143 remote-endpoint = <&tn_ag_out>; 4144 }; 4145 }; 4146 4147 port@6 { 4148 reg = <6>; 4149 4150 funnel_in0_in6: endpoint { 4151 remote-endpoint = <&tpda_qdss_out>; 4152 }; 4153 }; 4154 4155 port@7 { 4156 reg = <7>; 4157 4158 funnel_in0_in7: endpoint { 4159 remote-endpoint = <&stm_out>; 4160 }; 4161 }; 4162 }; 4163 4164 out-ports { 4165 port { 4166 funnel_in0_out: endpoint { 4167 remote-endpoint = <&funnel_aoss_in7>; 4168 }; 4169 }; 4170 }; 4171 }; 4172 4173 tpdm@10800000 { 4174 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4175 reg = <0x0 0x10800000 0x0 0x1000>; 4176 4177 clocks = <&aoss_qmp>; 4178 clock-names = "apb_pclk"; 4179 4180 qcom,dsb-element-bits = <32>; 4181 qcom,dsb-msrs-num = <32>; 4182 4183 out-ports { 4184 port { 4185 tpdm_modem0_out: endpoint { 4186 remote-endpoint = <&tpda_modem_in0>; 4187 }; 4188 }; 4189 }; 4190 }; 4191 4192 tpda@10803000 { 4193 compatible = "qcom,coresight-tpda", "arm,primecell"; 4194 reg = <0x0 0x10803000 0x0 0x1000>; 4195 4196 clocks = <&aoss_qmp>; 4197 clock-names = "apb_pclk"; 4198 4199 in-ports { 4200 #address-cells = <1>; 4201 #size-cells = <0>; 4202 4203 port@0 { 4204 reg = <0>; 4205 4206 tpda_modem_in0: endpoint { 4207 remote-endpoint = <&tpdm_modem0_out>; 4208 }; 4209 }; 4210 4211 port@1 { 4212 reg = <1>; 4213 4214 tpda_modem_in1: endpoint { 4215 remote-endpoint = <&tpdm_modem1_out>; 4216 }; 4217 }; 4218 }; 4219 4220 out-ports { 4221 port { 4222 tpda_modem_out: endpoint { 4223 remote-endpoint = <&funnel_modem_dl_in0>; 4224 }; 4225 }; 4226 }; 4227 }; 4228 4229 funnel@10804000 { 4230 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4231 reg = <0x0 0x10804000 0x0 0x1000>; 4232 4233 clocks = <&aoss_qmp>; 4234 clock-names = "apb_pclk"; 4235 4236 in-ports { 4237 port { 4238 funnel_modem_dl_in0: endpoint { 4239 remote-endpoint = <&tpda_modem_out>; 4240 }; 4241 }; 4242 }; 4243 4244 out-ports { 4245 port { 4246 funnel_modem_dl_out: endpoint { 4247 remote-endpoint = <&tn_ag_in13>; 4248 }; 4249 }; 4250 }; 4251 }; 4252 4253 cti@1080b000 { 4254 compatible = "arm,coresight-cti", "arm,primecell"; 4255 reg = <0x0 0x1080b000 0x0 0x1000>; 4256 4257 clocks = <&aoss_qmp>; 4258 clock-names = "apb_pclk"; 4259 }; 4260 4261 tpdm@1082c000 { 4262 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4263 reg = <0x0 0x1082c000 0x0 0x1000>; 4264 4265 clocks = <&aoss_qmp>; 4266 clock-names = "apb_pclk"; 4267 4268 qcom,dsb-msrs-num = <32>; 4269 4270 out-ports { 4271 port { 4272 tpdm_gcc_out: endpoint { 4273 remote-endpoint = <&tn_ag_in17>; 4274 }; 4275 }; 4276 }; 4277 }; 4278 4279 tpdm@10841000 { 4280 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4281 reg = <0x0 0x10841000 0x0 0x1000>; 4282 4283 clocks = <&aoss_qmp>; 4284 clock-names = "apb_pclk"; 4285 4286 qcom,cmb-msrs-num = <32>; 4287 4288 out-ports { 4289 port { 4290 tpdm_prng_out: endpoint { 4291 remote-endpoint = <&tn_ag_in18>; 4292 }; 4293 }; 4294 }; 4295 }; 4296 4297 tpdm@1084e000 { 4298 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4299 reg = <0x0 0x1084e000 0x0 0x1000>; 4300 4301 clocks = <&aoss_qmp>; 4302 clock-names = "apb_pclk"; 4303 4304 qcom,cmb-element-bits = <32>; 4305 qcom,cmb-msrs-num = <32>; 4306 4307 out-ports { 4308 port { 4309 tpdm_mm_bcv_out: endpoint { 4310 remote-endpoint = <&tpda_mm_in0>; 4311 }; 4312 }; 4313 }; 4314 }; 4315 4316 tpdm@1084f000 { 4317 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4318 reg = <0x0 0x1084f000 0x0 0x1000>; 4319 4320 clocks = <&aoss_qmp>; 4321 clock-names = "apb_pclk"; 4322 4323 qcom,cmb-element-bits = <32>; 4324 qcom,cmb-msrs-num = <32>; 4325 4326 out-ports { 4327 port { 4328 tpdm_mm_lmh_out: endpoint { 4329 remote-endpoint = <&tpda_mm_in1>; 4330 }; 4331 }; 4332 }; 4333 }; 4334 4335 tpdm@10850000 { 4336 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4337 reg = <0x0 0x10850000 0x0 0x1000>; 4338 4339 clocks = <&aoss_qmp>; 4340 clock-names = "apb_pclk"; 4341 4342 qcom,cmb-element-bits = <64>; 4343 qcom,cmb-msrs-num = <32>; 4344 4345 out-ports { 4346 port { 4347 tpdm_mm_dpm_out: endpoint { 4348 remote-endpoint = <&tpda_mm_in2>; 4349 }; 4350 }; 4351 }; 4352 }; 4353 4354 tpda@10851000 { 4355 compatible = "qcom,coresight-tpda", "arm,primecell"; 4356 reg = <0x0 0x10851000 0x0 0x1000>; 4357 4358 clocks = <&aoss_qmp>; 4359 clock-names = "apb_pclk"; 4360 4361 in-ports { 4362 #address-cells = <1>; 4363 #size-cells = <0>; 4364 4365 port@0 { 4366 reg = <0>; 4367 4368 tpda_mm_in0: endpoint { 4369 remote-endpoint = <&tpdm_mm_bcv_out>; 4370 }; 4371 }; 4372 4373 port@1 { 4374 reg = <1>; 4375 4376 tpda_mm_in1: endpoint { 4377 remote-endpoint = <&tpdm_mm_lmh_out>; 4378 }; 4379 }; 4380 4381 port@2 { 4382 reg = <2>; 4383 4384 tpda_mm_in2: endpoint { 4385 remote-endpoint = <&tpdm_mm_dpm_out>; 4386 }; 4387 }; 4388 }; 4389 4390 out-ports { 4391 port { 4392 tpda_mm_out: endpoint { 4393 remote-endpoint = <&tn_ag_in4>; 4394 }; 4395 }; 4396 }; 4397 }; 4398 4399 tpdm@10980000 { 4400 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4401 reg = <0x0 0x10980000 0x0 0x1000>; 4402 4403 clocks = <&aoss_qmp>; 4404 clock-names = "apb_pclk"; 4405 4406 qcom,dsb-element-bits = <32>; 4407 qcom,dsb-msrs-num = <32>; 4408 4409 out-ports { 4410 port { 4411 tpdm_cdsp_out: endpoint { 4412 remote-endpoint = <&tpda_cdsp_in0>; 4413 }; 4414 }; 4415 }; 4416 }; 4417 4418 tpda@10986000 { 4419 compatible = "qcom,coresight-tpda", "arm,primecell"; 4420 reg = <0x0 0x10986000 0x0 0x1000>; 4421 4422 clocks = <&aoss_qmp>; 4423 clock-names = "apb_pclk"; 4424 4425 in-ports { 4426 #address-cells = <1>; 4427 #size-cells = <0>; 4428 4429 port@0 { 4430 reg = <0>; 4431 4432 tpda_cdsp_in0: endpoint { 4433 remote-endpoint = <&tpdm_cdsp_out>; 4434 }; 4435 }; 4436 4437 port@1 { 4438 reg = <1>; 4439 4440 tpda_cdsp_in1: endpoint { 4441 remote-endpoint = <&tpdm_cdsp_llm_out>; 4442 }; 4443 }; 4444 4445 port@2 { 4446 reg = <2>; 4447 4448 tpda_cdsp_in2: endpoint { 4449 remote-endpoint = <&tpdm_cdsp_llm2_out>; 4450 }; 4451 }; 4452 }; 4453 4454 out-ports { 4455 port { 4456 tpda_cdsp_out: endpoint { 4457 remote-endpoint = <&funnel_cdsp_in0>; 4458 }; 4459 }; 4460 }; 4461 }; 4462 4463 funnel@10987000 { 4464 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4465 reg = <0x0 0x10987000 0x0 0x1000>; 4466 4467 clocks = <&aoss_qmp>; 4468 clock-names = "apb_pclk"; 4469 4470 in-ports { 4471 port { 4472 funnel_cdsp_in0: endpoint { 4473 remote-endpoint = <&tpda_cdsp_out>; 4474 }; 4475 }; 4476 }; 4477 4478 out-ports { 4479 port { 4480 funnel_cdsp_out: endpoint { 4481 remote-endpoint = <&tn_ag_in16>; 4482 }; 4483 }; 4484 }; 4485 }; 4486 4487 cti@1098b000 { 4488 compatible = "arm,coresight-cti", "arm,primecell"; 4489 reg = <0x0 0x1098b000 0x0 0x1000>; 4490 4491 clocks = <&aoss_qmp>; 4492 clock-names = "apb_pclk"; 4493 }; 4494 4495 tpdm@109a3000 { 4496 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4497 reg = <0x0 0x109a3000 0x0 0x1000>; 4498 4499 clocks = <&aoss_qmp>; 4500 clock-names = "apb_pclk"; 4501 4502 qcom,cmb-msrs-num = <32>; 4503 qcom,dsb-msrs-num = <32>; 4504 4505 out-ports { 4506 port { 4507 tpdm_pmu_out: endpoint { 4508 remote-endpoint = <&tn_ag_in29>; 4509 }; 4510 }; 4511 }; 4512 }; 4513 4514 tpdm@109a4000 { 4515 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4516 reg = <0x0 0x109a4000 0x0 0x1000>; 4517 4518 clocks = <&aoss_qmp>; 4519 clock-names = "apb_pclk"; 4520 4521 qcom,cmb-msrs-num = <32>; 4522 4523 out-ports { 4524 port { 4525 tpdm_ipcc_cmb_out: endpoint { 4526 remote-endpoint = <&tn_ag_in28>; 4527 }; 4528 }; 4529 }; 4530 }; 4531 4532 tpdm@109a5000 { 4533 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4534 reg = <0x0 0x109a5000 0x0 0x1000>; 4535 4536 clocks = <&aoss_qmp>; 4537 clock-names = "apb_pclk"; 4538 4539 qcom,dsb-msrs-num = <32>; 4540 4541 out-ports { 4542 port { 4543 tpdm_dl_mm_out: endpoint { 4544 remote-endpoint = <&tn_ag_in25>; 4545 }; 4546 }; 4547 }; 4548 }; 4549 4550 tpdm@109a6000 { 4551 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4552 reg = <0x0 0x109a6000 0x0 0x1000>; 4553 4554 clocks = <&aoss_qmp>; 4555 clock-names = "apb_pclk"; 4556 4557 qcom,dsb-msrs-num = <32>; 4558 4559 out-ports { 4560 port { 4561 tpdm_north_dsb_out: endpoint { 4562 remote-endpoint = <&tn_ag_in26>; 4563 }; 4564 }; 4565 }; 4566 }; 4567 4568 tpdm@109a7000 { 4569 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4570 reg = <0x0 0x109a7000 0x0 0x1000>; 4571 4572 clocks = <&aoss_qmp>; 4573 clock-names = "apb_pclk"; 4574 4575 qcom,dsb-msrs-num = <32>; 4576 4577 out-ports { 4578 port { 4579 tpdm_south_dsb_out: endpoint { 4580 remote-endpoint = <&tn_ag_in27>; 4581 }; 4582 }; 4583 }; 4584 }; 4585 4586 tpdm@109a8000 { 4587 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4588 reg = <0x0 0x109a8000 0x0 0x1000>; 4589 4590 clocks = <&aoss_qmp>; 4591 clock-names = "apb_pclk"; 4592 4593 qcom,cmb-msrs-num = <32>; 4594 4595 out-ports { 4596 port { 4597 tpdm_rdpm_cmb0_out: endpoint { 4598 remote-endpoint = <&tn_ag_in30>; 4599 }; 4600 }; 4601 }; 4602 }; 4603 4604 tpdm@109a9000 { 4605 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4606 reg = <0x0 0x109a9000 0x0 0x1000>; 4607 4608 clocks = <&aoss_qmp>; 4609 clock-names = "apb_pclk"; 4610 4611 qcom,cmb-msrs-num = <32>; 4612 4613 out-ports { 4614 port { 4615 tpdm_rdpm_cmb1_out: endpoint { 4616 remote-endpoint = <&tn_ag_in31>; 4617 }; 4618 }; 4619 }; 4620 }; 4621 4622 tpdm@109aa000 { 4623 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4624 reg = <0x0 0x109aa000 0x0 0x1000>; 4625 4626 clocks = <&aoss_qmp>; 4627 clock-names = "apb_pclk"; 4628 4629 qcom,cmb-msrs-num = <32>; 4630 4631 out-ports { 4632 port { 4633 tpdm_rdpm_cmb2_out: endpoint { 4634 remote-endpoint = <&tn_ag_in32>; 4635 }; 4636 }; 4637 }; 4638 }; 4639 4640 tn@109ab000 { 4641 compatible = "qcom,coresight-tnoc", "arm,primecell"; 4642 reg = <0x0 0x109ab000 0x0 0x4200>; 4643 4644 clocks = <&aoss_qmp>; 4645 clock-names = "apb_pclk"; 4646 4647 in-ports { 4648 #address-cells = <1>; 4649 #size-cells = <0>; 4650 4651 port@4 { 4652 reg = <4>; 4653 4654 tn_ag_in4: endpoint { 4655 remote-endpoint = <&tpda_mm_out>; 4656 }; 4657 }; 4658 4659 port@d { 4660 reg = <0xd>; 4661 4662 tn_ag_in13: endpoint { 4663 remote-endpoint = <&funnel_modem_dl_out>; 4664 }; 4665 }; 4666 4667 port@10 { 4668 reg = <0x10>; 4669 4670 tn_ag_in16: endpoint { 4671 remote-endpoint = <&funnel_cdsp_out>; 4672 }; 4673 }; 4674 4675 port@11 { 4676 reg = <0x11>; 4677 4678 tn_ag_in17: endpoint { 4679 remote-endpoint = <&tpdm_gcc_out>; 4680 }; 4681 }; 4682 4683 port@12 { 4684 reg = <0x12>; 4685 4686 tn_ag_in18: endpoint { 4687 remote-endpoint = <&tpdm_prng_out>; 4688 }; 4689 }; 4690 4691 port@13 { 4692 reg = <0x13>; 4693 4694 tn_ag_in19: endpoint { 4695 remote-endpoint = <&tpdm_qm_out>; 4696 }; 4697 }; 4698 4699 port@19 { 4700 reg = <0x19>; 4701 4702 tn_ag_in25: endpoint { 4703 remote-endpoint = <&tpdm_dl_mm_out>; 4704 }; 4705 }; 4706 4707 port@1a { 4708 reg = <0x1a>; 4709 4710 tn_ag_in26: endpoint { 4711 remote-endpoint = <&tpdm_north_dsb_out>; 4712 }; 4713 }; 4714 4715 port@1b { 4716 reg = <0x1b>; 4717 4718 tn_ag_in27: endpoint { 4719 remote-endpoint = <&tpdm_south_dsb_out>; 4720 }; 4721 }; 4722 4723 port@1c { 4724 reg = <0x1c>; 4725 4726 tn_ag_in28: endpoint { 4727 remote-endpoint = <&tpdm_ipcc_cmb_out>; 4728 }; 4729 }; 4730 4731 port@1d { 4732 reg = <0x1d>; 4733 4734 tn_ag_in29: endpoint { 4735 remote-endpoint = <&tpdm_pmu_out>; 4736 }; 4737 }; 4738 4739 port@1e { 4740 reg = <0x1e>; 4741 4742 tn_ag_in30: endpoint { 4743 remote-endpoint = <&tpdm_rdpm_cmb0_out>; 4744 }; 4745 }; 4746 4747 port@1f { 4748 reg = <0x1f>; 4749 4750 tn_ag_in31: endpoint { 4751 remote-endpoint = <&tpdm_rdpm_cmb1_out>; 4752 }; 4753 }; 4754 4755 port@20 { 4756 reg = <0x20>; 4757 4758 tn_ag_in32: endpoint { 4759 remote-endpoint = <&tpdm_rdpm_cmb2_out>; 4760 }; 4761 }; 4762 }; 4763 4764 out-ports { 4765 port { 4766 tn_ag_out: endpoint { 4767 remote-endpoint = <&funnel_in0_in0>; 4768 }; 4769 }; 4770 }; 4771 }; 4772 4773 tpdm@109d0000 { 4774 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4775 reg = <0x0 0x109d0000 0x0 0x1000>; 4776 4777 clocks = <&aoss_qmp>; 4778 clock-names = "apb_pclk"; 4779 4780 qcom,dsb-msrs-num = <32>; 4781 4782 out-ports { 4783 port { 4784 tpdm_qm_out: endpoint { 4785 remote-endpoint = <&tn_ag_in19>; 4786 }; 4787 }; 4788 }; 4789 }; 4790 4791 funnel@10b04000 { 4792 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4793 reg = <0x0 0x10b04000 0x0 0x1000>; 4794 4795 clocks = <&aoss_qmp>; 4796 clock-names = "apb_pclk"; 4797 4798 in-ports { 4799 #address-cells = <1>; 4800 #size-cells = <0>; 4801 4802 port@6 { 4803 reg = <6>; 4804 4805 funnel_aoss_in6: endpoint { 4806 remote-endpoint = <&tpda_aoss_out>; 4807 }; 4808 }; 4809 4810 port@7 { 4811 reg = <7>; 4812 4813 funnel_aoss_in7: endpoint { 4814 remote-endpoint = <&funnel_in0_out>; 4815 }; 4816 }; 4817 4818 }; 4819 4820 out-ports { 4821 port { 4822 funnel_aoss_out: endpoint { 4823 remote-endpoint = <&tmc_etf_in>; 4824 }; 4825 }; 4826 }; 4827 }; 4828 4829 tmc@10b05000 { 4830 compatible = "arm,coresight-tmc", "arm,primecell"; 4831 reg = <0x0 0x10b05000 0x0 0x1000>; 4832 4833 clocks = <&aoss_qmp>; 4834 clock-names = "apb_pclk"; 4835 4836 in-ports { 4837 port { 4838 tmc_etf_in: endpoint { 4839 remote-endpoint = <&funnel_aoss_out>; 4840 }; 4841 }; 4842 }; 4843 }; 4844 4845 tpda@10b08000 { 4846 compatible = "qcom,coresight-tpda", "arm,primecell"; 4847 reg = <0x0 0x10b08000 0x0 0x1000>; 4848 4849 clocks = <&aoss_qmp>; 4850 clock-names = "apb_pclk"; 4851 4852 in-ports { 4853 #address-cells = <1>; 4854 #size-cells = <0>; 4855 4856 port@0 { 4857 reg = <0>; 4858 4859 tpda_aoss_in0: endpoint { 4860 remote-endpoint = <&tpdm_swao_prio0_out>; 4861 }; 4862 }; 4863 4864 port@1 { 4865 reg = <1>; 4866 4867 tpda_aoss_in1: endpoint { 4868 remote-endpoint = <&tpdm_swao_prio1_out>; 4869 }; 4870 }; 4871 4872 port@2 { 4873 reg = <2>; 4874 4875 tpda_aoss_in2: endpoint { 4876 remote-endpoint = <&tpdm_swao_prio2_out>; 4877 }; 4878 }; 4879 4880 port@3 { 4881 reg = <3>; 4882 4883 tpda_aoss_in3: endpoint { 4884 remote-endpoint = <&tpdm_swao_prio3_out>; 4885 }; 4886 }; 4887 4888 port@4 { 4889 reg = <4>; 4890 4891 tpda_aoss_in4: endpoint { 4892 remote-endpoint =<&tpdm_swao_out>; 4893 }; 4894 }; 4895 }; 4896 4897 out-ports { 4898 port { 4899 tpda_aoss_out: endpoint { 4900 remote-endpoint = <&funnel_aoss_in6>; 4901 }; 4902 }; 4903 }; 4904 }; 4905 4906 tpdm@10b09000 { 4907 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4908 reg = <0x0 0x10b09000 0x0 0x1000>; 4909 4910 clocks = <&aoss_qmp>; 4911 clock-names = "apb_pclk"; 4912 4913 qcom,cmb-element-bits = <64>; 4914 qcom,cmb-msrs-num = <32>; 4915 4916 out-ports { 4917 port { 4918 tpdm_swao_prio0_out: endpoint { 4919 remote-endpoint = <&tpda_aoss_in0>; 4920 }; 4921 }; 4922 }; 4923 }; 4924 4925 tpdm@10b0a000 { 4926 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4927 reg = <0x0 0x10b0a000 0x0 0x1000>; 4928 4929 clocks = <&aoss_qmp>; 4930 clock-names = "apb_pclk"; 4931 4932 qcom,cmb-element-bits = <64>; 4933 qcom,cmb-msrs-num = <32>; 4934 4935 out-ports { 4936 port { 4937 tpdm_swao_prio1_out: endpoint { 4938 remote-endpoint = <&tpda_aoss_in1>; 4939 }; 4940 }; 4941 }; 4942 }; 4943 4944 tpdm@10b0b000 { 4945 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4946 reg = <0x0 0x10b0b000 0x0 0x1000>; 4947 4948 clocks = <&aoss_qmp>; 4949 clock-names = "apb_pclk"; 4950 4951 qcom,cmb-element-bits = <64>; 4952 qcom,cmb-msrs-num = <32>; 4953 4954 out-ports { 4955 port { 4956 tpdm_swao_prio2_out: endpoint { 4957 remote-endpoint = <&tpda_aoss_in2>; 4958 }; 4959 }; 4960 }; 4961 }; 4962 4963 tpdm@10b0c000 { 4964 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4965 reg = <0x0 0x10b0c000 0x0 0x1000>; 4966 4967 clocks = <&aoss_qmp>; 4968 clock-names = "apb_pclk"; 4969 4970 qcom,cmb-element-bits = <64>; 4971 qcom,cmb-msrs-num = <32>; 4972 4973 out-ports { 4974 port { 4975 tpdm_swao_prio3_out: endpoint { 4976 remote-endpoint = <&tpda_aoss_in3>; 4977 }; 4978 }; 4979 }; 4980 }; 4981 4982 tpdm@10b0d000 { 4983 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4984 reg = <0x0 0x10b0d000 0x0 0x1000>; 4985 4986 clocks = <&aoss_qmp>; 4987 clock-names = "apb_pclk"; 4988 4989 qcom,dsb-element-bits = <32>; 4990 qcom,dsb-msrs-num = <32>; 4991 4992 out-ports { 4993 port { 4994 tpdm_swao_out: endpoint { 4995 remote-endpoint = <&tpda_aoss_in4>; 4996 }; 4997 }; 4998 }; 4999 }; 5000 5001 apps_smmu: iommu@15000000 { 5002 compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5003 reg = <0x0 0x15000000 0x0 0x100000>; 5004 5005 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5006 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5007 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5008 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5009 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5010 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5011 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5012 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5013 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5014 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5015 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5016 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5017 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5018 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5019 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5020 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5021 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5022 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5023 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5024 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5025 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5026 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5027 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5028 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5029 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5030 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5031 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5032 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5033 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5034 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5035 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5036 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5037 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5038 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5039 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5040 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5041 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5042 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5043 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5044 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5045 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5046 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5047 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5048 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5049 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5050 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5051 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5052 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5053 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5055 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5056 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5057 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5058 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5061 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5069 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 5118 5119 #iommu-cells = <2>; 5120 #global-interrupts = <1>; 5121 5122 dma-coherent; 5123 }; 5124 5125 intc: interrupt-controller@16000000 { 5126 compatible = "arm,gic-v3"; 5127 reg = <0x0 0x16000000 0x0 0x10000>, 5128 <0x0 0x16080000 0x0 0x200000>; 5129 5130 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5131 5132 #interrupt-cells = <3>; 5133 interrupt-controller; 5134 5135 #redistributor-regions = <1>; 5136 redistributor-stride = <0x0 0x40000>; 5137 5138 #address-cells = <2>; 5139 #size-cells = <2>; 5140 ranges; 5141 5142 gic_its: msi-controller@16040000 { 5143 compatible = "arm,gic-v3-its"; 5144 reg = <0x0 0x16040000 0x0 0x40000>; 5145 5146 msi-controller; 5147 #msi-cells = <1>; 5148 }; 5149 }; 5150 5151 pcie0: pcie@1c00000 { 5152 device_type = "pci"; 5153 compatible = "qcom,pcie-sm8750", "qcom,pcie-sm8550"; 5154 reg = <0x0 0x01c00000 0x0 0x3000>, 5155 <0x0 0x40000000 0x0 0xf1d>, 5156 <0x0 0x40000f20 0x0 0xa8>, 5157 <0x0 0x40001000 0x0 0x1000>, 5158 <0x0 0x40100000 0x0 0x100000>, 5159 <0x0 0x01c03000 0x0 0x1000>; 5160 reg-names = "parf", 5161 "dbi", 5162 "elbi", 5163 "atu", 5164 "config", 5165 "mhi"; 5166 5167 #address-cells = <3>; 5168 #size-cells = <2>; 5169 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 5170 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>, 5171 <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x00000000>; 5172 bus-range = <0x00 0xff>; 5173 5174 dma-coherent; 5175 5176 linux,pci-domain = <0>; 5177 5178 msi-map = <0x0 &gic_its 0x1400 0x1>, 5179 <0x100 &gic_its 0x1401 0x1>; 5180 msi-map-mask = <0xff00>; 5181 5182 num-lanes = <2>; 5183 5184 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 5185 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 5186 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 5187 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 5188 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 5189 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 5190 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 5191 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 5192 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 5193 interrupt-names = "msi0", 5194 "msi1", 5195 "msi2", 5196 "msi3", 5197 "msi4", 5198 "msi5", 5199 "msi6", 5200 "msi7", 5201 "global"; 5202 5203 #interrupt-cells = <1>; 5204 interrupt-map-mask = <0 0 0 0x7>; 5205 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 5206 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 5207 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 5208 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 5209 5210 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 5211 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 5212 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 5213 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 5214 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 5215 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 5216 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 5217 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 5218 clock-names = "aux", 5219 "cfg", 5220 "bus_master", 5221 "bus_slave", 5222 "slave_q2a", 5223 "ddrss_sf_tbu", 5224 "noc_aggr", 5225 "cnoc_sf_axi"; 5226 5227 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 5228 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5229 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5230 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 5231 interconnect-names = "pcie-mem", 5232 "cpu-pcie"; 5233 5234 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 5235 <0x100 &apps_smmu 0x1401 0x1>; 5236 5237 resets = <&gcc GCC_PCIE_0_BCR>; 5238 reset-names = "pci"; 5239 5240 power-domains = <&gcc GCC_PCIE_0_GDSC>; 5241 5242 operating-points-v2 = <&pcie0_opp_table>; 5243 5244 status = "disabled"; 5245 5246 pcie0_opp_table: opp-table { 5247 compatible = "operating-points-v2"; 5248 5249 /* GEN 1 x1 */ 5250 opp-2500000 { 5251 opp-hz = /bits/ 64 <2500000>; 5252 required-opps = <&rpmhpd_opp_low_svs>; 5253 opp-peak-kBps = <250000 1>; 5254 }; 5255 5256 /* GEN 1 x2 and GEN 2 x1 */ 5257 opp-5000000 { 5258 opp-hz = /bits/ 64 <5000000>; 5259 required-opps = <&rpmhpd_opp_low_svs>; 5260 opp-peak-kBps = <500000 1>; 5261 }; 5262 5263 /* GEN 2 x2 */ 5264 opp-10000000 { 5265 opp-hz = /bits/ 64 <10000000>; 5266 required-opps = <&rpmhpd_opp_low_svs>; 5267 opp-peak-kBps = <1000000 1>; 5268 }; 5269 5270 /* GEN 3 x1 */ 5271 opp-8000000 { 5272 opp-hz = /bits/ 64 <8000000>; 5273 required-opps = <&rpmhpd_opp_nom>; 5274 opp-peak-kBps = <984500 1>; 5275 }; 5276 5277 /* GEN 3 x2 */ 5278 opp-16000000 { 5279 opp-hz = /bits/ 64 <16000000>; 5280 required-opps = <&rpmhpd_opp_nom>; 5281 opp-peak-kBps = <1969000 1>; 5282 }; 5283 5284 }; 5285 5286 pcieport0: pcie@0 { 5287 device_type = "pci"; 5288 reg = <0x0 0x0 0x0 0x0 0x0>; 5289 bus-range = <0x01 0xff>; 5290 5291 #address-cells = <3>; 5292 #size-cells = <2>; 5293 ranges; 5294 phys = <&pcie0_phy>; 5295 }; 5296 }; 5297 5298 pcie0_phy: phy@1c06000 { 5299 compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy"; 5300 reg = <0 0x01c06000 0 0x2000>; 5301 5302 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 5303 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 5304 <&tcsrcc TCSR_PCIE_0_CLKREF_EN>, 5305 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 5306 <&gcc GCC_PCIE_0_PIPE_CLK>; 5307 clock-names = "aux", 5308 "cfg_ahb", 5309 "ref", 5310 "rchng", 5311 "pipe"; 5312 5313 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 5314 assigned-clock-rates = <100000000>; 5315 5316 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 5317 reset-names = "phy"; 5318 5319 power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>; 5320 5321 #clock-cells = <0>; 5322 clock-output-names = "pcie0_pipe_clk"; 5323 5324 #phy-cells = <0>; 5325 5326 status = "disabled"; 5327 }; 5328 5329 ufs_mem_phy: phy@1d80000 { 5330 compatible = "qcom,sm8750-qmp-ufs-phy"; 5331 reg = <0x0 0x01d80000 0x0 0x2000>; 5332 5333 clocks = <&rpmhcc RPMH_CXO_CLK>, 5334 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 5335 <&tcsrcc TCSR_UFS_CLKREF_EN>; 5336 5337 clock-names = "ref", 5338 "ref_aux", 5339 "qref"; 5340 5341 resets = <&ufs_mem_hc 0>; 5342 reset-names = "ufsphy"; 5343 5344 power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; 5345 5346 #clock-cells = <1>; 5347 #phy-cells = <0>; 5348 5349 status = "disabled"; 5350 }; 5351 5352 ufs_mem_hc: ufs@1d84000 { 5353 compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 5354 reg = <0x0 0x01d84000 0x0 0x3000>; 5355 5356 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 5357 5358 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 5359 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 5360 <&gcc GCC_UFS_PHY_AHB_CLK>, 5361 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 5362 <&rpmhcc RPMH_LN_BB_CLK3>, 5363 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 5364 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 5365 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 5366 clock-names = "core_clk", 5367 "bus_aggr_clk", 5368 "iface_clk", 5369 "core_clk_unipro", 5370 "ref_clk", 5371 "tx_lane0_sync_clk", 5372 "rx_lane0_sync_clk", 5373 "rx_lane1_sync_clk"; 5374 5375 operating-points-v2 = <&ufs_opp_table>; 5376 5377 resets = <&gcc GCC_UFS_PHY_BCR>; 5378 reset-names = "rst"; 5379 5380 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 5381 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5382 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5383 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5384 interconnect-names = "ufs-ddr", 5385 "cpu-ufs"; 5386 5387 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 5388 required-opps = <&rpmhpd_opp_nom>; 5389 5390 iommus = <&apps_smmu 0x60 0>; 5391 dma-coherent; 5392 5393 lanes-per-direction = <2>; 5394 5395 phys = <&ufs_mem_phy>; 5396 phy-names = "ufsphy"; 5397 5398 #reset-cells = <1>; 5399 5400 status = "disabled"; 5401 5402 ufs_opp_table: opp-table { 5403 compatible = "operating-points-v2"; 5404 5405 opp-100000000 { 5406 opp-hz = /bits/ 64 <100000000>, 5407 /bits/ 64 <0>, 5408 /bits/ 64 <0>, 5409 /bits/ 64 <100000000>, 5410 /bits/ 64 <0>, 5411 /bits/ 64 <0>, 5412 /bits/ 64 <0>, 5413 /bits/ 64 <0>; 5414 required-opps = <&rpmhpd_opp_low_svs>; 5415 }; 5416 5417 opp-403000000 { 5418 opp-hz = /bits/ 64 <403000000>, 5419 /bits/ 64 <0>, 5420 /bits/ 64 <0>, 5421 /bits/ 64 <403000000>, 5422 /bits/ 64 <0>, 5423 /bits/ 64 <0>, 5424 /bits/ 64 <0>, 5425 /bits/ 64 <0>; 5426 required-opps = <&rpmhpd_opp_nom>; 5427 }; 5428 }; 5429 }; 5430 5431 cpucp_mbox: mailbox@16430000 { 5432 compatible = "qcom,sm8750-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; 5433 reg = <0x0 0x16430000 0x0 0x8000>, <0x0 0x17830000 0x0 0x8000>; 5434 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 5435 #mbox-cells = <1>; 5436 }; 5437 5438 apps_rsc: rsc@16500000 { 5439 compatible = "qcom,rpmh-rsc"; 5440 reg = <0x0 0x16500000 0x0 0x10000>, 5441 <0x0 0x16510000 0x0 0x10000>, 5442 <0x0 0x16520000 0x0 0x10000>; 5443 reg-names = "drv-0", 5444 "drv-1", 5445 "drv-2"; 5446 5447 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5448 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5449 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5450 qcom,tcs-offset = <0xd00>; 5451 qcom,drv-id = <2>; 5452 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 5453 <WAKE_TCS 2>, <CONTROL_TCS 0>; 5454 5455 label = "apps_rsc"; 5456 5457 power-domains = <&system_pd>; 5458 5459 apps_bcm_voter: bcm-voter { 5460 compatible = "qcom,bcm-voter"; 5461 }; 5462 5463 rpmhcc: clock-controller { 5464 compatible = "qcom,sm8750-rpmh-clk"; 5465 5466 clocks = <&xo_board>; 5467 clock-names = "xo"; 5468 5469 #clock-cells = <1>; 5470 }; 5471 5472 rpmhpd: power-controller { 5473 compatible = "qcom,sm8750-rpmhpd"; 5474 5475 operating-points-v2 = <&rpmhpd_opp_table>; 5476 5477 #power-domain-cells = <1>; 5478 5479 rpmhpd_opp_table: opp-table { 5480 compatible = "operating-points-v2"; 5481 5482 rpmhpd_opp_ret: opp-16 { 5483 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5484 }; 5485 5486 rpmhpd_opp_min_svs: opp-48 { 5487 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5488 }; 5489 5490 rpmhpd_opp_low_svs_d3: opp-50 { 5491 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>; 5492 }; 5493 5494 rpmhpd_opp_low_svs_d2: opp-52 { 5495 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5496 }; 5497 5498 rpmhpd_opp_low_svs_d1: opp-56 { 5499 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5500 }; 5501 5502 rpmhpd_opp_low_svs_d0: opp-60 { 5503 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5504 }; 5505 5506 rpmhpd_opp_low_svs: opp-64 { 5507 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5508 }; 5509 5510 rpmhpd_opp_low_svs_l1: opp-80 { 5511 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5512 }; 5513 5514 rpmhpd_opp_svs: opp-128 { 5515 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5516 }; 5517 5518 rpmhpd_opp_svs_l0: opp-144 { 5519 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5520 }; 5521 5522 rpmhpd_opp_svs_l1: opp-192 { 5523 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5524 }; 5525 5526 rpmhpd_opp_svs_l2: opp-224 { 5527 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5528 }; 5529 5530 rpmhpd_opp_nom: opp-256 { 5531 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5532 }; 5533 5534 rpmhpd_opp_nom_l1: opp-320 { 5535 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5536 }; 5537 5538 rpmhpd_opp_nom_l2: opp-336 { 5539 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5540 }; 5541 5542 rpmhpd_opp_turbo: opp-384 { 5543 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5544 }; 5545 5546 rpmhpd_opp_turbo_l1: opp-416 { 5547 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5548 }; 5549 5550 rpmhpd_opp_turbo_l2: opp-432 { 5551 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 5552 }; 5553 5554 rpmhpd_opp_turbo_l3: opp-448 { 5555 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 5556 }; 5557 5558 rpmhpd_opp_turbo_l4: opp-452 { 5559 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 5560 }; 5561 5562 rpmhpd_opp_super_turbo_no_cpr: opp-480 { 5563 opp-level = 5564 <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>; 5565 }; 5566 }; 5567 }; 5568 }; 5569 5570 timer@16800000 { 5571 compatible = "arm,armv7-timer-mem"; 5572 reg = <0x0 0x16800000 0x0 0x1000>; 5573 5574 #address-cells = <2>; 5575 #size-cells = <1>; 5576 ranges = <0 0 0 0 0x20000000>; 5577 5578 frame@16801000 { 5579 reg = <0x0 0x16801000 0x1000>, 5580 <0x0 0x16802000 0x1000>; 5581 5582 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5583 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5584 5585 frame-number = <0>; 5586 }; 5587 5588 frame@16803000 { 5589 reg = <0x0 0x16803000 0x1000>; 5590 5591 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5592 5593 frame-number = <1>; 5594 5595 status = "disabled"; 5596 }; 5597 5598 frame@16805000 { 5599 reg = <0x0 0x16805000 0x1000>; 5600 5601 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5602 5603 frame-number = <2>; 5604 5605 status = "disabled"; 5606 }; 5607 5608 frame@16807000 { 5609 reg = <0x0 0x16807000 0x1000>; 5610 5611 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5612 5613 frame-number = <3>; 5614 5615 status = "disabled"; 5616 }; 5617 5618 frame@16809000 { 5619 reg = <0x0 0x16809000 0x1000>; 5620 5621 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5622 5623 frame-number = <4>; 5624 5625 status = "disabled"; 5626 }; 5627 5628 frame@1680b000 { 5629 reg = <0x0 0x1680b000 0x1000>; 5630 5631 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5632 5633 frame-number = <5>; 5634 5635 status = "disabled"; 5636 }; 5637 5638 frame@1680d000 { 5639 reg = <0x0 0x1680d000 0x1000>; 5640 5641 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5642 5643 frame-number = <6>; 5644 5645 status = "disabled"; 5646 }; 5647 }; 5648 5649 sram: sram@17b4e000 { 5650 compatible = "mmio-sram"; 5651 reg = <0x0 0x17b4e000 0x0 0x400>; 5652 5653 #address-cells = <1>; 5654 #size-cells = <1>; 5655 ranges = <0x0 0x0 0x17b4e000 0x400>; 5656 5657 cpu_scp_lpri0: scp-sram-section@0 { 5658 compatible = "arm,scmi-shmem"; 5659 reg = <0x0 0x200>; 5660 }; 5661 5662 cpu_scp_lpri1: scp-sram-section@200 { 5663 compatible = "arm,scmi-shmem"; 5664 reg = <0x200 0x200>; 5665 }; 5666 }; 5667 5668 /* cluster0 */ 5669 pmu@240b3400 { 5670 compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon"; 5671 reg = <0x0 0x240b3400 0x0 0x600>; 5672 5673 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5674 5675 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5676 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5677 5678 operating-points-v2 = <&cpu_bwmon_opp_table>; 5679 5680 nonposted-mmio; 5681 5682 cpu_bwmon_opp_table: opp-table { 5683 compatible = "operating-points-v2"; 5684 5685 opp-0 { 5686 opp-peak-kBps = <800000>; 5687 }; 5688 5689 opp-1 { 5690 opp-peak-kBps = <2188000>; 5691 }; 5692 5693 opp-2 { 5694 opp-peak-kBps = <5414400>; 5695 }; 5696 5697 opp-3 { 5698 opp-peak-kBps = <6220800>; 5699 }; 5700 5701 opp-4 { 5702 opp-peak-kBps = <6835200>; 5703 }; 5704 5705 opp-5 { 5706 opp-peak-kBps = <8371200>; 5707 }; 5708 5709 opp-6 { 5710 opp-peak-kBps = <10944000>; 5711 }; 5712 5713 opp-7 { 5714 opp-peak-kBps = <12748800>; 5715 }; 5716 5717 opp-8 { 5718 opp-peak-kBps = <14745600>; 5719 }; 5720 5721 opp-9 { 5722 opp-peak-kBps = <16896000>; 5723 }; 5724 5725 opp-10 { 5726 opp-peak-kBps = <19046400>; 5727 }; 5728 }; 5729 }; 5730 5731 /* cluster1 */ 5732 pmu@240b7400 { 5733 compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon"; 5734 reg = <0x0 0x240b7400 0x0 0x600>; 5735 5736 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5737 5738 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5739 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5740 5741 operating-points-v2 = <&cpu_bwmon_opp_table>; 5742 }; 5743 5744 gem_noc: interconnect@24100000 { 5745 compatible = "qcom,sm8750-gem-noc"; 5746 reg = <0x0 0x24100000 0x0 0x14b080>; 5747 qcom,bcm-voters = <&apps_bcm_voter>; 5748 #interconnect-cells = <2>; 5749 }; 5750 5751 system-cache-controller@24800000 { 5752 compatible = "qcom,sm8750-llcc"; 5753 reg = <0x0 0x24800000 0x0 0x200000>, 5754 <0x0 0x25800000 0x0 0x200000>, 5755 <0x0 0x24c00000 0x0 0x200000>, 5756 <0x0 0x25c00000 0x0 0x200000>, 5757 <0x0 0x26800000 0x0 0x200000>, 5758 <0x0 0x26c00000 0x0 0x200000>; 5759 reg-names = "llcc0_base", 5760 "llcc1_base", 5761 "llcc2_base", 5762 "llcc3_base", 5763 "llcc_broadcast_base", 5764 "llcc_broadcast_and_base"; 5765 5766 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 5767 }; 5768 5769 nsp_noc: interconnect@320c0000 { 5770 compatible = "qcom,sm8750-nsp-noc"; 5771 reg = <0x0 0x320c0000 0x0 0x13080>; 5772 qcom,bcm-voters = <&apps_bcm_voter>; 5773 #interconnect-cells = <2>; 5774 }; 5775 5776 remoteproc_cdsp: remoteproc@32300000 { 5777 compatible = "qcom,sm8750-cdsp-pas", "qcom,sm8650-cdsp-pas"; 5778 reg = <0x0 0x32300000 0x0 0x10000>; 5779 5780 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5781 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 5782 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 5783 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 5784 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, 5785 <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; 5786 interrupt-names = "wdog", 5787 "fatal", 5788 "ready", 5789 "handover", 5790 "stop-ack", 5791 "shutdown-ack"; 5792 5793 clocks = <&rpmhcc RPMH_CXO_CLK>; 5794 clock-names = "xo"; 5795 5796 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 5797 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5798 5799 power-domains = <&rpmhpd RPMHPD_CX>, 5800 <&rpmhpd RPMHPD_MXC>, 5801 <&rpmhpd RPMHPD_NSP>; 5802 power-domain-names = "cx", 5803 "mxc", 5804 "nsp"; 5805 5806 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; 5807 qcom,qmp = <&aoss_qmp>; 5808 qcom,smem-states = <&smp2p_cdsp_out 0>; 5809 qcom,smem-state-names = "stop"; 5810 5811 status = "disabled"; 5812 5813 glink-edge { 5814 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5815 IPCC_MPROC_SIGNAL_GLINK_QMP 5816 IRQ_TYPE_EDGE_RISING>; 5817 mboxes = <&ipcc IPCC_CLIENT_CDSP 5818 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5819 qcom,remote-pid = <5>; 5820 label = "cdsp"; 5821 5822 fastrpc { 5823 compatible = "qcom,fastrpc"; 5824 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5825 label = "cdsp"; 5826 qcom,non-secure-domain; 5827 #address-cells = <1>; 5828 #size-cells = <0>; 5829 5830 compute-cb@1 { 5831 compatible = "qcom,fastrpc-compute-cb"; 5832 reg = <1>; 5833 iommus = <&apps_smmu 0x19c1 0x0>, 5834 <&apps_smmu 0x0c21 0x0>, 5835 <&apps_smmu 0x0c01 0x40>; 5836 dma-coherent; 5837 }; 5838 5839 compute-cb@2 { 5840 compatible = "qcom,fastrpc-compute-cb"; 5841 reg = <2>; 5842 iommus = <&apps_smmu 0x1962 0x0>, 5843 <&apps_smmu 0x0c02 0x20>, 5844 <&apps_smmu 0x0c42 0x0>, 5845 <&apps_smmu 0x19c2 0x0>; 5846 dma-coherent; 5847 }; 5848 5849 compute-cb@3 { 5850 compatible = "qcom,fastrpc-compute-cb"; 5851 reg = <3>; 5852 iommus = <&apps_smmu 0x1963 0x0>, 5853 <&apps_smmu 0x0c23 0x0>, 5854 <&apps_smmu 0x0c03 0x40>, 5855 <&apps_smmu 0x19c3 0x0>; 5856 dma-coherent; 5857 }; 5858 5859 compute-cb@4 { 5860 compatible = "qcom,fastrpc-compute-cb"; 5861 reg = <4>; 5862 iommus = <&apps_smmu 0x1964 0x0>, 5863 <&apps_smmu 0x0c24 0x0>, 5864 <&apps_smmu 0x0c04 0x40>, 5865 <&apps_smmu 0x19c4 0x0>; 5866 dma-coherent; 5867 }; 5868 5869 compute-cb@5 { 5870 compatible = "qcom,fastrpc-compute-cb"; 5871 reg = <5>; 5872 iommus = <&apps_smmu 0x1965 0x0>, 5873 <&apps_smmu 0x0c25 0x0>, 5874 <&apps_smmu 0x0c05 0x40>, 5875 <&apps_smmu 0x19c5 0x0>; 5876 dma-coherent; 5877 }; 5878 5879 compute-cb@6 { 5880 compatible = "qcom,fastrpc-compute-cb"; 5881 reg = <6>; 5882 iommus = <&apps_smmu 0x1966 0x0>, 5883 <&apps_smmu 0x0c06 0x20>, 5884 <&apps_smmu 0x0c46 0x0>, 5885 <&apps_smmu 0x19c6 0x0>; 5886 dma-coherent; 5887 }; 5888 5889 compute-cb@7 { 5890 compatible = "qcom,fastrpc-compute-cb"; 5891 reg = <7>; 5892 iommus = <&apps_smmu 0x1967 0x0>, 5893 <&apps_smmu 0x0c27 0x0>, 5894 <&apps_smmu 0x0c07 0x40>, 5895 <&apps_smmu 0x19c7 0x0>; 5896 dma-coherent; 5897 }; 5898 5899 compute-cb@8 { 5900 compatible = "qcom,fastrpc-compute-cb"; 5901 reg = <8>; 5902 iommus = <&apps_smmu 0x1968 0x0>, 5903 <&apps_smmu 0x0c08 0x20>, 5904 <&apps_smmu 0x0c48 0x0>, 5905 <&apps_smmu 0x19c8 0x0>; 5906 dma-coherent; 5907 }; 5908 5909 /* note: secure cb9 in downstream */ 5910 5911 compute-cb@12 { 5912 compatible = "qcom,fastrpc-compute-cb"; 5913 reg = <12>; 5914 iommus = <&apps_smmu 0x196c 0x0>, 5915 <&apps_smmu 0x0c2c 0x20>, 5916 <&apps_smmu 0x0c0c 0x40>, 5917 <&apps_smmu 0x19cc 0x0>; 5918 dma-coherent; 5919 }; 5920 5921 compute-cb@13 { 5922 compatible = "qcom,fastrpc-compute-cb"; 5923 reg = <13>; 5924 iommus = <&apps_smmu 0x196d 0x0>, 5925 <&apps_smmu 0x0c0d 0x20>, 5926 <&apps_smmu 0x0c2e 0x0>, 5927 <&apps_smmu 0x0c4d 0x0>, 5928 <&apps_smmu 0x19cd 0x0>; 5929 dma-coherent; 5930 }; 5931 5932 compute-cb@14 { 5933 compatible = "qcom,fastrpc-compute-cb"; 5934 reg = <14>; 5935 iommus = <&apps_smmu 0x196e 0x0>, 5936 <&apps_smmu 0x0c0e 0x20>, 5937 <&apps_smmu 0x19ce 0x0>; 5938 dma-coherent; 5939 }; 5940 }; 5941 }; 5942 }; 5943 }; 5944 5945 thermal-zones { 5946 aoss0-thermal { 5947 thermal-sensors = <&tsens0 0>; 5948 5949 trips { 5950 trip-point0 { 5951 temperature = <120000>; 5952 hysteresis = <5000>; 5953 type = "hot"; 5954 }; 5955 5956 aoss0-critical { 5957 temperature = <125000>; 5958 hysteresis = <0>; 5959 type = "critical"; 5960 }; 5961 }; 5962 }; 5963 5964 cpu-0-0-0-thermal { 5965 thermal-sensors = <&tsens0 1>; 5966 5967 trips { 5968 trip-point0 { 5969 temperature = <120000>; 5970 hysteresis = <5000>; 5971 type = "hot"; 5972 }; 5973 5974 cpu-0-0-0-critical { 5975 temperature = <125000>; 5976 hysteresis = <0>; 5977 type = "critical"; 5978 }; 5979 }; 5980 }; 5981 5982 cpu-0-0-1-thermal { 5983 thermal-sensors = <&tsens0 2>; 5984 5985 trips { 5986 trip-point0 { 5987 temperature = <120000>; 5988 hysteresis = <5000>; 5989 type = "hot"; 5990 }; 5991 5992 cpu-0-0-1-critical { 5993 temperature = <125000>; 5994 hysteresis = <0>; 5995 type = "critical"; 5996 }; 5997 }; 5998 }; 5999 6000 cpu-0-1-0-thermal { 6001 thermal-sensors = <&tsens0 3>; 6002 6003 trips { 6004 trip-point0 { 6005 temperature = <120000>; 6006 hysteresis = <5000>; 6007 type = "hot"; 6008 }; 6009 6010 cpu-0-1-0-critical { 6011 temperature = <125000>; 6012 hysteresis = <0>; 6013 type = "critical"; 6014 }; 6015 }; 6016 }; 6017 6018 cpu-0-1-1-thermal { 6019 thermal-sensors = <&tsens0 4>; 6020 6021 trips { 6022 trip-point0 { 6023 temperature = <120000>; 6024 hysteresis = <5000>; 6025 type = "hot"; 6026 }; 6027 6028 cpu-0-1-1-critical { 6029 temperature = <125000>; 6030 hysteresis = <0>; 6031 type = "critical"; 6032 }; 6033 }; 6034 }; 6035 6036 cpu-0-2-0-thermal { 6037 thermal-sensors = <&tsens0 5>; 6038 6039 trips { 6040 trip-point0 { 6041 temperature = <120000>; 6042 hysteresis = <5000>; 6043 type = "hot"; 6044 }; 6045 6046 cpu-0-2-0-critical { 6047 temperature = <125000>; 6048 hysteresis = <0>; 6049 type = "critical"; 6050 }; 6051 }; 6052 }; 6053 6054 cpu-0-2-1-thermal { 6055 thermal-sensors = <&tsens0 6>; 6056 6057 trips { 6058 trip-point0 { 6059 temperature = <120000>; 6060 hysteresis = <5000>; 6061 type = "hot"; 6062 }; 6063 6064 cpu-0-2-1-critical { 6065 temperature = <125000>; 6066 hysteresis = <0>; 6067 type = "critical"; 6068 }; 6069 }; 6070 }; 6071 6072 cpu-0-3-0-thermal { 6073 thermal-sensors = <&tsens0 7>; 6074 6075 trips { 6076 trip-point0 { 6077 temperature = <120000>; 6078 hysteresis = <5000>; 6079 type = "hot"; 6080 }; 6081 6082 cpu-0-3-0-critical { 6083 temperature = <125000>; 6084 hysteresis = <0>; 6085 type = "critical"; 6086 }; 6087 }; 6088 }; 6089 6090 cpu-0-3-1-thermal { 6091 thermal-sensors = <&tsens0 8>; 6092 6093 trips { 6094 trip-point0 { 6095 temperature = <120000>; 6096 hysteresis = <5000>; 6097 type = "hot"; 6098 }; 6099 6100 cpu-0-3-1-critical { 6101 temperature = <125000>; 6102 hysteresis = <0>; 6103 type = "critical"; 6104 }; 6105 }; 6106 }; 6107 6108 cpu-0-4-0-thermal { 6109 thermal-sensors = <&tsens0 9>; 6110 6111 trips { 6112 trip-point0 { 6113 temperature = <120000>; 6114 hysteresis = <5000>; 6115 type = "hot"; 6116 }; 6117 6118 cpu-0-4-0-critical { 6119 temperature = <125000>; 6120 hysteresis = <0>; 6121 type = "critical"; 6122 }; 6123 }; 6124 }; 6125 6126 cpu-0-4-1-thermal { 6127 thermal-sensors = <&tsens0 10>; 6128 6129 trips { 6130 trip-point0 { 6131 temperature = <120000>; 6132 hysteresis = <5000>; 6133 type = "hot"; 6134 }; 6135 6136 cpu-0-4-1-critical { 6137 temperature = <125000>; 6138 hysteresis = <0>; 6139 type = "critical"; 6140 }; 6141 }; 6142 }; 6143 6144 cpu-0-5-0-thermal { 6145 thermal-sensors = <&tsens0 11>; 6146 6147 trips { 6148 trip-point0 { 6149 temperature = <120000>; 6150 hysteresis = <5000>; 6151 type = "hot"; 6152 }; 6153 6154 cpu-0-5-0-critical { 6155 temperature = <125000>; 6156 hysteresis = <0>; 6157 type = "critical"; 6158 }; 6159 }; 6160 }; 6161 6162 cpu-0-5-1-thermal { 6163 thermal-sensors = <&tsens0 12>; 6164 6165 trips { 6166 trip-point0 { 6167 temperature = <120000>; 6168 hysteresis = <5000>; 6169 type = "hot"; 6170 }; 6171 6172 cpu-0-5-1-critical { 6173 temperature = <125000>; 6174 hysteresis = <0>; 6175 type = "critical"; 6176 }; 6177 }; 6178 }; 6179 6180 cpuss-0-0-thermal { 6181 thermal-sensors = <&tsens0 13>; 6182 6183 trips { 6184 trip-point0 { 6185 temperature = <120000>; 6186 hysteresis = <5000>; 6187 type = "hot"; 6188 }; 6189 6190 cpuss-0-0-critical { 6191 temperature = <125000>; 6192 hysteresis = <0>; 6193 type = "critical"; 6194 }; 6195 }; 6196 }; 6197 6198 cpuss-0-1-thermal { 6199 thermal-sensors = <&tsens0 14>; 6200 6201 trips { 6202 trip-point0 { 6203 temperature = <120000>; 6204 hysteresis = <5000>; 6205 type = "hot"; 6206 }; 6207 6208 cpuss-0-1-critical { 6209 temperature = <125000>; 6210 hysteresis = <0>; 6211 type = "critical"; 6212 }; 6213 }; 6214 }; 6215 6216 aoss1-thermal { 6217 thermal-sensors = <&tsens1 0>; 6218 6219 trips { 6220 trip-point0 { 6221 temperature = <120000>; 6222 hysteresis = <5000>; 6223 type = "hot"; 6224 }; 6225 6226 aoss1-critical { 6227 temperature = <125000>; 6228 hysteresis = <0>; 6229 type = "critical"; 6230 }; 6231 }; 6232 }; 6233 6234 cpu-1-0-0-thermal { 6235 thermal-sensors = <&tsens1 1>; 6236 6237 trips { 6238 trip-point0 { 6239 temperature = <120000>; 6240 hysteresis = <5000>; 6241 type = "hot"; 6242 }; 6243 6244 cpu-1-0-0-critical { 6245 temperature = <125000>; 6246 hysteresis = <0>; 6247 type = "critical"; 6248 }; 6249 }; 6250 }; 6251 6252 cpu-1-0-1-thermal { 6253 thermal-sensors = <&tsens1 2>; 6254 6255 trips { 6256 trip-point0 { 6257 temperature = <120000>; 6258 hysteresis = <5000>; 6259 type = "hot"; 6260 }; 6261 6262 cpu-1-0-1-critical { 6263 temperature = <125000>; 6264 hysteresis = <0>; 6265 type = "critical"; 6266 }; 6267 }; 6268 }; 6269 6270 cpu-1-1-0-thermal { 6271 thermal-sensors = <&tsens1 3>; 6272 6273 trips { 6274 trip-point0 { 6275 temperature = <120000>; 6276 hysteresis = <5000>; 6277 type = "hot"; 6278 }; 6279 6280 cpu-1-1-0-critical { 6281 temperature = <125000>; 6282 hysteresis = <0>; 6283 type = "critical"; 6284 }; 6285 }; 6286 }; 6287 6288 cpu-1-1-1-thermal { 6289 thermal-sensors = <&tsens1 4>; 6290 6291 trips { 6292 trip-point0 { 6293 temperature = <120000>; 6294 hysteresis = <5000>; 6295 type = "hot"; 6296 }; 6297 6298 cpu-1-1-1-critical { 6299 temperature = <125000>; 6300 hysteresis = <0>; 6301 type = "critical"; 6302 }; 6303 }; 6304 }; 6305 6306 cpuss-1-0-thermal { 6307 thermal-sensors = <&tsens1 5>; 6308 6309 trips { 6310 trip-point0 { 6311 temperature = <120000>; 6312 hysteresis = <5000>; 6313 type = "hot"; 6314 }; 6315 6316 cpuss-1-0-critical { 6317 temperature = <125000>; 6318 hysteresis = <0>; 6319 type = "critical"; 6320 }; 6321 }; 6322 }; 6323 6324 cpuss-1-1-thermal { 6325 thermal-sensors = <&tsens1 6>; 6326 6327 trips { 6328 trip-point0 { 6329 temperature = <120000>; 6330 hysteresis = <5000>; 6331 type = "hot"; 6332 }; 6333 6334 cpuss-1-1-critical { 6335 temperature = <125000>; 6336 hysteresis = <0>; 6337 type = "critical"; 6338 }; 6339 }; 6340 }; 6341 6342 aoss2-thermal { 6343 thermal-sensors = <&tsens2 0>; 6344 6345 trips { 6346 trip-point0 { 6347 temperature = <120000>; 6348 hysteresis = <5000>; 6349 type = "hot"; 6350 }; 6351 6352 aoss2-critical { 6353 temperature = <125000>; 6354 hysteresis = <0>; 6355 type = "critical"; 6356 }; 6357 }; 6358 }; 6359 6360 gpuss0-thermal { 6361 thermal-sensors = <&tsens2 1>; 6362 6363 trips { 6364 trip-point0 { 6365 temperature = <120000>; 6366 hysteresis = <5000>; 6367 type = "hot"; 6368 }; 6369 6370 gpuss0-critical { 6371 temperature = <125000>; 6372 hysteresis = <0>; 6373 type = "critical"; 6374 }; 6375 }; 6376 }; 6377 6378 gpuss1-thermal { 6379 thermal-sensors = <&tsens2 2>; 6380 6381 trips { 6382 trip-point0 { 6383 temperature = <120000>; 6384 hysteresis = <5000>; 6385 type = "hot"; 6386 }; 6387 6388 gpuss1-critical { 6389 temperature = <125000>; 6390 hysteresis = <0>; 6391 type = "critical"; 6392 }; 6393 }; 6394 }; 6395 6396 gpuss2-thermal { 6397 thermal-sensors = <&tsens2 3>; 6398 6399 trips { 6400 trip-point0 { 6401 temperature = <120000>; 6402 hysteresis = <5000>; 6403 type = "hot"; 6404 }; 6405 6406 gpuss2-critical { 6407 temperature = <125000>; 6408 hysteresis = <0>; 6409 type = "critical"; 6410 }; 6411 }; 6412 }; 6413 6414 gpuss3-thermal { 6415 thermal-sensors = <&tsens2 4>; 6416 6417 trips { 6418 trip-point0 { 6419 temperature = <120000>; 6420 hysteresis = <5000>; 6421 type = "hot"; 6422 }; 6423 6424 gpuss3-critical { 6425 temperature = <125000>; 6426 hysteresis = <0>; 6427 type = "critical"; 6428 }; 6429 }; 6430 }; 6431 6432 gpuss4-thermal { 6433 thermal-sensors = <&tsens2 5>; 6434 6435 trips { 6436 trip-point0 { 6437 temperature = <120000>; 6438 hysteresis = <5000>; 6439 type = "hot"; 6440 }; 6441 6442 gpuss4-critical { 6443 temperature = <125000>; 6444 hysteresis = <0>; 6445 type = "critical"; 6446 }; 6447 }; 6448 }; 6449 6450 gpuss5-thermal { 6451 thermal-sensors = <&tsens2 6>; 6452 6453 trips { 6454 trip-point0 { 6455 temperature = <120000>; 6456 hysteresis = <5000>; 6457 type = "hot"; 6458 }; 6459 6460 gpuss5-critical { 6461 temperature = <125000>; 6462 hysteresis = <0>; 6463 type = "critical"; 6464 }; 6465 }; 6466 }; 6467 6468 gpuss6-thermal { 6469 thermal-sensors = <&tsens2 7>; 6470 6471 trips { 6472 trip-point0 { 6473 temperature = <120000>; 6474 hysteresis = <5000>; 6475 type = "hot"; 6476 }; 6477 6478 gpuss6-critical { 6479 temperature = <125000>; 6480 hysteresis = <0>; 6481 type = "critical"; 6482 }; 6483 }; 6484 }; 6485 6486 gpuss7-thermal { 6487 thermal-sensors = <&tsens2 8>; 6488 6489 trips { 6490 trip-point0 { 6491 temperature = <120000>; 6492 hysteresis = <5000>; 6493 type = "hot"; 6494 }; 6495 6496 gpuss7-critical { 6497 temperature = <125000>; 6498 hysteresis = <0>; 6499 type = "critical"; 6500 }; 6501 }; 6502 }; 6503 6504 modem0-thermal { 6505 thermal-sensors = <&tsens2 9>; 6506 6507 trips { 6508 trip-point0 { 6509 temperature = <120000>; 6510 hysteresis = <5000>; 6511 type = "hot"; 6512 }; 6513 6514 modem0-critical { 6515 temperature = <125000>; 6516 hysteresis = <0>; 6517 type = "critical"; 6518 }; 6519 }; 6520 }; 6521 6522 modem1-thermal { 6523 thermal-sensors = <&tsens2 10>; 6524 6525 trips { 6526 trip-point0 { 6527 temperature = <120000>; 6528 hysteresis = <5000>; 6529 type = "hot"; 6530 }; 6531 6532 modem1-critical { 6533 temperature = <125000>; 6534 hysteresis = <0>; 6535 type = "critical"; 6536 }; 6537 }; 6538 }; 6539 6540 modem2-thermal { 6541 thermal-sensors = <&tsens2 11>; 6542 6543 trips { 6544 trip-point0 { 6545 temperature = <120000>; 6546 hysteresis = <5000>; 6547 type = "hot"; 6548 }; 6549 6550 modem2-critical { 6551 temperature = <125000>; 6552 hysteresis = <0>; 6553 type = "critical"; 6554 }; 6555 }; 6556 }; 6557 6558 modem3-thermal { 6559 thermal-sensors = <&tsens2 12>; 6560 6561 trips { 6562 trip-point0 { 6563 temperature = <120000>; 6564 hysteresis = <5000>; 6565 type = "hot"; 6566 }; 6567 6568 modem3-critical { 6569 temperature = <125000>; 6570 hysteresis = <0>; 6571 type = "critical"; 6572 }; 6573 }; 6574 }; 6575 6576 camera0-thermal { 6577 thermal-sensors = <&tsens2 13>; 6578 6579 trips { 6580 trip-point0 { 6581 temperature = <120000>; 6582 hysteresis = <5000>; 6583 type = "hot"; 6584 }; 6585 6586 camera0-critical { 6587 temperature = <125000>; 6588 hysteresis = <0>; 6589 type = "critical"; 6590 }; 6591 }; 6592 }; 6593 6594 camera1-thermal { 6595 thermal-sensors = <&tsens2 14>; 6596 6597 trips { 6598 trip-point0 { 6599 temperature = <120000>; 6600 hysteresis = <5000>; 6601 type = "hot"; 6602 }; 6603 6604 camera1-critical { 6605 temperature = <125000>; 6606 hysteresis = <0>; 6607 type = "critical"; 6608 }; 6609 }; 6610 }; 6611 6612 video-thermal { 6613 thermal-sensors = <&tsens2 15>; 6614 6615 trips { 6616 trip-point0 { 6617 temperature = <120000>; 6618 hysteresis = <5000>; 6619 type = "hot"; 6620 }; 6621 6622 video-critical { 6623 temperature = <125000>; 6624 hysteresis = <0>; 6625 type = "critical"; 6626 }; 6627 }; 6628 }; 6629 6630 aoss3-thermal { 6631 thermal-sensors = <&tsens3 0>; 6632 6633 trips { 6634 trip-point0 { 6635 temperature = <120000>; 6636 hysteresis = <5000>; 6637 type = "hot"; 6638 }; 6639 6640 aoss3-critical { 6641 temperature = <125000>; 6642 hysteresis = <0>; 6643 type = "critical"; 6644 }; 6645 }; 6646 }; 6647 6648 nsphvx0-thermal { 6649 thermal-sensors = <&tsens3 1>; 6650 6651 trips { 6652 trip-point0 { 6653 temperature = <120000>; 6654 hysteresis = <5000>; 6655 type = "hot"; 6656 }; 6657 6658 nsphvx0-critical { 6659 temperature = <125000>; 6660 hysteresis = <0>; 6661 type = "critical"; 6662 }; 6663 }; 6664 }; 6665 6666 nsphvx1-thermal { 6667 thermal-sensors = <&tsens3 2>; 6668 6669 trips { 6670 trip-point0 { 6671 temperature = <120000>; 6672 hysteresis = <5000>; 6673 type = "hot"; 6674 }; 6675 6676 nsphvx1-critical { 6677 temperature = <125000>; 6678 hysteresis = <0>; 6679 type = "critical"; 6680 }; 6681 }; 6682 }; 6683 6684 nsphvx2-thermal { 6685 thermal-sensors = <&tsens3 3>; 6686 6687 trips { 6688 trip-point0 { 6689 temperature = <120000>; 6690 hysteresis = <5000>; 6691 type = "hot"; 6692 }; 6693 6694 nsphvx2-critical { 6695 temperature = <125000>; 6696 hysteresis = <0>; 6697 type = "critical"; 6698 }; 6699 }; 6700 }; 6701 6702 nsphmx0-thermal { 6703 thermal-sensors = <&tsens3 4>; 6704 6705 trips { 6706 trip-point0 { 6707 temperature = <120000>; 6708 hysteresis = <5000>; 6709 type = "hot"; 6710 }; 6711 6712 nsphmx0-critical { 6713 temperature = <125000>; 6714 hysteresis = <0>; 6715 type = "critical"; 6716 }; 6717 }; 6718 }; 6719 6720 nsphmx1-thermal { 6721 thermal-sensors = <&tsens3 5>; 6722 6723 trips { 6724 trip-point0 { 6725 temperature = <120000>; 6726 hysteresis = <5000>; 6727 type = "hot"; 6728 }; 6729 6730 nsphmx1-critical { 6731 temperature = <125000>; 6732 hysteresis = <0>; 6733 type = "critical"; 6734 }; 6735 }; 6736 }; 6737 6738 nsphmx2-thermal { 6739 thermal-sensors = <&tsens3 6>; 6740 6741 trips { 6742 trip-point0 { 6743 temperature = <120000>; 6744 hysteresis = <5000>; 6745 type = "hot"; 6746 }; 6747 6748 nsphmx2-critical { 6749 temperature = <125000>; 6750 hysteresis = <0>; 6751 type = "critical"; 6752 }; 6753 }; 6754 }; 6755 6756 nsphmx3-thermal { 6757 thermal-sensors = <&tsens3 7>; 6758 6759 trips { 6760 trip-point0 { 6761 temperature = <120000>; 6762 hysteresis = <5000>; 6763 type = "hot"; 6764 }; 6765 6766 nsphmx3-critical { 6767 temperature = <125000>; 6768 hysteresis = <0>; 6769 type = "critical"; 6770 }; 6771 }; 6772 }; 6773 6774 ddr-thermal { 6775 thermal-sensors = <&tsens3 8>; 6776 6777 trips { 6778 trip-point0 { 6779 temperature = <120000>; 6780 hysteresis = <2000>; 6781 type = "hot"; 6782 }; 6783 6784 ddr-critical { 6785 temperature = <125000>; 6786 hysteresis = <0>; 6787 type = "critical"; 6788 }; 6789 }; 6790 }; 6791 }; 6792 6793 timer { 6794 compatible = "arm,armv8-timer"; 6795 6796 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6797 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6798 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6799 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6800 }; 6801 6802 tpdm-cdsp-llm { 6803 compatible = "qcom,coresight-static-tpdm"; 6804 qcom,cmb-element-bits = <32>; 6805 6806 out-ports { 6807 port { 6808 tpdm_cdsp_llm_out: endpoint { 6809 remote-endpoint = <&tpda_cdsp_in1>; 6810 }; 6811 }; 6812 }; 6813 }; 6814 6815 tpdm-cdsp-llm2 { 6816 compatible = "qcom,coresight-static-tpdm"; 6817 qcom,cmb-element-bits = <32>; 6818 6819 out-ports { 6820 port { 6821 tpdm_cdsp_llm2_out: endpoint { 6822 remote-endpoint = <&tpda_cdsp_in2>; 6823 }; 6824 }; 6825 }; 6826 }; 6827 6828 tpdm-modem1 { 6829 compatible = "qcom,coresight-static-tpdm"; 6830 qcom,dsb-element-bits = <32>; 6831 6832 out-ports { 6833 port { 6834 tpdm_modem1_out: endpoint { 6835 remote-endpoint = <&tpda_modem_in1>; 6836 }; 6837 }; 6838 }; 6839 }; 6840}; 6841