1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8650-dispcc.h> 8#include <dt-bindings/clock/qcom,sm8650-gcc.h> 9#include <dt-bindings/clock/qcom,sm8650-gpucc.h> 10#include <dt-bindings/clock/qcom,sm8650-tcsr.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/firmware/qcom,scm.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/reset/qcom,sm8650-gpucc.h> 22#include <dt-bindings/soc/qcom,gpr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 chosen { }; 34 35 clocks { 36 xo_board: xo-board { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 }; 45 46 bi_tcxo_div2: bi-tcxo-div2-clk { 47 compatible = "fixed-factor-clock"; 48 #clock-cells = <0>; 49 50 clocks = <&rpmhcc RPMH_CXO_CLK>; 51 clock-mult = <1>; 52 clock-div = <2>; 53 }; 54 55 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 56 compatible = "fixed-factor-clock"; 57 #clock-cells = <0>; 58 59 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 60 clock-mult = <1>; 61 clock-div = <2>; 62 }; 63 64 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 65 compatible = "fixed-clock"; 66 #clock-cells = <0>; 67 }; 68 }; 69 70 cpus { 71 #address-cells = <2>; 72 #size-cells = <0>; 73 74 CPU0: cpu@0 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a520"; 77 reg = <0 0>; 78 79 clocks = <&cpufreq_hw 0>; 80 81 power-domains = <&CPU_PD0>; 82 power-domain-names = "psci"; 83 84 enable-method = "psci"; 85 next-level-cache = <&L2_0>; 86 capacity-dmips-mhz = <1024>; 87 dynamic-power-coefficient = <100>; 88 89 qcom,freq-domain = <&cpufreq_hw 0>; 90 91 #cooling-cells = <2>; 92 93 L2_0: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 next-level-cache = <&L3_0>; 98 99 L3_0: l3-cache { 100 compatible = "cache"; 101 cache-level = <3>; 102 cache-unified; 103 }; 104 }; 105 }; 106 107 CPU1: cpu@100 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a520"; 110 reg = <0 0x100>; 111 112 clocks = <&cpufreq_hw 0>; 113 114 power-domains = <&CPU_PD1>; 115 power-domain-names = "psci"; 116 117 enable-method = "psci"; 118 next-level-cache = <&L2_0>; 119 capacity-dmips-mhz = <1024>; 120 dynamic-power-coefficient = <100>; 121 122 qcom,freq-domain = <&cpufreq_hw 0>; 123 124 #cooling-cells = <2>; 125 }; 126 127 CPU2: cpu@200 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a720"; 130 reg = <0 0x200>; 131 132 clocks = <&cpufreq_hw 3>; 133 134 power-domains = <&CPU_PD2>; 135 power-domain-names = "psci"; 136 137 enable-method = "psci"; 138 next-level-cache = <&L2_200>; 139 capacity-dmips-mhz = <1792>; 140 dynamic-power-coefficient = <238>; 141 142 qcom,freq-domain = <&cpufreq_hw 3>; 143 144 #cooling-cells = <2>; 145 146 L2_200: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU3: cpu@300 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a720"; 157 reg = <0 0x300>; 158 159 clocks = <&cpufreq_hw 3>; 160 161 power-domains = <&CPU_PD3>; 162 power-domain-names = "psci"; 163 164 enable-method = "psci"; 165 next-level-cache = <&L2_200>; 166 capacity-dmips-mhz = <1792>; 167 dynamic-power-coefficient = <238>; 168 169 qcom,freq-domain = <&cpufreq_hw 3>; 170 171 #cooling-cells = <2>; 172 }; 173 174 CPU4: cpu@400 { 175 device_type = "cpu"; 176 compatible = "arm,cortex-a720"; 177 reg = <0 0x400>; 178 179 clocks = <&cpufreq_hw 3>; 180 181 power-domains = <&CPU_PD4>; 182 power-domain-names = "psci"; 183 184 enable-method = "psci"; 185 next-level-cache = <&L2_400>; 186 capacity-dmips-mhz = <1792>; 187 dynamic-power-coefficient = <238>; 188 189 qcom,freq-domain = <&cpufreq_hw 3>; 190 191 #cooling-cells = <2>; 192 193 L2_400: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 next-level-cache = <&L3_0>; 198 }; 199 }; 200 201 CPU5: cpu@500 { 202 device_type = "cpu"; 203 compatible = "arm,cortex-a720"; 204 reg = <0 0x500>; 205 206 clocks = <&cpufreq_hw 1>; 207 208 power-domains = <&CPU_PD5>; 209 power-domain-names = "psci"; 210 211 enable-method = "psci"; 212 next-level-cache = <&L2_500>; 213 capacity-dmips-mhz = <1792>; 214 dynamic-power-coefficient = <238>; 215 216 qcom,freq-domain = <&cpufreq_hw 1>; 217 218 #cooling-cells = <2>; 219 220 L2_500: l2-cache { 221 compatible = "cache"; 222 cache-level = <2>; 223 cache-unified; 224 next-level-cache = <&L3_0>; 225 }; 226 }; 227 228 CPU6: cpu@600 { 229 device_type = "cpu"; 230 compatible = "arm,cortex-a720"; 231 reg = <0 0x600>; 232 233 clocks = <&cpufreq_hw 1>; 234 235 power-domains = <&CPU_PD6>; 236 power-domain-names = "psci"; 237 238 enable-method = "psci"; 239 next-level-cache = <&L2_600>; 240 capacity-dmips-mhz = <1792>; 241 dynamic-power-coefficient = <238>; 242 243 qcom,freq-domain = <&cpufreq_hw 1>; 244 245 #cooling-cells = <2>; 246 247 L2_600: l2-cache { 248 compatible = "cache"; 249 cache-level = <2>; 250 cache-unified; 251 next-level-cache = <&L3_0>; 252 }; 253 }; 254 255 CPU7: cpu@700 { 256 device_type = "cpu"; 257 compatible = "arm,cortex-x4"; 258 reg = <0 0x700>; 259 260 clocks = <&cpufreq_hw 2>; 261 262 power-domains = <&CPU_PD7>; 263 power-domain-names = "psci"; 264 265 enable-method = "psci"; 266 next-level-cache = <&L2_700>; 267 capacity-dmips-mhz = <1894>; 268 dynamic-power-coefficient = <588>; 269 270 qcom,freq-domain = <&cpufreq_hw 2>; 271 272 #cooling-cells = <2>; 273 274 L2_700: l2-cache { 275 compatible = "cache"; 276 cache-level = <2>; 277 cache-unified; 278 next-level-cache = <&L3_0>; 279 }; 280 }; 281 282 cpu-map { 283 cluster0 { 284 core0 { 285 cpu = <&CPU0>; 286 }; 287 288 core1 { 289 cpu = <&CPU1>; 290 }; 291 292 core2 { 293 cpu = <&CPU2>; 294 }; 295 296 core3 { 297 cpu = <&CPU3>; 298 }; 299 300 core4 { 301 cpu = <&CPU4>; 302 }; 303 304 core5 { 305 cpu = <&CPU5>; 306 }; 307 308 core6 { 309 cpu = <&CPU6>; 310 }; 311 312 core7 { 313 cpu = <&CPU7>; 314 }; 315 }; 316 }; 317 318 idle-states { 319 entry-method = "psci"; 320 321 SILVER_CPU_SLEEP_0: cpu-sleep-0-0 { 322 compatible = "arm,idle-state"; 323 idle-state-name = "silver-rail-power-collapse"; 324 arm,psci-suspend-param = <0x40000004>; 325 entry-latency-us = <550>; 326 exit-latency-us = <750>; 327 min-residency-us = <6700>; 328 local-timer-stop; 329 }; 330 331 GOLD_CPU_SLEEP_0: cpu-sleep-1-0 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "gold-rail-power-collapse"; 334 arm,psci-suspend-param = <0x40000004>; 335 entry-latency-us = <600>; 336 exit-latency-us = <1300>; 337 min-residency-us = <8136>; 338 local-timer-stop; 339 }; 340 341 GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "gold-plus-rail-power-collapse"; 344 arm,psci-suspend-param = <0x40000004>; 345 entry-latency-us = <500>; 346 exit-latency-us = <1350>; 347 min-residency-us = <7480>; 348 local-timer-stop; 349 }; 350 }; 351 352 domain-idle-states { 353 CLUSTER_SLEEP_0: cluster-sleep-0 { 354 compatible = "domain-idle-state"; 355 arm,psci-suspend-param = <0x41000044>; 356 entry-latency-us = <750>; 357 exit-latency-us = <2350>; 358 min-residency-us = <9144>; 359 }; 360 361 CLUSTER_SLEEP_1: cluster-sleep-1 { 362 compatible = "domain-idle-state"; 363 arm,psci-suspend-param = <0x4100c344>; 364 entry-latency-us = <2800>; 365 exit-latency-us = <4400>; 366 min-residency-us = <10150>; 367 }; 368 }; 369 }; 370 371 firmware { 372 scm: scm { 373 compatible = "qcom,scm-sm8650", "qcom,scm"; 374 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 375 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 376 }; 377 }; 378 379 clk_virt: interconnect-0 { 380 compatible = "qcom,sm8650-clk-virt"; 381 #interconnect-cells = <2>; 382 qcom,bcm-voters = <&apps_bcm_voter>; 383 }; 384 385 mc_virt: interconnect-1 { 386 compatible = "qcom,sm8650-mc-virt"; 387 #interconnect-cells = <2>; 388 qcom,bcm-voters = <&apps_bcm_voter>; 389 }; 390 391 memory@a0000000 { 392 device_type = "memory"; 393 /* We expect the bootloader to fill in the size */ 394 reg = <0 0xa0000000 0 0>; 395 }; 396 397 pmu { 398 compatible = "arm,armv8-pmuv3"; 399 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 400 }; 401 402 psci { 403 compatible = "arm,psci-1.0"; 404 method = "smc"; 405 406 CPU_PD0: power-domain-cpu0 { 407 #power-domain-cells = <0>; 408 power-domains = <&CLUSTER_PD>; 409 domain-idle-states = <&SILVER_CPU_SLEEP_0>; 410 }; 411 412 CPU_PD1: power-domain-cpu1 { 413 #power-domain-cells = <0>; 414 power-domains = <&CLUSTER_PD>; 415 domain-idle-states = <&SILVER_CPU_SLEEP_0>; 416 }; 417 418 CPU_PD2: power-domain-cpu2 { 419 #power-domain-cells = <0>; 420 power-domains = <&CLUSTER_PD>; 421 domain-idle-states = <&SILVER_CPU_SLEEP_0>; 422 }; 423 424 CPU_PD3: power-domain-cpu3 { 425 #power-domain-cells = <0>; 426 power-domains = <&CLUSTER_PD>; 427 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 428 }; 429 430 CPU_PD4: power-domain-cpu4 { 431 #power-domain-cells = <0>; 432 power-domains = <&CLUSTER_PD>; 433 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 434 }; 435 436 CPU_PD5: power-domain-cpu5 { 437 #power-domain-cells = <0>; 438 power-domains = <&CLUSTER_PD>; 439 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 440 }; 441 442 CPU_PD6: power-domain-cpu6 { 443 #power-domain-cells = <0>; 444 power-domains = <&CLUSTER_PD>; 445 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 446 }; 447 448 CPU_PD7: power-domain-cpu7 { 449 #power-domain-cells = <0>; 450 power-domains = <&CLUSTER_PD>; 451 domain-idle-states = <&GOLD_PLUS_CPU_SLEEP_0>; 452 }; 453 454 CLUSTER_PD: power-domain-cluster { 455 #power-domain-cells = <0>; 456 domain-idle-states = <&CLUSTER_SLEEP_0>, 457 <&CLUSTER_SLEEP_1>; 458 }; 459 }; 460 461 reserved_memory: reserved-memory { 462 #address-cells = <2>; 463 #size-cells = <2>; 464 ranges; 465 466 hyp_mem: hyp@80000000 { 467 reg = <0 0x80000000 0 0xe00000>; 468 no-map; 469 }; 470 471 cpusys_vm_mem: cpusys-vm@80e00000 { 472 reg = <0 0x80e00000 0 0x400000>; 473 no-map; 474 }; 475 476 /* Merged xbl_dtlog, xbl_ramdump and aop_image regions */ 477 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 { 478 reg = <0 0x81a00000 0 0x260000>; 479 no-map; 480 }; 481 482 aop_cmd_db_mem: aop-cmd-db@81c60000 { 483 compatible = "qcom,cmd-db"; 484 reg = <0 0x81c60000 0 0x20000>; 485 no-map; 486 }; 487 488 /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ 489 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 490 reg = <0 0x81c80000 0 0x74000>; 491 no-map; 492 }; 493 494 /* Secdata region can be reused by apps */ 495 496 smem: smem@81d00000 { 497 compatible = "qcom,smem"; 498 reg = <0 0x81d00000 0 0x200000>; 499 hwlocks = <&tcsr_mutex 3>; 500 no-map; 501 }; 502 503 adsp_mhi_mem: adsp-mhi@81f00000 { 504 reg = <0 0x81f00000 0 0x20000>; 505 no-map; 506 }; 507 508 pvmfw_mem: pvmfw@824a0000 { 509 reg = <0 0x824a0000 0 0x100000>; 510 no-map; 511 }; 512 513 global_sync_mem: global-sync@82600000 { 514 reg = <0 0x82600000 0 0x100000>; 515 no-map; 516 }; 517 518 tz_stat_mem: tz-stat@82700000 { 519 reg = <0 0x82700000 0 0x100000>; 520 no-map; 521 }; 522 523 qdss_mem: qdss@82800000 { 524 reg = <0 0x82800000 0 0x2000000>; 525 no-map; 526 }; 527 528 mpss_dsm_mem: mpss-dsm@86b00000 { 529 reg = <0 0x86b00000 0 0x4900000>; 530 no-map; 531 }; 532 533 mpss_dsm_mem_2: mpss-dsm-2@8b400000 { 534 reg = <0 0x8b400000 0 0x800000>; 535 no-map; 536 }; 537 538 mpss_mem: mpss@8bc00000 { 539 reg = <0 0x8bc00000 0 0xf400000>; 540 no-map; 541 }; 542 543 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { 544 reg = <0 0x9b000000 0 0x80000>; 545 no-map; 546 }; 547 548 ipa_fw_mem: ipa-fw@9b080000 { 549 reg = <0 0x9b080000 0 0x10000>; 550 no-map; 551 }; 552 553 ipa_gsi_mem: ipa-gsi@9b090000 { 554 reg = <0 0x9b090000 0 0xa000>; 555 no-map; 556 }; 557 558 gpu_micro_code_mem: gpu-micro-code@9b09a000 { 559 reg = <0 0x9b09a000 0 0x2000>; 560 no-map; 561 }; 562 563 spss_region_mem: spss@9b0a0000 { 564 reg = <0 0x9b0a0000 0 0x1e0000>; 565 no-map; 566 }; 567 568 /* First part of the "SPU secure shared memory" region */ 569 spu_tz_shared_mem: spu-tz-shared@9b280000 { 570 reg = <0 0x9b280000 0 0x60000>; 571 no-map; 572 }; 573 574 /* Second part of the "SPU secure shared memory" region */ 575 spu_modem_shared_mem: spu-modem-shared@9b2e0000 { 576 reg = <0 0x9b2e0000 0 0x20000>; 577 no-map; 578 }; 579 580 camera_mem: camera@9b300000 { 581 reg = <0 0x9b300000 0 0x800000>; 582 no-map; 583 }; 584 585 video_mem: video@9bb00000 { 586 reg = <0 0x9bb00000 0 0x800000>; 587 no-map; 588 }; 589 590 cvp_mem: cvp@9c300000 { 591 reg = <0 0x9c300000 0 0x700000>; 592 no-map; 593 }; 594 595 cdsp_mem: cdsp@9ca00000 { 596 reg = <0 0x9ca00000 0 0x1400000>; 597 no-map; 598 }; 599 600 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 { 601 reg = <0 0x9de00000 0 0x80000>; 602 no-map; 603 }; 604 605 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 { 606 reg = <0 0x9de80000 0 0x80000>; 607 no-map; 608 }; 609 610 adspslpi_mem: adspslpi@9df00000 { 611 reg = <0 0x9df00000 0 0x4080000>; 612 no-map; 613 }; 614 615 rmtfs_mem: rmtfs@d7c00000 { 616 compatible = "qcom,rmtfs-mem"; 617 reg = <0 0xd7c00000 0 0x400000>; 618 no-map; 619 620 qcom,client-id = <1>; 621 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 622 }; 623 624 /* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */ 625 tz_merged_mem: tz-merged@d8000000 { 626 reg = <0 0xd8000000 0 0x800000>; 627 no-map; 628 }; 629 630 hwfence_shbuf: hwfence-shbuf@e6440000 { 631 reg = <0 0xe6440000 0 0x2dd000>; 632 no-map; 633 }; 634 635 trust_ui_vm_mem: trust-ui-vm@f3800000 { 636 reg = <0 0xf3800000 0 0x4400000>; 637 no-map; 638 }; 639 640 oem_vm_mem: oem-vm@f7c00000 { 641 reg = <0 0xf7c00000 0 0x4c00000>; 642 no-map; 643 }; 644 645 llcc_lpi_mem: llcc-lpi@ff800000 { 646 reg = <0 0xff800000 0 0x600000>; 647 no-map; 648 }; 649 }; 650 651 smp2p-adsp { 652 compatible = "qcom,smp2p"; 653 654 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 655 IPCC_MPROC_SIGNAL_SMP2P 656 IRQ_TYPE_EDGE_RISING>; 657 658 mboxes = <&ipcc IPCC_CLIENT_LPASS 659 IPCC_MPROC_SIGNAL_SMP2P>; 660 661 qcom,smem = <443>, <429>; 662 qcom,local-pid = <0>; 663 qcom,remote-pid = <2>; 664 665 smp2p_adsp_out: master-kernel { 666 qcom,entry-name = "master-kernel"; 667 #qcom,smem-state-cells = <1>; 668 }; 669 670 smp2p_adsp_in: slave-kernel { 671 qcom,entry-name = "slave-kernel"; 672 interrupt-controller; 673 #interrupt-cells = <2>; 674 }; 675 }; 676 677 smp2p-cdsp { 678 compatible = "qcom,smp2p"; 679 680 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 681 IPCC_MPROC_SIGNAL_SMP2P 682 IRQ_TYPE_EDGE_RISING>; 683 684 mboxes = <&ipcc IPCC_CLIENT_CDSP 685 IPCC_MPROC_SIGNAL_SMP2P>; 686 687 qcom,smem = <94>, <432>; 688 qcom,local-pid = <0>; 689 qcom,remote-pid = <5>; 690 691 smp2p_cdsp_out: master-kernel { 692 qcom,entry-name = "master-kernel"; 693 #qcom,smem-state-cells = <1>; 694 }; 695 696 smp2p_cdsp_in: slave-kernel { 697 qcom,entry-name = "slave-kernel"; 698 interrupt-controller; 699 #interrupt-cells = <2>; 700 }; 701 }; 702 703 smp2p-modem { 704 compatible = "qcom,smp2p"; 705 706 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 707 IPCC_MPROC_SIGNAL_SMP2P 708 IRQ_TYPE_EDGE_RISING>; 709 710 mboxes = <&ipcc IPCC_CLIENT_MPSS 711 IPCC_MPROC_SIGNAL_SMP2P>; 712 713 qcom,smem = <435>, <428>; 714 qcom,local-pid = <0>; 715 qcom,remote-pid = <1>; 716 717 smp2p_modem_out: master-kernel { 718 qcom,entry-name = "master-kernel"; 719 #qcom,smem-state-cells = <1>; 720 }; 721 722 smp2p_modem_in: slave-kernel { 723 qcom,entry-name = "slave-kernel"; 724 interrupt-controller; 725 #interrupt-cells = <2>; 726 }; 727 728 ipa_smp2p_out: ipa-ap-to-modem { 729 qcom,entry-name = "ipa"; 730 #qcom,smem-state-cells = <1>; 731 }; 732 733 ipa_smp2p_in: ipa-modem-to-ap { 734 qcom,entry-name = "ipa"; 735 interrupt-controller; 736 #interrupt-cells = <2>; 737 }; 738 }; 739 740 soc: soc@0 { 741 compatible = "simple-bus"; 742 743 #address-cells = <2>; 744 #size-cells = <2>; 745 dma-ranges = <0 0 0 0 0x10 0>; 746 ranges = <0 0 0 0 0x10 0>; 747 748 gcc: clock-controller@100000 { 749 compatible = "qcom,sm8650-gcc"; 750 reg = <0 0x00100000 0 0x1f4200>; 751 752 clocks = <&bi_tcxo_div2>, 753 <&bi_tcxo_ao_div2>, 754 <&sleep_clk>, 755 <&pcie0_phy>, 756 <&pcie1_phy>, 757 <&pcie_1_phy_aux_clk>, 758 <&ufs_mem_phy 0>, 759 <&ufs_mem_phy 1>, 760 <&ufs_mem_phy 2>, 761 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 762 763 #clock-cells = <1>; 764 #reset-cells = <1>; 765 #power-domain-cells = <1>; 766 }; 767 768 ipcc: mailbox@406000 { 769 compatible = "qcom,sm8650-ipcc", "qcom,ipcc"; 770 reg = <0 0x00406000 0 0x1000>; 771 772 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 773 interrupt-controller; 774 #interrupt-cells = <3>; 775 776 #mbox-cells = <2>; 777 }; 778 779 gpi_dma2: dma-controller@800000 { 780 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 781 reg = <0 0x00800000 0 0x60000>; 782 783 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 795 796 dma-channels = <12>; 797 dma-channel-mask = <0x3f>; 798 #dma-cells = <3>; 799 800 iommus = <&apps_smmu 0x436 0>; 801 802 dma-coherent; 803 804 status = "disabled"; 805 }; 806 807 qupv3_id_1: geniqup@8c0000 { 808 compatible = "qcom,geni-se-qup"; 809 reg = <0 0x008c0000 0 0x2000>; 810 811 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 812 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 813 clock-names = "m-ahb", 814 "s-ahb"; 815 816 iommus = <&apps_smmu 0x423 0>; 817 818 dma-coherent; 819 820 #address-cells = <2>; 821 #size-cells = <2>; 822 ranges; 823 824 status = "disabled"; 825 826 i2c8: i2c@880000 { 827 compatible = "qcom,geni-i2c"; 828 reg = <0 0x00880000 0 0x4000>; 829 830 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 831 832 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 833 clock-names = "se"; 834 835 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 836 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 837 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 838 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 839 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 840 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 841 interconnect-names = "qup-core", 842 "qup-config", 843 "qup-memory"; 844 845 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 846 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 847 dma-names = "tx", 848 "rx"; 849 850 pinctrl-0 = <&qup_i2c8_data_clk>; 851 pinctrl-names = "default"; 852 853 #address-cells = <1>; 854 #size-cells = <0>; 855 856 status = "disabled"; 857 }; 858 859 spi8: spi@880000 { 860 compatible = "qcom,geni-spi"; 861 reg = <0 0x00880000 0 0x4000>; 862 863 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 864 865 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 866 clock-names = "se"; 867 868 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 869 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 870 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 871 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 872 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 873 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 874 interconnect-names = "qup-core", 875 "qup-config", 876 "qup-memory"; 877 878 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 879 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 880 dma-names = "tx", 881 "rx"; 882 883 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 884 pinctrl-names = "default"; 885 886 #address-cells = <1>; 887 #size-cells = <0>; 888 889 status = "disabled"; 890 }; 891 892 i2c9: i2c@884000 { 893 compatible = "qcom,geni-i2c"; 894 reg = <0 0x00884000 0 0x4000>; 895 896 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 897 898 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 899 clock-names = "se"; 900 901 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 902 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 903 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 904 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 905 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 906 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 907 interconnect-names = "qup-core", 908 "qup-config", 909 "qup-memory"; 910 911 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 912 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 913 dma-names = "tx", 914 "rx"; 915 916 pinctrl-0 = <&qup_i2c9_data_clk>; 917 pinctrl-names = "default"; 918 919 #address-cells = <1>; 920 #size-cells = <0>; 921 922 status = "disabled"; 923 }; 924 925 spi9: spi@884000 { 926 compatible = "qcom,geni-spi"; 927 reg = <0 0x00884000 0 0x4000>; 928 929 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 930 931 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 932 clock-names = "se"; 933 934 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 935 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 936 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 937 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 938 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 939 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 940 interconnect-names = "qup-core", 941 "qup-config", 942 "qup-memory"; 943 944 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 945 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 946 dma-names = "tx", 947 "rx"; 948 949 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 950 pinctrl-names = "default"; 951 952 #address-cells = <1>; 953 #size-cells = <0>; 954 955 status = "disabled"; 956 }; 957 958 i2c10: i2c@888000 { 959 compatible = "qcom,geni-i2c"; 960 reg = <0 0x00888000 0 0x4000>; 961 962 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 963 964 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 965 clock-names = "se"; 966 967 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 968 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 969 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 970 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 971 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 972 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 973 interconnect-names = "qup-core", 974 "qup-config", 975 "qup-memory"; 976 977 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 978 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 979 dma-names = "tx", 980 "rx"; 981 982 pinctrl-0 = <&qup_i2c10_data_clk>; 983 pinctrl-names = "default"; 984 985 #address-cells = <1>; 986 #size-cells = <0>; 987 988 status = "disabled"; 989 }; 990 991 spi10: spi@888000 { 992 compatible = "qcom,geni-spi"; 993 reg = <0 0x00888000 0 0x4000>; 994 995 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 996 997 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 998 clock-names = "se"; 999 1000 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1001 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1002 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1003 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1004 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1005 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1006 interconnect-names = "qup-core", 1007 "qup-config", 1008 "qup-memory"; 1009 1010 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1011 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1012 dma-names = "tx", 1013 "rx"; 1014 1015 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1016 pinctrl-names = "default"; 1017 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 1021 status = "disabled"; 1022 }; 1023 1024 i2c11: i2c@88c000 { 1025 compatible = "qcom,geni-i2c"; 1026 reg = <0 0x0088c000 0 0x4000>; 1027 1028 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1029 1030 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1031 clock-names = "se"; 1032 1033 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1034 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1035 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1036 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1037 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1038 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1039 interconnect-names = "qup-core", 1040 "qup-config", 1041 "qup-memory"; 1042 1043 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1044 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1045 dma-names = "tx", 1046 "rx"; 1047 1048 pinctrl-0 = <&qup_i2c11_data_clk>; 1049 pinctrl-names = "default"; 1050 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 1054 status = "disabled"; 1055 }; 1056 1057 spi11: spi@88c000 { 1058 compatible = "qcom,geni-spi"; 1059 reg = <0 0x0088c000 0 0x4000>; 1060 1061 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1062 1063 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1064 clock-names = "se"; 1065 1066 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1067 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1068 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1069 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1070 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1071 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1072 interconnect-names = "qup-core", 1073 "qup-config", 1074 "qup-memory"; 1075 1076 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1077 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1078 dma-names = "tx", 1079 "rx"; 1080 1081 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1082 pinctrl-names = "default"; 1083 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 1087 status = "disabled"; 1088 }; 1089 1090 i2c12: i2c@890000 { 1091 compatible = "qcom,geni-i2c"; 1092 reg = <0 0x00890000 0 0x4000>; 1093 1094 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1095 1096 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1097 clock-names = "se"; 1098 1099 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1100 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1101 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1102 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1103 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1104 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1105 interconnect-names = "qup-core", 1106 "qup-config", 1107 "qup-memory"; 1108 1109 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1110 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1111 dma-names = "tx", 1112 "rx"; 1113 1114 pinctrl-0 = <&qup_i2c12_data_clk>; 1115 pinctrl-names = "default"; 1116 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 1120 status = "disabled"; 1121 }; 1122 1123 spi12: spi@890000 { 1124 compatible = "qcom,geni-spi"; 1125 reg = <0 0x00890000 0 0x4000>; 1126 1127 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1128 1129 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1130 clock-names = "se"; 1131 1132 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1133 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1134 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1135 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1136 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1137 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1138 interconnect-names = "qup-core", 1139 "qup-config", 1140 "qup-memory"; 1141 1142 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1143 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1144 dma-names = "tx", 1145 "rx"; 1146 1147 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1148 pinctrl-names = "default"; 1149 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 1153 status = "disabled"; 1154 }; 1155 1156 i2c13: i2c@894000 { 1157 compatible = "qcom,geni-i2c"; 1158 reg = <0 0x00894000 0 0x4000>; 1159 1160 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1161 1162 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1163 clock-names = "se"; 1164 1165 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1166 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1167 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1168 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1169 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1170 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1171 interconnect-names = "qup-core", 1172 "qup-config", 1173 "qup-memory"; 1174 1175 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1176 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1177 dma-names = "tx", 1178 "rx"; 1179 1180 pinctrl-0 = <&qup_i2c13_data_clk>; 1181 pinctrl-names = "default"; 1182 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 1186 status = "disabled"; 1187 }; 1188 1189 spi13: spi@894000 { 1190 compatible = "qcom,geni-spi"; 1191 reg = <0 0x00894000 0 0x4000>; 1192 1193 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1194 1195 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1196 clock-names = "se"; 1197 1198 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1199 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1200 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1201 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1202 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1203 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1204 interconnect-names = "qup-core", 1205 "qup-config", 1206 "qup-memory"; 1207 1208 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1209 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1210 dma-names = "tx", 1211 "rx"; 1212 1213 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1214 pinctrl-names = "default"; 1215 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 1219 status = "disabled"; 1220 }; 1221 1222 uart14: serial@898000 { 1223 compatible = "qcom,geni-uart"; 1224 reg = <0 0x00898000 0 0x4000>; 1225 1226 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1227 1228 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1229 clock-names = "se"; 1230 1231 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1232 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1233 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1234 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1235 interconnect-names = "qup-core", 1236 "qup-config"; 1237 1238 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1239 pinctrl-names = "default"; 1240 1241 status = "disabled"; 1242 }; 1243 1244 uart15: serial@89c000 { 1245 compatible = "qcom,geni-debug-uart"; 1246 reg = <0 0x0089c000 0 0x4000>; 1247 1248 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1249 1250 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1251 clock-names = "se"; 1252 1253 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1254 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1255 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1256 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1257 interconnect-names = "qup-core", 1258 "qup-config"; 1259 1260 pinctrl-0 = <&qup_uart15_default>; 1261 pinctrl-names = "default"; 1262 1263 status = "disabled"; 1264 }; 1265 }; 1266 1267 i2c_master_hub_0: geniqup@9c0000 { 1268 compatible = "qcom,geni-se-i2c-master-hub"; 1269 reg = <0 0x009c0000 0 0x2000>; 1270 1271 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1272 clock-names = "s-ahb"; 1273 1274 #address-cells = <2>; 1275 #size-cells = <2>; 1276 ranges; 1277 1278 status = "disabled"; 1279 1280 i2c_hub_0: i2c@980000 { 1281 compatible = "qcom,geni-i2c-master-hub"; 1282 reg = <0 0x00980000 0 0x4000>; 1283 1284 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1285 1286 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1287 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1288 clock-names = "se", 1289 "core"; 1290 1291 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1292 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1293 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1294 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1295 interconnect-names = "qup-core", 1296 "qup-config"; 1297 1298 pinctrl-0 = <&hub_i2c0_data_clk>; 1299 pinctrl-names = "default"; 1300 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 1304 status = "disabled"; 1305 }; 1306 1307 i2c_hub_1: i2c@984000 { 1308 compatible = "qcom,geni-i2c-master-hub"; 1309 reg = <0 0x00984000 0 0x4000>; 1310 1311 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1312 1313 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1314 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1315 clock-names = "se", 1316 "core"; 1317 1318 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1319 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1320 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1321 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1322 interconnect-names = "qup-core", 1323 "qup-config"; 1324 1325 pinctrl-0 = <&hub_i2c1_data_clk>; 1326 pinctrl-names = "default"; 1327 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 1331 status = "disabled"; 1332 }; 1333 1334 i2c_hub_2: i2c@988000 { 1335 compatible = "qcom,geni-i2c-master-hub"; 1336 reg = <0 0x00988000 0 0x4000>; 1337 1338 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1339 1340 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1341 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1342 clock-names = "se", 1343 "core"; 1344 1345 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1346 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1347 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1348 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1349 interconnect-names = "qup-core", 1350 "qup-config"; 1351 1352 pinctrl-0 = <&hub_i2c2_data_clk>; 1353 pinctrl-names = "default"; 1354 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 1358 status = "disabled"; 1359 }; 1360 1361 i2c_hub_3: i2c@98c000 { 1362 compatible = "qcom,geni-i2c-master-hub"; 1363 reg = <0 0x0098c000 0 0x4000>; 1364 1365 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1366 1367 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1368 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1369 clock-names = "se", 1370 "core"; 1371 1372 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1373 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1374 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1375 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1376 interconnect-names = "qup-core", 1377 "qup-config"; 1378 1379 pinctrl-0 = <&hub_i2c3_data_clk>; 1380 pinctrl-names = "default"; 1381 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 1385 status = "disabled"; 1386 }; 1387 1388 i2c_hub_4: i2c@990000 { 1389 compatible = "qcom,geni-i2c-master-hub"; 1390 reg = <0 0x00990000 0 0x4000>; 1391 1392 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1393 1394 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1395 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1396 clock-names = "se", 1397 "core"; 1398 1399 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1400 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1401 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1402 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1403 interconnect-names = "qup-core", 1404 "qup-config"; 1405 1406 pinctrl-0 = <&hub_i2c4_data_clk>; 1407 pinctrl-names = "default"; 1408 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 1412 status = "disabled"; 1413 }; 1414 1415 i2c_hub_5: i2c@994000 { 1416 compatible = "qcom,geni-i2c-master-hub"; 1417 reg = <0 0x00994000 0 0x4000>; 1418 1419 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1420 1421 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1422 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1423 clock-names = "se", 1424 "core"; 1425 1426 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1427 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1428 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1429 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1430 interconnect-names = "qup-core", 1431 "qup-config"; 1432 1433 pinctrl-0 = <&hub_i2c5_data_clk>; 1434 pinctrl-names = "default"; 1435 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 1439 status = "disabled"; 1440 }; 1441 1442 i2c_hub_6: i2c@998000 { 1443 compatible = "qcom,geni-i2c-master-hub"; 1444 reg = <0 0x00998000 0 0x4000>; 1445 1446 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1447 1448 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1449 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1450 clock-names = "se", 1451 "core"; 1452 1453 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1454 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1455 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1456 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1457 interconnect-names = "qup-core", 1458 "qup-config"; 1459 1460 pinctrl-0 = <&hub_i2c6_data_clk>; 1461 pinctrl-names = "default"; 1462 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 1466 status = "disabled"; 1467 }; 1468 1469 i2c_hub_7: i2c@99c000 { 1470 compatible = "qcom,geni-i2c-master-hub"; 1471 reg = <0 0x0099c000 0 0x4000>; 1472 1473 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1474 1475 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1476 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1477 clock-names = "se", 1478 "core"; 1479 1480 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1481 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1482 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1483 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1484 interconnect-names = "qup-core", 1485 "qup-config"; 1486 1487 pinctrl-0 = <&hub_i2c7_data_clk>; 1488 pinctrl-names = "default"; 1489 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 1493 status = "disabled"; 1494 }; 1495 1496 i2c_hub_8: i2c@9a0000 { 1497 compatible = "qcom,geni-i2c-master-hub"; 1498 reg = <0 0x009a0000 0 0x4000>; 1499 1500 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1501 1502 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1503 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1504 clock-names = "se", 1505 "core"; 1506 1507 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1508 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1509 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1510 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1511 interconnect-names = "qup-core", 1512 "qup-config"; 1513 1514 pinctrl-0 = <&hub_i2c8_data_clk>; 1515 pinctrl-names = "default"; 1516 1517 #address-cells = <1>; 1518 #size-cells = <0>; 1519 1520 status = "disabled"; 1521 }; 1522 1523 i2c_hub_9: i2c@9a4000 { 1524 compatible = "qcom,geni-i2c-master-hub"; 1525 reg = <0 0x009a4000 0 0x4000>; 1526 1527 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1528 1529 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1530 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1531 clock-names = "se", 1532 "core"; 1533 1534 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1535 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1536 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1537 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1538 interconnect-names = "qup-core", 1539 "qup-config"; 1540 1541 pinctrl-0 = <&hub_i2c9_data_clk>; 1542 pinctrl-names = "default"; 1543 1544 #address-cells = <1>; 1545 #size-cells = <0>; 1546 1547 status = "disabled"; 1548 }; 1549 }; 1550 1551 gpi_dma1: dma-controller@a00000 { 1552 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 1553 reg = <0 0x00a00000 0 0x60000>; 1554 1555 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1558 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1559 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1567 1568 dma-channels = <12>; 1569 dma-channel-mask = <0xc>; 1570 #dma-cells = <3>; 1571 1572 iommus = <&apps_smmu 0xb6 0>; 1573 dma-coherent; 1574 1575 status = "disabled"; 1576 }; 1577 1578 qupv3_id_0: geniqup@ac0000 { 1579 compatible = "qcom,geni-se-qup"; 1580 reg = <0 0x00ac0000 0 0x2000>; 1581 1582 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1583 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1584 clock-names = "m-ahb", 1585 "s-ahb"; 1586 1587 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1588 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 1589 interconnect-names = "qup-core"; 1590 1591 iommus = <&apps_smmu 0xa3 0>; 1592 1593 dma-coherent; 1594 1595 #address-cells = <2>; 1596 #size-cells = <2>; 1597 ranges; 1598 1599 status = "disabled"; 1600 1601 i2c0: i2c@a80000 { 1602 compatible = "qcom,geni-i2c"; 1603 reg = <0 0x00a80000 0 0x4000>; 1604 1605 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1606 1607 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1608 clock-names = "se"; 1609 1610 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1611 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1612 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1613 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1614 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1615 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1616 interconnect-names = "qup-core", 1617 "qup-config", 1618 "qup-memory"; 1619 1620 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1621 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1622 dma-names = "tx", 1623 "rx"; 1624 1625 pinctrl-0 = <&qup_i2c0_data_clk>; 1626 pinctrl-names = "default"; 1627 1628 #address-cells = <1>; 1629 #size-cells = <0>; 1630 1631 status = "disabled"; 1632 }; 1633 1634 spi0: spi@a80000 { 1635 compatible = "qcom,geni-spi"; 1636 reg = <0 0x00a80000 0 0x4000>; 1637 1638 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1639 1640 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1641 clock-names = "se"; 1642 1643 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1644 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1645 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1646 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1647 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1648 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1649 interconnect-names = "qup-core", 1650 "qup-config", 1651 "qup-memory"; 1652 1653 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1654 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1655 dma-names = "tx", 1656 "rx"; 1657 1658 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1659 pinctrl-names = "default"; 1660 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 1664 status = "disabled"; 1665 }; 1666 1667 i2c1: i2c@a84000 { 1668 compatible = "qcom,geni-i2c"; 1669 reg = <0 0x00a84000 0 0x4000>; 1670 1671 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1672 1673 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1674 clock-names = "se"; 1675 1676 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1677 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1678 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1679 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1680 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1681 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1682 interconnect-names = "qup-core", 1683 "qup-config", 1684 "qup-memory"; 1685 1686 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1687 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1688 dma-names = "tx", 1689 "rx"; 1690 1691 pinctrl-0 = <&qup_i2c1_data_clk>; 1692 pinctrl-names = "default"; 1693 1694 #address-cells = <1>; 1695 #size-cells = <0>; 1696 1697 status = "disabled"; 1698 }; 1699 1700 spi1: spi@a84000 { 1701 compatible = "qcom,geni-spi"; 1702 reg = <0 0x00a84000 0 0x4000>; 1703 1704 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1705 1706 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1707 clock-names = "se"; 1708 1709 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1710 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1711 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1712 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1713 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1714 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1715 interconnect-names = "qup-core", 1716 "qup-config", 1717 "qup-memory"; 1718 1719 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1720 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1721 dma-names = "tx", 1722 "rx"; 1723 1724 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1725 pinctrl-names = "default"; 1726 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 1730 status = "disabled"; 1731 }; 1732 1733 i2c2: i2c@a88000 { 1734 compatible = "qcom,geni-i2c"; 1735 reg = <0 0x00a88000 0 0x4000>; 1736 1737 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1738 1739 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1740 clock-names = "se"; 1741 1742 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1743 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1744 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1745 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1746 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1747 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1748 interconnect-names = "qup-core", 1749 "qup-config", 1750 "qup-memory"; 1751 1752 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1753 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1754 dma-names = "tx", 1755 "rx"; 1756 1757 pinctrl-0 = <&qup_i2c2_data_clk>; 1758 pinctrl-names = "default"; 1759 1760 #address-cells = <1>; 1761 #size-cells = <0>; 1762 1763 status = "disabled"; 1764 }; 1765 1766 spi2: spi@a88000 { 1767 compatible = "qcom,geni-spi"; 1768 reg = <0 0x00a88000 0 0x4000>; 1769 1770 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1771 1772 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1773 clock-names = "se"; 1774 1775 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1776 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1777 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1778 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1779 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1780 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1781 interconnect-names = "qup-core", 1782 "qup-config", 1783 "qup-memory"; 1784 1785 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1786 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1787 dma-names = "tx", 1788 "rx"; 1789 1790 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1791 pinctrl-names = "default"; 1792 1793 #address-cells = <1>; 1794 #size-cells = <0>; 1795 1796 status = "disabled"; 1797 }; 1798 1799 i2c3: i2c@a8c000 { 1800 compatible = "qcom,geni-i2c"; 1801 reg = <0 0x00a8c000 0 0x4000>; 1802 1803 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1804 1805 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1806 clock-names = "se"; 1807 1808 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1809 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1810 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1811 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1812 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1813 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1814 interconnect-names = "qup-core", 1815 "qup-config", 1816 "qup-memory"; 1817 1818 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1819 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1820 dma-names = "tx", 1821 "rx"; 1822 1823 pinctrl-0 = <&qup_i2c3_data_clk>; 1824 pinctrl-names = "default"; 1825 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 1829 status = "disabled"; 1830 }; 1831 1832 spi3: spi@a8c000 { 1833 compatible = "qcom,geni-spi"; 1834 reg = <0 0x00a8c000 0 0x4000>; 1835 1836 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1837 1838 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1839 clock-names = "se"; 1840 1841 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1842 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1843 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1844 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1845 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1846 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1847 interconnect-names = "qup-core", 1848 "qup-config", 1849 "qup-memory"; 1850 1851 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1852 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1853 dma-names = "tx", 1854 "rx"; 1855 1856 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1857 pinctrl-names = "default"; 1858 1859 #address-cells = <1>; 1860 #size-cells = <0>; 1861 1862 status = "disabled"; 1863 }; 1864 1865 i2c4: i2c@a90000 { 1866 compatible = "qcom,geni-i2c"; 1867 reg = <0 0x00a90000 0 0x4000>; 1868 1869 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1870 1871 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1872 clock-names = "se"; 1873 1874 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1875 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1876 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1877 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1878 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1879 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1880 interconnect-names = "qup-core", 1881 "qup-config", 1882 "qup-memory"; 1883 1884 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1885 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1886 dma-names = "tx", 1887 "rx"; 1888 1889 pinctrl-0 = <&qup_i2c4_data_clk>; 1890 pinctrl-names = "default"; 1891 1892 #address-cells = <1>; 1893 #size-cells = <0>; 1894 1895 status = "disabled"; 1896 }; 1897 1898 spi4: spi@a90000 { 1899 compatible = "qcom,geni-spi"; 1900 reg = <0 0x00a90000 0 0x4000>; 1901 1902 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1903 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1905 clock-names = "se"; 1906 1907 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1908 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1909 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1910 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1911 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1912 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1913 interconnect-names = "qup-core", 1914 "qup-config", 1915 "qup-memory"; 1916 1917 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1918 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1919 dma-names = "tx", 1920 "rx"; 1921 1922 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1923 pinctrl-names = "default"; 1924 1925 #address-cells = <1>; 1926 #size-cells = <0>; 1927 1928 status = "disabled"; 1929 }; 1930 1931 i2c5: i2c@a94000 { 1932 compatible = "qcom,geni-i2c"; 1933 reg = <0 0x00a94000 0 0x4000>; 1934 1935 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1936 1937 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1938 clock-names = "se"; 1939 1940 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1941 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1942 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1943 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1944 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1945 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1946 interconnect-names = "qup-core", 1947 "qup-config", 1948 "qup-memory"; 1949 1950 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1951 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1952 dma-names = "tx", 1953 "rx"; 1954 1955 pinctrl-0 = <&qup_i2c5_data_clk>; 1956 pinctrl-names = "default"; 1957 1958 #address-cells = <1>; 1959 #size-cells = <0>; 1960 1961 status = "disabled"; 1962 }; 1963 1964 spi5: spi@a94000 { 1965 compatible = "qcom,geni-spi"; 1966 reg = <0 0x00a94000 0 0x4000>; 1967 1968 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1969 1970 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1971 clock-names = "se"; 1972 1973 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1974 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1975 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1976 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1977 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1978 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1979 interconnect-names = "qup-core", 1980 "qup-config", 1981 "qup-memory"; 1982 1983 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1984 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1985 dma-names = "tx", 1986 "rx"; 1987 1988 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1989 pinctrl-names = "default"; 1990 1991 #address-cells = <1>; 1992 #size-cells = <0>; 1993 1994 status = "disabled"; 1995 }; 1996 1997 i2c6: i2c@a98000 { 1998 compatible = "qcom,geni-i2c"; 1999 reg = <0 0x00a98000 0 0x4000>; 2000 2001 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 2002 2003 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2004 clock-names = "se"; 2005 2006 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2007 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2008 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2009 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2010 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2011 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2012 interconnect-names = "qup-core", 2013 "qup-config", 2014 "qup-memory"; 2015 2016 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2017 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2018 dma-names = "tx", 2019 "rx"; 2020 2021 pinctrl-0 = <&qup_i2c6_data_clk>; 2022 pinctrl-names = "default"; 2023 2024 #address-cells = <1>; 2025 #size-cells = <0>; 2026 2027 status = "disabled"; 2028 }; 2029 2030 spi6: spi@a98000 { 2031 compatible = "qcom,geni-spi"; 2032 reg = <0 0x00a98000 0 0x4000>; 2033 2034 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 2035 2036 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2037 clock-names = "se"; 2038 2039 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2040 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2041 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2042 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2043 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2044 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2045 interconnect-names = "qup-core", 2046 "qup-config", 2047 "qup-memory"; 2048 2049 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2050 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2051 dma-names = "tx", 2052 "rx"; 2053 2054 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2055 pinctrl-names = "default"; 2056 2057 #address-cells = <1>; 2058 #size-cells = <0>; 2059 2060 status = "disabled"; 2061 }; 2062 2063 i2c7: i2c@a9c000 { 2064 compatible = "qcom,geni-i2c"; 2065 reg = <0 0x00a9c000 0 0x4000>; 2066 2067 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 2068 2069 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2070 clock-names = "se"; 2071 2072 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2073 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2074 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2075 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2076 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2077 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2078 interconnect-names = "qup-core", 2079 "qup-config", 2080 "qup-memory"; 2081 2082 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2083 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2084 dma-names = "tx", 2085 "rx"; 2086 2087 pinctrl-0 = <&qup_i2c7_data_clk>; 2088 pinctrl-names = "default"; 2089 2090 #address-cells = <1>; 2091 #size-cells = <0>; 2092 2093 status = "disabled"; 2094 }; 2095 2096 spi7: spi@a9c000 { 2097 compatible = "qcom,geni-spi"; 2098 reg = <0 0x00a9c000 0 0x4000>; 2099 2100 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 2101 2102 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2103 clock-names = "se"; 2104 2105 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2106 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2107 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2108 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2109 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2110 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2111 interconnect-names = "qup-core", 2112 "qup-config", 2113 "qup-memory"; 2114 2115 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2116 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2117 dma-names = "tx", 2118 "rx"; 2119 2120 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2121 pinctrl-names = "default"; 2122 2123 #address-cells = <1>; 2124 #size-cells = <0>; 2125 2126 status = "disabled"; 2127 }; 2128 }; 2129 2130 cnoc_main: interconnect@1500000 { 2131 compatible = "qcom,sm8650-cnoc-main"; 2132 reg = <0 0x01500000 0 0x14080>; 2133 2134 qcom,bcm-voters = <&apps_bcm_voter>; 2135 2136 #interconnect-cells = <2>; 2137 }; 2138 2139 config_noc: interconnect@1600000 { 2140 compatible = "qcom,sm8650-config-noc"; 2141 reg = <0 0x01600000 0 0x6200>; 2142 2143 qcom,bcm-voters = <&apps_bcm_voter>; 2144 2145 #interconnect-cells = <2>; 2146 }; 2147 2148 system_noc: interconnect@1680000 { 2149 compatible = "qcom,sm8650-system-noc"; 2150 reg = <0 0x01680000 0 0x1d080>; 2151 2152 qcom,bcm-voters = <&apps_bcm_voter>; 2153 2154 #interconnect-cells = <2>; 2155 }; 2156 2157 pcie_noc: interconnect@16c0000 { 2158 compatible = "qcom,sm8650-pcie-anoc"; 2159 reg = <0 0x016c0000 0 0x12200>; 2160 2161 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2162 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 2163 2164 qcom,bcm-voters = <&apps_bcm_voter>; 2165 2166 #interconnect-cells = <2>; 2167 }; 2168 2169 aggre1_noc: interconnect@16e0000 { 2170 compatible = "qcom,sm8650-aggre1-noc"; 2171 reg = <0 0x016e0000 0 0x16400>; 2172 2173 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2174 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2175 2176 qcom,bcm-voters = <&apps_bcm_voter>; 2177 2178 #interconnect-cells = <2>; 2179 }; 2180 2181 aggre2_noc: interconnect@1700000 { 2182 compatible = "qcom,sm8650-aggre2-noc"; 2183 reg = <0 0x01700000 0 0x1e400>; 2184 2185 clocks = <&rpmhcc RPMH_IPA_CLK>; 2186 2187 qcom,bcm-voters = <&apps_bcm_voter>; 2188 2189 #interconnect-cells = <2>; 2190 }; 2191 2192 mmss_noc: interconnect@1780000 { 2193 compatible = "qcom,sm8650-mmss-noc"; 2194 reg = <0 0x01780000 0 0x5b800>; 2195 2196 qcom,bcm-voters = <&apps_bcm_voter>; 2197 2198 #interconnect-cells = <2>; 2199 }; 2200 2201 rng: rng@10c3000 { 2202 compatible = "qcom,sm8650-trng", "qcom,trng"; 2203 reg = <0 0x010c3000 0 0x1000>; 2204 }; 2205 2206 pcie0: pci@1c00000 { 2207 device_type = "pci"; 2208 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 2209 reg = <0 0x01c00000 0 0x3000>, 2210 <0 0x60000000 0 0xf1d>, 2211 <0 0x60000f20 0 0xa8>, 2212 <0 0x60001000 0 0x1000>, 2213 <0 0x60100000 0 0x100000>; 2214 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2215 2216 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 2217 interrupt-names = "msi"; 2218 2219 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2220 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2221 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2222 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2223 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2224 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2225 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2226 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2227 clock-names = "aux", 2228 "cfg", 2229 "bus_master", 2230 "bus_slave", 2231 "slave_q2a", 2232 "ddrss_sf_tbu", 2233 "noc_aggr", 2234 "cnoc_sf_axi"; 2235 2236 resets = <&gcc GCC_PCIE_0_BCR>; 2237 reset-names = "pci"; 2238 2239 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2240 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2241 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2242 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 2243 interconnect-names = "pcie-mem", 2244 "cpu-pcie"; 2245 2246 power-domains = <&gcc PCIE_0_GDSC>; 2247 2248 iommu-map = <0 &apps_smmu 0x1400 0x1>, 2249 <0x100 &apps_smmu 0x1401 0x1>; 2250 2251 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 2252 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 2253 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 2254 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 2255 interrupt-map-mask = <0 0 0 0x7>; 2256 #interrupt-cells = <1>; 2257 2258 linux,pci-domain = <0>; 2259 num-lanes = <2>; 2260 bus-range = <0 0xff>; 2261 2262 phys = <&pcie0_phy>; 2263 phy-names = "pciephy"; 2264 2265 #address-cells = <3>; 2266 #size-cells = <2>; 2267 ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, 2268 <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>; 2269 2270 dma-coherent; 2271 2272 status = "disabled"; 2273 }; 2274 2275 pcie0_phy: phy@1c06000 { 2276 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy"; 2277 reg = <0 0x01c06000 0 0x2000>; 2278 2279 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2280 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2281 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 2282 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2283 <&gcc GCC_PCIE_0_PIPE_CLK>; 2284 clock-names = "aux", 2285 "cfg_ahb", 2286 "ref", 2287 "rchng", 2288 "pipe"; 2289 2290 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2291 assigned-clock-rates = <100000000>; 2292 2293 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2294 reset-names = "phy"; 2295 2296 power-domains = <&gcc PCIE_0_PHY_GDSC>; 2297 2298 #clock-cells = <0>; 2299 clock-output-names = "pcie0_pipe_clk"; 2300 2301 #phy-cells = <0>; 2302 2303 status = "disabled"; 2304 }; 2305 2306 pcie1: pci@1c08000 { 2307 device_type = "pci"; 2308 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 2309 reg = <0 0x01c08000 0 0x3000>, 2310 <0 0x40000000 0 0xf1d>, 2311 <0 0x40000f20 0 0xa8>, 2312 <0 0x40001000 0 0x1000>, 2313 <0 0x40100000 0 0x100000>; 2314 reg-names = "parf", 2315 "dbi", 2316 "elbi", 2317 "atu", 2318 "config"; 2319 2320 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2321 interrupt-names = "msi"; 2322 2323 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2324 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2325 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2326 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2327 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2328 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2329 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2330 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2331 clock-names = "aux", 2332 "cfg", 2333 "bus_master", 2334 "bus_slave", 2335 "slave_q2a", 2336 "ddrss_sf_tbu", 2337 "noc_aggr", 2338 "cnoc_sf_axi"; 2339 2340 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2341 assigned-clock-rates = <19200000>; 2342 2343 resets = <&gcc GCC_PCIE_1_BCR>, 2344 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2345 reset-names = "pci", 2346 "link_down"; 2347 2348 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2349 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2350 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2351 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; 2352 interconnect-names = "pcie-mem", 2353 "cpu-pcie"; 2354 2355 power-domains = <&gcc PCIE_1_GDSC>; 2356 2357 iommu-map = <0 &apps_smmu 0x1480 0x1>, 2358 <0x100 &apps_smmu 0x1481 0x1>; 2359 2360 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2361 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2362 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2363 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2364 interrupt-map-mask = <0 0 0 0x7>; 2365 #interrupt-cells = <1>; 2366 2367 linux,pci-domain = <1>; 2368 num-lanes = <2>; 2369 bus-range = <0 0xff>; 2370 2371 phys = <&pcie1_phy>; 2372 phy-names = "pciephy"; 2373 2374 dma-coherent; 2375 2376 #address-cells = <3>; 2377 #size-cells = <2>; 2378 ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, 2379 <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; 2380 2381 status = "disabled"; 2382 }; 2383 2384 pcie1_phy: phy@1c0e000 { 2385 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy"; 2386 reg = <0 0x01c0e000 0 0x2000>; 2387 2388 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2389 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2390 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 2391 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2392 <&gcc GCC_PCIE_1_PIPE_CLK>; 2393 clock-names = "aux", 2394 "cfg_ahb", 2395 "ref", 2396 "rchng", 2397 "pipe"; 2398 2399 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2400 assigned-clock-rates = <100000000>; 2401 2402 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 2403 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 2404 reset-names = "phy", 2405 "phy_nocsr"; 2406 2407 power-domains = <&gcc PCIE_1_PHY_GDSC>; 2408 2409 #clock-cells = <0>; 2410 clock-output-names = "pcie1_pipe_clk"; 2411 2412 #phy-cells = <0>; 2413 2414 status = "disabled"; 2415 }; 2416 2417 cryptobam: dma-controller@1dc4000 { 2418 compatible = "qcom,bam-v1.7.0"; 2419 reg = <0 0x01dc4000 0 0x28000>; 2420 2421 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2422 2423 #dma-cells = <1>; 2424 2425 iommus = <&apps_smmu 0x480 0>, 2426 <&apps_smmu 0x481 0>; 2427 2428 qcom,ee = <0>; 2429 qcom,controlled-remotely; 2430 }; 2431 2432 crypto: crypto@1dfa000 { 2433 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; 2434 reg = <0 0x01dfa000 0 0x6000>; 2435 2436 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 2437 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2438 interconnect-names = "memory"; 2439 2440 dmas = <&cryptobam 4>, <&cryptobam 5>; 2441 dma-names = "rx", "tx"; 2442 2443 iommus = <&apps_smmu 0x480 0>, 2444 <&apps_smmu 0x481 0>; 2445 }; 2446 2447 ufs_mem_phy: phy@1d80000 { 2448 compatible = "qcom,sm8650-qmp-ufs-phy"; 2449 reg = <0 0x01d80000 0 0x2000>; 2450 2451 clocks = <&tcsr TCSR_UFS_CLKREF_EN>, 2452 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2453 clock-names = "ref", 2454 "ref_aux"; 2455 2456 resets = <&ufs_mem_hc 0>; 2457 reset-names = "ufsphy"; 2458 2459 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 2460 2461 #clock-cells = <1>; 2462 #phy-cells = <0>; 2463 2464 status = "disabled"; 2465 }; 2466 2467 ufs_mem_hc: ufs@1d84000 { 2468 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2469 reg = <0 0x01d84000 0 0x3000>; 2470 2471 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2472 2473 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2474 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2475 <&gcc GCC_UFS_PHY_AHB_CLK>, 2476 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2477 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 2478 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2479 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2480 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2481 clock-names = "core_clk", 2482 "bus_aggr_clk", 2483 "iface_clk", 2484 "core_clk_unipro", 2485 "ref_clk", 2486 "tx_lane0_sync_clk", 2487 "rx_lane0_sync_clk", 2488 "rx_lane1_sync_clk"; 2489 freq-table-hz = <100000000 403000000>, 2490 <0 0>, 2491 <0 0>, 2492 <100000000 403000000>, 2493 <100000000 403000000>, 2494 <0 0>, 2495 <0 0>, 2496 <0 0>; 2497 2498 resets = <&gcc GCC_UFS_PHY_BCR>; 2499 reset-names = "rst"; 2500 2501 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2502 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2503 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2504 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2505 interconnect-names = "ufs-ddr", 2506 "cpu-ufs"; 2507 2508 power-domains = <&gcc UFS_PHY_GDSC>; 2509 required-opps = <&rpmhpd_opp_nom>; 2510 2511 iommus = <&apps_smmu 0x60 0>; 2512 2513 lanes-per-direction = <2>; 2514 qcom,ice = <&ice>; 2515 2516 phys = <&ufs_mem_phy>; 2517 phy-names = "ufsphy"; 2518 2519 #reset-cells = <1>; 2520 2521 status = "disabled"; 2522 }; 2523 2524 ice: crypto@1d88000 { 2525 compatible = "qcom,sm8650-inline-crypto-engine", 2526 "qcom,inline-crypto-engine"; 2527 reg = <0 0x01d88000 0 0x8000>; 2528 2529 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2530 }; 2531 2532 tcsr_mutex: hwlock@1f40000 { 2533 compatible = "qcom,tcsr-mutex"; 2534 reg = <0 0x01f40000 0 0x20000>; 2535 2536 #hwlock-cells = <1>; 2537 }; 2538 2539 tcsr: clock-controller@1fc0000 { 2540 compatible = "qcom,sm8650-tcsr", "syscon"; 2541 reg = <0 0x01fc0000 0 0xa0000>; 2542 2543 clocks = <&rpmhcc RPMH_CXO_CLK>; 2544 2545 #clock-cells = <1>; 2546 #reset-cells = <1>; 2547 }; 2548 2549 gpucc: clock-controller@3d90000 { 2550 compatible = "qcom,sm8650-gpucc"; 2551 reg = <0 0x03d90000 0 0xa000>; 2552 2553 clocks = <&bi_tcxo_div2>, 2554 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2555 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2556 2557 #clock-cells = <1>; 2558 #reset-cells = <1>; 2559 #power-domain-cells = <1>; 2560 }; 2561 2562 ipa: ipa@3f40000 { 2563 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; 2564 2565 iommus = <&apps_smmu 0x4a0 0x0>, 2566 <&apps_smmu 0x4a2 0x0>; 2567 reg = <0 0x3f40000 0 0x10000>, 2568 <0 0x3f50000 0 0x5000>, 2569 <0 0x3e04000 0 0xfc000>; 2570 reg-names = "ipa-reg", 2571 "ipa-shared", 2572 "gsi"; 2573 2574 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2575 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2576 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2577 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2578 interrupt-names = "ipa", 2579 "gsi", 2580 "ipa-clock-query", 2581 "ipa-setup-ready"; 2582 2583 clocks = <&rpmhcc RPMH_IPA_CLK>; 2584 clock-names = "core"; 2585 2586 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2587 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2588 interconnect-names = "memory", 2589 "config"; 2590 2591 qcom,qmp = <&aoss_qmp>; 2592 2593 qcom,smem-states = <&ipa_smp2p_out 0>, 2594 <&ipa_smp2p_out 1>; 2595 qcom,smem-state-names = "ipa-clock-enabled-valid", 2596 "ipa-clock-enabled"; 2597 2598 status = "disabled"; 2599 }; 2600 2601 remoteproc_mpss: remoteproc@4080000 { 2602 compatible = "qcom,sm8650-mpss-pas"; 2603 reg = <0 0x04080000 0 0x4040>; 2604 2605 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2606 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2607 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2608 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2609 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2610 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2611 interrupt-names = "wdog", 2612 "fatal", 2613 "ready", 2614 "handover", 2615 "stop-ack", 2616 "shutdown-ack"; 2617 2618 clocks = <&rpmhcc RPMH_CXO_CLK>; 2619 clock-names = "xo"; 2620 2621 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 2622 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2623 2624 power-domains = <&rpmhpd RPMHPD_CX>, 2625 <&rpmhpd RPMHPD_MSS>; 2626 power-domain-names = "cx", 2627 "mss"; 2628 2629 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, 2630 <&mpss_dsm_mem>, <&mpss_dsm_mem_2>; 2631 2632 qcom,qmp = <&aoss_qmp>; 2633 2634 qcom,smem-states = <&smp2p_modem_out 0>; 2635 qcom,smem-state-names = "stop"; 2636 2637 status = "disabled"; 2638 2639 glink-edge { 2640 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2641 IPCC_MPROC_SIGNAL_GLINK_QMP 2642 IRQ_TYPE_EDGE_RISING>; 2643 2644 mboxes = <&ipcc IPCC_CLIENT_MPSS 2645 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2646 2647 qcom,remote-pid = <1>; 2648 2649 label = "mpss"; 2650 }; 2651 }; 2652 2653 lpass_wsa2macro: codec@6aa0000 { 2654 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 2655 reg = <0 0x06aa0000 0 0x1000>; 2656 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2657 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2658 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2659 <&lpass_vamacro>; 2660 clock-names = "mclk", 2661 "macro", 2662 "dcodec", 2663 "fsgen"; 2664 2665 #clock-cells = <0>; 2666 clock-output-names = "wsa2-mclk"; 2667 #sound-dai-cells = <1>; 2668 }; 2669 2670 swr3: soundwire@6ab0000 { 2671 compatible = "qcom,soundwire-v2.0.0"; 2672 reg = <0 0x06ab0000 0 0x10000>; 2673 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2674 clocks = <&lpass_wsa2macro>; 2675 clock-names = "iface"; 2676 label = "WSA2"; 2677 2678 pinctrl-0 = <&wsa2_swr_active>; 2679 pinctrl-names = "default"; 2680 2681 qcom,din-ports = <4>; 2682 qcom,dout-ports = <9>; 2683 2684 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2685 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2686 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2687 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2688 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2689 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2690 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2691 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2692 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2693 2694 #address-cells = <2>; 2695 #size-cells = <0>; 2696 #sound-dai-cells = <1>; 2697 status = "disabled"; 2698 }; 2699 2700 lpass_rxmacro: codec@6ac0000 { 2701 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 2702 reg = <0 0x06ac0000 0 0x1000>; 2703 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2704 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2705 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2706 <&lpass_vamacro>; 2707 clock-names = "mclk", 2708 "macro", 2709 "dcodec", 2710 "fsgen"; 2711 2712 #clock-cells = <0>; 2713 clock-output-names = "mclk"; 2714 #sound-dai-cells = <1>; 2715 }; 2716 2717 swr1: soundwire@6ad0000 { 2718 compatible = "qcom,soundwire-v2.0.0"; 2719 reg = <0 0x06ad0000 0 0x10000>; 2720 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2721 clocks = <&lpass_rxmacro>; 2722 clock-names = "iface"; 2723 label = "RX"; 2724 2725 pinctrl-0 = <&rx_swr_active>; 2726 pinctrl-names = "default"; 2727 2728 qcom,din-ports = <0>; 2729 qcom,dout-ports = <11>; 2730 2731 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>; 2732 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>; 2733 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 2734 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>; 2735 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>; 2736 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>; 2737 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>; 2738 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>; 2739 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; 2740 2741 #address-cells = <2>; 2742 #size-cells = <0>; 2743 #sound-dai-cells = <1>; 2744 status = "disabled"; 2745 }; 2746 2747 lpass_txmacro: codec@6ae0000 { 2748 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 2749 reg = <0 0x06ae0000 0 0x1000>; 2750 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2751 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2752 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2753 <&lpass_vamacro>; 2754 clock-names = "mclk", 2755 "macro", 2756 "dcodec", 2757 "fsgen"; 2758 2759 #clock-cells = <0>; 2760 clock-output-names = "mclk"; 2761 #sound-dai-cells = <1>; 2762 }; 2763 2764 lpass_wsamacro: codec@6b00000 { 2765 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 2766 reg = <0 0x06b00000 0 0x1000>; 2767 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2768 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2769 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2770 <&lpass_vamacro>; 2771 clock-names = "mclk", 2772 "macro", 2773 "dcodec", 2774 "fsgen"; 2775 2776 #clock-cells = <0>; 2777 clock-output-names = "mclk"; 2778 #sound-dai-cells = <1>; 2779 }; 2780 2781 swr0: soundwire@6b10000 { 2782 compatible = "qcom,soundwire-v2.0.0"; 2783 reg = <0 0x06b10000 0 0x10000>; 2784 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2785 clocks = <&lpass_wsamacro>; 2786 clock-names = "iface"; 2787 label = "WSA"; 2788 2789 pinctrl-0 = <&wsa_swr_active>; 2790 pinctrl-names = "default"; 2791 2792 qcom,din-ports = <4>; 2793 qcom,dout-ports = <9>; 2794 2795 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2796 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2797 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2798 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2799 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2800 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2801 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2802 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2803 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2804 2805 #address-cells = <2>; 2806 #size-cells = <0>; 2807 #sound-dai-cells = <1>; 2808 status = "disabled"; 2809 }; 2810 2811 swr2: soundwire@6d30000 { 2812 compatible = "qcom,soundwire-v2.0.0"; 2813 reg = <0 0x06d30000 0 0x10000>; 2814 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2815 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2816 interrupt-names = "core", "wakeup"; 2817 clocks = <&lpass_txmacro>; 2818 clock-names = "iface"; 2819 label = "TX"; 2820 2821 pinctrl-0 = <&tx_swr_active>; 2822 pinctrl-names = "default"; 2823 2824 qcom,din-ports = <4>; 2825 qcom,dout-ports = <0>; 2826 2827 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2828 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2829 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2830 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2831 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2832 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2833 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2834 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2835 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2836 2837 #address-cells = <2>; 2838 #size-cells = <0>; 2839 #sound-dai-cells = <1>; 2840 status = "disabled"; 2841 }; 2842 2843 lpass_vamacro: codec@6d44000 { 2844 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 2845 reg = <0 0x06d44000 0 0x1000>; 2846 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2847 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2848 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2849 clock-names = "mclk", 2850 "macro", 2851 "dcodec"; 2852 2853 #clock-cells = <0>; 2854 clock-output-names = "fsgen"; 2855 #sound-dai-cells = <1>; 2856 }; 2857 2858 lpass_tlmm: pinctrl@6e80000 { 2859 compatible = "qcom,sm8650-lpass-lpi-pinctrl"; 2860 reg = <0 0x06e80000 0 0x20000>; 2861 2862 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2863 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2864 clock-names = "core", "audio"; 2865 2866 gpio-controller; 2867 #gpio-cells = <2>; 2868 gpio-ranges = <&lpass_tlmm 0 0 23>; 2869 2870 tx_swr_active: tx-swr-active-state { 2871 clk-pins { 2872 pins = "gpio0"; 2873 function = "swr_tx_clk"; 2874 drive-strength = <2>; 2875 slew-rate = <1>; 2876 bias-disable; 2877 }; 2878 2879 data-pins { 2880 pins = "gpio1", "gpio2", "gpio14"; 2881 function = "swr_tx_data"; 2882 drive-strength = <2>; 2883 slew-rate = <1>; 2884 bias-bus-hold; 2885 }; 2886 }; 2887 2888 rx_swr_active: rx-swr-active-state { 2889 clk-pins { 2890 pins = "gpio3"; 2891 function = "swr_rx_clk"; 2892 drive-strength = <2>; 2893 slew-rate = <1>; 2894 bias-disable; 2895 }; 2896 2897 data-pins { 2898 pins = "gpio4", "gpio5"; 2899 function = "swr_rx_data"; 2900 drive-strength = <2>; 2901 slew-rate = <1>; 2902 bias-bus-hold; 2903 }; 2904 }; 2905 2906 dmic01_default: dmic01-default-state { 2907 clk-pins { 2908 pins = "gpio6"; 2909 function = "dmic1_clk"; 2910 drive-strength = <8>; 2911 output-high; 2912 }; 2913 2914 data-pins { 2915 pins = "gpio7"; 2916 function = "dmic1_data"; 2917 drive-strength = <8>; 2918 input-enable; 2919 }; 2920 }; 2921 2922 dmic02_default: dmic02-default-state { 2923 clk-pins { 2924 pins = "gpio8"; 2925 function = "dmic2_clk"; 2926 drive-strength = <8>; 2927 output-high; 2928 }; 2929 2930 data-pins { 2931 pins = "gpio9"; 2932 function = "dmic2_data"; 2933 drive-strength = <8>; 2934 input-enable; 2935 }; 2936 }; 2937 2938 wsa_swr_active: wsa-swr-active-state { 2939 clk-pins { 2940 pins = "gpio10"; 2941 function = "wsa_swr_clk"; 2942 drive-strength = <2>; 2943 slew-rate = <1>; 2944 bias-disable; 2945 }; 2946 2947 data-pins { 2948 pins = "gpio11"; 2949 function = "wsa_swr_data"; 2950 drive-strength = <2>; 2951 slew-rate = <1>; 2952 bias-bus-hold; 2953 }; 2954 }; 2955 2956 wsa2_swr_active: wsa2-swr-active-state { 2957 clk-pins { 2958 pins = "gpio15"; 2959 function = "wsa2_swr_clk"; 2960 drive-strength = <2>; 2961 slew-rate = <1>; 2962 bias-disable; 2963 }; 2964 2965 data-pins { 2966 pins = "gpio16"; 2967 function = "wsa2_swr_data"; 2968 drive-strength = <2>; 2969 slew-rate = <1>; 2970 bias-bus-hold; 2971 }; 2972 }; 2973 }; 2974 2975 lpass_lpiaon_noc: interconnect@7400000 { 2976 compatible = "qcom,sm8650-lpass-lpiaon-noc"; 2977 reg = <0 0x07400000 0 0x19080>; 2978 2979 #interconnect-cells = <2>; 2980 2981 qcom,bcm-voters = <&apps_bcm_voter>; 2982 }; 2983 2984 lpass_lpicx_noc: interconnect@7430000 { 2985 compatible = "qcom,sm8650-lpass-lpicx-noc"; 2986 reg = <0 0x07430000 0 0x3a200>; 2987 2988 #interconnect-cells = <2>; 2989 2990 qcom,bcm-voters = <&apps_bcm_voter>; 2991 }; 2992 2993 lpass_ag_noc: interconnect@7e40000 { 2994 compatible = "qcom,sm8650-lpass-ag-noc"; 2995 reg = <0 0x07e40000 0 0xe080>; 2996 2997 #interconnect-cells = <2>; 2998 2999 qcom,bcm-voters = <&apps_bcm_voter>; 3000 }; 3001 3002 sdhc_2: mmc@8804000 { 3003 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; 3004 reg = <0 0x08804000 0 0x1000>; 3005 3006 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3007 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3008 interrupt-names = "hc_irq", 3009 "pwr_irq"; 3010 3011 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3012 <&gcc GCC_SDCC2_APPS_CLK>, 3013 <&rpmhcc RPMH_CXO_CLK>; 3014 clock-names = "iface", 3015 "core", 3016 "xo"; 3017 3018 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3019 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3020 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3021 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; 3022 interconnect-names = "sdhc-ddr", 3023 "cpu-sdhc"; 3024 3025 power-domains = <&rpmhpd RPMHPD_CX>; 3026 operating-points-v2 = <&sdhc2_opp_table>; 3027 3028 iommus = <&apps_smmu 0x540 0>; 3029 3030 bus-width = <4>; 3031 3032 /* Forbid SDR104/SDR50 - broken hw! */ 3033 sdhci-caps-mask = <0x3 0>; 3034 3035 qcom,dll-config = <0x0007642c>; 3036 qcom,ddr-config = <0x80040868>; 3037 3038 dma-coherent; 3039 3040 status = "disabled"; 3041 3042 sdhc2_opp_table: opp-table { 3043 compatible = "operating-points-v2"; 3044 3045 opp-19200000 { 3046 opp-hz = /bits/ 64 <19200000>; 3047 required-opps = <&rpmhpd_opp_min_svs>; 3048 }; 3049 3050 opp-50000000 { 3051 opp-hz = /bits/ 64 <50000000>; 3052 required-opps = <&rpmhpd_opp_low_svs>; 3053 }; 3054 3055 opp-100000000 { 3056 opp-hz = /bits/ 64 <100000000>; 3057 required-opps = <&rpmhpd_opp_svs>; 3058 }; 3059 3060 opp-202000000 { 3061 opp-hz = /bits/ 64 <202000000>; 3062 required-opps = <&rpmhpd_opp_svs_l1>; 3063 }; 3064 }; 3065 }; 3066 3067 mdss: display-subsystem@ae00000 { 3068 compatible = "qcom,sm8650-mdss"; 3069 reg = <0 0x0ae00000 0 0x1000>; 3070 reg-names = "mdss"; 3071 3072 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3073 3074 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3075 <&gcc GCC_DISP_HF_AXI_CLK>, 3076 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3077 3078 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3079 3080 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 3081 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 3082 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 3083 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3084 interconnect-names = "mdp0-mem", 3085 "mdp1-mem"; 3086 3087 power-domains = <&dispcc MDSS_GDSC>; 3088 3089 iommus = <&apps_smmu 0x1c00 0x2>; 3090 3091 interrupt-controller; 3092 #interrupt-cells = <1>; 3093 3094 #address-cells = <2>; 3095 #size-cells = <2>; 3096 ranges; 3097 3098 status = "disabled"; 3099 3100 mdss_mdp: display-controller@ae01000 { 3101 compatible = "qcom,sm8650-dpu"; 3102 reg = <0 0x0ae01000 0 0x8f000>, 3103 <0 0x0aeb0000 0 0x2008>; 3104 reg-names = "mdp", 3105 "vbif"; 3106 3107 interrupts-extended = <&mdss 0>; 3108 3109 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3110 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3111 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3112 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3113 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3114 clock-names = "nrt_bus", 3115 "iface", 3116 "lut", 3117 "core", 3118 "vsync"; 3119 3120 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3121 assigned-clock-rates = <19200000>; 3122 3123 operating-points-v2 = <&mdp_opp_table>; 3124 3125 power-domains = <&rpmhpd RPMHPD_MMCX>; 3126 3127 ports { 3128 #address-cells = <1>; 3129 #size-cells = <0>; 3130 3131 port@0 { 3132 reg = <0>; 3133 3134 dpu_intf1_out: endpoint { 3135 remote-endpoint = <&mdss_dsi0_in>; 3136 }; 3137 }; 3138 3139 port@1 { 3140 reg = <1>; 3141 3142 dpu_intf2_out: endpoint { 3143 remote-endpoint = <&mdss_dsi1_in>; 3144 }; 3145 }; 3146 3147 port@2 { 3148 reg = <2>; 3149 3150 dpu_intf0_out: endpoint { 3151 remote-endpoint = <&mdss_dp0_in>; 3152 }; 3153 }; 3154 }; 3155 3156 mdp_opp_table: opp-table { 3157 compatible = "operating-points-v2"; 3158 3159 opp-200000000 { 3160 opp-hz = /bits/ 64 <200000000>; 3161 required-opps = <&rpmhpd_opp_low_svs>; 3162 }; 3163 3164 opp-325000000 { 3165 opp-hz = /bits/ 64 <325000000>; 3166 required-opps = <&rpmhpd_opp_svs>; 3167 }; 3168 3169 opp-375000000 { 3170 opp-hz = /bits/ 64 <375000000>; 3171 required-opps = <&rpmhpd_opp_svs_l1>; 3172 }; 3173 3174 opp-514000000 { 3175 opp-hz = /bits/ 64 <514000000>; 3176 required-opps = <&rpmhpd_opp_nom>; 3177 }; 3178 }; 3179 }; 3180 3181 mdss_dsi0: dsi@ae94000 { 3182 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3183 reg = <0 0x0ae94000 0 0x400>; 3184 reg-names = "dsi_ctrl"; 3185 3186 interrupts-extended = <&mdss 4>; 3187 3188 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3189 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3190 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3191 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3192 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3193 <&gcc GCC_DISP_HF_AXI_CLK>; 3194 clock-names = "byte", 3195 "byte_intf", 3196 "pixel", 3197 "core", 3198 "iface", 3199 "bus"; 3200 3201 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3202 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3203 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3204 <&mdss_dsi0_phy 1>; 3205 3206 operating-points-v2 = <&mdss_dsi_opp_table>; 3207 3208 power-domains = <&rpmhpd RPMHPD_MMCX>; 3209 3210 phys = <&mdss_dsi0_phy>; 3211 phy-names = "dsi"; 3212 3213 #address-cells = <1>; 3214 #size-cells = <0>; 3215 3216 status = "disabled"; 3217 3218 ports { 3219 #address-cells = <1>; 3220 #size-cells = <0>; 3221 3222 port@0 { 3223 reg = <0>; 3224 3225 mdss_dsi0_in: endpoint { 3226 remote-endpoint = <&dpu_intf1_out>; 3227 }; 3228 }; 3229 3230 port@1 { 3231 reg = <1>; 3232 3233 mdss_dsi0_out: endpoint { 3234 }; 3235 }; 3236 }; 3237 3238 mdss_dsi_opp_table: opp-table { 3239 compatible = "operating-points-v2"; 3240 3241 opp-187500000 { 3242 opp-hz = /bits/ 64 <187500000>; 3243 required-opps = <&rpmhpd_opp_low_svs>; 3244 }; 3245 3246 opp-300000000 { 3247 opp-hz = /bits/ 64 <300000000>; 3248 required-opps = <&rpmhpd_opp_svs>; 3249 }; 3250 3251 opp-358000000 { 3252 opp-hz = /bits/ 64 <358000000>; 3253 required-opps = <&rpmhpd_opp_svs_l1>; 3254 }; 3255 }; 3256 }; 3257 3258 mdss_dsi0_phy: phy@ae95000 { 3259 compatible = "qcom,sm8650-dsi-phy-4nm"; 3260 reg = <0 0x0ae95000 0 0x200>, 3261 <0 0x0ae95200 0 0x280>, 3262 <0 0x0ae95500 0 0x400>; 3263 reg-names = "dsi_phy", 3264 "dsi_phy_lane", 3265 "dsi_pll"; 3266 3267 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3268 <&rpmhcc RPMH_CXO_CLK>; 3269 clock-names = "iface", 3270 "ref"; 3271 3272 #clock-cells = <1>; 3273 #phy-cells = <0>; 3274 3275 status = "disabled"; 3276 }; 3277 3278 mdss_dsi1: dsi@ae96000 { 3279 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3280 reg = <0 0x0ae96000 0 0x400>; 3281 reg-names = "dsi_ctrl"; 3282 3283 interrupts-extended = <&mdss 5>; 3284 3285 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3286 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3287 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3288 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3289 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3290 <&gcc GCC_DISP_HF_AXI_CLK>; 3291 clock-names = "byte", 3292 "byte_intf", 3293 "pixel", 3294 "core", 3295 "iface", 3296 "bus"; 3297 3298 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3299 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3300 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3301 <&mdss_dsi1_phy 1>; 3302 3303 operating-points-v2 = <&mdss_dsi_opp_table>; 3304 3305 power-domains = <&rpmhpd RPMHPD_MMCX>; 3306 3307 phys = <&mdss_dsi1_phy>; 3308 phy-names = "dsi"; 3309 3310 #address-cells = <1>; 3311 #size-cells = <0>; 3312 3313 status = "disabled"; 3314 3315 ports { 3316 #address-cells = <1>; 3317 #size-cells = <0>; 3318 3319 port@0 { 3320 reg = <0>; 3321 3322 mdss_dsi1_in: endpoint { 3323 remote-endpoint = <&dpu_intf2_out>; 3324 }; 3325 }; 3326 3327 port@1 { 3328 reg = <1>; 3329 3330 mdss_dsi1_out: endpoint { 3331 }; 3332 }; 3333 }; 3334 }; 3335 3336 mdss_dsi1_phy: phy@ae97000 { 3337 compatible = "qcom,sm8650-dsi-phy-4nm"; 3338 reg = <0 0x0ae97000 0 0x200>, 3339 <0 0x0ae97200 0 0x280>, 3340 <0 0x0ae97500 0 0x400>; 3341 reg-names = "dsi_phy", 3342 "dsi_phy_lane", 3343 "dsi_pll"; 3344 3345 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3346 <&rpmhcc RPMH_CXO_CLK>; 3347 clock-names = "iface", 3348 "ref"; 3349 3350 #clock-cells = <1>; 3351 #phy-cells = <0>; 3352 3353 status = "disabled"; 3354 }; 3355 3356 mdss_dp0: displayport-controller@af54000 { 3357 compatible = "qcom,sm8650-dp"; 3358 reg = <0 0xaf54000 0 0x104>, 3359 <0 0xaf54200 0 0xc0>, 3360 <0 0xaf55000 0 0x770>, 3361 <0 0xaf56000 0 0x9c>, 3362 <0 0xaf57000 0 0x9c>; 3363 3364 interrupts-extended = <&mdss 12>; 3365 3366 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3367 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3368 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3369 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3370 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3371 clock-names = "core_iface", 3372 "core_aux", 3373 "ctrl_link", 3374 "ctrl_link_iface", 3375 "stream_pixel"; 3376 3377 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3378 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3379 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3380 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3381 3382 operating-points-v2 = <&dp_opp_table>; 3383 3384 power-domains = <&rpmhpd RPMHPD_MMCX>; 3385 3386 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 3387 phy-names = "dp"; 3388 3389 #sound-dai-cells = <0>; 3390 3391 status = "disabled"; 3392 3393 dp_opp_table: opp-table { 3394 compatible = "operating-points-v2"; 3395 3396 opp-162000000 { 3397 opp-hz = /bits/ 64 <162000000>; 3398 required-opps = <&rpmhpd_opp_low_svs_d1>; 3399 }; 3400 3401 opp-270000000 { 3402 opp-hz = /bits/ 64 <270000000>; 3403 required-opps = <&rpmhpd_opp_low_svs>; 3404 }; 3405 3406 opp-540000000 { 3407 opp-hz = /bits/ 64 <540000000>; 3408 required-opps = <&rpmhpd_opp_svs_l1>; 3409 }; 3410 3411 opp-810000000 { 3412 opp-hz = /bits/ 64 <810000000>; 3413 required-opps = <&rpmhpd_opp_nom>; 3414 }; 3415 }; 3416 3417 ports { 3418 #address-cells = <1>; 3419 #size-cells = <0>; 3420 3421 port@0 { 3422 reg = <0>; 3423 3424 mdss_dp0_in: endpoint { 3425 remote-endpoint = <&dpu_intf0_out>; 3426 }; 3427 }; 3428 3429 port@1 { 3430 reg = <1>; 3431 3432 mdss_dp0_out: endpoint { 3433 }; 3434 }; 3435 }; 3436 }; 3437 }; 3438 3439 dispcc: clock-controller@af00000 { 3440 compatible = "qcom,sm8650-dispcc"; 3441 reg = <0 0x0af00000 0 0x20000>; 3442 3443 clocks = <&bi_tcxo_div2>, 3444 <&bi_tcxo_ao_div2>, 3445 <&gcc GCC_DISP_AHB_CLK>, 3446 <&sleep_clk>, 3447 <&mdss_dsi0_phy 0>, 3448 <&mdss_dsi0_phy 1>, 3449 <&mdss_dsi1_phy 0>, 3450 <&mdss_dsi1_phy 1>, 3451 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3452 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3453 <0>, /* dp1 */ 3454 <0>, 3455 <0>, /* dp2 */ 3456 <0>, 3457 <0>, /* dp3 */ 3458 <0>; 3459 3460 power-domains = <&rpmhpd RPMHPD_MMCX>; 3461 required-opps = <&rpmhpd_opp_low_svs>; 3462 3463 #clock-cells = <1>; 3464 #reset-cells = <1>; 3465 #power-domain-cells = <1>; 3466 3467 status = "disabled"; 3468 }; 3469 3470 usb_1_hsphy: phy@88e3000 { 3471 compatible = "qcom,sm8650-snps-eusb2-phy", 3472 "qcom,sm8550-snps-eusb2-phy"; 3473 reg = <0 0x088e3000 0 0x154>; 3474 3475 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 3476 clock-names = "ref"; 3477 3478 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3479 3480 #phy-cells = <0>; 3481 3482 status = "disabled"; 3483 }; 3484 3485 usb_dp_qmpphy: phy@88e8000 { 3486 compatible = "qcom,sm8650-qmp-usb3-dp-phy"; 3487 reg = <0 0x088e8000 0 0x3000>; 3488 3489 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3490 <&rpmhcc RPMH_CXO_CLK>, 3491 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3492 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3493 clock-names = "aux", 3494 "ref", 3495 "com_aux", 3496 "usb3_pipe"; 3497 3498 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3499 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 3500 reset-names = "phy", 3501 "common"; 3502 3503 power-domains = <&gcc USB3_PHY_GDSC>; 3504 3505 #clock-cells = <1>; 3506 #phy-cells = <1>; 3507 3508 status = "disabled"; 3509 3510 ports { 3511 #address-cells = <1>; 3512 #size-cells = <0>; 3513 3514 port@0 { 3515 reg = <0>; 3516 3517 usb_dp_qmpphy_out: endpoint { 3518 }; 3519 }; 3520 3521 port@1 { 3522 reg = <1>; 3523 3524 usb_dp_qmpphy_usb_ss_in: endpoint { 3525 }; 3526 }; 3527 3528 port@2 { 3529 reg = <2>; 3530 3531 usb_dp_qmpphy_dp_in: endpoint { 3532 }; 3533 }; 3534 }; 3535 }; 3536 3537 usb_1: usb@a6f8800 { 3538 compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; 3539 reg = <0 0x0a6f8800 0 0x400>; 3540 3541 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3542 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3543 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 3544 <&pdc 14 IRQ_TYPE_EDGE_RISING>; 3545 interrupt-names = "hs_phy_irq", 3546 "ss_phy_irq", 3547 "dm_hs_phy_irq", 3548 "dp_hs_phy_irq"; 3549 3550 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3551 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3552 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3553 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3554 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3555 <&tcsr TCSR_USB3_CLKREF_EN>; 3556 clock-names = "cfg_noc", 3557 "core", 3558 "iface", 3559 "sleep", 3560 "mock_utmi", 3561 "xo"; 3562 3563 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3564 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3565 assigned-clock-rates = <19200000>, <200000000>; 3566 3567 resets = <&gcc GCC_USB30_PRIM_BCR>; 3568 3569 power-domains = <&gcc USB30_PRIM_GDSC>; 3570 required-opps = <&rpmhpd_opp_nom>; 3571 3572 #address-cells = <2>; 3573 #size-cells = <2>; 3574 ranges; 3575 3576 status = "disabled"; 3577 3578 usb_1_dwc3: usb@a600000 { 3579 compatible = "snps,dwc3"; 3580 reg = <0 0x0a600000 0 0xcd00>; 3581 3582 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3583 3584 iommus = <&apps_smmu 0x40 0>; 3585 3586 phys = <&usb_1_hsphy>, 3587 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 3588 phy-names = "usb2-phy", 3589 "usb3-phy"; 3590 3591 snps,hird-threshold = /bits/ 8 <0x0>; 3592 snps,usb2-gadget-lpm-disable; 3593 snps,dis_u2_susphy_quirk; 3594 snps,dis_enblslpm_quirk; 3595 snps,dis-u1-entry-quirk; 3596 snps,dis-u2-entry-quirk; 3597 snps,is-utmi-l1-suspend; 3598 snps,usb3_lpm_capable; 3599 snps,usb2-lpm-disable; 3600 snps,has-lpm-erratum; 3601 tx-fifo-resize; 3602 3603 dma-coherent; 3604 3605 ports { 3606 #address-cells = <1>; 3607 #size-cells = <0>; 3608 3609 port@0 { 3610 reg = <0>; 3611 3612 usb_1_dwc3_hs: endpoint { 3613 }; 3614 }; 3615 3616 port@1 { 3617 reg = <1>; 3618 3619 usb_1_dwc3_ss: endpoint { 3620 }; 3621 }; 3622 }; 3623 }; 3624 }; 3625 3626 pdc: interrupt-controller@b220000 { 3627 compatible = "qcom,sm8650-pdc", "qcom,pdc"; 3628 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3629 3630 interrupt-parent = <&intc>; 3631 3632 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3633 <125 63 1>, <126 716 12>, 3634 <138 251 5>, <143 244 4>; 3635 3636 #interrupt-cells = <2>; 3637 interrupt-controller; 3638 }; 3639 3640 tsens0: thermal-sensor@c228000 { 3641 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 3642 reg = <0 0x0c228000 0 0x1000>, /* TM */ 3643 <0 0x0c222000 0 0x1000>; /* SROT */ 3644 3645 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 3647 interrupt-names = "uplow", 3648 "critical"; 3649 3650 #qcom,sensors = <15>; 3651 3652 #thermal-sensor-cells = <1>; 3653 }; 3654 3655 tsens1: thermal-sensor@c229000 { 3656 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 3657 reg = <0 0x0c229000 0 0x1000>, /* TM */ 3658 <0 0x0c223000 0 0x1000>; /* SROT */ 3659 3660 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3661 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 3662 interrupt-names = "uplow", 3663 "critical"; 3664 3665 #qcom,sensors = <16>; 3666 3667 #thermal-sensor-cells = <1>; 3668 }; 3669 3670 tsens2: thermal-sensor@c22a000 { 3671 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 3672 reg = <0 0x0c22a000 0 0x1000>, /* TM */ 3673 <0 0x0c224000 0 0x1000>; /* SROT */ 3674 3675 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 3676 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 3677 interrupt-names = "uplow", 3678 "critical"; 3679 3680 #qcom,sensors = <13>; 3681 3682 #thermal-sensor-cells = <1>; 3683 }; 3684 3685 aoss_qmp: power-management@c300000 { 3686 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; 3687 reg = <0 0x0c300000 0 0x400>; 3688 3689 interrupt-parent = <&ipcc>; 3690 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3691 IRQ_TYPE_EDGE_RISING>; 3692 3693 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3694 3695 #clock-cells = <0>; 3696 }; 3697 3698 sram@c3f0000 { 3699 compatible = "qcom,rpmh-stats"; 3700 reg = <0 0x0c3f0000 0 0x400>; 3701 }; 3702 3703 spmi_bus: spmi@c400000 { 3704 compatible = "qcom,spmi-pmic-arb"; 3705 reg = <0 0x0c400000 0 0x3000>, 3706 <0 0x0c500000 0 0x4000000>, 3707 <0 0x0c440000 0 0x80000>, 3708 <0 0x0c4c0000 0 0x20000>, 3709 <0 0x0c42d000 0 0x4000>; 3710 reg-names = "core", 3711 "chnls", 3712 "obsrvr", 3713 "intr", 3714 "cnfg"; 3715 3716 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3717 interrupt-names = "periph_irq"; 3718 3719 qcom,ee = <0>; 3720 qcom,channel = <0>; 3721 qcom,bus-id = <0>; 3722 3723 interrupt-controller; 3724 #interrupt-cells = <4>; 3725 3726 #address-cells = <2>; 3727 #size-cells = <0>; 3728 }; 3729 3730 tlmm: pinctrl@f100000 { 3731 compatible = "qcom,sm8650-tlmm"; 3732 reg = <0 0x0f100000 0 0x300000>; 3733 3734 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3735 3736 gpio-controller; 3737 #gpio-cells = <2>; 3738 3739 interrupt-controller; 3740 #interrupt-cells = <2>; 3741 3742 gpio-ranges = <&tlmm 0 0 211>; 3743 3744 wakeup-parent = <&pdc>; 3745 3746 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3747 /* SDA, SCL */ 3748 pins = "gpio64", "gpio65"; 3749 function = "i2chub0_se0"; 3750 drive-strength = <2>; 3751 bias-pull-up; 3752 }; 3753 3754 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 3755 /* SDA, SCL */ 3756 pins = "gpio66", "gpio67"; 3757 function = "i2chub0_se1"; 3758 drive-strength = <2>; 3759 bias-pull-up; 3760 }; 3761 3762 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 3763 /* SDA, SCL */ 3764 pins = "gpio68", "gpio69"; 3765 function = "i2chub0_se2"; 3766 drive-strength = <2>; 3767 bias-pull-up; 3768 }; 3769 3770 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 3771 /* SDA, SCL */ 3772 pins = "gpio70", "gpio71"; 3773 function = "i2chub0_se3"; 3774 drive-strength = <2>; 3775 bias-pull-up; 3776 }; 3777 3778 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 3779 /* SDA, SCL */ 3780 pins = "gpio72", "gpio73"; 3781 function = "i2chub0_se4"; 3782 drive-strength = <2>; 3783 bias-pull-up; 3784 }; 3785 3786 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 3787 /* SDA, SCL */ 3788 pins = "gpio74", "gpio75"; 3789 function = "i2chub0_se5"; 3790 drive-strength = <2>; 3791 bias-pull-up; 3792 }; 3793 3794 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 3795 /* SDA, SCL */ 3796 pins = "gpio76", "gpio77"; 3797 function = "i2chub0_se6"; 3798 drive-strength = <2>; 3799 bias-pull-up; 3800 }; 3801 3802 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 3803 /* SDA, SCL */ 3804 pins = "gpio78", "gpio79"; 3805 function = "i2chub0_se7"; 3806 drive-strength = <2>; 3807 bias-pull-up; 3808 }; 3809 3810 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 3811 /* SDA, SCL */ 3812 pins = "gpio206", "gpio207"; 3813 function = "i2chub0_se8"; 3814 drive-strength = <2>; 3815 bias-pull-up; 3816 }; 3817 3818 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 3819 /* SDA, SCL */ 3820 pins = "gpio80", "gpio81"; 3821 function = "i2chub0_se9"; 3822 drive-strength = <2>; 3823 bias-pull-up; 3824 }; 3825 3826 pcie0_default_state: pcie0-default-state { 3827 perst-pins { 3828 pins = "gpio94"; 3829 function = "gpio"; 3830 drive-strength = <2>; 3831 bias-pull-down; 3832 }; 3833 3834 clkreq-pins { 3835 pins = "gpio95"; 3836 function = "pcie0_clk_req_n"; 3837 drive-strength = <2>; 3838 bias-pull-up; 3839 }; 3840 3841 wake-pins { 3842 pins = "gpio96"; 3843 function = "gpio"; 3844 drive-strength = <2>; 3845 bias-pull-up; 3846 }; 3847 }; 3848 3849 pcie1_default_state: pcie1-default-state { 3850 perst-pins { 3851 pins = "gpio97"; 3852 function = "gpio"; 3853 drive-strength = <2>; 3854 bias-pull-down; 3855 }; 3856 3857 clkreq-pins { 3858 pins = "gpio98"; 3859 function = "pcie1_clk_req_n"; 3860 drive-strength = <2>; 3861 bias-pull-up; 3862 }; 3863 3864 wake-pins { 3865 pins = "gpio99"; 3866 function = "gpio"; 3867 drive-strength = <2>; 3868 bias-pull-up; 3869 }; 3870 }; 3871 3872 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3873 /* SDA, SCL */ 3874 pins = "gpio32", "gpio33"; 3875 function = "qup1_se0"; 3876 drive-strength = <2>; 3877 bias-pull-up; 3878 }; 3879 3880 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3881 /* SDA, SCL */ 3882 pins = "gpio36", "gpio37"; 3883 function = "qup1_se1"; 3884 drive-strength = <2>; 3885 bias-pull-up; 3886 }; 3887 3888 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3889 /* SDA, SCL */ 3890 pins = "gpio40", "gpio41"; 3891 function = "qup1_se2"; 3892 drive-strength = <2>; 3893 bias-pull-up; 3894 }; 3895 3896 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3897 /* SDA, SCL */ 3898 pins = "gpio44", "gpio45"; 3899 function = "qup1_se3"; 3900 drive-strength = <2>; 3901 bias-pull-up; 3902 }; 3903 3904 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3905 /* SDA, SCL */ 3906 pins = "gpio48", "gpio49"; 3907 function = "qup1_se4"; 3908 drive-strength = <2>; 3909 bias-pull-up; 3910 }; 3911 3912 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3913 /* SDA, SCL */ 3914 pins = "gpio52", "gpio53"; 3915 function = "qup1_se5"; 3916 drive-strength = <2>; 3917 bias-pull-up; 3918 }; 3919 3920 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3921 /* SDA, SCL */ 3922 pins = "gpio56", "gpio57"; 3923 function = "qup1_se6"; 3924 drive-strength = <2>; 3925 bias-pull-up; 3926 }; 3927 3928 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 3929 /* SDA, SCL */ 3930 pins = "gpio60", "gpio61"; 3931 function = "qup1_se7"; 3932 drive-strength = <2>; 3933 bias-pull-up; 3934 }; 3935 3936 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3937 /* SDA, SCL */ 3938 pins = "gpio0", "gpio1"; 3939 function = "qup2_se0"; 3940 drive-strength = <2>; 3941 bias-pull-up; 3942 }; 3943 3944 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3945 /* SDA, SCL */ 3946 pins = "gpio4", "gpio5"; 3947 function = "qup2_se1"; 3948 drive-strength = <2>; 3949 bias-pull-up; 3950 }; 3951 3952 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3953 /* SDA, SCL */ 3954 pins = "gpio8", "gpio9"; 3955 function = "qup2_se2"; 3956 drive-strength = <2>; 3957 bias-pull-up; 3958 }; 3959 3960 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3961 /* SDA, SCL */ 3962 pins = "gpio12", "gpio13"; 3963 function = "qup2_se3"; 3964 drive-strength = <2>; 3965 bias-pull-up; 3966 }; 3967 3968 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3969 /* SDA, SCL */ 3970 pins = "gpio16", "gpio17"; 3971 function = "qup2_se4"; 3972 drive-strength = <2>; 3973 bias-pull-up; 3974 }; 3975 3976 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3977 /* SDA, SCL */ 3978 pins = "gpio20", "gpio21"; 3979 function = "qup2_se5"; 3980 drive-strength = <2>; 3981 bias-pull-up; 3982 }; 3983 3984 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3985 /* SDA, SCL */ 3986 pins = "gpio24", "gpio25"; 3987 function = "qup2_se6"; 3988 drive-strength = <2>; 3989 bias-pull-up; 3990 }; 3991 3992 qup_spi0_cs: qup-spi0-cs-state { 3993 pins = "gpio35"; 3994 function = "qup1_se0"; 3995 drive-strength = <6>; 3996 bias-disable; 3997 }; 3998 3999 qup_spi0_data_clk: qup-spi0-data-clk-state { 4000 /* MISO, MOSI, CLK */ 4001 pins = "gpio32", "gpio33", "gpio34"; 4002 function = "qup1_se0"; 4003 drive-strength = <6>; 4004 bias-disable; 4005 }; 4006 4007 qup_spi1_cs: qup-spi1-cs-state { 4008 pins = "gpio39"; 4009 function = "qup1_se1"; 4010 drive-strength = <6>; 4011 bias-disable; 4012 }; 4013 4014 qup_spi1_data_clk: qup-spi1-data-clk-state { 4015 /* MISO, MOSI, CLK */ 4016 pins = "gpio36", "gpio37", "gpio38"; 4017 function = "qup1_se1"; 4018 drive-strength = <6>; 4019 bias-disable; 4020 }; 4021 4022 qup_spi2_cs: qup-spi2-cs-state { 4023 pins = "gpio43"; 4024 function = "qup1_se2"; 4025 drive-strength = <6>; 4026 bias-disable; 4027 }; 4028 4029 qup_spi2_data_clk: qup-spi2-data-clk-state { 4030 /* MISO, MOSI, CLK */ 4031 pins = "gpio40", "gpio41", "gpio42"; 4032 function = "qup1_se2"; 4033 drive-strength = <6>; 4034 bias-disable; 4035 }; 4036 4037 qup_spi3_cs: qup-spi3-cs-state { 4038 pins = "gpio47"; 4039 function = "qup1_se3"; 4040 drive-strength = <6>; 4041 bias-disable; 4042 }; 4043 4044 qup_spi3_data_clk: qup-spi3-data-clk-state { 4045 /* MISO, MOSI, CLK */ 4046 pins = "gpio44", "gpio45", "gpio46"; 4047 function = "qup1_se3"; 4048 drive-strength = <6>; 4049 bias-disable; 4050 }; 4051 4052 qup_spi4_cs: qup-spi4-cs-state { 4053 pins = "gpio51"; 4054 function = "qup1_se4"; 4055 drive-strength = <6>; 4056 bias-disable; 4057 }; 4058 4059 qup_spi4_data_clk: qup-spi4-data-clk-state { 4060 /* MISO, MOSI, CLK */ 4061 pins = "gpio48", "gpio49", "gpio50"; 4062 function = "qup1_se4"; 4063 drive-strength = <6>; 4064 bias-disable; 4065 }; 4066 4067 qup_spi5_cs: qup-spi5-cs-state { 4068 pins = "gpio55"; 4069 function = "qup1_se5"; 4070 drive-strength = <6>; 4071 bias-disable; 4072 }; 4073 4074 qup_spi5_data_clk: qup-spi5-data-clk-state { 4075 /* MISO, MOSI, CLK */ 4076 pins = "gpio52", "gpio53", "gpio54"; 4077 function = "qup1_se5"; 4078 drive-strength = <6>; 4079 bias-disable; 4080 }; 4081 4082 qup_spi6_cs: qup-spi6-cs-state { 4083 pins = "gpio59"; 4084 function = "qup1_se6"; 4085 drive-strength = <6>; 4086 bias-disable; 4087 }; 4088 4089 qup_spi6_data_clk: qup-spi6-data-clk-state { 4090 /* MISO, MOSI, CLK */ 4091 pins = "gpio56", "gpio57", "gpio58"; 4092 function = "qup1_se6"; 4093 drive-strength = <6>; 4094 bias-disable; 4095 }; 4096 4097 qup_spi7_cs: qup-spi7-cs-state { 4098 pins = "gpio63"; 4099 function = "qup1_se7"; 4100 drive-strength = <6>; 4101 bias-disable; 4102 }; 4103 4104 qup_spi7_data_clk: qup-spi7-data-clk-state { 4105 /* MISO, MOSI, CLK */ 4106 pins = "gpio60", "gpio61", "gpio62"; 4107 function = "qup1_se7"; 4108 drive-strength = <6>; 4109 bias-disable; 4110 }; 4111 4112 qup_spi8_cs: qup-spi8-cs-state { 4113 pins = "gpio3"; 4114 function = "qup2_se0"; 4115 drive-strength = <6>; 4116 bias-disable; 4117 }; 4118 4119 qup_spi8_data_clk: qup-spi8-data-clk-state { 4120 /* MISO, MOSI, CLK */ 4121 pins = "gpio0", "gpio1", "gpio2"; 4122 function = "qup2_se0"; 4123 drive-strength = <6>; 4124 bias-disable; 4125 }; 4126 4127 qup_spi9_cs: qup-spi9-cs-state { 4128 pins = "gpio7"; 4129 function = "qup2_se1"; 4130 drive-strength = <6>; 4131 bias-disable; 4132 }; 4133 4134 qup_spi9_data_clk: qup-spi9-data-clk-state { 4135 /* MISO, MOSI, CLK */ 4136 pins = "gpio4", "gpio5", "gpio6"; 4137 function = "qup2_se1"; 4138 drive-strength = <6>; 4139 bias-disable; 4140 }; 4141 4142 qup_spi10_cs: qup-spi10-cs-state { 4143 pins = "gpio11"; 4144 function = "qup2_se2"; 4145 drive-strength = <6>; 4146 bias-disable; 4147 }; 4148 4149 qup_spi10_data_clk: qup-spi10-data-clk-state { 4150 /* MISO, MOSI, CLK */ 4151 pins = "gpio8", "gpio9", "gpio10"; 4152 function = "qup2_se2"; 4153 drive-strength = <6>; 4154 bias-disable; 4155 }; 4156 4157 qup_spi11_cs: qup-spi11-cs-state { 4158 pins = "gpio15"; 4159 function = "qup2_se3"; 4160 drive-strength = <6>; 4161 bias-disable; 4162 }; 4163 4164 qup_spi11_data_clk: qup-spi11-data-clk-state { 4165 /* MISO, MOSI, CLK */ 4166 pins = "gpio12", "gpio13", "gpio14"; 4167 function = "qup2_se3"; 4168 drive-strength = <6>; 4169 bias-disable; 4170 }; 4171 4172 qup_spi12_cs: qup-spi12-cs-state { 4173 pins = "gpio19"; 4174 function = "qup2_se4"; 4175 drive-strength = <6>; 4176 bias-disable; 4177 }; 4178 4179 qup_spi12_data_clk: qup-spi12-data-clk-state { 4180 /* MISO, MOSI, CLK */ 4181 pins = "gpio16", "gpio17", "gpio18"; 4182 function = "qup2_se4"; 4183 drive-strength = <6>; 4184 bias-disable; 4185 }; 4186 4187 qup_spi13_cs: qup-spi13-cs-state { 4188 pins = "gpio23"; 4189 function = "qup2_se5"; 4190 drive-strength = <6>; 4191 bias-disable; 4192 }; 4193 4194 qup_spi13_data_clk: qup-spi13-data-clk-state { 4195 /* MISO, MOSI, CLK */ 4196 pins = "gpio20", "gpio21", "gpio22"; 4197 function = "qup2_se5"; 4198 drive-strength = <6>; 4199 bias-disable; 4200 }; 4201 4202 qup_spi14_cs: qup-spi14-cs-state { 4203 pins = "gpio27"; 4204 function = "qup2_se6"; 4205 drive-strength = <6>; 4206 bias-disable; 4207 }; 4208 4209 qup_spi14_data_clk: qup-spi14-data-clk-state { 4210 /* MISO, MOSI, CLK */ 4211 pins = "gpio24", "gpio25", "gpio26"; 4212 function = "qup2_se6"; 4213 drive-strength = <6>; 4214 bias-disable; 4215 }; 4216 4217 qup_uart14_default: qup-uart14-default-state { 4218 /* TX, RX */ 4219 pins = "gpio26", "gpio27"; 4220 function = "qup2_se6"; 4221 drive-strength = <2>; 4222 bias-pull-up; 4223 }; 4224 4225 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 4226 /* CTS, RTS */ 4227 pins = "gpio24", "gpio25"; 4228 function = "qup2_se6"; 4229 drive-strength = <2>; 4230 bias-pull-down; 4231 }; 4232 4233 qup_uart15_default: qup-uart15-default-state { 4234 /* TX, RX */ 4235 pins = "gpio30", "gpio31"; 4236 function = "qup2_se7"; 4237 drive-strength = <2>; 4238 bias-disable; 4239 }; 4240 4241 sdc2_sleep: sdc2-sleep-state { 4242 clk-pins { 4243 pins = "sdc2_clk"; 4244 drive-strength = <2>; 4245 bias-disable; 4246 }; 4247 4248 cmd-pins { 4249 pins = "sdc2_cmd"; 4250 drive-strength = <2>; 4251 bias-pull-up; 4252 }; 4253 4254 data-pins { 4255 pins = "sdc2_data"; 4256 drive-strength = <2>; 4257 bias-pull-up; 4258 }; 4259 }; 4260 4261 sdc2_default: sdc2-default-state { 4262 clk-pins { 4263 pins = "sdc2_clk"; 4264 drive-strength = <16>; 4265 bias-disable; 4266 }; 4267 4268 cmd-pins { 4269 pins = "sdc2_cmd"; 4270 drive-strength = <10>; 4271 bias-pull-up; 4272 }; 4273 4274 data-pins { 4275 pins = "sdc2_data"; 4276 drive-strength = <10>; 4277 bias-pull-up; 4278 }; 4279 }; 4280 }; 4281 4282 apps_smmu: iommu@15000000 { 4283 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4284 reg = <0 0x15000000 0 0x100000>; 4285 4286 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4287 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4288 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4289 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4290 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4291 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4292 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4293 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4294 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4295 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4296 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4297 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4298 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4299 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4300 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4301 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4302 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4303 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4304 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4305 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4306 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4307 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4308 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4309 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4310 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4311 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4312 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4313 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4314 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4315 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4316 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4317 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4318 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4319 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4320 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4321 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4322 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4323 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4324 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4325 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4326 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4327 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4328 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4329 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4330 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4331 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4332 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4333 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4334 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4335 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4336 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4337 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4338 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4339 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4340 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4341 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4342 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4343 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4344 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4345 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4346 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4347 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4348 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4349 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4350 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4351 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4352 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4353 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4354 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4355 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4356 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4357 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4358 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4359 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4360 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4361 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4362 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4363 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4364 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4365 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4366 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4367 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4368 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4369 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4370 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4371 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4372 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4373 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4374 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4375 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4376 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4377 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4378 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4379 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4380 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4381 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4382 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 4383 4384 #iommu-cells = <2>; 4385 #global-interrupts = <1>; 4386 4387 dma-coherent; 4388 }; 4389 4390 intc: interrupt-controller@17100000 { 4391 compatible = "arm,gic-v3"; 4392 reg = <0 0x17100000 0 0x10000>, /* GICD */ 4393 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 4394 4395 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4396 4397 #interrupt-cells = <3>; 4398 interrupt-controller; 4399 4400 #redistributor-regions = <1>; 4401 redistributor-stride = <0 0x40000>; 4402 4403 #address-cells = <2>; 4404 #size-cells = <2>; 4405 ranges; 4406 4407 gic_its: msi-controller@17140000 { 4408 compatible = "arm,gic-v3-its"; 4409 reg = <0 0x17140000 0 0x20000>; 4410 4411 msi-controller; 4412 #msi-cells = <1>; 4413 }; 4414 }; 4415 4416 timer@17420000 { 4417 compatible = "arm,armv7-timer-mem"; 4418 reg = <0 0x17420000 0 0x1000>; 4419 4420 ranges = <0 0 0 0x20000000>; 4421 #address-cells = <1>; 4422 #size-cells = <1>; 4423 4424 frame@17421000 { 4425 reg = <0x17421000 0x1000>, 4426 <0x17422000 0x1000>; 4427 4428 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4429 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4430 4431 frame-number = <0>; 4432 }; 4433 4434 frame@17423000 { 4435 reg = <0x17423000 0x1000>; 4436 4437 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4438 4439 frame-number = <1>; 4440 4441 status = "disabled"; 4442 }; 4443 4444 frame@17425000 { 4445 reg = <0x17425000 0x1000>; 4446 4447 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4448 4449 frame-number = <2>; 4450 4451 status = "disabled"; 4452 }; 4453 4454 frame@17427000 { 4455 reg = <0x17427000 0x1000>; 4456 4457 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4458 4459 frame-number = <3>; 4460 4461 status = "disabled"; 4462 }; 4463 4464 frame@17429000 { 4465 reg = <0x17429000 0x1000>; 4466 4467 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4468 4469 frame-number = <4>; 4470 4471 status = "disabled"; 4472 }; 4473 4474 frame@1742b000 { 4475 reg = <0x1742b000 0x1000>; 4476 4477 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4478 4479 frame-number = <5>; 4480 4481 status = "disabled"; 4482 }; 4483 4484 frame@1742d000 { 4485 reg = <0x1742d000 0x1000>; 4486 4487 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4488 4489 frame-number = <6>; 4490 4491 status = "disabled"; 4492 }; 4493 }; 4494 4495 apps_rsc: rsc@17a00000 { 4496 compatible = "qcom,rpmh-rsc"; 4497 reg = <0 0x17a00000 0 0x10000>, 4498 <0 0x17a10000 0 0x10000>, 4499 <0 0x17a20000 0 0x10000>, 4500 <0 0x17a30000 0 0x10000>; 4501 reg-names = "drv-0", 4502 "drv-1", 4503 "drv-2"; 4504 4505 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4506 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4507 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4508 4509 power-domains = <&CLUSTER_PD>; 4510 4511 qcom,tcs-offset = <0xd00>; 4512 qcom,drv-id = <2>; 4513 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4514 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4515 4516 label = "apps_rsc"; 4517 4518 apps_bcm_voter: bcm-voter { 4519 compatible = "qcom,bcm-voter"; 4520 }; 4521 4522 rpmhcc: clock-controller { 4523 compatible = "qcom,sm8650-rpmh-clk"; 4524 4525 clocks = <&xo_board>; 4526 clock-names = "xo"; 4527 4528 #clock-cells = <1>; 4529 }; 4530 4531 rpmhpd: power-controller { 4532 compatible = "qcom,sm8650-rpmhpd"; 4533 4534 operating-points-v2 = <&rpmhpd_opp_table>; 4535 4536 #power-domain-cells = <1>; 4537 4538 rpmhpd_opp_table: opp-table { 4539 compatible = "operating-points-v2"; 4540 4541 rpmhpd_opp_ret: opp-16 { 4542 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4543 }; 4544 4545 rpmhpd_opp_min_svs: opp-48 { 4546 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4547 }; 4548 4549 rpmhpd_opp_low_svs_d2: opp-52 { 4550 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 4551 }; 4552 4553 rpmhpd_opp_low_svs_d1: opp-56 { 4554 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4555 }; 4556 4557 rpmhpd_opp_low_svs_d0: opp-60 { 4558 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 4559 }; 4560 4561 rpmhpd_opp_low_svs: opp-64 { 4562 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4563 }; 4564 4565 rpmhpd_opp_low_svs_l1: opp-80 { 4566 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4567 }; 4568 4569 rpmhpd_opp_svs: opp-128 { 4570 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4571 }; 4572 4573 rpmhpd_opp_svs_l0: opp-144 { 4574 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4575 }; 4576 4577 rpmhpd_opp_svs_l1: opp-192 { 4578 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4579 }; 4580 4581 rpmhpd_opp_nom: opp-256 { 4582 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4583 }; 4584 4585 rpmhpd_opp_nom_l1: opp-320 { 4586 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4587 }; 4588 4589 rpmhpd_opp_nom_l2: opp-336 { 4590 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4591 }; 4592 4593 rpmhpd_opp_turbo: opp-384 { 4594 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4595 }; 4596 4597 rpmhpd_opp_turbo_l1: opp-416 { 4598 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4599 }; 4600 }; 4601 }; 4602 }; 4603 4604 cpufreq_hw: cpufreq@17d91000 { 4605 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss"; 4606 reg = <0 0x17d91000 0 0x1000>, 4607 <0 0x17d92000 0 0x1000>, 4608 <0 0x17d93000 0 0x1000>, 4609 <0 0x17d94000 0 0x1000>; 4610 reg-names = "freq-domain0", 4611 "freq-domain1", 4612 "freq-domain2", 4613 "freq-domain3"; 4614 4615 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4616 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4617 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 4618 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 4619 interrupt-names = "dcvsh-irq-0", 4620 "dcvsh-irq-1", 4621 "dcvsh-irq-2", 4622 "dcvsh-irq-3"; 4623 4624 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 4625 clock-names = "xo", "alternate"; 4626 4627 #freq-domain-cells = <1>; 4628 #clock-cells = <1>; 4629 }; 4630 4631 pmu@24091000 { 4632 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4633 reg = <0 0x24091000 0 0x1000>; 4634 4635 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4636 4637 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 4638 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4639 4640 operating-points-v2 = <&llcc_bwmon_opp_table>; 4641 4642 llcc_bwmon_opp_table: opp-table { 4643 compatible = "operating-points-v2"; 4644 4645 opp-0 { 4646 opp-peak-kBps = <2086000>; 4647 }; 4648 4649 opp-1 { 4650 opp-peak-kBps = <2929000>; 4651 }; 4652 4653 opp-2 { 4654 opp-peak-kBps = <5931000>; 4655 }; 4656 4657 opp-3 { 4658 opp-peak-kBps = <6515000>; 4659 }; 4660 4661 opp-4 { 4662 opp-peak-kBps = <7980000>; 4663 }; 4664 4665 opp-5 { 4666 opp-peak-kBps = <10437000>; 4667 }; 4668 4669 opp-6 { 4670 opp-peak-kBps = <12157000>; 4671 }; 4672 4673 opp-7 { 4674 opp-peak-kBps = <14060000>; 4675 }; 4676 4677 opp-8 { 4678 opp-peak-kBps = <16113000>; 4679 }; 4680 }; 4681 }; 4682 4683 pmu@240b7400 { 4684 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; 4685 reg = <0 0x240b7400 0 0x600>; 4686 4687 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4688 4689 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4690 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4691 4692 operating-points-v2 = <&cpu_bwmon_opp_table>; 4693 4694 cpu_bwmon_opp_table: opp-table { 4695 compatible = "operating-points-v2"; 4696 4697 opp-0 { 4698 opp-peak-kBps = <4577000>; 4699 }; 4700 4701 opp-1 { 4702 opp-peak-kBps = <7110000>; 4703 }; 4704 4705 opp-2 { 4706 opp-peak-kBps = <9155000>; 4707 }; 4708 4709 opp-3 { 4710 opp-peak-kBps = <12298000>; 4711 }; 4712 4713 opp-4 { 4714 opp-peak-kBps = <14236000>; 4715 }; 4716 4717 opp-5 { 4718 opp-peak-kBps = <16265000>; 4719 }; 4720 }; 4721 }; 4722 4723 gem_noc: interconnect@24100000 { 4724 compatible = "qcom,sm8650-gem-noc"; 4725 reg = <0 0x24100000 0 0xc5080>; 4726 4727 qcom,bcm-voters = <&apps_bcm_voter>; 4728 4729 #interconnect-cells = <2>; 4730 }; 4731 4732 system-cache-controller@25000000 { 4733 compatible = "qcom,sm8650-llcc"; 4734 reg = <0 0x25000000 0 0x200000>, 4735 <0 0x25400000 0 0x200000>, 4736 <0 0x25200000 0 0x200000>, 4737 <0 0x25600000 0 0x200000>, 4738 <0 0x25800000 0 0x200000>; 4739 reg-names = "llcc0_base", 4740 "llcc1_base", 4741 "llcc2_base", 4742 "llcc3_base", 4743 "llcc_broadcast_base"; 4744 4745 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4746 }; 4747 4748 remoteproc_adsp: remoteproc@30000000 { 4749 compatible = "qcom,sm8650-adsp-pas"; 4750 reg = <0 0x30000000 0 0x100>; 4751 4752 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4753 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4754 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4755 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4756 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4757 interrupt-names = "wdog", 4758 "fatal", 4759 "ready", 4760 "handover", 4761 "stop-ack"; 4762 4763 clocks = <&rpmhcc RPMH_CXO_CLK>; 4764 clock-names = "xo"; 4765 4766 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 4767 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4768 4769 power-domains = <&rpmhpd RPMHPD_LCX>, 4770 <&rpmhpd RPMHPD_LMX>; 4771 power-domain-names = "lcx", 4772 "lmx"; 4773 4774 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 4775 4776 qcom,qmp = <&aoss_qmp>; 4777 4778 qcom,smem-states = <&smp2p_adsp_out 0>; 4779 qcom,smem-state-names = "stop"; 4780 4781 status = "disabled"; 4782 4783 remoteproc_adsp_glink: glink-edge { 4784 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4785 IPCC_MPROC_SIGNAL_GLINK_QMP 4786 IRQ_TYPE_EDGE_RISING>; 4787 4788 mboxes = <&ipcc IPCC_CLIENT_LPASS 4789 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4790 4791 qcom,remote-pid = <2>; 4792 4793 label = "lpass"; 4794 4795 fastrpc { 4796 compatible = "qcom,fastrpc"; 4797 4798 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4799 4800 label = "adsp"; 4801 4802 #address-cells = <1>; 4803 #size-cells = <0>; 4804 4805 compute-cb@3 { 4806 compatible = "qcom,fastrpc-compute-cb"; 4807 reg = <3>; 4808 4809 iommus = <&apps_smmu 0x1003 0x80>, 4810 <&apps_smmu 0x1043 0x20>; 4811 }; 4812 4813 compute-cb@4 { 4814 compatible = "qcom,fastrpc-compute-cb"; 4815 reg = <4>; 4816 4817 iommus = <&apps_smmu 0x1004 0x80>, 4818 <&apps_smmu 0x1044 0x20>; 4819 }; 4820 4821 compute-cb@5 { 4822 compatible = "qcom,fastrpc-compute-cb"; 4823 reg = <5>; 4824 4825 iommus = <&apps_smmu 0x1005 0x80>, 4826 <&apps_smmu 0x1045 0x20>; 4827 }; 4828 4829 compute-cb@6 { 4830 compatible = "qcom,fastrpc-compute-cb"; 4831 reg = <6>; 4832 4833 iommus = <&apps_smmu 0x1006 0x80>, 4834 <&apps_smmu 0x1046 0x20>; 4835 }; 4836 4837 compute-cb@7 { 4838 compatible = "qcom,fastrpc-compute-cb"; 4839 reg = <7>; 4840 4841 iommus = <&apps_smmu 0x1007 0x40>, 4842 <&apps_smmu 0x1067 0x0>, 4843 <&apps_smmu 0x1087 0x0>; 4844 }; 4845 }; 4846 4847 gpr { 4848 compatible = "qcom,gpr"; 4849 qcom,glink-channels = "adsp_apps"; 4850 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4851 qcom,intents = <512 20>; 4852 #address-cells = <1>; 4853 #size-cells = <0>; 4854 4855 q6apm: service@1 { 4856 compatible = "qcom,q6apm"; 4857 reg = <GPR_APM_MODULE_IID>; 4858 #sound-dai-cells = <0>; 4859 qcom,protection-domain = "avs/audio", 4860 "msm/adsp/audio_pd"; 4861 4862 q6apmbedai: bedais { 4863 compatible = "qcom,q6apm-lpass-dais"; 4864 #sound-dai-cells = <1>; 4865 }; 4866 4867 q6apmdai: dais { 4868 compatible = "qcom,q6apm-dais"; 4869 iommus = <&apps_smmu 0x1001 0x80>, 4870 <&apps_smmu 0x1061 0x0>; 4871 }; 4872 }; 4873 4874 q6prm: service@2 { 4875 compatible = "qcom,q6prm"; 4876 reg = <GPR_PRM_MODULE_IID>; 4877 qcom,protection-domain = "avs/audio", 4878 "msm/adsp/audio_pd"; 4879 4880 q6prmcc: clock-controller { 4881 compatible = "qcom,q6prm-lpass-clocks"; 4882 #clock-cells = <2>; 4883 }; 4884 }; 4885 }; 4886 }; 4887 }; 4888 4889 nsp_noc: interconnect@320c0000 { 4890 compatible = "qcom,sm8650-nsp-noc"; 4891 reg = <0 0x320c0000 0 0xf080>; 4892 4893 qcom,bcm-voters = <&apps_bcm_voter>; 4894 4895 #interconnect-cells = <2>; 4896 }; 4897 4898 remoteproc_cdsp: remoteproc@32300000 { 4899 compatible = "qcom,sm8650-cdsp-pas"; 4900 reg = <0 0x32300000 0 0x1400000>; 4901 4902 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4903 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 4904 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 4905 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 4906 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 4907 interrupt-names = "wdog", 4908 "fatal", 4909 "ready", 4910 "handover", 4911 "stop-ack"; 4912 4913 clocks = <&rpmhcc RPMH_CXO_CLK>; 4914 clock-names = "xo"; 4915 4916 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 4917 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4918 4919 power-domains = <&rpmhpd RPMHPD_CX>, 4920 <&rpmhpd RPMHPD_MXC>, 4921 <&rpmhpd RPMHPD_NSP>; 4922 power-domain-names = "cx", 4923 "mxc", 4924 "nsp"; 4925 4926 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; 4927 4928 qcom,qmp = <&aoss_qmp>; 4929 4930 qcom,smem-states = <&smp2p_cdsp_out 0>; 4931 qcom,smem-state-names = "stop"; 4932 4933 status = "disabled"; 4934 4935 glink-edge { 4936 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4937 IPCC_MPROC_SIGNAL_GLINK_QMP 4938 IRQ_TYPE_EDGE_RISING>; 4939 4940 mboxes = <&ipcc IPCC_CLIENT_CDSP 4941 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4942 4943 qcom,remote-pid = <5>; 4944 4945 label = "cdsp"; 4946 4947 fastrpc { 4948 compatible = "qcom,fastrpc"; 4949 4950 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4951 4952 label = "cdsp"; 4953 4954 #address-cells = <1>; 4955 #size-cells = <0>; 4956 4957 compute-cb@1 { 4958 compatible = "qcom,fastrpc-compute-cb"; 4959 reg = <1>; 4960 4961 iommus = <&apps_smmu 0x1961 0x0>, 4962 <&apps_smmu 0x0c01 0x20>, 4963 <&apps_smmu 0x19c1 0x0>; 4964 }; 4965 4966 compute-cb@2 { 4967 compatible = "qcom,fastrpc-compute-cb"; 4968 reg = <2>; 4969 4970 iommus = <&apps_smmu 0x1962 0x0>, 4971 <&apps_smmu 0x0c02 0x20>, 4972 <&apps_smmu 0x19c2 0x0>; 4973 }; 4974 4975 compute-cb@3 { 4976 compatible = "qcom,fastrpc-compute-cb"; 4977 reg = <3>; 4978 4979 iommus = <&apps_smmu 0x1963 0x0>, 4980 <&apps_smmu 0x0c03 0x20>, 4981 <&apps_smmu 0x19c3 0x0>; 4982 }; 4983 4984 compute-cb@4 { 4985 compatible = "qcom,fastrpc-compute-cb"; 4986 reg = <4>; 4987 4988 iommus = <&apps_smmu 0x1964 0x0>, 4989 <&apps_smmu 0x0c04 0x20>, 4990 <&apps_smmu 0x19c4 0x0>; 4991 }; 4992 4993 compute-cb@5 { 4994 compatible = "qcom,fastrpc-compute-cb"; 4995 reg = <5>; 4996 4997 iommus = <&apps_smmu 0x1965 0x0>, 4998 <&apps_smmu 0x0c05 0x20>, 4999 <&apps_smmu 0x19c5 0x0>; 5000 }; 5001 5002 compute-cb@6 { 5003 compatible = "qcom,fastrpc-compute-cb"; 5004 reg = <6>; 5005 5006 iommus = <&apps_smmu 0x1966 0x0>, 5007 <&apps_smmu 0x0c06 0x20>, 5008 <&apps_smmu 0x19c6 0x0>; 5009 }; 5010 5011 compute-cb@7 { 5012 compatible = "qcom,fastrpc-compute-cb"; 5013 reg = <7>; 5014 5015 iommus = <&apps_smmu 0x1967 0x0>, 5016 <&apps_smmu 0x0c07 0x20>, 5017 <&apps_smmu 0x19c7 0x0>; 5018 }; 5019 5020 compute-cb@8 { 5021 compatible = "qcom,fastrpc-compute-cb"; 5022 reg = <8>; 5023 5024 iommus = <&apps_smmu 0x1968 0x0>, 5025 <&apps_smmu 0x0c08 0x20>, 5026 <&apps_smmu 0x19c8 0x0>; 5027 }; 5028 }; 5029 }; 5030 }; 5031 }; 5032 5033 thermal-zones { 5034 aoss0-thermal { 5035 polling-delay-passive = <0>; 5036 polling-delay = <0>; 5037 thermal-sensors = <&tsens0 0>; 5038 5039 trips { 5040 trip-point0 { 5041 temperature = <90000>; 5042 hysteresis = <2000>; 5043 type = "hot"; 5044 }; 5045 5046 aoss0-critical { 5047 temperature = <110000>; 5048 hysteresis = <0>; 5049 type = "critical"; 5050 }; 5051 }; 5052 }; 5053 5054 cpuss0-thermal { 5055 polling-delay-passive = <0>; 5056 polling-delay = <0>; 5057 thermal-sensors = <&tsens0 1>; 5058 5059 trips { 5060 trip-point0 { 5061 temperature = <90000>; 5062 hysteresis = <2000>; 5063 type = "hot"; 5064 }; 5065 5066 cpuss0-critical { 5067 temperature = <110000>; 5068 hysteresis = <0>; 5069 type = "critical"; 5070 }; 5071 }; 5072 }; 5073 5074 cpuss1-thermal { 5075 polling-delay-passive = <0>; 5076 polling-delay = <0>; 5077 thermal-sensors = <&tsens0 2>; 5078 5079 trips { 5080 trip-point0 { 5081 temperature = <90000>; 5082 hysteresis = <2000>; 5083 type = "hot"; 5084 }; 5085 5086 cpuss1-critical { 5087 temperature = <110000>; 5088 hysteresis = <0>; 5089 type = "critical"; 5090 }; 5091 }; 5092 }; 5093 5094 cpuss2-thermal { 5095 polling-delay-passive = <0>; 5096 polling-delay = <0>; 5097 thermal-sensors = <&tsens0 3>; 5098 5099 trips { 5100 trip-point0 { 5101 temperature = <90000>; 5102 hysteresis = <2000>; 5103 type = "hot"; 5104 }; 5105 5106 cpuss2-critical { 5107 temperature = <110000>; 5108 hysteresis = <0>; 5109 type = "critical"; 5110 }; 5111 }; 5112 }; 5113 5114 cpuss3-thermal { 5115 polling-delay-passive = <0>; 5116 polling-delay = <0>; 5117 thermal-sensors = <&tsens0 4>; 5118 5119 trips { 5120 trip-point0 { 5121 temperature = <90000>; 5122 hysteresis = <2000>; 5123 type = "hot"; 5124 }; 5125 5126 cpuss3-critical { 5127 temperature = <110000>; 5128 hysteresis = <0>; 5129 type = "critical"; 5130 }; 5131 }; 5132 }; 5133 5134 cpu2-top-thermal { 5135 polling-delay-passive = <0>; 5136 polling-delay = <0>; 5137 thermal-sensors = <&tsens0 5>; 5138 5139 trips { 5140 trip-point0 { 5141 temperature = <90000>; 5142 hysteresis = <2000>; 5143 type = "passive"; 5144 }; 5145 5146 trip-point1 { 5147 temperature = <95000>; 5148 hysteresis = <2000>; 5149 type = "passive"; 5150 }; 5151 5152 cpu2-critical { 5153 temperature = <110000>; 5154 hysteresis = <1000>; 5155 type = "critical"; 5156 }; 5157 }; 5158 }; 5159 5160 cpu2-bottom-thermal { 5161 polling-delay-passive = <0>; 5162 polling-delay = <0>; 5163 thermal-sensors = <&tsens0 6>; 5164 5165 trips { 5166 trip-point0 { 5167 temperature = <90000>; 5168 hysteresis = <2000>; 5169 type = "passive"; 5170 }; 5171 5172 trip-point1 { 5173 temperature = <95000>; 5174 hysteresis = <2000>; 5175 type = "passive"; 5176 }; 5177 5178 cpu2-critical { 5179 temperature = <110000>; 5180 hysteresis = <1000>; 5181 type = "critical"; 5182 }; 5183 }; 5184 }; 5185 5186 cpu3-top-thermal { 5187 polling-delay-passive = <0>; 5188 polling-delay = <0>; 5189 thermal-sensors = <&tsens0 7>; 5190 5191 trips { 5192 trip-point0 { 5193 temperature = <90000>; 5194 hysteresis = <2000>; 5195 type = "passive"; 5196 }; 5197 5198 trip-point1 { 5199 temperature = <95000>; 5200 hysteresis = <2000>; 5201 type = "passive"; 5202 }; 5203 5204 cpu3-critical { 5205 temperature = <110000>; 5206 hysteresis = <1000>; 5207 type = "critical"; 5208 }; 5209 }; 5210 }; 5211 5212 cpu3-bottom-thermal { 5213 polling-delay-passive = <0>; 5214 polling-delay = <0>; 5215 thermal-sensors = <&tsens0 8>; 5216 5217 trips { 5218 trip-point0 { 5219 temperature = <90000>; 5220 hysteresis = <2000>; 5221 type = "passive"; 5222 }; 5223 5224 trip-point1 { 5225 temperature = <95000>; 5226 hysteresis = <2000>; 5227 type = "passive"; 5228 }; 5229 5230 cpu3-critical { 5231 temperature = <110000>; 5232 hysteresis = <1000>; 5233 type = "critical"; 5234 }; 5235 }; 5236 }; 5237 5238 cpu4-top-thermal { 5239 polling-delay-passive = <0>; 5240 polling-delay = <0>; 5241 thermal-sensors = <&tsens0 9>; 5242 5243 trips { 5244 trip-point0 { 5245 temperature = <90000>; 5246 hysteresis = <2000>; 5247 type = "passive"; 5248 }; 5249 5250 trip-point1 { 5251 temperature = <95000>; 5252 hysteresis = <2000>; 5253 type = "passive"; 5254 }; 5255 5256 cpu4-critical { 5257 temperature = <110000>; 5258 hysteresis = <1000>; 5259 type = "critical"; 5260 }; 5261 }; 5262 }; 5263 5264 cpu4-bottom-thermal { 5265 polling-delay-passive = <0>; 5266 polling-delay = <0>; 5267 thermal-sensors = <&tsens0 10>; 5268 5269 trips { 5270 trip-point0 { 5271 temperature = <90000>; 5272 hysteresis = <2000>; 5273 type = "passive"; 5274 }; 5275 5276 trip-point1 { 5277 temperature = <95000>; 5278 hysteresis = <2000>; 5279 type = "passive"; 5280 }; 5281 5282 cpu4-critical { 5283 temperature = <110000>; 5284 hysteresis = <1000>; 5285 type = "critical"; 5286 }; 5287 }; 5288 }; 5289 5290 cpu5-top-thermal { 5291 polling-delay-passive = <0>; 5292 polling-delay = <0>; 5293 thermal-sensors = <&tsens0 11>; 5294 5295 trips { 5296 trip-point0 { 5297 temperature = <90000>; 5298 hysteresis = <2000>; 5299 type = "passive"; 5300 }; 5301 5302 trip-point1 { 5303 temperature = <95000>; 5304 hysteresis = <2000>; 5305 type = "passive"; 5306 }; 5307 5308 cpu5-critical { 5309 temperature = <110000>; 5310 hysteresis = <1000>; 5311 type = "critical"; 5312 }; 5313 }; 5314 }; 5315 5316 cpu5-bottom-thermal { 5317 polling-delay-passive = <0>; 5318 polling-delay = <0>; 5319 thermal-sensors = <&tsens0 12>; 5320 5321 trips { 5322 trip-point0 { 5323 temperature = <90000>; 5324 hysteresis = <2000>; 5325 type = "passive"; 5326 }; 5327 5328 trip-point1 { 5329 temperature = <95000>; 5330 hysteresis = <2000>; 5331 type = "passive"; 5332 }; 5333 5334 cpu5-critical { 5335 temperature = <110000>; 5336 hysteresis = <1000>; 5337 type = "critical"; 5338 }; 5339 }; 5340 }; 5341 5342 cpu6-top-thermal { 5343 polling-delay-passive = <0>; 5344 polling-delay = <0>; 5345 thermal-sensors = <&tsens0 13>; 5346 5347 trips { 5348 trip-point0 { 5349 temperature = <90000>; 5350 hysteresis = <2000>; 5351 type = "passive"; 5352 }; 5353 5354 trip-point1 { 5355 temperature = <95000>; 5356 hysteresis = <2000>; 5357 type = "passive"; 5358 }; 5359 5360 cpu6-critical { 5361 temperature = <110000>; 5362 hysteresis = <1000>; 5363 type = "critical"; 5364 }; 5365 }; 5366 }; 5367 5368 cpu6-bottom-thermal { 5369 polling-delay-passive = <0>; 5370 polling-delay = <0>; 5371 thermal-sensors = <&tsens0 14>; 5372 5373 trips { 5374 trip-point0 { 5375 temperature = <90000>; 5376 hysteresis = <2000>; 5377 type = "passive"; 5378 }; 5379 5380 trip-point1 { 5381 temperature = <95000>; 5382 hysteresis = <2000>; 5383 type = "passive"; 5384 }; 5385 5386 cpu6-critical { 5387 temperature = <110000>; 5388 hysteresis = <1000>; 5389 type = "critical"; 5390 }; 5391 }; 5392 }; 5393 5394 aoss1-thermal { 5395 polling-delay-passive = <0>; 5396 polling-delay = <0>; 5397 thermal-sensors = <&tsens1 0>; 5398 5399 trips { 5400 trip-point0 { 5401 temperature = <90000>; 5402 hysteresis = <2000>; 5403 type = "hot"; 5404 }; 5405 5406 aoss1-critical { 5407 temperature = <110000>; 5408 hysteresis = <0>; 5409 type = "critical"; 5410 }; 5411 }; 5412 }; 5413 5414 cpu7-top-thermal { 5415 polling-delay-passive = <0>; 5416 polling-delay = <0>; 5417 thermal-sensors = <&tsens1 1>; 5418 5419 trips { 5420 trip-point0 { 5421 temperature = <90000>; 5422 hysteresis = <2000>; 5423 type = "passive"; 5424 }; 5425 5426 trip-point1 { 5427 temperature = <95000>; 5428 hysteresis = <2000>; 5429 type = "passive"; 5430 }; 5431 5432 cpu7-critical { 5433 temperature = <110000>; 5434 hysteresis = <1000>; 5435 type = "critical"; 5436 }; 5437 }; 5438 }; 5439 5440 cpu7-middle-thermal { 5441 polling-delay-passive = <0>; 5442 polling-delay = <0>; 5443 thermal-sensors = <&tsens1 2>; 5444 5445 trips { 5446 trip-point0 { 5447 temperature = <90000>; 5448 hysteresis = <2000>; 5449 type = "passive"; 5450 }; 5451 5452 trip-point1 { 5453 temperature = <95000>; 5454 hysteresis = <2000>; 5455 type = "passive"; 5456 }; 5457 5458 cpu7-critical { 5459 temperature = <110000>; 5460 hysteresis = <1000>; 5461 type = "critical"; 5462 }; 5463 }; 5464 }; 5465 5466 cpu7-bottom-thermal { 5467 polling-delay-passive = <0>; 5468 polling-delay = <0>; 5469 thermal-sensors = <&tsens1 3>; 5470 5471 trips { 5472 trip-point0 { 5473 temperature = <90000>; 5474 hysteresis = <2000>; 5475 type = "passive"; 5476 }; 5477 5478 trip-point1 { 5479 temperature = <95000>; 5480 hysteresis = <2000>; 5481 type = "passive"; 5482 }; 5483 5484 cpu7-critical { 5485 temperature = <110000>; 5486 hysteresis = <1000>; 5487 type = "critical"; 5488 }; 5489 }; 5490 }; 5491 5492 cpu0-thermal { 5493 polling-delay-passive = <0>; 5494 polling-delay = <0>; 5495 thermal-sensors = <&tsens1 4>; 5496 5497 trips { 5498 trip-point0 { 5499 temperature = <90000>; 5500 hysteresis = <2000>; 5501 type = "passive"; 5502 }; 5503 5504 trip-point1 { 5505 temperature = <95000>; 5506 hysteresis = <2000>; 5507 type = "passive"; 5508 }; 5509 5510 cpu0-critical { 5511 temperature = <110000>; 5512 hysteresis = <1000>; 5513 type = "critical"; 5514 }; 5515 }; 5516 }; 5517 5518 cpu1-thermal { 5519 polling-delay-passive = <0>; 5520 polling-delay = <0>; 5521 thermal-sensors = <&tsens1 5>; 5522 5523 trips { 5524 trip-point0 { 5525 temperature = <90000>; 5526 hysteresis = <2000>; 5527 type = "passive"; 5528 }; 5529 5530 trip-point1 { 5531 temperature = <95000>; 5532 hysteresis = <2000>; 5533 type = "passive"; 5534 }; 5535 5536 cpu1-critical { 5537 temperature = <110000>; 5538 hysteresis = <1000>; 5539 type = "critical"; 5540 }; 5541 }; 5542 }; 5543 5544 nsphvx0-thermal { 5545 polling-delay-passive = <10>; 5546 polling-delay = <0>; 5547 thermal-sensors = <&tsens2 6>; 5548 5549 trips { 5550 trip-point0 { 5551 temperature = <90000>; 5552 hysteresis = <2000>; 5553 type = "hot"; 5554 }; 5555 5556 nsphvx1-critical { 5557 temperature = <110000>; 5558 hysteresis = <0>; 5559 type = "critical"; 5560 }; 5561 }; 5562 }; 5563 5564 nsphvx1-thermal { 5565 polling-delay-passive = <10>; 5566 polling-delay = <0>; 5567 thermal-sensors = <&tsens2 7>; 5568 5569 trips { 5570 trip-point0 { 5571 temperature = <90000>; 5572 hysteresis = <2000>; 5573 type = "hot"; 5574 }; 5575 5576 nsphvx1-critical { 5577 temperature = <110000>; 5578 hysteresis = <0>; 5579 type = "critical"; 5580 }; 5581 }; 5582 }; 5583 5584 nsphmx0-thermal { 5585 polling-delay-passive = <10>; 5586 polling-delay = <0>; 5587 thermal-sensors = <&tsens2 8>; 5588 5589 trips { 5590 trip-point0 { 5591 temperature = <90000>; 5592 hysteresis = <2000>; 5593 type = "hot"; 5594 }; 5595 5596 nsphmx0-critical { 5597 temperature = <110000>; 5598 hysteresis = <0>; 5599 type = "critical"; 5600 }; 5601 }; 5602 }; 5603 5604 nsphmx1-thermal { 5605 polling-delay-passive = <10>; 5606 polling-delay = <0>; 5607 thermal-sensors = <&tsens2 9>; 5608 5609 trips { 5610 trip-point0 { 5611 temperature = <90000>; 5612 hysteresis = <2000>; 5613 type = "hot"; 5614 }; 5615 5616 nsphmx1-critical { 5617 temperature = <110000>; 5618 hysteresis = <0>; 5619 type = "critical"; 5620 }; 5621 }; 5622 }; 5623 5624 nsphmx2-thermal { 5625 polling-delay-passive = <10>; 5626 polling-delay = <0>; 5627 thermal-sensors = <&tsens2 10>; 5628 5629 trips { 5630 trip-point0 { 5631 temperature = <90000>; 5632 hysteresis = <2000>; 5633 type = "hot"; 5634 }; 5635 5636 nsphmx2-critical { 5637 temperature = <110000>; 5638 hysteresis = <0>; 5639 type = "critical"; 5640 }; 5641 }; 5642 }; 5643 5644 nsphmx3-thermal { 5645 polling-delay-passive = <10>; 5646 polling-delay = <0>; 5647 thermal-sensors = <&tsens2 11>; 5648 5649 trips { 5650 trip-point0 { 5651 temperature = <90000>; 5652 hysteresis = <2000>; 5653 type = "hot"; 5654 }; 5655 5656 nsphmx3-critical { 5657 temperature = <110000>; 5658 hysteresis = <0>; 5659 type = "critical"; 5660 }; 5661 }; 5662 }; 5663 5664 video-thermal { 5665 polling-delay-passive = <10>; 5666 polling-delay = <0>; 5667 thermal-sensors = <&tsens1 12>; 5668 5669 trips { 5670 trip-point0 { 5671 temperature = <90000>; 5672 hysteresis = <2000>; 5673 type = "hot"; 5674 }; 5675 5676 video-critical { 5677 temperature = <110000>; 5678 hysteresis = <0>; 5679 type = "critical"; 5680 }; 5681 }; 5682 }; 5683 5684 ddr-thermal { 5685 polling-delay-passive = <10>; 5686 polling-delay = <0>; 5687 thermal-sensors = <&tsens1 13>; 5688 5689 trips { 5690 trip-point0 { 5691 temperature = <90000>; 5692 hysteresis = <2000>; 5693 type = "hot"; 5694 }; 5695 5696 ddr-critical { 5697 temperature = <110000>; 5698 hysteresis = <0>; 5699 type = "critical"; 5700 }; 5701 }; 5702 }; 5703 5704 camera0-thermal { 5705 polling-delay-passive = <0>; 5706 polling-delay = <0>; 5707 thermal-sensors = <&tsens1 14>; 5708 5709 trips { 5710 trip-point0 { 5711 temperature = <90000>; 5712 hysteresis = <2000>; 5713 type = "hot"; 5714 }; 5715 5716 camera0-critical { 5717 temperature = <110000>; 5718 hysteresis = <0>; 5719 type = "critical"; 5720 }; 5721 }; 5722 }; 5723 5724 camera1-thermal { 5725 polling-delay-passive = <0>; 5726 polling-delay = <0>; 5727 thermal-sensors = <&tsens1 15>; 5728 5729 trips { 5730 trip-point0 { 5731 temperature = <90000>; 5732 hysteresis = <2000>; 5733 type = "hot"; 5734 }; 5735 5736 camera1-critical { 5737 temperature = <110000>; 5738 hysteresis = <0>; 5739 type = "critical"; 5740 }; 5741 }; 5742 }; 5743 5744 aoss2-thermal { 5745 polling-delay-passive = <0>; 5746 polling-delay = <0>; 5747 thermal-sensors = <&tsens2 0>; 5748 5749 trips { 5750 trip-point0 { 5751 temperature = <90000>; 5752 hysteresis = <2000>; 5753 type = "hot"; 5754 }; 5755 5756 aoss2-critical { 5757 temperature = <110000>; 5758 hysteresis = <0>; 5759 type = "critical"; 5760 }; 5761 }; 5762 }; 5763 5764 gpuss0-thermal { 5765 polling-delay-passive = <10>; 5766 polling-delay = <0>; 5767 thermal-sensors = <&tsens2 1>; 5768 5769 trips { 5770 trip-point0 { 5771 temperature = <90000>; 5772 hysteresis = <2000>; 5773 type = "hot"; 5774 }; 5775 5776 gpuss0-critical { 5777 temperature = <110000>; 5778 hysteresis = <0>; 5779 type = "critical"; 5780 }; 5781 }; 5782 }; 5783 5784 gpuss1-thermal { 5785 polling-delay-passive = <10>; 5786 polling-delay = <0>; 5787 thermal-sensors = <&tsens2 2>; 5788 5789 trips { 5790 trip-point0 { 5791 temperature = <90000>; 5792 hysteresis = <2000>; 5793 type = "hot"; 5794 }; 5795 5796 gpuss1-critical { 5797 temperature = <110000>; 5798 hysteresis = <0>; 5799 type = "critical"; 5800 }; 5801 }; 5802 }; 5803 5804 gpuss2-thermal { 5805 polling-delay-passive = <10>; 5806 polling-delay = <0>; 5807 thermal-sensors = <&tsens2 3>; 5808 5809 trips { 5810 trip-point0 { 5811 temperature = <90000>; 5812 hysteresis = <2000>; 5813 type = "hot"; 5814 }; 5815 5816 gpuss2-critical { 5817 temperature = <110000>; 5818 hysteresis = <0>; 5819 type = "critical"; 5820 }; 5821 }; 5822 }; 5823 5824 gpuss3-thermal { 5825 polling-delay-passive = <10>; 5826 polling-delay = <0>; 5827 thermal-sensors = <&tsens2 4>; 5828 5829 trips { 5830 trip-point0 { 5831 temperature = <90000>; 5832 hysteresis = <2000>; 5833 type = "hot"; 5834 }; 5835 5836 gpuss3-critical { 5837 temperature = <110000>; 5838 hysteresis = <0>; 5839 type = "critical"; 5840 }; 5841 }; 5842 }; 5843 5844 gpuss4-thermal { 5845 polling-delay-passive = <10>; 5846 polling-delay = <0>; 5847 thermal-sensors = <&tsens2 5>; 5848 5849 trips { 5850 trip-point0 { 5851 temperature = <90000>; 5852 hysteresis = <2000>; 5853 type = "hot"; 5854 }; 5855 5856 gpuss4-critical { 5857 temperature = <110000>; 5858 hysteresis = <0>; 5859 type = "critical"; 5860 }; 5861 }; 5862 }; 5863 5864 gpuss5-thermal { 5865 polling-delay-passive = <10>; 5866 polling-delay = <0>; 5867 thermal-sensors = <&tsens2 6>; 5868 5869 trips { 5870 trip-point0 { 5871 temperature = <90000>; 5872 hysteresis = <2000>; 5873 type = "hot"; 5874 }; 5875 5876 gpuss5-critical { 5877 temperature = <110000>; 5878 hysteresis = <0>; 5879 type = "critical"; 5880 }; 5881 }; 5882 }; 5883 5884 gpuss6-thermal { 5885 polling-delay-passive = <10>; 5886 polling-delay = <0>; 5887 thermal-sensors = <&tsens2 7>; 5888 5889 trips { 5890 trip-point0 { 5891 temperature = <90000>; 5892 hysteresis = <2000>; 5893 type = "hot"; 5894 }; 5895 5896 gpuss6-critical { 5897 temperature = <110000>; 5898 hysteresis = <0>; 5899 type = "critical"; 5900 }; 5901 }; 5902 }; 5903 5904 gpuss7-thermal { 5905 polling-delay-passive = <10>; 5906 polling-delay = <0>; 5907 thermal-sensors = <&tsens2 8>; 5908 5909 trips { 5910 trip-point0 { 5911 temperature = <90000>; 5912 hysteresis = <2000>; 5913 type = "hot"; 5914 }; 5915 5916 gpuss7-critical { 5917 temperature = <110000>; 5918 hysteresis = <0>; 5919 type = "critical"; 5920 }; 5921 }; 5922 }; 5923 5924 modem0-thermal { 5925 polling-delay-passive = <0>; 5926 polling-delay = <0>; 5927 thermal-sensors = <&tsens2 9>; 5928 5929 trips { 5930 trip-point0 { 5931 temperature = <90000>; 5932 hysteresis = <2000>; 5933 type = "hot"; 5934 }; 5935 5936 modem0-critical { 5937 temperature = <110000>; 5938 hysteresis = <0>; 5939 type = "critical"; 5940 }; 5941 }; 5942 }; 5943 5944 modem1-thermal { 5945 polling-delay-passive = <0>; 5946 polling-delay = <0>; 5947 thermal-sensors = <&tsens2 10>; 5948 5949 trips { 5950 trip-point0 { 5951 temperature = <90000>; 5952 hysteresis = <2000>; 5953 type = "hot"; 5954 }; 5955 5956 modem1-critical { 5957 temperature = <110000>; 5958 hysteresis = <0>; 5959 type = "critical"; 5960 }; 5961 }; 5962 }; 5963 5964 modem2-thermal { 5965 polling-delay-passive = <0>; 5966 polling-delay = <0>; 5967 thermal-sensors = <&tsens2 11>; 5968 5969 trips { 5970 trip-point0 { 5971 temperature = <90000>; 5972 hysteresis = <2000>; 5973 type = "hot"; 5974 }; 5975 5976 modem2-critical { 5977 temperature = <110000>; 5978 hysteresis = <0>; 5979 type = "critical"; 5980 }; 5981 }; 5982 }; 5983 5984 modem3-thermal { 5985 polling-delay-passive = <0>; 5986 polling-delay = <0>; 5987 thermal-sensors = <&tsens2 12>; 5988 5989 trips { 5990 trip-point0 { 5991 temperature = <90000>; 5992 hysteresis = <2000>; 5993 type = "hot"; 5994 }; 5995 5996 modem3-critical { 5997 temperature = <110000>; 5998 hysteresis = <0>; 5999 type = "critical"; 6000 }; 6001 }; 6002 }; 6003 }; 6004 6005 timer { 6006 compatible = "arm,armv8-timer"; 6007 6008 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6009 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6010 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6011 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6012 }; 6013}; 6014