1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8650-dispcc.h> 8#include <dt-bindings/clock/qcom,sm8650-gcc.h> 9#include <dt-bindings/clock/qcom,sm8650-gpucc.h> 10#include <dt-bindings/clock/qcom,sm8650-tcsr.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/firmware/qcom,scm.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/reset/qcom,sm8650-gpucc.h> 22#include <dt-bindings/soc/qcom,gpr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 chosen { }; 34 35 clocks { 36 xo_board: xo-board { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 }; 45 46 bi_tcxo_div2: bi-tcxo-div2-clk { 47 compatible = "fixed-factor-clock"; 48 #clock-cells = <0>; 49 50 clocks = <&rpmhcc RPMH_CXO_CLK>; 51 clock-mult = <1>; 52 clock-div = <2>; 53 }; 54 55 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 56 compatible = "fixed-factor-clock"; 57 #clock-cells = <0>; 58 59 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 60 clock-mult = <1>; 61 clock-div = <2>; 62 }; 63 64 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 65 compatible = "fixed-clock"; 66 #clock-cells = <0>; 67 }; 68 }; 69 70 cpus { 71 #address-cells = <2>; 72 #size-cells = <0>; 73 74 CPU0: cpu@0 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a520"; 77 reg = <0 0>; 78 79 clocks = <&cpufreq_hw 0>; 80 81 power-domains = <&CPU_PD0>; 82 power-domain-names = "psci"; 83 84 enable-method = "psci"; 85 next-level-cache = <&L2_0>; 86 capacity-dmips-mhz = <1024>; 87 dynamic-power-coefficient = <100>; 88 89 qcom,freq-domain = <&cpufreq_hw 0>; 90 91 #cooling-cells = <2>; 92 93 L2_0: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 next-level-cache = <&L3_0>; 98 99 L3_0: l3-cache { 100 compatible = "cache"; 101 cache-level = <3>; 102 cache-unified; 103 }; 104 }; 105 }; 106 107 CPU1: cpu@100 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a520"; 110 reg = <0 0x100>; 111 112 clocks = <&cpufreq_hw 0>; 113 114 power-domains = <&CPU_PD1>; 115 power-domain-names = "psci"; 116 117 enable-method = "psci"; 118 next-level-cache = <&L2_0>; 119 capacity-dmips-mhz = <1024>; 120 dynamic-power-coefficient = <100>; 121 122 qcom,freq-domain = <&cpufreq_hw 0>; 123 124 #cooling-cells = <2>; 125 }; 126 127 CPU2: cpu@200 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a720"; 130 reg = <0 0x200>; 131 132 clocks = <&cpufreq_hw 3>; 133 134 power-domains = <&CPU_PD2>; 135 power-domain-names = "psci"; 136 137 enable-method = "psci"; 138 next-level-cache = <&L2_200>; 139 capacity-dmips-mhz = <1792>; 140 dynamic-power-coefficient = <238>; 141 142 qcom,freq-domain = <&cpufreq_hw 3>; 143 144 #cooling-cells = <2>; 145 146 L2_200: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU3: cpu@300 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a720"; 157 reg = <0 0x300>; 158 159 clocks = <&cpufreq_hw 3>; 160 161 power-domains = <&CPU_PD3>; 162 power-domain-names = "psci"; 163 164 enable-method = "psci"; 165 next-level-cache = <&L2_200>; 166 capacity-dmips-mhz = <1792>; 167 dynamic-power-coefficient = <238>; 168 169 qcom,freq-domain = <&cpufreq_hw 3>; 170 171 #cooling-cells = <2>; 172 }; 173 174 CPU4: cpu@400 { 175 device_type = "cpu"; 176 compatible = "arm,cortex-a720"; 177 reg = <0 0x400>; 178 179 clocks = <&cpufreq_hw 3>; 180 181 power-domains = <&CPU_PD4>; 182 power-domain-names = "psci"; 183 184 enable-method = "psci"; 185 next-level-cache = <&L2_400>; 186 capacity-dmips-mhz = <1792>; 187 dynamic-power-coefficient = <238>; 188 189 qcom,freq-domain = <&cpufreq_hw 3>; 190 191 #cooling-cells = <2>; 192 193 L2_400: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 next-level-cache = <&L3_0>; 198 }; 199 }; 200 201 CPU5: cpu@500 { 202 device_type = "cpu"; 203 compatible = "arm,cortex-a720"; 204 reg = <0 0x500>; 205 206 clocks = <&cpufreq_hw 1>; 207 208 power-domains = <&CPU_PD5>; 209 power-domain-names = "psci"; 210 211 enable-method = "psci"; 212 next-level-cache = <&L2_500>; 213 capacity-dmips-mhz = <1792>; 214 dynamic-power-coefficient = <238>; 215 216 qcom,freq-domain = <&cpufreq_hw 1>; 217 218 #cooling-cells = <2>; 219 220 L2_500: l2-cache { 221 compatible = "cache"; 222 cache-level = <2>; 223 cache-unified; 224 next-level-cache = <&L3_0>; 225 }; 226 }; 227 228 CPU6: cpu@600 { 229 device_type = "cpu"; 230 compatible = "arm,cortex-a720"; 231 reg = <0 0x600>; 232 233 clocks = <&cpufreq_hw 1>; 234 235 power-domains = <&CPU_PD6>; 236 power-domain-names = "psci"; 237 238 enable-method = "psci"; 239 next-level-cache = <&L2_600>; 240 capacity-dmips-mhz = <1792>; 241 dynamic-power-coefficient = <238>; 242 243 qcom,freq-domain = <&cpufreq_hw 1>; 244 245 #cooling-cells = <2>; 246 247 L2_600: l2-cache { 248 compatible = "cache"; 249 cache-level = <2>; 250 cache-unified; 251 next-level-cache = <&L3_0>; 252 }; 253 }; 254 255 CPU7: cpu@700 { 256 device_type = "cpu"; 257 compatible = "arm,cortex-x4"; 258 reg = <0 0x700>; 259 260 clocks = <&cpufreq_hw 2>; 261 262 power-domains = <&CPU_PD7>; 263 power-domain-names = "psci"; 264 265 enable-method = "psci"; 266 next-level-cache = <&L2_700>; 267 capacity-dmips-mhz = <1894>; 268 dynamic-power-coefficient = <588>; 269 270 qcom,freq-domain = <&cpufreq_hw 2>; 271 272 #cooling-cells = <2>; 273 274 L2_700: l2-cache { 275 compatible = "cache"; 276 cache-level = <2>; 277 cache-unified; 278 next-level-cache = <&L3_0>; 279 }; 280 }; 281 282 cpu-map { 283 cluster0 { 284 core0 { 285 cpu = <&CPU0>; 286 }; 287 288 core1 { 289 cpu = <&CPU1>; 290 }; 291 292 core2 { 293 cpu = <&CPU2>; 294 }; 295 296 core3 { 297 cpu = <&CPU3>; 298 }; 299 300 core4 { 301 cpu = <&CPU4>; 302 }; 303 304 core5 { 305 cpu = <&CPU5>; 306 }; 307 308 core6 { 309 cpu = <&CPU6>; 310 }; 311 312 core7 { 313 cpu = <&CPU7>; 314 }; 315 }; 316 }; 317 318 idle-states { 319 entry-method = "psci"; 320 321 SILVER_CPU_SLEEP_0: cpu-sleep-0-0 { 322 compatible = "arm,idle-state"; 323 idle-state-name = "silver-rail-power-collapse"; 324 arm,psci-suspend-param = <0x40000004>; 325 entry-latency-us = <550>; 326 exit-latency-us = <750>; 327 min-residency-us = <6700>; 328 local-timer-stop; 329 }; 330 331 GOLD_CPU_SLEEP_0: cpu-sleep-1-0 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "gold-rail-power-collapse"; 334 arm,psci-suspend-param = <0x40000004>; 335 entry-latency-us = <600>; 336 exit-latency-us = <1300>; 337 min-residency-us = <8136>; 338 local-timer-stop; 339 }; 340 341 GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "gold-plus-rail-power-collapse"; 344 arm,psci-suspend-param = <0x40000004>; 345 entry-latency-us = <500>; 346 exit-latency-us = <1350>; 347 min-residency-us = <7480>; 348 local-timer-stop; 349 }; 350 }; 351 352 domain-idle-states { 353 CLUSTER_SLEEP_0: cluster-sleep-0 { 354 compatible = "domain-idle-state"; 355 arm,psci-suspend-param = <0x41000044>; 356 entry-latency-us = <750>; 357 exit-latency-us = <2350>; 358 min-residency-us = <9144>; 359 }; 360 361 CLUSTER_SLEEP_1: cluster-sleep-1 { 362 compatible = "domain-idle-state"; 363 arm,psci-suspend-param = <0x4100c344>; 364 entry-latency-us = <2800>; 365 exit-latency-us = <4400>; 366 min-residency-us = <10150>; 367 }; 368 }; 369 }; 370 371 firmware { 372 scm: scm { 373 compatible = "qcom,scm-sm8650", "qcom,scm"; 374 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 375 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 376 }; 377 }; 378 379 clk_virt: interconnect-0 { 380 compatible = "qcom,sm8650-clk-virt"; 381 #interconnect-cells = <2>; 382 qcom,bcm-voters = <&apps_bcm_voter>; 383 }; 384 385 mc_virt: interconnect-1 { 386 compatible = "qcom,sm8650-mc-virt"; 387 #interconnect-cells = <2>; 388 qcom,bcm-voters = <&apps_bcm_voter>; 389 }; 390 391 memory@a0000000 { 392 device_type = "memory"; 393 /* We expect the bootloader to fill in the size */ 394 reg = <0 0xa0000000 0 0>; 395 }; 396 397 pmu { 398 compatible = "arm,armv8-pmuv3"; 399 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 400 }; 401 402 psci { 403 compatible = "arm,psci-1.0"; 404 method = "smc"; 405 406 CPU_PD0: power-domain-cpu0 { 407 #power-domain-cells = <0>; 408 power-domains = <&CLUSTER_PD>; 409 domain-idle-states = <&SILVER_CPU_SLEEP_0>; 410 }; 411 412 CPU_PD1: power-domain-cpu1 { 413 #power-domain-cells = <0>; 414 power-domains = <&CLUSTER_PD>; 415 domain-idle-states = <&SILVER_CPU_SLEEP_0>; 416 }; 417 418 CPU_PD2: power-domain-cpu2 { 419 #power-domain-cells = <0>; 420 power-domains = <&CLUSTER_PD>; 421 domain-idle-states = <&SILVER_CPU_SLEEP_0>; 422 }; 423 424 CPU_PD3: power-domain-cpu3 { 425 #power-domain-cells = <0>; 426 power-domains = <&CLUSTER_PD>; 427 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 428 }; 429 430 CPU_PD4: power-domain-cpu4 { 431 #power-domain-cells = <0>; 432 power-domains = <&CLUSTER_PD>; 433 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 434 }; 435 436 CPU_PD5: power-domain-cpu5 { 437 #power-domain-cells = <0>; 438 power-domains = <&CLUSTER_PD>; 439 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 440 }; 441 442 CPU_PD6: power-domain-cpu6 { 443 #power-domain-cells = <0>; 444 power-domains = <&CLUSTER_PD>; 445 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 446 }; 447 448 CPU_PD7: power-domain-cpu7 { 449 #power-domain-cells = <0>; 450 power-domains = <&CLUSTER_PD>; 451 domain-idle-states = <&GOLD_PLUS_CPU_SLEEP_0>; 452 }; 453 454 CLUSTER_PD: power-domain-cluster { 455 #power-domain-cells = <0>; 456 domain-idle-states = <&CLUSTER_SLEEP_0>, 457 <&CLUSTER_SLEEP_1>; 458 }; 459 }; 460 461 reserved_memory: reserved-memory { 462 #address-cells = <2>; 463 #size-cells = <2>; 464 ranges; 465 466 hyp_mem: hyp@80000000 { 467 reg = <0 0x80000000 0 0xe00000>; 468 no-map; 469 }; 470 471 cpusys_vm_mem: cpusys-vm@80e00000 { 472 reg = <0 0x80e00000 0 0x400000>; 473 no-map; 474 }; 475 476 /* Merged xbl_dtlog, xbl_ramdump and aop_image regions */ 477 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 { 478 reg = <0 0x81a00000 0 0x260000>; 479 no-map; 480 }; 481 482 aop_cmd_db_mem: aop-cmd-db@81c60000 { 483 compatible = "qcom,cmd-db"; 484 reg = <0 0x81c60000 0 0x20000>; 485 no-map; 486 }; 487 488 /* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */ 489 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 490 reg = <0 0x81c80000 0 0x75000>; 491 no-map; 492 }; 493 494 /* Secdata region can be reused by apps */ 495 496 smem: smem@81d00000 { 497 compatible = "qcom,smem"; 498 reg = <0 0x81d00000 0 0x200000>; 499 hwlocks = <&tcsr_mutex 3>; 500 no-map; 501 }; 502 503 adsp_mhi_mem: adsp-mhi@81f00000 { 504 reg = <0 0x81f00000 0 0x20000>; 505 no-map; 506 }; 507 508 pvmfw_mem: pvmfw@824a0000 { 509 reg = <0 0x824a0000 0 0x100000>; 510 no-map; 511 }; 512 513 global_sync_mem: global-sync@82600000 { 514 reg = <0 0x82600000 0 0x100000>; 515 no-map; 516 }; 517 518 tz_stat_mem: tz-stat@82700000 { 519 reg = <0 0x82700000 0 0x100000>; 520 no-map; 521 }; 522 523 qdss_mem: qdss@82800000 { 524 reg = <0 0x82800000 0 0x2000000>; 525 no-map; 526 }; 527 528 qlink_logging_mem: qlink-logging@84800000 { 529 reg = <0 0x84800000 0 0x200000>; 530 no-map; 531 }; 532 533 mpss_dsm_mem: mpss-dsm@86b00000 { 534 reg = <0 0x86b00000 0 0x4900000>; 535 no-map; 536 }; 537 538 mpss_dsm_mem_2: mpss-dsm-2@8b400000 { 539 reg = <0 0x8b400000 0 0x800000>; 540 no-map; 541 }; 542 543 mpss_mem: mpss@8bc00000 { 544 reg = <0 0x8bc00000 0 0xf400000>; 545 no-map; 546 }; 547 548 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { 549 reg = <0 0x9b000000 0 0x80000>; 550 no-map; 551 }; 552 553 ipa_fw_mem: ipa-fw@9b080000 { 554 reg = <0 0x9b080000 0 0x10000>; 555 no-map; 556 }; 557 558 ipa_gsi_mem: ipa-gsi@9b090000 { 559 reg = <0 0x9b090000 0 0xa000>; 560 no-map; 561 }; 562 563 gpu_micro_code_mem: gpu-micro-code@9b09a000 { 564 reg = <0 0x9b09a000 0 0x2000>; 565 no-map; 566 }; 567 568 spss_region_mem: spss@9b0a0000 { 569 reg = <0 0x9b0a0000 0 0x1e0000>; 570 no-map; 571 }; 572 573 /* First part of the "SPU secure shared memory" region */ 574 spu_tz_shared_mem: spu-tz-shared@9b280000 { 575 reg = <0 0x9b280000 0 0x60000>; 576 no-map; 577 }; 578 579 /* Second part of the "SPU secure shared memory" region */ 580 spu_modem_shared_mem: spu-modem-shared@9b2e0000 { 581 reg = <0 0x9b2e0000 0 0x20000>; 582 no-map; 583 }; 584 585 camera_mem: camera@9b300000 { 586 reg = <0 0x9b300000 0 0x800000>; 587 no-map; 588 }; 589 590 video_mem: video@9bb00000 { 591 reg = <0 0x9bb00000 0 0x800000>; 592 no-map; 593 }; 594 595 cvp_mem: cvp@9c300000 { 596 reg = <0 0x9c300000 0 0x700000>; 597 no-map; 598 }; 599 600 cdsp_mem: cdsp@9ca00000 { 601 reg = <0 0x9ca00000 0 0x1400000>; 602 no-map; 603 }; 604 605 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 { 606 reg = <0 0x9de00000 0 0x80000>; 607 no-map; 608 }; 609 610 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 { 611 reg = <0 0x9de80000 0 0x80000>; 612 no-map; 613 }; 614 615 adspslpi_mem: adspslpi@9df00000 { 616 reg = <0 0x9df00000 0 0x4080000>; 617 no-map; 618 }; 619 620 rmtfs_mem: rmtfs@d7c00000 { 621 compatible = "qcom,rmtfs-mem"; 622 reg = <0 0xd7c00000 0 0x400000>; 623 no-map; 624 625 qcom,client-id = <1>; 626 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 627 }; 628 629 /* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */ 630 tz_merged_mem: tz-merged@d8000000 { 631 reg = <0 0xd8000000 0 0x800000>; 632 no-map; 633 }; 634 635 hwfence_shbuf: hwfence-shbuf@e6440000 { 636 reg = <0 0xe6440000 0 0x2dd000>; 637 no-map; 638 }; 639 640 trust_ui_vm_mem: trust-ui-vm@f3800000 { 641 reg = <0 0xf3800000 0 0x4400000>; 642 no-map; 643 }; 644 645 oem_vm_mem: oem-vm@f7c00000 { 646 reg = <0 0xf7c00000 0 0x4c00000>; 647 no-map; 648 }; 649 650 llcc_lpi_mem: llcc-lpi@ff800000 { 651 reg = <0 0xff800000 0 0x600000>; 652 no-map; 653 }; 654 }; 655 656 smp2p-adsp { 657 compatible = "qcom,smp2p"; 658 659 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 660 IPCC_MPROC_SIGNAL_SMP2P 661 IRQ_TYPE_EDGE_RISING>; 662 663 mboxes = <&ipcc IPCC_CLIENT_LPASS 664 IPCC_MPROC_SIGNAL_SMP2P>; 665 666 qcom,smem = <443>, <429>; 667 qcom,local-pid = <0>; 668 qcom,remote-pid = <2>; 669 670 smp2p_adsp_out: master-kernel { 671 qcom,entry-name = "master-kernel"; 672 #qcom,smem-state-cells = <1>; 673 }; 674 675 smp2p_adsp_in: slave-kernel { 676 qcom,entry-name = "slave-kernel"; 677 interrupt-controller; 678 #interrupt-cells = <2>; 679 }; 680 }; 681 682 smp2p-cdsp { 683 compatible = "qcom,smp2p"; 684 685 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 686 IPCC_MPROC_SIGNAL_SMP2P 687 IRQ_TYPE_EDGE_RISING>; 688 689 mboxes = <&ipcc IPCC_CLIENT_CDSP 690 IPCC_MPROC_SIGNAL_SMP2P>; 691 692 qcom,smem = <94>, <432>; 693 qcom,local-pid = <0>; 694 qcom,remote-pid = <5>; 695 696 smp2p_cdsp_out: master-kernel { 697 qcom,entry-name = "master-kernel"; 698 #qcom,smem-state-cells = <1>; 699 }; 700 701 smp2p_cdsp_in: slave-kernel { 702 qcom,entry-name = "slave-kernel"; 703 interrupt-controller; 704 #interrupt-cells = <2>; 705 }; 706 }; 707 708 smp2p-modem { 709 compatible = "qcom,smp2p"; 710 711 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 712 IPCC_MPROC_SIGNAL_SMP2P 713 IRQ_TYPE_EDGE_RISING>; 714 715 mboxes = <&ipcc IPCC_CLIENT_MPSS 716 IPCC_MPROC_SIGNAL_SMP2P>; 717 718 qcom,smem = <435>, <428>; 719 qcom,local-pid = <0>; 720 qcom,remote-pid = <1>; 721 722 smp2p_modem_out: master-kernel { 723 qcom,entry-name = "master-kernel"; 724 #qcom,smem-state-cells = <1>; 725 }; 726 727 smp2p_modem_in: slave-kernel { 728 qcom,entry-name = "slave-kernel"; 729 interrupt-controller; 730 #interrupt-cells = <2>; 731 }; 732 733 ipa_smp2p_out: ipa-ap-to-modem { 734 qcom,entry-name = "ipa"; 735 #qcom,smem-state-cells = <1>; 736 }; 737 738 ipa_smp2p_in: ipa-modem-to-ap { 739 qcom,entry-name = "ipa"; 740 interrupt-controller; 741 #interrupt-cells = <2>; 742 }; 743 }; 744 745 soc: soc@0 { 746 compatible = "simple-bus"; 747 748 #address-cells = <2>; 749 #size-cells = <2>; 750 dma-ranges = <0 0 0 0 0x10 0>; 751 ranges = <0 0 0 0 0x10 0>; 752 753 gcc: clock-controller@100000 { 754 compatible = "qcom,sm8650-gcc"; 755 reg = <0 0x00100000 0 0x1f4200>; 756 757 clocks = <&bi_tcxo_div2>, 758 <&bi_tcxo_ao_div2>, 759 <&sleep_clk>, 760 <&pcie0_phy>, 761 <&pcie1_phy>, 762 <&pcie_1_phy_aux_clk>, 763 <&ufs_mem_phy 0>, 764 <&ufs_mem_phy 1>, 765 <&ufs_mem_phy 2>, 766 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 767 768 #clock-cells = <1>; 769 #reset-cells = <1>; 770 #power-domain-cells = <1>; 771 }; 772 773 ipcc: mailbox@406000 { 774 compatible = "qcom,sm8650-ipcc", "qcom,ipcc"; 775 reg = <0 0x00406000 0 0x1000>; 776 777 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 778 interrupt-controller; 779 #interrupt-cells = <3>; 780 781 #mbox-cells = <2>; 782 }; 783 784 gpi_dma2: dma-controller@800000 { 785 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 786 reg = <0 0x00800000 0 0x60000>; 787 788 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 800 801 dma-channels = <12>; 802 dma-channel-mask = <0x3f>; 803 #dma-cells = <3>; 804 805 iommus = <&apps_smmu 0x436 0>; 806 807 dma-coherent; 808 809 status = "disabled"; 810 }; 811 812 qupv3_id_1: geniqup@8c0000 { 813 compatible = "qcom,geni-se-qup"; 814 reg = <0 0x008c0000 0 0x2000>; 815 816 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 817 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 818 clock-names = "m-ahb", 819 "s-ahb"; 820 821 iommus = <&apps_smmu 0x423 0>; 822 823 dma-coherent; 824 825 #address-cells = <2>; 826 #size-cells = <2>; 827 ranges; 828 829 status = "disabled"; 830 831 i2c8: i2c@880000 { 832 compatible = "qcom,geni-i2c"; 833 reg = <0 0x00880000 0 0x4000>; 834 835 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 836 837 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 838 clock-names = "se"; 839 840 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 841 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 842 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 843 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 844 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 845 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 846 interconnect-names = "qup-core", 847 "qup-config", 848 "qup-memory"; 849 850 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 851 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 852 dma-names = "tx", 853 "rx"; 854 855 pinctrl-0 = <&qup_i2c8_data_clk>; 856 pinctrl-names = "default"; 857 858 #address-cells = <1>; 859 #size-cells = <0>; 860 861 status = "disabled"; 862 }; 863 864 spi8: spi@880000 { 865 compatible = "qcom,geni-spi"; 866 reg = <0 0x00880000 0 0x4000>; 867 868 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 869 870 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 871 clock-names = "se"; 872 873 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 874 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 875 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 876 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 877 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 878 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 879 interconnect-names = "qup-core", 880 "qup-config", 881 "qup-memory"; 882 883 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 884 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 885 dma-names = "tx", 886 "rx"; 887 888 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 889 pinctrl-names = "default"; 890 891 #address-cells = <1>; 892 #size-cells = <0>; 893 894 status = "disabled"; 895 }; 896 897 i2c9: i2c@884000 { 898 compatible = "qcom,geni-i2c"; 899 reg = <0 0x00884000 0 0x4000>; 900 901 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 902 903 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 904 clock-names = "se"; 905 906 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 907 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 908 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 909 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 910 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 911 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 912 interconnect-names = "qup-core", 913 "qup-config", 914 "qup-memory"; 915 916 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 917 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 918 dma-names = "tx", 919 "rx"; 920 921 pinctrl-0 = <&qup_i2c9_data_clk>; 922 pinctrl-names = "default"; 923 924 #address-cells = <1>; 925 #size-cells = <0>; 926 927 status = "disabled"; 928 }; 929 930 spi9: spi@884000 { 931 compatible = "qcom,geni-spi"; 932 reg = <0 0x00884000 0 0x4000>; 933 934 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 935 936 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 937 clock-names = "se"; 938 939 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 940 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 941 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 942 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 943 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 944 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 945 interconnect-names = "qup-core", 946 "qup-config", 947 "qup-memory"; 948 949 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 950 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 951 dma-names = "tx", 952 "rx"; 953 954 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 955 pinctrl-names = "default"; 956 957 #address-cells = <1>; 958 #size-cells = <0>; 959 960 status = "disabled"; 961 }; 962 963 i2c10: i2c@888000 { 964 compatible = "qcom,geni-i2c"; 965 reg = <0 0x00888000 0 0x4000>; 966 967 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 968 969 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 970 clock-names = "se"; 971 972 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 973 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 974 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 975 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 976 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 977 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 978 interconnect-names = "qup-core", 979 "qup-config", 980 "qup-memory"; 981 982 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 983 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 984 dma-names = "tx", 985 "rx"; 986 987 pinctrl-0 = <&qup_i2c10_data_clk>; 988 pinctrl-names = "default"; 989 990 #address-cells = <1>; 991 #size-cells = <0>; 992 993 status = "disabled"; 994 }; 995 996 spi10: spi@888000 { 997 compatible = "qcom,geni-spi"; 998 reg = <0 0x00888000 0 0x4000>; 999 1000 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1001 1002 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1003 clock-names = "se"; 1004 1005 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1006 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1007 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1008 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1009 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1010 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1011 interconnect-names = "qup-core", 1012 "qup-config", 1013 "qup-memory"; 1014 1015 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1016 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1017 dma-names = "tx", 1018 "rx"; 1019 1020 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1021 pinctrl-names = "default"; 1022 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 1026 status = "disabled"; 1027 }; 1028 1029 i2c11: i2c@88c000 { 1030 compatible = "qcom,geni-i2c"; 1031 reg = <0 0x0088c000 0 0x4000>; 1032 1033 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1034 1035 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1036 clock-names = "se"; 1037 1038 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1039 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1040 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1041 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1042 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1043 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1044 interconnect-names = "qup-core", 1045 "qup-config", 1046 "qup-memory"; 1047 1048 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1049 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1050 dma-names = "tx", 1051 "rx"; 1052 1053 pinctrl-0 = <&qup_i2c11_data_clk>; 1054 pinctrl-names = "default"; 1055 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 1059 status = "disabled"; 1060 }; 1061 1062 spi11: spi@88c000 { 1063 compatible = "qcom,geni-spi"; 1064 reg = <0 0x0088c000 0 0x4000>; 1065 1066 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1067 1068 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1069 clock-names = "se"; 1070 1071 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1072 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1073 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1074 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1075 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1076 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1077 interconnect-names = "qup-core", 1078 "qup-config", 1079 "qup-memory"; 1080 1081 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1082 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1083 dma-names = "tx", 1084 "rx"; 1085 1086 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1087 pinctrl-names = "default"; 1088 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 1092 status = "disabled"; 1093 }; 1094 1095 i2c12: i2c@890000 { 1096 compatible = "qcom,geni-i2c"; 1097 reg = <0 0x00890000 0 0x4000>; 1098 1099 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1100 1101 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1102 clock-names = "se"; 1103 1104 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1105 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1106 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1107 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1108 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1109 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1110 interconnect-names = "qup-core", 1111 "qup-config", 1112 "qup-memory"; 1113 1114 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1115 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1116 dma-names = "tx", 1117 "rx"; 1118 1119 pinctrl-0 = <&qup_i2c12_data_clk>; 1120 pinctrl-names = "default"; 1121 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 1125 status = "disabled"; 1126 }; 1127 1128 spi12: spi@890000 { 1129 compatible = "qcom,geni-spi"; 1130 reg = <0 0x00890000 0 0x4000>; 1131 1132 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1133 1134 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1135 clock-names = "se"; 1136 1137 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1138 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1139 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1140 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1141 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1142 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1143 interconnect-names = "qup-core", 1144 "qup-config", 1145 "qup-memory"; 1146 1147 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1148 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1149 dma-names = "tx", 1150 "rx"; 1151 1152 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1153 pinctrl-names = "default"; 1154 1155 #address-cells = <1>; 1156 #size-cells = <0>; 1157 1158 status = "disabled"; 1159 }; 1160 1161 i2c13: i2c@894000 { 1162 compatible = "qcom,geni-i2c"; 1163 reg = <0 0x00894000 0 0x4000>; 1164 1165 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1166 1167 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1168 clock-names = "se"; 1169 1170 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1171 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1172 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1173 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1174 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1176 interconnect-names = "qup-core", 1177 "qup-config", 1178 "qup-memory"; 1179 1180 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1181 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1182 dma-names = "tx", 1183 "rx"; 1184 1185 pinctrl-0 = <&qup_i2c13_data_clk>; 1186 pinctrl-names = "default"; 1187 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 1191 status = "disabled"; 1192 }; 1193 1194 spi13: spi@894000 { 1195 compatible = "qcom,geni-spi"; 1196 reg = <0 0x00894000 0 0x4000>; 1197 1198 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1199 1200 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1201 clock-names = "se"; 1202 1203 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1204 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1205 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1206 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1207 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1208 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1209 interconnect-names = "qup-core", 1210 "qup-config", 1211 "qup-memory"; 1212 1213 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1214 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1215 dma-names = "tx", 1216 "rx"; 1217 1218 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1219 pinctrl-names = "default"; 1220 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 1224 status = "disabled"; 1225 }; 1226 1227 uart14: serial@898000 { 1228 compatible = "qcom,geni-uart"; 1229 reg = <0 0x00898000 0 0x4000>; 1230 1231 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1232 1233 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1234 clock-names = "se"; 1235 1236 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1237 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1238 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1239 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1240 interconnect-names = "qup-core", 1241 "qup-config"; 1242 1243 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1244 pinctrl-names = "default"; 1245 1246 status = "disabled"; 1247 }; 1248 1249 uart15: serial@89c000 { 1250 compatible = "qcom,geni-debug-uart"; 1251 reg = <0 0x0089c000 0 0x4000>; 1252 1253 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1254 1255 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1256 clock-names = "se"; 1257 1258 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1259 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1260 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1261 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1262 interconnect-names = "qup-core", 1263 "qup-config"; 1264 1265 pinctrl-0 = <&qup_uart15_default>; 1266 pinctrl-names = "default"; 1267 1268 status = "disabled"; 1269 }; 1270 }; 1271 1272 i2c_master_hub_0: geniqup@9c0000 { 1273 compatible = "qcom,geni-se-i2c-master-hub"; 1274 reg = <0 0x009c0000 0 0x2000>; 1275 1276 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1277 clock-names = "s-ahb"; 1278 1279 #address-cells = <2>; 1280 #size-cells = <2>; 1281 ranges; 1282 1283 status = "disabled"; 1284 1285 i2c_hub_0: i2c@980000 { 1286 compatible = "qcom,geni-i2c-master-hub"; 1287 reg = <0 0x00980000 0 0x4000>; 1288 1289 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1290 1291 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1292 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1293 clock-names = "se", 1294 "core"; 1295 1296 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1297 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1298 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1299 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1300 interconnect-names = "qup-core", 1301 "qup-config"; 1302 1303 pinctrl-0 = <&hub_i2c0_data_clk>; 1304 pinctrl-names = "default"; 1305 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 1309 status = "disabled"; 1310 }; 1311 1312 i2c_hub_1: i2c@984000 { 1313 compatible = "qcom,geni-i2c-master-hub"; 1314 reg = <0 0x00984000 0 0x4000>; 1315 1316 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1317 1318 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1319 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1320 clock-names = "se", 1321 "core"; 1322 1323 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1324 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1325 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1326 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1327 interconnect-names = "qup-core", 1328 "qup-config"; 1329 1330 pinctrl-0 = <&hub_i2c1_data_clk>; 1331 pinctrl-names = "default"; 1332 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 1336 status = "disabled"; 1337 }; 1338 1339 i2c_hub_2: i2c@988000 { 1340 compatible = "qcom,geni-i2c-master-hub"; 1341 reg = <0 0x00988000 0 0x4000>; 1342 1343 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1344 1345 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1346 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1347 clock-names = "se", 1348 "core"; 1349 1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1351 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1352 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1353 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1354 interconnect-names = "qup-core", 1355 "qup-config"; 1356 1357 pinctrl-0 = <&hub_i2c2_data_clk>; 1358 pinctrl-names = "default"; 1359 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 1363 status = "disabled"; 1364 }; 1365 1366 i2c_hub_3: i2c@98c000 { 1367 compatible = "qcom,geni-i2c-master-hub"; 1368 reg = <0 0x0098c000 0 0x4000>; 1369 1370 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1371 1372 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1373 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1374 clock-names = "se", 1375 "core"; 1376 1377 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1378 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1379 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1380 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1381 interconnect-names = "qup-core", 1382 "qup-config"; 1383 1384 pinctrl-0 = <&hub_i2c3_data_clk>; 1385 pinctrl-names = "default"; 1386 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 1390 status = "disabled"; 1391 }; 1392 1393 i2c_hub_4: i2c@990000 { 1394 compatible = "qcom,geni-i2c-master-hub"; 1395 reg = <0 0x00990000 0 0x4000>; 1396 1397 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1398 1399 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1400 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1401 clock-names = "se", 1402 "core"; 1403 1404 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1405 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1406 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1407 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1408 interconnect-names = "qup-core", 1409 "qup-config"; 1410 1411 pinctrl-0 = <&hub_i2c4_data_clk>; 1412 pinctrl-names = "default"; 1413 1414 #address-cells = <1>; 1415 #size-cells = <0>; 1416 1417 status = "disabled"; 1418 }; 1419 1420 i2c_hub_5: i2c@994000 { 1421 compatible = "qcom,geni-i2c-master-hub"; 1422 reg = <0 0x00994000 0 0x4000>; 1423 1424 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1425 1426 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1427 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1428 clock-names = "se", 1429 "core"; 1430 1431 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1432 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1433 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1434 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1435 interconnect-names = "qup-core", 1436 "qup-config"; 1437 1438 pinctrl-0 = <&hub_i2c5_data_clk>; 1439 pinctrl-names = "default"; 1440 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 1444 status = "disabled"; 1445 }; 1446 1447 i2c_hub_6: i2c@998000 { 1448 compatible = "qcom,geni-i2c-master-hub"; 1449 reg = <0 0x00998000 0 0x4000>; 1450 1451 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1452 1453 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1454 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1455 clock-names = "se", 1456 "core"; 1457 1458 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1459 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1460 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1461 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1462 interconnect-names = "qup-core", 1463 "qup-config"; 1464 1465 pinctrl-0 = <&hub_i2c6_data_clk>; 1466 pinctrl-names = "default"; 1467 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 1471 status = "disabled"; 1472 }; 1473 1474 i2c_hub_7: i2c@99c000 { 1475 compatible = "qcom,geni-i2c-master-hub"; 1476 reg = <0 0x0099c000 0 0x4000>; 1477 1478 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1479 1480 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1481 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1482 clock-names = "se", 1483 "core"; 1484 1485 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1486 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1487 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1488 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1489 interconnect-names = "qup-core", 1490 "qup-config"; 1491 1492 pinctrl-0 = <&hub_i2c7_data_clk>; 1493 pinctrl-names = "default"; 1494 1495 #address-cells = <1>; 1496 #size-cells = <0>; 1497 1498 status = "disabled"; 1499 }; 1500 1501 i2c_hub_8: i2c@9a0000 { 1502 compatible = "qcom,geni-i2c-master-hub"; 1503 reg = <0 0x009a0000 0 0x4000>; 1504 1505 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1506 1507 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1508 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1509 clock-names = "se", 1510 "core"; 1511 1512 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1513 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1514 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1515 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1516 interconnect-names = "qup-core", 1517 "qup-config"; 1518 1519 pinctrl-0 = <&hub_i2c8_data_clk>; 1520 pinctrl-names = "default"; 1521 1522 #address-cells = <1>; 1523 #size-cells = <0>; 1524 1525 status = "disabled"; 1526 }; 1527 1528 i2c_hub_9: i2c@9a4000 { 1529 compatible = "qcom,geni-i2c-master-hub"; 1530 reg = <0 0x009a4000 0 0x4000>; 1531 1532 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1533 1534 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1535 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1536 clock-names = "se", 1537 "core"; 1538 1539 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1540 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1541 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1542 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1543 interconnect-names = "qup-core", 1544 "qup-config"; 1545 1546 pinctrl-0 = <&hub_i2c9_data_clk>; 1547 pinctrl-names = "default"; 1548 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 1552 status = "disabled"; 1553 }; 1554 }; 1555 1556 gpi_dma1: dma-controller@a00000 { 1557 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 1558 reg = <0 0x00a00000 0 0x60000>; 1559 1560 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1572 1573 dma-channels = <12>; 1574 dma-channel-mask = <0xc>; 1575 #dma-cells = <3>; 1576 1577 iommus = <&apps_smmu 0xb6 0>; 1578 dma-coherent; 1579 1580 status = "disabled"; 1581 }; 1582 1583 qupv3_id_0: geniqup@ac0000 { 1584 compatible = "qcom,geni-se-qup"; 1585 reg = <0 0x00ac0000 0 0x2000>; 1586 1587 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1588 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1589 clock-names = "m-ahb", 1590 "s-ahb"; 1591 1592 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1593 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 1594 interconnect-names = "qup-core"; 1595 1596 iommus = <&apps_smmu 0xa3 0>; 1597 1598 dma-coherent; 1599 1600 #address-cells = <2>; 1601 #size-cells = <2>; 1602 ranges; 1603 1604 status = "disabled"; 1605 1606 i2c0: i2c@a80000 { 1607 compatible = "qcom,geni-i2c"; 1608 reg = <0 0x00a80000 0 0x4000>; 1609 1610 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1611 1612 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1613 clock-names = "se"; 1614 1615 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1616 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1617 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1618 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1619 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1620 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1621 interconnect-names = "qup-core", 1622 "qup-config", 1623 "qup-memory"; 1624 1625 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1626 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1627 dma-names = "tx", 1628 "rx"; 1629 1630 pinctrl-0 = <&qup_i2c0_data_clk>; 1631 pinctrl-names = "default"; 1632 1633 #address-cells = <1>; 1634 #size-cells = <0>; 1635 1636 status = "disabled"; 1637 }; 1638 1639 spi0: spi@a80000 { 1640 compatible = "qcom,geni-spi"; 1641 reg = <0 0x00a80000 0 0x4000>; 1642 1643 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1644 1645 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1646 clock-names = "se"; 1647 1648 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1649 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1650 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1651 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1652 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1653 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1654 interconnect-names = "qup-core", 1655 "qup-config", 1656 "qup-memory"; 1657 1658 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1659 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1660 dma-names = "tx", 1661 "rx"; 1662 1663 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1664 pinctrl-names = "default"; 1665 1666 #address-cells = <1>; 1667 #size-cells = <0>; 1668 1669 status = "disabled"; 1670 }; 1671 1672 i2c1: i2c@a84000 { 1673 compatible = "qcom,geni-i2c"; 1674 reg = <0 0x00a84000 0 0x4000>; 1675 1676 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1677 1678 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1679 clock-names = "se"; 1680 1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1682 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1683 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1684 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1685 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1686 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1687 interconnect-names = "qup-core", 1688 "qup-config", 1689 "qup-memory"; 1690 1691 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1692 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1693 dma-names = "tx", 1694 "rx"; 1695 1696 pinctrl-0 = <&qup_i2c1_data_clk>; 1697 pinctrl-names = "default"; 1698 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 1702 status = "disabled"; 1703 }; 1704 1705 spi1: spi@a84000 { 1706 compatible = "qcom,geni-spi"; 1707 reg = <0 0x00a84000 0 0x4000>; 1708 1709 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1710 1711 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1712 clock-names = "se"; 1713 1714 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1715 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1716 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1717 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1718 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1719 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1720 interconnect-names = "qup-core", 1721 "qup-config", 1722 "qup-memory"; 1723 1724 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1725 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1726 dma-names = "tx", 1727 "rx"; 1728 1729 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1730 pinctrl-names = "default"; 1731 1732 #address-cells = <1>; 1733 #size-cells = <0>; 1734 1735 status = "disabled"; 1736 }; 1737 1738 i2c2: i2c@a88000 { 1739 compatible = "qcom,geni-i2c"; 1740 reg = <0 0x00a88000 0 0x4000>; 1741 1742 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1743 1744 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1745 clock-names = "se"; 1746 1747 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1748 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1749 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1750 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1751 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1752 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1753 interconnect-names = "qup-core", 1754 "qup-config", 1755 "qup-memory"; 1756 1757 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1758 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1759 dma-names = "tx", 1760 "rx"; 1761 1762 pinctrl-0 = <&qup_i2c2_data_clk>; 1763 pinctrl-names = "default"; 1764 1765 #address-cells = <1>; 1766 #size-cells = <0>; 1767 1768 status = "disabled"; 1769 }; 1770 1771 spi2: spi@a88000 { 1772 compatible = "qcom,geni-spi"; 1773 reg = <0 0x00a88000 0 0x4000>; 1774 1775 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1776 1777 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1778 clock-names = "se"; 1779 1780 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1781 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1782 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1783 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1784 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1785 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1786 interconnect-names = "qup-core", 1787 "qup-config", 1788 "qup-memory"; 1789 1790 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1791 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1792 dma-names = "tx", 1793 "rx"; 1794 1795 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1796 pinctrl-names = "default"; 1797 1798 #address-cells = <1>; 1799 #size-cells = <0>; 1800 1801 status = "disabled"; 1802 }; 1803 1804 i2c3: i2c@a8c000 { 1805 compatible = "qcom,geni-i2c"; 1806 reg = <0 0x00a8c000 0 0x4000>; 1807 1808 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1809 1810 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1811 clock-names = "se"; 1812 1813 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1814 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1815 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1816 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1817 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1818 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1819 interconnect-names = "qup-core", 1820 "qup-config", 1821 "qup-memory"; 1822 1823 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1824 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1825 dma-names = "tx", 1826 "rx"; 1827 1828 pinctrl-0 = <&qup_i2c3_data_clk>; 1829 pinctrl-names = "default"; 1830 1831 #address-cells = <1>; 1832 #size-cells = <0>; 1833 1834 status = "disabled"; 1835 }; 1836 1837 spi3: spi@a8c000 { 1838 compatible = "qcom,geni-spi"; 1839 reg = <0 0x00a8c000 0 0x4000>; 1840 1841 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1842 1843 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1844 clock-names = "se"; 1845 1846 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1847 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1848 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1849 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1850 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1851 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1852 interconnect-names = "qup-core", 1853 "qup-config", 1854 "qup-memory"; 1855 1856 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1857 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1858 dma-names = "tx", 1859 "rx"; 1860 1861 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1862 pinctrl-names = "default"; 1863 1864 #address-cells = <1>; 1865 #size-cells = <0>; 1866 1867 status = "disabled"; 1868 }; 1869 1870 i2c4: i2c@a90000 { 1871 compatible = "qcom,geni-i2c"; 1872 reg = <0 0x00a90000 0 0x4000>; 1873 1874 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1875 1876 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1877 clock-names = "se"; 1878 1879 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1880 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1881 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1882 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1883 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1884 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1885 interconnect-names = "qup-core", 1886 "qup-config", 1887 "qup-memory"; 1888 1889 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1890 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1891 dma-names = "tx", 1892 "rx"; 1893 1894 pinctrl-0 = <&qup_i2c4_data_clk>; 1895 pinctrl-names = "default"; 1896 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 1900 status = "disabled"; 1901 }; 1902 1903 spi4: spi@a90000 { 1904 compatible = "qcom,geni-spi"; 1905 reg = <0 0x00a90000 0 0x4000>; 1906 1907 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1908 1909 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1910 clock-names = "se"; 1911 1912 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1913 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1914 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1915 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1916 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1917 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1918 interconnect-names = "qup-core", 1919 "qup-config", 1920 "qup-memory"; 1921 1922 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1923 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1924 dma-names = "tx", 1925 "rx"; 1926 1927 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1928 pinctrl-names = "default"; 1929 1930 #address-cells = <1>; 1931 #size-cells = <0>; 1932 1933 status = "disabled"; 1934 }; 1935 1936 i2c5: i2c@a94000 { 1937 compatible = "qcom,geni-i2c"; 1938 reg = <0 0x00a94000 0 0x4000>; 1939 1940 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1941 1942 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1943 clock-names = "se"; 1944 1945 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1946 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1947 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1948 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1949 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1950 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1951 interconnect-names = "qup-core", 1952 "qup-config", 1953 "qup-memory"; 1954 1955 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1956 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1957 dma-names = "tx", 1958 "rx"; 1959 1960 pinctrl-0 = <&qup_i2c5_data_clk>; 1961 pinctrl-names = "default"; 1962 1963 #address-cells = <1>; 1964 #size-cells = <0>; 1965 1966 status = "disabled"; 1967 }; 1968 1969 spi5: spi@a94000 { 1970 compatible = "qcom,geni-spi"; 1971 reg = <0 0x00a94000 0 0x4000>; 1972 1973 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1974 1975 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1976 clock-names = "se"; 1977 1978 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1979 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1980 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1981 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1982 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1983 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1984 interconnect-names = "qup-core", 1985 "qup-config", 1986 "qup-memory"; 1987 1988 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1989 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1990 dma-names = "tx", 1991 "rx"; 1992 1993 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1994 pinctrl-names = "default"; 1995 1996 #address-cells = <1>; 1997 #size-cells = <0>; 1998 1999 status = "disabled"; 2000 }; 2001 2002 i2c6: i2c@a98000 { 2003 compatible = "qcom,geni-i2c"; 2004 reg = <0 0x00a98000 0 0x4000>; 2005 2006 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 2007 2008 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2009 clock-names = "se"; 2010 2011 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2012 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2013 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2014 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2015 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2016 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2017 interconnect-names = "qup-core", 2018 "qup-config", 2019 "qup-memory"; 2020 2021 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2022 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2023 dma-names = "tx", 2024 "rx"; 2025 2026 pinctrl-0 = <&qup_i2c6_data_clk>; 2027 pinctrl-names = "default"; 2028 2029 #address-cells = <1>; 2030 #size-cells = <0>; 2031 2032 status = "disabled"; 2033 }; 2034 2035 spi6: spi@a98000 { 2036 compatible = "qcom,geni-spi"; 2037 reg = <0 0x00a98000 0 0x4000>; 2038 2039 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 2040 2041 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2042 clock-names = "se"; 2043 2044 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2045 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2046 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2047 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2048 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2049 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2050 interconnect-names = "qup-core", 2051 "qup-config", 2052 "qup-memory"; 2053 2054 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2055 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2056 dma-names = "tx", 2057 "rx"; 2058 2059 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2060 pinctrl-names = "default"; 2061 2062 #address-cells = <1>; 2063 #size-cells = <0>; 2064 2065 status = "disabled"; 2066 }; 2067 2068 i2c7: i2c@a9c000 { 2069 compatible = "qcom,geni-i2c"; 2070 reg = <0 0x00a9c000 0 0x4000>; 2071 2072 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 2073 2074 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2075 clock-names = "se"; 2076 2077 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2078 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2079 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2080 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2081 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2082 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2083 interconnect-names = "qup-core", 2084 "qup-config", 2085 "qup-memory"; 2086 2087 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2088 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2089 dma-names = "tx", 2090 "rx"; 2091 2092 pinctrl-0 = <&qup_i2c7_data_clk>; 2093 pinctrl-names = "default"; 2094 2095 #address-cells = <1>; 2096 #size-cells = <0>; 2097 2098 status = "disabled"; 2099 }; 2100 2101 spi7: spi@a9c000 { 2102 compatible = "qcom,geni-spi"; 2103 reg = <0 0x00a9c000 0 0x4000>; 2104 2105 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 2106 2107 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2108 clock-names = "se"; 2109 2110 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2111 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2112 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2113 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2114 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2115 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2116 interconnect-names = "qup-core", 2117 "qup-config", 2118 "qup-memory"; 2119 2120 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2121 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2122 dma-names = "tx", 2123 "rx"; 2124 2125 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2126 pinctrl-names = "default"; 2127 2128 #address-cells = <1>; 2129 #size-cells = <0>; 2130 2131 status = "disabled"; 2132 }; 2133 }; 2134 2135 cnoc_main: interconnect@1500000 { 2136 compatible = "qcom,sm8650-cnoc-main"; 2137 reg = <0 0x01500000 0 0x14080>; 2138 2139 qcom,bcm-voters = <&apps_bcm_voter>; 2140 2141 #interconnect-cells = <2>; 2142 }; 2143 2144 config_noc: interconnect@1600000 { 2145 compatible = "qcom,sm8650-config-noc"; 2146 reg = <0 0x01600000 0 0x6200>; 2147 2148 qcom,bcm-voters = <&apps_bcm_voter>; 2149 2150 #interconnect-cells = <2>; 2151 }; 2152 2153 system_noc: interconnect@1680000 { 2154 compatible = "qcom,sm8650-system-noc"; 2155 reg = <0 0x01680000 0 0x1d080>; 2156 2157 qcom,bcm-voters = <&apps_bcm_voter>; 2158 2159 #interconnect-cells = <2>; 2160 }; 2161 2162 pcie_noc: interconnect@16c0000 { 2163 compatible = "qcom,sm8650-pcie-anoc"; 2164 reg = <0 0x016c0000 0 0x12200>; 2165 2166 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2167 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 2168 2169 qcom,bcm-voters = <&apps_bcm_voter>; 2170 2171 #interconnect-cells = <2>; 2172 }; 2173 2174 aggre1_noc: interconnect@16e0000 { 2175 compatible = "qcom,sm8650-aggre1-noc"; 2176 reg = <0 0x016e0000 0 0x16400>; 2177 2178 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2179 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2180 2181 qcom,bcm-voters = <&apps_bcm_voter>; 2182 2183 #interconnect-cells = <2>; 2184 }; 2185 2186 aggre2_noc: interconnect@1700000 { 2187 compatible = "qcom,sm8650-aggre2-noc"; 2188 reg = <0 0x01700000 0 0x1e400>; 2189 2190 clocks = <&rpmhcc RPMH_IPA_CLK>; 2191 2192 qcom,bcm-voters = <&apps_bcm_voter>; 2193 2194 #interconnect-cells = <2>; 2195 }; 2196 2197 mmss_noc: interconnect@1780000 { 2198 compatible = "qcom,sm8650-mmss-noc"; 2199 reg = <0 0x01780000 0 0x5b800>; 2200 2201 qcom,bcm-voters = <&apps_bcm_voter>; 2202 2203 #interconnect-cells = <2>; 2204 }; 2205 2206 rng: rng@10c3000 { 2207 compatible = "qcom,sm8650-trng", "qcom,trng"; 2208 reg = <0 0x010c3000 0 0x1000>; 2209 }; 2210 2211 pcie0: pci@1c00000 { 2212 device_type = "pci"; 2213 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 2214 reg = <0 0x01c00000 0 0x3000>, 2215 <0 0x60000000 0 0xf1d>, 2216 <0 0x60000f20 0 0xa8>, 2217 <0 0x60001000 0 0x1000>, 2218 <0 0x60100000 0 0x100000>; 2219 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2220 2221 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2223 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2228 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2229 interrupt-names = "msi0", 2230 "msi1", 2231 "msi2", 2232 "msi3", 2233 "msi4", 2234 "msi5", 2235 "msi6", 2236 "msi7"; 2237 2238 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2239 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2240 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2241 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2242 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2243 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2244 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2245 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2246 clock-names = "aux", 2247 "cfg", 2248 "bus_master", 2249 "bus_slave", 2250 "slave_q2a", 2251 "ddrss_sf_tbu", 2252 "noc_aggr", 2253 "cnoc_sf_axi"; 2254 2255 resets = <&gcc GCC_PCIE_0_BCR>; 2256 reset-names = "pci"; 2257 2258 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2259 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2260 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2261 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 2262 interconnect-names = "pcie-mem", 2263 "cpu-pcie"; 2264 2265 power-domains = <&gcc PCIE_0_GDSC>; 2266 2267 iommu-map = <0 &apps_smmu 0x1400 0x1>, 2268 <0x100 &apps_smmu 0x1401 0x1>; 2269 2270 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 2271 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 2272 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 2273 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 2274 interrupt-map-mask = <0 0 0 0x7>; 2275 #interrupt-cells = <1>; 2276 2277 msi-map = <0x0 &gic_its 0x1400 0x1>, 2278 <0x100 &gic_its 0x1401 0x1>; 2279 msi-map-mask = <0xff00>; 2280 2281 linux,pci-domain = <0>; 2282 num-lanes = <2>; 2283 bus-range = <0 0xff>; 2284 2285 phys = <&pcie0_phy>; 2286 phy-names = "pciephy"; 2287 2288 #address-cells = <3>; 2289 #size-cells = <2>; 2290 ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, 2291 <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>; 2292 2293 dma-coherent; 2294 2295 status = "disabled"; 2296 2297 pcie@0 { 2298 device_type = "pci"; 2299 reg = <0x0 0x0 0x0 0x0 0x0>; 2300 bus-range = <0x01 0xff>; 2301 2302 #address-cells = <3>; 2303 #size-cells = <2>; 2304 ranges; 2305 }; 2306 }; 2307 2308 pcie0_phy: phy@1c06000 { 2309 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy"; 2310 reg = <0 0x01c06000 0 0x2000>; 2311 2312 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2313 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2314 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 2315 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2316 <&gcc GCC_PCIE_0_PIPE_CLK>; 2317 clock-names = "aux", 2318 "cfg_ahb", 2319 "ref", 2320 "rchng", 2321 "pipe"; 2322 2323 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2324 assigned-clock-rates = <100000000>; 2325 2326 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2327 reset-names = "phy"; 2328 2329 power-domains = <&gcc PCIE_0_PHY_GDSC>; 2330 2331 #clock-cells = <0>; 2332 clock-output-names = "pcie0_pipe_clk"; 2333 2334 #phy-cells = <0>; 2335 2336 status = "disabled"; 2337 }; 2338 2339 pcie1: pci@1c08000 { 2340 device_type = "pci"; 2341 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 2342 reg = <0 0x01c08000 0 0x3000>, 2343 <0 0x40000000 0 0xf1d>, 2344 <0 0x40000f20 0 0xa8>, 2345 <0 0x40001000 0 0x1000>, 2346 <0 0x40100000 0 0x100000>; 2347 reg-names = "parf", 2348 "dbi", 2349 "elbi", 2350 "atu", 2351 "config"; 2352 2353 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2354 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2355 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2356 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2357 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2358 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2359 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2360 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2361 interrupt-names = "msi0", 2362 "msi1", 2363 "msi2", 2364 "msi3", 2365 "msi4", 2366 "msi5", 2367 "msi6", 2368 "msi7"; 2369 2370 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2371 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2372 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2373 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2374 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2375 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2376 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2377 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2378 clock-names = "aux", 2379 "cfg", 2380 "bus_master", 2381 "bus_slave", 2382 "slave_q2a", 2383 "ddrss_sf_tbu", 2384 "noc_aggr", 2385 "cnoc_sf_axi"; 2386 2387 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2388 assigned-clock-rates = <19200000>; 2389 2390 resets = <&gcc GCC_PCIE_1_BCR>, 2391 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2392 reset-names = "pci", 2393 "link_down"; 2394 2395 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2396 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2397 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2398 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; 2399 interconnect-names = "pcie-mem", 2400 "cpu-pcie"; 2401 2402 power-domains = <&gcc PCIE_1_GDSC>; 2403 2404 iommu-map = <0 &apps_smmu 0x1480 0x1>, 2405 <0x100 &apps_smmu 0x1481 0x1>; 2406 2407 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2408 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2409 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2410 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2411 interrupt-map-mask = <0 0 0 0x7>; 2412 #interrupt-cells = <1>; 2413 2414 msi-map = <0x0 &gic_its 0x1480 0x1>, 2415 <0x100 &gic_its 0x1481 0x1>; 2416 msi-map-mask = <0xff00>; 2417 2418 linux,pci-domain = <1>; 2419 num-lanes = <2>; 2420 bus-range = <0 0xff>; 2421 2422 phys = <&pcie1_phy>; 2423 phy-names = "pciephy"; 2424 2425 dma-coherent; 2426 2427 #address-cells = <3>; 2428 #size-cells = <2>; 2429 ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, 2430 <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; 2431 2432 status = "disabled"; 2433 2434 pcie@0 { 2435 device_type = "pci"; 2436 reg = <0x0 0x0 0x0 0x0 0x0>; 2437 bus-range = <0x01 0xff>; 2438 2439 #address-cells = <3>; 2440 #size-cells = <2>; 2441 ranges; 2442 }; 2443 }; 2444 2445 pcie1_phy: phy@1c0e000 { 2446 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy"; 2447 reg = <0 0x01c0e000 0 0x2000>; 2448 2449 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2450 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2451 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 2452 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2453 <&gcc GCC_PCIE_1_PIPE_CLK>; 2454 clock-names = "aux", 2455 "cfg_ahb", 2456 "ref", 2457 "rchng", 2458 "pipe"; 2459 2460 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2461 assigned-clock-rates = <100000000>; 2462 2463 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 2464 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 2465 reset-names = "phy", 2466 "phy_nocsr"; 2467 2468 power-domains = <&gcc PCIE_1_PHY_GDSC>; 2469 2470 #clock-cells = <0>; 2471 clock-output-names = "pcie1_pipe_clk"; 2472 2473 #phy-cells = <0>; 2474 2475 status = "disabled"; 2476 }; 2477 2478 cryptobam: dma-controller@1dc4000 { 2479 compatible = "qcom,bam-v1.7.0"; 2480 reg = <0 0x01dc4000 0 0x28000>; 2481 2482 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2483 2484 #dma-cells = <1>; 2485 2486 iommus = <&apps_smmu 0x480 0>, 2487 <&apps_smmu 0x481 0>; 2488 2489 qcom,ee = <0>; 2490 qcom,controlled-remotely; 2491 }; 2492 2493 crypto: crypto@1dfa000 { 2494 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; 2495 reg = <0 0x01dfa000 0 0x6000>; 2496 2497 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 2498 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2499 interconnect-names = "memory"; 2500 2501 dmas = <&cryptobam 4>, <&cryptobam 5>; 2502 dma-names = "rx", "tx"; 2503 2504 iommus = <&apps_smmu 0x480 0>, 2505 <&apps_smmu 0x481 0>; 2506 }; 2507 2508 ufs_mem_phy: phy@1d80000 { 2509 compatible = "qcom,sm8650-qmp-ufs-phy"; 2510 reg = <0 0x01d80000 0 0x2000>; 2511 2512 clocks = <&rpmhcc RPMH_CXO_CLK>, 2513 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2514 <&tcsr TCSR_UFS_CLKREF_EN>; 2515 clock-names = "ref", 2516 "ref_aux", 2517 "qref"; 2518 2519 resets = <&ufs_mem_hc 0>; 2520 reset-names = "ufsphy"; 2521 2522 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 2523 2524 #clock-cells = <1>; 2525 #phy-cells = <0>; 2526 2527 status = "disabled"; 2528 }; 2529 2530 ufs_mem_hc: ufs@1d84000 { 2531 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2532 reg = <0 0x01d84000 0 0x3000>; 2533 2534 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2535 2536 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2537 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2538 <&gcc GCC_UFS_PHY_AHB_CLK>, 2539 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2540 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 2541 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2542 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2543 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2544 clock-names = "core_clk", 2545 "bus_aggr_clk", 2546 "iface_clk", 2547 "core_clk_unipro", 2548 "ref_clk", 2549 "tx_lane0_sync_clk", 2550 "rx_lane0_sync_clk", 2551 "rx_lane1_sync_clk"; 2552 freq-table-hz = <100000000 403000000>, 2553 <0 0>, 2554 <0 0>, 2555 <100000000 403000000>, 2556 <100000000 403000000>, 2557 <0 0>, 2558 <0 0>, 2559 <0 0>; 2560 2561 resets = <&gcc GCC_UFS_PHY_BCR>; 2562 reset-names = "rst"; 2563 2564 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2565 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2566 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2567 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2568 interconnect-names = "ufs-ddr", 2569 "cpu-ufs"; 2570 2571 power-domains = <&gcc UFS_PHY_GDSC>; 2572 required-opps = <&rpmhpd_opp_nom>; 2573 2574 iommus = <&apps_smmu 0x60 0>; 2575 2576 lanes-per-direction = <2>; 2577 qcom,ice = <&ice>; 2578 2579 phys = <&ufs_mem_phy>; 2580 phy-names = "ufsphy"; 2581 2582 #reset-cells = <1>; 2583 2584 status = "disabled"; 2585 }; 2586 2587 ice: crypto@1d88000 { 2588 compatible = "qcom,sm8650-inline-crypto-engine", 2589 "qcom,inline-crypto-engine"; 2590 reg = <0 0x01d88000 0 0x8000>; 2591 2592 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2593 }; 2594 2595 tcsr_mutex: hwlock@1f40000 { 2596 compatible = "qcom,tcsr-mutex"; 2597 reg = <0 0x01f40000 0 0x20000>; 2598 2599 #hwlock-cells = <1>; 2600 }; 2601 2602 tcsr: clock-controller@1fc0000 { 2603 compatible = "qcom,sm8650-tcsr", "syscon"; 2604 reg = <0 0x01fc0000 0 0xa0000>; 2605 2606 clocks = <&rpmhcc RPMH_CXO_CLK>; 2607 2608 #clock-cells = <1>; 2609 #reset-cells = <1>; 2610 }; 2611 2612 gpu: gpu@3d00000 { 2613 compatible = "qcom,adreno-43051401", "qcom,adreno"; 2614 reg = <0x0 0x03d00000 0x0 0x40000>, 2615 <0x0 0x03d9e000 0x0 0x2000>, 2616 <0x0 0x03d61000 0x0 0x800>; 2617 reg-names = "kgsl_3d0_reg_memory", 2618 "cx_mem", 2619 "cx_dbgc"; 2620 2621 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2622 2623 iommus = <&adreno_smmu 0 0x0>, 2624 <&adreno_smmu 1 0x0>; 2625 2626 operating-points-v2 = <&gpu_opp_table>; 2627 2628 qcom,gmu = <&gmu>; 2629 2630 status = "disabled"; 2631 2632 zap-shader { 2633 memory-region = <&gpu_micro_code_mem>; 2634 }; 2635 2636 /* Speedbin needs more work on A740+, keep only lower freqs */ 2637 gpu_opp_table: opp-table { 2638 compatible = "operating-points-v2"; 2639 2640 opp-231000000 { 2641 opp-hz = /bits/ 64 <231000000>; 2642 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 2643 }; 2644 2645 opp-310000000 { 2646 opp-hz = /bits/ 64 <310000000>; 2647 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2648 }; 2649 2650 opp-366000000 { 2651 opp-hz = /bits/ 64 <366000000>; 2652 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 2653 }; 2654 2655 opp-422000000 { 2656 opp-hz = /bits/ 64 <422000000>; 2657 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2658 }; 2659 2660 opp-500000000 { 2661 opp-hz = /bits/ 64 <500000000>; 2662 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2663 }; 2664 2665 opp-578000000 { 2666 opp-hz = /bits/ 64 <578000000>; 2667 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2668 }; 2669 2670 opp-629000000 { 2671 opp-hz = /bits/ 64 <629000000>; 2672 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2673 }; 2674 2675 opp-680000000 { 2676 opp-hz = /bits/ 64 <680000000>; 2677 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2678 }; 2679 2680 opp-720000000 { 2681 opp-hz = /bits/ 64 <720000000>; 2682 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2683 }; 2684 2685 opp-770000000 { 2686 opp-hz = /bits/ 64 <770000000>; 2687 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2688 }; 2689 2690 opp-834000000 { 2691 opp-hz = /bits/ 64 <834000000>; 2692 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2693 }; 2694 }; 2695 }; 2696 2697 gmu: gmu@3d6a000 { 2698 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; 2699 reg = <0x0 0x03d6a000 0x0 0x35000>, 2700 <0x0 0x03d50000 0x0 0x10000>, 2701 <0x0 0x0b280000 0x0 0x10000>; 2702 reg-names = "gmu", "rscc", "gmu_pdc"; 2703 2704 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2705 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2706 interrupt-names = "hfi", "gmu"; 2707 2708 clocks = <&gpucc GPU_CC_AHB_CLK>, 2709 <&gpucc GPU_CC_CX_GMU_CLK>, 2710 <&gpucc GPU_CC_CXO_CLK>, 2711 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2712 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2713 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2714 <&gpucc GPU_CC_DEMET_CLK>; 2715 clock-names = "ahb", 2716 "gmu", 2717 "cxo", 2718 "axi", 2719 "memnoc", 2720 "hub", 2721 "demet"; 2722 2723 power-domains = <&gpucc GPU_CX_GDSC>, 2724 <&gpucc GPU_GX_GDSC>; 2725 power-domain-names = "cx", 2726 "gx"; 2727 2728 iommus = <&adreno_smmu 5 0x0>; 2729 2730 qcom,qmp = <&aoss_qmp>; 2731 2732 operating-points-v2 = <&gmu_opp_table>; 2733 2734 gmu_opp_table: opp-table { 2735 compatible = "operating-points-v2"; 2736 2737 opp-260000000 { 2738 opp-hz = /bits/ 64 <260000000>; 2739 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2740 }; 2741 2742 opp-625000000 { 2743 opp-hz = /bits/ 64 <625000000>; 2744 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2745 }; 2746 }; 2747 }; 2748 2749 gpucc: clock-controller@3d90000 { 2750 compatible = "qcom,sm8650-gpucc"; 2751 reg = <0 0x03d90000 0 0xa000>; 2752 2753 clocks = <&bi_tcxo_div2>, 2754 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2755 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2756 2757 #clock-cells = <1>; 2758 #reset-cells = <1>; 2759 #power-domain-cells = <1>; 2760 }; 2761 2762 adreno_smmu: iommu@3da0000 { 2763 compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", 2764 "qcom,smmu-500", "arm,mmu-500"; 2765 reg = <0x0 0x03da0000 0x0 0x40000>; 2766 #iommu-cells = <2>; 2767 #global-interrupts = <1>; 2768 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2769 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>, 2770 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2771 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2772 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2773 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2774 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2775 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2776 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2777 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2778 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2779 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2780 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2781 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2782 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2783 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2784 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2785 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2786 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2787 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2788 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2789 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2790 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2791 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2792 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2793 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 2794 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2795 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2796 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2797 <&gpucc GPU_CC_AHB_CLK>; 2798 clock-names = "hlos", 2799 "bus", 2800 "iface", 2801 "ahb"; 2802 power-domains = <&gpucc GPU_CX_GDSC>; 2803 dma-coherent; 2804 }; 2805 2806 ipa: ipa@3f40000 { 2807 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; 2808 2809 iommus = <&apps_smmu 0x4a0 0x0>, 2810 <&apps_smmu 0x4a2 0x0>; 2811 reg = <0 0x3f40000 0 0x10000>, 2812 <0 0x3f50000 0 0x5000>, 2813 <0 0x3e04000 0 0xfc000>; 2814 reg-names = "ipa-reg", 2815 "ipa-shared", 2816 "gsi"; 2817 2818 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2819 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2820 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2821 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2822 interrupt-names = "ipa", 2823 "gsi", 2824 "ipa-clock-query", 2825 "ipa-setup-ready"; 2826 2827 clocks = <&rpmhcc RPMH_IPA_CLK>; 2828 clock-names = "core"; 2829 2830 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2831 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2832 interconnect-names = "memory", 2833 "config"; 2834 2835 qcom,qmp = <&aoss_qmp>; 2836 2837 qcom,smem-states = <&ipa_smp2p_out 0>, 2838 <&ipa_smp2p_out 1>; 2839 qcom,smem-state-names = "ipa-clock-enabled-valid", 2840 "ipa-clock-enabled"; 2841 2842 status = "disabled"; 2843 }; 2844 2845 remoteproc_mpss: remoteproc@4080000 { 2846 compatible = "qcom,sm8650-mpss-pas"; 2847 reg = <0 0x04080000 0 0x4040>; 2848 2849 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2850 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2851 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2852 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2853 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2854 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2855 interrupt-names = "wdog", 2856 "fatal", 2857 "ready", 2858 "handover", 2859 "stop-ack", 2860 "shutdown-ack"; 2861 2862 clocks = <&rpmhcc RPMH_CXO_CLK>; 2863 clock-names = "xo"; 2864 2865 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 2866 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2867 2868 power-domains = <&rpmhpd RPMHPD_CX>, 2869 <&rpmhpd RPMHPD_MSS>; 2870 power-domain-names = "cx", 2871 "mss"; 2872 2873 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, 2874 <&mpss_dsm_mem>, <&mpss_dsm_mem_2>, 2875 <&qlink_logging_mem>; 2876 2877 qcom,qmp = <&aoss_qmp>; 2878 2879 qcom,smem-states = <&smp2p_modem_out 0>; 2880 qcom,smem-state-names = "stop"; 2881 2882 status = "disabled"; 2883 2884 glink-edge { 2885 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2886 IPCC_MPROC_SIGNAL_GLINK_QMP 2887 IRQ_TYPE_EDGE_RISING>; 2888 2889 mboxes = <&ipcc IPCC_CLIENT_MPSS 2890 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2891 2892 qcom,remote-pid = <1>; 2893 2894 label = "mpss"; 2895 }; 2896 }; 2897 2898 lpass_wsa2macro: codec@6aa0000 { 2899 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 2900 reg = <0 0x06aa0000 0 0x1000>; 2901 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2902 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2903 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2904 <&lpass_vamacro>; 2905 clock-names = "mclk", 2906 "macro", 2907 "dcodec", 2908 "fsgen"; 2909 2910 #clock-cells = <0>; 2911 clock-output-names = "wsa2-mclk"; 2912 #sound-dai-cells = <1>; 2913 }; 2914 2915 swr3: soundwire@6ab0000 { 2916 compatible = "qcom,soundwire-v2.0.0"; 2917 reg = <0 0x06ab0000 0 0x10000>; 2918 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2919 clocks = <&lpass_wsa2macro>; 2920 clock-names = "iface"; 2921 label = "WSA2"; 2922 2923 pinctrl-0 = <&wsa2_swr_active>; 2924 pinctrl-names = "default"; 2925 2926 qcom,din-ports = <4>; 2927 qcom,dout-ports = <9>; 2928 2929 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2930 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2931 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2932 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2933 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2934 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2935 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2936 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2937 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2938 2939 #address-cells = <2>; 2940 #size-cells = <0>; 2941 #sound-dai-cells = <1>; 2942 status = "disabled"; 2943 }; 2944 2945 lpass_rxmacro: codec@6ac0000 { 2946 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 2947 reg = <0 0x06ac0000 0 0x1000>; 2948 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2949 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2950 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2951 <&lpass_vamacro>; 2952 clock-names = "mclk", 2953 "macro", 2954 "dcodec", 2955 "fsgen"; 2956 2957 #clock-cells = <0>; 2958 clock-output-names = "mclk"; 2959 #sound-dai-cells = <1>; 2960 }; 2961 2962 swr1: soundwire@6ad0000 { 2963 compatible = "qcom,soundwire-v2.0.0"; 2964 reg = <0 0x06ad0000 0 0x10000>; 2965 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2966 clocks = <&lpass_rxmacro>; 2967 clock-names = "iface"; 2968 label = "RX"; 2969 2970 pinctrl-0 = <&rx_swr_active>; 2971 pinctrl-names = "default"; 2972 2973 qcom,din-ports = <0>; 2974 qcom,dout-ports = <11>; 2975 2976 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>; 2977 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>; 2978 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 2979 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>; 2980 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>; 2981 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>; 2982 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>; 2983 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>; 2984 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; 2985 2986 #address-cells = <2>; 2987 #size-cells = <0>; 2988 #sound-dai-cells = <1>; 2989 status = "disabled"; 2990 }; 2991 2992 lpass_txmacro: codec@6ae0000 { 2993 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 2994 reg = <0 0x06ae0000 0 0x1000>; 2995 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2996 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2997 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2998 <&lpass_vamacro>; 2999 clock-names = "mclk", 3000 "macro", 3001 "dcodec", 3002 "fsgen"; 3003 3004 #clock-cells = <0>; 3005 clock-output-names = "mclk"; 3006 #sound-dai-cells = <1>; 3007 }; 3008 3009 lpass_wsamacro: codec@6b00000 { 3010 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 3011 reg = <0 0x06b00000 0 0x1000>; 3012 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3013 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3014 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3015 <&lpass_vamacro>; 3016 clock-names = "mclk", 3017 "macro", 3018 "dcodec", 3019 "fsgen"; 3020 3021 #clock-cells = <0>; 3022 clock-output-names = "mclk"; 3023 #sound-dai-cells = <1>; 3024 }; 3025 3026 swr0: soundwire@6b10000 { 3027 compatible = "qcom,soundwire-v2.0.0"; 3028 reg = <0 0x06b10000 0 0x10000>; 3029 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 3030 clocks = <&lpass_wsamacro>; 3031 clock-names = "iface"; 3032 label = "WSA"; 3033 3034 pinctrl-0 = <&wsa_swr_active>; 3035 pinctrl-names = "default"; 3036 3037 qcom,din-ports = <4>; 3038 qcom,dout-ports = <9>; 3039 3040 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3041 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3042 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3043 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3044 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3045 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3046 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3047 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3048 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3049 3050 #address-cells = <2>; 3051 #size-cells = <0>; 3052 #sound-dai-cells = <1>; 3053 status = "disabled"; 3054 }; 3055 3056 swr2: soundwire@6d30000 { 3057 compatible = "qcom,soundwire-v2.0.0"; 3058 reg = <0 0x06d30000 0 0x10000>; 3059 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 3060 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 3061 interrupt-names = "core", "wakeup"; 3062 clocks = <&lpass_txmacro>; 3063 clock-names = "iface"; 3064 label = "TX"; 3065 3066 pinctrl-0 = <&tx_swr_active>; 3067 pinctrl-names = "default"; 3068 3069 qcom,din-ports = <4>; 3070 qcom,dout-ports = <0>; 3071 3072 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3073 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 3074 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3075 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3076 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3077 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3078 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3079 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3080 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 3081 3082 #address-cells = <2>; 3083 #size-cells = <0>; 3084 #sound-dai-cells = <1>; 3085 status = "disabled"; 3086 }; 3087 3088 lpass_vamacro: codec@6d44000 { 3089 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 3090 reg = <0 0x06d44000 0 0x1000>; 3091 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3092 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3093 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3094 clock-names = "mclk", 3095 "macro", 3096 "dcodec"; 3097 3098 #clock-cells = <0>; 3099 clock-output-names = "fsgen"; 3100 #sound-dai-cells = <1>; 3101 }; 3102 3103 lpass_tlmm: pinctrl@6e80000 { 3104 compatible = "qcom,sm8650-lpass-lpi-pinctrl"; 3105 reg = <0 0x06e80000 0 0x20000>; 3106 3107 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3108 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3109 clock-names = "core", "audio"; 3110 3111 gpio-controller; 3112 #gpio-cells = <2>; 3113 gpio-ranges = <&lpass_tlmm 0 0 23>; 3114 3115 tx_swr_active: tx-swr-active-state { 3116 clk-pins { 3117 pins = "gpio0"; 3118 function = "swr_tx_clk"; 3119 drive-strength = <2>; 3120 slew-rate = <1>; 3121 bias-disable; 3122 }; 3123 3124 data-pins { 3125 pins = "gpio1", "gpio2", "gpio14"; 3126 function = "swr_tx_data"; 3127 drive-strength = <2>; 3128 slew-rate = <1>; 3129 bias-bus-hold; 3130 }; 3131 }; 3132 3133 rx_swr_active: rx-swr-active-state { 3134 clk-pins { 3135 pins = "gpio3"; 3136 function = "swr_rx_clk"; 3137 drive-strength = <2>; 3138 slew-rate = <1>; 3139 bias-disable; 3140 }; 3141 3142 data-pins { 3143 pins = "gpio4", "gpio5"; 3144 function = "swr_rx_data"; 3145 drive-strength = <2>; 3146 slew-rate = <1>; 3147 bias-bus-hold; 3148 }; 3149 }; 3150 3151 dmic01_default: dmic01-default-state { 3152 clk-pins { 3153 pins = "gpio6"; 3154 function = "dmic1_clk"; 3155 drive-strength = <8>; 3156 output-high; 3157 }; 3158 3159 data-pins { 3160 pins = "gpio7"; 3161 function = "dmic1_data"; 3162 drive-strength = <8>; 3163 input-enable; 3164 }; 3165 }; 3166 3167 dmic23_default: dmic23-default-state { 3168 clk-pins { 3169 pins = "gpio8"; 3170 function = "dmic2_clk"; 3171 drive-strength = <8>; 3172 output-high; 3173 }; 3174 3175 data-pins { 3176 pins = "gpio9"; 3177 function = "dmic2_data"; 3178 drive-strength = <8>; 3179 input-enable; 3180 }; 3181 }; 3182 3183 wsa_swr_active: wsa-swr-active-state { 3184 clk-pins { 3185 pins = "gpio10"; 3186 function = "wsa_swr_clk"; 3187 drive-strength = <2>; 3188 slew-rate = <1>; 3189 bias-disable; 3190 }; 3191 3192 data-pins { 3193 pins = "gpio11"; 3194 function = "wsa_swr_data"; 3195 drive-strength = <2>; 3196 slew-rate = <1>; 3197 bias-bus-hold; 3198 }; 3199 }; 3200 3201 wsa2_swr_active: wsa2-swr-active-state { 3202 clk-pins { 3203 pins = "gpio15"; 3204 function = "wsa2_swr_clk"; 3205 drive-strength = <2>; 3206 slew-rate = <1>; 3207 bias-disable; 3208 }; 3209 3210 data-pins { 3211 pins = "gpio16"; 3212 function = "wsa2_swr_data"; 3213 drive-strength = <2>; 3214 slew-rate = <1>; 3215 bias-bus-hold; 3216 }; 3217 }; 3218 }; 3219 3220 lpass_lpiaon_noc: interconnect@7400000 { 3221 compatible = "qcom,sm8650-lpass-lpiaon-noc"; 3222 reg = <0 0x07400000 0 0x19080>; 3223 3224 #interconnect-cells = <2>; 3225 3226 qcom,bcm-voters = <&apps_bcm_voter>; 3227 }; 3228 3229 lpass_lpicx_noc: interconnect@7430000 { 3230 compatible = "qcom,sm8650-lpass-lpicx-noc"; 3231 reg = <0 0x07430000 0 0x3a200>; 3232 3233 #interconnect-cells = <2>; 3234 3235 qcom,bcm-voters = <&apps_bcm_voter>; 3236 }; 3237 3238 lpass_ag_noc: interconnect@7e40000 { 3239 compatible = "qcom,sm8650-lpass-ag-noc"; 3240 reg = <0 0x07e40000 0 0xe080>; 3241 3242 #interconnect-cells = <2>; 3243 3244 qcom,bcm-voters = <&apps_bcm_voter>; 3245 }; 3246 3247 sdhc_2: mmc@8804000 { 3248 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; 3249 reg = <0 0x08804000 0 0x1000>; 3250 3251 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3252 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3253 interrupt-names = "hc_irq", 3254 "pwr_irq"; 3255 3256 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3257 <&gcc GCC_SDCC2_APPS_CLK>, 3258 <&rpmhcc RPMH_CXO_CLK>; 3259 clock-names = "iface", 3260 "core", 3261 "xo"; 3262 3263 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3264 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3265 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3266 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; 3267 interconnect-names = "sdhc-ddr", 3268 "cpu-sdhc"; 3269 3270 power-domains = <&rpmhpd RPMHPD_CX>; 3271 operating-points-v2 = <&sdhc2_opp_table>; 3272 3273 iommus = <&apps_smmu 0x540 0>; 3274 3275 bus-width = <4>; 3276 3277 /* Forbid SDR104/SDR50 - broken hw! */ 3278 sdhci-caps-mask = <0x3 0>; 3279 3280 qcom,dll-config = <0x0007642c>; 3281 qcom,ddr-config = <0x80040868>; 3282 3283 dma-coherent; 3284 3285 status = "disabled"; 3286 3287 sdhc2_opp_table: opp-table { 3288 compatible = "operating-points-v2"; 3289 3290 opp-19200000 { 3291 opp-hz = /bits/ 64 <19200000>; 3292 required-opps = <&rpmhpd_opp_min_svs>; 3293 }; 3294 3295 opp-50000000 { 3296 opp-hz = /bits/ 64 <50000000>; 3297 required-opps = <&rpmhpd_opp_low_svs>; 3298 }; 3299 3300 opp-100000000 { 3301 opp-hz = /bits/ 64 <100000000>; 3302 required-opps = <&rpmhpd_opp_svs>; 3303 }; 3304 3305 opp-202000000 { 3306 opp-hz = /bits/ 64 <202000000>; 3307 required-opps = <&rpmhpd_opp_svs_l1>; 3308 }; 3309 }; 3310 }; 3311 3312 mdss: display-subsystem@ae00000 { 3313 compatible = "qcom,sm8650-mdss"; 3314 reg = <0 0x0ae00000 0 0x1000>; 3315 reg-names = "mdss"; 3316 3317 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3318 3319 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3320 <&gcc GCC_DISP_HF_AXI_CLK>, 3321 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3322 3323 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3324 3325 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 3326 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 3327 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 3328 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3329 interconnect-names = "mdp0-mem", 3330 "mdp1-mem"; 3331 3332 power-domains = <&dispcc MDSS_GDSC>; 3333 3334 iommus = <&apps_smmu 0x1c00 0x2>; 3335 3336 interrupt-controller; 3337 #interrupt-cells = <1>; 3338 3339 #address-cells = <2>; 3340 #size-cells = <2>; 3341 ranges; 3342 3343 status = "disabled"; 3344 3345 mdss_mdp: display-controller@ae01000 { 3346 compatible = "qcom,sm8650-dpu"; 3347 reg = <0 0x0ae01000 0 0x8f000>, 3348 <0 0x0aeb0000 0 0x2008>; 3349 reg-names = "mdp", 3350 "vbif"; 3351 3352 interrupts-extended = <&mdss 0>; 3353 3354 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3355 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3356 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3357 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3358 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3359 clock-names = "nrt_bus", 3360 "iface", 3361 "lut", 3362 "core", 3363 "vsync"; 3364 3365 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3366 assigned-clock-rates = <19200000>; 3367 3368 operating-points-v2 = <&mdp_opp_table>; 3369 3370 power-domains = <&rpmhpd RPMHPD_MMCX>; 3371 3372 ports { 3373 #address-cells = <1>; 3374 #size-cells = <0>; 3375 3376 port@0 { 3377 reg = <0>; 3378 3379 dpu_intf1_out: endpoint { 3380 remote-endpoint = <&mdss_dsi0_in>; 3381 }; 3382 }; 3383 3384 port@1 { 3385 reg = <1>; 3386 3387 dpu_intf2_out: endpoint { 3388 remote-endpoint = <&mdss_dsi1_in>; 3389 }; 3390 }; 3391 3392 port@2 { 3393 reg = <2>; 3394 3395 dpu_intf0_out: endpoint { 3396 remote-endpoint = <&mdss_dp0_in>; 3397 }; 3398 }; 3399 }; 3400 3401 mdp_opp_table: opp-table { 3402 compatible = "operating-points-v2"; 3403 3404 opp-200000000 { 3405 opp-hz = /bits/ 64 <200000000>; 3406 required-opps = <&rpmhpd_opp_low_svs>; 3407 }; 3408 3409 opp-325000000 { 3410 opp-hz = /bits/ 64 <325000000>; 3411 required-opps = <&rpmhpd_opp_svs>; 3412 }; 3413 3414 opp-375000000 { 3415 opp-hz = /bits/ 64 <375000000>; 3416 required-opps = <&rpmhpd_opp_svs_l1>; 3417 }; 3418 3419 opp-514000000 { 3420 opp-hz = /bits/ 64 <514000000>; 3421 required-opps = <&rpmhpd_opp_nom>; 3422 }; 3423 }; 3424 }; 3425 3426 mdss_dsi0: dsi@ae94000 { 3427 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3428 reg = <0 0x0ae94000 0 0x400>; 3429 reg-names = "dsi_ctrl"; 3430 3431 interrupts-extended = <&mdss 4>; 3432 3433 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3434 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3435 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3436 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3437 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3438 <&gcc GCC_DISP_HF_AXI_CLK>; 3439 clock-names = "byte", 3440 "byte_intf", 3441 "pixel", 3442 "core", 3443 "iface", 3444 "bus"; 3445 3446 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3447 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3448 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3449 <&mdss_dsi0_phy 1>; 3450 3451 operating-points-v2 = <&mdss_dsi_opp_table>; 3452 3453 power-domains = <&rpmhpd RPMHPD_MMCX>; 3454 3455 phys = <&mdss_dsi0_phy>; 3456 phy-names = "dsi"; 3457 3458 #address-cells = <1>; 3459 #size-cells = <0>; 3460 3461 status = "disabled"; 3462 3463 ports { 3464 #address-cells = <1>; 3465 #size-cells = <0>; 3466 3467 port@0 { 3468 reg = <0>; 3469 3470 mdss_dsi0_in: endpoint { 3471 remote-endpoint = <&dpu_intf1_out>; 3472 }; 3473 }; 3474 3475 port@1 { 3476 reg = <1>; 3477 3478 mdss_dsi0_out: endpoint { 3479 }; 3480 }; 3481 }; 3482 3483 mdss_dsi_opp_table: opp-table { 3484 compatible = "operating-points-v2"; 3485 3486 opp-187500000 { 3487 opp-hz = /bits/ 64 <187500000>; 3488 required-opps = <&rpmhpd_opp_low_svs>; 3489 }; 3490 3491 opp-300000000 { 3492 opp-hz = /bits/ 64 <300000000>; 3493 required-opps = <&rpmhpd_opp_svs>; 3494 }; 3495 3496 opp-358000000 { 3497 opp-hz = /bits/ 64 <358000000>; 3498 required-opps = <&rpmhpd_opp_svs_l1>; 3499 }; 3500 }; 3501 }; 3502 3503 mdss_dsi0_phy: phy@ae95000 { 3504 compatible = "qcom,sm8650-dsi-phy-4nm"; 3505 reg = <0 0x0ae95000 0 0x200>, 3506 <0 0x0ae95200 0 0x280>, 3507 <0 0x0ae95500 0 0x400>; 3508 reg-names = "dsi_phy", 3509 "dsi_phy_lane", 3510 "dsi_pll"; 3511 3512 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3513 <&rpmhcc RPMH_CXO_CLK>; 3514 clock-names = "iface", 3515 "ref"; 3516 3517 #clock-cells = <1>; 3518 #phy-cells = <0>; 3519 3520 status = "disabled"; 3521 }; 3522 3523 mdss_dsi1: dsi@ae96000 { 3524 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3525 reg = <0 0x0ae96000 0 0x400>; 3526 reg-names = "dsi_ctrl"; 3527 3528 interrupts-extended = <&mdss 5>; 3529 3530 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3531 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3532 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3533 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3534 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3535 <&gcc GCC_DISP_HF_AXI_CLK>; 3536 clock-names = "byte", 3537 "byte_intf", 3538 "pixel", 3539 "core", 3540 "iface", 3541 "bus"; 3542 3543 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3544 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3545 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3546 <&mdss_dsi1_phy 1>; 3547 3548 operating-points-v2 = <&mdss_dsi_opp_table>; 3549 3550 power-domains = <&rpmhpd RPMHPD_MMCX>; 3551 3552 phys = <&mdss_dsi1_phy>; 3553 phy-names = "dsi"; 3554 3555 #address-cells = <1>; 3556 #size-cells = <0>; 3557 3558 status = "disabled"; 3559 3560 ports { 3561 #address-cells = <1>; 3562 #size-cells = <0>; 3563 3564 port@0 { 3565 reg = <0>; 3566 3567 mdss_dsi1_in: endpoint { 3568 remote-endpoint = <&dpu_intf2_out>; 3569 }; 3570 }; 3571 3572 port@1 { 3573 reg = <1>; 3574 3575 mdss_dsi1_out: endpoint { 3576 }; 3577 }; 3578 }; 3579 }; 3580 3581 mdss_dsi1_phy: phy@ae97000 { 3582 compatible = "qcom,sm8650-dsi-phy-4nm"; 3583 reg = <0 0x0ae97000 0 0x200>, 3584 <0 0x0ae97200 0 0x280>, 3585 <0 0x0ae97500 0 0x400>; 3586 reg-names = "dsi_phy", 3587 "dsi_phy_lane", 3588 "dsi_pll"; 3589 3590 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3591 <&rpmhcc RPMH_CXO_CLK>; 3592 clock-names = "iface", 3593 "ref"; 3594 3595 #clock-cells = <1>; 3596 #phy-cells = <0>; 3597 3598 status = "disabled"; 3599 }; 3600 3601 mdss_dp0: displayport-controller@af54000 { 3602 compatible = "qcom,sm8650-dp"; 3603 reg = <0 0xaf54000 0 0x104>, 3604 <0 0xaf54200 0 0xc0>, 3605 <0 0xaf55000 0 0x770>, 3606 <0 0xaf56000 0 0x9c>, 3607 <0 0xaf57000 0 0x9c>; 3608 3609 interrupts-extended = <&mdss 12>; 3610 3611 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3612 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3613 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3614 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3615 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3616 clock-names = "core_iface", 3617 "core_aux", 3618 "ctrl_link", 3619 "ctrl_link_iface", 3620 "stream_pixel"; 3621 3622 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3623 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3624 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3625 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3626 3627 operating-points-v2 = <&dp_opp_table>; 3628 3629 power-domains = <&rpmhpd RPMHPD_MMCX>; 3630 3631 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 3632 phy-names = "dp"; 3633 3634 #sound-dai-cells = <0>; 3635 3636 status = "disabled"; 3637 3638 dp_opp_table: opp-table { 3639 compatible = "operating-points-v2"; 3640 3641 opp-162000000 { 3642 opp-hz = /bits/ 64 <162000000>; 3643 required-opps = <&rpmhpd_opp_low_svs_d1>; 3644 }; 3645 3646 opp-270000000 { 3647 opp-hz = /bits/ 64 <270000000>; 3648 required-opps = <&rpmhpd_opp_low_svs>; 3649 }; 3650 3651 opp-540000000 { 3652 opp-hz = /bits/ 64 <540000000>; 3653 required-opps = <&rpmhpd_opp_svs_l1>; 3654 }; 3655 3656 opp-810000000 { 3657 opp-hz = /bits/ 64 <810000000>; 3658 required-opps = <&rpmhpd_opp_nom>; 3659 }; 3660 }; 3661 3662 ports { 3663 #address-cells = <1>; 3664 #size-cells = <0>; 3665 3666 port@0 { 3667 reg = <0>; 3668 3669 mdss_dp0_in: endpoint { 3670 remote-endpoint = <&dpu_intf0_out>; 3671 }; 3672 }; 3673 3674 port@1 { 3675 reg = <1>; 3676 3677 mdss_dp0_out: endpoint { 3678 }; 3679 }; 3680 }; 3681 }; 3682 }; 3683 3684 dispcc: clock-controller@af00000 { 3685 compatible = "qcom,sm8650-dispcc"; 3686 reg = <0 0x0af00000 0 0x20000>; 3687 3688 clocks = <&bi_tcxo_div2>, 3689 <&bi_tcxo_ao_div2>, 3690 <&gcc GCC_DISP_AHB_CLK>, 3691 <&sleep_clk>, 3692 <&mdss_dsi0_phy 0>, 3693 <&mdss_dsi0_phy 1>, 3694 <&mdss_dsi1_phy 0>, 3695 <&mdss_dsi1_phy 1>, 3696 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3697 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3698 <0>, /* dp1 */ 3699 <0>, 3700 <0>, /* dp2 */ 3701 <0>, 3702 <0>, /* dp3 */ 3703 <0>; 3704 3705 power-domains = <&rpmhpd RPMHPD_MMCX>; 3706 required-opps = <&rpmhpd_opp_low_svs>; 3707 3708 #clock-cells = <1>; 3709 #reset-cells = <1>; 3710 #power-domain-cells = <1>; 3711 3712 status = "disabled"; 3713 }; 3714 3715 usb_1_hsphy: phy@88e3000 { 3716 compatible = "qcom,sm8650-snps-eusb2-phy", 3717 "qcom,sm8550-snps-eusb2-phy"; 3718 reg = <0 0x088e3000 0 0x154>; 3719 3720 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 3721 clock-names = "ref"; 3722 3723 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3724 3725 #phy-cells = <0>; 3726 3727 status = "disabled"; 3728 }; 3729 3730 usb_dp_qmpphy: phy@88e8000 { 3731 compatible = "qcom,sm8650-qmp-usb3-dp-phy"; 3732 reg = <0 0x088e8000 0 0x3000>; 3733 3734 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3735 <&rpmhcc RPMH_CXO_CLK>, 3736 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3737 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3738 clock-names = "aux", 3739 "ref", 3740 "com_aux", 3741 "usb3_pipe"; 3742 3743 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3744 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 3745 reset-names = "phy", 3746 "common"; 3747 3748 power-domains = <&gcc USB3_PHY_GDSC>; 3749 3750 #clock-cells = <1>; 3751 #phy-cells = <1>; 3752 3753 status = "disabled"; 3754 3755 ports { 3756 #address-cells = <1>; 3757 #size-cells = <0>; 3758 3759 port@0 { 3760 reg = <0>; 3761 3762 usb_dp_qmpphy_out: endpoint { 3763 }; 3764 }; 3765 3766 port@1 { 3767 reg = <1>; 3768 3769 usb_dp_qmpphy_usb_ss_in: endpoint { 3770 }; 3771 }; 3772 3773 port@2 { 3774 reg = <2>; 3775 3776 usb_dp_qmpphy_dp_in: endpoint { 3777 }; 3778 }; 3779 }; 3780 }; 3781 3782 usb_1: usb@a6f8800 { 3783 compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; 3784 reg = <0 0x0a6f8800 0 0x400>; 3785 3786 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3787 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3788 <&pdc 14 IRQ_TYPE_EDGE_RISING>, 3789 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 3790 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3791 interrupt-names = "pwr_event", 3792 "hs_phy_irq", 3793 "dp_hs_phy_irq", 3794 "dm_hs_phy_irq", 3795 "ss_phy_irq"; 3796 3797 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3798 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3799 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3800 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3801 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3802 <&tcsr TCSR_USB3_CLKREF_EN>; 3803 clock-names = "cfg_noc", 3804 "core", 3805 "iface", 3806 "sleep", 3807 "mock_utmi", 3808 "xo"; 3809 3810 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3811 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3812 assigned-clock-rates = <19200000>, <200000000>; 3813 3814 resets = <&gcc GCC_USB30_PRIM_BCR>; 3815 3816 power-domains = <&gcc USB30_PRIM_GDSC>; 3817 required-opps = <&rpmhpd_opp_nom>; 3818 3819 #address-cells = <2>; 3820 #size-cells = <2>; 3821 ranges; 3822 3823 status = "disabled"; 3824 3825 usb_1_dwc3: usb@a600000 { 3826 compatible = "snps,dwc3"; 3827 reg = <0 0x0a600000 0 0xcd00>; 3828 3829 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3830 3831 iommus = <&apps_smmu 0x40 0>; 3832 3833 phys = <&usb_1_hsphy>, 3834 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 3835 phy-names = "usb2-phy", 3836 "usb3-phy"; 3837 3838 snps,hird-threshold = /bits/ 8 <0x0>; 3839 snps,usb2-gadget-lpm-disable; 3840 snps,dis_u2_susphy_quirk; 3841 snps,dis_enblslpm_quirk; 3842 snps,dis-u1-entry-quirk; 3843 snps,dis-u2-entry-quirk; 3844 snps,is-utmi-l1-suspend; 3845 snps,usb3_lpm_capable; 3846 snps,usb2-lpm-disable; 3847 snps,has-lpm-erratum; 3848 tx-fifo-resize; 3849 3850 dma-coherent; 3851 3852 ports { 3853 #address-cells = <1>; 3854 #size-cells = <0>; 3855 3856 port@0 { 3857 reg = <0>; 3858 3859 usb_1_dwc3_hs: endpoint { 3860 }; 3861 }; 3862 3863 port@1 { 3864 reg = <1>; 3865 3866 usb_1_dwc3_ss: endpoint { 3867 }; 3868 }; 3869 }; 3870 }; 3871 }; 3872 3873 pdc: interrupt-controller@b220000 { 3874 compatible = "qcom,sm8650-pdc", "qcom,pdc"; 3875 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3876 3877 interrupt-parent = <&intc>; 3878 3879 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3880 <125 63 1>, <126 716 12>, 3881 <138 251 5>, <143 244 4>; 3882 3883 #interrupt-cells = <2>; 3884 interrupt-controller; 3885 }; 3886 3887 tsens0: thermal-sensor@c228000 { 3888 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 3889 reg = <0 0x0c228000 0 0x1000>, /* TM */ 3890 <0 0x0c222000 0 0x1000>; /* SROT */ 3891 3892 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3893 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 3894 interrupt-names = "uplow", 3895 "critical"; 3896 3897 #qcom,sensors = <15>; 3898 3899 #thermal-sensor-cells = <1>; 3900 }; 3901 3902 tsens1: thermal-sensor@c229000 { 3903 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 3904 reg = <0 0x0c229000 0 0x1000>, /* TM */ 3905 <0 0x0c223000 0 0x1000>; /* SROT */ 3906 3907 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3908 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 3909 interrupt-names = "uplow", 3910 "critical"; 3911 3912 #qcom,sensors = <16>; 3913 3914 #thermal-sensor-cells = <1>; 3915 }; 3916 3917 tsens2: thermal-sensor@c22a000 { 3918 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 3919 reg = <0 0x0c22a000 0 0x1000>, /* TM */ 3920 <0 0x0c224000 0 0x1000>; /* SROT */ 3921 3922 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 3923 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 3924 interrupt-names = "uplow", 3925 "critical"; 3926 3927 #qcom,sensors = <13>; 3928 3929 #thermal-sensor-cells = <1>; 3930 }; 3931 3932 aoss_qmp: power-management@c300000 { 3933 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; 3934 reg = <0 0x0c300000 0 0x400>; 3935 3936 interrupt-parent = <&ipcc>; 3937 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3938 IRQ_TYPE_EDGE_RISING>; 3939 3940 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3941 3942 #clock-cells = <0>; 3943 }; 3944 3945 sram@c3f0000 { 3946 compatible = "qcom,rpmh-stats"; 3947 reg = <0 0x0c3f0000 0 0x400>; 3948 }; 3949 3950 spmi_bus: spmi@c400000 { 3951 compatible = "qcom,spmi-pmic-arb"; 3952 reg = <0 0x0c400000 0 0x3000>, 3953 <0 0x0c500000 0 0x400000>, 3954 <0 0x0c440000 0 0x80000>, 3955 <0 0x0c4c0000 0 0x20000>, 3956 <0 0x0c42d000 0 0x4000>; 3957 reg-names = "core", 3958 "chnls", 3959 "obsrvr", 3960 "intr", 3961 "cnfg"; 3962 3963 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3964 interrupt-names = "periph_irq"; 3965 3966 qcom,ee = <0>; 3967 qcom,channel = <0>; 3968 qcom,bus-id = <0>; 3969 3970 interrupt-controller; 3971 #interrupt-cells = <4>; 3972 3973 #address-cells = <2>; 3974 #size-cells = <0>; 3975 }; 3976 3977 tlmm: pinctrl@f100000 { 3978 compatible = "qcom,sm8650-tlmm"; 3979 reg = <0 0x0f100000 0 0x300000>; 3980 3981 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3982 3983 gpio-controller; 3984 #gpio-cells = <2>; 3985 3986 interrupt-controller; 3987 #interrupt-cells = <2>; 3988 3989 gpio-ranges = <&tlmm 0 0 211>; 3990 3991 wakeup-parent = <&pdc>; 3992 3993 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3994 /* SDA, SCL */ 3995 pins = "gpio64", "gpio65"; 3996 function = "i2chub0_se0"; 3997 drive-strength = <2>; 3998 bias-pull-up; 3999 }; 4000 4001 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 4002 /* SDA, SCL */ 4003 pins = "gpio66", "gpio67"; 4004 function = "i2chub0_se1"; 4005 drive-strength = <2>; 4006 bias-pull-up; 4007 }; 4008 4009 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 4010 /* SDA, SCL */ 4011 pins = "gpio68", "gpio69"; 4012 function = "i2chub0_se2"; 4013 drive-strength = <2>; 4014 bias-pull-up; 4015 }; 4016 4017 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 4018 /* SDA, SCL */ 4019 pins = "gpio70", "gpio71"; 4020 function = "i2chub0_se3"; 4021 drive-strength = <2>; 4022 bias-pull-up; 4023 }; 4024 4025 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 4026 /* SDA, SCL */ 4027 pins = "gpio72", "gpio73"; 4028 function = "i2chub0_se4"; 4029 drive-strength = <2>; 4030 bias-pull-up; 4031 }; 4032 4033 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 4034 /* SDA, SCL */ 4035 pins = "gpio74", "gpio75"; 4036 function = "i2chub0_se5"; 4037 drive-strength = <2>; 4038 bias-pull-up; 4039 }; 4040 4041 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 4042 /* SDA, SCL */ 4043 pins = "gpio76", "gpio77"; 4044 function = "i2chub0_se6"; 4045 drive-strength = <2>; 4046 bias-pull-up; 4047 }; 4048 4049 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 4050 /* SDA, SCL */ 4051 pins = "gpio78", "gpio79"; 4052 function = "i2chub0_se7"; 4053 drive-strength = <2>; 4054 bias-pull-up; 4055 }; 4056 4057 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 4058 /* SDA, SCL */ 4059 pins = "gpio206", "gpio207"; 4060 function = "i2chub0_se8"; 4061 drive-strength = <2>; 4062 bias-pull-up; 4063 }; 4064 4065 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 4066 /* SDA, SCL */ 4067 pins = "gpio80", "gpio81"; 4068 function = "i2chub0_se9"; 4069 drive-strength = <2>; 4070 bias-pull-up; 4071 }; 4072 4073 pcie0_default_state: pcie0-default-state { 4074 perst-pins { 4075 pins = "gpio94"; 4076 function = "gpio"; 4077 drive-strength = <2>; 4078 bias-pull-down; 4079 }; 4080 4081 clkreq-pins { 4082 pins = "gpio95"; 4083 function = "pcie0_clk_req_n"; 4084 drive-strength = <2>; 4085 bias-pull-up; 4086 }; 4087 4088 wake-pins { 4089 pins = "gpio96"; 4090 function = "gpio"; 4091 drive-strength = <2>; 4092 bias-pull-up; 4093 }; 4094 }; 4095 4096 pcie1_default_state: pcie1-default-state { 4097 perst-pins { 4098 pins = "gpio97"; 4099 function = "gpio"; 4100 drive-strength = <2>; 4101 bias-pull-down; 4102 }; 4103 4104 clkreq-pins { 4105 pins = "gpio98"; 4106 function = "pcie1_clk_req_n"; 4107 drive-strength = <2>; 4108 bias-pull-up; 4109 }; 4110 4111 wake-pins { 4112 pins = "gpio99"; 4113 function = "gpio"; 4114 drive-strength = <2>; 4115 bias-pull-up; 4116 }; 4117 }; 4118 4119 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4120 /* SDA, SCL */ 4121 pins = "gpio32", "gpio33"; 4122 function = "qup1_se0"; 4123 drive-strength = <2>; 4124 bias-pull-up; 4125 }; 4126 4127 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4128 /* SDA, SCL */ 4129 pins = "gpio36", "gpio37"; 4130 function = "qup1_se1"; 4131 drive-strength = <2>; 4132 bias-pull-up; 4133 }; 4134 4135 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4136 /* SDA, SCL */ 4137 pins = "gpio40", "gpio41"; 4138 function = "qup1_se2"; 4139 drive-strength = <2>; 4140 bias-pull-up; 4141 }; 4142 4143 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4144 /* SDA, SCL */ 4145 pins = "gpio44", "gpio45"; 4146 function = "qup1_se3"; 4147 drive-strength = <2>; 4148 bias-pull-up; 4149 }; 4150 4151 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4152 /* SDA, SCL */ 4153 pins = "gpio48", "gpio49"; 4154 function = "qup1_se4"; 4155 drive-strength = <2>; 4156 bias-pull-up; 4157 }; 4158 4159 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4160 /* SDA, SCL */ 4161 pins = "gpio52", "gpio53"; 4162 function = "qup1_se5"; 4163 drive-strength = <2>; 4164 bias-pull-up; 4165 }; 4166 4167 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4168 /* SDA, SCL */ 4169 pins = "gpio56", "gpio57"; 4170 function = "qup1_se6"; 4171 drive-strength = <2>; 4172 bias-pull-up; 4173 }; 4174 4175 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4176 /* SDA, SCL */ 4177 pins = "gpio60", "gpio61"; 4178 function = "qup1_se7"; 4179 drive-strength = <2>; 4180 bias-pull-up; 4181 }; 4182 4183 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4184 /* SDA, SCL */ 4185 pins = "gpio0", "gpio1"; 4186 function = "qup2_se0"; 4187 drive-strength = <2>; 4188 bias-pull-up; 4189 }; 4190 4191 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4192 /* SDA, SCL */ 4193 pins = "gpio4", "gpio5"; 4194 function = "qup2_se1"; 4195 drive-strength = <2>; 4196 bias-pull-up; 4197 }; 4198 4199 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4200 /* SDA, SCL */ 4201 pins = "gpio8", "gpio9"; 4202 function = "qup2_se2"; 4203 drive-strength = <2>; 4204 bias-pull-up; 4205 }; 4206 4207 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4208 /* SDA, SCL */ 4209 pins = "gpio12", "gpio13"; 4210 function = "qup2_se3"; 4211 drive-strength = <2>; 4212 bias-pull-up; 4213 }; 4214 4215 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4216 /* SDA, SCL */ 4217 pins = "gpio16", "gpio17"; 4218 function = "qup2_se4"; 4219 drive-strength = <2>; 4220 bias-pull-up; 4221 }; 4222 4223 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4224 /* SDA, SCL */ 4225 pins = "gpio20", "gpio21"; 4226 function = "qup2_se5"; 4227 drive-strength = <2>; 4228 bias-pull-up; 4229 }; 4230 4231 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4232 /* SDA, SCL */ 4233 pins = "gpio24", "gpio25"; 4234 function = "qup2_se6"; 4235 drive-strength = <2>; 4236 bias-pull-up; 4237 }; 4238 4239 qup_spi0_cs: qup-spi0-cs-state { 4240 pins = "gpio35"; 4241 function = "qup1_se0"; 4242 drive-strength = <6>; 4243 bias-disable; 4244 }; 4245 4246 qup_spi0_data_clk: qup-spi0-data-clk-state { 4247 /* MISO, MOSI, CLK */ 4248 pins = "gpio32", "gpio33", "gpio34"; 4249 function = "qup1_se0"; 4250 drive-strength = <6>; 4251 bias-disable; 4252 }; 4253 4254 qup_spi1_cs: qup-spi1-cs-state { 4255 pins = "gpio39"; 4256 function = "qup1_se1"; 4257 drive-strength = <6>; 4258 bias-disable; 4259 }; 4260 4261 qup_spi1_data_clk: qup-spi1-data-clk-state { 4262 /* MISO, MOSI, CLK */ 4263 pins = "gpio36", "gpio37", "gpio38"; 4264 function = "qup1_se1"; 4265 drive-strength = <6>; 4266 bias-disable; 4267 }; 4268 4269 qup_spi2_cs: qup-spi2-cs-state { 4270 pins = "gpio43"; 4271 function = "qup1_se2"; 4272 drive-strength = <6>; 4273 bias-disable; 4274 }; 4275 4276 qup_spi2_data_clk: qup-spi2-data-clk-state { 4277 /* MISO, MOSI, CLK */ 4278 pins = "gpio40", "gpio41", "gpio42"; 4279 function = "qup1_se2"; 4280 drive-strength = <6>; 4281 bias-disable; 4282 }; 4283 4284 qup_spi3_cs: qup-spi3-cs-state { 4285 pins = "gpio47"; 4286 function = "qup1_se3"; 4287 drive-strength = <6>; 4288 bias-disable; 4289 }; 4290 4291 qup_spi3_data_clk: qup-spi3-data-clk-state { 4292 /* MISO, MOSI, CLK */ 4293 pins = "gpio44", "gpio45", "gpio46"; 4294 function = "qup1_se3"; 4295 drive-strength = <6>; 4296 bias-disable; 4297 }; 4298 4299 qup_spi4_cs: qup-spi4-cs-state { 4300 pins = "gpio51"; 4301 function = "qup1_se4"; 4302 drive-strength = <6>; 4303 bias-disable; 4304 }; 4305 4306 qup_spi4_data_clk: qup-spi4-data-clk-state { 4307 /* MISO, MOSI, CLK */ 4308 pins = "gpio48", "gpio49", "gpio50"; 4309 function = "qup1_se4"; 4310 drive-strength = <6>; 4311 bias-disable; 4312 }; 4313 4314 qup_spi5_cs: qup-spi5-cs-state { 4315 pins = "gpio55"; 4316 function = "qup1_se5"; 4317 drive-strength = <6>; 4318 bias-disable; 4319 }; 4320 4321 qup_spi5_data_clk: qup-spi5-data-clk-state { 4322 /* MISO, MOSI, CLK */ 4323 pins = "gpio52", "gpio53", "gpio54"; 4324 function = "qup1_se5"; 4325 drive-strength = <6>; 4326 bias-disable; 4327 }; 4328 4329 qup_spi6_cs: qup-spi6-cs-state { 4330 pins = "gpio59"; 4331 function = "qup1_se6"; 4332 drive-strength = <6>; 4333 bias-disable; 4334 }; 4335 4336 qup_spi6_data_clk: qup-spi6-data-clk-state { 4337 /* MISO, MOSI, CLK */ 4338 pins = "gpio56", "gpio57", "gpio58"; 4339 function = "qup1_se6"; 4340 drive-strength = <6>; 4341 bias-disable; 4342 }; 4343 4344 qup_spi7_cs: qup-spi7-cs-state { 4345 pins = "gpio63"; 4346 function = "qup1_se7"; 4347 drive-strength = <6>; 4348 bias-disable; 4349 }; 4350 4351 qup_spi7_data_clk: qup-spi7-data-clk-state { 4352 /* MISO, MOSI, CLK */ 4353 pins = "gpio60", "gpio61", "gpio62"; 4354 function = "qup1_se7"; 4355 drive-strength = <6>; 4356 bias-disable; 4357 }; 4358 4359 qup_spi8_cs: qup-spi8-cs-state { 4360 pins = "gpio3"; 4361 function = "qup2_se0"; 4362 drive-strength = <6>; 4363 bias-disable; 4364 }; 4365 4366 qup_spi8_data_clk: qup-spi8-data-clk-state { 4367 /* MISO, MOSI, CLK */ 4368 pins = "gpio0", "gpio1", "gpio2"; 4369 function = "qup2_se0"; 4370 drive-strength = <6>; 4371 bias-disable; 4372 }; 4373 4374 qup_spi9_cs: qup-spi9-cs-state { 4375 pins = "gpio7"; 4376 function = "qup2_se1"; 4377 drive-strength = <6>; 4378 bias-disable; 4379 }; 4380 4381 qup_spi9_data_clk: qup-spi9-data-clk-state { 4382 /* MISO, MOSI, CLK */ 4383 pins = "gpio4", "gpio5", "gpio6"; 4384 function = "qup2_se1"; 4385 drive-strength = <6>; 4386 bias-disable; 4387 }; 4388 4389 qup_spi10_cs: qup-spi10-cs-state { 4390 pins = "gpio11"; 4391 function = "qup2_se2"; 4392 drive-strength = <6>; 4393 bias-disable; 4394 }; 4395 4396 qup_spi10_data_clk: qup-spi10-data-clk-state { 4397 /* MISO, MOSI, CLK */ 4398 pins = "gpio8", "gpio9", "gpio10"; 4399 function = "qup2_se2"; 4400 drive-strength = <6>; 4401 bias-disable; 4402 }; 4403 4404 qup_spi11_cs: qup-spi11-cs-state { 4405 pins = "gpio15"; 4406 function = "qup2_se3"; 4407 drive-strength = <6>; 4408 bias-disable; 4409 }; 4410 4411 qup_spi11_data_clk: qup-spi11-data-clk-state { 4412 /* MISO, MOSI, CLK */ 4413 pins = "gpio12", "gpio13", "gpio14"; 4414 function = "qup2_se3"; 4415 drive-strength = <6>; 4416 bias-disable; 4417 }; 4418 4419 qup_spi12_cs: qup-spi12-cs-state { 4420 pins = "gpio19"; 4421 function = "qup2_se4"; 4422 drive-strength = <6>; 4423 bias-disable; 4424 }; 4425 4426 qup_spi12_data_clk: qup-spi12-data-clk-state { 4427 /* MISO, MOSI, CLK */ 4428 pins = "gpio16", "gpio17", "gpio18"; 4429 function = "qup2_se4"; 4430 drive-strength = <6>; 4431 bias-disable; 4432 }; 4433 4434 qup_spi13_cs: qup-spi13-cs-state { 4435 pins = "gpio23"; 4436 function = "qup2_se5"; 4437 drive-strength = <6>; 4438 bias-disable; 4439 }; 4440 4441 qup_spi13_data_clk: qup-spi13-data-clk-state { 4442 /* MISO, MOSI, CLK */ 4443 pins = "gpio20", "gpio21", "gpio22"; 4444 function = "qup2_se5"; 4445 drive-strength = <6>; 4446 bias-disable; 4447 }; 4448 4449 qup_spi14_cs: qup-spi14-cs-state { 4450 pins = "gpio27"; 4451 function = "qup2_se6"; 4452 drive-strength = <6>; 4453 bias-disable; 4454 }; 4455 4456 qup_spi14_data_clk: qup-spi14-data-clk-state { 4457 /* MISO, MOSI, CLK */ 4458 pins = "gpio24", "gpio25", "gpio26"; 4459 function = "qup2_se6"; 4460 drive-strength = <6>; 4461 bias-disable; 4462 }; 4463 4464 qup_uart14_default: qup-uart14-default-state { 4465 /* TX, RX */ 4466 pins = "gpio26", "gpio27"; 4467 function = "qup2_se6"; 4468 drive-strength = <2>; 4469 bias-pull-up; 4470 }; 4471 4472 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 4473 /* CTS, RTS */ 4474 pins = "gpio24", "gpio25"; 4475 function = "qup2_se6"; 4476 drive-strength = <2>; 4477 bias-pull-down; 4478 }; 4479 4480 qup_uart15_default: qup-uart15-default-state { 4481 /* TX, RX */ 4482 pins = "gpio30", "gpio31"; 4483 function = "qup2_se7"; 4484 drive-strength = <2>; 4485 bias-disable; 4486 }; 4487 4488 sdc2_sleep: sdc2-sleep-state { 4489 clk-pins { 4490 pins = "sdc2_clk"; 4491 drive-strength = <2>; 4492 bias-disable; 4493 }; 4494 4495 cmd-pins { 4496 pins = "sdc2_cmd"; 4497 drive-strength = <2>; 4498 bias-pull-up; 4499 }; 4500 4501 data-pins { 4502 pins = "sdc2_data"; 4503 drive-strength = <2>; 4504 bias-pull-up; 4505 }; 4506 }; 4507 4508 sdc2_default: sdc2-default-state { 4509 clk-pins { 4510 pins = "sdc2_clk"; 4511 drive-strength = <16>; 4512 bias-disable; 4513 }; 4514 4515 cmd-pins { 4516 pins = "sdc2_cmd"; 4517 drive-strength = <10>; 4518 bias-pull-up; 4519 }; 4520 4521 data-pins { 4522 pins = "sdc2_data"; 4523 drive-strength = <10>; 4524 bias-pull-up; 4525 }; 4526 }; 4527 }; 4528 4529 apps_smmu: iommu@15000000 { 4530 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4531 reg = <0 0x15000000 0 0x100000>; 4532 4533 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4534 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4535 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4536 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4537 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4538 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4539 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4540 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4541 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4542 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4543 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4544 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4545 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4546 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4547 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4548 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4549 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4550 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4551 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4552 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4553 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4554 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4555 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4556 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4557 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4558 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4559 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4560 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4561 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4562 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4563 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4564 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4565 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4566 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4567 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4568 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4569 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4570 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4571 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4572 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4573 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4574 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4575 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4576 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4577 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4578 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4579 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4580 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4581 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4582 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4583 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4584 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4585 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4586 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4587 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4588 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4589 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4590 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4591 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4592 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4593 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4594 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4595 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4596 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4597 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4598 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4599 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4600 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4601 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4602 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4603 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4604 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4605 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4606 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4607 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4608 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4609 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4610 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4611 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4612 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4613 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4614 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4615 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4616 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4617 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4618 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4619 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4620 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4621 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4622 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4623 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4624 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4625 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4626 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4627 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4628 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4629 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 4630 4631 #iommu-cells = <2>; 4632 #global-interrupts = <1>; 4633 4634 dma-coherent; 4635 }; 4636 4637 intc: interrupt-controller@17100000 { 4638 compatible = "arm,gic-v3"; 4639 reg = <0 0x17100000 0 0x10000>, /* GICD */ 4640 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 4641 4642 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4643 4644 #interrupt-cells = <3>; 4645 interrupt-controller; 4646 4647 #redistributor-regions = <1>; 4648 redistributor-stride = <0 0x40000>; 4649 4650 #address-cells = <2>; 4651 #size-cells = <2>; 4652 ranges; 4653 4654 gic_its: msi-controller@17140000 { 4655 compatible = "arm,gic-v3-its"; 4656 reg = <0 0x17140000 0 0x20000>; 4657 4658 msi-controller; 4659 #msi-cells = <1>; 4660 }; 4661 }; 4662 4663 timer@17420000 { 4664 compatible = "arm,armv7-timer-mem"; 4665 reg = <0 0x17420000 0 0x1000>; 4666 4667 ranges = <0 0 0 0x20000000>; 4668 #address-cells = <1>; 4669 #size-cells = <1>; 4670 4671 frame@17421000 { 4672 reg = <0x17421000 0x1000>, 4673 <0x17422000 0x1000>; 4674 4675 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4676 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4677 4678 frame-number = <0>; 4679 }; 4680 4681 frame@17423000 { 4682 reg = <0x17423000 0x1000>; 4683 4684 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4685 4686 frame-number = <1>; 4687 4688 status = "disabled"; 4689 }; 4690 4691 frame@17425000 { 4692 reg = <0x17425000 0x1000>; 4693 4694 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4695 4696 frame-number = <2>; 4697 4698 status = "disabled"; 4699 }; 4700 4701 frame@17427000 { 4702 reg = <0x17427000 0x1000>; 4703 4704 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4705 4706 frame-number = <3>; 4707 4708 status = "disabled"; 4709 }; 4710 4711 frame@17429000 { 4712 reg = <0x17429000 0x1000>; 4713 4714 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4715 4716 frame-number = <4>; 4717 4718 status = "disabled"; 4719 }; 4720 4721 frame@1742b000 { 4722 reg = <0x1742b000 0x1000>; 4723 4724 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4725 4726 frame-number = <5>; 4727 4728 status = "disabled"; 4729 }; 4730 4731 frame@1742d000 { 4732 reg = <0x1742d000 0x1000>; 4733 4734 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4735 4736 frame-number = <6>; 4737 4738 status = "disabled"; 4739 }; 4740 }; 4741 4742 apps_rsc: rsc@17a00000 { 4743 compatible = "qcom,rpmh-rsc"; 4744 reg = <0 0x17a00000 0 0x10000>, 4745 <0 0x17a10000 0 0x10000>, 4746 <0 0x17a20000 0 0x10000>, 4747 <0 0x17a30000 0 0x10000>; 4748 reg-names = "drv-0", 4749 "drv-1", 4750 "drv-2"; 4751 4752 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4753 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4754 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4755 4756 power-domains = <&CLUSTER_PD>; 4757 4758 qcom,tcs-offset = <0xd00>; 4759 qcom,drv-id = <2>; 4760 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4761 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4762 4763 label = "apps_rsc"; 4764 4765 apps_bcm_voter: bcm-voter { 4766 compatible = "qcom,bcm-voter"; 4767 }; 4768 4769 rpmhcc: clock-controller { 4770 compatible = "qcom,sm8650-rpmh-clk"; 4771 4772 clocks = <&xo_board>; 4773 clock-names = "xo"; 4774 4775 #clock-cells = <1>; 4776 }; 4777 4778 rpmhpd: power-controller { 4779 compatible = "qcom,sm8650-rpmhpd"; 4780 4781 operating-points-v2 = <&rpmhpd_opp_table>; 4782 4783 #power-domain-cells = <1>; 4784 4785 rpmhpd_opp_table: opp-table { 4786 compatible = "operating-points-v2"; 4787 4788 rpmhpd_opp_ret: opp-16 { 4789 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4790 }; 4791 4792 rpmhpd_opp_min_svs: opp-48 { 4793 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4794 }; 4795 4796 rpmhpd_opp_low_svs_d2: opp-52 { 4797 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 4798 }; 4799 4800 rpmhpd_opp_low_svs_d1: opp-56 { 4801 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4802 }; 4803 4804 rpmhpd_opp_low_svs_d0: opp-60 { 4805 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 4806 }; 4807 4808 rpmhpd_opp_low_svs: opp-64 { 4809 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4810 }; 4811 4812 rpmhpd_opp_low_svs_l1: opp-80 { 4813 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4814 }; 4815 4816 rpmhpd_opp_svs: opp-128 { 4817 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4818 }; 4819 4820 rpmhpd_opp_svs_l0: opp-144 { 4821 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4822 }; 4823 4824 rpmhpd_opp_svs_l1: opp-192 { 4825 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4826 }; 4827 4828 rpmhpd_opp_nom: opp-256 { 4829 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4830 }; 4831 4832 rpmhpd_opp_nom_l1: opp-320 { 4833 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4834 }; 4835 4836 rpmhpd_opp_nom_l2: opp-336 { 4837 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4838 }; 4839 4840 rpmhpd_opp_turbo: opp-384 { 4841 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4842 }; 4843 4844 rpmhpd_opp_turbo_l1: opp-416 { 4845 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4846 }; 4847 }; 4848 }; 4849 }; 4850 4851 cpufreq_hw: cpufreq@17d91000 { 4852 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss"; 4853 reg = <0 0x17d91000 0 0x1000>, 4854 <0 0x17d92000 0 0x1000>, 4855 <0 0x17d93000 0 0x1000>, 4856 <0 0x17d94000 0 0x1000>; 4857 reg-names = "freq-domain0", 4858 "freq-domain1", 4859 "freq-domain2", 4860 "freq-domain3"; 4861 4862 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4863 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4864 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 4865 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 4866 interrupt-names = "dcvsh-irq-0", 4867 "dcvsh-irq-1", 4868 "dcvsh-irq-2", 4869 "dcvsh-irq-3"; 4870 4871 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 4872 clock-names = "xo", "alternate"; 4873 4874 #freq-domain-cells = <1>; 4875 #clock-cells = <1>; 4876 }; 4877 4878 pmu@24091000 { 4879 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4880 reg = <0 0x24091000 0 0x1000>; 4881 4882 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4883 4884 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 4885 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4886 4887 operating-points-v2 = <&llcc_bwmon_opp_table>; 4888 4889 llcc_bwmon_opp_table: opp-table { 4890 compatible = "operating-points-v2"; 4891 4892 opp-0 { 4893 opp-peak-kBps = <2086000>; 4894 }; 4895 4896 opp-1 { 4897 opp-peak-kBps = <2929000>; 4898 }; 4899 4900 opp-2 { 4901 opp-peak-kBps = <5931000>; 4902 }; 4903 4904 opp-3 { 4905 opp-peak-kBps = <6515000>; 4906 }; 4907 4908 opp-4 { 4909 opp-peak-kBps = <7980000>; 4910 }; 4911 4912 opp-5 { 4913 opp-peak-kBps = <10437000>; 4914 }; 4915 4916 opp-6 { 4917 opp-peak-kBps = <12157000>; 4918 }; 4919 4920 opp-7 { 4921 opp-peak-kBps = <14060000>; 4922 }; 4923 4924 opp-8 { 4925 opp-peak-kBps = <16113000>; 4926 }; 4927 }; 4928 }; 4929 4930 pmu@240b7400 { 4931 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; 4932 reg = <0 0x240b7400 0 0x600>; 4933 4934 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4935 4936 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4937 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4938 4939 operating-points-v2 = <&cpu_bwmon_opp_table>; 4940 4941 cpu_bwmon_opp_table: opp-table { 4942 compatible = "operating-points-v2"; 4943 4944 opp-0 { 4945 opp-peak-kBps = <4577000>; 4946 }; 4947 4948 opp-1 { 4949 opp-peak-kBps = <7110000>; 4950 }; 4951 4952 opp-2 { 4953 opp-peak-kBps = <9155000>; 4954 }; 4955 4956 opp-3 { 4957 opp-peak-kBps = <12298000>; 4958 }; 4959 4960 opp-4 { 4961 opp-peak-kBps = <14236000>; 4962 }; 4963 4964 opp-5 { 4965 opp-peak-kBps = <16265000>; 4966 }; 4967 }; 4968 }; 4969 4970 gem_noc: interconnect@24100000 { 4971 compatible = "qcom,sm8650-gem-noc"; 4972 reg = <0 0x24100000 0 0xc5080>; 4973 4974 qcom,bcm-voters = <&apps_bcm_voter>; 4975 4976 #interconnect-cells = <2>; 4977 }; 4978 4979 system-cache-controller@25000000 { 4980 compatible = "qcom,sm8650-llcc"; 4981 reg = <0 0x25000000 0 0x200000>, 4982 <0 0x25400000 0 0x200000>, 4983 <0 0x25200000 0 0x200000>, 4984 <0 0x25600000 0 0x200000>, 4985 <0 0x25800000 0 0x200000>; 4986 reg-names = "llcc0_base", 4987 "llcc1_base", 4988 "llcc2_base", 4989 "llcc3_base", 4990 "llcc_broadcast_base"; 4991 4992 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4993 }; 4994 4995 remoteproc_adsp: remoteproc@30000000 { 4996 compatible = "qcom,sm8650-adsp-pas"; 4997 reg = <0 0x30000000 0 0x100>; 4998 4999 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 5000 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5001 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5002 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5003 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5004 interrupt-names = "wdog", 5005 "fatal", 5006 "ready", 5007 "handover", 5008 "stop-ack"; 5009 5010 clocks = <&rpmhcc RPMH_CXO_CLK>; 5011 clock-names = "xo"; 5012 5013 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 5014 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5015 5016 power-domains = <&rpmhpd RPMHPD_LCX>, 5017 <&rpmhpd RPMHPD_LMX>; 5018 power-domain-names = "lcx", 5019 "lmx"; 5020 5021 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 5022 5023 qcom,qmp = <&aoss_qmp>; 5024 5025 qcom,smem-states = <&smp2p_adsp_out 0>; 5026 qcom,smem-state-names = "stop"; 5027 5028 status = "disabled"; 5029 5030 remoteproc_adsp_glink: glink-edge { 5031 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5032 IPCC_MPROC_SIGNAL_GLINK_QMP 5033 IRQ_TYPE_EDGE_RISING>; 5034 5035 mboxes = <&ipcc IPCC_CLIENT_LPASS 5036 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5037 5038 qcom,remote-pid = <2>; 5039 5040 label = "lpass"; 5041 5042 fastrpc { 5043 compatible = "qcom,fastrpc"; 5044 5045 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5046 5047 label = "adsp"; 5048 5049 qcom,non-secure-domain; 5050 5051 #address-cells = <1>; 5052 #size-cells = <0>; 5053 5054 compute-cb@3 { 5055 compatible = "qcom,fastrpc-compute-cb"; 5056 reg = <3>; 5057 5058 iommus = <&apps_smmu 0x1003 0x80>, 5059 <&apps_smmu 0x1043 0x20>; 5060 dma-coherent; 5061 }; 5062 5063 compute-cb@4 { 5064 compatible = "qcom,fastrpc-compute-cb"; 5065 reg = <4>; 5066 5067 iommus = <&apps_smmu 0x1004 0x80>, 5068 <&apps_smmu 0x1044 0x20>; 5069 dma-coherent; 5070 }; 5071 5072 compute-cb@5 { 5073 compatible = "qcom,fastrpc-compute-cb"; 5074 reg = <5>; 5075 5076 iommus = <&apps_smmu 0x1005 0x80>, 5077 <&apps_smmu 0x1045 0x20>; 5078 dma-coherent; 5079 }; 5080 5081 compute-cb@6 { 5082 compatible = "qcom,fastrpc-compute-cb"; 5083 reg = <6>; 5084 5085 iommus = <&apps_smmu 0x1006 0x80>, 5086 <&apps_smmu 0x1046 0x20>; 5087 dma-coherent; 5088 }; 5089 5090 compute-cb@7 { 5091 compatible = "qcom,fastrpc-compute-cb"; 5092 reg = <7>; 5093 5094 iommus = <&apps_smmu 0x1007 0x40>, 5095 <&apps_smmu 0x1067 0x0>, 5096 <&apps_smmu 0x1087 0x0>; 5097 dma-coherent; 5098 }; 5099 }; 5100 5101 gpr { 5102 compatible = "qcom,gpr"; 5103 qcom,glink-channels = "adsp_apps"; 5104 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 5105 qcom,intents = <512 20>; 5106 #address-cells = <1>; 5107 #size-cells = <0>; 5108 5109 q6apm: service@1 { 5110 compatible = "qcom,q6apm"; 5111 reg = <GPR_APM_MODULE_IID>; 5112 #sound-dai-cells = <0>; 5113 qcom,protection-domain = "avs/audio", 5114 "msm/adsp/audio_pd"; 5115 5116 q6apmbedai: bedais { 5117 compatible = "qcom,q6apm-lpass-dais"; 5118 #sound-dai-cells = <1>; 5119 }; 5120 5121 q6apmdai: dais { 5122 compatible = "qcom,q6apm-dais"; 5123 iommus = <&apps_smmu 0x1001 0x80>, 5124 <&apps_smmu 0x1061 0x0>; 5125 }; 5126 }; 5127 5128 q6prm: service@2 { 5129 compatible = "qcom,q6prm"; 5130 reg = <GPR_PRM_MODULE_IID>; 5131 qcom,protection-domain = "avs/audio", 5132 "msm/adsp/audio_pd"; 5133 5134 q6prmcc: clock-controller { 5135 compatible = "qcom,q6prm-lpass-clocks"; 5136 #clock-cells = <2>; 5137 }; 5138 }; 5139 }; 5140 }; 5141 }; 5142 5143 nsp_noc: interconnect@320c0000 { 5144 compatible = "qcom,sm8650-nsp-noc"; 5145 reg = <0 0x320c0000 0 0xf080>; 5146 5147 qcom,bcm-voters = <&apps_bcm_voter>; 5148 5149 #interconnect-cells = <2>; 5150 }; 5151 5152 remoteproc_cdsp: remoteproc@32300000 { 5153 compatible = "qcom,sm8650-cdsp-pas"; 5154 reg = <0 0x32300000 0 0x1400000>; 5155 5156 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5157 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 5158 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 5159 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 5160 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 5161 interrupt-names = "wdog", 5162 "fatal", 5163 "ready", 5164 "handover", 5165 "stop-ack"; 5166 5167 clocks = <&rpmhcc RPMH_CXO_CLK>; 5168 clock-names = "xo"; 5169 5170 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 5171 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5172 5173 power-domains = <&rpmhpd RPMHPD_CX>, 5174 <&rpmhpd RPMHPD_MXC>, 5175 <&rpmhpd RPMHPD_NSP>; 5176 power-domain-names = "cx", 5177 "mxc", 5178 "nsp"; 5179 5180 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; 5181 5182 qcom,qmp = <&aoss_qmp>; 5183 5184 qcom,smem-states = <&smp2p_cdsp_out 0>; 5185 qcom,smem-state-names = "stop"; 5186 5187 status = "disabled"; 5188 5189 glink-edge { 5190 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5191 IPCC_MPROC_SIGNAL_GLINK_QMP 5192 IRQ_TYPE_EDGE_RISING>; 5193 5194 mboxes = <&ipcc IPCC_CLIENT_CDSP 5195 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5196 5197 qcom,remote-pid = <5>; 5198 5199 label = "cdsp"; 5200 5201 fastrpc { 5202 compatible = "qcom,fastrpc"; 5203 5204 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5205 5206 label = "cdsp"; 5207 5208 qcom,non-secure-domain; 5209 5210 #address-cells = <1>; 5211 #size-cells = <0>; 5212 5213 compute-cb@1 { 5214 compatible = "qcom,fastrpc-compute-cb"; 5215 reg = <1>; 5216 5217 iommus = <&apps_smmu 0x1961 0x0>, 5218 <&apps_smmu 0x0c01 0x20>, 5219 <&apps_smmu 0x19c1 0x0>; 5220 dma-coherent; 5221 }; 5222 5223 compute-cb@2 { 5224 compatible = "qcom,fastrpc-compute-cb"; 5225 reg = <2>; 5226 5227 iommus = <&apps_smmu 0x1962 0x0>, 5228 <&apps_smmu 0x0c02 0x20>, 5229 <&apps_smmu 0x19c2 0x0>; 5230 dma-coherent; 5231 }; 5232 5233 compute-cb@3 { 5234 compatible = "qcom,fastrpc-compute-cb"; 5235 reg = <3>; 5236 5237 iommus = <&apps_smmu 0x1963 0x0>, 5238 <&apps_smmu 0x0c03 0x20>, 5239 <&apps_smmu 0x19c3 0x0>; 5240 dma-coherent; 5241 }; 5242 5243 compute-cb@4 { 5244 compatible = "qcom,fastrpc-compute-cb"; 5245 reg = <4>; 5246 5247 iommus = <&apps_smmu 0x1964 0x0>, 5248 <&apps_smmu 0x0c04 0x20>, 5249 <&apps_smmu 0x19c4 0x0>; 5250 dma-coherent; 5251 }; 5252 5253 compute-cb@5 { 5254 compatible = "qcom,fastrpc-compute-cb"; 5255 reg = <5>; 5256 5257 iommus = <&apps_smmu 0x1965 0x0>, 5258 <&apps_smmu 0x0c05 0x20>, 5259 <&apps_smmu 0x19c5 0x0>; 5260 dma-coherent; 5261 }; 5262 5263 compute-cb@6 { 5264 compatible = "qcom,fastrpc-compute-cb"; 5265 reg = <6>; 5266 5267 iommus = <&apps_smmu 0x1966 0x0>, 5268 <&apps_smmu 0x0c06 0x20>, 5269 <&apps_smmu 0x19c6 0x0>; 5270 dma-coherent; 5271 }; 5272 5273 compute-cb@7 { 5274 compatible = "qcom,fastrpc-compute-cb"; 5275 reg = <7>; 5276 5277 iommus = <&apps_smmu 0x1967 0x0>, 5278 <&apps_smmu 0x0c07 0x20>, 5279 <&apps_smmu 0x19c7 0x0>; 5280 dma-coherent; 5281 }; 5282 5283 compute-cb@8 { 5284 compatible = "qcom,fastrpc-compute-cb"; 5285 reg = <8>; 5286 5287 iommus = <&apps_smmu 0x1968 0x0>, 5288 <&apps_smmu 0x0c08 0x20>, 5289 <&apps_smmu 0x19c8 0x0>; 5290 dma-coherent; 5291 }; 5292 5293 /* note: secure cb9 in downstream */ 5294 5295 compute-cb@10 { 5296 compatible = "qcom,fastrpc-compute-cb"; 5297 reg = <12>; 5298 5299 iommus = <&apps_smmu 0x196c 0x0>, 5300 <&apps_smmu 0x0c0c 0x20>, 5301 <&apps_smmu 0x19cc 0x0>; 5302 dma-coherent; 5303 }; 5304 5305 compute-cb@11 { 5306 compatible = "qcom,fastrpc-compute-cb"; 5307 reg = <13>; 5308 5309 iommus = <&apps_smmu 0x196d 0x0>, 5310 <&apps_smmu 0x0c0d 0x20>, 5311 <&apps_smmu 0x19cd 0x0>; 5312 dma-coherent; 5313 }; 5314 5315 compute-cb@12 { 5316 compatible = "qcom,fastrpc-compute-cb"; 5317 reg = <14>; 5318 5319 iommus = <&apps_smmu 0x196e 0x0>, 5320 <&apps_smmu 0x0c0e 0x20>, 5321 <&apps_smmu 0x19ce 0x0>; 5322 dma-coherent; 5323 }; 5324 }; 5325 }; 5326 }; 5327 }; 5328 5329 thermal-zones { 5330 aoss0-thermal { 5331 polling-delay-passive = <0>; 5332 polling-delay = <0>; 5333 thermal-sensors = <&tsens0 0>; 5334 5335 trips { 5336 trip-point0 { 5337 temperature = <90000>; 5338 hysteresis = <2000>; 5339 type = "hot"; 5340 }; 5341 5342 aoss0-critical { 5343 temperature = <110000>; 5344 hysteresis = <0>; 5345 type = "critical"; 5346 }; 5347 }; 5348 }; 5349 5350 cpuss0-thermal { 5351 polling-delay-passive = <0>; 5352 polling-delay = <0>; 5353 thermal-sensors = <&tsens0 1>; 5354 5355 trips { 5356 trip-point0 { 5357 temperature = <90000>; 5358 hysteresis = <2000>; 5359 type = "hot"; 5360 }; 5361 5362 cpuss0-critical { 5363 temperature = <110000>; 5364 hysteresis = <0>; 5365 type = "critical"; 5366 }; 5367 }; 5368 }; 5369 5370 cpuss1-thermal { 5371 polling-delay-passive = <0>; 5372 polling-delay = <0>; 5373 thermal-sensors = <&tsens0 2>; 5374 5375 trips { 5376 trip-point0 { 5377 temperature = <90000>; 5378 hysteresis = <2000>; 5379 type = "hot"; 5380 }; 5381 5382 cpuss1-critical { 5383 temperature = <110000>; 5384 hysteresis = <0>; 5385 type = "critical"; 5386 }; 5387 }; 5388 }; 5389 5390 cpuss2-thermal { 5391 polling-delay-passive = <0>; 5392 polling-delay = <0>; 5393 thermal-sensors = <&tsens0 3>; 5394 5395 trips { 5396 trip-point0 { 5397 temperature = <90000>; 5398 hysteresis = <2000>; 5399 type = "hot"; 5400 }; 5401 5402 cpuss2-critical { 5403 temperature = <110000>; 5404 hysteresis = <0>; 5405 type = "critical"; 5406 }; 5407 }; 5408 }; 5409 5410 cpuss3-thermal { 5411 polling-delay-passive = <0>; 5412 polling-delay = <0>; 5413 thermal-sensors = <&tsens0 4>; 5414 5415 trips { 5416 trip-point0 { 5417 temperature = <90000>; 5418 hysteresis = <2000>; 5419 type = "hot"; 5420 }; 5421 5422 cpuss3-critical { 5423 temperature = <110000>; 5424 hysteresis = <0>; 5425 type = "critical"; 5426 }; 5427 }; 5428 }; 5429 5430 cpu2-top-thermal { 5431 polling-delay-passive = <0>; 5432 polling-delay = <0>; 5433 thermal-sensors = <&tsens0 5>; 5434 5435 trips { 5436 trip-point0 { 5437 temperature = <90000>; 5438 hysteresis = <2000>; 5439 type = "passive"; 5440 }; 5441 5442 trip-point1 { 5443 temperature = <95000>; 5444 hysteresis = <2000>; 5445 type = "passive"; 5446 }; 5447 5448 cpu2-critical { 5449 temperature = <110000>; 5450 hysteresis = <1000>; 5451 type = "critical"; 5452 }; 5453 }; 5454 }; 5455 5456 cpu2-bottom-thermal { 5457 polling-delay-passive = <0>; 5458 polling-delay = <0>; 5459 thermal-sensors = <&tsens0 6>; 5460 5461 trips { 5462 trip-point0 { 5463 temperature = <90000>; 5464 hysteresis = <2000>; 5465 type = "passive"; 5466 }; 5467 5468 trip-point1 { 5469 temperature = <95000>; 5470 hysteresis = <2000>; 5471 type = "passive"; 5472 }; 5473 5474 cpu2-critical { 5475 temperature = <110000>; 5476 hysteresis = <1000>; 5477 type = "critical"; 5478 }; 5479 }; 5480 }; 5481 5482 cpu3-top-thermal { 5483 polling-delay-passive = <0>; 5484 polling-delay = <0>; 5485 thermal-sensors = <&tsens0 7>; 5486 5487 trips { 5488 trip-point0 { 5489 temperature = <90000>; 5490 hysteresis = <2000>; 5491 type = "passive"; 5492 }; 5493 5494 trip-point1 { 5495 temperature = <95000>; 5496 hysteresis = <2000>; 5497 type = "passive"; 5498 }; 5499 5500 cpu3-critical { 5501 temperature = <110000>; 5502 hysteresis = <1000>; 5503 type = "critical"; 5504 }; 5505 }; 5506 }; 5507 5508 cpu3-bottom-thermal { 5509 polling-delay-passive = <0>; 5510 polling-delay = <0>; 5511 thermal-sensors = <&tsens0 8>; 5512 5513 trips { 5514 trip-point0 { 5515 temperature = <90000>; 5516 hysteresis = <2000>; 5517 type = "passive"; 5518 }; 5519 5520 trip-point1 { 5521 temperature = <95000>; 5522 hysteresis = <2000>; 5523 type = "passive"; 5524 }; 5525 5526 cpu3-critical { 5527 temperature = <110000>; 5528 hysteresis = <1000>; 5529 type = "critical"; 5530 }; 5531 }; 5532 }; 5533 5534 cpu4-top-thermal { 5535 polling-delay-passive = <0>; 5536 polling-delay = <0>; 5537 thermal-sensors = <&tsens0 9>; 5538 5539 trips { 5540 trip-point0 { 5541 temperature = <90000>; 5542 hysteresis = <2000>; 5543 type = "passive"; 5544 }; 5545 5546 trip-point1 { 5547 temperature = <95000>; 5548 hysteresis = <2000>; 5549 type = "passive"; 5550 }; 5551 5552 cpu4-critical { 5553 temperature = <110000>; 5554 hysteresis = <1000>; 5555 type = "critical"; 5556 }; 5557 }; 5558 }; 5559 5560 cpu4-bottom-thermal { 5561 polling-delay-passive = <0>; 5562 polling-delay = <0>; 5563 thermal-sensors = <&tsens0 10>; 5564 5565 trips { 5566 trip-point0 { 5567 temperature = <90000>; 5568 hysteresis = <2000>; 5569 type = "passive"; 5570 }; 5571 5572 trip-point1 { 5573 temperature = <95000>; 5574 hysteresis = <2000>; 5575 type = "passive"; 5576 }; 5577 5578 cpu4-critical { 5579 temperature = <110000>; 5580 hysteresis = <1000>; 5581 type = "critical"; 5582 }; 5583 }; 5584 }; 5585 5586 cpu5-top-thermal { 5587 polling-delay-passive = <0>; 5588 polling-delay = <0>; 5589 thermal-sensors = <&tsens0 11>; 5590 5591 trips { 5592 trip-point0 { 5593 temperature = <90000>; 5594 hysteresis = <2000>; 5595 type = "passive"; 5596 }; 5597 5598 trip-point1 { 5599 temperature = <95000>; 5600 hysteresis = <2000>; 5601 type = "passive"; 5602 }; 5603 5604 cpu5-critical { 5605 temperature = <110000>; 5606 hysteresis = <1000>; 5607 type = "critical"; 5608 }; 5609 }; 5610 }; 5611 5612 cpu5-bottom-thermal { 5613 polling-delay-passive = <0>; 5614 polling-delay = <0>; 5615 thermal-sensors = <&tsens0 12>; 5616 5617 trips { 5618 trip-point0 { 5619 temperature = <90000>; 5620 hysteresis = <2000>; 5621 type = "passive"; 5622 }; 5623 5624 trip-point1 { 5625 temperature = <95000>; 5626 hysteresis = <2000>; 5627 type = "passive"; 5628 }; 5629 5630 cpu5-critical { 5631 temperature = <110000>; 5632 hysteresis = <1000>; 5633 type = "critical"; 5634 }; 5635 }; 5636 }; 5637 5638 cpu6-top-thermal { 5639 polling-delay-passive = <0>; 5640 polling-delay = <0>; 5641 thermal-sensors = <&tsens0 13>; 5642 5643 trips { 5644 trip-point0 { 5645 temperature = <90000>; 5646 hysteresis = <2000>; 5647 type = "passive"; 5648 }; 5649 5650 trip-point1 { 5651 temperature = <95000>; 5652 hysteresis = <2000>; 5653 type = "passive"; 5654 }; 5655 5656 cpu6-critical { 5657 temperature = <110000>; 5658 hysteresis = <1000>; 5659 type = "critical"; 5660 }; 5661 }; 5662 }; 5663 5664 cpu6-bottom-thermal { 5665 polling-delay-passive = <0>; 5666 polling-delay = <0>; 5667 thermal-sensors = <&tsens0 14>; 5668 5669 trips { 5670 trip-point0 { 5671 temperature = <90000>; 5672 hysteresis = <2000>; 5673 type = "passive"; 5674 }; 5675 5676 trip-point1 { 5677 temperature = <95000>; 5678 hysteresis = <2000>; 5679 type = "passive"; 5680 }; 5681 5682 cpu6-critical { 5683 temperature = <110000>; 5684 hysteresis = <1000>; 5685 type = "critical"; 5686 }; 5687 }; 5688 }; 5689 5690 aoss1-thermal { 5691 polling-delay-passive = <0>; 5692 polling-delay = <0>; 5693 thermal-sensors = <&tsens1 0>; 5694 5695 trips { 5696 trip-point0 { 5697 temperature = <90000>; 5698 hysteresis = <2000>; 5699 type = "hot"; 5700 }; 5701 5702 aoss1-critical { 5703 temperature = <110000>; 5704 hysteresis = <0>; 5705 type = "critical"; 5706 }; 5707 }; 5708 }; 5709 5710 cpu7-top-thermal { 5711 polling-delay-passive = <0>; 5712 polling-delay = <0>; 5713 thermal-sensors = <&tsens1 1>; 5714 5715 trips { 5716 trip-point0 { 5717 temperature = <90000>; 5718 hysteresis = <2000>; 5719 type = "passive"; 5720 }; 5721 5722 trip-point1 { 5723 temperature = <95000>; 5724 hysteresis = <2000>; 5725 type = "passive"; 5726 }; 5727 5728 cpu7-critical { 5729 temperature = <110000>; 5730 hysteresis = <1000>; 5731 type = "critical"; 5732 }; 5733 }; 5734 }; 5735 5736 cpu7-middle-thermal { 5737 polling-delay-passive = <0>; 5738 polling-delay = <0>; 5739 thermal-sensors = <&tsens1 2>; 5740 5741 trips { 5742 trip-point0 { 5743 temperature = <90000>; 5744 hysteresis = <2000>; 5745 type = "passive"; 5746 }; 5747 5748 trip-point1 { 5749 temperature = <95000>; 5750 hysteresis = <2000>; 5751 type = "passive"; 5752 }; 5753 5754 cpu7-critical { 5755 temperature = <110000>; 5756 hysteresis = <1000>; 5757 type = "critical"; 5758 }; 5759 }; 5760 }; 5761 5762 cpu7-bottom-thermal { 5763 polling-delay-passive = <0>; 5764 polling-delay = <0>; 5765 thermal-sensors = <&tsens1 3>; 5766 5767 trips { 5768 trip-point0 { 5769 temperature = <90000>; 5770 hysteresis = <2000>; 5771 type = "passive"; 5772 }; 5773 5774 trip-point1 { 5775 temperature = <95000>; 5776 hysteresis = <2000>; 5777 type = "passive"; 5778 }; 5779 5780 cpu7-critical { 5781 temperature = <110000>; 5782 hysteresis = <1000>; 5783 type = "critical"; 5784 }; 5785 }; 5786 }; 5787 5788 cpu0-thermal { 5789 polling-delay-passive = <0>; 5790 polling-delay = <0>; 5791 thermal-sensors = <&tsens1 4>; 5792 5793 trips { 5794 trip-point0 { 5795 temperature = <90000>; 5796 hysteresis = <2000>; 5797 type = "passive"; 5798 }; 5799 5800 trip-point1 { 5801 temperature = <95000>; 5802 hysteresis = <2000>; 5803 type = "passive"; 5804 }; 5805 5806 cpu0-critical { 5807 temperature = <110000>; 5808 hysteresis = <1000>; 5809 type = "critical"; 5810 }; 5811 }; 5812 }; 5813 5814 cpu1-thermal { 5815 polling-delay-passive = <0>; 5816 polling-delay = <0>; 5817 thermal-sensors = <&tsens1 5>; 5818 5819 trips { 5820 trip-point0 { 5821 temperature = <90000>; 5822 hysteresis = <2000>; 5823 type = "passive"; 5824 }; 5825 5826 trip-point1 { 5827 temperature = <95000>; 5828 hysteresis = <2000>; 5829 type = "passive"; 5830 }; 5831 5832 cpu1-critical { 5833 temperature = <110000>; 5834 hysteresis = <1000>; 5835 type = "critical"; 5836 }; 5837 }; 5838 }; 5839 5840 nsphvx0-thermal { 5841 polling-delay-passive = <10>; 5842 polling-delay = <0>; 5843 thermal-sensors = <&tsens2 6>; 5844 5845 trips { 5846 trip-point0 { 5847 temperature = <90000>; 5848 hysteresis = <2000>; 5849 type = "hot"; 5850 }; 5851 5852 nsphvx1-critical { 5853 temperature = <110000>; 5854 hysteresis = <0>; 5855 type = "critical"; 5856 }; 5857 }; 5858 }; 5859 5860 nsphvx1-thermal { 5861 polling-delay-passive = <10>; 5862 polling-delay = <0>; 5863 thermal-sensors = <&tsens2 7>; 5864 5865 trips { 5866 trip-point0 { 5867 temperature = <90000>; 5868 hysteresis = <2000>; 5869 type = "hot"; 5870 }; 5871 5872 nsphvx1-critical { 5873 temperature = <110000>; 5874 hysteresis = <0>; 5875 type = "critical"; 5876 }; 5877 }; 5878 }; 5879 5880 nsphmx0-thermal { 5881 polling-delay-passive = <10>; 5882 polling-delay = <0>; 5883 thermal-sensors = <&tsens2 8>; 5884 5885 trips { 5886 trip-point0 { 5887 temperature = <90000>; 5888 hysteresis = <2000>; 5889 type = "hot"; 5890 }; 5891 5892 nsphmx0-critical { 5893 temperature = <110000>; 5894 hysteresis = <0>; 5895 type = "critical"; 5896 }; 5897 }; 5898 }; 5899 5900 nsphmx1-thermal { 5901 polling-delay-passive = <10>; 5902 polling-delay = <0>; 5903 thermal-sensors = <&tsens2 9>; 5904 5905 trips { 5906 trip-point0 { 5907 temperature = <90000>; 5908 hysteresis = <2000>; 5909 type = "hot"; 5910 }; 5911 5912 nsphmx1-critical { 5913 temperature = <110000>; 5914 hysteresis = <0>; 5915 type = "critical"; 5916 }; 5917 }; 5918 }; 5919 5920 nsphmx2-thermal { 5921 polling-delay-passive = <10>; 5922 polling-delay = <0>; 5923 thermal-sensors = <&tsens2 10>; 5924 5925 trips { 5926 trip-point0 { 5927 temperature = <90000>; 5928 hysteresis = <2000>; 5929 type = "hot"; 5930 }; 5931 5932 nsphmx2-critical { 5933 temperature = <110000>; 5934 hysteresis = <0>; 5935 type = "critical"; 5936 }; 5937 }; 5938 }; 5939 5940 nsphmx3-thermal { 5941 polling-delay-passive = <10>; 5942 polling-delay = <0>; 5943 thermal-sensors = <&tsens2 11>; 5944 5945 trips { 5946 trip-point0 { 5947 temperature = <90000>; 5948 hysteresis = <2000>; 5949 type = "hot"; 5950 }; 5951 5952 nsphmx3-critical { 5953 temperature = <110000>; 5954 hysteresis = <0>; 5955 type = "critical"; 5956 }; 5957 }; 5958 }; 5959 5960 video-thermal { 5961 polling-delay-passive = <10>; 5962 polling-delay = <0>; 5963 thermal-sensors = <&tsens1 12>; 5964 5965 trips { 5966 trip-point0 { 5967 temperature = <90000>; 5968 hysteresis = <2000>; 5969 type = "hot"; 5970 }; 5971 5972 video-critical { 5973 temperature = <110000>; 5974 hysteresis = <0>; 5975 type = "critical"; 5976 }; 5977 }; 5978 }; 5979 5980 ddr-thermal { 5981 polling-delay-passive = <10>; 5982 polling-delay = <0>; 5983 thermal-sensors = <&tsens1 13>; 5984 5985 trips { 5986 trip-point0 { 5987 temperature = <90000>; 5988 hysteresis = <2000>; 5989 type = "hot"; 5990 }; 5991 5992 ddr-critical { 5993 temperature = <110000>; 5994 hysteresis = <0>; 5995 type = "critical"; 5996 }; 5997 }; 5998 }; 5999 6000 camera0-thermal { 6001 polling-delay-passive = <0>; 6002 polling-delay = <0>; 6003 thermal-sensors = <&tsens1 14>; 6004 6005 trips { 6006 trip-point0 { 6007 temperature = <90000>; 6008 hysteresis = <2000>; 6009 type = "hot"; 6010 }; 6011 6012 camera0-critical { 6013 temperature = <110000>; 6014 hysteresis = <0>; 6015 type = "critical"; 6016 }; 6017 }; 6018 }; 6019 6020 camera1-thermal { 6021 polling-delay-passive = <0>; 6022 polling-delay = <0>; 6023 thermal-sensors = <&tsens1 15>; 6024 6025 trips { 6026 trip-point0 { 6027 temperature = <90000>; 6028 hysteresis = <2000>; 6029 type = "hot"; 6030 }; 6031 6032 camera1-critical { 6033 temperature = <110000>; 6034 hysteresis = <0>; 6035 type = "critical"; 6036 }; 6037 }; 6038 }; 6039 6040 aoss2-thermal { 6041 polling-delay-passive = <0>; 6042 polling-delay = <0>; 6043 thermal-sensors = <&tsens2 0>; 6044 6045 trips { 6046 trip-point0 { 6047 temperature = <90000>; 6048 hysteresis = <2000>; 6049 type = "hot"; 6050 }; 6051 6052 aoss2-critical { 6053 temperature = <110000>; 6054 hysteresis = <0>; 6055 type = "critical"; 6056 }; 6057 }; 6058 }; 6059 6060 gpuss0-thermal { 6061 polling-delay-passive = <10>; 6062 polling-delay = <0>; 6063 thermal-sensors = <&tsens2 1>; 6064 6065 trips { 6066 trip-point0 { 6067 temperature = <90000>; 6068 hysteresis = <2000>; 6069 type = "hot"; 6070 }; 6071 6072 gpuss0-critical { 6073 temperature = <110000>; 6074 hysteresis = <0>; 6075 type = "critical"; 6076 }; 6077 }; 6078 }; 6079 6080 gpuss1-thermal { 6081 polling-delay-passive = <10>; 6082 polling-delay = <0>; 6083 thermal-sensors = <&tsens2 2>; 6084 6085 trips { 6086 trip-point0 { 6087 temperature = <90000>; 6088 hysteresis = <2000>; 6089 type = "hot"; 6090 }; 6091 6092 gpuss1-critical { 6093 temperature = <110000>; 6094 hysteresis = <0>; 6095 type = "critical"; 6096 }; 6097 }; 6098 }; 6099 6100 gpuss2-thermal { 6101 polling-delay-passive = <10>; 6102 polling-delay = <0>; 6103 thermal-sensors = <&tsens2 3>; 6104 6105 trips { 6106 trip-point0 { 6107 temperature = <90000>; 6108 hysteresis = <2000>; 6109 type = "hot"; 6110 }; 6111 6112 gpuss2-critical { 6113 temperature = <110000>; 6114 hysteresis = <0>; 6115 type = "critical"; 6116 }; 6117 }; 6118 }; 6119 6120 gpuss3-thermal { 6121 polling-delay-passive = <10>; 6122 polling-delay = <0>; 6123 thermal-sensors = <&tsens2 4>; 6124 6125 trips { 6126 trip-point0 { 6127 temperature = <90000>; 6128 hysteresis = <2000>; 6129 type = "hot"; 6130 }; 6131 6132 gpuss3-critical { 6133 temperature = <110000>; 6134 hysteresis = <0>; 6135 type = "critical"; 6136 }; 6137 }; 6138 }; 6139 6140 gpuss4-thermal { 6141 polling-delay-passive = <10>; 6142 polling-delay = <0>; 6143 thermal-sensors = <&tsens2 5>; 6144 6145 trips { 6146 trip-point0 { 6147 temperature = <90000>; 6148 hysteresis = <2000>; 6149 type = "hot"; 6150 }; 6151 6152 gpuss4-critical { 6153 temperature = <110000>; 6154 hysteresis = <0>; 6155 type = "critical"; 6156 }; 6157 }; 6158 }; 6159 6160 gpuss5-thermal { 6161 polling-delay-passive = <10>; 6162 polling-delay = <0>; 6163 thermal-sensors = <&tsens2 6>; 6164 6165 trips { 6166 trip-point0 { 6167 temperature = <90000>; 6168 hysteresis = <2000>; 6169 type = "hot"; 6170 }; 6171 6172 gpuss5-critical { 6173 temperature = <110000>; 6174 hysteresis = <0>; 6175 type = "critical"; 6176 }; 6177 }; 6178 }; 6179 6180 gpuss6-thermal { 6181 polling-delay-passive = <10>; 6182 polling-delay = <0>; 6183 thermal-sensors = <&tsens2 7>; 6184 6185 trips { 6186 trip-point0 { 6187 temperature = <90000>; 6188 hysteresis = <2000>; 6189 type = "hot"; 6190 }; 6191 6192 gpuss6-critical { 6193 temperature = <110000>; 6194 hysteresis = <0>; 6195 type = "critical"; 6196 }; 6197 }; 6198 }; 6199 6200 gpuss7-thermal { 6201 polling-delay-passive = <10>; 6202 polling-delay = <0>; 6203 thermal-sensors = <&tsens2 8>; 6204 6205 trips { 6206 trip-point0 { 6207 temperature = <90000>; 6208 hysteresis = <2000>; 6209 type = "hot"; 6210 }; 6211 6212 gpuss7-critical { 6213 temperature = <110000>; 6214 hysteresis = <0>; 6215 type = "critical"; 6216 }; 6217 }; 6218 }; 6219 6220 modem0-thermal { 6221 polling-delay-passive = <0>; 6222 polling-delay = <0>; 6223 thermal-sensors = <&tsens2 9>; 6224 6225 trips { 6226 trip-point0 { 6227 temperature = <90000>; 6228 hysteresis = <2000>; 6229 type = "hot"; 6230 }; 6231 6232 modem0-critical { 6233 temperature = <110000>; 6234 hysteresis = <0>; 6235 type = "critical"; 6236 }; 6237 }; 6238 }; 6239 6240 modem1-thermal { 6241 polling-delay-passive = <0>; 6242 polling-delay = <0>; 6243 thermal-sensors = <&tsens2 10>; 6244 6245 trips { 6246 trip-point0 { 6247 temperature = <90000>; 6248 hysteresis = <2000>; 6249 type = "hot"; 6250 }; 6251 6252 modem1-critical { 6253 temperature = <110000>; 6254 hysteresis = <0>; 6255 type = "critical"; 6256 }; 6257 }; 6258 }; 6259 6260 modem2-thermal { 6261 polling-delay-passive = <0>; 6262 polling-delay = <0>; 6263 thermal-sensors = <&tsens2 11>; 6264 6265 trips { 6266 trip-point0 { 6267 temperature = <90000>; 6268 hysteresis = <2000>; 6269 type = "hot"; 6270 }; 6271 6272 modem2-critical { 6273 temperature = <110000>; 6274 hysteresis = <0>; 6275 type = "critical"; 6276 }; 6277 }; 6278 }; 6279 6280 modem3-thermal { 6281 polling-delay-passive = <0>; 6282 polling-delay = <0>; 6283 thermal-sensors = <&tsens2 12>; 6284 6285 trips { 6286 trip-point0 { 6287 temperature = <90000>; 6288 hysteresis = <2000>; 6289 type = "hot"; 6290 }; 6291 6292 modem3-critical { 6293 temperature = <110000>; 6294 hysteresis = <0>; 6295 type = "critical"; 6296 }; 6297 }; 6298 }; 6299 }; 6300 6301 timer { 6302 compatible = "arm,armv8-timer"; 6303 6304 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6305 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6306 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6307 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6308 }; 6309}; 6310