1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sm8650-camcc.h> 9#include <dt-bindings/clock/qcom,sm8650-dispcc.h> 10#include <dt-bindings/clock/qcom,sm8650-gcc.h> 11#include <dt-bindings/clock/qcom,sm8650-gpucc.h> 12#include <dt-bindings/clock/qcom,sm8650-tcsr.h> 13#include <dt-bindings/clock/qcom,sm8650-videocc.h> 14#include <dt-bindings/dma/qcom-gpi.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,icc.h> 18#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> 19#include <dt-bindings/interconnect/qcom,osm-l3.h> 20#include <dt-bindings/interrupt-controller/arm-gic.h> 21#include <dt-bindings/mailbox/qcom-ipcc.h> 22#include <dt-bindings/phy/phy-qcom-qmp.h> 23#include <dt-bindings/power/qcom,rpmhpd.h> 24#include <dt-bindings/power/qcom-rpmpd.h> 25#include <dt-bindings/reset/qcom,sm8650-gpucc.h> 26#include <dt-bindings/soc/qcom,gpr.h> 27#include <dt-bindings/soc/qcom,rpmh-rsc.h> 28#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 29#include <dt-bindings/thermal/thermal.h> 30 31/ { 32 interrupt-parent = <&intc>; 33 34 #address-cells = <2>; 35 #size-cells = <2>; 36 37 chosen { }; 38 39 clocks { 40 xo_board: xo-board { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 }; 44 45 sleep_clk: sleep-clk { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 }; 49 50 bi_tcxo_div2: bi-tcxo-div2-clk { 51 compatible = "fixed-factor-clock"; 52 #clock-cells = <0>; 53 54 clocks = <&rpmhcc RPMH_CXO_CLK>; 55 clock-mult = <1>; 56 clock-div = <2>; 57 }; 58 59 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 60 compatible = "fixed-factor-clock"; 61 #clock-cells = <0>; 62 63 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 64 clock-mult = <1>; 65 clock-div = <2>; 66 }; 67 }; 68 69 cpus { 70 #address-cells = <2>; 71 #size-cells = <0>; 72 73 cpu0: cpu@0 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a520"; 76 reg = <0 0>; 77 78 clocks = <&cpufreq_hw 0>; 79 80 power-domains = <&cpu_pd0>; 81 power-domain-names = "psci"; 82 83 enable-method = "psci"; 84 next-level-cache = <&l2_0>; 85 capacity-dmips-mhz = <1024>; 86 dynamic-power-coefficient = <100>; 87 88 qcom,freq-domain = <&cpufreq_hw 0>; 89 90 operating-points-v2 = <&cpu0_opp_table>; 91 92 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 93 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 94 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 95 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 96 <&epss_l3 MASTER_EPSS_L3_APPS 97 &epss_l3 SLAVE_EPSS_L3_SHARED>; 98 99 #cooling-cells = <2>; 100 101 l2_0: l2-cache { 102 compatible = "cache"; 103 cache-level = <2>; 104 cache-unified; 105 next-level-cache = <&l3_0>; 106 107 l3_0: l3-cache { 108 compatible = "cache"; 109 cache-level = <3>; 110 cache-unified; 111 }; 112 }; 113 }; 114 115 cpu1: cpu@100 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a520"; 118 reg = <0 0x100>; 119 120 clocks = <&cpufreq_hw 0>; 121 122 power-domains = <&cpu_pd1>; 123 power-domain-names = "psci"; 124 125 enable-method = "psci"; 126 next-level-cache = <&l2_0>; 127 capacity-dmips-mhz = <1024>; 128 dynamic-power-coefficient = <100>; 129 130 qcom,freq-domain = <&cpufreq_hw 0>; 131 132 operating-points-v2 = <&cpu0_opp_table>; 133 134 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 135 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 136 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 137 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 138 <&epss_l3 MASTER_EPSS_L3_APPS 139 &epss_l3 SLAVE_EPSS_L3_SHARED>; 140 141 #cooling-cells = <2>; 142 }; 143 144 cpu2: cpu@200 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-a720"; 147 reg = <0 0x200>; 148 149 clocks = <&cpufreq_hw 3>; 150 151 power-domains = <&cpu_pd2>; 152 power-domain-names = "psci"; 153 154 enable-method = "psci"; 155 next-level-cache = <&l2_200>; 156 capacity-dmips-mhz = <1792>; 157 dynamic-power-coefficient = <238>; 158 159 qcom,freq-domain = <&cpufreq_hw 3>; 160 161 operating-points-v2 = <&cpu2_opp_table>; 162 163 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 164 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 165 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 166 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 167 <&epss_l3 MASTER_EPSS_L3_APPS 168 &epss_l3 SLAVE_EPSS_L3_SHARED>; 169 170 #cooling-cells = <2>; 171 172 l2_200: l2-cache { 173 compatible = "cache"; 174 cache-level = <2>; 175 cache-unified; 176 next-level-cache = <&l3_0>; 177 }; 178 }; 179 180 cpu3: cpu@300 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a720"; 183 reg = <0 0x300>; 184 185 clocks = <&cpufreq_hw 3>; 186 187 power-domains = <&cpu_pd3>; 188 power-domain-names = "psci"; 189 190 enable-method = "psci"; 191 next-level-cache = <&l2_300>; 192 capacity-dmips-mhz = <1792>; 193 dynamic-power-coefficient = <238>; 194 195 qcom,freq-domain = <&cpufreq_hw 3>; 196 197 operating-points-v2 = <&cpu2_opp_table>; 198 199 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 200 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 201 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 203 <&epss_l3 MASTER_EPSS_L3_APPS 204 &epss_l3 SLAVE_EPSS_L3_SHARED>; 205 206 #cooling-cells = <2>; 207 208 l2_300: l2-cache { 209 compatible = "cache"; 210 cache-level = <2>; 211 cache-unified; 212 next-level-cache = <&l3_0>; 213 }; 214 }; 215 216 cpu4: cpu@400 { 217 device_type = "cpu"; 218 compatible = "arm,cortex-a720"; 219 reg = <0 0x400>; 220 221 clocks = <&cpufreq_hw 3>; 222 223 power-domains = <&cpu_pd4>; 224 power-domain-names = "psci"; 225 226 enable-method = "psci"; 227 next-level-cache = <&l2_400>; 228 capacity-dmips-mhz = <1792>; 229 dynamic-power-coefficient = <238>; 230 231 qcom,freq-domain = <&cpufreq_hw 3>; 232 233 operating-points-v2 = <&cpu2_opp_table>; 234 235 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 236 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 237 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 238 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 239 <&epss_l3 MASTER_EPSS_L3_APPS 240 &epss_l3 SLAVE_EPSS_L3_SHARED>; 241 242 #cooling-cells = <2>; 243 244 l2_400: l2-cache { 245 compatible = "cache"; 246 cache-level = <2>; 247 cache-unified; 248 next-level-cache = <&l3_0>; 249 }; 250 }; 251 252 cpu5: cpu@500 { 253 device_type = "cpu"; 254 compatible = "arm,cortex-a720"; 255 reg = <0 0x500>; 256 257 clocks = <&cpufreq_hw 1>; 258 259 power-domains = <&cpu_pd5>; 260 power-domain-names = "psci"; 261 262 enable-method = "psci"; 263 next-level-cache = <&l2_500>; 264 capacity-dmips-mhz = <1792>; 265 dynamic-power-coefficient = <238>; 266 267 qcom,freq-domain = <&cpufreq_hw 1>; 268 269 operating-points-v2 = <&cpu5_opp_table>; 270 271 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 272 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 273 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 274 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 275 <&epss_l3 MASTER_EPSS_L3_APPS 276 &epss_l3 SLAVE_EPSS_L3_SHARED>; 277 278 #cooling-cells = <2>; 279 280 l2_500: l2-cache { 281 compatible = "cache"; 282 cache-level = <2>; 283 cache-unified; 284 next-level-cache = <&l3_0>; 285 }; 286 }; 287 288 cpu6: cpu@600 { 289 device_type = "cpu"; 290 compatible = "arm,cortex-a720"; 291 reg = <0 0x600>; 292 293 clocks = <&cpufreq_hw 1>; 294 295 power-domains = <&cpu_pd6>; 296 power-domain-names = "psci"; 297 298 enable-method = "psci"; 299 next-level-cache = <&l2_600>; 300 capacity-dmips-mhz = <1792>; 301 dynamic-power-coefficient = <238>; 302 303 qcom,freq-domain = <&cpufreq_hw 1>; 304 305 operating-points-v2 = <&cpu5_opp_table>; 306 307 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 308 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 309 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 310 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 311 <&epss_l3 MASTER_EPSS_L3_APPS 312 &epss_l3 SLAVE_EPSS_L3_SHARED>; 313 314 #cooling-cells = <2>; 315 316 l2_600: l2-cache { 317 compatible = "cache"; 318 cache-level = <2>; 319 cache-unified; 320 next-level-cache = <&l3_0>; 321 }; 322 }; 323 324 cpu7: cpu@700 { 325 device_type = "cpu"; 326 compatible = "arm,cortex-x4"; 327 reg = <0 0x700>; 328 329 clocks = <&cpufreq_hw 2>; 330 331 power-domains = <&cpu_pd7>; 332 power-domain-names = "psci"; 333 334 enable-method = "psci"; 335 next-level-cache = <&l2_700>; 336 capacity-dmips-mhz = <1894>; 337 dynamic-power-coefficient = <588>; 338 339 qcom,freq-domain = <&cpufreq_hw 2>; 340 341 operating-points-v2 = <&cpu7_opp_table>; 342 343 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 344 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 345 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 346 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 347 <&epss_l3 MASTER_EPSS_L3_APPS 348 &epss_l3 SLAVE_EPSS_L3_SHARED>; 349 350 #cooling-cells = <2>; 351 352 l2_700: l2-cache { 353 compatible = "cache"; 354 cache-level = <2>; 355 cache-unified; 356 next-level-cache = <&l3_0>; 357 }; 358 }; 359 360 cpu-map { 361 cluster0 { 362 core0 { 363 cpu = <&cpu0>; 364 }; 365 366 core1 { 367 cpu = <&cpu1>; 368 }; 369 370 core2 { 371 cpu = <&cpu2>; 372 }; 373 374 core3 { 375 cpu = <&cpu3>; 376 }; 377 378 core4 { 379 cpu = <&cpu4>; 380 }; 381 382 core5 { 383 cpu = <&cpu5>; 384 }; 385 386 core6 { 387 cpu = <&cpu6>; 388 }; 389 390 core7 { 391 cpu = <&cpu7>; 392 }; 393 }; 394 }; 395 396 idle-states { 397 entry-method = "psci"; 398 399 silver_cpu_sleep_0: cpu-sleep-0-0 { 400 compatible = "arm,idle-state"; 401 idle-state-name = "silver-rail-power-collapse"; 402 arm,psci-suspend-param = <0x40000004>; 403 entry-latency-us = <550>; 404 exit-latency-us = <750>; 405 min-residency-us = <6700>; 406 local-timer-stop; 407 }; 408 409 gold_cpu_sleep_0: cpu-sleep-1-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "gold-rail-power-collapse"; 412 arm,psci-suspend-param = <0x40000004>; 413 entry-latency-us = <600>; 414 exit-latency-us = <1300>; 415 min-residency-us = <8136>; 416 local-timer-stop; 417 }; 418 419 gold_plus_cpu_sleep_0: cpu-sleep-2-0 { 420 compatible = "arm,idle-state"; 421 idle-state-name = "gold-plus-rail-power-collapse"; 422 arm,psci-suspend-param = <0x40000004>; 423 entry-latency-us = <500>; 424 exit-latency-us = <1350>; 425 min-residency-us = <7480>; 426 local-timer-stop; 427 }; 428 }; 429 430 domain-idle-states { 431 cluster_sleep_0: cluster-sleep-0 { 432 compatible = "domain-idle-state"; 433 arm,psci-suspend-param = <0x41000044>; 434 entry-latency-us = <750>; 435 exit-latency-us = <2350>; 436 min-residency-us = <9144>; 437 }; 438 439 cluster_sleep_1: cluster-sleep-1 { 440 compatible = "domain-idle-state"; 441 arm,psci-suspend-param = <0x4100c344>; 442 entry-latency-us = <2800>; 443 exit-latency-us = <4400>; 444 min-residency-us = <10150>; 445 }; 446 }; 447 }; 448 449 ete-0 { 450 compatible = "arm,embedded-trace-extension"; 451 452 cpu = <&cpu0>; 453 454 out-ports { 455 port { 456 ete0_out_funnel_ete: endpoint { 457 remote-endpoint = <&funnel_ete_in_ete0>; 458 }; 459 }; 460 }; 461 }; 462 463 ete-1 { 464 compatible = "arm,embedded-trace-extension"; 465 466 cpu = <&cpu1>; 467 468 out-ports { 469 port { 470 ete1_out_funnel_ete: endpoint { 471 remote-endpoint = <&funnel_ete_in_ete1>; 472 }; 473 }; 474 }; 475 }; 476 477 ete-2 { 478 compatible = "arm,embedded-trace-extension"; 479 480 cpu = <&cpu2>; 481 482 out-ports { 483 port { 484 ete2_out_funnel_ete: endpoint { 485 remote-endpoint = <&funnel_ete_in_ete2>; 486 }; 487 }; 488 }; 489 }; 490 491 ete-3 { 492 compatible = "arm,embedded-trace-extension"; 493 494 cpu = <&cpu3>; 495 496 out-ports { 497 port { 498 ete3_out_funnel_ete: endpoint { 499 remote-endpoint = <&funnel_ete_in_ete3>; 500 }; 501 }; 502 }; 503 }; 504 505 ete-4 { 506 compatible = "arm,embedded-trace-extension"; 507 508 cpu = <&cpu4>; 509 510 out-ports { 511 port { 512 ete4_out_funnel_ete: endpoint { 513 remote-endpoint = <&funnel_ete_in_ete4>; 514 }; 515 }; 516 }; 517 }; 518 519 ete-5 { 520 compatible = "arm,embedded-trace-extension"; 521 522 cpu = <&cpu5>; 523 524 out-ports { 525 port { 526 ete5_out_funnel_ete: endpoint { 527 remote-endpoint = <&funnel_ete_in_ete5>; 528 }; 529 }; 530 }; 531 }; 532 533 ete-6 { 534 compatible = "arm,embedded-trace-extension"; 535 536 cpu = <&cpu6>; 537 538 out-ports { 539 port { 540 ete6_out_funnel_ete: endpoint { 541 remote-endpoint = <&funnel_ete_in_ete6>; 542 }; 543 }; 544 }; 545 }; 546 547 ete-7 { 548 compatible = "arm,embedded-trace-extension"; 549 550 cpu = <&cpu7>; 551 552 out-ports { 553 port { 554 ete7_out_funnel_ete: endpoint { 555 remote-endpoint = <&funnel_ete_in_ete7>; 556 }; 557 }; 558 }; 559 }; 560 561 funnel-ete { 562 compatible = "arm,coresight-static-funnel"; 563 564 in-ports { 565 #address-cells = <1>; 566 #size-cells = <0>; 567 568 port@0 { 569 reg = <0>; 570 571 funnel_ete_in_ete0: endpoint { 572 remote-endpoint = <&ete0_out_funnel_ete>; 573 }; 574 }; 575 576 port@1 { 577 reg = <1>; 578 579 funnel_ete_in_ete1: endpoint { 580 remote-endpoint = <&ete1_out_funnel_ete>; 581 }; 582 }; 583 584 port@2 { 585 reg = <2>; 586 587 funnel_ete_in_ete2: endpoint { 588 remote-endpoint = <&ete2_out_funnel_ete>; 589 }; 590 }; 591 592 port@3 { 593 reg = <3>; 594 595 funnel_ete_in_ete3: endpoint { 596 remote-endpoint = <&ete3_out_funnel_ete>; 597 }; 598 }; 599 600 port@4 { 601 reg = <4>; 602 603 funnel_ete_in_ete4: endpoint { 604 remote-endpoint = <&ete4_out_funnel_ete>; 605 }; 606 }; 607 608 port@5 { 609 reg = <5>; 610 611 funnel_ete_in_ete5: endpoint { 612 remote-endpoint = <&ete5_out_funnel_ete>; 613 }; 614 }; 615 616 port@6 { 617 reg = <6>; 618 619 funnel_ete_in_ete6: endpoint { 620 remote-endpoint = <&ete6_out_funnel_ete>; 621 }; 622 }; 623 624 port@7 { 625 reg = <7>; 626 627 funnel_ete_in_ete7: endpoint { 628 remote-endpoint = <&ete7_out_funnel_ete>; 629 }; 630 }; 631 }; 632 633 out-ports { 634 port { 635 funnel_ete_out_funnel_apss: endpoint { 636 remote-endpoint = <&funnel_apss_in_funnel_ete>; 637 }; 638 }; 639 }; 640 }; 641 642 firmware { 643 scm: scm { 644 compatible = "qcom,scm-sm8650", "qcom,scm"; 645 qcom,dload-mode = <&tcsr 0x19000>; 646 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 647 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 648 }; 649 }; 650 651 clk_virt: interconnect-0 { 652 compatible = "qcom,sm8650-clk-virt"; 653 #interconnect-cells = <2>; 654 qcom,bcm-voters = <&apps_bcm_voter>; 655 }; 656 657 mc_virt: interconnect-1 { 658 compatible = "qcom,sm8650-mc-virt"; 659 #interconnect-cells = <2>; 660 qcom,bcm-voters = <&apps_bcm_voter>; 661 }; 662 663 qup_opp_table_100mhz: opp-table-qup100mhz { 664 compatible = "operating-points-v2"; 665 666 opp-75000000 { 667 opp-hz = /bits/ 64 <75000000>; 668 required-opps = <&rpmhpd_opp_low_svs>; 669 }; 670 671 opp-100000000 { 672 opp-hz = /bits/ 64 <100000000>; 673 required-opps = <&rpmhpd_opp_svs>; 674 }; 675 }; 676 677 qup_opp_table_120mhz: opp-table-qup120mhz { 678 compatible = "operating-points-v2"; 679 680 opp-75000000 { 681 opp-hz = /bits/ 64 <75000000>; 682 required-opps = <&rpmhpd_opp_low_svs>; 683 }; 684 685 opp-120000000 { 686 opp-hz = /bits/ 64 <120000000>; 687 required-opps = <&rpmhpd_opp_svs>; 688 }; 689 }; 690 691 qup_opp_table_128mhz: opp-table-qup128mhz { 692 compatible = "operating-points-v2"; 693 694 opp-75000000 { 695 opp-hz = /bits/ 64 <75000000>; 696 required-opps = <&rpmhpd_opp_low_svs>; 697 }; 698 699 opp-128000000 { 700 opp-hz = /bits/ 64 <128000000>; 701 required-opps = <&rpmhpd_opp_svs>; 702 }; 703 }; 704 705 qup_opp_table_240mhz: opp-table-qup240mhz { 706 compatible = "operating-points-v2"; 707 708 opp-150000000 { 709 opp-hz = /bits/ 64 <150000000>; 710 required-opps = <&rpmhpd_opp_low_svs>; 711 }; 712 713 opp-240000000 { 714 opp-hz = /bits/ 64 <240000000>; 715 required-opps = <&rpmhpd_opp_svs>; 716 }; 717 }; 718 719 memory@a0000000 { 720 device_type = "memory"; 721 /* We expect the bootloader to fill in the size */ 722 reg = <0 0xa0000000 0 0>; 723 }; 724 725 cpu0_opp_table: opp-table-cpu0 { 726 compatible = "operating-points-v2"; 727 opp-shared; 728 729 opp-307200000 { 730 opp-hz = /bits/ 64 <307200000>; 731 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 732 }; 733 734 opp-364800000 { 735 opp-hz = /bits/ 64 <364800000>; 736 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 737 }; 738 739 opp-460800000 { 740 opp-hz = /bits/ 64 <460800000>; 741 opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>; 742 }; 743 744 opp-556800000 { 745 opp-hz = /bits/ 64 <556800000>; 746 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 747 }; 748 749 opp-672000000 { 750 opp-hz = /bits/ 64 <672000000>; 751 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 752 }; 753 754 opp-787200000 { 755 opp-hz = /bits/ 64 <787200000>; 756 opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>; 757 }; 758 759 opp-902400000 { 760 opp-hz = /bits/ 64 <902400000>; 761 opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>; 762 }; 763 764 opp-1017600000 { 765 opp-hz = /bits/ 64 <1017600000>; 766 opp-peak-kBps = <(466000 * 16) (547000 * 4) (940800 * 32)>; 767 }; 768 769 opp-1132800000 { 770 opp-hz = /bits/ 64 <1132800000>; 771 opp-peak-kBps = <(466000 * 16) (547000 * 4) (1036800 * 32)>; 772 }; 773 774 opp-1248000000 { 775 opp-hz = /bits/ 64 <1248000000>; 776 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1132800 * 32)>; 777 }; 778 779 opp-1344000000 { 780 opp-hz = /bits/ 64 <1344000000>; 781 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; 782 }; 783 784 opp-1440000000 { 785 opp-hz = /bits/ 64 <1440000000>; 786 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; 787 }; 788 789 opp-1459200000 { 790 opp-hz = /bits/ 64 <1459200000>; 791 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; 792 }; 793 794 opp-1536000000 { 795 opp-hz = /bits/ 64 <1536000000>; 796 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>; 797 }; 798 799 opp-1574400000 { 800 opp-hz = /bits/ 64 <1574400000>; 801 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>; 802 }; 803 804 opp-1651200000 { 805 opp-hz = /bits/ 64 <1651200000>; 806 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; 807 }; 808 809 opp-1689600000 { 810 opp-hz = /bits/ 64 <1689600000>; 811 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; 812 }; 813 814 opp-1747200000 { 815 opp-hz = /bits/ 64 <1747200000>; 816 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; 817 }; 818 819 opp-1804800000 { 820 opp-hz = /bits/ 64 <1804800000>; 821 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>; 822 }; 823 824 opp-1843200000 { 825 opp-hz = /bits/ 64 <1843200000>; 826 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>; 827 }; 828 829 opp-1920000000 { 830 opp-hz = /bits/ 64 <1920000000>; 831 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>; 832 }; 833 834 opp-1939200000 { 835 opp-hz = /bits/ 64 <1939200000>; 836 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>; 837 }; 838 839 opp-2035200000 { 840 opp-hz = /bits/ 64 <2035200000>; 841 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>; 842 }; 843 844 opp-2150400000 { 845 opp-hz = /bits/ 64 <2150400000>; 846 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>; 847 }; 848 849 opp-2265600000 { 850 opp-hz = /bits/ 64 <2265600000>; 851 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (2035200 * 32)>; 852 }; 853 }; 854 855 cpu2_opp_table: opp-table-cpu2 { 856 compatible = "operating-points-v2"; 857 opp-shared; 858 859 opp-460800000 { 860 opp-hz = /bits/ 64 <460800000>; 861 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 862 }; 863 864 opp-499200000 { 865 opp-hz = /bits/ 64 <499200000>; 866 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 867 }; 868 869 opp-576000000 { 870 opp-hz = /bits/ 64 <576000000>; 871 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 872 }; 873 874 opp-614400000 { 875 opp-hz = /bits/ 64 <614400000>; 876 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 877 }; 878 879 opp-691200000 { 880 opp-hz = /bits/ 64 <691200000>; 881 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 882 }; 883 884 opp-729600000 { 885 opp-hz = /bits/ 64 <729600000>; 886 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 887 }; 888 889 opp-806400000 { 890 opp-hz = /bits/ 64 <806400000>; 891 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 892 }; 893 894 opp-844800000 { 895 opp-hz = /bits/ 64 <844800000>; 896 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 897 }; 898 899 opp-902400000 { 900 opp-hz = /bits/ 64 <902400000>; 901 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 902 }; 903 904 opp-960000000 { 905 opp-hz = /bits/ 64 <960000000>; 906 opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>; 907 }; 908 909 opp-1036800000 { 910 opp-hz = /bits/ 64 <1036800000>; 911 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 912 }; 913 914 opp-1075200000 { 915 opp-hz = /bits/ 64 <1075200000>; 916 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 917 }; 918 919 opp-1152000000 { 920 opp-hz = /bits/ 64 <1152000000>; 921 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 922 }; 923 924 opp-1190400000 { 925 opp-hz = /bits/ 64 <1190400000>; 926 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; 927 }; 928 929 opp-1267200000 { 930 opp-hz = /bits/ 64 <1267200000>; 931 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 932 }; 933 934 opp-1286400000 { 935 opp-hz = /bits/ 64 <1286400000>; 936 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 937 }; 938 939 opp-1382400000 { 940 opp-hz = /bits/ 64 <1382400000>; 941 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 942 }; 943 944 opp-1401600000 { 945 opp-hz = /bits/ 64 <1401600000>; 946 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; 947 }; 948 949 opp-1497600000 { 950 opp-hz = /bits/ 64 <1497600000>; 951 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 952 }; 953 954 opp-1612800000 { 955 opp-hz = /bits/ 64 <1612800000>; 956 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 957 }; 958 959 opp-1708800000 { 960 opp-hz = /bits/ 64 <1708800000>; 961 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 962 }; 963 964 opp-1728000000 { 965 opp-hz = /bits/ 64 <1728000000>; 966 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 967 }; 968 969 opp-1824000000 { 970 opp-hz = /bits/ 64 <1824000000>; 971 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 972 }; 973 974 opp-1843200000 { 975 opp-hz = /bits/ 64 <1843200000>; 976 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 977 }; 978 979 opp-1920000000 { 980 opp-hz = /bits/ 64 <1920000000>; 981 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>; 982 }; 983 984 opp-1958400000 { 985 opp-hz = /bits/ 64 <1958400000>; 986 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 987 }; 988 989 opp-2035200000 { 990 opp-hz = /bits/ 64 <2035200000>; 991 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 992 }; 993 994 opp-2073600000 { 995 opp-hz = /bits/ 64 <2073600000>; 996 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 997 }; 998 999 opp-2131200000 { 1000 opp-hz = /bits/ 64 <2131200000>; 1001 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1002 }; 1003 1004 opp-2188800000 { 1005 opp-hz = /bits/ 64 <2188800000>; 1006 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1007 }; 1008 1009 opp-2246400000 { 1010 opp-hz = /bits/ 64 <2246400000>; 1011 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1012 }; 1013 1014 opp-2304000000 { 1015 opp-hz = /bits/ 64 <2304000000>; 1016 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1017 }; 1018 1019 opp-2323200000 { 1020 opp-hz = /bits/ 64 <2323200000>; 1021 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1022 }; 1023 1024 opp-2380800000 { 1025 opp-hz = /bits/ 64 <2380800000>; 1026 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1027 }; 1028 1029 opp-2400000000 { 1030 opp-hz = /bits/ 64 <2400000000>; 1031 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1032 }; 1033 1034 opp-2438400000 { 1035 opp-hz = /bits/ 64 <2438400000>; 1036 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1037 }; 1038 1039 opp-2515200000 { 1040 opp-hz = /bits/ 64 <2515200000>; 1041 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1042 }; 1043 1044 opp-2572800000 { 1045 opp-hz = /bits/ 64 <2572800000>; 1046 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1047 }; 1048 1049 opp-2630400000 { 1050 opp-hz = /bits/ 64 <2630400000>; 1051 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1052 }; 1053 1054 opp-2707200000 { 1055 opp-hz = /bits/ 64 <2707200000>; 1056 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1057 }; 1058 1059 opp-2764800000 { 1060 opp-hz = /bits/ 64 <2764800000>; 1061 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; 1062 }; 1063 1064 opp-2841600000 { 1065 opp-hz = /bits/ 64 <2841600000>; 1066 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1067 }; 1068 1069 opp-2899200000 { 1070 opp-hz = /bits/ 64 <2899200000>; 1071 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1072 }; 1073 1074 opp-2956800000 { 1075 opp-hz = /bits/ 64 <2956800000>; 1076 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1077 }; 1078 1079 opp-3014400000 { 1080 opp-hz = /bits/ 64 <3014400000>; 1081 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1082 }; 1083 1084 opp-3072000000 { 1085 opp-hz = /bits/ 64 <3072000000>; 1086 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1087 }; 1088 1089 opp-3148800000 { 1090 opp-hz = /bits/ 64 <3148800000>; 1091 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1092 }; 1093 }; 1094 1095 cpu5_opp_table: opp-table-cpu5 { 1096 compatible = "operating-points-v2"; 1097 opp-shared; 1098 1099 opp-460800000 { 1100 opp-hz = /bits/ 64 <460800000>; 1101 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1102 }; 1103 1104 opp-499200000 { 1105 opp-hz = /bits/ 64 <499200000>; 1106 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1107 }; 1108 1109 opp-576000000 { 1110 opp-hz = /bits/ 64 <576000000>; 1111 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1112 }; 1113 1114 opp-614400000 { 1115 opp-hz = /bits/ 64 <614400000>; 1116 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 1117 }; 1118 1119 opp-691200000 { 1120 opp-hz = /bits/ 64 <691200000>; 1121 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1122 }; 1123 1124 opp-729600000 { 1125 opp-hz = /bits/ 64 <729600000>; 1126 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1127 }; 1128 1129 opp-806400000 { 1130 opp-hz = /bits/ 64 <806400000>; 1131 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1132 }; 1133 1134 opp-844800000 { 1135 opp-hz = /bits/ 64 <844800000>; 1136 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1137 }; 1138 1139 opp-902400000 { 1140 opp-hz = /bits/ 64 <902400000>; 1141 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1142 }; 1143 1144 opp-960000000 { 1145 opp-hz = /bits/ 64 <960000000>; 1146 opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>; 1147 }; 1148 1149 opp-1036800000 { 1150 opp-hz = /bits/ 64 <1036800000>; 1151 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1152 }; 1153 1154 opp-1075200000 { 1155 opp-hz = /bits/ 64 <1075200000>; 1156 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1157 }; 1158 1159 opp-1152000000 { 1160 opp-hz = /bits/ 64 <1152000000>; 1161 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1162 }; 1163 1164 opp-1190400000 { 1165 opp-hz = /bits/ 64 <1190400000>; 1166 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; 1167 }; 1168 1169 opp-1267200000 { 1170 opp-hz = /bits/ 64 <1267200000>; 1171 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1172 }; 1173 1174 opp-1286400000 { 1175 opp-hz = /bits/ 64 <1286400000>; 1176 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1177 }; 1178 1179 opp-1382400000 { 1180 opp-hz = /bits/ 64 <1382400000>; 1181 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1182 }; 1183 1184 opp-1401600000 { 1185 opp-hz = /bits/ 64 <1401600000>; 1186 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; 1187 }; 1188 1189 opp-1497600000 { 1190 opp-hz = /bits/ 64 <1497600000>; 1191 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1192 }; 1193 1194 opp-1612800000 { 1195 opp-hz = /bits/ 64 <1612800000>; 1196 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1197 }; 1198 1199 opp-1708800000 { 1200 opp-hz = /bits/ 64 <1708800000>; 1201 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1202 }; 1203 1204 opp-1728000000 { 1205 opp-hz = /bits/ 64 <1728000000>; 1206 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1207 }; 1208 1209 opp-1824000000 { 1210 opp-hz = /bits/ 64 <1824000000>; 1211 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1212 }; 1213 1214 opp-1843200000 { 1215 opp-hz = /bits/ 64 <1843200000>; 1216 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1217 }; 1218 1219 opp-1920000000 { 1220 opp-hz = /bits/ 64 <1920000000>; 1221 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>; 1222 }; 1223 1224 opp-1958400000 { 1225 opp-hz = /bits/ 64 <1958400000>; 1226 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1227 }; 1228 1229 opp-2035200000 { 1230 opp-hz = /bits/ 64 <2035200000>; 1231 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1232 }; 1233 1234 opp-2073600000 { 1235 opp-hz = /bits/ 64 <2073600000>; 1236 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1237 }; 1238 1239 opp-2131200000 { 1240 opp-hz = /bits/ 64 <2131200000>; 1241 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1242 }; 1243 1244 opp-2188800000 { 1245 opp-hz = /bits/ 64 <2188800000>; 1246 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1247 }; 1248 1249 opp-2246400000 { 1250 opp-hz = /bits/ 64 <2246400000>; 1251 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1252 }; 1253 1254 opp-2304000000 { 1255 opp-hz = /bits/ 64 <2304000000>; 1256 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1257 }; 1258 1259 opp-2323200000 { 1260 opp-hz = /bits/ 64 <2323200000>; 1261 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1262 }; 1263 1264 opp-2380800000 { 1265 opp-hz = /bits/ 64 <2380800000>; 1266 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1267 }; 1268 1269 opp-2400000000 { 1270 opp-hz = /bits/ 64 <2400000000>; 1271 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1272 }; 1273 1274 opp-2438400000 { 1275 opp-hz = /bits/ 64 <2438400000>; 1276 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1277 }; 1278 1279 opp-2515200000 { 1280 opp-hz = /bits/ 64 <2515200000>; 1281 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1282 }; 1283 1284 opp-2572800000 { 1285 opp-hz = /bits/ 64 <2572800000>; 1286 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1287 }; 1288 1289 opp-2630400000 { 1290 opp-hz = /bits/ 64 <2630400000>; 1291 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1292 }; 1293 1294 opp-2707200000 { 1295 opp-hz = /bits/ 64 <2707200000>; 1296 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1297 }; 1298 1299 opp-2764800000 { 1300 opp-hz = /bits/ 64 <2764800000>; 1301 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; 1302 }; 1303 1304 opp-2841600000 { 1305 opp-hz = /bits/ 64 <2841600000>; 1306 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1307 }; 1308 1309 opp-2899200000 { 1310 opp-hz = /bits/ 64 <2899200000>; 1311 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1312 }; 1313 1314 opp-2956800000 { 1315 opp-hz = /bits/ 64 <2956800000>; 1316 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1317 }; 1318 1319 opp-3014400000 { 1320 opp-hz = /bits/ 64 <3014400000>; 1321 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1322 }; 1323 1324 opp-3072000000 { 1325 opp-hz = /bits/ 64 <3072000000>; 1326 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1327 }; 1328 1329 opp-3148800000 { 1330 opp-hz = /bits/ 64 <3148800000>; 1331 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1332 }; 1333 }; 1334 1335 cpu7_opp_table: opp-table-cpu7 { 1336 compatible = "operating-points-v2"; 1337 opp-shared; 1338 1339 opp-480000000 { 1340 opp-hz = /bits/ 64 <480000000>; 1341 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1342 }; 1343 1344 opp-499200000 { 1345 opp-hz = /bits/ 64 <499200000>; 1346 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1347 }; 1348 1349 opp-576000000 { 1350 opp-hz = /bits/ 64 <576000000>; 1351 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1352 }; 1353 1354 opp-614400000 { 1355 opp-hz = /bits/ 64 <614400000>; 1356 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 1357 }; 1358 1359 opp-672000000 { 1360 opp-hz = /bits/ 64 <672000000>; 1361 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1362 }; 1363 1364 opp-729600000 { 1365 opp-hz = /bits/ 64 <729600000>; 1366 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1367 }; 1368 1369 opp-787200000 { 1370 opp-hz = /bits/ 64 <787200000>; 1371 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1372 }; 1373 1374 opp-844800000 { 1375 opp-hz = /bits/ 64 <844800000>; 1376 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1377 }; 1378 1379 opp-902400000 { 1380 opp-hz = /bits/ 64 <902400000>; 1381 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1382 }; 1383 1384 opp-940800000 { 1385 opp-hz = /bits/ 64 <940800000>; 1386 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1387 }; 1388 1389 opp-1017600000 { 1390 opp-hz = /bits/ 64 <1017600000>; 1391 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1392 }; 1393 1394 opp-1075200000 { 1395 opp-hz = /bits/ 64 <1075200000>; 1396 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1397 }; 1398 1399 opp-1132800000 { 1400 opp-hz = /bits/ 64 <1132800000>; 1401 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1402 }; 1403 1404 opp-1190400000 { 1405 opp-hz = /bits/ 64 <1190400000>; 1406 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; 1407 }; 1408 1409 opp-1248000000 { 1410 opp-hz = /bits/ 64 <1248000000>; 1411 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1412 }; 1413 1414 opp-1305600000 { 1415 opp-hz = /bits/ 64 <1305600000>; 1416 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1417 }; 1418 1419 opp-1363200000 { 1420 opp-hz = /bits/ 64 <1363200000>; 1421 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1422 }; 1423 1424 opp-1420800000 { 1425 opp-hz = /bits/ 64 <1420800000>; 1426 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; 1427 }; 1428 1429 opp-1478400000 { 1430 opp-hz = /bits/ 64 <1478400000>; 1431 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1432 }; 1433 1434 opp-1555200000 { 1435 opp-hz = /bits/ 64 <1555200000>; 1436 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1437 }; 1438 1439 opp-1593600000 { 1440 opp-hz = /bits/ 64 <1593600000>; 1441 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1442 }; 1443 1444 opp-1670400000 { 1445 opp-hz = /bits/ 64 <1670400000>; 1446 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1447 }; 1448 1449 opp-1708800000 { 1450 opp-hz = /bits/ 64 <1708800000>; 1451 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1452 }; 1453 1454 opp-1804800000 { 1455 opp-hz = /bits/ 64 <1804800000>; 1456 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1457 }; 1458 1459 opp-1824000000 { 1460 opp-hz = /bits/ 64 <1824000000>; 1461 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1462 }; 1463 1464 opp-1939200000 { 1465 opp-hz = /bits/ 64 <1939200000>; 1466 opp-peak-kBps = <(806000 * 16) (3686000 * 4) (1440000 * 32)>; 1467 }; 1468 1469 opp-2035200000 { 1470 opp-hz = /bits/ 64 <2035200000>; 1471 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1472 }; 1473 1474 opp-2073600000 { 1475 opp-hz = /bits/ 64 <2073600000>; 1476 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1477 }; 1478 1479 opp-2112000000 { 1480 opp-hz = /bits/ 64 <2112000000>; 1481 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1482 }; 1483 1484 opp-2169600000 { 1485 opp-hz = /bits/ 64 <2169600000>; 1486 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1487 }; 1488 1489 opp-2208000000 { 1490 opp-hz = /bits/ 64 <2208000000>; 1491 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1492 }; 1493 1494 opp-2246400000 { 1495 opp-hz = /bits/ 64 <2246400000>; 1496 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1497 }; 1498 1499 opp-2304000000 { 1500 opp-hz = /bits/ 64 <2304000000>; 1501 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1502 }; 1503 1504 opp-2342400000 { 1505 opp-hz = /bits/ 64 <2342400000>; 1506 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1507 }; 1508 1509 opp-2380800000 { 1510 opp-hz = /bits/ 64 <2380800000>; 1511 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1512 }; 1513 1514 opp-2438400000 { 1515 opp-hz = /bits/ 64 <2438400000>; 1516 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1517 }; 1518 1519 opp-2457600000 { 1520 opp-hz = /bits/ 64 <2457600000>; 1521 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1522 }; 1523 1524 opp-2496000000 { 1525 opp-hz = /bits/ 64 <2496000000>; 1526 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1527 }; 1528 1529 opp-2553600000 { 1530 opp-hz = /bits/ 64 <2553600000>; 1531 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1532 }; 1533 1534 opp-2630400000 { 1535 opp-hz = /bits/ 64 <2630400000>; 1536 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1537 }; 1538 1539 opp-2688000000 { 1540 opp-hz = /bits/ 64 <2688000000>; 1541 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1542 }; 1543 1544 opp-2745600000 { 1545 opp-hz = /bits/ 64 <2745600000>; 1546 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; 1547 }; 1548 1549 opp-2803200000 { 1550 opp-hz = /bits/ 64 <2803200000>; 1551 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1552 }; 1553 1554 opp-2880000000 { 1555 opp-hz = /bits/ 64 <2880000000>; 1556 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1557 }; 1558 1559 opp-2937600000 { 1560 opp-hz = /bits/ 64 <2937600000>; 1561 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1562 }; 1563 1564 opp-2995200000 { 1565 opp-hz = /bits/ 64 <2995200000>; 1566 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1567 }; 1568 1569 opp-3052800000 { 1570 opp-hz = /bits/ 64 <3052800000>; 1571 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1572 }; 1573 1574 opp-3187200000 { 1575 opp-hz = /bits/ 64 <3187200000>; 1576 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1577 }; 1578 1579 opp-3302400000 { 1580 opp-hz = /bits/ 64 <3302400000>; 1581 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1582 }; 1583 }; 1584 1585 pmu-a520 { 1586 compatible = "arm,cortex-a520-pmu"; 1587 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 1588 }; 1589 1590 pmu-a720 { 1591 compatible = "arm,cortex-a720-pmu"; 1592 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 1593 }; 1594 1595 pmu-x4 { 1596 compatible = "arm,cortex-x4-pmu"; 1597 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster2>; 1598 }; 1599 1600 psci { 1601 compatible = "arm,psci-1.0"; 1602 method = "smc"; 1603 1604 cpu_pd0: power-domain-cpu0 { 1605 #power-domain-cells = <0>; 1606 power-domains = <&cluster_pd>; 1607 domain-idle-states = <&silver_cpu_sleep_0>; 1608 }; 1609 1610 cpu_pd1: power-domain-cpu1 { 1611 #power-domain-cells = <0>; 1612 power-domains = <&cluster_pd>; 1613 domain-idle-states = <&silver_cpu_sleep_0>; 1614 }; 1615 1616 cpu_pd2: power-domain-cpu2 { 1617 #power-domain-cells = <0>; 1618 power-domains = <&cluster_pd>; 1619 domain-idle-states = <&gold_cpu_sleep_0>; 1620 }; 1621 1622 cpu_pd3: power-domain-cpu3 { 1623 #power-domain-cells = <0>; 1624 power-domains = <&cluster_pd>; 1625 domain-idle-states = <&gold_cpu_sleep_0>; 1626 }; 1627 1628 cpu_pd4: power-domain-cpu4 { 1629 #power-domain-cells = <0>; 1630 power-domains = <&cluster_pd>; 1631 domain-idle-states = <&gold_cpu_sleep_0>; 1632 }; 1633 1634 cpu_pd5: power-domain-cpu5 { 1635 #power-domain-cells = <0>; 1636 power-domains = <&cluster_pd>; 1637 domain-idle-states = <&gold_cpu_sleep_0>; 1638 }; 1639 1640 cpu_pd6: power-domain-cpu6 { 1641 #power-domain-cells = <0>; 1642 power-domains = <&cluster_pd>; 1643 domain-idle-states = <&gold_cpu_sleep_0>; 1644 }; 1645 1646 cpu_pd7: power-domain-cpu7 { 1647 #power-domain-cells = <0>; 1648 power-domains = <&cluster_pd>; 1649 domain-idle-states = <&gold_plus_cpu_sleep_0>; 1650 }; 1651 1652 cluster_pd: power-domain-cluster { 1653 #power-domain-cells = <0>; 1654 domain-idle-states = <&cluster_sleep_0>, 1655 <&cluster_sleep_1>; 1656 }; 1657 }; 1658 1659 reserved_memory: reserved-memory { 1660 #address-cells = <2>; 1661 #size-cells = <2>; 1662 ranges; 1663 1664 hyp_mem: hyp@80000000 { 1665 reg = <0 0x80000000 0 0xe00000>; 1666 no-map; 1667 }; 1668 1669 cpusys_vm_mem: cpusys-vm@80e00000 { 1670 reg = <0 0x80e00000 0 0x400000>; 1671 no-map; 1672 }; 1673 1674 /* Merged xbl_dtlog, xbl_ramdump and aop_image regions */ 1675 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 { 1676 reg = <0 0x81a00000 0 0x260000>; 1677 no-map; 1678 }; 1679 1680 aop_cmd_db_mem: aop-cmd-db@81c60000 { 1681 compatible = "qcom,cmd-db"; 1682 reg = <0 0x81c60000 0 0x20000>; 1683 no-map; 1684 }; 1685 1686 /* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */ 1687 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 1688 reg = <0 0x81c80000 0 0x75000>; 1689 no-map; 1690 }; 1691 1692 /* Secdata region can be reused by apps */ 1693 1694 smem: smem@81d00000 { 1695 compatible = "qcom,smem"; 1696 reg = <0 0x81d00000 0 0x200000>; 1697 hwlocks = <&tcsr_mutex 3>; 1698 no-map; 1699 }; 1700 1701 adsp_mhi_mem: adsp-mhi@81f00000 { 1702 reg = <0 0x81f00000 0 0x20000>; 1703 no-map; 1704 }; 1705 1706 pvmfw_mem: pvmfw@824a0000 { 1707 reg = <0 0x824a0000 0 0x100000>; 1708 no-map; 1709 }; 1710 1711 global_sync_mem: global-sync@82600000 { 1712 reg = <0 0x82600000 0 0x100000>; 1713 no-map; 1714 }; 1715 1716 tz_stat_mem: tz-stat@82700000 { 1717 reg = <0 0x82700000 0 0x100000>; 1718 no-map; 1719 }; 1720 1721 qdss_mem: qdss@82800000 { 1722 reg = <0 0x82800000 0 0x2000000>; 1723 no-map; 1724 }; 1725 1726 qlink_logging_mem: qlink-logging@84800000 { 1727 reg = <0 0x84800000 0 0x200000>; 1728 no-map; 1729 }; 1730 1731 mpss_dsm_mem: mpss-dsm@86b00000 { 1732 reg = <0 0x86b00000 0 0x4900000>; 1733 no-map; 1734 }; 1735 1736 mpss_dsm_mem_2: mpss-dsm-2@8b400000 { 1737 reg = <0 0x8b400000 0 0x800000>; 1738 no-map; 1739 }; 1740 1741 mpss_mem: mpss@8bc00000 { 1742 reg = <0 0x8bc00000 0 0xf400000>; 1743 no-map; 1744 }; 1745 1746 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { 1747 reg = <0 0x9b000000 0 0x80000>; 1748 no-map; 1749 }; 1750 1751 ipa_fw_mem: ipa-fw@9b080000 { 1752 reg = <0 0x9b080000 0 0x10000>; 1753 no-map; 1754 }; 1755 1756 ipa_gsi_mem: ipa-gsi@9b090000 { 1757 reg = <0 0x9b090000 0 0xa000>; 1758 no-map; 1759 }; 1760 1761 gpu_micro_code_mem: gpu-micro-code@9b09a000 { 1762 reg = <0 0x9b09a000 0 0x2000>; 1763 no-map; 1764 }; 1765 1766 spss_region_mem: spss@9b0a0000 { 1767 reg = <0 0x9b0a0000 0 0x1e0000>; 1768 no-map; 1769 }; 1770 1771 /* First part of the "SPU secure shared memory" region */ 1772 spu_tz_shared_mem: spu-tz-shared@9b280000 { 1773 reg = <0 0x9b280000 0 0x60000>; 1774 no-map; 1775 }; 1776 1777 /* Second part of the "SPU secure shared memory" region */ 1778 spu_modem_shared_mem: spu-modem-shared@9b2e0000 { 1779 reg = <0 0x9b2e0000 0 0x20000>; 1780 no-map; 1781 }; 1782 1783 camera_mem: camera@9b300000 { 1784 reg = <0 0x9b300000 0 0x800000>; 1785 no-map; 1786 }; 1787 1788 video_mem: video@9bb00000 { 1789 reg = <0 0x9bb00000 0 0x800000>; 1790 no-map; 1791 }; 1792 1793 cvp_mem: cvp@9c300000 { 1794 reg = <0 0x9c300000 0 0x700000>; 1795 no-map; 1796 }; 1797 1798 cdsp_mem: cdsp@9ca00000 { 1799 reg = <0 0x9ca00000 0 0x1400000>; 1800 no-map; 1801 }; 1802 1803 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 { 1804 reg = <0 0x9de00000 0 0x80000>; 1805 no-map; 1806 }; 1807 1808 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 { 1809 reg = <0 0x9de80000 0 0x80000>; 1810 no-map; 1811 }; 1812 1813 adspslpi_mem: adspslpi@9df00000 { 1814 reg = <0 0x9df00000 0 0x4080000>; 1815 no-map; 1816 }; 1817 1818 rmtfs_mem: rmtfs@d7c00000 { 1819 compatible = "qcom,rmtfs-mem"; 1820 reg = <0 0xd7c00000 0 0x400000>; 1821 no-map; 1822 1823 qcom,client-id = <1>; 1824 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 1825 }; 1826 1827 /* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */ 1828 tz_merged_mem: tz-merged@d8000000 { 1829 reg = <0 0xd8000000 0 0x800000>; 1830 no-map; 1831 }; 1832 1833 hwfence_shbuf: hwfence-shbuf@e6440000 { 1834 reg = <0 0xe6440000 0 0x2dd000>; 1835 no-map; 1836 }; 1837 1838 trust_ui_vm_mem: trust-ui-vm@f3800000 { 1839 reg = <0 0xf3800000 0 0x4400000>; 1840 no-map; 1841 }; 1842 1843 oem_vm_mem: oem-vm@f7c00000 { 1844 reg = <0 0xf7c00000 0 0x4c00000>; 1845 no-map; 1846 }; 1847 1848 llcc_lpi_mem: llcc-lpi@ff800000 { 1849 reg = <0 0xff800000 0 0x600000>; 1850 no-map; 1851 }; 1852 }; 1853 1854 smp2p-adsp { 1855 compatible = "qcom,smp2p"; 1856 1857 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1858 IPCC_MPROC_SIGNAL_SMP2P 1859 IRQ_TYPE_EDGE_RISING>; 1860 1861 mboxes = <&ipcc IPCC_CLIENT_LPASS 1862 IPCC_MPROC_SIGNAL_SMP2P>; 1863 1864 qcom,smem = <443>, <429>; 1865 qcom,local-pid = <0>; 1866 qcom,remote-pid = <2>; 1867 1868 smp2p_adsp_out: master-kernel { 1869 qcom,entry-name = "master-kernel"; 1870 #qcom,smem-state-cells = <1>; 1871 }; 1872 1873 smp2p_adsp_in: slave-kernel { 1874 qcom,entry-name = "slave-kernel"; 1875 interrupt-controller; 1876 #interrupt-cells = <2>; 1877 }; 1878 }; 1879 1880 smp2p-cdsp { 1881 compatible = "qcom,smp2p"; 1882 1883 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1884 IPCC_MPROC_SIGNAL_SMP2P 1885 IRQ_TYPE_EDGE_RISING>; 1886 1887 mboxes = <&ipcc IPCC_CLIENT_CDSP 1888 IPCC_MPROC_SIGNAL_SMP2P>; 1889 1890 qcom,smem = <94>, <432>; 1891 qcom,local-pid = <0>; 1892 qcom,remote-pid = <5>; 1893 1894 smp2p_cdsp_out: master-kernel { 1895 qcom,entry-name = "master-kernel"; 1896 #qcom,smem-state-cells = <1>; 1897 }; 1898 1899 smp2p_cdsp_in: slave-kernel { 1900 qcom,entry-name = "slave-kernel"; 1901 interrupt-controller; 1902 #interrupt-cells = <2>; 1903 }; 1904 }; 1905 1906 smp2p-modem { 1907 compatible = "qcom,smp2p"; 1908 1909 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1910 IPCC_MPROC_SIGNAL_SMP2P 1911 IRQ_TYPE_EDGE_RISING>; 1912 1913 mboxes = <&ipcc IPCC_CLIENT_MPSS 1914 IPCC_MPROC_SIGNAL_SMP2P>; 1915 1916 qcom,smem = <435>, <428>; 1917 qcom,local-pid = <0>; 1918 qcom,remote-pid = <1>; 1919 1920 smp2p_modem_out: master-kernel { 1921 qcom,entry-name = "master-kernel"; 1922 #qcom,smem-state-cells = <1>; 1923 }; 1924 1925 smp2p_modem_in: slave-kernel { 1926 qcom,entry-name = "slave-kernel"; 1927 interrupt-controller; 1928 #interrupt-cells = <2>; 1929 }; 1930 1931 ipa_smp2p_out: ipa-ap-to-modem { 1932 qcom,entry-name = "ipa"; 1933 #qcom,smem-state-cells = <1>; 1934 }; 1935 1936 ipa_smp2p_in: ipa-modem-to-ap { 1937 qcom,entry-name = "ipa"; 1938 interrupt-controller; 1939 #interrupt-cells = <2>; 1940 }; 1941 }; 1942 1943 soc: soc@0 { 1944 compatible = "simple-bus"; 1945 1946 #address-cells = <2>; 1947 #size-cells = <2>; 1948 dma-ranges = <0 0 0 0 0x10 0>; 1949 ranges = <0 0 0 0 0x10 0>; 1950 1951 gcc: clock-controller@100000 { 1952 compatible = "qcom,sm8650-gcc"; 1953 reg = <0 0x00100000 0 0x1f4200>; 1954 1955 clocks = <&bi_tcxo_div2>, 1956 <&bi_tcxo_ao_div2>, 1957 <&sleep_clk>, 1958 <&pcie0_phy>, 1959 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 1960 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 1961 <&ufs_mem_phy 0>, 1962 <&ufs_mem_phy 1>, 1963 <&ufs_mem_phy 2>, 1964 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 1965 1966 #clock-cells = <1>; 1967 #reset-cells = <1>; 1968 #power-domain-cells = <1>; 1969 }; 1970 1971 ipcc: mailbox@406000 { 1972 compatible = "qcom,sm8650-ipcc", "qcom,ipcc"; 1973 reg = <0 0x00406000 0 0x1000>; 1974 1975 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>; 1976 interrupt-controller; 1977 #interrupt-cells = <3>; 1978 1979 #mbox-cells = <2>; 1980 }; 1981 1982 gpi_dma2: dma-controller@800000 { 1983 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 1984 reg = <0 0x00800000 0 0x60000>; 1985 1986 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>, 1987 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>, 1988 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, 1989 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, 1990 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, 1991 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, 1992 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, 1993 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, 1994 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, 1995 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>, 1996 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>, 1997 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>; 1998 1999 dma-channels = <12>; 2000 dma-channel-mask = <0x3f>; 2001 #dma-cells = <3>; 2002 2003 iommus = <&apps_smmu 0x436 0>; 2004 2005 dma-coherent; 2006 2007 status = "disabled"; 2008 }; 2009 2010 qupv3_id_1: geniqup@8c0000 { 2011 compatible = "qcom,geni-se-qup"; 2012 reg = <0 0x008c0000 0 0x2000>; 2013 2014 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 2015 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 2016 clock-names = "m-ahb", 2017 "s-ahb"; 2018 2019 iommus = <&apps_smmu 0x423 0>; 2020 2021 dma-coherent; 2022 2023 #address-cells = <2>; 2024 #size-cells = <2>; 2025 ranges; 2026 2027 status = "disabled"; 2028 2029 i2c8: i2c@880000 { 2030 compatible = "qcom,geni-i2c"; 2031 reg = <0 0x00880000 0 0x4000>; 2032 2033 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 2034 2035 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 2036 clock-names = "se"; 2037 2038 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2039 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2040 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2041 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2042 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2043 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2044 interconnect-names = "qup-core", 2045 "qup-config", 2046 "qup-memory"; 2047 2048 power-domains = <&rpmhpd RPMHPD_CX>; 2049 2050 operating-points-v2 = <&qup_opp_table_120mhz>; 2051 2052 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 2053 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 2054 dma-names = "tx", 2055 "rx"; 2056 2057 pinctrl-0 = <&qup_i2c8_data_clk>; 2058 pinctrl-names = "default"; 2059 2060 #address-cells = <1>; 2061 #size-cells = <0>; 2062 2063 status = "disabled"; 2064 }; 2065 2066 spi8: spi@880000 { 2067 compatible = "qcom,geni-spi"; 2068 reg = <0 0x00880000 0 0x4000>; 2069 2070 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 2071 2072 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 2073 clock-names = "se"; 2074 2075 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2076 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2077 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2078 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2079 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2080 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2081 interconnect-names = "qup-core", 2082 "qup-config", 2083 "qup-memory"; 2084 2085 power-domains = <&rpmhpd RPMHPD_CX>; 2086 2087 operating-points-v2 = <&qup_opp_table_100mhz>; 2088 2089 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 2090 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 2091 dma-names = "tx", 2092 "rx"; 2093 2094 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 2095 pinctrl-names = "default"; 2096 2097 #address-cells = <1>; 2098 #size-cells = <0>; 2099 2100 status = "disabled"; 2101 }; 2102 2103 i2c9: i2c@884000 { 2104 compatible = "qcom,geni-i2c"; 2105 reg = <0 0x00884000 0 0x4000>; 2106 2107 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; 2108 2109 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 2110 clock-names = "se"; 2111 2112 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2113 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2114 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2115 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2116 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2117 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2118 interconnect-names = "qup-core", 2119 "qup-config", 2120 "qup-memory"; 2121 2122 power-domains = <&rpmhpd RPMHPD_CX>; 2123 2124 operating-points-v2 = <&qup_opp_table_120mhz>; 2125 2126 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 2127 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 2128 dma-names = "tx", 2129 "rx"; 2130 2131 pinctrl-0 = <&qup_i2c9_data_clk>; 2132 pinctrl-names = "default"; 2133 2134 #address-cells = <1>; 2135 #size-cells = <0>; 2136 2137 status = "disabled"; 2138 }; 2139 2140 spi9: spi@884000 { 2141 compatible = "qcom,geni-spi"; 2142 reg = <0 0x00884000 0 0x4000>; 2143 2144 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; 2145 2146 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 2147 clock-names = "se"; 2148 2149 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2150 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2151 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2152 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2153 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2154 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2155 interconnect-names = "qup-core", 2156 "qup-config", 2157 "qup-memory"; 2158 2159 power-domains = <&rpmhpd RPMHPD_CX>; 2160 2161 operating-points-v2 = <&qup_opp_table_120mhz>; 2162 2163 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 2164 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 2165 dma-names = "tx", 2166 "rx"; 2167 2168 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 2169 pinctrl-names = "default"; 2170 2171 #address-cells = <1>; 2172 #size-cells = <0>; 2173 2174 status = "disabled"; 2175 }; 2176 2177 i2c10: i2c@888000 { 2178 compatible = "qcom,geni-i2c"; 2179 reg = <0 0x00888000 0 0x4000>; 2180 2181 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; 2182 2183 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 2184 clock-names = "se"; 2185 2186 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2187 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2188 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2189 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2190 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2191 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2192 interconnect-names = "qup-core", 2193 "qup-config", 2194 "qup-memory"; 2195 2196 power-domains = <&rpmhpd RPMHPD_CX>; 2197 2198 operating-points-v2 = <&qup_opp_table_120mhz>; 2199 2200 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 2201 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 2202 dma-names = "tx", 2203 "rx"; 2204 2205 pinctrl-0 = <&qup_i2c10_data_clk>; 2206 pinctrl-names = "default"; 2207 2208 #address-cells = <1>; 2209 #size-cells = <0>; 2210 2211 status = "disabled"; 2212 }; 2213 2214 spi10: spi@888000 { 2215 compatible = "qcom,geni-spi"; 2216 reg = <0 0x00888000 0 0x4000>; 2217 2218 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; 2219 2220 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 2221 clock-names = "se"; 2222 2223 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2224 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2225 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2226 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2227 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2228 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2229 interconnect-names = "qup-core", 2230 "qup-config", 2231 "qup-memory"; 2232 2233 power-domains = <&rpmhpd RPMHPD_CX>; 2234 2235 operating-points-v2 = <&qup_opp_table_120mhz>; 2236 2237 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 2238 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 2239 dma-names = "tx", 2240 "rx"; 2241 2242 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 2243 pinctrl-names = "default"; 2244 2245 #address-cells = <1>; 2246 #size-cells = <0>; 2247 2248 status = "disabled"; 2249 }; 2250 2251 i2c11: i2c@88c000 { 2252 compatible = "qcom,geni-i2c"; 2253 reg = <0 0x0088c000 0 0x4000>; 2254 2255 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2256 2257 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 2258 clock-names = "se"; 2259 2260 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2261 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2262 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2263 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2264 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2265 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2266 interconnect-names = "qup-core", 2267 "qup-config", 2268 "qup-memory"; 2269 2270 power-domains = <&rpmhpd RPMHPD_CX>; 2271 2272 operating-points-v2 = <&qup_opp_table_120mhz>; 2273 2274 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 2275 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 2276 dma-names = "tx", 2277 "rx"; 2278 2279 pinctrl-0 = <&qup_i2c11_data_clk>; 2280 pinctrl-names = "default"; 2281 2282 #address-cells = <1>; 2283 #size-cells = <0>; 2284 2285 status = "disabled"; 2286 }; 2287 2288 spi11: spi@88c000 { 2289 compatible = "qcom,geni-spi"; 2290 reg = <0 0x0088c000 0 0x4000>; 2291 2292 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2293 2294 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 2295 clock-names = "se"; 2296 2297 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2298 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2299 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2300 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2301 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2302 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2303 interconnect-names = "qup-core", 2304 "qup-config", 2305 "qup-memory"; 2306 2307 power-domains = <&rpmhpd RPMHPD_CX>; 2308 2309 operating-points-v2 = <&qup_opp_table_120mhz>; 2310 2311 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 2312 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 2313 dma-names = "tx", 2314 "rx"; 2315 2316 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 2317 pinctrl-names = "default"; 2318 2319 #address-cells = <1>; 2320 #size-cells = <0>; 2321 2322 status = "disabled"; 2323 }; 2324 2325 i2c12: i2c@890000 { 2326 compatible = "qcom,geni-i2c"; 2327 reg = <0 0x00890000 0 0x4000>; 2328 2329 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2330 2331 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 2332 clock-names = "se"; 2333 2334 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2335 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2336 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2337 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2338 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2339 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2340 interconnect-names = "qup-core", 2341 "qup-config", 2342 "qup-memory"; 2343 2344 power-domains = <&rpmhpd RPMHPD_CX>; 2345 2346 operating-points-v2 = <&qup_opp_table_100mhz>; 2347 2348 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 2349 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 2350 dma-names = "tx", 2351 "rx"; 2352 2353 pinctrl-0 = <&qup_i2c12_data_clk>; 2354 pinctrl-names = "default"; 2355 2356 #address-cells = <1>; 2357 #size-cells = <0>; 2358 2359 status = "disabled"; 2360 }; 2361 2362 spi12: spi@890000 { 2363 compatible = "qcom,geni-spi"; 2364 reg = <0 0x00890000 0 0x4000>; 2365 2366 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2367 2368 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 2369 clock-names = "se"; 2370 2371 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2372 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2373 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2374 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2375 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2376 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2377 interconnect-names = "qup-core", 2378 "qup-config", 2379 "qup-memory"; 2380 2381 power-domains = <&rpmhpd RPMHPD_CX>; 2382 2383 operating-points-v2 = <&qup_opp_table_100mhz>; 2384 2385 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 2386 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 2387 dma-names = "tx", 2388 "rx"; 2389 2390 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 2391 pinctrl-names = "default"; 2392 2393 #address-cells = <1>; 2394 #size-cells = <0>; 2395 2396 status = "disabled"; 2397 }; 2398 2399 i2c13: i2c@894000 { 2400 compatible = "qcom,geni-i2c"; 2401 reg = <0 0x00894000 0 0x4000>; 2402 2403 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; 2404 2405 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 2406 clock-names = "se"; 2407 2408 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2409 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2410 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2411 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2412 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2413 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2414 interconnect-names = "qup-core", 2415 "qup-config", 2416 "qup-memory"; 2417 2418 power-domains = <&rpmhpd RPMHPD_CX>; 2419 2420 operating-points-v2 = <&qup_opp_table_100mhz>; 2421 2422 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 2423 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 2424 dma-names = "tx", 2425 "rx"; 2426 2427 pinctrl-0 = <&qup_i2c13_data_clk>; 2428 pinctrl-names = "default"; 2429 2430 #address-cells = <1>; 2431 #size-cells = <0>; 2432 2433 status = "disabled"; 2434 }; 2435 2436 spi13: spi@894000 { 2437 compatible = "qcom,geni-spi"; 2438 reg = <0 0x00894000 0 0x4000>; 2439 2440 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; 2441 2442 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 2443 clock-names = "se"; 2444 2445 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2446 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2447 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2448 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2449 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2450 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2451 interconnect-names = "qup-core", 2452 "qup-config", 2453 "qup-memory"; 2454 2455 power-domains = <&rpmhpd RPMHPD_CX>; 2456 2457 operating-points-v2 = <&qup_opp_table_100mhz>; 2458 2459 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 2460 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 2461 dma-names = "tx", 2462 "rx"; 2463 2464 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 2465 pinctrl-names = "default"; 2466 2467 #address-cells = <1>; 2468 #size-cells = <0>; 2469 2470 status = "disabled"; 2471 }; 2472 2473 uart14: serial@898000 { 2474 compatible = "qcom,geni-uart"; 2475 reg = <0 0x00898000 0 0x4000>; 2476 2477 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH 0>; 2478 2479 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 2480 clock-names = "se"; 2481 2482 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2483 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2484 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2485 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 2486 interconnect-names = "qup-core", 2487 "qup-config"; 2488 2489 power-domains = <&rpmhpd RPMHPD_CX>; 2490 2491 operating-points-v2 = <&qup_opp_table_128mhz>; 2492 2493 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 2494 pinctrl-names = "default"; 2495 2496 status = "disabled"; 2497 }; 2498 2499 uart15: serial@89c000 { 2500 compatible = "qcom,geni-debug-uart"; 2501 reg = <0 0x0089c000 0 0x4000>; 2502 2503 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 2504 2505 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 2506 clock-names = "se"; 2507 2508 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2509 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2510 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2511 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 2512 interconnect-names = "qup-core", 2513 "qup-config"; 2514 2515 power-domains = <&rpmhpd RPMHPD_CX>; 2516 2517 operating-points-v2 = <&qup_opp_table_100mhz>; 2518 2519 pinctrl-0 = <&qup_uart15_default>; 2520 pinctrl-names = "default"; 2521 2522 status = "disabled"; 2523 }; 2524 }; 2525 2526 i2c_master_hub_0: geniqup@9c0000 { 2527 compatible = "qcom,geni-se-i2c-master-hub"; 2528 reg = <0 0x009c0000 0 0x2000>; 2529 2530 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 2531 clock-names = "s-ahb"; 2532 2533 #address-cells = <2>; 2534 #size-cells = <2>; 2535 ranges; 2536 2537 status = "disabled"; 2538 2539 i2c_hub_0: i2c@980000 { 2540 compatible = "qcom,geni-i2c-master-hub"; 2541 reg = <0 0x00980000 0 0x4000>; 2542 2543 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>; 2544 2545 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 2546 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2547 clock-names = "se", 2548 "core"; 2549 2550 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2551 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2552 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2553 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2554 interconnect-names = "qup-core", 2555 "qup-config"; 2556 2557 power-domains = <&rpmhpd RPMHPD_CX>; 2558 2559 required-opps = <&rpmhpd_opp_low_svs>; 2560 2561 pinctrl-0 = <&hub_i2c0_data_clk>; 2562 pinctrl-names = "default"; 2563 2564 #address-cells = <1>; 2565 #size-cells = <0>; 2566 2567 status = "disabled"; 2568 }; 2569 2570 i2c_hub_1: i2c@984000 { 2571 compatible = "qcom,geni-i2c-master-hub"; 2572 reg = <0 0x00984000 0 0x4000>; 2573 2574 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH 0>; 2575 2576 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 2577 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2578 clock-names = "se", 2579 "core"; 2580 2581 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2582 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2583 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2584 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2585 interconnect-names = "qup-core", 2586 "qup-config"; 2587 2588 power-domains = <&rpmhpd RPMHPD_CX>; 2589 2590 required-opps = <&rpmhpd_opp_low_svs>; 2591 2592 pinctrl-0 = <&hub_i2c1_data_clk>; 2593 pinctrl-names = "default"; 2594 2595 #address-cells = <1>; 2596 #size-cells = <0>; 2597 2598 status = "disabled"; 2599 }; 2600 2601 i2c_hub_2: i2c@988000 { 2602 compatible = "qcom,geni-i2c-master-hub"; 2603 reg = <0 0x00988000 0 0x4000>; 2604 2605 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH 0>; 2606 2607 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 2608 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2609 clock-names = "se", 2610 "core"; 2611 2612 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2613 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2614 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2615 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2616 interconnect-names = "qup-core", 2617 "qup-config"; 2618 2619 power-domains = <&rpmhpd RPMHPD_CX>; 2620 2621 required-opps = <&rpmhpd_opp_low_svs>; 2622 2623 pinctrl-0 = <&hub_i2c2_data_clk>; 2624 pinctrl-names = "default"; 2625 2626 #address-cells = <1>; 2627 #size-cells = <0>; 2628 2629 status = "disabled"; 2630 }; 2631 2632 i2c_hub_3: i2c@98c000 { 2633 compatible = "qcom,geni-i2c-master-hub"; 2634 reg = <0 0x0098c000 0 0x4000>; 2635 2636 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>; 2637 2638 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 2639 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2640 clock-names = "se", 2641 "core"; 2642 2643 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2644 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2645 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2646 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2647 interconnect-names = "qup-core", 2648 "qup-config"; 2649 2650 power-domains = <&rpmhpd RPMHPD_CX>; 2651 2652 required-opps = <&rpmhpd_opp_low_svs>; 2653 2654 pinctrl-0 = <&hub_i2c3_data_clk>; 2655 pinctrl-names = "default"; 2656 2657 #address-cells = <1>; 2658 #size-cells = <0>; 2659 2660 status = "disabled"; 2661 }; 2662 2663 i2c_hub_4: i2c@990000 { 2664 compatible = "qcom,geni-i2c-master-hub"; 2665 reg = <0 0x00990000 0 0x4000>; 2666 2667 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>; 2668 2669 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 2670 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2671 clock-names = "se", 2672 "core"; 2673 2674 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2675 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2676 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2677 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2678 interconnect-names = "qup-core", 2679 "qup-config"; 2680 2681 power-domains = <&rpmhpd RPMHPD_CX>; 2682 2683 required-opps = <&rpmhpd_opp_low_svs>; 2684 2685 pinctrl-0 = <&hub_i2c4_data_clk>; 2686 pinctrl-names = "default"; 2687 2688 #address-cells = <1>; 2689 #size-cells = <0>; 2690 2691 status = "disabled"; 2692 }; 2693 2694 i2c_hub_5: i2c@994000 { 2695 compatible = "qcom,geni-i2c-master-hub"; 2696 reg = <0 0x00994000 0 0x4000>; 2697 2698 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH 0>; 2699 2700 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 2701 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2702 clock-names = "se", 2703 "core"; 2704 2705 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2706 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2707 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2708 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2709 interconnect-names = "qup-core", 2710 "qup-config"; 2711 2712 power-domains = <&rpmhpd RPMHPD_CX>; 2713 2714 required-opps = <&rpmhpd_opp_low_svs>; 2715 2716 pinctrl-0 = <&hub_i2c5_data_clk>; 2717 pinctrl-names = "default"; 2718 2719 #address-cells = <1>; 2720 #size-cells = <0>; 2721 2722 status = "disabled"; 2723 }; 2724 2725 i2c_hub_6: i2c@998000 { 2726 compatible = "qcom,geni-i2c-master-hub"; 2727 reg = <0 0x00998000 0 0x4000>; 2728 2729 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH 0>; 2730 2731 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 2732 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2733 clock-names = "se", 2734 "core"; 2735 2736 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2737 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2738 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2739 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2740 interconnect-names = "qup-core", 2741 "qup-config"; 2742 2743 power-domains = <&rpmhpd RPMHPD_CX>; 2744 2745 required-opps = <&rpmhpd_opp_low_svs>; 2746 2747 pinctrl-0 = <&hub_i2c6_data_clk>; 2748 pinctrl-names = "default"; 2749 2750 #address-cells = <1>; 2751 #size-cells = <0>; 2752 2753 status = "disabled"; 2754 }; 2755 2756 i2c_hub_7: i2c@99c000 { 2757 compatible = "qcom,geni-i2c-master-hub"; 2758 reg = <0 0x0099c000 0 0x4000>; 2759 2760 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; 2761 2762 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 2763 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2764 clock-names = "se", 2765 "core"; 2766 2767 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2768 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2769 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2770 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2771 interconnect-names = "qup-core", 2772 "qup-config"; 2773 2774 power-domains = <&rpmhpd RPMHPD_CX>; 2775 2776 required-opps = <&rpmhpd_opp_low_svs>; 2777 2778 pinctrl-0 = <&hub_i2c7_data_clk>; 2779 pinctrl-names = "default"; 2780 2781 #address-cells = <1>; 2782 #size-cells = <0>; 2783 2784 status = "disabled"; 2785 }; 2786 2787 i2c_hub_8: i2c@9a0000 { 2788 compatible = "qcom,geni-i2c-master-hub"; 2789 reg = <0 0x009a0000 0 0x4000>; 2790 2791 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH 0>; 2792 2793 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 2794 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2795 clock-names = "se", 2796 "core"; 2797 2798 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2799 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2800 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2801 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2802 interconnect-names = "qup-core", 2803 "qup-config"; 2804 2805 power-domains = <&rpmhpd RPMHPD_CX>; 2806 2807 required-opps = <&rpmhpd_opp_low_svs>; 2808 2809 pinctrl-0 = <&hub_i2c8_data_clk>; 2810 pinctrl-names = "default"; 2811 2812 #address-cells = <1>; 2813 #size-cells = <0>; 2814 2815 status = "disabled"; 2816 }; 2817 2818 i2c_hub_9: i2c@9a4000 { 2819 compatible = "qcom,geni-i2c-master-hub"; 2820 reg = <0 0x009a4000 0 0x4000>; 2821 2822 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH 0>; 2823 2824 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 2825 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2826 clock-names = "se", 2827 "core"; 2828 2829 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2830 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2831 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2832 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2833 interconnect-names = "qup-core", 2834 "qup-config"; 2835 2836 power-domains = <&rpmhpd RPMHPD_CX>; 2837 2838 required-opps = <&rpmhpd_opp_low_svs>; 2839 2840 pinctrl-0 = <&hub_i2c9_data_clk>; 2841 pinctrl-names = "default"; 2842 2843 #address-cells = <1>; 2844 #size-cells = <0>; 2845 2846 status = "disabled"; 2847 }; 2848 }; 2849 2850 gpi_dma1: dma-controller@a00000 { 2851 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 2852 reg = <0 0x00a00000 0 0x60000>; 2853 2854 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>, 2855 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>, 2856 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>, 2857 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>, 2858 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>, 2859 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>, 2860 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>, 2861 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>, 2862 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>, 2863 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>, 2864 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>, 2865 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 2866 2867 dma-channels = <12>; 2868 dma-channel-mask = <0xc>; 2869 #dma-cells = <3>; 2870 2871 iommus = <&apps_smmu 0xb6 0>; 2872 dma-coherent; 2873 2874 status = "disabled"; 2875 }; 2876 2877 qupv3_id_0: geniqup@ac0000 { 2878 compatible = "qcom,geni-se-qup"; 2879 reg = <0 0x00ac0000 0 0x2000>; 2880 2881 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 2882 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 2883 clock-names = "m-ahb", 2884 "s-ahb"; 2885 2886 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2887 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 2888 interconnect-names = "qup-core"; 2889 2890 iommus = <&apps_smmu 0xa3 0>; 2891 2892 dma-coherent; 2893 2894 #address-cells = <2>; 2895 #size-cells = <2>; 2896 ranges; 2897 2898 status = "disabled"; 2899 2900 i2c0: i2c@a80000 { 2901 compatible = "qcom,geni-i2c"; 2902 reg = <0 0x00a80000 0 0x4000>; 2903 2904 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 2905 2906 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2907 clock-names = "se"; 2908 2909 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2910 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2911 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2912 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2913 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2914 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2915 interconnect-names = "qup-core", 2916 "qup-config", 2917 "qup-memory"; 2918 2919 power-domains = <&rpmhpd RPMHPD_CX>; 2920 2921 operating-points-v2 = <&qup_opp_table_120mhz>; 2922 2923 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 2924 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 2925 dma-names = "tx", 2926 "rx"; 2927 2928 pinctrl-0 = <&qup_i2c0_data_clk>; 2929 pinctrl-names = "default"; 2930 2931 #address-cells = <1>; 2932 #size-cells = <0>; 2933 2934 status = "disabled"; 2935 }; 2936 2937 spi0: spi@a80000 { 2938 compatible = "qcom,geni-spi"; 2939 reg = <0 0x00a80000 0 0x4000>; 2940 2941 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 2942 2943 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2944 clock-names = "se"; 2945 2946 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2947 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2948 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2949 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2950 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2951 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2952 interconnect-names = "qup-core", 2953 "qup-config", 2954 "qup-memory"; 2955 2956 power-domains = <&rpmhpd RPMHPD_CX>; 2957 2958 operating-points-v2 = <&qup_opp_table_120mhz>; 2959 2960 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 2961 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 2962 dma-names = "tx", 2963 "rx"; 2964 2965 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2966 pinctrl-names = "default"; 2967 2968 #address-cells = <1>; 2969 #size-cells = <0>; 2970 2971 status = "disabled"; 2972 }; 2973 2974 i2c1: i2c@a84000 { 2975 compatible = "qcom,geni-i2c"; 2976 reg = <0 0x00a84000 0 0x4000>; 2977 2978 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 2979 2980 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2981 clock-names = "se"; 2982 2983 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2984 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2985 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2986 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2987 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2988 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2989 interconnect-names = "qup-core", 2990 "qup-config", 2991 "qup-memory"; 2992 2993 power-domains = <&rpmhpd RPMHPD_CX>; 2994 2995 operating-points-v2 = <&qup_opp_table_120mhz>; 2996 2997 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 2998 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 2999 dma-names = "tx", 3000 "rx"; 3001 3002 pinctrl-0 = <&qup_i2c1_data_clk>; 3003 pinctrl-names = "default"; 3004 3005 #address-cells = <1>; 3006 #size-cells = <0>; 3007 3008 status = "disabled"; 3009 }; 3010 3011 spi1: spi@a84000 { 3012 compatible = "qcom,geni-spi"; 3013 reg = <0 0x00a84000 0 0x4000>; 3014 3015 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 3016 3017 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 3018 clock-names = "se"; 3019 3020 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3021 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3022 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3023 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3024 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3025 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3026 interconnect-names = "qup-core", 3027 "qup-config", 3028 "qup-memory"; 3029 3030 power-domains = <&rpmhpd RPMHPD_CX>; 3031 3032 operating-points-v2 = <&qup_opp_table_120mhz>; 3033 3034 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 3035 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 3036 dma-names = "tx", 3037 "rx"; 3038 3039 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 3040 pinctrl-names = "default"; 3041 3042 #address-cells = <1>; 3043 #size-cells = <0>; 3044 3045 status = "disabled"; 3046 }; 3047 3048 i2c2: i2c@a88000 { 3049 compatible = "qcom,geni-i2c"; 3050 reg = <0 0x00a88000 0 0x4000>; 3051 3052 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 3053 3054 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 3055 clock-names = "se"; 3056 3057 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3058 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3059 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3060 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3061 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3062 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3063 interconnect-names = "qup-core", 3064 "qup-config", 3065 "qup-memory"; 3066 3067 power-domains = <&rpmhpd RPMHPD_CX>; 3068 3069 operating-points-v2 = <&qup_opp_table_240mhz>; 3070 3071 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 3072 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 3073 dma-names = "tx", 3074 "rx"; 3075 3076 pinctrl-0 = <&qup_i2c2_data_clk>; 3077 pinctrl-names = "default"; 3078 3079 #address-cells = <1>; 3080 #size-cells = <0>; 3081 3082 status = "disabled"; 3083 }; 3084 3085 spi2: spi@a88000 { 3086 compatible = "qcom,geni-spi"; 3087 reg = <0 0x00a88000 0 0x4000>; 3088 3089 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 3090 3091 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 3092 clock-names = "se"; 3093 3094 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3095 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3096 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3097 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3098 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3099 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3100 interconnect-names = "qup-core", 3101 "qup-config", 3102 "qup-memory"; 3103 3104 power-domains = <&rpmhpd RPMHPD_CX>; 3105 3106 operating-points-v2 = <&qup_opp_table_240mhz>; 3107 3108 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 3109 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 3110 dma-names = "tx", 3111 "rx"; 3112 3113 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 3114 pinctrl-names = "default"; 3115 3116 #address-cells = <1>; 3117 #size-cells = <0>; 3118 3119 status = "disabled"; 3120 }; 3121 3122 i2c3: i2c@a8c000 { 3123 compatible = "qcom,geni-i2c"; 3124 reg = <0 0x00a8c000 0 0x4000>; 3125 3126 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 3127 3128 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 3129 clock-names = "se"; 3130 3131 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3132 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3133 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3134 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3135 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3136 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3137 interconnect-names = "qup-core", 3138 "qup-config", 3139 "qup-memory"; 3140 3141 power-domains = <&rpmhpd RPMHPD_CX>; 3142 3143 operating-points-v2 = <&qup_opp_table_100mhz>; 3144 3145 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 3146 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 3147 dma-names = "tx", 3148 "rx"; 3149 3150 pinctrl-0 = <&qup_i2c3_data_clk>; 3151 pinctrl-names = "default"; 3152 3153 #address-cells = <1>; 3154 #size-cells = <0>; 3155 3156 status = "disabled"; 3157 }; 3158 3159 spi3: spi@a8c000 { 3160 compatible = "qcom,geni-spi"; 3161 reg = <0 0x00a8c000 0 0x4000>; 3162 3163 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 3164 3165 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 3166 clock-names = "se"; 3167 3168 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3169 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3170 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3171 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3172 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3173 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3174 interconnect-names = "qup-core", 3175 "qup-config", 3176 "qup-memory"; 3177 3178 power-domains = <&rpmhpd RPMHPD_CX>; 3179 3180 operating-points-v2 = <&qup_opp_table_100mhz>; 3181 3182 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 3183 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 3184 dma-names = "tx", 3185 "rx"; 3186 3187 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 3188 pinctrl-names = "default"; 3189 3190 #address-cells = <1>; 3191 #size-cells = <0>; 3192 3193 status = "disabled"; 3194 }; 3195 3196 i2c4: i2c@a90000 { 3197 compatible = "qcom,geni-i2c"; 3198 reg = <0 0x00a90000 0 0x4000>; 3199 3200 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; 3201 3202 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 3203 clock-names = "se"; 3204 3205 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3206 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3207 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3208 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3209 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3210 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3211 interconnect-names = "qup-core", 3212 "qup-config", 3213 "qup-memory"; 3214 3215 power-domains = <&rpmhpd RPMHPD_CX>; 3216 3217 operating-points-v2 = <&qup_opp_table_120mhz>; 3218 3219 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 3220 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 3221 dma-names = "tx", 3222 "rx"; 3223 3224 pinctrl-0 = <&qup_i2c4_data_clk>; 3225 pinctrl-names = "default"; 3226 3227 #address-cells = <1>; 3228 #size-cells = <0>; 3229 3230 status = "disabled"; 3231 }; 3232 3233 spi4: spi@a90000 { 3234 compatible = "qcom,geni-spi"; 3235 reg = <0 0x00a90000 0 0x4000>; 3236 3237 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; 3238 3239 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 3240 clock-names = "se"; 3241 3242 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3243 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3244 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3245 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3246 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3247 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3248 interconnect-names = "qup-core", 3249 "qup-config", 3250 "qup-memory"; 3251 3252 power-domains = <&rpmhpd RPMHPD_CX>; 3253 3254 operating-points-v2 = <&qup_opp_table_120mhz>; 3255 3256 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 3257 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 3258 dma-names = "tx", 3259 "rx"; 3260 3261 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 3262 pinctrl-names = "default"; 3263 3264 #address-cells = <1>; 3265 #size-cells = <0>; 3266 3267 status = "disabled"; 3268 }; 3269 3270 i2c5: i2c@a94000 { 3271 compatible = "qcom,geni-i2c"; 3272 reg = <0 0x00a94000 0 0x4000>; 3273 3274 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; 3275 3276 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 3277 clock-names = "se"; 3278 3279 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3280 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3281 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3282 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3283 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3284 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3285 interconnect-names = "qup-core", 3286 "qup-config", 3287 "qup-memory"; 3288 3289 power-domains = <&rpmhpd RPMHPD_CX>; 3290 3291 operating-points-v2 = <&qup_opp_table_100mhz>; 3292 3293 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 3294 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 3295 dma-names = "tx", 3296 "rx"; 3297 3298 pinctrl-0 = <&qup_i2c5_data_clk>; 3299 pinctrl-names = "default"; 3300 3301 #address-cells = <1>; 3302 #size-cells = <0>; 3303 3304 status = "disabled"; 3305 }; 3306 3307 spi5: spi@a94000 { 3308 compatible = "qcom,geni-spi"; 3309 reg = <0 0x00a94000 0 0x4000>; 3310 3311 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; 3312 3313 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 3314 clock-names = "se"; 3315 3316 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3317 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3318 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3319 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3320 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3321 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3322 interconnect-names = "qup-core", 3323 "qup-config", 3324 "qup-memory"; 3325 3326 power-domains = <&rpmhpd RPMHPD_CX>; 3327 3328 operating-points-v2 = <&qup_opp_table_100mhz>; 3329 3330 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 3331 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 3332 dma-names = "tx", 3333 "rx"; 3334 3335 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 3336 pinctrl-names = "default"; 3337 3338 #address-cells = <1>; 3339 #size-cells = <0>; 3340 3341 status = "disabled"; 3342 }; 3343 3344 i2c6: i2c@a98000 { 3345 compatible = "qcom,geni-i2c"; 3346 reg = <0 0x00a98000 0 0x4000>; 3347 3348 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 3349 3350 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 3351 clock-names = "se"; 3352 3353 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3354 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3355 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3356 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3357 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3358 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3359 interconnect-names = "qup-core", 3360 "qup-config", 3361 "qup-memory"; 3362 3363 power-domains = <&rpmhpd RPMHPD_CX>; 3364 3365 operating-points-v2 = <&qup_opp_table_120mhz>; 3366 3367 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 3368 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 3369 dma-names = "tx", 3370 "rx"; 3371 3372 pinctrl-0 = <&qup_i2c6_data_clk>; 3373 pinctrl-names = "default"; 3374 3375 #address-cells = <1>; 3376 #size-cells = <0>; 3377 3378 status = "disabled"; 3379 }; 3380 3381 spi6: spi@a98000 { 3382 compatible = "qcom,geni-spi"; 3383 reg = <0 0x00a98000 0 0x4000>; 3384 3385 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 3386 3387 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 3388 clock-names = "se"; 3389 3390 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3391 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3392 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3393 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3394 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3395 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3396 interconnect-names = "qup-core", 3397 "qup-config", 3398 "qup-memory"; 3399 3400 power-domains = <&rpmhpd RPMHPD_CX>; 3401 3402 operating-points-v2 = <&qup_opp_table_120mhz>; 3403 3404 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 3405 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 3406 dma-names = "tx", 3407 "rx"; 3408 3409 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 3410 pinctrl-names = "default"; 3411 3412 #address-cells = <1>; 3413 #size-cells = <0>; 3414 3415 status = "disabled"; 3416 }; 3417 3418 i2c7: i2c@a9c000 { 3419 compatible = "qcom,geni-i2c"; 3420 reg = <0 0x00a9c000 0 0x4000>; 3421 3422 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>; 3423 3424 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 3425 clock-names = "se"; 3426 3427 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3428 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3429 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3430 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3431 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3432 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3433 interconnect-names = "qup-core", 3434 "qup-config", 3435 "qup-memory"; 3436 3437 power-domains = <&rpmhpd RPMHPD_CX>; 3438 3439 operating-points-v2 = <&qup_opp_table_100mhz>; 3440 3441 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 3442 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 3443 dma-names = "tx", 3444 "rx"; 3445 3446 pinctrl-0 = <&qup_i2c7_data_clk>; 3447 pinctrl-names = "default"; 3448 3449 #address-cells = <1>; 3450 #size-cells = <0>; 3451 3452 status = "disabled"; 3453 }; 3454 3455 spi7: spi@a9c000 { 3456 compatible = "qcom,geni-spi"; 3457 reg = <0 0x00a9c000 0 0x4000>; 3458 3459 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>; 3460 3461 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 3462 clock-names = "se"; 3463 3464 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3465 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3466 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3467 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3468 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3469 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3470 interconnect-names = "qup-core", 3471 "qup-config", 3472 "qup-memory"; 3473 3474 power-domains = <&rpmhpd RPMHPD_CX>; 3475 3476 operating-points-v2 = <&qup_opp_table_100mhz>; 3477 3478 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 3479 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 3480 dma-names = "tx", 3481 "rx"; 3482 3483 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 3484 pinctrl-names = "default"; 3485 3486 #address-cells = <1>; 3487 #size-cells = <0>; 3488 3489 status = "disabled"; 3490 }; 3491 }; 3492 3493 rng: rng@10c3000 { 3494 compatible = "qcom,sm8650-trng", "qcom,trng"; 3495 reg = <0 0x010c3000 0 0x1000>; 3496 }; 3497 3498 cnoc_main: interconnect@1500000 { 3499 compatible = "qcom,sm8650-cnoc-main"; 3500 reg = <0 0x01500000 0 0x14080>; 3501 3502 qcom,bcm-voters = <&apps_bcm_voter>; 3503 3504 #interconnect-cells = <2>; 3505 }; 3506 3507 config_noc: interconnect@1600000 { 3508 compatible = "qcom,sm8650-config-noc"; 3509 reg = <0 0x01600000 0 0x6200>; 3510 3511 qcom,bcm-voters = <&apps_bcm_voter>; 3512 3513 #interconnect-cells = <2>; 3514 }; 3515 3516 system_noc: interconnect@1680000 { 3517 compatible = "qcom,sm8650-system-noc"; 3518 reg = <0 0x01680000 0 0x1d080>; 3519 3520 qcom,bcm-voters = <&apps_bcm_voter>; 3521 3522 #interconnect-cells = <2>; 3523 }; 3524 3525 pcie_noc: interconnect@16c0000 { 3526 compatible = "qcom,sm8650-pcie-anoc"; 3527 reg = <0 0x016c0000 0 0x12200>; 3528 3529 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 3530 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 3531 3532 qcom,bcm-voters = <&apps_bcm_voter>; 3533 3534 #interconnect-cells = <2>; 3535 }; 3536 3537 aggre1_noc: interconnect@16e0000 { 3538 compatible = "qcom,sm8650-aggre1-noc"; 3539 reg = <0 0x016e0000 0 0x16400>; 3540 3541 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3542 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 3543 3544 qcom,bcm-voters = <&apps_bcm_voter>; 3545 3546 #interconnect-cells = <2>; 3547 }; 3548 3549 aggre2_noc: interconnect@1700000 { 3550 compatible = "qcom,sm8650-aggre2-noc"; 3551 reg = <0 0x01700000 0 0x1e400>; 3552 3553 clocks = <&rpmhcc RPMH_IPA_CLK>; 3554 3555 qcom,bcm-voters = <&apps_bcm_voter>; 3556 3557 #interconnect-cells = <2>; 3558 }; 3559 3560 mmss_noc: interconnect@1780000 { 3561 compatible = "qcom,sm8650-mmss-noc"; 3562 reg = <0 0x01780000 0 0x5b800>; 3563 3564 qcom,bcm-voters = <&apps_bcm_voter>; 3565 3566 #interconnect-cells = <2>; 3567 }; 3568 3569 pcie0: pcie@1c00000 { 3570 device_type = "pci"; 3571 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 3572 reg = <0 0x01c00000 0 0x3000>, 3573 <0 0x60000000 0 0xf1d>, 3574 <0 0x60000f20 0 0xa8>, 3575 <0 0x60001000 0 0x1000>, 3576 <0 0x60100000 0 0x100000>; 3577 reg-names = "parf", "dbi", "elbi", "atu", "config"; 3578 3579 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>, 3580 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>, 3581 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>, 3582 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>, 3583 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>, 3584 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>, 3585 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>, 3586 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>, 3587 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>; 3588 interrupt-names = "msi0", 3589 "msi1", 3590 "msi2", 3591 "msi3", 3592 "msi4", 3593 "msi5", 3594 "msi6", 3595 "msi7", 3596 "global"; 3597 3598 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 3599 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 3600 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 3601 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 3602 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 3603 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 3604 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 3605 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 3606 clock-names = "aux", 3607 "cfg", 3608 "bus_master", 3609 "bus_slave", 3610 "slave_q2a", 3611 "ddrss_sf_tbu", 3612 "noc_aggr", 3613 "cnoc_sf_axi"; 3614 3615 resets = <&gcc GCC_PCIE_0_BCR>; 3616 reset-names = "pci"; 3617 3618 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 3619 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3620 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3621 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 3622 interconnect-names = "pcie-mem", 3623 "cpu-pcie"; 3624 3625 power-domains = <&gcc PCIE_0_GDSC>; 3626 3627 operating-points-v2 = <&pcie0_opp_table>; 3628 3629 iommu-map = <0 &apps_smmu 0x1400 0x1>, 3630 <0x100 &apps_smmu 0x1401 0x1>; 3631 3632 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, 3633 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, 3634 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, 3635 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 3636 interrupt-map-mask = <0 0 0 0x7>; 3637 #interrupt-cells = <1>; 3638 3639 msi-map = <0x0 &gic_its 0x1400 0x1>, 3640 <0x100 &gic_its 0x1401 0x1>; 3641 msi-map-mask = <0xff00>; 3642 3643 linux,pci-domain = <0>; 3644 num-lanes = <2>; 3645 bus-range = <0 0xff>; 3646 3647 phys = <&pcie0_phy>; 3648 phy-names = "pciephy"; 3649 3650 #address-cells = <3>; 3651 #size-cells = <2>; 3652 ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, 3653 <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>; 3654 3655 dma-coherent; 3656 3657 status = "disabled"; 3658 3659 pcie0_opp_table: opp-table { 3660 compatible = "operating-points-v2"; 3661 3662 /* GEN 1 x1 */ 3663 opp-2500000 { 3664 opp-hz = /bits/ 64 <2500000>; 3665 required-opps = <&rpmhpd_opp_low_svs>; 3666 opp-peak-kBps = <250000 1>; 3667 }; 3668 3669 /* GEN 1 x2 and GEN 2 x1 */ 3670 opp-5000000 { 3671 opp-hz = /bits/ 64 <5000000>; 3672 required-opps = <&rpmhpd_opp_low_svs>; 3673 opp-peak-kBps = <500000 1>; 3674 }; 3675 3676 /* GEN 2 x2 */ 3677 opp-10000000 { 3678 opp-hz = /bits/ 64 <10000000>; 3679 required-opps = <&rpmhpd_opp_low_svs>; 3680 opp-peak-kBps = <1000000 1>; 3681 }; 3682 3683 /* GEN 3 x1 */ 3684 opp-8000000 { 3685 opp-hz = /bits/ 64 <8000000>; 3686 required-opps = <&rpmhpd_opp_nom>; 3687 opp-peak-kBps = <984500 1>; 3688 }; 3689 3690 /* GEN 3 x2 */ 3691 opp-16000000 { 3692 opp-hz = /bits/ 64 <16000000>; 3693 required-opps = <&rpmhpd_opp_nom>; 3694 opp-peak-kBps = <1969000 1>; 3695 }; 3696 }; 3697 3698 pcieport0: pcie@0 { 3699 device_type = "pci"; 3700 reg = <0x0 0x0 0x0 0x0 0x0>; 3701 bus-range = <0x01 0xff>; 3702 3703 #address-cells = <3>; 3704 #size-cells = <2>; 3705 ranges; 3706 }; 3707 }; 3708 3709 pcie0_phy: phy@1c06000 { 3710 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy"; 3711 reg = <0 0x01c06000 0 0x2000>; 3712 3713 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 3714 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 3715 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 3716 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 3717 <&gcc GCC_PCIE_0_PIPE_CLK>; 3718 clock-names = "aux", 3719 "cfg_ahb", 3720 "ref", 3721 "rchng", 3722 "pipe"; 3723 3724 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 3725 assigned-clock-rates = <100000000>; 3726 3727 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 3728 reset-names = "phy"; 3729 3730 power-domains = <&gcc PCIE_0_PHY_GDSC>; 3731 3732 #clock-cells = <0>; 3733 clock-output-names = "pcie0_pipe_clk"; 3734 3735 #phy-cells = <0>; 3736 3737 status = "disabled"; 3738 }; 3739 3740 pcie1: pcie@1c08000 { 3741 device_type = "pci"; 3742 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 3743 reg = <0 0x01c08000 0 0x3000>, 3744 <0 0x40000000 0 0xf1d>, 3745 <0 0x40000f20 0 0xa8>, 3746 <0 0x40001000 0 0x1000>, 3747 <0 0x40100000 0 0x100000>; 3748 reg-names = "parf", 3749 "dbi", 3750 "elbi", 3751 "atu", 3752 "config"; 3753 3754 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>, 3755 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>, 3756 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>, 3757 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 0>, 3758 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>, 3759 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 0>, 3760 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, 3761 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH 0>, 3762 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 3763 interrupt-names = "msi0", 3764 "msi1", 3765 "msi2", 3766 "msi3", 3767 "msi4", 3768 "msi5", 3769 "msi6", 3770 "msi7", 3771 "global"; 3772 3773 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 3774 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 3775 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 3776 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 3777 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 3778 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 3779 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 3780 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 3781 clock-names = "aux", 3782 "cfg", 3783 "bus_master", 3784 "bus_slave", 3785 "slave_q2a", 3786 "ddrss_sf_tbu", 3787 "noc_aggr", 3788 "cnoc_sf_axi"; 3789 3790 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 3791 assigned-clock-rates = <19200000>; 3792 3793 resets = <&gcc GCC_PCIE_1_BCR>, 3794 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 3795 reset-names = "pci", 3796 "link_down"; 3797 3798 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 3799 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3800 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3801 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3802 interconnect-names = "pcie-mem", 3803 "cpu-pcie"; 3804 3805 power-domains = <&gcc PCIE_1_GDSC>; 3806 3807 operating-points-v2 = <&pcie1_opp_table>; 3808 3809 iommu-map = <0 &apps_smmu 0x1480 0x1>, 3810 <0x100 &apps_smmu 0x1481 0x1>; 3811 3812 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, 3813 <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, 3814 <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, 3815 <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; 3816 interrupt-map-mask = <0 0 0 0x7>; 3817 #interrupt-cells = <1>; 3818 3819 msi-map = <0x0 &gic_its 0x1480 0x1>, 3820 <0x100 &gic_its 0x1481 0x1>; 3821 msi-map-mask = <0xff00>; 3822 3823 linux,pci-domain = <1>; 3824 num-lanes = <2>; 3825 bus-range = <0 0xff>; 3826 3827 phys = <&pcie1_phy>; 3828 phy-names = "pciephy"; 3829 3830 dma-coherent; 3831 3832 #address-cells = <3>; 3833 #size-cells = <2>; 3834 ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, 3835 <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; 3836 3837 status = "disabled"; 3838 3839 pcie1_opp_table: opp-table { 3840 compatible = "operating-points-v2"; 3841 3842 /* GEN 1 x1 */ 3843 opp-2500000 { 3844 opp-hz = /bits/ 64 <2500000>; 3845 required-opps = <&rpmhpd_opp_low_svs>; 3846 opp-peak-kBps = <250000 1>; 3847 }; 3848 3849 /* GEN 1 x2 and GEN 2 x1 */ 3850 opp-5000000 { 3851 opp-hz = /bits/ 64 <5000000>; 3852 required-opps = <&rpmhpd_opp_low_svs>; 3853 opp-peak-kBps = <500000 1>; 3854 }; 3855 3856 /* GEN 2 x2 */ 3857 opp-10000000 { 3858 opp-hz = /bits/ 64 <10000000>; 3859 required-opps = <&rpmhpd_opp_low_svs>; 3860 opp-peak-kBps = <1000000 1>; 3861 }; 3862 3863 /* GEN 3 x1 */ 3864 opp-8000000 { 3865 opp-hz = /bits/ 64 <8000000>; 3866 required-opps = <&rpmhpd_opp_nom>; 3867 opp-peak-kBps = <984500 1>; 3868 }; 3869 3870 /* GEN 3 x2 and GEN 4 x1 */ 3871 opp-16000000 { 3872 opp-hz = /bits/ 64 <16000000>; 3873 required-opps = <&rpmhpd_opp_nom>; 3874 opp-peak-kBps = <1969000 1>; 3875 }; 3876 3877 /* GEN 4 x2 */ 3878 opp-32000000 { 3879 opp-hz = /bits/ 64 <32000000>; 3880 required-opps = <&rpmhpd_opp_nom>; 3881 opp-peak-kBps = <3938000 1>; 3882 }; 3883 }; 3884 3885 pcie@0 { 3886 device_type = "pci"; 3887 reg = <0x0 0x0 0x0 0x0 0x0>; 3888 bus-range = <0x01 0xff>; 3889 3890 #address-cells = <3>; 3891 #size-cells = <2>; 3892 ranges; 3893 }; 3894 }; 3895 3896 pcie1_phy: phy@1c0e000 { 3897 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy"; 3898 reg = <0 0x01c0e000 0 0x2000>; 3899 3900 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 3901 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 3902 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 3903 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 3904 <&gcc GCC_PCIE_1_PIPE_CLK>; 3905 clock-names = "aux", 3906 "cfg_ahb", 3907 "ref", 3908 "rchng", 3909 "pipe"; 3910 3911 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 3912 assigned-clock-rates = <100000000>; 3913 3914 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 3915 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 3916 reset-names = "phy", 3917 "phy_nocsr"; 3918 3919 power-domains = <&gcc PCIE_1_PHY_GDSC>; 3920 3921 #clock-cells = <1>; 3922 clock-output-names = "pcie1_pipe_clk"; 3923 3924 #phy-cells = <0>; 3925 3926 status = "disabled"; 3927 }; 3928 3929 ufs_mem_phy: phy@1d80000 { 3930 compatible = "qcom,sm8650-qmp-ufs-phy"; 3931 reg = <0 0x01d80000 0 0x2000>; 3932 3933 clocks = <&rpmhcc RPMH_CXO_CLK>, 3934 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 3935 <&tcsr TCSR_UFS_CLKREF_EN>; 3936 clock-names = "ref", 3937 "ref_aux", 3938 "qref"; 3939 3940 resets = <&ufs_mem_hc 0>; 3941 reset-names = "ufsphy"; 3942 3943 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 3944 3945 #clock-cells = <1>; 3946 #phy-cells = <0>; 3947 3948 status = "disabled"; 3949 }; 3950 3951 ufs_mem_hc: ufshc@1d84000 { 3952 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 3953 reg = <0 0x01d84000 0 0x3000>; 3954 3955 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 3956 3957 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 3958 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3959 <&gcc GCC_UFS_PHY_AHB_CLK>, 3960 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 3961 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 3962 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 3963 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 3964 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 3965 clock-names = "core_clk", 3966 "bus_aggr_clk", 3967 "iface_clk", 3968 "core_clk_unipro", 3969 "ref_clk", 3970 "tx_lane0_sync_clk", 3971 "rx_lane0_sync_clk", 3972 "rx_lane1_sync_clk"; 3973 3974 resets = <&gcc GCC_UFS_PHY_BCR>; 3975 reset-names = "rst"; 3976 3977 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 3978 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3979 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3980 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3981 interconnect-names = "ufs-ddr", 3982 "cpu-ufs"; 3983 3984 power-domains = <&gcc UFS_PHY_GDSC>; 3985 required-opps = <&rpmhpd_opp_nom>; 3986 3987 operating-points-v2 = <&ufs_opp_table>; 3988 3989 iommus = <&apps_smmu 0x60 0>; 3990 3991 lanes-per-direction = <2>; 3992 qcom,ice = <&ice>; 3993 3994 phys = <&ufs_mem_phy>; 3995 phy-names = "ufsphy"; 3996 3997 #reset-cells = <1>; 3998 3999 status = "disabled"; 4000 4001 ufs_opp_table: opp-table { 4002 compatible = "operating-points-v2"; 4003 4004 opp-100000000 { 4005 opp-hz = /bits/ 64 <100000000>, 4006 /bits/ 64 <0>, 4007 /bits/ 64 <0>, 4008 /bits/ 64 <100000000>, 4009 /bits/ 64 <0>, 4010 /bits/ 64 <0>, 4011 /bits/ 64 <0>, 4012 /bits/ 64 <0>; 4013 required-opps = <&rpmhpd_opp_low_svs>; 4014 }; 4015 4016 opp-201500000 { 4017 opp-hz = /bits/ 64 <201500000>, 4018 /bits/ 64 <0>, 4019 /bits/ 64 <0>, 4020 /bits/ 64 <201500000>, 4021 /bits/ 64 <0>, 4022 /bits/ 64 <0>, 4023 /bits/ 64 <0>, 4024 /bits/ 64 <0>; 4025 required-opps = <&rpmhpd_opp_svs>; 4026 }; 4027 4028 opp-403000000 { 4029 opp-hz = /bits/ 64 <403000000>, 4030 /bits/ 64 <0>, 4031 /bits/ 64 <0>, 4032 /bits/ 64 <403000000>, 4033 /bits/ 64 <0>, 4034 /bits/ 64 <0>, 4035 /bits/ 64 <0>, 4036 /bits/ 64 <0>; 4037 required-opps = <&rpmhpd_opp_nom>; 4038 }; 4039 }; 4040 }; 4041 4042 ice: crypto@1d88000 { 4043 compatible = "qcom,sm8650-inline-crypto-engine", 4044 "qcom,inline-crypto-engine"; 4045 reg = <0 0x01d88000 0 0x18000>; 4046 4047 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4048 }; 4049 4050 cryptobam: dma-controller@1dc4000 { 4051 compatible = "qcom,bam-v1.7.0"; 4052 reg = <0 0x01dc4000 0 0x28000>; 4053 4054 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; 4055 4056 #dma-cells = <1>; 4057 4058 iommus = <&apps_smmu 0x480 0>, 4059 <&apps_smmu 0x481 0>; 4060 4061 qcom,ee = <0>; 4062 qcom,num-ees = <4>; 4063 num-channels = <20>; 4064 qcom,controlled-remotely; 4065 }; 4066 4067 crypto: crypto@1dfa000 { 4068 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; 4069 reg = <0 0x01dfa000 0 0x6000>; 4070 4071 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 4072 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4073 interconnect-names = "memory"; 4074 4075 dmas = <&cryptobam 4>, <&cryptobam 5>; 4076 dma-names = "rx", "tx"; 4077 4078 iommus = <&apps_smmu 0x480 0>, 4079 <&apps_smmu 0x481 0>; 4080 }; 4081 4082 tcsr_mutex: hwlock@1f40000 { 4083 compatible = "qcom,tcsr-mutex"; 4084 reg = <0 0x01f40000 0 0x20000>; 4085 4086 #hwlock-cells = <1>; 4087 }; 4088 4089 tcsr: clock-controller@1fc0000 { 4090 compatible = "qcom,sm8650-tcsr", "syscon"; 4091 reg = <0 0x01fc0000 0 0xa0000>; 4092 4093 clocks = <&rpmhcc RPMH_CXO_CLK>; 4094 4095 #clock-cells = <1>; 4096 #reset-cells = <1>; 4097 }; 4098 4099 gpu: gpu@3d00000 { 4100 compatible = "qcom,adreno-43051401", "qcom,adreno"; 4101 reg = <0x0 0x03d00000 0x0 0x40000>, 4102 <0x0 0x03d9e000 0x0 0x2000>, 4103 <0x0 0x03d61000 0x0 0x800>; 4104 reg-names = "kgsl_3d0_reg_memory", 4105 "cx_mem", 4106 "cx_dbgc"; 4107 4108 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; 4109 4110 iommus = <&adreno_smmu 0 0x0>, 4111 <&adreno_smmu 1 0x0>; 4112 4113 operating-points-v2 = <&gpu_opp_table>; 4114 4115 qcom,gmu = <&gmu>; 4116 #cooling-cells = <2>; 4117 4118 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4119 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4120 interconnect-names = "gfx-mem"; 4121 4122 status = "disabled"; 4123 4124 zap-shader { 4125 memory-region = <&gpu_micro_code_mem>; 4126 }; 4127 4128 /* Speedbin needs more work on A740+, keep only lower freqs */ 4129 gpu_opp_table: opp-table { 4130 compatible = "operating-points-v2-adreno", 4131 "operating-points-v2"; 4132 4133 opp-231000000 { 4134 opp-hz = /bits/ 64 <231000000>; 4135 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 4136 opp-peak-kBps = <2136718>; 4137 qcom,opp-acd-level = <0xc82f5ffd>; 4138 }; 4139 4140 opp-310000000 { 4141 opp-hz = /bits/ 64 <310000000>; 4142 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4143 opp-peak-kBps = <2136718>; 4144 qcom,opp-acd-level = <0xc82c5ffd>; 4145 }; 4146 4147 opp-366000000 { 4148 opp-hz = /bits/ 64 <366000000>; 4149 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 4150 opp-peak-kBps = <6074218>; 4151 qcom,opp-acd-level = <0xc02e5ffd>; 4152 }; 4153 4154 opp-422000000 { 4155 opp-hz = /bits/ 64 <422000000>; 4156 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4157 opp-peak-kBps = <8171875>; 4158 qcom,opp-acd-level = <0xc02d5ffd>; 4159 }; 4160 4161 opp-500000000 { 4162 opp-hz = /bits/ 64 <500000000>; 4163 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4164 opp-peak-kBps = <8171875>; 4165 qcom,opp-acd-level = <0xc02a5ffd>; 4166 }; 4167 4168 opp-578000000 { 4169 opp-hz = /bits/ 64 <578000000>; 4170 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4171 opp-peak-kBps = <8171875>; 4172 qcom,opp-acd-level = <0x882c5ffd>; 4173 }; 4174 4175 opp-629000000 { 4176 opp-hz = /bits/ 64 <629000000>; 4177 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4178 opp-peak-kBps = <10687500>; 4179 qcom,opp-acd-level = <0x882a5ffd>; 4180 }; 4181 4182 opp-680000000 { 4183 opp-hz = /bits/ 64 <680000000>; 4184 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4185 opp-peak-kBps = <12449218>; 4186 qcom,opp-acd-level = <0x882a5ffd>; 4187 }; 4188 4189 opp-720000000 { 4190 opp-hz = /bits/ 64 <720000000>; 4191 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4192 opp-peak-kBps = <12449218>; 4193 qcom,opp-acd-level = <0x882a5ffd>; 4194 }; 4195 4196 opp-770000000 { 4197 opp-hz = /bits/ 64 <770000000>; 4198 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4199 opp-peak-kBps = <12449218>; 4200 qcom,opp-acd-level = <0x882a5ffd>; 4201 }; 4202 4203 opp-834000000 { 4204 opp-hz = /bits/ 64 <834000000>; 4205 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4206 opp-peak-kBps = <14398437>; 4207 qcom,opp-acd-level = <0x882a5ffd>; 4208 }; 4209 }; 4210 }; 4211 4212 gmu: gmu@3d6a000 { 4213 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; 4214 reg = <0x0 0x03d6a000 0x0 0x35000>, 4215 <0x0 0x03d50000 0x0 0x10000>, 4216 <0x0 0x0b280000 0x0 0x10000>; 4217 reg-names = "gmu", "rscc", "gmu_pdc"; 4218 4219 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>, 4220 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 4221 interrupt-names = "hfi", "gmu"; 4222 4223 clocks = <&gpucc GPU_CC_AHB_CLK>, 4224 <&gpucc GPU_CC_CX_GMU_CLK>, 4225 <&gpucc GPU_CC_CXO_CLK>, 4226 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4227 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4228 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4229 <&gpucc GPU_CC_DEMET_CLK>; 4230 clock-names = "ahb", 4231 "gmu", 4232 "cxo", 4233 "axi", 4234 "memnoc", 4235 "hub", 4236 "demet"; 4237 4238 power-domains = <&gpucc GPU_CX_GDSC>, 4239 <&gpucc GPU_GX_GDSC>; 4240 power-domain-names = "cx", 4241 "gx"; 4242 4243 iommus = <&adreno_smmu 5 0x0>; 4244 4245 qcom,qmp = <&aoss_qmp>; 4246 4247 operating-points-v2 = <&gmu_opp_table>; 4248 4249 gmu_opp_table: opp-table { 4250 compatible = "operating-points-v2"; 4251 4252 opp-260000000 { 4253 opp-hz = /bits/ 64 <260000000>; 4254 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4255 }; 4256 4257 opp-625000000 { 4258 opp-hz = /bits/ 64 <625000000>; 4259 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4260 }; 4261 }; 4262 }; 4263 4264 gpucc: clock-controller@3d90000 { 4265 compatible = "qcom,sm8650-gpucc"; 4266 reg = <0 0x03d90000 0 0xa000>; 4267 4268 clocks = <&bi_tcxo_div2>, 4269 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4270 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4271 4272 #clock-cells = <1>; 4273 #reset-cells = <1>; 4274 #power-domain-cells = <1>; 4275 }; 4276 4277 adreno_smmu: iommu@3da0000 { 4278 compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", 4279 "qcom,smmu-500", "arm,mmu-500"; 4280 reg = <0x0 0x03da0000 0x0 0x40000>; 4281 #iommu-cells = <2>; 4282 #global-interrupts = <1>; 4283 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>, 4284 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>, 4285 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>, 4286 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>, 4287 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>, 4288 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>, 4289 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>, 4290 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>, 4291 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>, 4292 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>, 4293 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>, 4294 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>, 4295 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>, 4296 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>, 4297 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>, 4298 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>, 4299 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>, 4300 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>, 4301 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>, 4302 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>, 4303 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, 4304 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>, 4305 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>, 4306 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>, 4307 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>, 4308 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>; 4309 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4310 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4311 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4312 <&gpucc GPU_CC_AHB_CLK>; 4313 clock-names = "hlos", 4314 "bus", 4315 "iface", 4316 "ahb"; 4317 power-domains = <&gpucc GPU_CX_GDSC>; 4318 dma-coherent; 4319 }; 4320 4321 ipa: ipa@3f40000 { 4322 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; 4323 4324 iommus = <&apps_smmu 0x4a0 0x0>, 4325 <&apps_smmu 0x4a2 0x0>; 4326 reg = <0 0x3f40000 0 0x10000>, 4327 <0 0x3f50000 0 0x5000>, 4328 <0 0x3e04000 0 0xfc000>; 4329 reg-names = "ipa-reg", 4330 "ipa-shared", 4331 "gsi"; 4332 4333 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>, 4334 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>, 4335 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4336 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 4337 interrupt-names = "ipa", 4338 "gsi", 4339 "ipa-clock-query", 4340 "ipa-setup-ready"; 4341 4342 clocks = <&rpmhcc RPMH_IPA_CLK>; 4343 clock-names = "core"; 4344 4345 interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS 4346 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4347 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4348 &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4349 interconnect-names = "memory", 4350 "config"; 4351 4352 qcom,qmp = <&aoss_qmp>; 4353 4354 qcom,smem-states = <&ipa_smp2p_out 0>, 4355 <&ipa_smp2p_out 1>; 4356 qcom,smem-state-names = "ipa-clock-enabled-valid", 4357 "ipa-clock-enabled"; 4358 4359 status = "disabled"; 4360 }; 4361 4362 remoteproc_mpss: remoteproc@4080000 { 4363 compatible = "qcom,sm8650-mpss-pas"; 4364 reg = <0x0 0x04080000 0x0 0x10000>; 4365 4366 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, 4367 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 4368 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 4369 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 4370 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 4371 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 4372 interrupt-names = "wdog", 4373 "fatal", 4374 "ready", 4375 "handover", 4376 "stop-ack", 4377 "shutdown-ack"; 4378 4379 clocks = <&rpmhcc RPMH_CXO_CLK>; 4380 clock-names = "xo"; 4381 4382 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 4383 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4384 4385 power-domains = <&rpmhpd RPMHPD_CX>, 4386 <&rpmhpd RPMHPD_MSS>; 4387 power-domain-names = "cx", 4388 "mss"; 4389 4390 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, 4391 <&mpss_dsm_mem>, <&mpss_dsm_mem_2>, 4392 <&qlink_logging_mem>; 4393 4394 qcom,qmp = <&aoss_qmp>; 4395 4396 qcom,smem-states = <&smp2p_modem_out 0>; 4397 qcom,smem-state-names = "stop"; 4398 4399 status = "disabled"; 4400 4401 glink-edge { 4402 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 4403 IPCC_MPROC_SIGNAL_GLINK_QMP 4404 IRQ_TYPE_EDGE_RISING>; 4405 4406 mboxes = <&ipcc IPCC_CLIENT_MPSS 4407 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4408 4409 qcom,remote-pid = <1>; 4410 4411 label = "mpss"; 4412 }; 4413 }; 4414 4415 remoteproc_adsp: remoteproc@6800000 { 4416 compatible = "qcom,sm8650-adsp-pas"; 4417 reg = <0x0 0x06800000 0x0 0x10000>; 4418 4419 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4420 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4421 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4422 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4423 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4424 interrupt-names = "wdog", 4425 "fatal", 4426 "ready", 4427 "handover", 4428 "stop-ack"; 4429 4430 clocks = <&rpmhcc RPMH_CXO_CLK>; 4431 clock-names = "xo"; 4432 4433 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 4434 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4435 4436 power-domains = <&rpmhpd RPMHPD_LCX>, 4437 <&rpmhpd RPMHPD_LMX>; 4438 power-domain-names = "lcx", 4439 "lmx"; 4440 4441 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 4442 4443 qcom,qmp = <&aoss_qmp>; 4444 4445 qcom,smem-states = <&smp2p_adsp_out 0>; 4446 qcom,smem-state-names = "stop"; 4447 4448 status = "disabled"; 4449 4450 remoteproc_adsp_glink: glink-edge { 4451 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4452 IPCC_MPROC_SIGNAL_GLINK_QMP 4453 IRQ_TYPE_EDGE_RISING>; 4454 4455 mboxes = <&ipcc IPCC_CLIENT_LPASS 4456 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4457 4458 qcom,remote-pid = <2>; 4459 4460 label = "lpass"; 4461 4462 fastrpc { 4463 compatible = "qcom,fastrpc"; 4464 4465 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4466 4467 label = "adsp"; 4468 4469 qcom,non-secure-domain; 4470 4471 #address-cells = <1>; 4472 #size-cells = <0>; 4473 4474 compute-cb@3 { 4475 compatible = "qcom,fastrpc-compute-cb"; 4476 reg = <3>; 4477 4478 iommus = <&apps_smmu 0x1003 0x80>, 4479 <&apps_smmu 0x1043 0x20>; 4480 dma-coherent; 4481 }; 4482 4483 compute-cb@4 { 4484 compatible = "qcom,fastrpc-compute-cb"; 4485 reg = <4>; 4486 4487 iommus = <&apps_smmu 0x1004 0x80>, 4488 <&apps_smmu 0x1044 0x20>; 4489 dma-coherent; 4490 }; 4491 4492 compute-cb@5 { 4493 compatible = "qcom,fastrpc-compute-cb"; 4494 reg = <5>; 4495 4496 iommus = <&apps_smmu 0x1005 0x80>, 4497 <&apps_smmu 0x1045 0x20>; 4498 dma-coherent; 4499 }; 4500 4501 compute-cb@6 { 4502 compatible = "qcom,fastrpc-compute-cb"; 4503 reg = <6>; 4504 4505 iommus = <&apps_smmu 0x1006 0x80>, 4506 <&apps_smmu 0x1046 0x20>; 4507 dma-coherent; 4508 }; 4509 4510 compute-cb@7 { 4511 compatible = "qcom,fastrpc-compute-cb"; 4512 reg = <7>; 4513 4514 iommus = <&apps_smmu 0x1007 0x40>, 4515 <&apps_smmu 0x1067 0x0>, 4516 <&apps_smmu 0x1087 0x0>; 4517 dma-coherent; 4518 }; 4519 }; 4520 4521 gpr { 4522 compatible = "qcom,gpr"; 4523 qcom,glink-channels = "adsp_apps"; 4524 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4525 qcom,intents = <512 20>; 4526 #address-cells = <1>; 4527 #size-cells = <0>; 4528 4529 q6apm: service@1 { 4530 compatible = "qcom,q6apm"; 4531 reg = <GPR_APM_MODULE_IID>; 4532 #sound-dai-cells = <0>; 4533 qcom,protection-domain = "avs/audio", 4534 "msm/adsp/audio_pd"; 4535 4536 q6apmbedai: bedais { 4537 compatible = "qcom,q6apm-lpass-dais"; 4538 #sound-dai-cells = <1>; 4539 }; 4540 4541 q6apmdai: dais { 4542 compatible = "qcom,q6apm-dais"; 4543 iommus = <&apps_smmu 0x1001 0x80>, 4544 <&apps_smmu 0x1061 0x0>; 4545 }; 4546 }; 4547 4548 q6prm: service@2 { 4549 compatible = "qcom,q6prm"; 4550 reg = <GPR_PRM_MODULE_IID>; 4551 qcom,protection-domain = "avs/audio", 4552 "msm/adsp/audio_pd"; 4553 4554 q6prmcc: clock-controller { 4555 compatible = "qcom,q6prm-lpass-clocks"; 4556 #clock-cells = <2>; 4557 }; 4558 }; 4559 }; 4560 }; 4561 }; 4562 4563 lpass_wsa2macro: codec@6aa0000 { 4564 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4565 reg = <0 0x06aa0000 0 0x1000>; 4566 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4567 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4568 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4569 <&lpass_vamacro>; 4570 clock-names = "mclk", 4571 "macro", 4572 "dcodec", 4573 "fsgen"; 4574 4575 #clock-cells = <0>; 4576 clock-output-names = "wsa2-mclk"; 4577 #sound-dai-cells = <1>; 4578 }; 4579 4580 swr3: soundwire@6ab0000 { 4581 compatible = "qcom,soundwire-v2.0.0"; 4582 reg = <0 0x06ab0000 0 0x10000>; 4583 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 4584 clocks = <&lpass_wsa2macro>; 4585 clock-names = "iface"; 4586 label = "WSA2"; 4587 4588 pinctrl-0 = <&wsa2_swr_active>; 4589 pinctrl-names = "default"; 4590 4591 qcom,din-ports = <4>; 4592 qcom,dout-ports = <9>; 4593 4594 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4595 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4596 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4597 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4598 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4599 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4600 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4601 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4602 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4603 4604 #address-cells = <2>; 4605 #size-cells = <0>; 4606 #sound-dai-cells = <1>; 4607 status = "disabled"; 4608 }; 4609 4610 lpass_rxmacro: codec@6ac0000 { 4611 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 4612 reg = <0 0x06ac0000 0 0x1000>; 4613 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4614 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4615 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4616 <&lpass_vamacro>; 4617 clock-names = "mclk", 4618 "macro", 4619 "dcodec", 4620 "fsgen"; 4621 4622 #clock-cells = <0>; 4623 clock-output-names = "mclk"; 4624 #sound-dai-cells = <1>; 4625 }; 4626 4627 swr1: soundwire@6ad0000 { 4628 compatible = "qcom,soundwire-v2.0.0"; 4629 reg = <0 0x06ad0000 0 0x10000>; 4630 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 4631 clocks = <&lpass_rxmacro>; 4632 clock-names = "iface"; 4633 label = "RX"; 4634 4635 pinctrl-0 = <&rx_swr_active>; 4636 pinctrl-names = "default"; 4637 4638 qcom,din-ports = <0>; 4639 qcom,dout-ports = <11>; 4640 4641 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>; 4642 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>; 4643 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 4644 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>; 4645 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>; 4646 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>; 4647 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>; 4648 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>; 4649 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; 4650 4651 #address-cells = <2>; 4652 #size-cells = <0>; 4653 #sound-dai-cells = <1>; 4654 status = "disabled"; 4655 }; 4656 4657 lpass_txmacro: codec@6ae0000 { 4658 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 4659 reg = <0 0x06ae0000 0 0x1000>; 4660 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4661 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4662 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4663 <&lpass_vamacro>; 4664 clock-names = "mclk", 4665 "macro", 4666 "dcodec", 4667 "fsgen"; 4668 4669 #clock-cells = <0>; 4670 clock-output-names = "mclk"; 4671 #sound-dai-cells = <1>; 4672 }; 4673 4674 lpass_wsamacro: codec@6b00000 { 4675 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4676 reg = <0 0x06b00000 0 0x1000>; 4677 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4678 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4679 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4680 <&lpass_vamacro>; 4681 clock-names = "mclk", 4682 "macro", 4683 "dcodec", 4684 "fsgen"; 4685 4686 #clock-cells = <0>; 4687 clock-output-names = "mclk"; 4688 #sound-dai-cells = <1>; 4689 }; 4690 4691 swr0: soundwire@6b10000 { 4692 compatible = "qcom,soundwire-v2.0.0"; 4693 reg = <0 0x06b10000 0 0x10000>; 4694 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 4695 clocks = <&lpass_wsamacro>; 4696 clock-names = "iface"; 4697 label = "WSA"; 4698 4699 pinctrl-0 = <&wsa_swr_active>; 4700 pinctrl-names = "default"; 4701 4702 qcom,din-ports = <4>; 4703 qcom,dout-ports = <9>; 4704 4705 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4706 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4707 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4708 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4709 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4710 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4711 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4712 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4713 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4714 4715 #address-cells = <2>; 4716 #size-cells = <0>; 4717 #sound-dai-cells = <1>; 4718 status = "disabled"; 4719 }; 4720 4721 swr2: soundwire@6d30000 { 4722 compatible = "qcom,soundwire-v2.0.0"; 4723 reg = <0 0x06d30000 0 0x10000>; 4724 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>, 4725 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>; 4726 interrupt-names = "core", "wakeup"; 4727 clocks = <&lpass_txmacro>; 4728 clock-names = "iface"; 4729 label = "TX"; 4730 4731 pinctrl-0 = <&tx_swr_active>; 4732 pinctrl-names = "default"; 4733 4734 qcom,din-ports = <4>; 4735 qcom,dout-ports = <0>; 4736 4737 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 4738 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 4739 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 4740 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 4741 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 4742 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 4743 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 4744 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 4745 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 4746 4747 #address-cells = <2>; 4748 #size-cells = <0>; 4749 #sound-dai-cells = <1>; 4750 status = "disabled"; 4751 }; 4752 4753 lpass_vamacro: codec@6d44000 { 4754 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 4755 reg = <0 0x06d44000 0 0x1000>; 4756 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4757 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4758 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4759 clock-names = "mclk", 4760 "macro", 4761 "dcodec"; 4762 4763 #clock-cells = <0>; 4764 clock-output-names = "fsgen"; 4765 #sound-dai-cells = <1>; 4766 }; 4767 4768 lpass_tlmm: pinctrl@6e80000 { 4769 compatible = "qcom,sm8650-lpass-lpi-pinctrl"; 4770 reg = <0 0x06e80000 0 0x20000>; 4771 4772 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4773 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4774 clock-names = "core", "audio"; 4775 4776 gpio-controller; 4777 #gpio-cells = <2>; 4778 gpio-ranges = <&lpass_tlmm 0 0 23>; 4779 4780 tx_swr_active: tx-swr-active-state { 4781 clk-pins { 4782 pins = "gpio0"; 4783 function = "swr_tx_clk"; 4784 drive-strength = <2>; 4785 slew-rate = <1>; 4786 bias-disable; 4787 }; 4788 4789 data-pins { 4790 pins = "gpio1", "gpio2", "gpio14"; 4791 function = "swr_tx_data"; 4792 drive-strength = <2>; 4793 slew-rate = <1>; 4794 bias-bus-hold; 4795 }; 4796 }; 4797 4798 rx_swr_active: rx-swr-active-state { 4799 clk-pins { 4800 pins = "gpio3"; 4801 function = "swr_rx_clk"; 4802 drive-strength = <2>; 4803 slew-rate = <1>; 4804 bias-disable; 4805 }; 4806 4807 data-pins { 4808 pins = "gpio4", "gpio5"; 4809 function = "swr_rx_data"; 4810 drive-strength = <2>; 4811 slew-rate = <1>; 4812 bias-bus-hold; 4813 }; 4814 }; 4815 4816 dmic01_default: dmic01-default-state { 4817 clk-pins { 4818 pins = "gpio6"; 4819 function = "dmic1_clk"; 4820 drive-strength = <8>; 4821 output-high; 4822 }; 4823 4824 data-pins { 4825 pins = "gpio7"; 4826 function = "dmic1_data"; 4827 drive-strength = <8>; 4828 input-enable; 4829 }; 4830 }; 4831 4832 dmic23_default: dmic23-default-state { 4833 clk-pins { 4834 pins = "gpio8"; 4835 function = "dmic2_clk"; 4836 drive-strength = <8>; 4837 output-high; 4838 }; 4839 4840 data-pins { 4841 pins = "gpio9"; 4842 function = "dmic2_data"; 4843 drive-strength = <8>; 4844 input-enable; 4845 }; 4846 }; 4847 4848 wsa_swr_active: wsa-swr-active-state { 4849 clk-pins { 4850 pins = "gpio10"; 4851 function = "wsa_swr_clk"; 4852 drive-strength = <2>; 4853 slew-rate = <1>; 4854 bias-disable; 4855 }; 4856 4857 data-pins { 4858 pins = "gpio11"; 4859 function = "wsa_swr_data"; 4860 drive-strength = <2>; 4861 slew-rate = <1>; 4862 bias-bus-hold; 4863 }; 4864 }; 4865 4866 wsa2_swr_active: wsa2-swr-active-state { 4867 clk-pins { 4868 pins = "gpio15"; 4869 function = "wsa2_swr_clk"; 4870 drive-strength = <2>; 4871 slew-rate = <1>; 4872 bias-disable; 4873 }; 4874 4875 data-pins { 4876 pins = "gpio16"; 4877 function = "wsa2_swr_data"; 4878 drive-strength = <2>; 4879 slew-rate = <1>; 4880 bias-bus-hold; 4881 }; 4882 }; 4883 }; 4884 4885 lpass_lpiaon_noc: interconnect@7400000 { 4886 compatible = "qcom,sm8650-lpass-lpiaon-noc"; 4887 reg = <0 0x07400000 0 0x19080>; 4888 4889 #interconnect-cells = <2>; 4890 4891 qcom,bcm-voters = <&apps_bcm_voter>; 4892 }; 4893 4894 lpass_lpicx_noc: interconnect@7430000 { 4895 compatible = "qcom,sm8650-lpass-lpicx-noc"; 4896 reg = <0 0x07430000 0 0x3a200>; 4897 4898 #interconnect-cells = <2>; 4899 4900 qcom,bcm-voters = <&apps_bcm_voter>; 4901 }; 4902 4903 lpass_ag_noc: interconnect@7e40000 { 4904 compatible = "qcom,sm8650-lpass-ag-noc"; 4905 reg = <0 0x07e40000 0 0xe080>; 4906 4907 #interconnect-cells = <2>; 4908 4909 qcom,bcm-voters = <&apps_bcm_voter>; 4910 }; 4911 4912 sdhc_2: mmc@8804000 { 4913 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; 4914 reg = <0 0x08804000 0 0x1000>; 4915 4916 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>, 4917 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH 0>; 4918 interrupt-names = "hc_irq", 4919 "pwr_irq"; 4920 4921 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4922 <&gcc GCC_SDCC2_APPS_CLK>, 4923 <&rpmhcc RPMH_CXO_CLK>; 4924 clock-names = "iface", 4925 "core", 4926 "xo"; 4927 4928 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 4929 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4930 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4931 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4932 interconnect-names = "sdhc-ddr", 4933 "cpu-sdhc"; 4934 4935 power-domains = <&rpmhpd RPMHPD_CX>; 4936 operating-points-v2 = <&sdhc2_opp_table>; 4937 4938 iommus = <&apps_smmu 0x540 0>; 4939 4940 bus-width = <4>; 4941 4942 /* Forbid SDR104/SDR50 - broken hw! */ 4943 sdhci-caps-mask = <0x3 0>; 4944 4945 qcom,dll-config = <0x0007642c>; 4946 qcom,ddr-config = <0x80040868>; 4947 4948 dma-coherent; 4949 4950 status = "disabled"; 4951 4952 sdhc2_opp_table: opp-table { 4953 compatible = "operating-points-v2"; 4954 4955 opp-19200000 { 4956 opp-hz = /bits/ 64 <19200000>; 4957 required-opps = <&rpmhpd_opp_min_svs>; 4958 }; 4959 4960 opp-50000000 { 4961 opp-hz = /bits/ 64 <50000000>; 4962 required-opps = <&rpmhpd_opp_low_svs>; 4963 }; 4964 4965 opp-100000000 { 4966 opp-hz = /bits/ 64 <100000000>; 4967 required-opps = <&rpmhpd_opp_svs>; 4968 }; 4969 4970 opp-202000000 { 4971 opp-hz = /bits/ 64 <202000000>; 4972 required-opps = <&rpmhpd_opp_svs_l1>; 4973 }; 4974 }; 4975 }; 4976 4977 usb_1_hsphy: phy@88e3000 { 4978 compatible = "qcom,sm8650-snps-eusb2-phy", 4979 "qcom,sm8550-snps-eusb2-phy"; 4980 reg = <0 0x088e3000 0 0x154>; 4981 4982 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 4983 clock-names = "ref"; 4984 4985 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4986 4987 #phy-cells = <0>; 4988 4989 status = "disabled"; 4990 }; 4991 4992 usb_dp_qmpphy: phy@88e8000 { 4993 compatible = "qcom,sm8650-qmp-usb3-dp-phy"; 4994 reg = <0 0x088e8000 0 0x3000>; 4995 4996 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4997 <&rpmhcc RPMH_CXO_CLK>, 4998 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4999 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 5000 clock-names = "aux", 5001 "ref", 5002 "com_aux", 5003 "usb3_pipe"; 5004 5005 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 5006 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 5007 reset-names = "phy", 5008 "common"; 5009 5010 power-domains = <&gcc USB3_PHY_GDSC>; 5011 5012 #clock-cells = <1>; 5013 #phy-cells = <1>; 5014 5015 mode-switch; 5016 orientation-switch; 5017 5018 status = "disabled"; 5019 5020 ports { 5021 #address-cells = <1>; 5022 #size-cells = <0>; 5023 5024 port@0 { 5025 reg = <0>; 5026 5027 usb_dp_qmpphy_out: endpoint { 5028 }; 5029 }; 5030 5031 port@1 { 5032 reg = <1>; 5033 5034 usb_dp_qmpphy_usb_ss_in: endpoint { 5035 remote-endpoint = <&usb_1_dwc3_ss>; 5036 }; 5037 }; 5038 5039 port@2 { 5040 reg = <2>; 5041 5042 usb_dp_qmpphy_dp_in: endpoint { 5043 remote-endpoint = <&mdss_dp0_out>; 5044 }; 5045 }; 5046 }; 5047 }; 5048 5049 usb_1: usb@a600000 { 5050 compatible = "qcom,sm8650-dwc3", "qcom,snps-dwc3"; 5051 reg = <0 0x0a600000 0 0xfc100>; 5052 5053 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, 5054 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, 5055 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, 5056 <&pdc 14 IRQ_TYPE_EDGE_RISING>, 5057 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 5058 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 5059 interrupt-names = "dwc_usb3", 5060 "pwr_event", 5061 "hs_phy_irq", 5062 "dp_hs_phy_irq", 5063 "dm_hs_phy_irq", 5064 "ss_phy_irq"; 5065 5066 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5067 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5068 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5069 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5070 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5071 <&tcsr TCSR_USB3_CLKREF_EN>; 5072 clock-names = "cfg_noc", 5073 "core", 5074 "iface", 5075 "sleep", 5076 "mock_utmi", 5077 "xo"; 5078 5079 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5080 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5081 assigned-clock-rates = <19200000>, <200000000>; 5082 5083 resets = <&gcc GCC_USB30_PRIM_BCR>; 5084 5085 phys = <&usb_1_hsphy>, 5086 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 5087 phy-names = "usb2-phy", 5088 "usb3-phy"; 5089 5090 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 5091 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5092 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5093 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 5094 interconnect-names = "usb-ddr", 5095 "apps-usb"; 5096 5097 iommus = <&apps_smmu 0x40 0>; 5098 5099 power-domains = <&gcc USB30_PRIM_GDSC>; 5100 required-opps = <&rpmhpd_opp_nom>; 5101 5102 snps,hird-threshold = /bits/ 8 <0x0>; 5103 snps,usb2-gadget-lpm-disable; 5104 snps,dis_u2_susphy_quirk; 5105 snps,dis_enblslpm_quirk; 5106 snps,dis-u1-entry-quirk; 5107 snps,dis-u2-entry-quirk; 5108 snps,is-utmi-l1-suspend; 5109 snps,usb3_lpm_capable; 5110 snps,usb2-lpm-disable; 5111 snps,has-lpm-erratum; 5112 tx-fifo-resize; 5113 5114 dma-coherent; 5115 5116 #address-cells = <1>; 5117 #size-cells = <0>; 5118 5119 status = "disabled"; 5120 5121 ports { 5122 #address-cells = <1>; 5123 #size-cells = <0>; 5124 5125 port@0 { 5126 reg = <0>; 5127 5128 usb_1_dwc3_hs: endpoint { 5129 }; 5130 }; 5131 5132 port@1 { 5133 reg = <1>; 5134 5135 usb_1_dwc3_ss: endpoint { 5136 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 5137 }; 5138 }; 5139 }; 5140 }; 5141 5142 iris: video-codec@aa00000 { 5143 compatible = "qcom,sm8650-iris"; 5144 reg = <0 0x0aa00000 0 0xf0000>; 5145 5146 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; 5147 5148 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 5149 <&videocc VIDEO_CC_MVS0_GDSC>, 5150 <&rpmhpd RPMHPD_MXC>, 5151 <&rpmhpd RPMHPD_MMCX>; 5152 power-domain-names = "venus", 5153 "vcodec0", 5154 "mxc", 5155 "mmcx"; 5156 5157 operating-points-v2 = <&iris_opp_table>; 5158 5159 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 5160 <&videocc VIDEO_CC_MVS0C_CLK>, 5161 <&videocc VIDEO_CC_MVS0_CLK>; 5162 clock-names = "iface", 5163 "core", 5164 "vcodec0_core"; 5165 5166 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5167 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5168 <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS 5169 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5170 interconnect-names = "cpu-cfg", 5171 "video-mem"; 5172 5173 memory-region = <&video_mem>; 5174 5175 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 5176 <&videocc VIDEO_CC_XO_CLK_ARES>, 5177 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 5178 reset-names = "bus", 5179 "xo", 5180 "core"; 5181 5182 iommus = <&apps_smmu 0x1940 0>, 5183 <&apps_smmu 0x1947 0>; 5184 5185 dma-coherent; 5186 5187 /* 5188 * IRIS firmware is signed by vendors, only 5189 * enable on boards where the proper signed firmware 5190 * is available. 5191 */ 5192 status = "disabled"; 5193 5194 iris_opp_table: opp-table { 5195 compatible = "operating-points-v2"; 5196 5197 opp-196000000 { 5198 opp-hz = /bits/ 64 <196000000>; 5199 required-opps = <&rpmhpd_opp_low_svs_d1>, 5200 <&rpmhpd_opp_low_svs_d1>; 5201 }; 5202 5203 opp-300000000 { 5204 opp-hz = /bits/ 64 <300000000>; 5205 required-opps = <&rpmhpd_opp_low_svs>, 5206 <&rpmhpd_opp_low_svs>; 5207 }; 5208 5209 opp-380000000 { 5210 opp-hz = /bits/ 64 <380000000>; 5211 required-opps = <&rpmhpd_opp_svs>, 5212 <&rpmhpd_opp_svs>; 5213 }; 5214 5215 opp-435000000 { 5216 opp-hz = /bits/ 64 <435000000>; 5217 required-opps = <&rpmhpd_opp_svs_l1>, 5218 <&rpmhpd_opp_svs_l1>; 5219 }; 5220 5221 opp-480000000 { 5222 opp-hz = /bits/ 64 <480000000>; 5223 required-opps = <&rpmhpd_opp_nom>, 5224 <&rpmhpd_opp_nom>; 5225 }; 5226 5227 opp-533333334 { 5228 opp-hz = /bits/ 64 <533333334>; 5229 required-opps = <&rpmhpd_opp_turbo>, 5230 <&rpmhpd_opp_turbo>; 5231 }; 5232 }; 5233 }; 5234 5235 videocc: clock-controller@aaf0000 { 5236 compatible = "qcom,sm8650-videocc"; 5237 reg = <0 0x0aaf0000 0 0x10000>; 5238 clocks = <&bi_tcxo_div2>, 5239 <&gcc GCC_VIDEO_AHB_CLK>; 5240 power-domains = <&rpmhpd RPMHPD_MMCX>, 5241 <&rpmhpd RPMHPD_MXC>; 5242 #clock-cells = <1>; 5243 #reset-cells = <1>; 5244 #power-domain-cells = <1>; 5245 }; 5246 5247 cci0: cci@ac15000 { 5248 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 5249 reg = <0 0x0ac15000 0 0x1000>; 5250 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>; 5251 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5252 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 5253 <&camcc CAM_CC_CPAS_AHB_CLK>, 5254 <&camcc CAM_CC_CCI_0_CLK>; 5255 clock-names = "camnoc_axi", 5256 "cpas_ahb", 5257 "cci"; 5258 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 5259 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 5260 pinctrl-names = "default", "sleep"; 5261 status = "disabled"; 5262 #address-cells = <1>; 5263 #size-cells = <0>; 5264 5265 cci0_i2c0: i2c-bus@0 { 5266 reg = <0>; 5267 clock-frequency = <1000000>; 5268 #address-cells = <1>; 5269 #size-cells = <0>; 5270 }; 5271 5272 cci0_i2c1: i2c-bus@1 { 5273 reg = <1>; 5274 clock-frequency = <1000000>; 5275 #address-cells = <1>; 5276 #size-cells = <0>; 5277 }; 5278 }; 5279 5280 cci1: cci@ac16000 { 5281 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 5282 reg = <0 0x0ac16000 0 0x1000>; 5283 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING 0>; 5284 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5285 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 5286 <&camcc CAM_CC_CPAS_AHB_CLK>, 5287 <&camcc CAM_CC_CCI_1_CLK>; 5288 clock-names = "camnoc_axi", 5289 "cpas_ahb", 5290 "cci"; 5291 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 5292 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 5293 pinctrl-names = "default", "sleep"; 5294 status = "disabled"; 5295 #address-cells = <1>; 5296 #size-cells = <0>; 5297 5298 cci1_i2c0: i2c-bus@0 { 5299 reg = <0>; 5300 clock-frequency = <1000000>; 5301 #address-cells = <1>; 5302 #size-cells = <0>; 5303 }; 5304 5305 cci1_i2c1: i2c-bus@1 { 5306 reg = <1>; 5307 clock-frequency = <1000000>; 5308 #address-cells = <1>; 5309 #size-cells = <0>; 5310 }; 5311 }; 5312 5313 cci2: cci@ac17000 { 5314 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 5315 reg = <0 0x0ac17000 0 0x1000>; 5316 interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING 0>; 5317 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5318 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 5319 <&camcc CAM_CC_CPAS_AHB_CLK>, 5320 <&camcc CAM_CC_CCI_2_CLK>; 5321 clock-names = "camnoc_axi", 5322 "cpas_ahb", 5323 "cci"; 5324 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 5325 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 5326 pinctrl-names = "default", "sleep"; 5327 status = "disabled"; 5328 #address-cells = <1>; 5329 #size-cells = <0>; 5330 5331 cci2_i2c0: i2c-bus@0 { 5332 reg = <0>; 5333 clock-frequency = <1000000>; 5334 #address-cells = <1>; 5335 #size-cells = <0>; 5336 }; 5337 5338 cci2_i2c1: i2c-bus@1 { 5339 reg = <1>; 5340 clock-frequency = <1000000>; 5341 #address-cells = <1>; 5342 #size-cells = <0>; 5343 }; 5344 }; 5345 5346 camcc: clock-controller@ade0000 { 5347 compatible = "qcom,sm8650-camcc"; 5348 reg = <0 0x0ade0000 0 0x20000>; 5349 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 5350 <&bi_tcxo_div2>, 5351 <&bi_tcxo_ao_div2>, 5352 <&sleep_clk>; 5353 power-domains = <&rpmhpd RPMHPD_MMCX>, 5354 <&rpmhpd RPMHPD_MXC>; 5355 #clock-cells = <1>; 5356 #reset-cells = <1>; 5357 #power-domain-cells = <1>; 5358 }; 5359 5360 mdss: display-subsystem@ae00000 { 5361 compatible = "qcom,sm8650-mdss"; 5362 reg = <0 0x0ae00000 0 0x1000>; 5363 reg-names = "mdss"; 5364 5365 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>; 5366 5367 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5368 <&gcc GCC_DISP_HF_AXI_CLK>, 5369 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5370 5371 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5372 5373 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 5374 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5375 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5376 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5377 interconnect-names = "mdp0-mem", 5378 "cpu-cfg"; 5379 5380 power-domains = <&dispcc MDSS_GDSC>; 5381 5382 iommus = <&apps_smmu 0x1c00 0x2>; 5383 5384 interrupt-controller; 5385 #interrupt-cells = <1>; 5386 5387 #address-cells = <2>; 5388 #size-cells = <2>; 5389 ranges; 5390 5391 status = "disabled"; 5392 5393 mdss_mdp: display-controller@ae01000 { 5394 compatible = "qcom,sm8650-dpu"; 5395 reg = <0 0x0ae01000 0 0x8f000>, 5396 <0 0x0aeb0000 0 0x3000>; 5397 reg-names = "mdp", 5398 "vbif"; 5399 5400 interrupts-extended = <&mdss 0>; 5401 5402 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5403 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5404 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5405 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5406 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5407 clock-names = "nrt_bus", 5408 "iface", 5409 "lut", 5410 "core", 5411 "vsync"; 5412 5413 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5414 assigned-clock-rates = <19200000>; 5415 5416 operating-points-v2 = <&mdp_opp_table>; 5417 5418 power-domains = <&rpmhpd RPMHPD_MMCX>; 5419 5420 ports { 5421 #address-cells = <1>; 5422 #size-cells = <0>; 5423 5424 port@0 { 5425 reg = <0>; 5426 5427 dpu_intf1_out: endpoint { 5428 remote-endpoint = <&mdss_dsi0_in>; 5429 }; 5430 }; 5431 5432 port@1 { 5433 reg = <1>; 5434 5435 dpu_intf2_out: endpoint { 5436 remote-endpoint = <&mdss_dsi1_in>; 5437 }; 5438 }; 5439 5440 port@2 { 5441 reg = <2>; 5442 5443 dpu_intf0_out: endpoint { 5444 remote-endpoint = <&mdss_dp0_in>; 5445 }; 5446 }; 5447 }; 5448 5449 mdp_opp_table: opp-table { 5450 compatible = "operating-points-v2"; 5451 5452 opp-200000000 { 5453 opp-hz = /bits/ 64 <200000000>; 5454 required-opps = <&rpmhpd_opp_low_svs>; 5455 }; 5456 5457 opp-325000000 { 5458 opp-hz = /bits/ 64 <325000000>; 5459 required-opps = <&rpmhpd_opp_svs>; 5460 }; 5461 5462 opp-375000000 { 5463 opp-hz = /bits/ 64 <375000000>; 5464 required-opps = <&rpmhpd_opp_svs_l1>; 5465 }; 5466 5467 opp-514000000 { 5468 opp-hz = /bits/ 64 <514000000>; 5469 required-opps = <&rpmhpd_opp_nom>; 5470 }; 5471 }; 5472 }; 5473 5474 mdss_dsi0: dsi@ae94000 { 5475 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5476 reg = <0 0x0ae94000 0 0x400>; 5477 reg-names = "dsi_ctrl"; 5478 5479 interrupts-extended = <&mdss 4>; 5480 5481 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 5482 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 5483 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 5484 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 5485 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5486 <&gcc GCC_DISP_HF_AXI_CLK>; 5487 clock-names = "byte", 5488 "byte_intf", 5489 "pixel", 5490 "core", 5491 "iface", 5492 "bus"; 5493 5494 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 5495 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 5496 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5497 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 5498 5499 operating-points-v2 = <&mdss_dsi_opp_table>; 5500 5501 power-domains = <&rpmhpd RPMHPD_MMCX>; 5502 5503 phys = <&mdss_dsi0_phy>; 5504 phy-names = "dsi"; 5505 5506 #address-cells = <1>; 5507 #size-cells = <0>; 5508 5509 status = "disabled"; 5510 5511 ports { 5512 #address-cells = <1>; 5513 #size-cells = <0>; 5514 5515 port@0 { 5516 reg = <0>; 5517 5518 mdss_dsi0_in: endpoint { 5519 remote-endpoint = <&dpu_intf1_out>; 5520 }; 5521 }; 5522 5523 port@1 { 5524 reg = <1>; 5525 5526 mdss_dsi0_out: endpoint { 5527 }; 5528 }; 5529 }; 5530 5531 mdss_dsi_opp_table: opp-table { 5532 compatible = "operating-points-v2"; 5533 5534 opp-187500000 { 5535 opp-hz = /bits/ 64 <187500000>; 5536 required-opps = <&rpmhpd_opp_low_svs>; 5537 }; 5538 5539 opp-300000000 { 5540 opp-hz = /bits/ 64 <300000000>; 5541 required-opps = <&rpmhpd_opp_svs>; 5542 }; 5543 5544 opp-358000000 { 5545 opp-hz = /bits/ 64 <358000000>; 5546 required-opps = <&rpmhpd_opp_svs_l1>; 5547 }; 5548 }; 5549 }; 5550 5551 mdss_dsi0_phy: phy@ae95000 { 5552 compatible = "qcom,sm8650-dsi-phy-4nm"; 5553 reg = <0 0x0ae95000 0 0x200>, 5554 <0 0x0ae95200 0 0x280>, 5555 <0 0x0ae95500 0 0x400>; 5556 reg-names = "dsi_phy", 5557 "dsi_phy_lane", 5558 "dsi_pll"; 5559 5560 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5561 <&rpmhcc RPMH_CXO_CLK>; 5562 clock-names = "iface", 5563 "ref"; 5564 5565 #clock-cells = <1>; 5566 #phy-cells = <0>; 5567 5568 status = "disabled"; 5569 }; 5570 5571 mdss_dsi1: dsi@ae96000 { 5572 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5573 reg = <0 0x0ae96000 0 0x400>; 5574 reg-names = "dsi_ctrl"; 5575 5576 interrupts-extended = <&mdss 5>; 5577 5578 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 5579 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 5580 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 5581 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 5582 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5583 <&gcc GCC_DISP_HF_AXI_CLK>; 5584 clock-names = "byte", 5585 "byte_intf", 5586 "pixel", 5587 "core", 5588 "iface", 5589 "bus"; 5590 5591 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 5592 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 5593 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 5594 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 5595 5596 operating-points-v2 = <&mdss_dsi_opp_table>; 5597 5598 power-domains = <&rpmhpd RPMHPD_MMCX>; 5599 5600 phys = <&mdss_dsi1_phy>; 5601 phy-names = "dsi"; 5602 5603 #address-cells = <1>; 5604 #size-cells = <0>; 5605 5606 status = "disabled"; 5607 5608 ports { 5609 #address-cells = <1>; 5610 #size-cells = <0>; 5611 5612 port@0 { 5613 reg = <0>; 5614 5615 mdss_dsi1_in: endpoint { 5616 remote-endpoint = <&dpu_intf2_out>; 5617 }; 5618 }; 5619 5620 port@1 { 5621 reg = <1>; 5622 5623 mdss_dsi1_out: endpoint { 5624 }; 5625 }; 5626 }; 5627 }; 5628 5629 mdss_dsi1_phy: phy@ae97000 { 5630 compatible = "qcom,sm8650-dsi-phy-4nm"; 5631 reg = <0 0x0ae97000 0 0x200>, 5632 <0 0x0ae97200 0 0x280>, 5633 <0 0x0ae97500 0 0x400>; 5634 reg-names = "dsi_phy", 5635 "dsi_phy_lane", 5636 "dsi_pll"; 5637 5638 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5639 <&rpmhcc RPMH_CXO_CLK>; 5640 clock-names = "iface", 5641 "ref"; 5642 5643 #clock-cells = <1>; 5644 #phy-cells = <0>; 5645 5646 status = "disabled"; 5647 }; 5648 5649 mdss_dp0: displayport-controller@af54000 { 5650 compatible = "qcom,sm8650-dp"; 5651 reg = <0 0xaf54000 0 0x104>, 5652 <0 0xaf54200 0 0xc0>, 5653 <0 0xaf55000 0 0x770>, 5654 <0 0xaf56000 0 0x9c>, 5655 <0 0xaf57000 0 0x9c>; 5656 5657 interrupts-extended = <&mdss 12>; 5658 5659 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5660 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 5661 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 5662 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5663 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5664 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 5665 clock-names = "core_iface", 5666 "core_aux", 5667 "ctrl_link", 5668 "ctrl_link_iface", 5669 "stream_pixel", 5670 "stream_1_pixel"; 5671 5672 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5673 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5674 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 5675 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5676 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5677 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5678 5679 operating-points-v2 = <&dp_opp_table>; 5680 5681 power-domains = <&rpmhpd RPMHPD_MMCX>; 5682 5683 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 5684 phy-names = "dp"; 5685 5686 #sound-dai-cells = <0>; 5687 5688 status = "disabled"; 5689 5690 dp_opp_table: opp-table { 5691 compatible = "operating-points-v2"; 5692 5693 opp-162000000 { 5694 opp-hz = /bits/ 64 <162000000>; 5695 required-opps = <&rpmhpd_opp_low_svs_d1>; 5696 }; 5697 5698 opp-270000000 { 5699 opp-hz = /bits/ 64 <270000000>; 5700 required-opps = <&rpmhpd_opp_low_svs>; 5701 }; 5702 5703 opp-540000000 { 5704 opp-hz = /bits/ 64 <540000000>; 5705 required-opps = <&rpmhpd_opp_svs_l1>; 5706 }; 5707 5708 opp-810000000 { 5709 opp-hz = /bits/ 64 <810000000>; 5710 required-opps = <&rpmhpd_opp_nom>; 5711 }; 5712 }; 5713 5714 ports { 5715 #address-cells = <1>; 5716 #size-cells = <0>; 5717 5718 port@0 { 5719 reg = <0>; 5720 5721 mdss_dp0_in: endpoint { 5722 remote-endpoint = <&dpu_intf0_out>; 5723 }; 5724 }; 5725 5726 port@1 { 5727 reg = <1>; 5728 5729 mdss_dp0_out: endpoint { 5730 data-lanes = <0 1 2 3>; 5731 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 5732 }; 5733 }; 5734 }; 5735 }; 5736 }; 5737 5738 dispcc: clock-controller@af00000 { 5739 compatible = "qcom,sm8650-dispcc"; 5740 reg = <0 0x0af00000 0 0x20000>; 5741 5742 clocks = <&bi_tcxo_div2>, 5743 <&bi_tcxo_ao_div2>, 5744 <&gcc GCC_DISP_AHB_CLK>, 5745 <&sleep_clk>, 5746 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5747 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 5748 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 5749 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 5750 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5751 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5752 <0>, /* dp1 */ 5753 <0>, 5754 <0>, /* dp2 */ 5755 <0>, 5756 <0>, /* dp3 */ 5757 <0>; 5758 5759 power-domains = <&rpmhpd RPMHPD_MMCX>; 5760 required-opps = <&rpmhpd_opp_low_svs>; 5761 5762 #clock-cells = <1>; 5763 #reset-cells = <1>; 5764 #power-domain-cells = <1>; 5765 }; 5766 5767 pdc: interrupt-controller@b220000 { 5768 compatible = "qcom,sm8650-pdc", "qcom,pdc"; 5769 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 5770 5771 interrupt-parent = <&intc>; 5772 5773 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 5774 <125 63 1>, <126 716 12>, 5775 <138 251 5>, <143 244 4>; 5776 5777 #interrupt-cells = <2>; 5778 interrupt-controller; 5779 }; 5780 5781 tsens0: thermal-sensor@c228000 { 5782 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 5783 reg = <0 0x0c228000 0 0x1000>, /* TM */ 5784 <0 0x0c222000 0 0x1000>; /* SROT */ 5785 5786 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>, 5787 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 5788 interrupt-names = "uplow", 5789 "critical"; 5790 5791 #qcom,sensors = <15>; 5792 5793 #thermal-sensor-cells = <1>; 5794 }; 5795 5796 tsens1: thermal-sensor@c229000 { 5797 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 5798 reg = <0 0x0c229000 0 0x1000>, /* TM */ 5799 <0 0x0c223000 0 0x1000>; /* SROT */ 5800 5801 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>, 5802 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 5803 interrupt-names = "uplow", 5804 "critical"; 5805 5806 #qcom,sensors = <16>; 5807 5808 #thermal-sensor-cells = <1>; 5809 }; 5810 5811 tsens2: thermal-sensor@c22a000 { 5812 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 5813 reg = <0 0x0c22a000 0 0x1000>, /* TM */ 5814 <0 0x0c224000 0 0x1000>; /* SROT */ 5815 5816 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>, 5817 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 5818 interrupt-names = "uplow", 5819 "critical"; 5820 5821 #qcom,sensors = <13>; 5822 5823 #thermal-sensor-cells = <1>; 5824 }; 5825 5826 aoss_qmp: power-management@c300000 { 5827 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; 5828 reg = <0 0x0c300000 0 0x400>; 5829 5830 interrupt-parent = <&ipcc>; 5831 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 5832 IRQ_TYPE_EDGE_RISING>; 5833 5834 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5835 5836 #clock-cells = <0>; 5837 }; 5838 5839 sram@c3f0000 { 5840 compatible = "qcom,rpmh-stats"; 5841 reg = <0 0x0c3f0000 0 0x400>; 5842 qcom,qmp = <&aoss_qmp>; 5843 }; 5844 5845 spmi_bus: spmi@c400000 { 5846 compatible = "qcom,spmi-pmic-arb"; 5847 reg = <0 0x0c400000 0 0x3000>, 5848 <0 0x0c500000 0 0x400000>, 5849 <0 0x0c440000 0 0x80000>, 5850 <0 0x0c4c0000 0 0x20000>, 5851 <0 0x0c42d000 0 0x4000>; 5852 reg-names = "core", 5853 "chnls", 5854 "obsrvr", 5855 "intr", 5856 "cnfg"; 5857 5858 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5859 interrupt-names = "periph_irq"; 5860 5861 qcom,ee = <0>; 5862 qcom,channel = <0>; 5863 qcom,bus-id = <0>; 5864 5865 interrupt-controller; 5866 #interrupt-cells = <4>; 5867 5868 #address-cells = <2>; 5869 #size-cells = <0>; 5870 }; 5871 5872 tlmm: pinctrl@f100000 { 5873 compatible = "qcom,sm8650-tlmm"; 5874 reg = <0 0x0f100000 0 0x300000>; 5875 5876 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; 5877 5878 gpio-controller; 5879 #gpio-cells = <2>; 5880 5881 interrupt-controller; 5882 #interrupt-cells = <2>; 5883 5884 gpio-ranges = <&tlmm 0 0 211>; 5885 5886 wakeup-parent = <&pdc>; 5887 5888 cci0_0_default: cci0-0-default-state { 5889 sda-pins { 5890 pins = "gpio113"; 5891 function = "cci_i2c_sda"; 5892 drive-strength = <2>; 5893 bias-pull-up = <2200>; 5894 }; 5895 5896 scl-pins { 5897 pins = "gpio114"; 5898 function = "cci_i2c_scl"; 5899 drive-strength = <2>; 5900 bias-pull-up = <2200>; 5901 }; 5902 }; 5903 5904 cci0_0_sleep: cci0-0-sleep-state { 5905 sda-pins { 5906 pins = "gpio113"; 5907 function = "cci_i2c_sda"; 5908 drive-strength = <2>; 5909 bias-pull-down; 5910 }; 5911 5912 scl-pins { 5913 pins = "gpio114"; 5914 function = "cci_i2c_scl"; 5915 drive-strength = <2>; 5916 bias-pull-down; 5917 }; 5918 }; 5919 5920 cci0_1_default: cci0-1-default-state { 5921 sda-pins { 5922 pins = "gpio115"; 5923 function = "cci_i2c_sda"; 5924 drive-strength = <2>; 5925 bias-pull-up = <2200>; 5926 }; 5927 5928 scl-pins { 5929 pins = "gpio116"; 5930 function = "cci_i2c_scl"; 5931 drive-strength = <2>; 5932 bias-pull-up = <2200>; 5933 }; 5934 }; 5935 5936 cci0_1_sleep: cci0-1-sleep-state { 5937 sda-pins { 5938 pins = "gpio115"; 5939 function = "cci_i2c_sda"; 5940 drive-strength = <2>; 5941 bias-pull-down; 5942 }; 5943 5944 scl-pins { 5945 pins = "gpio116"; 5946 function = "cci_i2c_scl"; 5947 drive-strength = <2>; 5948 bias-pull-down; 5949 }; 5950 }; 5951 5952 cci1_0_default: cci1-0-default-state { 5953 sda-pins { 5954 pins = "gpio117"; 5955 function = "cci_i2c_sda"; 5956 drive-strength = <2>; 5957 bias-pull-up = <2200>; 5958 }; 5959 5960 scl-pins { 5961 pins = "gpio118"; 5962 function = "cci_i2c_scl"; 5963 drive-strength = <2>; 5964 bias-pull-up = <2200>; 5965 }; 5966 }; 5967 5968 cci1_0_sleep: cci1-0-sleep-state { 5969 sda-pins { 5970 pins = "gpio117"; 5971 function = "cci_i2c_sda"; 5972 drive-strength = <2>; 5973 bias-pull-down; 5974 }; 5975 5976 scl-pins { 5977 pins = "gpio118"; 5978 function = "cci_i2c_scl"; 5979 drive-strength = <2>; 5980 bias-pull-down; 5981 }; 5982 }; 5983 5984 cci1_1_default: cci1-1-default-state { 5985 sda-pins { 5986 pins = "gpio12"; 5987 function = "cci_i2c_sda"; 5988 drive-strength = <2>; 5989 bias-pull-up = <2200>; 5990 }; 5991 5992 scl-pins { 5993 pins = "gpio13"; 5994 function = "cci_i2c_scl"; 5995 drive-strength = <2>; 5996 bias-pull-up = <2200>; 5997 }; 5998 }; 5999 6000 cci1_1_sleep: cci1-1-sleep-state { 6001 sda-pins { 6002 pins = "gpio12"; 6003 function = "cci_i2c_sda"; 6004 drive-strength = <2>; 6005 bias-pull-down; 6006 }; 6007 6008 scl-pins { 6009 pins = "gpio13"; 6010 function = "cci_i2c_scl"; 6011 drive-strength = <2>; 6012 bias-pull-down; 6013 }; 6014 }; 6015 6016 cci2_0_default: cci2-0-default-state { 6017 sda-pins { 6018 pins = "gpio112"; 6019 function = "cci_i2c_sda"; 6020 drive-strength = <2>; 6021 bias-pull-up = <2200>; 6022 }; 6023 6024 scl-pins { 6025 pins = "gpio153"; 6026 function = "cci_i2c_scl"; 6027 drive-strength = <2>; 6028 bias-pull-up = <2200>; 6029 }; 6030 }; 6031 6032 cci2_0_sleep: cci2-0-sleep-state { 6033 sda-pins { 6034 pins = "gpio112"; 6035 function = "cci_i2c_sda"; 6036 drive-strength = <2>; 6037 bias-pull-down; 6038 }; 6039 6040 scl-pins { 6041 pins = "gpio153"; 6042 function = "cci_i2c_scl"; 6043 drive-strength = <2>; 6044 bias-pull-down; 6045 }; 6046 }; 6047 6048 cci2_1_default: cci2-1-default-state { 6049 sda-pins { 6050 pins = "gpio119"; 6051 function = "cci_i2c_sda"; 6052 drive-strength = <2>; 6053 bias-pull-up = <2200>; 6054 }; 6055 6056 scl-pins { 6057 pins = "gpio120"; 6058 function = "cci_i2c_scl"; 6059 drive-strength = <2>; 6060 bias-pull-up = <2200>; 6061 }; 6062 }; 6063 6064 cci2_1_sleep: cci2-1-sleep-state { 6065 sda-pins { 6066 pins = "gpio119"; 6067 function = "cci_i2c_sda"; 6068 drive-strength = <2>; 6069 bias-pull-down; 6070 }; 6071 6072 scl-pins { 6073 pins = "gpio120"; 6074 function = "cci_i2c_scl"; 6075 drive-strength = <2>; 6076 bias-pull-down; 6077 }; 6078 }; 6079 6080 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 6081 /* SDA, SCL */ 6082 pins = "gpio64", "gpio65"; 6083 function = "i2chub0_se0"; 6084 drive-strength = <2>; 6085 bias-pull-up; 6086 }; 6087 6088 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 6089 /* SDA, SCL */ 6090 pins = "gpio66", "gpio67"; 6091 function = "i2chub0_se1"; 6092 drive-strength = <2>; 6093 bias-pull-up; 6094 }; 6095 6096 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 6097 /* SDA, SCL */ 6098 pins = "gpio68", "gpio69"; 6099 function = "i2chub0_se2"; 6100 drive-strength = <2>; 6101 bias-pull-up; 6102 }; 6103 6104 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 6105 /* SDA, SCL */ 6106 pins = "gpio70", "gpio71"; 6107 function = "i2chub0_se3"; 6108 drive-strength = <2>; 6109 bias-pull-up; 6110 }; 6111 6112 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 6113 /* SDA, SCL */ 6114 pins = "gpio72", "gpio73"; 6115 function = "i2chub0_se4"; 6116 drive-strength = <2>; 6117 bias-pull-up; 6118 }; 6119 6120 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 6121 /* SDA, SCL */ 6122 pins = "gpio74", "gpio75"; 6123 function = "i2chub0_se5"; 6124 drive-strength = <2>; 6125 bias-pull-up; 6126 }; 6127 6128 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 6129 /* SDA, SCL */ 6130 pins = "gpio76", "gpio77"; 6131 function = "i2chub0_se6"; 6132 drive-strength = <2>; 6133 bias-pull-up; 6134 }; 6135 6136 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 6137 /* SDA, SCL */ 6138 pins = "gpio78", "gpio79"; 6139 function = "i2chub0_se7"; 6140 drive-strength = <2>; 6141 bias-pull-up; 6142 }; 6143 6144 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 6145 /* SDA, SCL */ 6146 pins = "gpio206", "gpio207"; 6147 function = "i2chub0_se8"; 6148 drive-strength = <2>; 6149 bias-pull-up; 6150 }; 6151 6152 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 6153 /* SDA, SCL */ 6154 pins = "gpio80", "gpio81"; 6155 function = "i2chub0_se9"; 6156 drive-strength = <2>; 6157 bias-pull-up; 6158 }; 6159 6160 pcie0_default_state: pcie0-default-state { 6161 perst-pins { 6162 pins = "gpio94"; 6163 function = "gpio"; 6164 drive-strength = <2>; 6165 bias-pull-down; 6166 }; 6167 6168 clkreq-pins { 6169 pins = "gpio95"; 6170 function = "pcie0_clk_req_n"; 6171 drive-strength = <2>; 6172 bias-pull-up; 6173 }; 6174 6175 wake-pins { 6176 pins = "gpio96"; 6177 function = "gpio"; 6178 drive-strength = <2>; 6179 bias-pull-up; 6180 }; 6181 }; 6182 6183 pcie1_default_state: pcie1-default-state { 6184 perst-pins { 6185 pins = "gpio97"; 6186 function = "gpio"; 6187 drive-strength = <2>; 6188 bias-pull-down; 6189 }; 6190 6191 clkreq-pins { 6192 pins = "gpio98"; 6193 function = "pcie1_clk_req_n"; 6194 drive-strength = <2>; 6195 bias-pull-up; 6196 }; 6197 6198 wake-pins { 6199 pins = "gpio99"; 6200 function = "gpio"; 6201 drive-strength = <2>; 6202 bias-pull-up; 6203 }; 6204 }; 6205 6206 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 6207 /* SDA, SCL */ 6208 pins = "gpio32", "gpio33"; 6209 function = "qup1_se0"; 6210 drive-strength = <2>; 6211 bias-pull-up; 6212 }; 6213 6214 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 6215 /* SDA, SCL */ 6216 pins = "gpio36", "gpio37"; 6217 function = "qup1_se1"; 6218 drive-strength = <2>; 6219 bias-pull-up; 6220 }; 6221 6222 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 6223 /* SDA, SCL */ 6224 pins = "gpio40", "gpio41"; 6225 function = "qup1_se2"; 6226 drive-strength = <2>; 6227 bias-pull-up; 6228 }; 6229 6230 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 6231 /* SDA, SCL */ 6232 pins = "gpio44", "gpio45"; 6233 function = "qup1_se3"; 6234 drive-strength = <2>; 6235 bias-pull-up; 6236 }; 6237 6238 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 6239 /* SDA, SCL */ 6240 pins = "gpio48", "gpio49"; 6241 function = "qup1_se4"; 6242 drive-strength = <2>; 6243 bias-pull-up; 6244 }; 6245 6246 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 6247 /* SDA, SCL */ 6248 pins = "gpio52", "gpio53"; 6249 function = "qup1_se5"; 6250 drive-strength = <2>; 6251 bias-pull-up; 6252 }; 6253 6254 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 6255 /* SDA, SCL */ 6256 pins = "gpio56", "gpio57"; 6257 function = "qup1_se6"; 6258 drive-strength = <2>; 6259 bias-pull-up; 6260 }; 6261 6262 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 6263 /* SDA, SCL */ 6264 pins = "gpio60", "gpio61"; 6265 function = "qup1_se7"; 6266 drive-strength = <2>; 6267 bias-pull-up; 6268 }; 6269 6270 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 6271 /* SDA, SCL */ 6272 pins = "gpio0", "gpio1"; 6273 function = "qup2_se0"; 6274 drive-strength = <2>; 6275 bias-pull-up; 6276 }; 6277 6278 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 6279 /* SDA, SCL */ 6280 pins = "gpio4", "gpio5"; 6281 function = "qup2_se1"; 6282 drive-strength = <2>; 6283 bias-pull-up; 6284 }; 6285 6286 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 6287 /* SDA, SCL */ 6288 pins = "gpio8", "gpio9"; 6289 function = "qup2_se2"; 6290 drive-strength = <2>; 6291 bias-pull-up; 6292 }; 6293 6294 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 6295 /* SDA, SCL */ 6296 pins = "gpio12", "gpio13"; 6297 function = "qup2_se3"; 6298 drive-strength = <2>; 6299 bias-pull-up; 6300 }; 6301 6302 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 6303 /* SDA, SCL */ 6304 pins = "gpio16", "gpio17"; 6305 function = "qup2_se4"; 6306 drive-strength = <2>; 6307 bias-pull-up; 6308 }; 6309 6310 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 6311 /* SDA, SCL */ 6312 pins = "gpio20", "gpio21"; 6313 function = "qup2_se5"; 6314 drive-strength = <2>; 6315 bias-pull-up; 6316 }; 6317 6318 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 6319 /* SDA, SCL */ 6320 pins = "gpio24", "gpio25"; 6321 function = "qup2_se6"; 6322 drive-strength = <2>; 6323 bias-pull-up; 6324 }; 6325 6326 qup_spi0_cs: qup-spi0-cs-state { 6327 pins = "gpio35"; 6328 function = "qup1_se0"; 6329 drive-strength = <6>; 6330 bias-disable; 6331 }; 6332 6333 qup_spi0_data_clk: qup-spi0-data-clk-state { 6334 /* MISO, MOSI, CLK */ 6335 pins = "gpio32", "gpio33", "gpio34"; 6336 function = "qup1_se0"; 6337 drive-strength = <6>; 6338 bias-disable; 6339 }; 6340 6341 qup_spi1_cs: qup-spi1-cs-state { 6342 pins = "gpio39"; 6343 function = "qup1_se1"; 6344 drive-strength = <6>; 6345 bias-disable; 6346 }; 6347 6348 qup_spi1_data_clk: qup-spi1-data-clk-state { 6349 /* MISO, MOSI, CLK */ 6350 pins = "gpio36", "gpio37", "gpio38"; 6351 function = "qup1_se1"; 6352 drive-strength = <6>; 6353 bias-disable; 6354 }; 6355 6356 qup_spi2_cs: qup-spi2-cs-state { 6357 pins = "gpio43"; 6358 function = "qup1_se2"; 6359 drive-strength = <6>; 6360 bias-disable; 6361 }; 6362 6363 qup_spi2_data_clk: qup-spi2-data-clk-state { 6364 /* MISO, MOSI, CLK */ 6365 pins = "gpio40", "gpio41", "gpio42"; 6366 function = "qup1_se2"; 6367 drive-strength = <6>; 6368 bias-disable; 6369 }; 6370 6371 qup_spi3_cs: qup-spi3-cs-state { 6372 pins = "gpio47"; 6373 function = "qup1_se3"; 6374 drive-strength = <6>; 6375 bias-disable; 6376 }; 6377 6378 qup_spi3_data_clk: qup-spi3-data-clk-state { 6379 /* MISO, MOSI, CLK */ 6380 pins = "gpio44", "gpio45", "gpio46"; 6381 function = "qup1_se3"; 6382 drive-strength = <6>; 6383 bias-disable; 6384 }; 6385 6386 qup_spi4_cs: qup-spi4-cs-state { 6387 pins = "gpio51"; 6388 function = "qup1_se4"; 6389 drive-strength = <6>; 6390 bias-disable; 6391 }; 6392 6393 qup_spi4_data_clk: qup-spi4-data-clk-state { 6394 /* MISO, MOSI, CLK */ 6395 pins = "gpio48", "gpio49", "gpio50"; 6396 function = "qup1_se4"; 6397 drive-strength = <6>; 6398 bias-disable; 6399 }; 6400 6401 qup_spi5_cs: qup-spi5-cs-state { 6402 pins = "gpio55"; 6403 function = "qup1_se5"; 6404 drive-strength = <6>; 6405 bias-disable; 6406 }; 6407 6408 qup_spi5_data_clk: qup-spi5-data-clk-state { 6409 /* MISO, MOSI, CLK */ 6410 pins = "gpio52", "gpio53", "gpio54"; 6411 function = "qup1_se5"; 6412 drive-strength = <6>; 6413 bias-disable; 6414 }; 6415 6416 qup_spi6_cs: qup-spi6-cs-state { 6417 pins = "gpio59"; 6418 function = "qup1_se6"; 6419 drive-strength = <6>; 6420 bias-disable; 6421 }; 6422 6423 qup_spi6_data_clk: qup-spi6-data-clk-state { 6424 /* MISO, MOSI, CLK */ 6425 pins = "gpio56", "gpio57", "gpio58"; 6426 function = "qup1_se6"; 6427 drive-strength = <6>; 6428 bias-disable; 6429 }; 6430 6431 qup_spi7_cs: qup-spi7-cs-state { 6432 pins = "gpio63"; 6433 function = "qup1_se7"; 6434 drive-strength = <6>; 6435 bias-disable; 6436 }; 6437 6438 qup_spi7_data_clk: qup-spi7-data-clk-state { 6439 /* MISO, MOSI, CLK */ 6440 pins = "gpio60", "gpio61", "gpio62"; 6441 function = "qup1_se7"; 6442 drive-strength = <6>; 6443 bias-disable; 6444 }; 6445 6446 qup_spi8_cs: qup-spi8-cs-state { 6447 pins = "gpio3"; 6448 function = "qup2_se0"; 6449 drive-strength = <6>; 6450 bias-disable; 6451 }; 6452 6453 qup_spi8_data_clk: qup-spi8-data-clk-state { 6454 /* MISO, MOSI, CLK */ 6455 pins = "gpio0", "gpio1", "gpio2"; 6456 function = "qup2_se0"; 6457 drive-strength = <6>; 6458 bias-disable; 6459 }; 6460 6461 qup_spi9_cs: qup-spi9-cs-state { 6462 pins = "gpio7"; 6463 function = "qup2_se1"; 6464 drive-strength = <6>; 6465 bias-disable; 6466 }; 6467 6468 qup_spi9_data_clk: qup-spi9-data-clk-state { 6469 /* MISO, MOSI, CLK */ 6470 pins = "gpio4", "gpio5", "gpio6"; 6471 function = "qup2_se1"; 6472 drive-strength = <6>; 6473 bias-disable; 6474 }; 6475 6476 qup_spi10_cs: qup-spi10-cs-state { 6477 pins = "gpio11"; 6478 function = "qup2_se2"; 6479 drive-strength = <6>; 6480 bias-disable; 6481 }; 6482 6483 qup_spi10_data_clk: qup-spi10-data-clk-state { 6484 /* MISO, MOSI, CLK */ 6485 pins = "gpio8", "gpio9", "gpio10"; 6486 function = "qup2_se2"; 6487 drive-strength = <6>; 6488 bias-disable; 6489 }; 6490 6491 qup_spi11_cs: qup-spi11-cs-state { 6492 pins = "gpio15"; 6493 function = "qup2_se3"; 6494 drive-strength = <6>; 6495 bias-disable; 6496 }; 6497 6498 qup_spi11_data_clk: qup-spi11-data-clk-state { 6499 /* MISO, MOSI, CLK */ 6500 pins = "gpio12", "gpio13", "gpio14"; 6501 function = "qup2_se3"; 6502 drive-strength = <6>; 6503 bias-disable; 6504 }; 6505 6506 qup_spi12_cs: qup-spi12-cs-state { 6507 pins = "gpio19"; 6508 function = "qup2_se4"; 6509 drive-strength = <6>; 6510 bias-disable; 6511 }; 6512 6513 qup_spi12_data_clk: qup-spi12-data-clk-state { 6514 /* MISO, MOSI, CLK */ 6515 pins = "gpio16", "gpio17", "gpio18"; 6516 function = "qup2_se4"; 6517 drive-strength = <6>; 6518 bias-disable; 6519 }; 6520 6521 qup_spi13_cs: qup-spi13-cs-state { 6522 pins = "gpio23"; 6523 function = "qup2_se5"; 6524 drive-strength = <6>; 6525 bias-disable; 6526 }; 6527 6528 qup_spi13_data_clk: qup-spi13-data-clk-state { 6529 /* MISO, MOSI, CLK */ 6530 pins = "gpio20", "gpio21", "gpio22"; 6531 function = "qup2_se5"; 6532 drive-strength = <6>; 6533 bias-disable; 6534 }; 6535 6536 qup_spi14_cs: qup-spi14-cs-state { 6537 pins = "gpio27"; 6538 function = "qup2_se6"; 6539 drive-strength = <6>; 6540 bias-disable; 6541 }; 6542 6543 qup_spi14_data_clk: qup-spi14-data-clk-state { 6544 /* MISO, MOSI, CLK */ 6545 pins = "gpio24", "gpio25", "gpio26"; 6546 function = "qup2_se6"; 6547 drive-strength = <6>; 6548 bias-disable; 6549 }; 6550 6551 qup_uart14_default: qup-uart14-default-state { 6552 /* TX, RX */ 6553 pins = "gpio26", "gpio27"; 6554 function = "qup2_se6"; 6555 drive-strength = <2>; 6556 bias-pull-up; 6557 }; 6558 6559 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 6560 /* CTS, RTS */ 6561 pins = "gpio24", "gpio25"; 6562 function = "qup2_se6"; 6563 drive-strength = <2>; 6564 bias-pull-down; 6565 }; 6566 6567 qup_uart15_default: qup-uart15-default-state { 6568 /* TX, RX */ 6569 pins = "gpio30", "gpio31"; 6570 function = "qup2_se7"; 6571 drive-strength = <2>; 6572 bias-disable; 6573 }; 6574 6575 sdc2_sleep: sdc2-sleep-state { 6576 clk-pins { 6577 pins = "sdc2_clk"; 6578 drive-strength = <2>; 6579 bias-disable; 6580 }; 6581 6582 cmd-pins { 6583 pins = "sdc2_cmd"; 6584 drive-strength = <2>; 6585 bias-pull-up; 6586 }; 6587 6588 data-pins { 6589 pins = "sdc2_data"; 6590 drive-strength = <2>; 6591 bias-pull-up; 6592 }; 6593 }; 6594 6595 sdc2_default: sdc2-default-state { 6596 clk-pins { 6597 pins = "sdc2_clk"; 6598 drive-strength = <16>; 6599 bias-disable; 6600 }; 6601 6602 cmd-pins { 6603 pins = "sdc2_cmd"; 6604 drive-strength = <10>; 6605 bias-pull-up; 6606 }; 6607 6608 data-pins { 6609 pins = "sdc2_data"; 6610 drive-strength = <10>; 6611 bias-pull-up; 6612 }; 6613 }; 6614 }; 6615 6616 funnel@10042000 { 6617 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6618 6619 reg = <0x0 0x10042000 0x0 0x1000>; 6620 6621 clocks = <&aoss_qmp>; 6622 clock-names = "apb_pclk"; 6623 6624 in-ports { 6625 #address-cells = <1>; 6626 #size-cells = <0>; 6627 6628 port@4 { 6629 reg = <4>; 6630 6631 funnel_in1_in_funnel_apss: endpoint { 6632 remote-endpoint = <&funnel_apss_out_funnel_in1>; 6633 }; 6634 }; 6635 }; 6636 6637 out-ports { 6638 port { 6639 funnel_in1_out_funnel_qdss: endpoint { 6640 remote-endpoint = <&funnel_qdss_in_funnel_in1>; 6641 }; 6642 }; 6643 }; 6644 }; 6645 6646 funnel@10045000 { 6647 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6648 6649 reg = <0x0 0x10045000 0x0 0x1000>; 6650 6651 clocks = <&aoss_qmp>; 6652 clock-names = "apb_pclk"; 6653 6654 in-ports { 6655 #address-cells = <1>; 6656 #size-cells = <0>; 6657 6658 port@1 { 6659 reg = <1>; 6660 6661 funnel_qdss_in_funnel_in1: endpoint { 6662 remote-endpoint = <&funnel_in1_out_funnel_qdss>; 6663 }; 6664 }; 6665 }; 6666 6667 out-ports { 6668 port { 6669 funnel_qdss_out_funnel_aoss: endpoint { 6670 remote-endpoint = <&funnel_aoss_in_funnel_qdss>; 6671 }; 6672 }; 6673 }; 6674 }; 6675 6676 funnel@10b04000 { 6677 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6678 6679 reg = <0x0 0x10b04000 0x0 0x1000>; 6680 6681 clocks = <&aoss_qmp>; 6682 clock-names = "apb_pclk"; 6683 6684 in-ports { 6685 #address-cells = <1>; 6686 #size-cells = <0>; 6687 6688 port@7 { 6689 reg = <7>; 6690 6691 funnel_aoss_in_funnel_qdss: endpoint { 6692 remote-endpoint = <&funnel_qdss_out_funnel_aoss>; 6693 }; 6694 }; 6695 }; 6696 6697 out-ports { 6698 port { 6699 funnel_aoss_out_tmc_etf: endpoint { 6700 remote-endpoint = <&tmc_etf_in_funnel_aoss>; 6701 }; 6702 }; 6703 }; 6704 }; 6705 6706 tmc@10b05000 { 6707 compatible = "arm,coresight-tmc", "arm,primecell"; 6708 6709 reg = <0x0 0x10b05000 0x0 0x1000>; 6710 6711 clocks = <&aoss_qmp>; 6712 clock-names = "apb_pclk"; 6713 6714 in-ports { 6715 port { 6716 tmc_etf_in_funnel_aoss: endpoint { 6717 remote-endpoint = <&funnel_aoss_out_tmc_etf>; 6718 }; 6719 }; 6720 }; 6721 }; 6722 6723 funnel@13810000 { 6724 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6725 6726 reg = <0x0 0x13810000 0x0 0x1000>; 6727 6728 clocks = <&aoss_qmp>; 6729 clock-names = "apb_pclk"; 6730 6731 in-ports { 6732 port { 6733 funnel_apss_in_funnel_ete: endpoint { 6734 remote-endpoint = <&funnel_ete_out_funnel_apss>; 6735 }; 6736 }; 6737 }; 6738 6739 out-ports { 6740 port { 6741 funnel_apss_out_funnel_in1: endpoint { 6742 remote-endpoint = <&funnel_in1_in_funnel_apss>; 6743 }; 6744 }; 6745 }; 6746 }; 6747 6748 apps_smmu: iommu@15000000 { 6749 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6750 reg = <0 0x15000000 0 0x100000>; 6751 6752 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, 6753 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, 6754 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, 6755 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, 6756 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, 6757 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 6758 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, 6759 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 6760 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 6761 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, 6762 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, 6763 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 6764 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 6765 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 6766 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, 6767 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, 6768 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, 6769 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, 6770 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 6771 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, 6772 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, 6773 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, 6774 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, 6775 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, 6776 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, 6777 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, 6778 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, 6779 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, 6780 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, 6781 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, 6782 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, 6783 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, 6784 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, 6785 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, 6786 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, 6787 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, 6788 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, 6789 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, 6790 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, 6791 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, 6792 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, 6793 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, 6794 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, 6795 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, 6796 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, 6797 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, 6798 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, 6799 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, 6800 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, 6801 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, 6802 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, 6803 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, 6804 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, 6805 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, 6806 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, 6807 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, 6808 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, 6809 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, 6810 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, 6811 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, 6812 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, 6813 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>, 6814 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>, 6815 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>, 6816 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>, 6817 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>, 6818 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>, 6819 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 6820 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 6821 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>, 6822 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>, 6823 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>, 6824 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>, 6825 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>, 6826 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>, 6827 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>, 6828 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>, 6829 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>, 6830 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, 6831 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, 6832 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, 6833 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, 6834 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, 6835 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>, 6836 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>, 6837 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>, 6838 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>, 6839 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>, 6840 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>, 6841 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>, 6842 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>, 6843 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>, 6844 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>, 6845 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>, 6846 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>, 6847 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>, 6848 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>; 6849 6850 #iommu-cells = <2>; 6851 #global-interrupts = <1>; 6852 6853 dma-coherent; 6854 }; 6855 6856 intc: interrupt-controller@17100000 { 6857 compatible = "arm,gic-v3"; 6858 reg = <0 0x17100000 0 0x10000>, /* GICD */ 6859 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 6860 6861 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>; 6862 6863 #interrupt-cells = <4>; 6864 interrupt-controller; 6865 6866 #redistributor-regions = <1>; 6867 redistributor-stride = <0 0x40000>; 6868 6869 #address-cells = <2>; 6870 #size-cells = <2>; 6871 ranges; 6872 6873 ppi-partitions { 6874 ppi_cluster0: interrupt-partition-0 { 6875 affinity = <&cpu0 &cpu1>; 6876 }; 6877 6878 ppi_cluster1: interrupt-partition-1 { 6879 affinity = <&cpu2 &cpu3 &cpu4 &cpu5 &cpu6>; 6880 }; 6881 6882 ppi_cluster2: interrupt-partition-2 { 6883 affinity = <&cpu7>; 6884 }; 6885 }; 6886 6887 gic_its: msi-controller@17140000 { 6888 compatible = "arm,gic-v3-its"; 6889 reg = <0 0x17140000 0 0x20000>; 6890 6891 msi-controller; 6892 #msi-cells = <1>; 6893 }; 6894 }; 6895 6896 timer@17420000 { 6897 compatible = "arm,armv7-timer-mem"; 6898 reg = <0 0x17420000 0 0x1000>; 6899 6900 ranges = <0 0 0 0x20000000>; 6901 #address-cells = <1>; 6902 #size-cells = <1>; 6903 6904 frame@17421000 { 6905 reg = <0x17421000 0x1000>, 6906 <0x17422000 0x1000>; 6907 6908 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, 6909 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 6910 6911 frame-number = <0>; 6912 }; 6913 6914 frame@17423000 { 6915 reg = <0x17423000 0x1000>; 6916 6917 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 6918 6919 frame-number = <1>; 6920 6921 status = "disabled"; 6922 }; 6923 6924 frame@17425000 { 6925 reg = <0x17425000 0x1000>; 6926 6927 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 6928 6929 frame-number = <2>; 6930 6931 status = "disabled"; 6932 }; 6933 6934 frame@17427000 { 6935 reg = <0x17427000 0x1000>; 6936 6937 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 6938 6939 frame-number = <3>; 6940 6941 status = "disabled"; 6942 }; 6943 6944 frame@17429000 { 6945 reg = <0x17429000 0x1000>; 6946 6947 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 6948 6949 frame-number = <4>; 6950 6951 status = "disabled"; 6952 }; 6953 6954 frame@1742b000 { 6955 reg = <0x1742b000 0x1000>; 6956 6957 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; 6958 6959 frame-number = <5>; 6960 6961 status = "disabled"; 6962 }; 6963 6964 frame@1742d000 { 6965 reg = <0x1742d000 0x1000>; 6966 6967 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 6968 6969 frame-number = <6>; 6970 6971 status = "disabled"; 6972 }; 6973 }; 6974 6975 apps_rsc: rsc@17a00000 { 6976 compatible = "qcom,rpmh-rsc"; 6977 reg = <0 0x17a00000 0 0x10000>, 6978 <0 0x17a10000 0 0x10000>, 6979 <0 0x17a20000 0 0x10000>; 6980 reg-names = "drv-0", 6981 "drv-1", 6982 "drv-2"; 6983 6984 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, 6985 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, 6986 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; 6987 6988 power-domains = <&cluster_pd>; 6989 6990 qcom,tcs-offset = <0xd00>; 6991 qcom,drv-id = <2>; 6992 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 6993 <WAKE_TCS 2>, <CONTROL_TCS 0>; 6994 6995 label = "apps_rsc"; 6996 6997 apps_bcm_voter: bcm-voter { 6998 compatible = "qcom,bcm-voter"; 6999 }; 7000 7001 rpmhcc: clock-controller { 7002 compatible = "qcom,sm8650-rpmh-clk"; 7003 7004 clocks = <&xo_board>; 7005 clock-names = "xo"; 7006 7007 #clock-cells = <1>; 7008 }; 7009 7010 rpmhpd: power-controller { 7011 compatible = "qcom,sm8650-rpmhpd"; 7012 7013 operating-points-v2 = <&rpmhpd_opp_table>; 7014 7015 #power-domain-cells = <1>; 7016 7017 rpmhpd_opp_table: opp-table { 7018 compatible = "operating-points-v2"; 7019 7020 rpmhpd_opp_ret: opp-16 { 7021 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 7022 }; 7023 7024 rpmhpd_opp_min_svs: opp-48 { 7025 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 7026 }; 7027 7028 rpmhpd_opp_low_svs_d2: opp-52 { 7029 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 7030 }; 7031 7032 rpmhpd_opp_low_svs_d1: opp-56 { 7033 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 7034 }; 7035 7036 rpmhpd_opp_low_svs_d0: opp-60 { 7037 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 7038 }; 7039 7040 rpmhpd_opp_low_svs: opp-64 { 7041 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 7042 }; 7043 7044 rpmhpd_opp_low_svs_l1: opp-80 { 7045 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 7046 }; 7047 7048 rpmhpd_opp_svs: opp-128 { 7049 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 7050 }; 7051 7052 rpmhpd_opp_svs_l0: opp-144 { 7053 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 7054 }; 7055 7056 rpmhpd_opp_svs_l1: opp-192 { 7057 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 7058 }; 7059 7060 rpmhpd_opp_nom: opp-256 { 7061 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 7062 }; 7063 7064 rpmhpd_opp_nom_l1: opp-320 { 7065 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 7066 }; 7067 7068 rpmhpd_opp_nom_l2: opp-336 { 7069 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 7070 }; 7071 7072 rpmhpd_opp_turbo: opp-384 { 7073 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 7074 }; 7075 7076 rpmhpd_opp_turbo_l1: opp-416 { 7077 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 7078 }; 7079 }; 7080 }; 7081 }; 7082 7083 epss_l3: interconnect@17d90000 { 7084 compatible = "qcom,sm8650-epss-l3", "qcom,epss-l3"; 7085 reg = <0 0x17d90000 0 0x1000>; 7086 7087 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 7088 clock-names = "xo", "alternate"; 7089 7090 #interconnect-cells = <1>; 7091 }; 7092 7093 cpufreq_hw: cpufreq@17d91000 { 7094 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss"; 7095 reg = <0 0x17d91000 0 0x1000>, 7096 <0 0x17d92000 0 0x1000>, 7097 <0 0x17d93000 0 0x1000>, 7098 <0 0x17d94000 0 0x1000>; 7099 reg-names = "freq-domain0", 7100 "freq-domain1", 7101 "freq-domain2", 7102 "freq-domain3"; 7103 7104 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, 7105 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>, 7106 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, 7107 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH 0>; 7108 interrupt-names = "dcvsh-irq-0", 7109 "dcvsh-irq-1", 7110 "dcvsh-irq-2", 7111 "dcvsh-irq-3"; 7112 7113 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 7114 clock-names = "xo", "alternate"; 7115 7116 #freq-domain-cells = <1>; 7117 #clock-cells = <1>; 7118 }; 7119 7120 pmu@24091000 { 7121 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 7122 reg = <0 0x24091000 0 0x1000>; 7123 7124 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 7125 7126 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 7127 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 7128 7129 operating-points-v2 = <&llcc_bwmon_opp_table>; 7130 7131 llcc_bwmon_opp_table: opp-table { 7132 compatible = "operating-points-v2"; 7133 7134 opp-0 { 7135 opp-peak-kBps = <2086000>; 7136 }; 7137 7138 opp-1 { 7139 opp-peak-kBps = <2929000>; 7140 }; 7141 7142 opp-2 { 7143 opp-peak-kBps = <5931000>; 7144 }; 7145 7146 opp-3 { 7147 opp-peak-kBps = <6515000>; 7148 }; 7149 7150 opp-4 { 7151 opp-peak-kBps = <7980000>; 7152 }; 7153 7154 opp-5 { 7155 opp-peak-kBps = <10437000>; 7156 }; 7157 7158 opp-6 { 7159 opp-peak-kBps = <12157000>; 7160 }; 7161 7162 opp-7 { 7163 opp-peak-kBps = <14060000>; 7164 }; 7165 7166 opp-8 { 7167 opp-peak-kBps = <16113000>; 7168 }; 7169 }; 7170 }; 7171 7172 pmu@240b7400 { 7173 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; 7174 reg = <0 0x240b7400 0 0x600>; 7175 7176 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>; 7177 7178 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 7179 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 7180 7181 operating-points-v2 = <&cpu_bwmon_opp_table>; 7182 7183 cpu_bwmon_opp_table: opp-table { 7184 compatible = "operating-points-v2"; 7185 7186 opp-0 { 7187 opp-peak-kBps = <4577000>; 7188 }; 7189 7190 opp-1 { 7191 opp-peak-kBps = <7110000>; 7192 }; 7193 7194 opp-2 { 7195 opp-peak-kBps = <9155000>; 7196 }; 7197 7198 opp-3 { 7199 opp-peak-kBps = <12298000>; 7200 }; 7201 7202 opp-4 { 7203 opp-peak-kBps = <14236000>; 7204 }; 7205 7206 opp-5 { 7207 opp-peak-kBps = <16265000>; 7208 }; 7209 }; 7210 }; 7211 7212 gem_noc: interconnect@24100000 { 7213 compatible = "qcom,sm8650-gem-noc"; 7214 reg = <0 0x24100000 0 0xc5080>; 7215 7216 qcom,bcm-voters = <&apps_bcm_voter>; 7217 7218 #interconnect-cells = <2>; 7219 }; 7220 7221 system-cache-controller@25000000 { 7222 compatible = "qcom,sm8650-llcc"; 7223 reg = <0 0x25000000 0 0x200000>, 7224 <0 0x25400000 0 0x200000>, 7225 <0 0x25200000 0 0x200000>, 7226 <0 0x25600000 0 0x200000>, 7227 <0 0x25800000 0 0x200000>, 7228 <0 0x25a00000 0 0x200000>; 7229 reg-names = "llcc0_base", 7230 "llcc1_base", 7231 "llcc2_base", 7232 "llcc3_base", 7233 "llcc_broadcast_base", 7234 "llcc_broadcast_and_base"; 7235 7236 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH 0>; 7237 }; 7238 7239 nsp_noc: interconnect@320c0000 { 7240 compatible = "qcom,sm8650-nsp-noc"; 7241 reg = <0 0x320c0000 0 0xf080>; 7242 7243 qcom,bcm-voters = <&apps_bcm_voter>; 7244 7245 #interconnect-cells = <2>; 7246 }; 7247 7248 remoteproc_cdsp: remoteproc@32300000 { 7249 compatible = "qcom,sm8650-cdsp-pas"; 7250 reg = <0x0 0x32300000 0x0 0x10000>; 7251 7252 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, 7253 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 7254 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 7255 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 7256 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 7257 interrupt-names = "wdog", 7258 "fatal", 7259 "ready", 7260 "handover", 7261 "stop-ack"; 7262 7263 clocks = <&rpmhcc RPMH_CXO_CLK>; 7264 clock-names = "xo"; 7265 7266 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 7267 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7268 7269 power-domains = <&rpmhpd RPMHPD_CX>, 7270 <&rpmhpd RPMHPD_MXC>, 7271 <&rpmhpd RPMHPD_NSP>; 7272 power-domain-names = "cx", 7273 "mxc", 7274 "nsp"; 7275 7276 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; 7277 7278 qcom,qmp = <&aoss_qmp>; 7279 7280 qcom,smem-states = <&smp2p_cdsp_out 0>; 7281 qcom,smem-state-names = "stop"; 7282 7283 status = "disabled"; 7284 7285 glink-edge { 7286 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 7287 IPCC_MPROC_SIGNAL_GLINK_QMP 7288 IRQ_TYPE_EDGE_RISING>; 7289 7290 mboxes = <&ipcc IPCC_CLIENT_CDSP 7291 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7292 7293 qcom,remote-pid = <5>; 7294 7295 label = "cdsp"; 7296 7297 fastrpc { 7298 compatible = "qcom,fastrpc"; 7299 7300 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7301 7302 label = "cdsp"; 7303 7304 qcom,non-secure-domain; 7305 7306 #address-cells = <1>; 7307 #size-cells = <0>; 7308 7309 compute-cb@1 { 7310 compatible = "qcom,fastrpc-compute-cb"; 7311 reg = <1>; 7312 7313 iommus = <&apps_smmu 0x1961 0x0>, 7314 <&apps_smmu 0x0c01 0x20>, 7315 <&apps_smmu 0x19c1 0x0>; 7316 dma-coherent; 7317 }; 7318 7319 compute-cb@2 { 7320 compatible = "qcom,fastrpc-compute-cb"; 7321 reg = <2>; 7322 7323 iommus = <&apps_smmu 0x1962 0x0>, 7324 <&apps_smmu 0x0c02 0x20>, 7325 <&apps_smmu 0x19c2 0x0>; 7326 dma-coherent; 7327 }; 7328 7329 compute-cb@3 { 7330 compatible = "qcom,fastrpc-compute-cb"; 7331 reg = <3>; 7332 7333 iommus = <&apps_smmu 0x1963 0x0>, 7334 <&apps_smmu 0x0c03 0x20>, 7335 <&apps_smmu 0x19c3 0x0>; 7336 dma-coherent; 7337 }; 7338 7339 compute-cb@4 { 7340 compatible = "qcom,fastrpc-compute-cb"; 7341 reg = <4>; 7342 7343 iommus = <&apps_smmu 0x1964 0x0>, 7344 <&apps_smmu 0x0c04 0x20>, 7345 <&apps_smmu 0x19c4 0x0>; 7346 dma-coherent; 7347 }; 7348 7349 compute-cb@5 { 7350 compatible = "qcom,fastrpc-compute-cb"; 7351 reg = <5>; 7352 7353 iommus = <&apps_smmu 0x1965 0x0>, 7354 <&apps_smmu 0x0c05 0x20>, 7355 <&apps_smmu 0x19c5 0x0>; 7356 dma-coherent; 7357 }; 7358 7359 compute-cb@6 { 7360 compatible = "qcom,fastrpc-compute-cb"; 7361 reg = <6>; 7362 7363 iommus = <&apps_smmu 0x1966 0x0>, 7364 <&apps_smmu 0x0c06 0x20>, 7365 <&apps_smmu 0x19c6 0x0>; 7366 dma-coherent; 7367 }; 7368 7369 compute-cb@7 { 7370 compatible = "qcom,fastrpc-compute-cb"; 7371 reg = <7>; 7372 7373 iommus = <&apps_smmu 0x1967 0x0>, 7374 <&apps_smmu 0x0c07 0x20>, 7375 <&apps_smmu 0x19c7 0x0>; 7376 dma-coherent; 7377 }; 7378 7379 compute-cb@8 { 7380 compatible = "qcom,fastrpc-compute-cb"; 7381 reg = <8>; 7382 7383 iommus = <&apps_smmu 0x1968 0x0>, 7384 <&apps_smmu 0x0c08 0x20>, 7385 <&apps_smmu 0x19c8 0x0>; 7386 dma-coherent; 7387 }; 7388 7389 /* note: secure cb9 in downstream */ 7390 7391 compute-cb@12 { 7392 compatible = "qcom,fastrpc-compute-cb"; 7393 reg = <12>; 7394 7395 iommus = <&apps_smmu 0x196c 0x0>, 7396 <&apps_smmu 0x0c0c 0x20>, 7397 <&apps_smmu 0x19cc 0x0>; 7398 dma-coherent; 7399 }; 7400 7401 compute-cb@13 { 7402 compatible = "qcom,fastrpc-compute-cb"; 7403 reg = <13>; 7404 7405 iommus = <&apps_smmu 0x196d 0x0>, 7406 <&apps_smmu 0x0c0d 0x20>, 7407 <&apps_smmu 0x19cd 0x0>; 7408 dma-coherent; 7409 }; 7410 7411 compute-cb@14 { 7412 compatible = "qcom,fastrpc-compute-cb"; 7413 reg = <14>; 7414 7415 iommus = <&apps_smmu 0x196e 0x0>, 7416 <&apps_smmu 0x0c0e 0x20>, 7417 <&apps_smmu 0x19ce 0x0>; 7418 dma-coherent; 7419 }; 7420 }; 7421 }; 7422 }; 7423 }; 7424 7425 thermal-zones { 7426 aoss0-thermal { 7427 thermal-sensors = <&tsens0 0>; 7428 7429 trips { 7430 aoss0-hot { 7431 temperature = <110000>; 7432 hysteresis = <1000>; 7433 type = "hot"; 7434 }; 7435 7436 aoss0-critical { 7437 temperature = <115000>; 7438 hysteresis = <0>; 7439 type = "critical"; 7440 }; 7441 }; 7442 }; 7443 7444 cpuss0-thermal { 7445 thermal-sensors = <&tsens0 1>; 7446 7447 trips { 7448 cpuss0-hot { 7449 temperature = <110000>; 7450 hysteresis = <1000>; 7451 type = "hot"; 7452 }; 7453 7454 cpuss0-critical { 7455 temperature = <115000>; 7456 hysteresis = <0>; 7457 type = "critical"; 7458 }; 7459 }; 7460 }; 7461 7462 cpuss1-thermal { 7463 thermal-sensors = <&tsens0 2>; 7464 7465 trips { 7466 cpuss1-hot { 7467 temperature = <110000>; 7468 hysteresis = <1000>; 7469 type = "hot"; 7470 }; 7471 7472 cpuss1-critical { 7473 temperature = <115000>; 7474 hysteresis = <0>; 7475 type = "critical"; 7476 }; 7477 }; 7478 }; 7479 7480 cpuss2-thermal { 7481 thermal-sensors = <&tsens0 3>; 7482 7483 trips { 7484 cpuss2-hot { 7485 temperature = <110000>; 7486 hysteresis = <1000>; 7487 type = "hot"; 7488 }; 7489 7490 cpuss2-critical { 7491 temperature = <115000>; 7492 hysteresis = <0>; 7493 type = "critical"; 7494 }; 7495 }; 7496 }; 7497 7498 cpuss3-thermal { 7499 thermal-sensors = <&tsens0 4>; 7500 7501 trips { 7502 cpuss3-hot { 7503 temperature = <110000>; 7504 hysteresis = <1000>; 7505 type = "hot"; 7506 }; 7507 7508 cpuss3-critical { 7509 temperature = <115000>; 7510 hysteresis = <0>; 7511 type = "critical"; 7512 }; 7513 }; 7514 }; 7515 7516 cpu2-top-thermal { 7517 thermal-sensors = <&tsens0 5>; 7518 7519 trips { 7520 cpu2-critical { 7521 temperature = <110000>; 7522 hysteresis = <1000>; 7523 type = "critical"; 7524 }; 7525 }; 7526 }; 7527 7528 cpu2-bottom-thermal { 7529 thermal-sensors = <&tsens0 6>; 7530 7531 trips { 7532 cpu2-critical { 7533 temperature = <110000>; 7534 hysteresis = <1000>; 7535 type = "critical"; 7536 }; 7537 }; 7538 }; 7539 7540 cpu3-top-thermal { 7541 thermal-sensors = <&tsens0 7>; 7542 7543 trips { 7544 cpu3-critical { 7545 temperature = <110000>; 7546 hysteresis = <1000>; 7547 type = "critical"; 7548 }; 7549 }; 7550 }; 7551 7552 cpu3-bottom-thermal { 7553 thermal-sensors = <&tsens0 8>; 7554 7555 trips { 7556 cpu3-critical { 7557 temperature = <110000>; 7558 hysteresis = <1000>; 7559 type = "critical"; 7560 }; 7561 }; 7562 }; 7563 7564 cpu4-top-thermal { 7565 thermal-sensors = <&tsens0 9>; 7566 7567 trips { 7568 cpu4-critical { 7569 temperature = <110000>; 7570 hysteresis = <1000>; 7571 type = "critical"; 7572 }; 7573 }; 7574 }; 7575 7576 cpu4-bottom-thermal { 7577 thermal-sensors = <&tsens0 10>; 7578 7579 trips { 7580 cpu4-critical { 7581 temperature = <110000>; 7582 hysteresis = <1000>; 7583 type = "critical"; 7584 }; 7585 }; 7586 }; 7587 7588 cpu5-top-thermal { 7589 thermal-sensors = <&tsens0 11>; 7590 7591 trips { 7592 cpu5-critical { 7593 temperature = <110000>; 7594 hysteresis = <1000>; 7595 type = "critical"; 7596 }; 7597 }; 7598 }; 7599 7600 cpu5-bottom-thermal { 7601 thermal-sensors = <&tsens0 12>; 7602 7603 trips { 7604 cpu5-critical { 7605 temperature = <110000>; 7606 hysteresis = <1000>; 7607 type = "critical"; 7608 }; 7609 }; 7610 }; 7611 7612 cpu6-top-thermal { 7613 thermal-sensors = <&tsens0 13>; 7614 7615 trips { 7616 cpu6-critical { 7617 temperature = <110000>; 7618 hysteresis = <1000>; 7619 type = "critical"; 7620 }; 7621 }; 7622 }; 7623 7624 cpu6-bottom-thermal { 7625 thermal-sensors = <&tsens0 14>; 7626 7627 trips { 7628 cpu6-critical { 7629 temperature = <110000>; 7630 hysteresis = <1000>; 7631 type = "critical"; 7632 }; 7633 }; 7634 }; 7635 7636 aoss1-thermal { 7637 thermal-sensors = <&tsens1 0>; 7638 7639 trips { 7640 aoss1-hot { 7641 temperature = <110000>; 7642 hysteresis = <1000>; 7643 type = "hot"; 7644 }; 7645 7646 aoss1-critical { 7647 temperature = <115000>; 7648 hysteresis = <0>; 7649 type = "critical"; 7650 }; 7651 }; 7652 }; 7653 7654 cpu7-top-thermal { 7655 thermal-sensors = <&tsens1 1>; 7656 7657 trips { 7658 cpu7-critical { 7659 temperature = <110000>; 7660 hysteresis = <1000>; 7661 type = "critical"; 7662 }; 7663 }; 7664 }; 7665 7666 cpu7-middle-thermal { 7667 thermal-sensors = <&tsens1 2>; 7668 7669 trips { 7670 cpu7-critical { 7671 temperature = <110000>; 7672 hysteresis = <1000>; 7673 type = "critical"; 7674 }; 7675 }; 7676 }; 7677 7678 cpu7-bottom-thermal { 7679 thermal-sensors = <&tsens1 3>; 7680 7681 trips { 7682 cpu7-critical { 7683 temperature = <110000>; 7684 hysteresis = <1000>; 7685 type = "critical"; 7686 }; 7687 }; 7688 }; 7689 7690 cpu0-thermal { 7691 thermal-sensors = <&tsens1 4>; 7692 7693 trips { 7694 cpu0-critical { 7695 temperature = <110000>; 7696 hysteresis = <1000>; 7697 type = "critical"; 7698 }; 7699 }; 7700 }; 7701 7702 cpu1-thermal { 7703 thermal-sensors = <&tsens1 5>; 7704 7705 trips { 7706 cpu1-critical { 7707 temperature = <110000>; 7708 hysteresis = <1000>; 7709 type = "critical"; 7710 }; 7711 }; 7712 }; 7713 7714 nsphvx0-thermal { 7715 thermal-sensors = <&tsens2 6>; 7716 7717 trips { 7718 nsphvx0-hot { 7719 temperature = <110000>; 7720 hysteresis = <1000>; 7721 type = "hot"; 7722 }; 7723 7724 nsphvx0-critical { 7725 temperature = <115000>; 7726 hysteresis = <0>; 7727 type = "critical"; 7728 }; 7729 }; 7730 }; 7731 7732 nsphvx1-thermal { 7733 thermal-sensors = <&tsens2 7>; 7734 7735 trips { 7736 nsphvx1-hot { 7737 temperature = <110000>; 7738 hysteresis = <1000>; 7739 type = "hot"; 7740 }; 7741 7742 nsphvx1-critical { 7743 temperature = <115000>; 7744 hysteresis = <0>; 7745 type = "critical"; 7746 }; 7747 }; 7748 }; 7749 7750 nsphmx0-thermal { 7751 thermal-sensors = <&tsens2 8>; 7752 7753 trips { 7754 nsphmx0-hot { 7755 temperature = <110000>; 7756 hysteresis = <1000>; 7757 type = "hot"; 7758 }; 7759 7760 nsphmx0-critical { 7761 temperature = <115000>; 7762 hysteresis = <0>; 7763 type = "critical"; 7764 }; 7765 }; 7766 }; 7767 7768 nsphmx1-thermal { 7769 thermal-sensors = <&tsens2 9>; 7770 7771 trips { 7772 nsphmx1-hot { 7773 temperature = <110000>; 7774 hysteresis = <1000>; 7775 type = "hot"; 7776 }; 7777 7778 nsphmx1-critical { 7779 temperature = <115000>; 7780 hysteresis = <0>; 7781 type = "critical"; 7782 }; 7783 }; 7784 }; 7785 7786 nsphmx2-thermal { 7787 thermal-sensors = <&tsens2 10>; 7788 7789 trips { 7790 nsphmx2-hot { 7791 temperature = <110000>; 7792 hysteresis = <1000>; 7793 type = "hot"; 7794 }; 7795 7796 nsphmx2-critical { 7797 temperature = <115000>; 7798 hysteresis = <0>; 7799 type = "critical"; 7800 }; 7801 }; 7802 }; 7803 7804 nsphmx3-thermal { 7805 thermal-sensors = <&tsens2 11>; 7806 7807 trips { 7808 nsphmx3-hot { 7809 temperature = <110000>; 7810 hysteresis = <1000>; 7811 type = "hot"; 7812 }; 7813 7814 nsphmx3-critical { 7815 temperature = <115000>; 7816 hysteresis = <0>; 7817 type = "critical"; 7818 }; 7819 }; 7820 }; 7821 7822 video-thermal { 7823 thermal-sensors = <&tsens1 12>; 7824 7825 trips { 7826 video-hot { 7827 temperature = <110000>; 7828 hysteresis = <1000>; 7829 type = "hot"; 7830 }; 7831 7832 video-critical { 7833 temperature = <115000>; 7834 hysteresis = <0>; 7835 type = "critical"; 7836 }; 7837 }; 7838 }; 7839 7840 ddr-thermal { 7841 thermal-sensors = <&tsens1 13>; 7842 7843 trips { 7844 ddr-hot { 7845 temperature = <110000>; 7846 hysteresis = <1000>; 7847 type = "hot"; 7848 }; 7849 7850 ddr-critical { 7851 temperature = <115000>; 7852 hysteresis = <0>; 7853 type = "critical"; 7854 }; 7855 }; 7856 }; 7857 7858 camera0-thermal { 7859 thermal-sensors = <&tsens1 14>; 7860 7861 trips { 7862 camera0-hot { 7863 temperature = <110000>; 7864 hysteresis = <1000>; 7865 type = "hot"; 7866 }; 7867 7868 camera0-critical { 7869 temperature = <115000>; 7870 hysteresis = <0>; 7871 type = "critical"; 7872 }; 7873 }; 7874 }; 7875 7876 camera1-thermal { 7877 thermal-sensors = <&tsens1 15>; 7878 7879 trips { 7880 camera1-hot { 7881 temperature = <110000>; 7882 hysteresis = <1000>; 7883 type = "hot"; 7884 }; 7885 7886 camera1-critical { 7887 temperature = <115000>; 7888 hysteresis = <0>; 7889 type = "critical"; 7890 }; 7891 }; 7892 }; 7893 7894 aoss2-thermal { 7895 thermal-sensors = <&tsens2 0>; 7896 7897 trips { 7898 aoss2-hot { 7899 temperature = <110000>; 7900 hysteresis = <1000>; 7901 type = "hot"; 7902 }; 7903 7904 aoss2-critical { 7905 temperature = <115000>; 7906 hysteresis = <0>; 7907 type = "critical"; 7908 }; 7909 }; 7910 }; 7911 7912 gpuss0-thermal { 7913 polling-delay-passive = <10>; 7914 7915 thermal-sensors = <&tsens2 1>; 7916 7917 cooling-maps { 7918 map0 { 7919 trip = <&gpu0_alert0>; 7920 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7921 }; 7922 }; 7923 7924 trips { 7925 gpu0_alert0: trip-point0 { 7926 temperature = <95000>; 7927 hysteresis = <1000>; 7928 type = "passive"; 7929 }; 7930 7931 trip-point1 { 7932 temperature = <110000>; 7933 hysteresis = <1000>; 7934 type = "hot"; 7935 }; 7936 7937 trip-point2 { 7938 temperature = <115000>; 7939 hysteresis = <0>; 7940 type = "critical"; 7941 }; 7942 }; 7943 }; 7944 7945 gpuss1-thermal { 7946 polling-delay-passive = <10>; 7947 7948 thermal-sensors = <&tsens2 2>; 7949 7950 cooling-maps { 7951 map0 { 7952 trip = <&gpu1_alert0>; 7953 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7954 }; 7955 }; 7956 7957 trips { 7958 gpu1_alert0: trip-point0 { 7959 temperature = <95000>; 7960 hysteresis = <1000>; 7961 type = "passive"; 7962 }; 7963 7964 trip-point1 { 7965 temperature = <110000>; 7966 hysteresis = <1000>; 7967 type = "hot"; 7968 }; 7969 7970 trip-point2 { 7971 temperature = <115000>; 7972 hysteresis = <0>; 7973 type = "critical"; 7974 }; 7975 }; 7976 }; 7977 7978 gpuss2-thermal { 7979 polling-delay-passive = <10>; 7980 7981 thermal-sensors = <&tsens2 3>; 7982 7983 cooling-maps { 7984 map0 { 7985 trip = <&gpu2_alert0>; 7986 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7987 }; 7988 }; 7989 7990 trips { 7991 gpu2_alert0: trip-point0 { 7992 temperature = <95000>; 7993 hysteresis = <1000>; 7994 type = "passive"; 7995 }; 7996 7997 trip-point1 { 7998 temperature = <110000>; 7999 hysteresis = <1000>; 8000 type = "hot"; 8001 }; 8002 8003 trip-point2 { 8004 temperature = <115000>; 8005 hysteresis = <0>; 8006 type = "critical"; 8007 }; 8008 }; 8009 }; 8010 8011 gpuss3-thermal { 8012 polling-delay-passive = <10>; 8013 8014 thermal-sensors = <&tsens2 4>; 8015 8016 cooling-maps { 8017 map0 { 8018 trip = <&gpu3_alert0>; 8019 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8020 }; 8021 }; 8022 8023 trips { 8024 gpu3_alert0: trip-point0 { 8025 temperature = <95000>; 8026 hysteresis = <1000>; 8027 type = "passive"; 8028 }; 8029 8030 trip-point1 { 8031 temperature = <110000>; 8032 hysteresis = <1000>; 8033 type = "hot"; 8034 }; 8035 8036 trip-point2 { 8037 temperature = <115000>; 8038 hysteresis = <0>; 8039 type = "critical"; 8040 }; 8041 }; 8042 }; 8043 8044 gpuss4-thermal { 8045 polling-delay-passive = <10>; 8046 8047 thermal-sensors = <&tsens2 5>; 8048 8049 cooling-maps { 8050 map0 { 8051 trip = <&gpu4_alert0>; 8052 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8053 }; 8054 }; 8055 8056 trips { 8057 gpu4_alert0: trip-point0 { 8058 temperature = <95000>; 8059 hysteresis = <1000>; 8060 type = "passive"; 8061 }; 8062 8063 trip-point1 { 8064 temperature = <110000>; 8065 hysteresis = <1000>; 8066 type = "hot"; 8067 }; 8068 8069 trip-point2 { 8070 temperature = <115000>; 8071 hysteresis = <0>; 8072 type = "critical"; 8073 }; 8074 }; 8075 }; 8076 8077 gpuss5-thermal { 8078 polling-delay-passive = <10>; 8079 8080 thermal-sensors = <&tsens2 6>; 8081 8082 cooling-maps { 8083 map0 { 8084 trip = <&gpu5_alert0>; 8085 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8086 }; 8087 }; 8088 8089 trips { 8090 gpu5_alert0: trip-point0 { 8091 temperature = <95000>; 8092 hysteresis = <1000>; 8093 type = "passive"; 8094 }; 8095 8096 trip-point1 { 8097 temperature = <110000>; 8098 hysteresis = <1000>; 8099 type = "hot"; 8100 }; 8101 8102 trip-point2 { 8103 temperature = <115000>; 8104 hysteresis = <0>; 8105 type = "critical"; 8106 }; 8107 }; 8108 }; 8109 8110 gpuss6-thermal { 8111 polling-delay-passive = <10>; 8112 8113 thermal-sensors = <&tsens2 7>; 8114 8115 cooling-maps { 8116 map0 { 8117 trip = <&gpu6_alert0>; 8118 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8119 }; 8120 }; 8121 8122 trips { 8123 gpu6_alert0: trip-point0 { 8124 temperature = <95000>; 8125 hysteresis = <1000>; 8126 type = "passive"; 8127 }; 8128 8129 trip-point1 { 8130 temperature = <110000>; 8131 hysteresis = <1000>; 8132 type = "hot"; 8133 }; 8134 8135 trip-point2 { 8136 temperature = <115000>; 8137 hysteresis = <0>; 8138 type = "critical"; 8139 }; 8140 }; 8141 }; 8142 8143 gpuss7-thermal { 8144 polling-delay-passive = <10>; 8145 8146 thermal-sensors = <&tsens2 8>; 8147 8148 cooling-maps { 8149 map0 { 8150 trip = <&gpu7_alert0>; 8151 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8152 }; 8153 }; 8154 8155 trips { 8156 gpu7_alert0: trip-point0 { 8157 temperature = <95000>; 8158 hysteresis = <1000>; 8159 type = "passive"; 8160 }; 8161 8162 trip-point1 { 8163 temperature = <110000>; 8164 hysteresis = <1000>; 8165 type = "hot"; 8166 }; 8167 8168 trip-point2 { 8169 temperature = <115000>; 8170 hysteresis = <0>; 8171 type = "critical"; 8172 }; 8173 }; 8174 }; 8175 8176 modem0-thermal { 8177 thermal-sensors = <&tsens2 9>; 8178 8179 trips { 8180 modem0-hot { 8181 temperature = <110000>; 8182 hysteresis = <1000>; 8183 type = "hot"; 8184 }; 8185 8186 modem0-critical { 8187 temperature = <115000>; 8188 hysteresis = <0>; 8189 type = "critical"; 8190 }; 8191 }; 8192 }; 8193 8194 modem1-thermal { 8195 thermal-sensors = <&tsens2 10>; 8196 8197 trips { 8198 modem1-hot { 8199 temperature = <110000>; 8200 hysteresis = <1000>; 8201 type = "hot"; 8202 }; 8203 8204 modem1-critical { 8205 temperature = <115000>; 8206 hysteresis = <0>; 8207 type = "critical"; 8208 }; 8209 }; 8210 }; 8211 8212 modem2-thermal { 8213 thermal-sensors = <&tsens2 11>; 8214 8215 trips { 8216 modem2-hot { 8217 temperature = <110000>; 8218 hysteresis = <1000>; 8219 type = "hot"; 8220 }; 8221 8222 modem2-critical { 8223 temperature = <115000>; 8224 hysteresis = <0>; 8225 type = "critical"; 8226 }; 8227 }; 8228 }; 8229 8230 modem3-thermal { 8231 thermal-sensors = <&tsens2 12>; 8232 8233 trips { 8234 modem3-hot { 8235 temperature = <110000>; 8236 hysteresis = <1000>; 8237 type = "hot"; 8238 }; 8239 8240 modem3-critical { 8241 temperature = <115000>; 8242 hysteresis = <0>; 8243 type = "critical"; 8244 }; 8245 }; 8246 }; 8247 }; 8248 8249 timer { 8250 compatible = "arm,armv8-timer"; 8251 8252 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 8253 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 8254 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 8255 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 8256 }; 8257}; 8258