1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8650-dispcc.h> 8#include <dt-bindings/clock/qcom,sm8650-gcc.h> 9#include <dt-bindings/clock/qcom,sm8650-gpucc.h> 10#include <dt-bindings/clock/qcom,sm8650-tcsr.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/firmware/qcom,scm.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/reset/qcom,sm8650-gpucc.h> 22#include <dt-bindings/soc/qcom,gpr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 chosen { }; 34 35 clocks { 36 xo_board: xo-board { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 }; 45 46 bi_tcxo_div2: bi-tcxo-div2-clk { 47 compatible = "fixed-factor-clock"; 48 #clock-cells = <0>; 49 50 clocks = <&rpmhcc RPMH_CXO_CLK>; 51 clock-mult = <1>; 52 clock-div = <2>; 53 }; 54 55 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 56 compatible = "fixed-factor-clock"; 57 #clock-cells = <0>; 58 59 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 60 clock-mult = <1>; 61 clock-div = <2>; 62 }; 63 64 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 65 compatible = "fixed-clock"; 66 #clock-cells = <0>; 67 }; 68 }; 69 70 cpus { 71 #address-cells = <2>; 72 #size-cells = <0>; 73 74 CPU0: cpu@0 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a520"; 77 reg = <0 0>; 78 79 clocks = <&cpufreq_hw 0>; 80 81 power-domains = <&CPU_PD0>; 82 power-domain-names = "psci"; 83 84 enable-method = "psci"; 85 next-level-cache = <&L2_0>; 86 capacity-dmips-mhz = <1024>; 87 dynamic-power-coefficient = <100>; 88 89 qcom,freq-domain = <&cpufreq_hw 0>; 90 91 #cooling-cells = <2>; 92 93 L2_0: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 next-level-cache = <&L3_0>; 98 99 L3_0: l3-cache { 100 compatible = "cache"; 101 cache-level = <3>; 102 cache-unified; 103 }; 104 }; 105 }; 106 107 CPU1: cpu@100 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a520"; 110 reg = <0 0x100>; 111 112 clocks = <&cpufreq_hw 0>; 113 114 power-domains = <&CPU_PD1>; 115 power-domain-names = "psci"; 116 117 enable-method = "psci"; 118 next-level-cache = <&L2_0>; 119 capacity-dmips-mhz = <1024>; 120 dynamic-power-coefficient = <100>; 121 122 qcom,freq-domain = <&cpufreq_hw 0>; 123 124 #cooling-cells = <2>; 125 }; 126 127 CPU2: cpu@200 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a720"; 130 reg = <0 0x200>; 131 132 clocks = <&cpufreq_hw 3>; 133 134 power-domains = <&CPU_PD2>; 135 power-domain-names = "psci"; 136 137 enable-method = "psci"; 138 next-level-cache = <&L2_200>; 139 capacity-dmips-mhz = <1792>; 140 dynamic-power-coefficient = <238>; 141 142 qcom,freq-domain = <&cpufreq_hw 3>; 143 144 #cooling-cells = <2>; 145 146 L2_200: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU3: cpu@300 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a720"; 157 reg = <0 0x300>; 158 159 clocks = <&cpufreq_hw 3>; 160 161 power-domains = <&CPU_PD3>; 162 power-domain-names = "psci"; 163 164 enable-method = "psci"; 165 next-level-cache = <&L2_200>; 166 capacity-dmips-mhz = <1792>; 167 dynamic-power-coefficient = <238>; 168 169 qcom,freq-domain = <&cpufreq_hw 3>; 170 171 #cooling-cells = <2>; 172 }; 173 174 CPU4: cpu@400 { 175 device_type = "cpu"; 176 compatible = "arm,cortex-a720"; 177 reg = <0 0x400>; 178 179 clocks = <&cpufreq_hw 3>; 180 181 power-domains = <&CPU_PD4>; 182 power-domain-names = "psci"; 183 184 enable-method = "psci"; 185 next-level-cache = <&L2_400>; 186 capacity-dmips-mhz = <1792>; 187 dynamic-power-coefficient = <238>; 188 189 qcom,freq-domain = <&cpufreq_hw 3>; 190 191 #cooling-cells = <2>; 192 193 L2_400: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 next-level-cache = <&L3_0>; 198 }; 199 }; 200 201 CPU5: cpu@500 { 202 device_type = "cpu"; 203 compatible = "arm,cortex-a720"; 204 reg = <0 0x500>; 205 206 clocks = <&cpufreq_hw 1>; 207 208 power-domains = <&CPU_PD5>; 209 power-domain-names = "psci"; 210 211 enable-method = "psci"; 212 next-level-cache = <&L2_500>; 213 capacity-dmips-mhz = <1792>; 214 dynamic-power-coefficient = <238>; 215 216 qcom,freq-domain = <&cpufreq_hw 1>; 217 218 #cooling-cells = <2>; 219 220 L2_500: l2-cache { 221 compatible = "cache"; 222 cache-level = <2>; 223 cache-unified; 224 next-level-cache = <&L3_0>; 225 }; 226 }; 227 228 CPU6: cpu@600 { 229 device_type = "cpu"; 230 compatible = "arm,cortex-a720"; 231 reg = <0 0x600>; 232 233 clocks = <&cpufreq_hw 1>; 234 235 power-domains = <&CPU_PD6>; 236 power-domain-names = "psci"; 237 238 enable-method = "psci"; 239 next-level-cache = <&L2_600>; 240 capacity-dmips-mhz = <1792>; 241 dynamic-power-coefficient = <238>; 242 243 qcom,freq-domain = <&cpufreq_hw 1>; 244 245 #cooling-cells = <2>; 246 247 L2_600: l2-cache { 248 compatible = "cache"; 249 cache-level = <2>; 250 cache-unified; 251 next-level-cache = <&L3_0>; 252 }; 253 }; 254 255 CPU7: cpu@700 { 256 device_type = "cpu"; 257 compatible = "arm,cortex-x4"; 258 reg = <0 0x700>; 259 260 clocks = <&cpufreq_hw 2>; 261 262 power-domains = <&CPU_PD7>; 263 power-domain-names = "psci"; 264 265 enable-method = "psci"; 266 next-level-cache = <&L2_700>; 267 capacity-dmips-mhz = <1894>; 268 dynamic-power-coefficient = <588>; 269 270 qcom,freq-domain = <&cpufreq_hw 2>; 271 272 #cooling-cells = <2>; 273 274 L2_700: l2-cache { 275 compatible = "cache"; 276 cache-level = <2>; 277 cache-unified; 278 next-level-cache = <&L3_0>; 279 }; 280 }; 281 282 cpu-map { 283 cluster0 { 284 core0 { 285 cpu = <&CPU0>; 286 }; 287 288 core1 { 289 cpu = <&CPU1>; 290 }; 291 292 core2 { 293 cpu = <&CPU2>; 294 }; 295 296 core3 { 297 cpu = <&CPU3>; 298 }; 299 300 core4 { 301 cpu = <&CPU4>; 302 }; 303 304 core5 { 305 cpu = <&CPU5>; 306 }; 307 308 core6 { 309 cpu = <&CPU6>; 310 }; 311 312 core7 { 313 cpu = <&CPU7>; 314 }; 315 }; 316 }; 317 318 idle-states { 319 entry-method = "psci"; 320 321 SILVER_CPU_SLEEP_0: cpu-sleep-0-0 { 322 compatible = "arm,idle-state"; 323 idle-state-name = "silver-rail-power-collapse"; 324 arm,psci-suspend-param = <0x40000004>; 325 entry-latency-us = <550>; 326 exit-latency-us = <750>; 327 min-residency-us = <6700>; 328 local-timer-stop; 329 }; 330 331 GOLD_CPU_SLEEP_0: cpu-sleep-1-0 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "gold-rail-power-collapse"; 334 arm,psci-suspend-param = <0x40000004>; 335 entry-latency-us = <600>; 336 exit-latency-us = <1300>; 337 min-residency-us = <8136>; 338 local-timer-stop; 339 }; 340 341 GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "gold-plus-rail-power-collapse"; 344 arm,psci-suspend-param = <0x40000004>; 345 entry-latency-us = <500>; 346 exit-latency-us = <1350>; 347 min-residency-us = <7480>; 348 local-timer-stop; 349 }; 350 }; 351 352 domain-idle-states { 353 CLUSTER_SLEEP_0: cluster-sleep-0 { 354 compatible = "domain-idle-state"; 355 arm,psci-suspend-param = <0x41000044>; 356 entry-latency-us = <750>; 357 exit-latency-us = <2350>; 358 min-residency-us = <9144>; 359 }; 360 361 CLUSTER_SLEEP_1: cluster-sleep-1 { 362 compatible = "domain-idle-state"; 363 arm,psci-suspend-param = <0x4100c344>; 364 entry-latency-us = <2800>; 365 exit-latency-us = <4400>; 366 min-residency-us = <10150>; 367 }; 368 }; 369 }; 370 371 firmware { 372 scm: scm { 373 compatible = "qcom,scm-sm8650", "qcom,scm"; 374 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 375 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 376 }; 377 }; 378 379 clk_virt: interconnect-0 { 380 compatible = "qcom,sm8650-clk-virt"; 381 #interconnect-cells = <2>; 382 qcom,bcm-voters = <&apps_bcm_voter>; 383 }; 384 385 mc_virt: interconnect-1 { 386 compatible = "qcom,sm8650-mc-virt"; 387 #interconnect-cells = <2>; 388 qcom,bcm-voters = <&apps_bcm_voter>; 389 }; 390 391 memory@a0000000 { 392 device_type = "memory"; 393 /* We expect the bootloader to fill in the size */ 394 reg = <0 0xa0000000 0 0>; 395 }; 396 397 pmu { 398 compatible = "arm,armv8-pmuv3"; 399 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 400 }; 401 402 psci { 403 compatible = "arm,psci-1.0"; 404 method = "smc"; 405 406 CPU_PD0: power-domain-cpu0 { 407 #power-domain-cells = <0>; 408 power-domains = <&CLUSTER_PD>; 409 domain-idle-states = <&SILVER_CPU_SLEEP_0>; 410 }; 411 412 CPU_PD1: power-domain-cpu1 { 413 #power-domain-cells = <0>; 414 power-domains = <&CLUSTER_PD>; 415 domain-idle-states = <&SILVER_CPU_SLEEP_0>; 416 }; 417 418 CPU_PD2: power-domain-cpu2 { 419 #power-domain-cells = <0>; 420 power-domains = <&CLUSTER_PD>; 421 domain-idle-states = <&SILVER_CPU_SLEEP_0>; 422 }; 423 424 CPU_PD3: power-domain-cpu3 { 425 #power-domain-cells = <0>; 426 power-domains = <&CLUSTER_PD>; 427 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 428 }; 429 430 CPU_PD4: power-domain-cpu4 { 431 #power-domain-cells = <0>; 432 power-domains = <&CLUSTER_PD>; 433 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 434 }; 435 436 CPU_PD5: power-domain-cpu5 { 437 #power-domain-cells = <0>; 438 power-domains = <&CLUSTER_PD>; 439 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 440 }; 441 442 CPU_PD6: power-domain-cpu6 { 443 #power-domain-cells = <0>; 444 power-domains = <&CLUSTER_PD>; 445 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 446 }; 447 448 CPU_PD7: power-domain-cpu7 { 449 #power-domain-cells = <0>; 450 power-domains = <&CLUSTER_PD>; 451 domain-idle-states = <&GOLD_PLUS_CPU_SLEEP_0>; 452 }; 453 454 CLUSTER_PD: power-domain-cluster { 455 #power-domain-cells = <0>; 456 domain-idle-states = <&CLUSTER_SLEEP_0>, 457 <&CLUSTER_SLEEP_1>; 458 }; 459 }; 460 461 reserved_memory: reserved-memory { 462 #address-cells = <2>; 463 #size-cells = <2>; 464 ranges; 465 466 hyp_mem: hyp@80000000 { 467 reg = <0 0x80000000 0 0xe00000>; 468 no-map; 469 }; 470 471 cpusys_vm_mem: cpusys-vm@80e00000 { 472 reg = <0 0x80e00000 0 0x400000>; 473 no-map; 474 }; 475 476 /* Merged xbl_dtlog, xbl_ramdump and aop_image regions */ 477 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 { 478 reg = <0 0x81a00000 0 0x260000>; 479 no-map; 480 }; 481 482 aop_cmd_db_mem: aop-cmd-db@81c60000 { 483 compatible = "qcom,cmd-db"; 484 reg = <0 0x81c60000 0 0x20000>; 485 no-map; 486 }; 487 488 /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ 489 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 490 reg = <0 0x81c80000 0 0x74000>; 491 no-map; 492 }; 493 494 /* Secdata region can be reused by apps */ 495 496 smem: smem@81d00000 { 497 compatible = "qcom,smem"; 498 reg = <0 0x81d00000 0 0x200000>; 499 hwlocks = <&tcsr_mutex 3>; 500 no-map; 501 }; 502 503 adsp_mhi_mem: adsp-mhi@81f00000 { 504 reg = <0 0x81f00000 0 0x20000>; 505 no-map; 506 }; 507 508 pvmfw_mem: pvmfw@824a0000 { 509 reg = <0 0x824a0000 0 0x100000>; 510 no-map; 511 }; 512 513 global_sync_mem: global-sync@82600000 { 514 reg = <0 0x82600000 0 0x100000>; 515 no-map; 516 }; 517 518 tz_stat_mem: tz-stat@82700000 { 519 reg = <0 0x82700000 0 0x100000>; 520 no-map; 521 }; 522 523 qdss_mem: qdss@82800000 { 524 reg = <0 0x82800000 0 0x2000000>; 525 no-map; 526 }; 527 528 qlink_logging_mem: qlink-logging@84800000 { 529 reg = <0 0x84800000 0 0x200000>; 530 no-map; 531 }; 532 533 mpss_dsm_mem: mpss-dsm@86b00000 { 534 reg = <0 0x86b00000 0 0x4900000>; 535 no-map; 536 }; 537 538 mpss_dsm_mem_2: mpss-dsm-2@8b400000 { 539 reg = <0 0x8b400000 0 0x800000>; 540 no-map; 541 }; 542 543 mpss_mem: mpss@8bc00000 { 544 reg = <0 0x8bc00000 0 0xf400000>; 545 no-map; 546 }; 547 548 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { 549 reg = <0 0x9b000000 0 0x80000>; 550 no-map; 551 }; 552 553 ipa_fw_mem: ipa-fw@9b080000 { 554 reg = <0 0x9b080000 0 0x10000>; 555 no-map; 556 }; 557 558 ipa_gsi_mem: ipa-gsi@9b090000 { 559 reg = <0 0x9b090000 0 0xa000>; 560 no-map; 561 }; 562 563 gpu_micro_code_mem: gpu-micro-code@9b09a000 { 564 reg = <0 0x9b09a000 0 0x2000>; 565 no-map; 566 }; 567 568 spss_region_mem: spss@9b0a0000 { 569 reg = <0 0x9b0a0000 0 0x1e0000>; 570 no-map; 571 }; 572 573 /* First part of the "SPU secure shared memory" region */ 574 spu_tz_shared_mem: spu-tz-shared@9b280000 { 575 reg = <0 0x9b280000 0 0x60000>; 576 no-map; 577 }; 578 579 /* Second part of the "SPU secure shared memory" region */ 580 spu_modem_shared_mem: spu-modem-shared@9b2e0000 { 581 reg = <0 0x9b2e0000 0 0x20000>; 582 no-map; 583 }; 584 585 camera_mem: camera@9b300000 { 586 reg = <0 0x9b300000 0 0x800000>; 587 no-map; 588 }; 589 590 video_mem: video@9bb00000 { 591 reg = <0 0x9bb00000 0 0x800000>; 592 no-map; 593 }; 594 595 cvp_mem: cvp@9c300000 { 596 reg = <0 0x9c300000 0 0x700000>; 597 no-map; 598 }; 599 600 cdsp_mem: cdsp@9ca00000 { 601 reg = <0 0x9ca00000 0 0x1400000>; 602 no-map; 603 }; 604 605 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 { 606 reg = <0 0x9de00000 0 0x80000>; 607 no-map; 608 }; 609 610 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 { 611 reg = <0 0x9de80000 0 0x80000>; 612 no-map; 613 }; 614 615 adspslpi_mem: adspslpi@9df00000 { 616 reg = <0 0x9df00000 0 0x4080000>; 617 no-map; 618 }; 619 620 rmtfs_mem: rmtfs@d7c00000 { 621 compatible = "qcom,rmtfs-mem"; 622 reg = <0 0xd7c00000 0 0x400000>; 623 no-map; 624 625 qcom,client-id = <1>; 626 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 627 }; 628 629 /* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */ 630 tz_merged_mem: tz-merged@d8000000 { 631 reg = <0 0xd8000000 0 0x800000>; 632 no-map; 633 }; 634 635 hwfence_shbuf: hwfence-shbuf@e6440000 { 636 reg = <0 0xe6440000 0 0x2dd000>; 637 no-map; 638 }; 639 640 trust_ui_vm_mem: trust-ui-vm@f3800000 { 641 reg = <0 0xf3800000 0 0x4400000>; 642 no-map; 643 }; 644 645 oem_vm_mem: oem-vm@f7c00000 { 646 reg = <0 0xf7c00000 0 0x4c00000>; 647 no-map; 648 }; 649 650 llcc_lpi_mem: llcc-lpi@ff800000 { 651 reg = <0 0xff800000 0 0x600000>; 652 no-map; 653 }; 654 }; 655 656 smp2p-adsp { 657 compatible = "qcom,smp2p"; 658 659 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 660 IPCC_MPROC_SIGNAL_SMP2P 661 IRQ_TYPE_EDGE_RISING>; 662 663 mboxes = <&ipcc IPCC_CLIENT_LPASS 664 IPCC_MPROC_SIGNAL_SMP2P>; 665 666 qcom,smem = <443>, <429>; 667 qcom,local-pid = <0>; 668 qcom,remote-pid = <2>; 669 670 smp2p_adsp_out: master-kernel { 671 qcom,entry-name = "master-kernel"; 672 #qcom,smem-state-cells = <1>; 673 }; 674 675 smp2p_adsp_in: slave-kernel { 676 qcom,entry-name = "slave-kernel"; 677 interrupt-controller; 678 #interrupt-cells = <2>; 679 }; 680 }; 681 682 smp2p-cdsp { 683 compatible = "qcom,smp2p"; 684 685 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 686 IPCC_MPROC_SIGNAL_SMP2P 687 IRQ_TYPE_EDGE_RISING>; 688 689 mboxes = <&ipcc IPCC_CLIENT_CDSP 690 IPCC_MPROC_SIGNAL_SMP2P>; 691 692 qcom,smem = <94>, <432>; 693 qcom,local-pid = <0>; 694 qcom,remote-pid = <5>; 695 696 smp2p_cdsp_out: master-kernel { 697 qcom,entry-name = "master-kernel"; 698 #qcom,smem-state-cells = <1>; 699 }; 700 701 smp2p_cdsp_in: slave-kernel { 702 qcom,entry-name = "slave-kernel"; 703 interrupt-controller; 704 #interrupt-cells = <2>; 705 }; 706 }; 707 708 smp2p-modem { 709 compatible = "qcom,smp2p"; 710 711 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 712 IPCC_MPROC_SIGNAL_SMP2P 713 IRQ_TYPE_EDGE_RISING>; 714 715 mboxes = <&ipcc IPCC_CLIENT_MPSS 716 IPCC_MPROC_SIGNAL_SMP2P>; 717 718 qcom,smem = <435>, <428>; 719 qcom,local-pid = <0>; 720 qcom,remote-pid = <1>; 721 722 smp2p_modem_out: master-kernel { 723 qcom,entry-name = "master-kernel"; 724 #qcom,smem-state-cells = <1>; 725 }; 726 727 smp2p_modem_in: slave-kernel { 728 qcom,entry-name = "slave-kernel"; 729 interrupt-controller; 730 #interrupt-cells = <2>; 731 }; 732 733 ipa_smp2p_out: ipa-ap-to-modem { 734 qcom,entry-name = "ipa"; 735 #qcom,smem-state-cells = <1>; 736 }; 737 738 ipa_smp2p_in: ipa-modem-to-ap { 739 qcom,entry-name = "ipa"; 740 interrupt-controller; 741 #interrupt-cells = <2>; 742 }; 743 }; 744 745 soc: soc@0 { 746 compatible = "simple-bus"; 747 748 #address-cells = <2>; 749 #size-cells = <2>; 750 dma-ranges = <0 0 0 0 0x10 0>; 751 ranges = <0 0 0 0 0x10 0>; 752 753 gcc: clock-controller@100000 { 754 compatible = "qcom,sm8650-gcc"; 755 reg = <0 0x00100000 0 0x1f4200>; 756 757 clocks = <&bi_tcxo_div2>, 758 <&bi_tcxo_ao_div2>, 759 <&sleep_clk>, 760 <&pcie0_phy>, 761 <&pcie1_phy>, 762 <&pcie_1_phy_aux_clk>, 763 <&ufs_mem_phy 0>, 764 <&ufs_mem_phy 1>, 765 <&ufs_mem_phy 2>, 766 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 767 768 #clock-cells = <1>; 769 #reset-cells = <1>; 770 #power-domain-cells = <1>; 771 }; 772 773 ipcc: mailbox@406000 { 774 compatible = "qcom,sm8650-ipcc", "qcom,ipcc"; 775 reg = <0 0x00406000 0 0x1000>; 776 777 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 778 interrupt-controller; 779 #interrupt-cells = <3>; 780 781 #mbox-cells = <2>; 782 }; 783 784 gpi_dma2: dma-controller@800000 { 785 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 786 reg = <0 0x00800000 0 0x60000>; 787 788 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 800 801 dma-channels = <12>; 802 dma-channel-mask = <0x3f>; 803 #dma-cells = <3>; 804 805 iommus = <&apps_smmu 0x436 0>; 806 807 dma-coherent; 808 809 status = "disabled"; 810 }; 811 812 qupv3_id_1: geniqup@8c0000 { 813 compatible = "qcom,geni-se-qup"; 814 reg = <0 0x008c0000 0 0x2000>; 815 816 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 817 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 818 clock-names = "m-ahb", 819 "s-ahb"; 820 821 iommus = <&apps_smmu 0x423 0>; 822 823 dma-coherent; 824 825 #address-cells = <2>; 826 #size-cells = <2>; 827 ranges; 828 829 status = "disabled"; 830 831 i2c8: i2c@880000 { 832 compatible = "qcom,geni-i2c"; 833 reg = <0 0x00880000 0 0x4000>; 834 835 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 836 837 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 838 clock-names = "se"; 839 840 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 841 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 842 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 843 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 844 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 845 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 846 interconnect-names = "qup-core", 847 "qup-config", 848 "qup-memory"; 849 850 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 851 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 852 dma-names = "tx", 853 "rx"; 854 855 pinctrl-0 = <&qup_i2c8_data_clk>; 856 pinctrl-names = "default"; 857 858 #address-cells = <1>; 859 #size-cells = <0>; 860 861 status = "disabled"; 862 }; 863 864 spi8: spi@880000 { 865 compatible = "qcom,geni-spi"; 866 reg = <0 0x00880000 0 0x4000>; 867 868 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 869 870 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 871 clock-names = "se"; 872 873 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 874 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 875 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 876 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 877 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 878 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 879 interconnect-names = "qup-core", 880 "qup-config", 881 "qup-memory"; 882 883 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 884 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 885 dma-names = "tx", 886 "rx"; 887 888 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 889 pinctrl-names = "default"; 890 891 #address-cells = <1>; 892 #size-cells = <0>; 893 894 status = "disabled"; 895 }; 896 897 i2c9: i2c@884000 { 898 compatible = "qcom,geni-i2c"; 899 reg = <0 0x00884000 0 0x4000>; 900 901 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 902 903 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 904 clock-names = "se"; 905 906 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 907 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 908 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 909 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 910 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 911 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 912 interconnect-names = "qup-core", 913 "qup-config", 914 "qup-memory"; 915 916 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 917 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 918 dma-names = "tx", 919 "rx"; 920 921 pinctrl-0 = <&qup_i2c9_data_clk>; 922 pinctrl-names = "default"; 923 924 #address-cells = <1>; 925 #size-cells = <0>; 926 927 status = "disabled"; 928 }; 929 930 spi9: spi@884000 { 931 compatible = "qcom,geni-spi"; 932 reg = <0 0x00884000 0 0x4000>; 933 934 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 935 936 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 937 clock-names = "se"; 938 939 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 940 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 941 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 942 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 943 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 944 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 945 interconnect-names = "qup-core", 946 "qup-config", 947 "qup-memory"; 948 949 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 950 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 951 dma-names = "tx", 952 "rx"; 953 954 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 955 pinctrl-names = "default"; 956 957 #address-cells = <1>; 958 #size-cells = <0>; 959 960 status = "disabled"; 961 }; 962 963 i2c10: i2c@888000 { 964 compatible = "qcom,geni-i2c"; 965 reg = <0 0x00888000 0 0x4000>; 966 967 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 968 969 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 970 clock-names = "se"; 971 972 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 973 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 974 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 975 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 976 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 977 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 978 interconnect-names = "qup-core", 979 "qup-config", 980 "qup-memory"; 981 982 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 983 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 984 dma-names = "tx", 985 "rx"; 986 987 pinctrl-0 = <&qup_i2c10_data_clk>; 988 pinctrl-names = "default"; 989 990 #address-cells = <1>; 991 #size-cells = <0>; 992 993 status = "disabled"; 994 }; 995 996 spi10: spi@888000 { 997 compatible = "qcom,geni-spi"; 998 reg = <0 0x00888000 0 0x4000>; 999 1000 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1001 1002 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1003 clock-names = "se"; 1004 1005 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1006 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1007 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1008 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1009 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1010 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1011 interconnect-names = "qup-core", 1012 "qup-config", 1013 "qup-memory"; 1014 1015 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1016 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1017 dma-names = "tx", 1018 "rx"; 1019 1020 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1021 pinctrl-names = "default"; 1022 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 1026 status = "disabled"; 1027 }; 1028 1029 i2c11: i2c@88c000 { 1030 compatible = "qcom,geni-i2c"; 1031 reg = <0 0x0088c000 0 0x4000>; 1032 1033 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1034 1035 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1036 clock-names = "se"; 1037 1038 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1039 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1040 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1041 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1042 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1043 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1044 interconnect-names = "qup-core", 1045 "qup-config", 1046 "qup-memory"; 1047 1048 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1049 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1050 dma-names = "tx", 1051 "rx"; 1052 1053 pinctrl-0 = <&qup_i2c11_data_clk>; 1054 pinctrl-names = "default"; 1055 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 1059 status = "disabled"; 1060 }; 1061 1062 spi11: spi@88c000 { 1063 compatible = "qcom,geni-spi"; 1064 reg = <0 0x0088c000 0 0x4000>; 1065 1066 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1067 1068 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1069 clock-names = "se"; 1070 1071 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1072 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1073 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1074 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1075 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1076 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1077 interconnect-names = "qup-core", 1078 "qup-config", 1079 "qup-memory"; 1080 1081 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1082 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1083 dma-names = "tx", 1084 "rx"; 1085 1086 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1087 pinctrl-names = "default"; 1088 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 1092 status = "disabled"; 1093 }; 1094 1095 i2c12: i2c@890000 { 1096 compatible = "qcom,geni-i2c"; 1097 reg = <0 0x00890000 0 0x4000>; 1098 1099 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1100 1101 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1102 clock-names = "se"; 1103 1104 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1105 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1106 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1107 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1108 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1109 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1110 interconnect-names = "qup-core", 1111 "qup-config", 1112 "qup-memory"; 1113 1114 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1115 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1116 dma-names = "tx", 1117 "rx"; 1118 1119 pinctrl-0 = <&qup_i2c12_data_clk>; 1120 pinctrl-names = "default"; 1121 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 1125 status = "disabled"; 1126 }; 1127 1128 spi12: spi@890000 { 1129 compatible = "qcom,geni-spi"; 1130 reg = <0 0x00890000 0 0x4000>; 1131 1132 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1133 1134 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1135 clock-names = "se"; 1136 1137 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1138 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1139 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1140 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1141 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1142 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1143 interconnect-names = "qup-core", 1144 "qup-config", 1145 "qup-memory"; 1146 1147 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1148 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1149 dma-names = "tx", 1150 "rx"; 1151 1152 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1153 pinctrl-names = "default"; 1154 1155 #address-cells = <1>; 1156 #size-cells = <0>; 1157 1158 status = "disabled"; 1159 }; 1160 1161 i2c13: i2c@894000 { 1162 compatible = "qcom,geni-i2c"; 1163 reg = <0 0x00894000 0 0x4000>; 1164 1165 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1166 1167 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1168 clock-names = "se"; 1169 1170 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1171 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1172 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1173 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1174 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1176 interconnect-names = "qup-core", 1177 "qup-config", 1178 "qup-memory"; 1179 1180 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1181 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1182 dma-names = "tx", 1183 "rx"; 1184 1185 pinctrl-0 = <&qup_i2c13_data_clk>; 1186 pinctrl-names = "default"; 1187 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 1191 status = "disabled"; 1192 }; 1193 1194 spi13: spi@894000 { 1195 compatible = "qcom,geni-spi"; 1196 reg = <0 0x00894000 0 0x4000>; 1197 1198 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1199 1200 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1201 clock-names = "se"; 1202 1203 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1204 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1205 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1206 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1207 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1208 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1209 interconnect-names = "qup-core", 1210 "qup-config", 1211 "qup-memory"; 1212 1213 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1214 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1215 dma-names = "tx", 1216 "rx"; 1217 1218 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1219 pinctrl-names = "default"; 1220 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 1224 status = "disabled"; 1225 }; 1226 1227 uart14: serial@898000 { 1228 compatible = "qcom,geni-uart"; 1229 reg = <0 0x00898000 0 0x4000>; 1230 1231 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1232 1233 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1234 clock-names = "se"; 1235 1236 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1237 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1238 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1239 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1240 interconnect-names = "qup-core", 1241 "qup-config"; 1242 1243 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1244 pinctrl-names = "default"; 1245 1246 status = "disabled"; 1247 }; 1248 1249 uart15: serial@89c000 { 1250 compatible = "qcom,geni-debug-uart"; 1251 reg = <0 0x0089c000 0 0x4000>; 1252 1253 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1254 1255 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1256 clock-names = "se"; 1257 1258 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1259 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1260 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1261 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1262 interconnect-names = "qup-core", 1263 "qup-config"; 1264 1265 pinctrl-0 = <&qup_uart15_default>; 1266 pinctrl-names = "default"; 1267 1268 status = "disabled"; 1269 }; 1270 }; 1271 1272 i2c_master_hub_0: geniqup@9c0000 { 1273 compatible = "qcom,geni-se-i2c-master-hub"; 1274 reg = <0 0x009c0000 0 0x2000>; 1275 1276 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1277 clock-names = "s-ahb"; 1278 1279 #address-cells = <2>; 1280 #size-cells = <2>; 1281 ranges; 1282 1283 status = "disabled"; 1284 1285 i2c_hub_0: i2c@980000 { 1286 compatible = "qcom,geni-i2c-master-hub"; 1287 reg = <0 0x00980000 0 0x4000>; 1288 1289 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1290 1291 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1292 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1293 clock-names = "se", 1294 "core"; 1295 1296 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1297 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1298 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1299 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1300 interconnect-names = "qup-core", 1301 "qup-config"; 1302 1303 pinctrl-0 = <&hub_i2c0_data_clk>; 1304 pinctrl-names = "default"; 1305 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 1309 status = "disabled"; 1310 }; 1311 1312 i2c_hub_1: i2c@984000 { 1313 compatible = "qcom,geni-i2c-master-hub"; 1314 reg = <0 0x00984000 0 0x4000>; 1315 1316 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1317 1318 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1319 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1320 clock-names = "se", 1321 "core"; 1322 1323 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1324 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1325 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1326 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1327 interconnect-names = "qup-core", 1328 "qup-config"; 1329 1330 pinctrl-0 = <&hub_i2c1_data_clk>; 1331 pinctrl-names = "default"; 1332 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 1336 status = "disabled"; 1337 }; 1338 1339 i2c_hub_2: i2c@988000 { 1340 compatible = "qcom,geni-i2c-master-hub"; 1341 reg = <0 0x00988000 0 0x4000>; 1342 1343 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1344 1345 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1346 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1347 clock-names = "se", 1348 "core"; 1349 1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1351 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1352 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1353 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1354 interconnect-names = "qup-core", 1355 "qup-config"; 1356 1357 pinctrl-0 = <&hub_i2c2_data_clk>; 1358 pinctrl-names = "default"; 1359 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 1363 status = "disabled"; 1364 }; 1365 1366 i2c_hub_3: i2c@98c000 { 1367 compatible = "qcom,geni-i2c-master-hub"; 1368 reg = <0 0x0098c000 0 0x4000>; 1369 1370 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1371 1372 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1373 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1374 clock-names = "se", 1375 "core"; 1376 1377 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1378 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1379 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1380 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1381 interconnect-names = "qup-core", 1382 "qup-config"; 1383 1384 pinctrl-0 = <&hub_i2c3_data_clk>; 1385 pinctrl-names = "default"; 1386 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 1390 status = "disabled"; 1391 }; 1392 1393 i2c_hub_4: i2c@990000 { 1394 compatible = "qcom,geni-i2c-master-hub"; 1395 reg = <0 0x00990000 0 0x4000>; 1396 1397 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1398 1399 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1400 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1401 clock-names = "se", 1402 "core"; 1403 1404 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1405 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1406 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1407 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1408 interconnect-names = "qup-core", 1409 "qup-config"; 1410 1411 pinctrl-0 = <&hub_i2c4_data_clk>; 1412 pinctrl-names = "default"; 1413 1414 #address-cells = <1>; 1415 #size-cells = <0>; 1416 1417 status = "disabled"; 1418 }; 1419 1420 i2c_hub_5: i2c@994000 { 1421 compatible = "qcom,geni-i2c-master-hub"; 1422 reg = <0 0x00994000 0 0x4000>; 1423 1424 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1425 1426 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1427 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1428 clock-names = "se", 1429 "core"; 1430 1431 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1432 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1433 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1434 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1435 interconnect-names = "qup-core", 1436 "qup-config"; 1437 1438 pinctrl-0 = <&hub_i2c5_data_clk>; 1439 pinctrl-names = "default"; 1440 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 1444 status = "disabled"; 1445 }; 1446 1447 i2c_hub_6: i2c@998000 { 1448 compatible = "qcom,geni-i2c-master-hub"; 1449 reg = <0 0x00998000 0 0x4000>; 1450 1451 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1452 1453 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1454 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1455 clock-names = "se", 1456 "core"; 1457 1458 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1459 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1460 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1461 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1462 interconnect-names = "qup-core", 1463 "qup-config"; 1464 1465 pinctrl-0 = <&hub_i2c6_data_clk>; 1466 pinctrl-names = "default"; 1467 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 1471 status = "disabled"; 1472 }; 1473 1474 i2c_hub_7: i2c@99c000 { 1475 compatible = "qcom,geni-i2c-master-hub"; 1476 reg = <0 0x0099c000 0 0x4000>; 1477 1478 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1479 1480 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1481 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1482 clock-names = "se", 1483 "core"; 1484 1485 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1486 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1487 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1488 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1489 interconnect-names = "qup-core", 1490 "qup-config"; 1491 1492 pinctrl-0 = <&hub_i2c7_data_clk>; 1493 pinctrl-names = "default"; 1494 1495 #address-cells = <1>; 1496 #size-cells = <0>; 1497 1498 status = "disabled"; 1499 }; 1500 1501 i2c_hub_8: i2c@9a0000 { 1502 compatible = "qcom,geni-i2c-master-hub"; 1503 reg = <0 0x009a0000 0 0x4000>; 1504 1505 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1506 1507 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1508 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1509 clock-names = "se", 1510 "core"; 1511 1512 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1513 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1514 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1515 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1516 interconnect-names = "qup-core", 1517 "qup-config"; 1518 1519 pinctrl-0 = <&hub_i2c8_data_clk>; 1520 pinctrl-names = "default"; 1521 1522 #address-cells = <1>; 1523 #size-cells = <0>; 1524 1525 status = "disabled"; 1526 }; 1527 1528 i2c_hub_9: i2c@9a4000 { 1529 compatible = "qcom,geni-i2c-master-hub"; 1530 reg = <0 0x009a4000 0 0x4000>; 1531 1532 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1533 1534 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1535 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1536 clock-names = "se", 1537 "core"; 1538 1539 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1540 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1541 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1542 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1543 interconnect-names = "qup-core", 1544 "qup-config"; 1545 1546 pinctrl-0 = <&hub_i2c9_data_clk>; 1547 pinctrl-names = "default"; 1548 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 1552 status = "disabled"; 1553 }; 1554 }; 1555 1556 gpi_dma1: dma-controller@a00000 { 1557 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 1558 reg = <0 0x00a00000 0 0x60000>; 1559 1560 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1572 1573 dma-channels = <12>; 1574 dma-channel-mask = <0xc>; 1575 #dma-cells = <3>; 1576 1577 iommus = <&apps_smmu 0xb6 0>; 1578 dma-coherent; 1579 1580 status = "disabled"; 1581 }; 1582 1583 qupv3_id_0: geniqup@ac0000 { 1584 compatible = "qcom,geni-se-qup"; 1585 reg = <0 0x00ac0000 0 0x2000>; 1586 1587 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1588 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1589 clock-names = "m-ahb", 1590 "s-ahb"; 1591 1592 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1593 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 1594 interconnect-names = "qup-core"; 1595 1596 iommus = <&apps_smmu 0xa3 0>; 1597 1598 dma-coherent; 1599 1600 #address-cells = <2>; 1601 #size-cells = <2>; 1602 ranges; 1603 1604 status = "disabled"; 1605 1606 i2c0: i2c@a80000 { 1607 compatible = "qcom,geni-i2c"; 1608 reg = <0 0x00a80000 0 0x4000>; 1609 1610 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1611 1612 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1613 clock-names = "se"; 1614 1615 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1616 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1617 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1618 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1619 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1620 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1621 interconnect-names = "qup-core", 1622 "qup-config", 1623 "qup-memory"; 1624 1625 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1626 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1627 dma-names = "tx", 1628 "rx"; 1629 1630 pinctrl-0 = <&qup_i2c0_data_clk>; 1631 pinctrl-names = "default"; 1632 1633 #address-cells = <1>; 1634 #size-cells = <0>; 1635 1636 status = "disabled"; 1637 }; 1638 1639 spi0: spi@a80000 { 1640 compatible = "qcom,geni-spi"; 1641 reg = <0 0x00a80000 0 0x4000>; 1642 1643 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1644 1645 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1646 clock-names = "se"; 1647 1648 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1649 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1650 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1651 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1652 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1653 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1654 interconnect-names = "qup-core", 1655 "qup-config", 1656 "qup-memory"; 1657 1658 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1659 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1660 dma-names = "tx", 1661 "rx"; 1662 1663 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1664 pinctrl-names = "default"; 1665 1666 #address-cells = <1>; 1667 #size-cells = <0>; 1668 1669 status = "disabled"; 1670 }; 1671 1672 i2c1: i2c@a84000 { 1673 compatible = "qcom,geni-i2c"; 1674 reg = <0 0x00a84000 0 0x4000>; 1675 1676 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1677 1678 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1679 clock-names = "se"; 1680 1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1682 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1683 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1684 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1685 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1686 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1687 interconnect-names = "qup-core", 1688 "qup-config", 1689 "qup-memory"; 1690 1691 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1692 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1693 dma-names = "tx", 1694 "rx"; 1695 1696 pinctrl-0 = <&qup_i2c1_data_clk>; 1697 pinctrl-names = "default"; 1698 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 1702 status = "disabled"; 1703 }; 1704 1705 spi1: spi@a84000 { 1706 compatible = "qcom,geni-spi"; 1707 reg = <0 0x00a84000 0 0x4000>; 1708 1709 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1710 1711 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1712 clock-names = "se"; 1713 1714 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1715 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1716 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1717 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1718 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1719 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1720 interconnect-names = "qup-core", 1721 "qup-config", 1722 "qup-memory"; 1723 1724 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1725 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1726 dma-names = "tx", 1727 "rx"; 1728 1729 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1730 pinctrl-names = "default"; 1731 1732 #address-cells = <1>; 1733 #size-cells = <0>; 1734 1735 status = "disabled"; 1736 }; 1737 1738 i2c2: i2c@a88000 { 1739 compatible = "qcom,geni-i2c"; 1740 reg = <0 0x00a88000 0 0x4000>; 1741 1742 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1743 1744 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1745 clock-names = "se"; 1746 1747 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1748 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1749 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1750 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1751 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1752 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1753 interconnect-names = "qup-core", 1754 "qup-config", 1755 "qup-memory"; 1756 1757 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1758 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1759 dma-names = "tx", 1760 "rx"; 1761 1762 pinctrl-0 = <&qup_i2c2_data_clk>; 1763 pinctrl-names = "default"; 1764 1765 #address-cells = <1>; 1766 #size-cells = <0>; 1767 1768 status = "disabled"; 1769 }; 1770 1771 spi2: spi@a88000 { 1772 compatible = "qcom,geni-spi"; 1773 reg = <0 0x00a88000 0 0x4000>; 1774 1775 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1776 1777 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1778 clock-names = "se"; 1779 1780 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1781 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1782 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1783 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1784 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1785 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1786 interconnect-names = "qup-core", 1787 "qup-config", 1788 "qup-memory"; 1789 1790 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1791 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1792 dma-names = "tx", 1793 "rx"; 1794 1795 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1796 pinctrl-names = "default"; 1797 1798 #address-cells = <1>; 1799 #size-cells = <0>; 1800 1801 status = "disabled"; 1802 }; 1803 1804 i2c3: i2c@a8c000 { 1805 compatible = "qcom,geni-i2c"; 1806 reg = <0 0x00a8c000 0 0x4000>; 1807 1808 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1809 1810 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1811 clock-names = "se"; 1812 1813 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1814 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1815 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1816 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1817 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1818 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1819 interconnect-names = "qup-core", 1820 "qup-config", 1821 "qup-memory"; 1822 1823 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1824 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1825 dma-names = "tx", 1826 "rx"; 1827 1828 pinctrl-0 = <&qup_i2c3_data_clk>; 1829 pinctrl-names = "default"; 1830 1831 #address-cells = <1>; 1832 #size-cells = <0>; 1833 1834 status = "disabled"; 1835 }; 1836 1837 spi3: spi@a8c000 { 1838 compatible = "qcom,geni-spi"; 1839 reg = <0 0x00a8c000 0 0x4000>; 1840 1841 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1842 1843 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1844 clock-names = "se"; 1845 1846 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1847 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1848 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1849 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1850 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1851 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1852 interconnect-names = "qup-core", 1853 "qup-config", 1854 "qup-memory"; 1855 1856 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1857 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1858 dma-names = "tx", 1859 "rx"; 1860 1861 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1862 pinctrl-names = "default"; 1863 1864 #address-cells = <1>; 1865 #size-cells = <0>; 1866 1867 status = "disabled"; 1868 }; 1869 1870 i2c4: i2c@a90000 { 1871 compatible = "qcom,geni-i2c"; 1872 reg = <0 0x00a90000 0 0x4000>; 1873 1874 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1875 1876 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1877 clock-names = "se"; 1878 1879 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1880 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1881 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1882 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1883 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1884 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1885 interconnect-names = "qup-core", 1886 "qup-config", 1887 "qup-memory"; 1888 1889 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1890 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1891 dma-names = "tx", 1892 "rx"; 1893 1894 pinctrl-0 = <&qup_i2c4_data_clk>; 1895 pinctrl-names = "default"; 1896 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 1900 status = "disabled"; 1901 }; 1902 1903 spi4: spi@a90000 { 1904 compatible = "qcom,geni-spi"; 1905 reg = <0 0x00a90000 0 0x4000>; 1906 1907 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1908 1909 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1910 clock-names = "se"; 1911 1912 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1913 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1914 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1915 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1916 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1917 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1918 interconnect-names = "qup-core", 1919 "qup-config", 1920 "qup-memory"; 1921 1922 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1923 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1924 dma-names = "tx", 1925 "rx"; 1926 1927 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1928 pinctrl-names = "default"; 1929 1930 #address-cells = <1>; 1931 #size-cells = <0>; 1932 1933 status = "disabled"; 1934 }; 1935 1936 i2c5: i2c@a94000 { 1937 compatible = "qcom,geni-i2c"; 1938 reg = <0 0x00a94000 0 0x4000>; 1939 1940 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1941 1942 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1943 clock-names = "se"; 1944 1945 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1946 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1947 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1948 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1949 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1950 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1951 interconnect-names = "qup-core", 1952 "qup-config", 1953 "qup-memory"; 1954 1955 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1956 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1957 dma-names = "tx", 1958 "rx"; 1959 1960 pinctrl-0 = <&qup_i2c5_data_clk>; 1961 pinctrl-names = "default"; 1962 1963 #address-cells = <1>; 1964 #size-cells = <0>; 1965 1966 status = "disabled"; 1967 }; 1968 1969 spi5: spi@a94000 { 1970 compatible = "qcom,geni-spi"; 1971 reg = <0 0x00a94000 0 0x4000>; 1972 1973 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1974 1975 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1976 clock-names = "se"; 1977 1978 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1979 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1980 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1981 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1982 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1983 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1984 interconnect-names = "qup-core", 1985 "qup-config", 1986 "qup-memory"; 1987 1988 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1989 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1990 dma-names = "tx", 1991 "rx"; 1992 1993 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1994 pinctrl-names = "default"; 1995 1996 #address-cells = <1>; 1997 #size-cells = <0>; 1998 1999 status = "disabled"; 2000 }; 2001 2002 i2c6: i2c@a98000 { 2003 compatible = "qcom,geni-i2c"; 2004 reg = <0 0x00a98000 0 0x4000>; 2005 2006 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 2007 2008 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2009 clock-names = "se"; 2010 2011 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2012 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2013 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2014 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2015 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2016 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2017 interconnect-names = "qup-core", 2018 "qup-config", 2019 "qup-memory"; 2020 2021 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2022 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2023 dma-names = "tx", 2024 "rx"; 2025 2026 pinctrl-0 = <&qup_i2c6_data_clk>; 2027 pinctrl-names = "default"; 2028 2029 #address-cells = <1>; 2030 #size-cells = <0>; 2031 2032 status = "disabled"; 2033 }; 2034 2035 spi6: spi@a98000 { 2036 compatible = "qcom,geni-spi"; 2037 reg = <0 0x00a98000 0 0x4000>; 2038 2039 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 2040 2041 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2042 clock-names = "se"; 2043 2044 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2045 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2046 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2047 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2048 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2049 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2050 interconnect-names = "qup-core", 2051 "qup-config", 2052 "qup-memory"; 2053 2054 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2055 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2056 dma-names = "tx", 2057 "rx"; 2058 2059 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2060 pinctrl-names = "default"; 2061 2062 #address-cells = <1>; 2063 #size-cells = <0>; 2064 2065 status = "disabled"; 2066 }; 2067 2068 i2c7: i2c@a9c000 { 2069 compatible = "qcom,geni-i2c"; 2070 reg = <0 0x00a9c000 0 0x4000>; 2071 2072 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 2073 2074 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2075 clock-names = "se"; 2076 2077 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2078 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2079 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2080 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2081 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2082 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2083 interconnect-names = "qup-core", 2084 "qup-config", 2085 "qup-memory"; 2086 2087 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2088 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2089 dma-names = "tx", 2090 "rx"; 2091 2092 pinctrl-0 = <&qup_i2c7_data_clk>; 2093 pinctrl-names = "default"; 2094 2095 #address-cells = <1>; 2096 #size-cells = <0>; 2097 2098 status = "disabled"; 2099 }; 2100 2101 spi7: spi@a9c000 { 2102 compatible = "qcom,geni-spi"; 2103 reg = <0 0x00a9c000 0 0x4000>; 2104 2105 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 2106 2107 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2108 clock-names = "se"; 2109 2110 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2111 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2112 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2113 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2114 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2115 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2116 interconnect-names = "qup-core", 2117 "qup-config", 2118 "qup-memory"; 2119 2120 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2121 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2122 dma-names = "tx", 2123 "rx"; 2124 2125 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2126 pinctrl-names = "default"; 2127 2128 #address-cells = <1>; 2129 #size-cells = <0>; 2130 2131 status = "disabled"; 2132 }; 2133 }; 2134 2135 cnoc_main: interconnect@1500000 { 2136 compatible = "qcom,sm8650-cnoc-main"; 2137 reg = <0 0x01500000 0 0x14080>; 2138 2139 qcom,bcm-voters = <&apps_bcm_voter>; 2140 2141 #interconnect-cells = <2>; 2142 }; 2143 2144 config_noc: interconnect@1600000 { 2145 compatible = "qcom,sm8650-config-noc"; 2146 reg = <0 0x01600000 0 0x6200>; 2147 2148 qcom,bcm-voters = <&apps_bcm_voter>; 2149 2150 #interconnect-cells = <2>; 2151 }; 2152 2153 system_noc: interconnect@1680000 { 2154 compatible = "qcom,sm8650-system-noc"; 2155 reg = <0 0x01680000 0 0x1d080>; 2156 2157 qcom,bcm-voters = <&apps_bcm_voter>; 2158 2159 #interconnect-cells = <2>; 2160 }; 2161 2162 pcie_noc: interconnect@16c0000 { 2163 compatible = "qcom,sm8650-pcie-anoc"; 2164 reg = <0 0x016c0000 0 0x12200>; 2165 2166 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2167 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 2168 2169 qcom,bcm-voters = <&apps_bcm_voter>; 2170 2171 #interconnect-cells = <2>; 2172 }; 2173 2174 aggre1_noc: interconnect@16e0000 { 2175 compatible = "qcom,sm8650-aggre1-noc"; 2176 reg = <0 0x016e0000 0 0x16400>; 2177 2178 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2179 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2180 2181 qcom,bcm-voters = <&apps_bcm_voter>; 2182 2183 #interconnect-cells = <2>; 2184 }; 2185 2186 aggre2_noc: interconnect@1700000 { 2187 compatible = "qcom,sm8650-aggre2-noc"; 2188 reg = <0 0x01700000 0 0x1e400>; 2189 2190 clocks = <&rpmhcc RPMH_IPA_CLK>; 2191 2192 qcom,bcm-voters = <&apps_bcm_voter>; 2193 2194 #interconnect-cells = <2>; 2195 }; 2196 2197 mmss_noc: interconnect@1780000 { 2198 compatible = "qcom,sm8650-mmss-noc"; 2199 reg = <0 0x01780000 0 0x5b800>; 2200 2201 qcom,bcm-voters = <&apps_bcm_voter>; 2202 2203 #interconnect-cells = <2>; 2204 }; 2205 2206 rng: rng@10c3000 { 2207 compatible = "qcom,sm8650-trng", "qcom,trng"; 2208 reg = <0 0x010c3000 0 0x1000>; 2209 }; 2210 2211 pcie0: pci@1c00000 { 2212 device_type = "pci"; 2213 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 2214 reg = <0 0x01c00000 0 0x3000>, 2215 <0 0x60000000 0 0xf1d>, 2216 <0 0x60000f20 0 0xa8>, 2217 <0 0x60001000 0 0x1000>, 2218 <0 0x60100000 0 0x100000>; 2219 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2220 2221 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2223 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2228 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2229 interrupt-names = "msi0", 2230 "msi1", 2231 "msi2", 2232 "msi3", 2233 "msi4", 2234 "msi5", 2235 "msi6", 2236 "msi7"; 2237 2238 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2239 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2240 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2241 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2242 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2243 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2244 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2245 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2246 clock-names = "aux", 2247 "cfg", 2248 "bus_master", 2249 "bus_slave", 2250 "slave_q2a", 2251 "ddrss_sf_tbu", 2252 "noc_aggr", 2253 "cnoc_sf_axi"; 2254 2255 resets = <&gcc GCC_PCIE_0_BCR>; 2256 reset-names = "pci"; 2257 2258 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2259 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2260 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2261 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 2262 interconnect-names = "pcie-mem", 2263 "cpu-pcie"; 2264 2265 power-domains = <&gcc PCIE_0_GDSC>; 2266 2267 iommu-map = <0 &apps_smmu 0x1400 0x1>, 2268 <0x100 &apps_smmu 0x1401 0x1>; 2269 2270 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 2271 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 2272 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 2273 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 2274 interrupt-map-mask = <0 0 0 0x7>; 2275 #interrupt-cells = <1>; 2276 2277 msi-map = <0x0 &gic_its 0x1400 0x1>, 2278 <0x100 &gic_its 0x1401 0x1>; 2279 msi-map-mask = <0xff00>; 2280 2281 linux,pci-domain = <0>; 2282 num-lanes = <2>; 2283 bus-range = <0 0xff>; 2284 2285 phys = <&pcie0_phy>; 2286 phy-names = "pciephy"; 2287 2288 #address-cells = <3>; 2289 #size-cells = <2>; 2290 ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, 2291 <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>; 2292 2293 dma-coherent; 2294 2295 status = "disabled"; 2296 }; 2297 2298 pcie0_phy: phy@1c06000 { 2299 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy"; 2300 reg = <0 0x01c06000 0 0x2000>; 2301 2302 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2303 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2304 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 2305 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2306 <&gcc GCC_PCIE_0_PIPE_CLK>; 2307 clock-names = "aux", 2308 "cfg_ahb", 2309 "ref", 2310 "rchng", 2311 "pipe"; 2312 2313 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2314 assigned-clock-rates = <100000000>; 2315 2316 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2317 reset-names = "phy"; 2318 2319 power-domains = <&gcc PCIE_0_PHY_GDSC>; 2320 2321 #clock-cells = <0>; 2322 clock-output-names = "pcie0_pipe_clk"; 2323 2324 #phy-cells = <0>; 2325 2326 status = "disabled"; 2327 }; 2328 2329 pcie1: pci@1c08000 { 2330 device_type = "pci"; 2331 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 2332 reg = <0 0x01c08000 0 0x3000>, 2333 <0 0x40000000 0 0xf1d>, 2334 <0 0x40000f20 0 0xa8>, 2335 <0 0x40001000 0 0x1000>, 2336 <0 0x40100000 0 0x100000>; 2337 reg-names = "parf", 2338 "dbi", 2339 "elbi", 2340 "atu", 2341 "config"; 2342 2343 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2344 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2345 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2346 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2347 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2348 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2349 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2350 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2351 interrupt-names = "msi0", 2352 "msi1", 2353 "msi2", 2354 "msi3", 2355 "msi4", 2356 "msi5", 2357 "msi6", 2358 "msi7"; 2359 2360 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2361 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2362 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2363 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2364 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2365 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2366 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2367 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2368 clock-names = "aux", 2369 "cfg", 2370 "bus_master", 2371 "bus_slave", 2372 "slave_q2a", 2373 "ddrss_sf_tbu", 2374 "noc_aggr", 2375 "cnoc_sf_axi"; 2376 2377 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2378 assigned-clock-rates = <19200000>; 2379 2380 resets = <&gcc GCC_PCIE_1_BCR>, 2381 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2382 reset-names = "pci", 2383 "link_down"; 2384 2385 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2386 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2387 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2388 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; 2389 interconnect-names = "pcie-mem", 2390 "cpu-pcie"; 2391 2392 power-domains = <&gcc PCIE_1_GDSC>; 2393 2394 iommu-map = <0 &apps_smmu 0x1480 0x1>, 2395 <0x100 &apps_smmu 0x1481 0x1>; 2396 2397 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2398 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2399 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2400 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2401 interrupt-map-mask = <0 0 0 0x7>; 2402 #interrupt-cells = <1>; 2403 2404 msi-map = <0x0 &gic_its 0x1480 0x1>, 2405 <0x100 &gic_its 0x1481 0x1>; 2406 msi-map-mask = <0xff00>; 2407 2408 linux,pci-domain = <1>; 2409 num-lanes = <2>; 2410 bus-range = <0 0xff>; 2411 2412 phys = <&pcie1_phy>; 2413 phy-names = "pciephy"; 2414 2415 dma-coherent; 2416 2417 #address-cells = <3>; 2418 #size-cells = <2>; 2419 ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, 2420 <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; 2421 2422 status = "disabled"; 2423 }; 2424 2425 pcie1_phy: phy@1c0e000 { 2426 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy"; 2427 reg = <0 0x01c0e000 0 0x2000>; 2428 2429 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2430 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2431 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 2432 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2433 <&gcc GCC_PCIE_1_PIPE_CLK>; 2434 clock-names = "aux", 2435 "cfg_ahb", 2436 "ref", 2437 "rchng", 2438 "pipe"; 2439 2440 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2441 assigned-clock-rates = <100000000>; 2442 2443 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 2444 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 2445 reset-names = "phy", 2446 "phy_nocsr"; 2447 2448 power-domains = <&gcc PCIE_1_PHY_GDSC>; 2449 2450 #clock-cells = <0>; 2451 clock-output-names = "pcie1_pipe_clk"; 2452 2453 #phy-cells = <0>; 2454 2455 status = "disabled"; 2456 }; 2457 2458 cryptobam: dma-controller@1dc4000 { 2459 compatible = "qcom,bam-v1.7.0"; 2460 reg = <0 0x01dc4000 0 0x28000>; 2461 2462 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2463 2464 #dma-cells = <1>; 2465 2466 iommus = <&apps_smmu 0x480 0>, 2467 <&apps_smmu 0x481 0>; 2468 2469 qcom,ee = <0>; 2470 qcom,controlled-remotely; 2471 }; 2472 2473 crypto: crypto@1dfa000 { 2474 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; 2475 reg = <0 0x01dfa000 0 0x6000>; 2476 2477 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 2478 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2479 interconnect-names = "memory"; 2480 2481 dmas = <&cryptobam 4>, <&cryptobam 5>; 2482 dma-names = "rx", "tx"; 2483 2484 iommus = <&apps_smmu 0x480 0>, 2485 <&apps_smmu 0x481 0>; 2486 }; 2487 2488 ufs_mem_phy: phy@1d80000 { 2489 compatible = "qcom,sm8650-qmp-ufs-phy"; 2490 reg = <0 0x01d80000 0 0x2000>; 2491 2492 clocks = <&rpmhcc RPMH_CXO_CLK>, 2493 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2494 <&tcsr TCSR_UFS_CLKREF_EN>; 2495 clock-names = "ref", 2496 "ref_aux", 2497 "qref"; 2498 2499 resets = <&ufs_mem_hc 0>; 2500 reset-names = "ufsphy"; 2501 2502 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 2503 2504 #clock-cells = <1>; 2505 #phy-cells = <0>; 2506 2507 status = "disabled"; 2508 }; 2509 2510 ufs_mem_hc: ufs@1d84000 { 2511 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2512 reg = <0 0x01d84000 0 0x3000>; 2513 2514 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2515 2516 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2517 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2518 <&gcc GCC_UFS_PHY_AHB_CLK>, 2519 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2520 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 2521 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2522 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2523 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2524 clock-names = "core_clk", 2525 "bus_aggr_clk", 2526 "iface_clk", 2527 "core_clk_unipro", 2528 "ref_clk", 2529 "tx_lane0_sync_clk", 2530 "rx_lane0_sync_clk", 2531 "rx_lane1_sync_clk"; 2532 freq-table-hz = <100000000 403000000>, 2533 <0 0>, 2534 <0 0>, 2535 <100000000 403000000>, 2536 <100000000 403000000>, 2537 <0 0>, 2538 <0 0>, 2539 <0 0>; 2540 2541 resets = <&gcc GCC_UFS_PHY_BCR>; 2542 reset-names = "rst"; 2543 2544 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2545 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2546 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2547 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2548 interconnect-names = "ufs-ddr", 2549 "cpu-ufs"; 2550 2551 power-domains = <&gcc UFS_PHY_GDSC>; 2552 required-opps = <&rpmhpd_opp_nom>; 2553 2554 iommus = <&apps_smmu 0x60 0>; 2555 2556 lanes-per-direction = <2>; 2557 qcom,ice = <&ice>; 2558 2559 phys = <&ufs_mem_phy>; 2560 phy-names = "ufsphy"; 2561 2562 #reset-cells = <1>; 2563 2564 status = "disabled"; 2565 }; 2566 2567 ice: crypto@1d88000 { 2568 compatible = "qcom,sm8650-inline-crypto-engine", 2569 "qcom,inline-crypto-engine"; 2570 reg = <0 0x01d88000 0 0x8000>; 2571 2572 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2573 }; 2574 2575 tcsr_mutex: hwlock@1f40000 { 2576 compatible = "qcom,tcsr-mutex"; 2577 reg = <0 0x01f40000 0 0x20000>; 2578 2579 #hwlock-cells = <1>; 2580 }; 2581 2582 tcsr: clock-controller@1fc0000 { 2583 compatible = "qcom,sm8650-tcsr", "syscon"; 2584 reg = <0 0x01fc0000 0 0xa0000>; 2585 2586 clocks = <&rpmhcc RPMH_CXO_CLK>; 2587 2588 #clock-cells = <1>; 2589 #reset-cells = <1>; 2590 }; 2591 2592 gpucc: clock-controller@3d90000 { 2593 compatible = "qcom,sm8650-gpucc"; 2594 reg = <0 0x03d90000 0 0xa000>; 2595 2596 clocks = <&bi_tcxo_div2>, 2597 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2598 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2599 2600 #clock-cells = <1>; 2601 #reset-cells = <1>; 2602 #power-domain-cells = <1>; 2603 }; 2604 2605 ipa: ipa@3f40000 { 2606 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; 2607 2608 iommus = <&apps_smmu 0x4a0 0x0>, 2609 <&apps_smmu 0x4a2 0x0>; 2610 reg = <0 0x3f40000 0 0x10000>, 2611 <0 0x3f50000 0 0x5000>, 2612 <0 0x3e04000 0 0xfc000>; 2613 reg-names = "ipa-reg", 2614 "ipa-shared", 2615 "gsi"; 2616 2617 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2618 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2619 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2620 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2621 interrupt-names = "ipa", 2622 "gsi", 2623 "ipa-clock-query", 2624 "ipa-setup-ready"; 2625 2626 clocks = <&rpmhcc RPMH_IPA_CLK>; 2627 clock-names = "core"; 2628 2629 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2630 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2631 interconnect-names = "memory", 2632 "config"; 2633 2634 qcom,qmp = <&aoss_qmp>; 2635 2636 qcom,smem-states = <&ipa_smp2p_out 0>, 2637 <&ipa_smp2p_out 1>; 2638 qcom,smem-state-names = "ipa-clock-enabled-valid", 2639 "ipa-clock-enabled"; 2640 2641 status = "disabled"; 2642 }; 2643 2644 remoteproc_mpss: remoteproc@4080000 { 2645 compatible = "qcom,sm8650-mpss-pas"; 2646 reg = <0 0x04080000 0 0x4040>; 2647 2648 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2649 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2650 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2651 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2652 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2653 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2654 interrupt-names = "wdog", 2655 "fatal", 2656 "ready", 2657 "handover", 2658 "stop-ack", 2659 "shutdown-ack"; 2660 2661 clocks = <&rpmhcc RPMH_CXO_CLK>; 2662 clock-names = "xo"; 2663 2664 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 2665 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2666 2667 power-domains = <&rpmhpd RPMHPD_CX>, 2668 <&rpmhpd RPMHPD_MSS>; 2669 power-domain-names = "cx", 2670 "mss"; 2671 2672 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, 2673 <&mpss_dsm_mem>, <&mpss_dsm_mem_2>, 2674 <&qlink_logging_mem>; 2675 2676 qcom,qmp = <&aoss_qmp>; 2677 2678 qcom,smem-states = <&smp2p_modem_out 0>; 2679 qcom,smem-state-names = "stop"; 2680 2681 status = "disabled"; 2682 2683 glink-edge { 2684 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2685 IPCC_MPROC_SIGNAL_GLINK_QMP 2686 IRQ_TYPE_EDGE_RISING>; 2687 2688 mboxes = <&ipcc IPCC_CLIENT_MPSS 2689 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2690 2691 qcom,remote-pid = <1>; 2692 2693 label = "mpss"; 2694 }; 2695 }; 2696 2697 lpass_wsa2macro: codec@6aa0000 { 2698 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 2699 reg = <0 0x06aa0000 0 0x1000>; 2700 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2701 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2702 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2703 <&lpass_vamacro>; 2704 clock-names = "mclk", 2705 "macro", 2706 "dcodec", 2707 "fsgen"; 2708 2709 #clock-cells = <0>; 2710 clock-output-names = "wsa2-mclk"; 2711 #sound-dai-cells = <1>; 2712 }; 2713 2714 swr3: soundwire@6ab0000 { 2715 compatible = "qcom,soundwire-v2.0.0"; 2716 reg = <0 0x06ab0000 0 0x10000>; 2717 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2718 clocks = <&lpass_wsa2macro>; 2719 clock-names = "iface"; 2720 label = "WSA2"; 2721 2722 pinctrl-0 = <&wsa2_swr_active>; 2723 pinctrl-names = "default"; 2724 2725 qcom,din-ports = <4>; 2726 qcom,dout-ports = <9>; 2727 2728 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2729 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2730 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2731 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2732 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2733 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2734 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2735 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2736 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2737 2738 #address-cells = <2>; 2739 #size-cells = <0>; 2740 #sound-dai-cells = <1>; 2741 status = "disabled"; 2742 }; 2743 2744 lpass_rxmacro: codec@6ac0000 { 2745 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 2746 reg = <0 0x06ac0000 0 0x1000>; 2747 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2748 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2749 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2750 <&lpass_vamacro>; 2751 clock-names = "mclk", 2752 "macro", 2753 "dcodec", 2754 "fsgen"; 2755 2756 #clock-cells = <0>; 2757 clock-output-names = "mclk"; 2758 #sound-dai-cells = <1>; 2759 }; 2760 2761 swr1: soundwire@6ad0000 { 2762 compatible = "qcom,soundwire-v2.0.0"; 2763 reg = <0 0x06ad0000 0 0x10000>; 2764 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2765 clocks = <&lpass_rxmacro>; 2766 clock-names = "iface"; 2767 label = "RX"; 2768 2769 pinctrl-0 = <&rx_swr_active>; 2770 pinctrl-names = "default"; 2771 2772 qcom,din-ports = <0>; 2773 qcom,dout-ports = <11>; 2774 2775 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>; 2776 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>; 2777 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 2778 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>; 2779 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>; 2780 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>; 2781 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>; 2782 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>; 2783 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; 2784 2785 #address-cells = <2>; 2786 #size-cells = <0>; 2787 #sound-dai-cells = <1>; 2788 status = "disabled"; 2789 }; 2790 2791 lpass_txmacro: codec@6ae0000 { 2792 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 2793 reg = <0 0x06ae0000 0 0x1000>; 2794 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2795 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2796 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2797 <&lpass_vamacro>; 2798 clock-names = "mclk", 2799 "macro", 2800 "dcodec", 2801 "fsgen"; 2802 2803 #clock-cells = <0>; 2804 clock-output-names = "mclk"; 2805 #sound-dai-cells = <1>; 2806 }; 2807 2808 lpass_wsamacro: codec@6b00000 { 2809 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 2810 reg = <0 0x06b00000 0 0x1000>; 2811 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2812 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2813 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2814 <&lpass_vamacro>; 2815 clock-names = "mclk", 2816 "macro", 2817 "dcodec", 2818 "fsgen"; 2819 2820 #clock-cells = <0>; 2821 clock-output-names = "mclk"; 2822 #sound-dai-cells = <1>; 2823 }; 2824 2825 swr0: soundwire@6b10000 { 2826 compatible = "qcom,soundwire-v2.0.0"; 2827 reg = <0 0x06b10000 0 0x10000>; 2828 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2829 clocks = <&lpass_wsamacro>; 2830 clock-names = "iface"; 2831 label = "WSA"; 2832 2833 pinctrl-0 = <&wsa_swr_active>; 2834 pinctrl-names = "default"; 2835 2836 qcom,din-ports = <4>; 2837 qcom,dout-ports = <9>; 2838 2839 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2840 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2841 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2842 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2843 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2844 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2845 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2846 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2847 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2848 2849 #address-cells = <2>; 2850 #size-cells = <0>; 2851 #sound-dai-cells = <1>; 2852 status = "disabled"; 2853 }; 2854 2855 swr2: soundwire@6d30000 { 2856 compatible = "qcom,soundwire-v2.0.0"; 2857 reg = <0 0x06d30000 0 0x10000>; 2858 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2859 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2860 interrupt-names = "core", "wakeup"; 2861 clocks = <&lpass_txmacro>; 2862 clock-names = "iface"; 2863 label = "TX"; 2864 2865 pinctrl-0 = <&tx_swr_active>; 2866 pinctrl-names = "default"; 2867 2868 qcom,din-ports = <4>; 2869 qcom,dout-ports = <0>; 2870 2871 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2872 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2873 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2874 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2875 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2876 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2877 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2878 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2879 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2880 2881 #address-cells = <2>; 2882 #size-cells = <0>; 2883 #sound-dai-cells = <1>; 2884 status = "disabled"; 2885 }; 2886 2887 lpass_vamacro: codec@6d44000 { 2888 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 2889 reg = <0 0x06d44000 0 0x1000>; 2890 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2891 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2892 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2893 clock-names = "mclk", 2894 "macro", 2895 "dcodec"; 2896 2897 #clock-cells = <0>; 2898 clock-output-names = "fsgen"; 2899 #sound-dai-cells = <1>; 2900 }; 2901 2902 lpass_tlmm: pinctrl@6e80000 { 2903 compatible = "qcom,sm8650-lpass-lpi-pinctrl"; 2904 reg = <0 0x06e80000 0 0x20000>; 2905 2906 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2907 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2908 clock-names = "core", "audio"; 2909 2910 gpio-controller; 2911 #gpio-cells = <2>; 2912 gpio-ranges = <&lpass_tlmm 0 0 23>; 2913 2914 tx_swr_active: tx-swr-active-state { 2915 clk-pins { 2916 pins = "gpio0"; 2917 function = "swr_tx_clk"; 2918 drive-strength = <2>; 2919 slew-rate = <1>; 2920 bias-disable; 2921 }; 2922 2923 data-pins { 2924 pins = "gpio1", "gpio2", "gpio14"; 2925 function = "swr_tx_data"; 2926 drive-strength = <2>; 2927 slew-rate = <1>; 2928 bias-bus-hold; 2929 }; 2930 }; 2931 2932 rx_swr_active: rx-swr-active-state { 2933 clk-pins { 2934 pins = "gpio3"; 2935 function = "swr_rx_clk"; 2936 drive-strength = <2>; 2937 slew-rate = <1>; 2938 bias-disable; 2939 }; 2940 2941 data-pins { 2942 pins = "gpio4", "gpio5"; 2943 function = "swr_rx_data"; 2944 drive-strength = <2>; 2945 slew-rate = <1>; 2946 bias-bus-hold; 2947 }; 2948 }; 2949 2950 dmic01_default: dmic01-default-state { 2951 clk-pins { 2952 pins = "gpio6"; 2953 function = "dmic1_clk"; 2954 drive-strength = <8>; 2955 output-high; 2956 }; 2957 2958 data-pins { 2959 pins = "gpio7"; 2960 function = "dmic1_data"; 2961 drive-strength = <8>; 2962 input-enable; 2963 }; 2964 }; 2965 2966 dmic23_default: dmic23-default-state { 2967 clk-pins { 2968 pins = "gpio8"; 2969 function = "dmic2_clk"; 2970 drive-strength = <8>; 2971 output-high; 2972 }; 2973 2974 data-pins { 2975 pins = "gpio9"; 2976 function = "dmic2_data"; 2977 drive-strength = <8>; 2978 input-enable; 2979 }; 2980 }; 2981 2982 wsa_swr_active: wsa-swr-active-state { 2983 clk-pins { 2984 pins = "gpio10"; 2985 function = "wsa_swr_clk"; 2986 drive-strength = <2>; 2987 slew-rate = <1>; 2988 bias-disable; 2989 }; 2990 2991 data-pins { 2992 pins = "gpio11"; 2993 function = "wsa_swr_data"; 2994 drive-strength = <2>; 2995 slew-rate = <1>; 2996 bias-bus-hold; 2997 }; 2998 }; 2999 3000 wsa2_swr_active: wsa2-swr-active-state { 3001 clk-pins { 3002 pins = "gpio15"; 3003 function = "wsa2_swr_clk"; 3004 drive-strength = <2>; 3005 slew-rate = <1>; 3006 bias-disable; 3007 }; 3008 3009 data-pins { 3010 pins = "gpio16"; 3011 function = "wsa2_swr_data"; 3012 drive-strength = <2>; 3013 slew-rate = <1>; 3014 bias-bus-hold; 3015 }; 3016 }; 3017 }; 3018 3019 lpass_lpiaon_noc: interconnect@7400000 { 3020 compatible = "qcom,sm8650-lpass-lpiaon-noc"; 3021 reg = <0 0x07400000 0 0x19080>; 3022 3023 #interconnect-cells = <2>; 3024 3025 qcom,bcm-voters = <&apps_bcm_voter>; 3026 }; 3027 3028 lpass_lpicx_noc: interconnect@7430000 { 3029 compatible = "qcom,sm8650-lpass-lpicx-noc"; 3030 reg = <0 0x07430000 0 0x3a200>; 3031 3032 #interconnect-cells = <2>; 3033 3034 qcom,bcm-voters = <&apps_bcm_voter>; 3035 }; 3036 3037 lpass_ag_noc: interconnect@7e40000 { 3038 compatible = "qcom,sm8650-lpass-ag-noc"; 3039 reg = <0 0x07e40000 0 0xe080>; 3040 3041 #interconnect-cells = <2>; 3042 3043 qcom,bcm-voters = <&apps_bcm_voter>; 3044 }; 3045 3046 sdhc_2: mmc@8804000 { 3047 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; 3048 reg = <0 0x08804000 0 0x1000>; 3049 3050 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3051 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3052 interrupt-names = "hc_irq", 3053 "pwr_irq"; 3054 3055 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3056 <&gcc GCC_SDCC2_APPS_CLK>, 3057 <&rpmhcc RPMH_CXO_CLK>; 3058 clock-names = "iface", 3059 "core", 3060 "xo"; 3061 3062 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3063 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3064 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3065 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; 3066 interconnect-names = "sdhc-ddr", 3067 "cpu-sdhc"; 3068 3069 power-domains = <&rpmhpd RPMHPD_CX>; 3070 operating-points-v2 = <&sdhc2_opp_table>; 3071 3072 iommus = <&apps_smmu 0x540 0>; 3073 3074 bus-width = <4>; 3075 3076 /* Forbid SDR104/SDR50 - broken hw! */ 3077 sdhci-caps-mask = <0x3 0>; 3078 3079 qcom,dll-config = <0x0007642c>; 3080 qcom,ddr-config = <0x80040868>; 3081 3082 dma-coherent; 3083 3084 status = "disabled"; 3085 3086 sdhc2_opp_table: opp-table { 3087 compatible = "operating-points-v2"; 3088 3089 opp-19200000 { 3090 opp-hz = /bits/ 64 <19200000>; 3091 required-opps = <&rpmhpd_opp_min_svs>; 3092 }; 3093 3094 opp-50000000 { 3095 opp-hz = /bits/ 64 <50000000>; 3096 required-opps = <&rpmhpd_opp_low_svs>; 3097 }; 3098 3099 opp-100000000 { 3100 opp-hz = /bits/ 64 <100000000>; 3101 required-opps = <&rpmhpd_opp_svs>; 3102 }; 3103 3104 opp-202000000 { 3105 opp-hz = /bits/ 64 <202000000>; 3106 required-opps = <&rpmhpd_opp_svs_l1>; 3107 }; 3108 }; 3109 }; 3110 3111 mdss: display-subsystem@ae00000 { 3112 compatible = "qcom,sm8650-mdss"; 3113 reg = <0 0x0ae00000 0 0x1000>; 3114 reg-names = "mdss"; 3115 3116 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3117 3118 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3119 <&gcc GCC_DISP_HF_AXI_CLK>, 3120 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3121 3122 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3123 3124 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 3125 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 3126 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 3127 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3128 interconnect-names = "mdp0-mem", 3129 "mdp1-mem"; 3130 3131 power-domains = <&dispcc MDSS_GDSC>; 3132 3133 iommus = <&apps_smmu 0x1c00 0x2>; 3134 3135 interrupt-controller; 3136 #interrupt-cells = <1>; 3137 3138 #address-cells = <2>; 3139 #size-cells = <2>; 3140 ranges; 3141 3142 status = "disabled"; 3143 3144 mdss_mdp: display-controller@ae01000 { 3145 compatible = "qcom,sm8650-dpu"; 3146 reg = <0 0x0ae01000 0 0x8f000>, 3147 <0 0x0aeb0000 0 0x2008>; 3148 reg-names = "mdp", 3149 "vbif"; 3150 3151 interrupts-extended = <&mdss 0>; 3152 3153 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3154 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3155 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3156 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3157 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3158 clock-names = "nrt_bus", 3159 "iface", 3160 "lut", 3161 "core", 3162 "vsync"; 3163 3164 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3165 assigned-clock-rates = <19200000>; 3166 3167 operating-points-v2 = <&mdp_opp_table>; 3168 3169 power-domains = <&rpmhpd RPMHPD_MMCX>; 3170 3171 ports { 3172 #address-cells = <1>; 3173 #size-cells = <0>; 3174 3175 port@0 { 3176 reg = <0>; 3177 3178 dpu_intf1_out: endpoint { 3179 remote-endpoint = <&mdss_dsi0_in>; 3180 }; 3181 }; 3182 3183 port@1 { 3184 reg = <1>; 3185 3186 dpu_intf2_out: endpoint { 3187 remote-endpoint = <&mdss_dsi1_in>; 3188 }; 3189 }; 3190 3191 port@2 { 3192 reg = <2>; 3193 3194 dpu_intf0_out: endpoint { 3195 remote-endpoint = <&mdss_dp0_in>; 3196 }; 3197 }; 3198 }; 3199 3200 mdp_opp_table: opp-table { 3201 compatible = "operating-points-v2"; 3202 3203 opp-200000000 { 3204 opp-hz = /bits/ 64 <200000000>; 3205 required-opps = <&rpmhpd_opp_low_svs>; 3206 }; 3207 3208 opp-325000000 { 3209 opp-hz = /bits/ 64 <325000000>; 3210 required-opps = <&rpmhpd_opp_svs>; 3211 }; 3212 3213 opp-375000000 { 3214 opp-hz = /bits/ 64 <375000000>; 3215 required-opps = <&rpmhpd_opp_svs_l1>; 3216 }; 3217 3218 opp-514000000 { 3219 opp-hz = /bits/ 64 <514000000>; 3220 required-opps = <&rpmhpd_opp_nom>; 3221 }; 3222 }; 3223 }; 3224 3225 mdss_dsi0: dsi@ae94000 { 3226 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3227 reg = <0 0x0ae94000 0 0x400>; 3228 reg-names = "dsi_ctrl"; 3229 3230 interrupts-extended = <&mdss 4>; 3231 3232 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3233 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3234 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3235 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3236 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3237 <&gcc GCC_DISP_HF_AXI_CLK>; 3238 clock-names = "byte", 3239 "byte_intf", 3240 "pixel", 3241 "core", 3242 "iface", 3243 "bus"; 3244 3245 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3246 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3247 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3248 <&mdss_dsi0_phy 1>; 3249 3250 operating-points-v2 = <&mdss_dsi_opp_table>; 3251 3252 power-domains = <&rpmhpd RPMHPD_MMCX>; 3253 3254 phys = <&mdss_dsi0_phy>; 3255 phy-names = "dsi"; 3256 3257 #address-cells = <1>; 3258 #size-cells = <0>; 3259 3260 status = "disabled"; 3261 3262 ports { 3263 #address-cells = <1>; 3264 #size-cells = <0>; 3265 3266 port@0 { 3267 reg = <0>; 3268 3269 mdss_dsi0_in: endpoint { 3270 remote-endpoint = <&dpu_intf1_out>; 3271 }; 3272 }; 3273 3274 port@1 { 3275 reg = <1>; 3276 3277 mdss_dsi0_out: endpoint { 3278 }; 3279 }; 3280 }; 3281 3282 mdss_dsi_opp_table: opp-table { 3283 compatible = "operating-points-v2"; 3284 3285 opp-187500000 { 3286 opp-hz = /bits/ 64 <187500000>; 3287 required-opps = <&rpmhpd_opp_low_svs>; 3288 }; 3289 3290 opp-300000000 { 3291 opp-hz = /bits/ 64 <300000000>; 3292 required-opps = <&rpmhpd_opp_svs>; 3293 }; 3294 3295 opp-358000000 { 3296 opp-hz = /bits/ 64 <358000000>; 3297 required-opps = <&rpmhpd_opp_svs_l1>; 3298 }; 3299 }; 3300 }; 3301 3302 mdss_dsi0_phy: phy@ae95000 { 3303 compatible = "qcom,sm8650-dsi-phy-4nm"; 3304 reg = <0 0x0ae95000 0 0x200>, 3305 <0 0x0ae95200 0 0x280>, 3306 <0 0x0ae95500 0 0x400>; 3307 reg-names = "dsi_phy", 3308 "dsi_phy_lane", 3309 "dsi_pll"; 3310 3311 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3312 <&rpmhcc RPMH_CXO_CLK>; 3313 clock-names = "iface", 3314 "ref"; 3315 3316 #clock-cells = <1>; 3317 #phy-cells = <0>; 3318 3319 status = "disabled"; 3320 }; 3321 3322 mdss_dsi1: dsi@ae96000 { 3323 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3324 reg = <0 0x0ae96000 0 0x400>; 3325 reg-names = "dsi_ctrl"; 3326 3327 interrupts-extended = <&mdss 5>; 3328 3329 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3330 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3331 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3332 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3333 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3334 <&gcc GCC_DISP_HF_AXI_CLK>; 3335 clock-names = "byte", 3336 "byte_intf", 3337 "pixel", 3338 "core", 3339 "iface", 3340 "bus"; 3341 3342 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3343 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3344 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3345 <&mdss_dsi1_phy 1>; 3346 3347 operating-points-v2 = <&mdss_dsi_opp_table>; 3348 3349 power-domains = <&rpmhpd RPMHPD_MMCX>; 3350 3351 phys = <&mdss_dsi1_phy>; 3352 phy-names = "dsi"; 3353 3354 #address-cells = <1>; 3355 #size-cells = <0>; 3356 3357 status = "disabled"; 3358 3359 ports { 3360 #address-cells = <1>; 3361 #size-cells = <0>; 3362 3363 port@0 { 3364 reg = <0>; 3365 3366 mdss_dsi1_in: endpoint { 3367 remote-endpoint = <&dpu_intf2_out>; 3368 }; 3369 }; 3370 3371 port@1 { 3372 reg = <1>; 3373 3374 mdss_dsi1_out: endpoint { 3375 }; 3376 }; 3377 }; 3378 }; 3379 3380 mdss_dsi1_phy: phy@ae97000 { 3381 compatible = "qcom,sm8650-dsi-phy-4nm"; 3382 reg = <0 0x0ae97000 0 0x200>, 3383 <0 0x0ae97200 0 0x280>, 3384 <0 0x0ae97500 0 0x400>; 3385 reg-names = "dsi_phy", 3386 "dsi_phy_lane", 3387 "dsi_pll"; 3388 3389 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3390 <&rpmhcc RPMH_CXO_CLK>; 3391 clock-names = "iface", 3392 "ref"; 3393 3394 #clock-cells = <1>; 3395 #phy-cells = <0>; 3396 3397 status = "disabled"; 3398 }; 3399 3400 mdss_dp0: displayport-controller@af54000 { 3401 compatible = "qcom,sm8650-dp"; 3402 reg = <0 0xaf54000 0 0x104>, 3403 <0 0xaf54200 0 0xc0>, 3404 <0 0xaf55000 0 0x770>, 3405 <0 0xaf56000 0 0x9c>, 3406 <0 0xaf57000 0 0x9c>; 3407 3408 interrupts-extended = <&mdss 12>; 3409 3410 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3411 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3412 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3413 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3414 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3415 clock-names = "core_iface", 3416 "core_aux", 3417 "ctrl_link", 3418 "ctrl_link_iface", 3419 "stream_pixel"; 3420 3421 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3422 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3423 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3424 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3425 3426 operating-points-v2 = <&dp_opp_table>; 3427 3428 power-domains = <&rpmhpd RPMHPD_MMCX>; 3429 3430 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 3431 phy-names = "dp"; 3432 3433 #sound-dai-cells = <0>; 3434 3435 status = "disabled"; 3436 3437 dp_opp_table: opp-table { 3438 compatible = "operating-points-v2"; 3439 3440 opp-162000000 { 3441 opp-hz = /bits/ 64 <162000000>; 3442 required-opps = <&rpmhpd_opp_low_svs_d1>; 3443 }; 3444 3445 opp-270000000 { 3446 opp-hz = /bits/ 64 <270000000>; 3447 required-opps = <&rpmhpd_opp_low_svs>; 3448 }; 3449 3450 opp-540000000 { 3451 opp-hz = /bits/ 64 <540000000>; 3452 required-opps = <&rpmhpd_opp_svs_l1>; 3453 }; 3454 3455 opp-810000000 { 3456 opp-hz = /bits/ 64 <810000000>; 3457 required-opps = <&rpmhpd_opp_nom>; 3458 }; 3459 }; 3460 3461 ports { 3462 #address-cells = <1>; 3463 #size-cells = <0>; 3464 3465 port@0 { 3466 reg = <0>; 3467 3468 mdss_dp0_in: endpoint { 3469 remote-endpoint = <&dpu_intf0_out>; 3470 }; 3471 }; 3472 3473 port@1 { 3474 reg = <1>; 3475 3476 mdss_dp0_out: endpoint { 3477 }; 3478 }; 3479 }; 3480 }; 3481 }; 3482 3483 dispcc: clock-controller@af00000 { 3484 compatible = "qcom,sm8650-dispcc"; 3485 reg = <0 0x0af00000 0 0x20000>; 3486 3487 clocks = <&bi_tcxo_div2>, 3488 <&bi_tcxo_ao_div2>, 3489 <&gcc GCC_DISP_AHB_CLK>, 3490 <&sleep_clk>, 3491 <&mdss_dsi0_phy 0>, 3492 <&mdss_dsi0_phy 1>, 3493 <&mdss_dsi1_phy 0>, 3494 <&mdss_dsi1_phy 1>, 3495 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3496 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3497 <0>, /* dp1 */ 3498 <0>, 3499 <0>, /* dp2 */ 3500 <0>, 3501 <0>, /* dp3 */ 3502 <0>; 3503 3504 power-domains = <&rpmhpd RPMHPD_MMCX>; 3505 required-opps = <&rpmhpd_opp_low_svs>; 3506 3507 #clock-cells = <1>; 3508 #reset-cells = <1>; 3509 #power-domain-cells = <1>; 3510 3511 status = "disabled"; 3512 }; 3513 3514 usb_1_hsphy: phy@88e3000 { 3515 compatible = "qcom,sm8650-snps-eusb2-phy", 3516 "qcom,sm8550-snps-eusb2-phy"; 3517 reg = <0 0x088e3000 0 0x154>; 3518 3519 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 3520 clock-names = "ref"; 3521 3522 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3523 3524 #phy-cells = <0>; 3525 3526 status = "disabled"; 3527 }; 3528 3529 usb_dp_qmpphy: phy@88e8000 { 3530 compatible = "qcom,sm8650-qmp-usb3-dp-phy"; 3531 reg = <0 0x088e8000 0 0x3000>; 3532 3533 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3534 <&rpmhcc RPMH_CXO_CLK>, 3535 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3536 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3537 clock-names = "aux", 3538 "ref", 3539 "com_aux", 3540 "usb3_pipe"; 3541 3542 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3543 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 3544 reset-names = "phy", 3545 "common"; 3546 3547 power-domains = <&gcc USB3_PHY_GDSC>; 3548 3549 #clock-cells = <1>; 3550 #phy-cells = <1>; 3551 3552 status = "disabled"; 3553 3554 ports { 3555 #address-cells = <1>; 3556 #size-cells = <0>; 3557 3558 port@0 { 3559 reg = <0>; 3560 3561 usb_dp_qmpphy_out: endpoint { 3562 }; 3563 }; 3564 3565 port@1 { 3566 reg = <1>; 3567 3568 usb_dp_qmpphy_usb_ss_in: endpoint { 3569 }; 3570 }; 3571 3572 port@2 { 3573 reg = <2>; 3574 3575 usb_dp_qmpphy_dp_in: endpoint { 3576 }; 3577 }; 3578 }; 3579 }; 3580 3581 usb_1: usb@a6f8800 { 3582 compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; 3583 reg = <0 0x0a6f8800 0 0x400>; 3584 3585 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3586 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3587 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 3588 <&pdc 14 IRQ_TYPE_EDGE_RISING>; 3589 interrupt-names = "hs_phy_irq", 3590 "ss_phy_irq", 3591 "dm_hs_phy_irq", 3592 "dp_hs_phy_irq"; 3593 3594 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3595 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3596 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3597 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3598 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3599 <&tcsr TCSR_USB3_CLKREF_EN>; 3600 clock-names = "cfg_noc", 3601 "core", 3602 "iface", 3603 "sleep", 3604 "mock_utmi", 3605 "xo"; 3606 3607 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3608 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3609 assigned-clock-rates = <19200000>, <200000000>; 3610 3611 resets = <&gcc GCC_USB30_PRIM_BCR>; 3612 3613 power-domains = <&gcc USB30_PRIM_GDSC>; 3614 required-opps = <&rpmhpd_opp_nom>; 3615 3616 #address-cells = <2>; 3617 #size-cells = <2>; 3618 ranges; 3619 3620 status = "disabled"; 3621 3622 usb_1_dwc3: usb@a600000 { 3623 compatible = "snps,dwc3"; 3624 reg = <0 0x0a600000 0 0xcd00>; 3625 3626 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3627 3628 iommus = <&apps_smmu 0x40 0>; 3629 3630 phys = <&usb_1_hsphy>, 3631 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 3632 phy-names = "usb2-phy", 3633 "usb3-phy"; 3634 3635 snps,hird-threshold = /bits/ 8 <0x0>; 3636 snps,usb2-gadget-lpm-disable; 3637 snps,dis_u2_susphy_quirk; 3638 snps,dis_enblslpm_quirk; 3639 snps,dis-u1-entry-quirk; 3640 snps,dis-u2-entry-quirk; 3641 snps,is-utmi-l1-suspend; 3642 snps,usb3_lpm_capable; 3643 snps,usb2-lpm-disable; 3644 snps,has-lpm-erratum; 3645 tx-fifo-resize; 3646 3647 dma-coherent; 3648 3649 ports { 3650 #address-cells = <1>; 3651 #size-cells = <0>; 3652 3653 port@0 { 3654 reg = <0>; 3655 3656 usb_1_dwc3_hs: endpoint { 3657 }; 3658 }; 3659 3660 port@1 { 3661 reg = <1>; 3662 3663 usb_1_dwc3_ss: endpoint { 3664 }; 3665 }; 3666 }; 3667 }; 3668 }; 3669 3670 pdc: interrupt-controller@b220000 { 3671 compatible = "qcom,sm8650-pdc", "qcom,pdc"; 3672 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3673 3674 interrupt-parent = <&intc>; 3675 3676 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3677 <125 63 1>, <126 716 12>, 3678 <138 251 5>, <143 244 4>; 3679 3680 #interrupt-cells = <2>; 3681 interrupt-controller; 3682 }; 3683 3684 tsens0: thermal-sensor@c228000 { 3685 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 3686 reg = <0 0x0c228000 0 0x1000>, /* TM */ 3687 <0 0x0c222000 0 0x1000>; /* SROT */ 3688 3689 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3690 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 3691 interrupt-names = "uplow", 3692 "critical"; 3693 3694 #qcom,sensors = <15>; 3695 3696 #thermal-sensor-cells = <1>; 3697 }; 3698 3699 tsens1: thermal-sensor@c229000 { 3700 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 3701 reg = <0 0x0c229000 0 0x1000>, /* TM */ 3702 <0 0x0c223000 0 0x1000>; /* SROT */ 3703 3704 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3705 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 3706 interrupt-names = "uplow", 3707 "critical"; 3708 3709 #qcom,sensors = <16>; 3710 3711 #thermal-sensor-cells = <1>; 3712 }; 3713 3714 tsens2: thermal-sensor@c22a000 { 3715 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 3716 reg = <0 0x0c22a000 0 0x1000>, /* TM */ 3717 <0 0x0c224000 0 0x1000>; /* SROT */ 3718 3719 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 3721 interrupt-names = "uplow", 3722 "critical"; 3723 3724 #qcom,sensors = <13>; 3725 3726 #thermal-sensor-cells = <1>; 3727 }; 3728 3729 aoss_qmp: power-management@c300000 { 3730 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; 3731 reg = <0 0x0c300000 0 0x400>; 3732 3733 interrupt-parent = <&ipcc>; 3734 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3735 IRQ_TYPE_EDGE_RISING>; 3736 3737 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3738 3739 #clock-cells = <0>; 3740 }; 3741 3742 sram@c3f0000 { 3743 compatible = "qcom,rpmh-stats"; 3744 reg = <0 0x0c3f0000 0 0x400>; 3745 }; 3746 3747 spmi_bus: spmi@c400000 { 3748 compatible = "qcom,spmi-pmic-arb"; 3749 reg = <0 0x0c400000 0 0x3000>, 3750 <0 0x0c500000 0 0x400000>, 3751 <0 0x0c440000 0 0x80000>, 3752 <0 0x0c4c0000 0 0x20000>, 3753 <0 0x0c42d000 0 0x4000>; 3754 reg-names = "core", 3755 "chnls", 3756 "obsrvr", 3757 "intr", 3758 "cnfg"; 3759 3760 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3761 interrupt-names = "periph_irq"; 3762 3763 qcom,ee = <0>; 3764 qcom,channel = <0>; 3765 qcom,bus-id = <0>; 3766 3767 interrupt-controller; 3768 #interrupt-cells = <4>; 3769 3770 #address-cells = <2>; 3771 #size-cells = <0>; 3772 }; 3773 3774 tlmm: pinctrl@f100000 { 3775 compatible = "qcom,sm8650-tlmm"; 3776 reg = <0 0x0f100000 0 0x300000>; 3777 3778 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3779 3780 gpio-controller; 3781 #gpio-cells = <2>; 3782 3783 interrupt-controller; 3784 #interrupt-cells = <2>; 3785 3786 gpio-ranges = <&tlmm 0 0 211>; 3787 3788 wakeup-parent = <&pdc>; 3789 3790 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3791 /* SDA, SCL */ 3792 pins = "gpio64", "gpio65"; 3793 function = "i2chub0_se0"; 3794 drive-strength = <2>; 3795 bias-pull-up; 3796 }; 3797 3798 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 3799 /* SDA, SCL */ 3800 pins = "gpio66", "gpio67"; 3801 function = "i2chub0_se1"; 3802 drive-strength = <2>; 3803 bias-pull-up; 3804 }; 3805 3806 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 3807 /* SDA, SCL */ 3808 pins = "gpio68", "gpio69"; 3809 function = "i2chub0_se2"; 3810 drive-strength = <2>; 3811 bias-pull-up; 3812 }; 3813 3814 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 3815 /* SDA, SCL */ 3816 pins = "gpio70", "gpio71"; 3817 function = "i2chub0_se3"; 3818 drive-strength = <2>; 3819 bias-pull-up; 3820 }; 3821 3822 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 3823 /* SDA, SCL */ 3824 pins = "gpio72", "gpio73"; 3825 function = "i2chub0_se4"; 3826 drive-strength = <2>; 3827 bias-pull-up; 3828 }; 3829 3830 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 3831 /* SDA, SCL */ 3832 pins = "gpio74", "gpio75"; 3833 function = "i2chub0_se5"; 3834 drive-strength = <2>; 3835 bias-pull-up; 3836 }; 3837 3838 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 3839 /* SDA, SCL */ 3840 pins = "gpio76", "gpio77"; 3841 function = "i2chub0_se6"; 3842 drive-strength = <2>; 3843 bias-pull-up; 3844 }; 3845 3846 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 3847 /* SDA, SCL */ 3848 pins = "gpio78", "gpio79"; 3849 function = "i2chub0_se7"; 3850 drive-strength = <2>; 3851 bias-pull-up; 3852 }; 3853 3854 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 3855 /* SDA, SCL */ 3856 pins = "gpio206", "gpio207"; 3857 function = "i2chub0_se8"; 3858 drive-strength = <2>; 3859 bias-pull-up; 3860 }; 3861 3862 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 3863 /* SDA, SCL */ 3864 pins = "gpio80", "gpio81"; 3865 function = "i2chub0_se9"; 3866 drive-strength = <2>; 3867 bias-pull-up; 3868 }; 3869 3870 pcie0_default_state: pcie0-default-state { 3871 perst-pins { 3872 pins = "gpio94"; 3873 function = "gpio"; 3874 drive-strength = <2>; 3875 bias-pull-down; 3876 }; 3877 3878 clkreq-pins { 3879 pins = "gpio95"; 3880 function = "pcie0_clk_req_n"; 3881 drive-strength = <2>; 3882 bias-pull-up; 3883 }; 3884 3885 wake-pins { 3886 pins = "gpio96"; 3887 function = "gpio"; 3888 drive-strength = <2>; 3889 bias-pull-up; 3890 }; 3891 }; 3892 3893 pcie1_default_state: pcie1-default-state { 3894 perst-pins { 3895 pins = "gpio97"; 3896 function = "gpio"; 3897 drive-strength = <2>; 3898 bias-pull-down; 3899 }; 3900 3901 clkreq-pins { 3902 pins = "gpio98"; 3903 function = "pcie1_clk_req_n"; 3904 drive-strength = <2>; 3905 bias-pull-up; 3906 }; 3907 3908 wake-pins { 3909 pins = "gpio99"; 3910 function = "gpio"; 3911 drive-strength = <2>; 3912 bias-pull-up; 3913 }; 3914 }; 3915 3916 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3917 /* SDA, SCL */ 3918 pins = "gpio32", "gpio33"; 3919 function = "qup1_se0"; 3920 drive-strength = <2>; 3921 bias-pull-up; 3922 }; 3923 3924 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3925 /* SDA, SCL */ 3926 pins = "gpio36", "gpio37"; 3927 function = "qup1_se1"; 3928 drive-strength = <2>; 3929 bias-pull-up; 3930 }; 3931 3932 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3933 /* SDA, SCL */ 3934 pins = "gpio40", "gpio41"; 3935 function = "qup1_se2"; 3936 drive-strength = <2>; 3937 bias-pull-up; 3938 }; 3939 3940 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3941 /* SDA, SCL */ 3942 pins = "gpio44", "gpio45"; 3943 function = "qup1_se3"; 3944 drive-strength = <2>; 3945 bias-pull-up; 3946 }; 3947 3948 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3949 /* SDA, SCL */ 3950 pins = "gpio48", "gpio49"; 3951 function = "qup1_se4"; 3952 drive-strength = <2>; 3953 bias-pull-up; 3954 }; 3955 3956 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3957 /* SDA, SCL */ 3958 pins = "gpio52", "gpio53"; 3959 function = "qup1_se5"; 3960 drive-strength = <2>; 3961 bias-pull-up; 3962 }; 3963 3964 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3965 /* SDA, SCL */ 3966 pins = "gpio56", "gpio57"; 3967 function = "qup1_se6"; 3968 drive-strength = <2>; 3969 bias-pull-up; 3970 }; 3971 3972 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 3973 /* SDA, SCL */ 3974 pins = "gpio60", "gpio61"; 3975 function = "qup1_se7"; 3976 drive-strength = <2>; 3977 bias-pull-up; 3978 }; 3979 3980 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3981 /* SDA, SCL */ 3982 pins = "gpio0", "gpio1"; 3983 function = "qup2_se0"; 3984 drive-strength = <2>; 3985 bias-pull-up; 3986 }; 3987 3988 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3989 /* SDA, SCL */ 3990 pins = "gpio4", "gpio5"; 3991 function = "qup2_se1"; 3992 drive-strength = <2>; 3993 bias-pull-up; 3994 }; 3995 3996 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3997 /* SDA, SCL */ 3998 pins = "gpio8", "gpio9"; 3999 function = "qup2_se2"; 4000 drive-strength = <2>; 4001 bias-pull-up; 4002 }; 4003 4004 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4005 /* SDA, SCL */ 4006 pins = "gpio12", "gpio13"; 4007 function = "qup2_se3"; 4008 drive-strength = <2>; 4009 bias-pull-up; 4010 }; 4011 4012 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4013 /* SDA, SCL */ 4014 pins = "gpio16", "gpio17"; 4015 function = "qup2_se4"; 4016 drive-strength = <2>; 4017 bias-pull-up; 4018 }; 4019 4020 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4021 /* SDA, SCL */ 4022 pins = "gpio20", "gpio21"; 4023 function = "qup2_se5"; 4024 drive-strength = <2>; 4025 bias-pull-up; 4026 }; 4027 4028 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4029 /* SDA, SCL */ 4030 pins = "gpio24", "gpio25"; 4031 function = "qup2_se6"; 4032 drive-strength = <2>; 4033 bias-pull-up; 4034 }; 4035 4036 qup_spi0_cs: qup-spi0-cs-state { 4037 pins = "gpio35"; 4038 function = "qup1_se0"; 4039 drive-strength = <6>; 4040 bias-disable; 4041 }; 4042 4043 qup_spi0_data_clk: qup-spi0-data-clk-state { 4044 /* MISO, MOSI, CLK */ 4045 pins = "gpio32", "gpio33", "gpio34"; 4046 function = "qup1_se0"; 4047 drive-strength = <6>; 4048 bias-disable; 4049 }; 4050 4051 qup_spi1_cs: qup-spi1-cs-state { 4052 pins = "gpio39"; 4053 function = "qup1_se1"; 4054 drive-strength = <6>; 4055 bias-disable; 4056 }; 4057 4058 qup_spi1_data_clk: qup-spi1-data-clk-state { 4059 /* MISO, MOSI, CLK */ 4060 pins = "gpio36", "gpio37", "gpio38"; 4061 function = "qup1_se1"; 4062 drive-strength = <6>; 4063 bias-disable; 4064 }; 4065 4066 qup_spi2_cs: qup-spi2-cs-state { 4067 pins = "gpio43"; 4068 function = "qup1_se2"; 4069 drive-strength = <6>; 4070 bias-disable; 4071 }; 4072 4073 qup_spi2_data_clk: qup-spi2-data-clk-state { 4074 /* MISO, MOSI, CLK */ 4075 pins = "gpio40", "gpio41", "gpio42"; 4076 function = "qup1_se2"; 4077 drive-strength = <6>; 4078 bias-disable; 4079 }; 4080 4081 qup_spi3_cs: qup-spi3-cs-state { 4082 pins = "gpio47"; 4083 function = "qup1_se3"; 4084 drive-strength = <6>; 4085 bias-disable; 4086 }; 4087 4088 qup_spi3_data_clk: qup-spi3-data-clk-state { 4089 /* MISO, MOSI, CLK */ 4090 pins = "gpio44", "gpio45", "gpio46"; 4091 function = "qup1_se3"; 4092 drive-strength = <6>; 4093 bias-disable; 4094 }; 4095 4096 qup_spi4_cs: qup-spi4-cs-state { 4097 pins = "gpio51"; 4098 function = "qup1_se4"; 4099 drive-strength = <6>; 4100 bias-disable; 4101 }; 4102 4103 qup_spi4_data_clk: qup-spi4-data-clk-state { 4104 /* MISO, MOSI, CLK */ 4105 pins = "gpio48", "gpio49", "gpio50"; 4106 function = "qup1_se4"; 4107 drive-strength = <6>; 4108 bias-disable; 4109 }; 4110 4111 qup_spi5_cs: qup-spi5-cs-state { 4112 pins = "gpio55"; 4113 function = "qup1_se5"; 4114 drive-strength = <6>; 4115 bias-disable; 4116 }; 4117 4118 qup_spi5_data_clk: qup-spi5-data-clk-state { 4119 /* MISO, MOSI, CLK */ 4120 pins = "gpio52", "gpio53", "gpio54"; 4121 function = "qup1_se5"; 4122 drive-strength = <6>; 4123 bias-disable; 4124 }; 4125 4126 qup_spi6_cs: qup-spi6-cs-state { 4127 pins = "gpio59"; 4128 function = "qup1_se6"; 4129 drive-strength = <6>; 4130 bias-disable; 4131 }; 4132 4133 qup_spi6_data_clk: qup-spi6-data-clk-state { 4134 /* MISO, MOSI, CLK */ 4135 pins = "gpio56", "gpio57", "gpio58"; 4136 function = "qup1_se6"; 4137 drive-strength = <6>; 4138 bias-disable; 4139 }; 4140 4141 qup_spi7_cs: qup-spi7-cs-state { 4142 pins = "gpio63"; 4143 function = "qup1_se7"; 4144 drive-strength = <6>; 4145 bias-disable; 4146 }; 4147 4148 qup_spi7_data_clk: qup-spi7-data-clk-state { 4149 /* MISO, MOSI, CLK */ 4150 pins = "gpio60", "gpio61", "gpio62"; 4151 function = "qup1_se7"; 4152 drive-strength = <6>; 4153 bias-disable; 4154 }; 4155 4156 qup_spi8_cs: qup-spi8-cs-state { 4157 pins = "gpio3"; 4158 function = "qup2_se0"; 4159 drive-strength = <6>; 4160 bias-disable; 4161 }; 4162 4163 qup_spi8_data_clk: qup-spi8-data-clk-state { 4164 /* MISO, MOSI, CLK */ 4165 pins = "gpio0", "gpio1", "gpio2"; 4166 function = "qup2_se0"; 4167 drive-strength = <6>; 4168 bias-disable; 4169 }; 4170 4171 qup_spi9_cs: qup-spi9-cs-state { 4172 pins = "gpio7"; 4173 function = "qup2_se1"; 4174 drive-strength = <6>; 4175 bias-disable; 4176 }; 4177 4178 qup_spi9_data_clk: qup-spi9-data-clk-state { 4179 /* MISO, MOSI, CLK */ 4180 pins = "gpio4", "gpio5", "gpio6"; 4181 function = "qup2_se1"; 4182 drive-strength = <6>; 4183 bias-disable; 4184 }; 4185 4186 qup_spi10_cs: qup-spi10-cs-state { 4187 pins = "gpio11"; 4188 function = "qup2_se2"; 4189 drive-strength = <6>; 4190 bias-disable; 4191 }; 4192 4193 qup_spi10_data_clk: qup-spi10-data-clk-state { 4194 /* MISO, MOSI, CLK */ 4195 pins = "gpio8", "gpio9", "gpio10"; 4196 function = "qup2_se2"; 4197 drive-strength = <6>; 4198 bias-disable; 4199 }; 4200 4201 qup_spi11_cs: qup-spi11-cs-state { 4202 pins = "gpio15"; 4203 function = "qup2_se3"; 4204 drive-strength = <6>; 4205 bias-disable; 4206 }; 4207 4208 qup_spi11_data_clk: qup-spi11-data-clk-state { 4209 /* MISO, MOSI, CLK */ 4210 pins = "gpio12", "gpio13", "gpio14"; 4211 function = "qup2_se3"; 4212 drive-strength = <6>; 4213 bias-disable; 4214 }; 4215 4216 qup_spi12_cs: qup-spi12-cs-state { 4217 pins = "gpio19"; 4218 function = "qup2_se4"; 4219 drive-strength = <6>; 4220 bias-disable; 4221 }; 4222 4223 qup_spi12_data_clk: qup-spi12-data-clk-state { 4224 /* MISO, MOSI, CLK */ 4225 pins = "gpio16", "gpio17", "gpio18"; 4226 function = "qup2_se4"; 4227 drive-strength = <6>; 4228 bias-disable; 4229 }; 4230 4231 qup_spi13_cs: qup-spi13-cs-state { 4232 pins = "gpio23"; 4233 function = "qup2_se5"; 4234 drive-strength = <6>; 4235 bias-disable; 4236 }; 4237 4238 qup_spi13_data_clk: qup-spi13-data-clk-state { 4239 /* MISO, MOSI, CLK */ 4240 pins = "gpio20", "gpio21", "gpio22"; 4241 function = "qup2_se5"; 4242 drive-strength = <6>; 4243 bias-disable; 4244 }; 4245 4246 qup_spi14_cs: qup-spi14-cs-state { 4247 pins = "gpio27"; 4248 function = "qup2_se6"; 4249 drive-strength = <6>; 4250 bias-disable; 4251 }; 4252 4253 qup_spi14_data_clk: qup-spi14-data-clk-state { 4254 /* MISO, MOSI, CLK */ 4255 pins = "gpio24", "gpio25", "gpio26"; 4256 function = "qup2_se6"; 4257 drive-strength = <6>; 4258 bias-disable; 4259 }; 4260 4261 qup_uart14_default: qup-uart14-default-state { 4262 /* TX, RX */ 4263 pins = "gpio26", "gpio27"; 4264 function = "qup2_se6"; 4265 drive-strength = <2>; 4266 bias-pull-up; 4267 }; 4268 4269 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 4270 /* CTS, RTS */ 4271 pins = "gpio24", "gpio25"; 4272 function = "qup2_se6"; 4273 drive-strength = <2>; 4274 bias-pull-down; 4275 }; 4276 4277 qup_uart15_default: qup-uart15-default-state { 4278 /* TX, RX */ 4279 pins = "gpio30", "gpio31"; 4280 function = "qup2_se7"; 4281 drive-strength = <2>; 4282 bias-disable; 4283 }; 4284 4285 sdc2_sleep: sdc2-sleep-state { 4286 clk-pins { 4287 pins = "sdc2_clk"; 4288 drive-strength = <2>; 4289 bias-disable; 4290 }; 4291 4292 cmd-pins { 4293 pins = "sdc2_cmd"; 4294 drive-strength = <2>; 4295 bias-pull-up; 4296 }; 4297 4298 data-pins { 4299 pins = "sdc2_data"; 4300 drive-strength = <2>; 4301 bias-pull-up; 4302 }; 4303 }; 4304 4305 sdc2_default: sdc2-default-state { 4306 clk-pins { 4307 pins = "sdc2_clk"; 4308 drive-strength = <16>; 4309 bias-disable; 4310 }; 4311 4312 cmd-pins { 4313 pins = "sdc2_cmd"; 4314 drive-strength = <10>; 4315 bias-pull-up; 4316 }; 4317 4318 data-pins { 4319 pins = "sdc2_data"; 4320 drive-strength = <10>; 4321 bias-pull-up; 4322 }; 4323 }; 4324 }; 4325 4326 apps_smmu: iommu@15000000 { 4327 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4328 reg = <0 0x15000000 0 0x100000>; 4329 4330 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4331 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4332 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4333 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4334 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4335 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4336 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4337 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4338 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4339 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4340 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4341 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4342 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4343 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4344 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4345 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4346 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4347 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4348 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4349 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4350 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4351 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4352 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4353 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4354 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4355 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4356 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4357 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4358 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4359 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4360 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4361 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4362 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4363 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4364 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4365 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4366 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4367 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4368 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4369 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4370 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4371 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4372 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4373 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4374 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4375 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4376 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4377 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4378 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4379 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4380 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4381 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4382 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4383 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4384 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4385 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4386 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4387 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4388 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4389 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4390 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4391 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4392 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4393 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4394 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4395 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4396 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4397 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4398 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4399 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4400 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4401 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4402 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4403 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4404 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4405 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4406 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4407 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4408 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4409 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4410 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4411 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4412 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4413 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4414 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4415 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4416 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4417 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4418 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4419 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4420 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4421 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4422 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4423 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4424 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4425 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4426 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 4427 4428 #iommu-cells = <2>; 4429 #global-interrupts = <1>; 4430 4431 dma-coherent; 4432 }; 4433 4434 intc: interrupt-controller@17100000 { 4435 compatible = "arm,gic-v3"; 4436 reg = <0 0x17100000 0 0x10000>, /* GICD */ 4437 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 4438 4439 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4440 4441 #interrupt-cells = <3>; 4442 interrupt-controller; 4443 4444 #redistributor-regions = <1>; 4445 redistributor-stride = <0 0x40000>; 4446 4447 #address-cells = <2>; 4448 #size-cells = <2>; 4449 ranges; 4450 4451 gic_its: msi-controller@17140000 { 4452 compatible = "arm,gic-v3-its"; 4453 reg = <0 0x17140000 0 0x20000>; 4454 4455 msi-controller; 4456 #msi-cells = <1>; 4457 }; 4458 }; 4459 4460 timer@17420000 { 4461 compatible = "arm,armv7-timer-mem"; 4462 reg = <0 0x17420000 0 0x1000>; 4463 4464 ranges = <0 0 0 0x20000000>; 4465 #address-cells = <1>; 4466 #size-cells = <1>; 4467 4468 frame@17421000 { 4469 reg = <0x17421000 0x1000>, 4470 <0x17422000 0x1000>; 4471 4472 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4473 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4474 4475 frame-number = <0>; 4476 }; 4477 4478 frame@17423000 { 4479 reg = <0x17423000 0x1000>; 4480 4481 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4482 4483 frame-number = <1>; 4484 4485 status = "disabled"; 4486 }; 4487 4488 frame@17425000 { 4489 reg = <0x17425000 0x1000>; 4490 4491 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4492 4493 frame-number = <2>; 4494 4495 status = "disabled"; 4496 }; 4497 4498 frame@17427000 { 4499 reg = <0x17427000 0x1000>; 4500 4501 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4502 4503 frame-number = <3>; 4504 4505 status = "disabled"; 4506 }; 4507 4508 frame@17429000 { 4509 reg = <0x17429000 0x1000>; 4510 4511 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4512 4513 frame-number = <4>; 4514 4515 status = "disabled"; 4516 }; 4517 4518 frame@1742b000 { 4519 reg = <0x1742b000 0x1000>; 4520 4521 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4522 4523 frame-number = <5>; 4524 4525 status = "disabled"; 4526 }; 4527 4528 frame@1742d000 { 4529 reg = <0x1742d000 0x1000>; 4530 4531 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4532 4533 frame-number = <6>; 4534 4535 status = "disabled"; 4536 }; 4537 }; 4538 4539 apps_rsc: rsc@17a00000 { 4540 compatible = "qcom,rpmh-rsc"; 4541 reg = <0 0x17a00000 0 0x10000>, 4542 <0 0x17a10000 0 0x10000>, 4543 <0 0x17a20000 0 0x10000>, 4544 <0 0x17a30000 0 0x10000>; 4545 reg-names = "drv-0", 4546 "drv-1", 4547 "drv-2"; 4548 4549 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4550 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4551 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4552 4553 power-domains = <&CLUSTER_PD>; 4554 4555 qcom,tcs-offset = <0xd00>; 4556 qcom,drv-id = <2>; 4557 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4558 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4559 4560 label = "apps_rsc"; 4561 4562 apps_bcm_voter: bcm-voter { 4563 compatible = "qcom,bcm-voter"; 4564 }; 4565 4566 rpmhcc: clock-controller { 4567 compatible = "qcom,sm8650-rpmh-clk"; 4568 4569 clocks = <&xo_board>; 4570 clock-names = "xo"; 4571 4572 #clock-cells = <1>; 4573 }; 4574 4575 rpmhpd: power-controller { 4576 compatible = "qcom,sm8650-rpmhpd"; 4577 4578 operating-points-v2 = <&rpmhpd_opp_table>; 4579 4580 #power-domain-cells = <1>; 4581 4582 rpmhpd_opp_table: opp-table { 4583 compatible = "operating-points-v2"; 4584 4585 rpmhpd_opp_ret: opp-16 { 4586 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4587 }; 4588 4589 rpmhpd_opp_min_svs: opp-48 { 4590 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4591 }; 4592 4593 rpmhpd_opp_low_svs_d2: opp-52 { 4594 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 4595 }; 4596 4597 rpmhpd_opp_low_svs_d1: opp-56 { 4598 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4599 }; 4600 4601 rpmhpd_opp_low_svs_d0: opp-60 { 4602 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 4603 }; 4604 4605 rpmhpd_opp_low_svs: opp-64 { 4606 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4607 }; 4608 4609 rpmhpd_opp_low_svs_l1: opp-80 { 4610 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4611 }; 4612 4613 rpmhpd_opp_svs: opp-128 { 4614 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4615 }; 4616 4617 rpmhpd_opp_svs_l0: opp-144 { 4618 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4619 }; 4620 4621 rpmhpd_opp_svs_l1: opp-192 { 4622 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4623 }; 4624 4625 rpmhpd_opp_nom: opp-256 { 4626 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4627 }; 4628 4629 rpmhpd_opp_nom_l1: opp-320 { 4630 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4631 }; 4632 4633 rpmhpd_opp_nom_l2: opp-336 { 4634 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4635 }; 4636 4637 rpmhpd_opp_turbo: opp-384 { 4638 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4639 }; 4640 4641 rpmhpd_opp_turbo_l1: opp-416 { 4642 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4643 }; 4644 }; 4645 }; 4646 }; 4647 4648 cpufreq_hw: cpufreq@17d91000 { 4649 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss"; 4650 reg = <0 0x17d91000 0 0x1000>, 4651 <0 0x17d92000 0 0x1000>, 4652 <0 0x17d93000 0 0x1000>, 4653 <0 0x17d94000 0 0x1000>; 4654 reg-names = "freq-domain0", 4655 "freq-domain1", 4656 "freq-domain2", 4657 "freq-domain3"; 4658 4659 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4660 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4661 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 4662 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 4663 interrupt-names = "dcvsh-irq-0", 4664 "dcvsh-irq-1", 4665 "dcvsh-irq-2", 4666 "dcvsh-irq-3"; 4667 4668 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 4669 clock-names = "xo", "alternate"; 4670 4671 #freq-domain-cells = <1>; 4672 #clock-cells = <1>; 4673 }; 4674 4675 pmu@24091000 { 4676 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4677 reg = <0 0x24091000 0 0x1000>; 4678 4679 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4680 4681 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 4682 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4683 4684 operating-points-v2 = <&llcc_bwmon_opp_table>; 4685 4686 llcc_bwmon_opp_table: opp-table { 4687 compatible = "operating-points-v2"; 4688 4689 opp-0 { 4690 opp-peak-kBps = <2086000>; 4691 }; 4692 4693 opp-1 { 4694 opp-peak-kBps = <2929000>; 4695 }; 4696 4697 opp-2 { 4698 opp-peak-kBps = <5931000>; 4699 }; 4700 4701 opp-3 { 4702 opp-peak-kBps = <6515000>; 4703 }; 4704 4705 opp-4 { 4706 opp-peak-kBps = <7980000>; 4707 }; 4708 4709 opp-5 { 4710 opp-peak-kBps = <10437000>; 4711 }; 4712 4713 opp-6 { 4714 opp-peak-kBps = <12157000>; 4715 }; 4716 4717 opp-7 { 4718 opp-peak-kBps = <14060000>; 4719 }; 4720 4721 opp-8 { 4722 opp-peak-kBps = <16113000>; 4723 }; 4724 }; 4725 }; 4726 4727 pmu@240b7400 { 4728 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; 4729 reg = <0 0x240b7400 0 0x600>; 4730 4731 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4732 4733 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4734 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4735 4736 operating-points-v2 = <&cpu_bwmon_opp_table>; 4737 4738 cpu_bwmon_opp_table: opp-table { 4739 compatible = "operating-points-v2"; 4740 4741 opp-0 { 4742 opp-peak-kBps = <4577000>; 4743 }; 4744 4745 opp-1 { 4746 opp-peak-kBps = <7110000>; 4747 }; 4748 4749 opp-2 { 4750 opp-peak-kBps = <9155000>; 4751 }; 4752 4753 opp-3 { 4754 opp-peak-kBps = <12298000>; 4755 }; 4756 4757 opp-4 { 4758 opp-peak-kBps = <14236000>; 4759 }; 4760 4761 opp-5 { 4762 opp-peak-kBps = <16265000>; 4763 }; 4764 }; 4765 }; 4766 4767 gem_noc: interconnect@24100000 { 4768 compatible = "qcom,sm8650-gem-noc"; 4769 reg = <0 0x24100000 0 0xc5080>; 4770 4771 qcom,bcm-voters = <&apps_bcm_voter>; 4772 4773 #interconnect-cells = <2>; 4774 }; 4775 4776 system-cache-controller@25000000 { 4777 compatible = "qcom,sm8650-llcc"; 4778 reg = <0 0x25000000 0 0x200000>, 4779 <0 0x25400000 0 0x200000>, 4780 <0 0x25200000 0 0x200000>, 4781 <0 0x25600000 0 0x200000>, 4782 <0 0x25800000 0 0x200000>; 4783 reg-names = "llcc0_base", 4784 "llcc1_base", 4785 "llcc2_base", 4786 "llcc3_base", 4787 "llcc_broadcast_base"; 4788 4789 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4790 }; 4791 4792 remoteproc_adsp: remoteproc@30000000 { 4793 compatible = "qcom,sm8650-adsp-pas"; 4794 reg = <0 0x30000000 0 0x100>; 4795 4796 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4797 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4798 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4799 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4800 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4801 interrupt-names = "wdog", 4802 "fatal", 4803 "ready", 4804 "handover", 4805 "stop-ack"; 4806 4807 clocks = <&rpmhcc RPMH_CXO_CLK>; 4808 clock-names = "xo"; 4809 4810 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 4811 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4812 4813 power-domains = <&rpmhpd RPMHPD_LCX>, 4814 <&rpmhpd RPMHPD_LMX>; 4815 power-domain-names = "lcx", 4816 "lmx"; 4817 4818 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 4819 4820 qcom,qmp = <&aoss_qmp>; 4821 4822 qcom,smem-states = <&smp2p_adsp_out 0>; 4823 qcom,smem-state-names = "stop"; 4824 4825 status = "disabled"; 4826 4827 remoteproc_adsp_glink: glink-edge { 4828 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4829 IPCC_MPROC_SIGNAL_GLINK_QMP 4830 IRQ_TYPE_EDGE_RISING>; 4831 4832 mboxes = <&ipcc IPCC_CLIENT_LPASS 4833 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4834 4835 qcom,remote-pid = <2>; 4836 4837 label = "lpass"; 4838 4839 fastrpc { 4840 compatible = "qcom,fastrpc"; 4841 4842 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4843 4844 label = "adsp"; 4845 4846 #address-cells = <1>; 4847 #size-cells = <0>; 4848 4849 compute-cb@3 { 4850 compatible = "qcom,fastrpc-compute-cb"; 4851 reg = <3>; 4852 4853 iommus = <&apps_smmu 0x1003 0x80>, 4854 <&apps_smmu 0x1043 0x20>; 4855 dma-coherent; 4856 }; 4857 4858 compute-cb@4 { 4859 compatible = "qcom,fastrpc-compute-cb"; 4860 reg = <4>; 4861 4862 iommus = <&apps_smmu 0x1004 0x80>, 4863 <&apps_smmu 0x1044 0x20>; 4864 dma-coherent; 4865 }; 4866 4867 compute-cb@5 { 4868 compatible = "qcom,fastrpc-compute-cb"; 4869 reg = <5>; 4870 4871 iommus = <&apps_smmu 0x1005 0x80>, 4872 <&apps_smmu 0x1045 0x20>; 4873 dma-coherent; 4874 }; 4875 4876 compute-cb@6 { 4877 compatible = "qcom,fastrpc-compute-cb"; 4878 reg = <6>; 4879 4880 iommus = <&apps_smmu 0x1006 0x80>, 4881 <&apps_smmu 0x1046 0x20>; 4882 dma-coherent; 4883 }; 4884 4885 compute-cb@7 { 4886 compatible = "qcom,fastrpc-compute-cb"; 4887 reg = <7>; 4888 4889 iommus = <&apps_smmu 0x1007 0x40>, 4890 <&apps_smmu 0x1067 0x0>, 4891 <&apps_smmu 0x1087 0x0>; 4892 dma-coherent; 4893 }; 4894 }; 4895 4896 gpr { 4897 compatible = "qcom,gpr"; 4898 qcom,glink-channels = "adsp_apps"; 4899 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4900 qcom,intents = <512 20>; 4901 #address-cells = <1>; 4902 #size-cells = <0>; 4903 4904 q6apm: service@1 { 4905 compatible = "qcom,q6apm"; 4906 reg = <GPR_APM_MODULE_IID>; 4907 #sound-dai-cells = <0>; 4908 qcom,protection-domain = "avs/audio", 4909 "msm/adsp/audio_pd"; 4910 4911 q6apmbedai: bedais { 4912 compatible = "qcom,q6apm-lpass-dais"; 4913 #sound-dai-cells = <1>; 4914 }; 4915 4916 q6apmdai: dais { 4917 compatible = "qcom,q6apm-dais"; 4918 iommus = <&apps_smmu 0x1001 0x80>, 4919 <&apps_smmu 0x1061 0x0>; 4920 }; 4921 }; 4922 4923 q6prm: service@2 { 4924 compatible = "qcom,q6prm"; 4925 reg = <GPR_PRM_MODULE_IID>; 4926 qcom,protection-domain = "avs/audio", 4927 "msm/adsp/audio_pd"; 4928 4929 q6prmcc: clock-controller { 4930 compatible = "qcom,q6prm-lpass-clocks"; 4931 #clock-cells = <2>; 4932 }; 4933 }; 4934 }; 4935 }; 4936 }; 4937 4938 nsp_noc: interconnect@320c0000 { 4939 compatible = "qcom,sm8650-nsp-noc"; 4940 reg = <0 0x320c0000 0 0xf080>; 4941 4942 qcom,bcm-voters = <&apps_bcm_voter>; 4943 4944 #interconnect-cells = <2>; 4945 }; 4946 4947 remoteproc_cdsp: remoteproc@32300000 { 4948 compatible = "qcom,sm8650-cdsp-pas"; 4949 reg = <0 0x32300000 0 0x1400000>; 4950 4951 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4952 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 4953 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 4954 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 4955 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 4956 interrupt-names = "wdog", 4957 "fatal", 4958 "ready", 4959 "handover", 4960 "stop-ack"; 4961 4962 clocks = <&rpmhcc RPMH_CXO_CLK>; 4963 clock-names = "xo"; 4964 4965 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 4966 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4967 4968 power-domains = <&rpmhpd RPMHPD_CX>, 4969 <&rpmhpd RPMHPD_MXC>, 4970 <&rpmhpd RPMHPD_NSP>; 4971 power-domain-names = "cx", 4972 "mxc", 4973 "nsp"; 4974 4975 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; 4976 4977 qcom,qmp = <&aoss_qmp>; 4978 4979 qcom,smem-states = <&smp2p_cdsp_out 0>; 4980 qcom,smem-state-names = "stop"; 4981 4982 status = "disabled"; 4983 4984 glink-edge { 4985 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4986 IPCC_MPROC_SIGNAL_GLINK_QMP 4987 IRQ_TYPE_EDGE_RISING>; 4988 4989 mboxes = <&ipcc IPCC_CLIENT_CDSP 4990 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4991 4992 qcom,remote-pid = <5>; 4993 4994 label = "cdsp"; 4995 4996 fastrpc { 4997 compatible = "qcom,fastrpc"; 4998 4999 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5000 5001 label = "cdsp"; 5002 5003 #address-cells = <1>; 5004 #size-cells = <0>; 5005 5006 compute-cb@1 { 5007 compatible = "qcom,fastrpc-compute-cb"; 5008 reg = <1>; 5009 5010 iommus = <&apps_smmu 0x1961 0x0>, 5011 <&apps_smmu 0x0c01 0x20>, 5012 <&apps_smmu 0x19c1 0x0>; 5013 dma-coherent; 5014 }; 5015 5016 compute-cb@2 { 5017 compatible = "qcom,fastrpc-compute-cb"; 5018 reg = <2>; 5019 5020 iommus = <&apps_smmu 0x1962 0x0>, 5021 <&apps_smmu 0x0c02 0x20>, 5022 <&apps_smmu 0x19c2 0x0>; 5023 dma-coherent; 5024 }; 5025 5026 compute-cb@3 { 5027 compatible = "qcom,fastrpc-compute-cb"; 5028 reg = <3>; 5029 5030 iommus = <&apps_smmu 0x1963 0x0>, 5031 <&apps_smmu 0x0c03 0x20>, 5032 <&apps_smmu 0x19c3 0x0>; 5033 dma-coherent; 5034 }; 5035 5036 compute-cb@4 { 5037 compatible = "qcom,fastrpc-compute-cb"; 5038 reg = <4>; 5039 5040 iommus = <&apps_smmu 0x1964 0x0>, 5041 <&apps_smmu 0x0c04 0x20>, 5042 <&apps_smmu 0x19c4 0x0>; 5043 dma-coherent; 5044 }; 5045 5046 compute-cb@5 { 5047 compatible = "qcom,fastrpc-compute-cb"; 5048 reg = <5>; 5049 5050 iommus = <&apps_smmu 0x1965 0x0>, 5051 <&apps_smmu 0x0c05 0x20>, 5052 <&apps_smmu 0x19c5 0x0>; 5053 dma-coherent; 5054 }; 5055 5056 compute-cb@6 { 5057 compatible = "qcom,fastrpc-compute-cb"; 5058 reg = <6>; 5059 5060 iommus = <&apps_smmu 0x1966 0x0>, 5061 <&apps_smmu 0x0c06 0x20>, 5062 <&apps_smmu 0x19c6 0x0>; 5063 dma-coherent; 5064 }; 5065 5066 compute-cb@7 { 5067 compatible = "qcom,fastrpc-compute-cb"; 5068 reg = <7>; 5069 5070 iommus = <&apps_smmu 0x1967 0x0>, 5071 <&apps_smmu 0x0c07 0x20>, 5072 <&apps_smmu 0x19c7 0x0>; 5073 dma-coherent; 5074 }; 5075 5076 compute-cb@8 { 5077 compatible = "qcom,fastrpc-compute-cb"; 5078 reg = <8>; 5079 5080 iommus = <&apps_smmu 0x1968 0x0>, 5081 <&apps_smmu 0x0c08 0x20>, 5082 <&apps_smmu 0x19c8 0x0>; 5083 dma-coherent; 5084 }; 5085 }; 5086 }; 5087 }; 5088 }; 5089 5090 thermal-zones { 5091 aoss0-thermal { 5092 polling-delay-passive = <0>; 5093 polling-delay = <0>; 5094 thermal-sensors = <&tsens0 0>; 5095 5096 trips { 5097 trip-point0 { 5098 temperature = <90000>; 5099 hysteresis = <2000>; 5100 type = "hot"; 5101 }; 5102 5103 aoss0-critical { 5104 temperature = <110000>; 5105 hysteresis = <0>; 5106 type = "critical"; 5107 }; 5108 }; 5109 }; 5110 5111 cpuss0-thermal { 5112 polling-delay-passive = <0>; 5113 polling-delay = <0>; 5114 thermal-sensors = <&tsens0 1>; 5115 5116 trips { 5117 trip-point0 { 5118 temperature = <90000>; 5119 hysteresis = <2000>; 5120 type = "hot"; 5121 }; 5122 5123 cpuss0-critical { 5124 temperature = <110000>; 5125 hysteresis = <0>; 5126 type = "critical"; 5127 }; 5128 }; 5129 }; 5130 5131 cpuss1-thermal { 5132 polling-delay-passive = <0>; 5133 polling-delay = <0>; 5134 thermal-sensors = <&tsens0 2>; 5135 5136 trips { 5137 trip-point0 { 5138 temperature = <90000>; 5139 hysteresis = <2000>; 5140 type = "hot"; 5141 }; 5142 5143 cpuss1-critical { 5144 temperature = <110000>; 5145 hysteresis = <0>; 5146 type = "critical"; 5147 }; 5148 }; 5149 }; 5150 5151 cpuss2-thermal { 5152 polling-delay-passive = <0>; 5153 polling-delay = <0>; 5154 thermal-sensors = <&tsens0 3>; 5155 5156 trips { 5157 trip-point0 { 5158 temperature = <90000>; 5159 hysteresis = <2000>; 5160 type = "hot"; 5161 }; 5162 5163 cpuss2-critical { 5164 temperature = <110000>; 5165 hysteresis = <0>; 5166 type = "critical"; 5167 }; 5168 }; 5169 }; 5170 5171 cpuss3-thermal { 5172 polling-delay-passive = <0>; 5173 polling-delay = <0>; 5174 thermal-sensors = <&tsens0 4>; 5175 5176 trips { 5177 trip-point0 { 5178 temperature = <90000>; 5179 hysteresis = <2000>; 5180 type = "hot"; 5181 }; 5182 5183 cpuss3-critical { 5184 temperature = <110000>; 5185 hysteresis = <0>; 5186 type = "critical"; 5187 }; 5188 }; 5189 }; 5190 5191 cpu2-top-thermal { 5192 polling-delay-passive = <0>; 5193 polling-delay = <0>; 5194 thermal-sensors = <&tsens0 5>; 5195 5196 trips { 5197 trip-point0 { 5198 temperature = <90000>; 5199 hysteresis = <2000>; 5200 type = "passive"; 5201 }; 5202 5203 trip-point1 { 5204 temperature = <95000>; 5205 hysteresis = <2000>; 5206 type = "passive"; 5207 }; 5208 5209 cpu2-critical { 5210 temperature = <110000>; 5211 hysteresis = <1000>; 5212 type = "critical"; 5213 }; 5214 }; 5215 }; 5216 5217 cpu2-bottom-thermal { 5218 polling-delay-passive = <0>; 5219 polling-delay = <0>; 5220 thermal-sensors = <&tsens0 6>; 5221 5222 trips { 5223 trip-point0 { 5224 temperature = <90000>; 5225 hysteresis = <2000>; 5226 type = "passive"; 5227 }; 5228 5229 trip-point1 { 5230 temperature = <95000>; 5231 hysteresis = <2000>; 5232 type = "passive"; 5233 }; 5234 5235 cpu2-critical { 5236 temperature = <110000>; 5237 hysteresis = <1000>; 5238 type = "critical"; 5239 }; 5240 }; 5241 }; 5242 5243 cpu3-top-thermal { 5244 polling-delay-passive = <0>; 5245 polling-delay = <0>; 5246 thermal-sensors = <&tsens0 7>; 5247 5248 trips { 5249 trip-point0 { 5250 temperature = <90000>; 5251 hysteresis = <2000>; 5252 type = "passive"; 5253 }; 5254 5255 trip-point1 { 5256 temperature = <95000>; 5257 hysteresis = <2000>; 5258 type = "passive"; 5259 }; 5260 5261 cpu3-critical { 5262 temperature = <110000>; 5263 hysteresis = <1000>; 5264 type = "critical"; 5265 }; 5266 }; 5267 }; 5268 5269 cpu3-bottom-thermal { 5270 polling-delay-passive = <0>; 5271 polling-delay = <0>; 5272 thermal-sensors = <&tsens0 8>; 5273 5274 trips { 5275 trip-point0 { 5276 temperature = <90000>; 5277 hysteresis = <2000>; 5278 type = "passive"; 5279 }; 5280 5281 trip-point1 { 5282 temperature = <95000>; 5283 hysteresis = <2000>; 5284 type = "passive"; 5285 }; 5286 5287 cpu3-critical { 5288 temperature = <110000>; 5289 hysteresis = <1000>; 5290 type = "critical"; 5291 }; 5292 }; 5293 }; 5294 5295 cpu4-top-thermal { 5296 polling-delay-passive = <0>; 5297 polling-delay = <0>; 5298 thermal-sensors = <&tsens0 9>; 5299 5300 trips { 5301 trip-point0 { 5302 temperature = <90000>; 5303 hysteresis = <2000>; 5304 type = "passive"; 5305 }; 5306 5307 trip-point1 { 5308 temperature = <95000>; 5309 hysteresis = <2000>; 5310 type = "passive"; 5311 }; 5312 5313 cpu4-critical { 5314 temperature = <110000>; 5315 hysteresis = <1000>; 5316 type = "critical"; 5317 }; 5318 }; 5319 }; 5320 5321 cpu4-bottom-thermal { 5322 polling-delay-passive = <0>; 5323 polling-delay = <0>; 5324 thermal-sensors = <&tsens0 10>; 5325 5326 trips { 5327 trip-point0 { 5328 temperature = <90000>; 5329 hysteresis = <2000>; 5330 type = "passive"; 5331 }; 5332 5333 trip-point1 { 5334 temperature = <95000>; 5335 hysteresis = <2000>; 5336 type = "passive"; 5337 }; 5338 5339 cpu4-critical { 5340 temperature = <110000>; 5341 hysteresis = <1000>; 5342 type = "critical"; 5343 }; 5344 }; 5345 }; 5346 5347 cpu5-top-thermal { 5348 polling-delay-passive = <0>; 5349 polling-delay = <0>; 5350 thermal-sensors = <&tsens0 11>; 5351 5352 trips { 5353 trip-point0 { 5354 temperature = <90000>; 5355 hysteresis = <2000>; 5356 type = "passive"; 5357 }; 5358 5359 trip-point1 { 5360 temperature = <95000>; 5361 hysteresis = <2000>; 5362 type = "passive"; 5363 }; 5364 5365 cpu5-critical { 5366 temperature = <110000>; 5367 hysteresis = <1000>; 5368 type = "critical"; 5369 }; 5370 }; 5371 }; 5372 5373 cpu5-bottom-thermal { 5374 polling-delay-passive = <0>; 5375 polling-delay = <0>; 5376 thermal-sensors = <&tsens0 12>; 5377 5378 trips { 5379 trip-point0 { 5380 temperature = <90000>; 5381 hysteresis = <2000>; 5382 type = "passive"; 5383 }; 5384 5385 trip-point1 { 5386 temperature = <95000>; 5387 hysteresis = <2000>; 5388 type = "passive"; 5389 }; 5390 5391 cpu5-critical { 5392 temperature = <110000>; 5393 hysteresis = <1000>; 5394 type = "critical"; 5395 }; 5396 }; 5397 }; 5398 5399 cpu6-top-thermal { 5400 polling-delay-passive = <0>; 5401 polling-delay = <0>; 5402 thermal-sensors = <&tsens0 13>; 5403 5404 trips { 5405 trip-point0 { 5406 temperature = <90000>; 5407 hysteresis = <2000>; 5408 type = "passive"; 5409 }; 5410 5411 trip-point1 { 5412 temperature = <95000>; 5413 hysteresis = <2000>; 5414 type = "passive"; 5415 }; 5416 5417 cpu6-critical { 5418 temperature = <110000>; 5419 hysteresis = <1000>; 5420 type = "critical"; 5421 }; 5422 }; 5423 }; 5424 5425 cpu6-bottom-thermal { 5426 polling-delay-passive = <0>; 5427 polling-delay = <0>; 5428 thermal-sensors = <&tsens0 14>; 5429 5430 trips { 5431 trip-point0 { 5432 temperature = <90000>; 5433 hysteresis = <2000>; 5434 type = "passive"; 5435 }; 5436 5437 trip-point1 { 5438 temperature = <95000>; 5439 hysteresis = <2000>; 5440 type = "passive"; 5441 }; 5442 5443 cpu6-critical { 5444 temperature = <110000>; 5445 hysteresis = <1000>; 5446 type = "critical"; 5447 }; 5448 }; 5449 }; 5450 5451 aoss1-thermal { 5452 polling-delay-passive = <0>; 5453 polling-delay = <0>; 5454 thermal-sensors = <&tsens1 0>; 5455 5456 trips { 5457 trip-point0 { 5458 temperature = <90000>; 5459 hysteresis = <2000>; 5460 type = "hot"; 5461 }; 5462 5463 aoss1-critical { 5464 temperature = <110000>; 5465 hysteresis = <0>; 5466 type = "critical"; 5467 }; 5468 }; 5469 }; 5470 5471 cpu7-top-thermal { 5472 polling-delay-passive = <0>; 5473 polling-delay = <0>; 5474 thermal-sensors = <&tsens1 1>; 5475 5476 trips { 5477 trip-point0 { 5478 temperature = <90000>; 5479 hysteresis = <2000>; 5480 type = "passive"; 5481 }; 5482 5483 trip-point1 { 5484 temperature = <95000>; 5485 hysteresis = <2000>; 5486 type = "passive"; 5487 }; 5488 5489 cpu7-critical { 5490 temperature = <110000>; 5491 hysteresis = <1000>; 5492 type = "critical"; 5493 }; 5494 }; 5495 }; 5496 5497 cpu7-middle-thermal { 5498 polling-delay-passive = <0>; 5499 polling-delay = <0>; 5500 thermal-sensors = <&tsens1 2>; 5501 5502 trips { 5503 trip-point0 { 5504 temperature = <90000>; 5505 hysteresis = <2000>; 5506 type = "passive"; 5507 }; 5508 5509 trip-point1 { 5510 temperature = <95000>; 5511 hysteresis = <2000>; 5512 type = "passive"; 5513 }; 5514 5515 cpu7-critical { 5516 temperature = <110000>; 5517 hysteresis = <1000>; 5518 type = "critical"; 5519 }; 5520 }; 5521 }; 5522 5523 cpu7-bottom-thermal { 5524 polling-delay-passive = <0>; 5525 polling-delay = <0>; 5526 thermal-sensors = <&tsens1 3>; 5527 5528 trips { 5529 trip-point0 { 5530 temperature = <90000>; 5531 hysteresis = <2000>; 5532 type = "passive"; 5533 }; 5534 5535 trip-point1 { 5536 temperature = <95000>; 5537 hysteresis = <2000>; 5538 type = "passive"; 5539 }; 5540 5541 cpu7-critical { 5542 temperature = <110000>; 5543 hysteresis = <1000>; 5544 type = "critical"; 5545 }; 5546 }; 5547 }; 5548 5549 cpu0-thermal { 5550 polling-delay-passive = <0>; 5551 polling-delay = <0>; 5552 thermal-sensors = <&tsens1 4>; 5553 5554 trips { 5555 trip-point0 { 5556 temperature = <90000>; 5557 hysteresis = <2000>; 5558 type = "passive"; 5559 }; 5560 5561 trip-point1 { 5562 temperature = <95000>; 5563 hysteresis = <2000>; 5564 type = "passive"; 5565 }; 5566 5567 cpu0-critical { 5568 temperature = <110000>; 5569 hysteresis = <1000>; 5570 type = "critical"; 5571 }; 5572 }; 5573 }; 5574 5575 cpu1-thermal { 5576 polling-delay-passive = <0>; 5577 polling-delay = <0>; 5578 thermal-sensors = <&tsens1 5>; 5579 5580 trips { 5581 trip-point0 { 5582 temperature = <90000>; 5583 hysteresis = <2000>; 5584 type = "passive"; 5585 }; 5586 5587 trip-point1 { 5588 temperature = <95000>; 5589 hysteresis = <2000>; 5590 type = "passive"; 5591 }; 5592 5593 cpu1-critical { 5594 temperature = <110000>; 5595 hysteresis = <1000>; 5596 type = "critical"; 5597 }; 5598 }; 5599 }; 5600 5601 nsphvx0-thermal { 5602 polling-delay-passive = <10>; 5603 polling-delay = <0>; 5604 thermal-sensors = <&tsens2 6>; 5605 5606 trips { 5607 trip-point0 { 5608 temperature = <90000>; 5609 hysteresis = <2000>; 5610 type = "hot"; 5611 }; 5612 5613 nsphvx1-critical { 5614 temperature = <110000>; 5615 hysteresis = <0>; 5616 type = "critical"; 5617 }; 5618 }; 5619 }; 5620 5621 nsphvx1-thermal { 5622 polling-delay-passive = <10>; 5623 polling-delay = <0>; 5624 thermal-sensors = <&tsens2 7>; 5625 5626 trips { 5627 trip-point0 { 5628 temperature = <90000>; 5629 hysteresis = <2000>; 5630 type = "hot"; 5631 }; 5632 5633 nsphvx1-critical { 5634 temperature = <110000>; 5635 hysteresis = <0>; 5636 type = "critical"; 5637 }; 5638 }; 5639 }; 5640 5641 nsphmx0-thermal { 5642 polling-delay-passive = <10>; 5643 polling-delay = <0>; 5644 thermal-sensors = <&tsens2 8>; 5645 5646 trips { 5647 trip-point0 { 5648 temperature = <90000>; 5649 hysteresis = <2000>; 5650 type = "hot"; 5651 }; 5652 5653 nsphmx0-critical { 5654 temperature = <110000>; 5655 hysteresis = <0>; 5656 type = "critical"; 5657 }; 5658 }; 5659 }; 5660 5661 nsphmx1-thermal { 5662 polling-delay-passive = <10>; 5663 polling-delay = <0>; 5664 thermal-sensors = <&tsens2 9>; 5665 5666 trips { 5667 trip-point0 { 5668 temperature = <90000>; 5669 hysteresis = <2000>; 5670 type = "hot"; 5671 }; 5672 5673 nsphmx1-critical { 5674 temperature = <110000>; 5675 hysteresis = <0>; 5676 type = "critical"; 5677 }; 5678 }; 5679 }; 5680 5681 nsphmx2-thermal { 5682 polling-delay-passive = <10>; 5683 polling-delay = <0>; 5684 thermal-sensors = <&tsens2 10>; 5685 5686 trips { 5687 trip-point0 { 5688 temperature = <90000>; 5689 hysteresis = <2000>; 5690 type = "hot"; 5691 }; 5692 5693 nsphmx2-critical { 5694 temperature = <110000>; 5695 hysteresis = <0>; 5696 type = "critical"; 5697 }; 5698 }; 5699 }; 5700 5701 nsphmx3-thermal { 5702 polling-delay-passive = <10>; 5703 polling-delay = <0>; 5704 thermal-sensors = <&tsens2 11>; 5705 5706 trips { 5707 trip-point0 { 5708 temperature = <90000>; 5709 hysteresis = <2000>; 5710 type = "hot"; 5711 }; 5712 5713 nsphmx3-critical { 5714 temperature = <110000>; 5715 hysteresis = <0>; 5716 type = "critical"; 5717 }; 5718 }; 5719 }; 5720 5721 video-thermal { 5722 polling-delay-passive = <10>; 5723 polling-delay = <0>; 5724 thermal-sensors = <&tsens1 12>; 5725 5726 trips { 5727 trip-point0 { 5728 temperature = <90000>; 5729 hysteresis = <2000>; 5730 type = "hot"; 5731 }; 5732 5733 video-critical { 5734 temperature = <110000>; 5735 hysteresis = <0>; 5736 type = "critical"; 5737 }; 5738 }; 5739 }; 5740 5741 ddr-thermal { 5742 polling-delay-passive = <10>; 5743 polling-delay = <0>; 5744 thermal-sensors = <&tsens1 13>; 5745 5746 trips { 5747 trip-point0 { 5748 temperature = <90000>; 5749 hysteresis = <2000>; 5750 type = "hot"; 5751 }; 5752 5753 ddr-critical { 5754 temperature = <110000>; 5755 hysteresis = <0>; 5756 type = "critical"; 5757 }; 5758 }; 5759 }; 5760 5761 camera0-thermal { 5762 polling-delay-passive = <0>; 5763 polling-delay = <0>; 5764 thermal-sensors = <&tsens1 14>; 5765 5766 trips { 5767 trip-point0 { 5768 temperature = <90000>; 5769 hysteresis = <2000>; 5770 type = "hot"; 5771 }; 5772 5773 camera0-critical { 5774 temperature = <110000>; 5775 hysteresis = <0>; 5776 type = "critical"; 5777 }; 5778 }; 5779 }; 5780 5781 camera1-thermal { 5782 polling-delay-passive = <0>; 5783 polling-delay = <0>; 5784 thermal-sensors = <&tsens1 15>; 5785 5786 trips { 5787 trip-point0 { 5788 temperature = <90000>; 5789 hysteresis = <2000>; 5790 type = "hot"; 5791 }; 5792 5793 camera1-critical { 5794 temperature = <110000>; 5795 hysteresis = <0>; 5796 type = "critical"; 5797 }; 5798 }; 5799 }; 5800 5801 aoss2-thermal { 5802 polling-delay-passive = <0>; 5803 polling-delay = <0>; 5804 thermal-sensors = <&tsens2 0>; 5805 5806 trips { 5807 trip-point0 { 5808 temperature = <90000>; 5809 hysteresis = <2000>; 5810 type = "hot"; 5811 }; 5812 5813 aoss2-critical { 5814 temperature = <110000>; 5815 hysteresis = <0>; 5816 type = "critical"; 5817 }; 5818 }; 5819 }; 5820 5821 gpuss0-thermal { 5822 polling-delay-passive = <10>; 5823 polling-delay = <0>; 5824 thermal-sensors = <&tsens2 1>; 5825 5826 trips { 5827 trip-point0 { 5828 temperature = <90000>; 5829 hysteresis = <2000>; 5830 type = "hot"; 5831 }; 5832 5833 gpuss0-critical { 5834 temperature = <110000>; 5835 hysteresis = <0>; 5836 type = "critical"; 5837 }; 5838 }; 5839 }; 5840 5841 gpuss1-thermal { 5842 polling-delay-passive = <10>; 5843 polling-delay = <0>; 5844 thermal-sensors = <&tsens2 2>; 5845 5846 trips { 5847 trip-point0 { 5848 temperature = <90000>; 5849 hysteresis = <2000>; 5850 type = "hot"; 5851 }; 5852 5853 gpuss1-critical { 5854 temperature = <110000>; 5855 hysteresis = <0>; 5856 type = "critical"; 5857 }; 5858 }; 5859 }; 5860 5861 gpuss2-thermal { 5862 polling-delay-passive = <10>; 5863 polling-delay = <0>; 5864 thermal-sensors = <&tsens2 3>; 5865 5866 trips { 5867 trip-point0 { 5868 temperature = <90000>; 5869 hysteresis = <2000>; 5870 type = "hot"; 5871 }; 5872 5873 gpuss2-critical { 5874 temperature = <110000>; 5875 hysteresis = <0>; 5876 type = "critical"; 5877 }; 5878 }; 5879 }; 5880 5881 gpuss3-thermal { 5882 polling-delay-passive = <10>; 5883 polling-delay = <0>; 5884 thermal-sensors = <&tsens2 4>; 5885 5886 trips { 5887 trip-point0 { 5888 temperature = <90000>; 5889 hysteresis = <2000>; 5890 type = "hot"; 5891 }; 5892 5893 gpuss3-critical { 5894 temperature = <110000>; 5895 hysteresis = <0>; 5896 type = "critical"; 5897 }; 5898 }; 5899 }; 5900 5901 gpuss4-thermal { 5902 polling-delay-passive = <10>; 5903 polling-delay = <0>; 5904 thermal-sensors = <&tsens2 5>; 5905 5906 trips { 5907 trip-point0 { 5908 temperature = <90000>; 5909 hysteresis = <2000>; 5910 type = "hot"; 5911 }; 5912 5913 gpuss4-critical { 5914 temperature = <110000>; 5915 hysteresis = <0>; 5916 type = "critical"; 5917 }; 5918 }; 5919 }; 5920 5921 gpuss5-thermal { 5922 polling-delay-passive = <10>; 5923 polling-delay = <0>; 5924 thermal-sensors = <&tsens2 6>; 5925 5926 trips { 5927 trip-point0 { 5928 temperature = <90000>; 5929 hysteresis = <2000>; 5930 type = "hot"; 5931 }; 5932 5933 gpuss5-critical { 5934 temperature = <110000>; 5935 hysteresis = <0>; 5936 type = "critical"; 5937 }; 5938 }; 5939 }; 5940 5941 gpuss6-thermal { 5942 polling-delay-passive = <10>; 5943 polling-delay = <0>; 5944 thermal-sensors = <&tsens2 7>; 5945 5946 trips { 5947 trip-point0 { 5948 temperature = <90000>; 5949 hysteresis = <2000>; 5950 type = "hot"; 5951 }; 5952 5953 gpuss6-critical { 5954 temperature = <110000>; 5955 hysteresis = <0>; 5956 type = "critical"; 5957 }; 5958 }; 5959 }; 5960 5961 gpuss7-thermal { 5962 polling-delay-passive = <10>; 5963 polling-delay = <0>; 5964 thermal-sensors = <&tsens2 8>; 5965 5966 trips { 5967 trip-point0 { 5968 temperature = <90000>; 5969 hysteresis = <2000>; 5970 type = "hot"; 5971 }; 5972 5973 gpuss7-critical { 5974 temperature = <110000>; 5975 hysteresis = <0>; 5976 type = "critical"; 5977 }; 5978 }; 5979 }; 5980 5981 modem0-thermal { 5982 polling-delay-passive = <0>; 5983 polling-delay = <0>; 5984 thermal-sensors = <&tsens2 9>; 5985 5986 trips { 5987 trip-point0 { 5988 temperature = <90000>; 5989 hysteresis = <2000>; 5990 type = "hot"; 5991 }; 5992 5993 modem0-critical { 5994 temperature = <110000>; 5995 hysteresis = <0>; 5996 type = "critical"; 5997 }; 5998 }; 5999 }; 6000 6001 modem1-thermal { 6002 polling-delay-passive = <0>; 6003 polling-delay = <0>; 6004 thermal-sensors = <&tsens2 10>; 6005 6006 trips { 6007 trip-point0 { 6008 temperature = <90000>; 6009 hysteresis = <2000>; 6010 type = "hot"; 6011 }; 6012 6013 modem1-critical { 6014 temperature = <110000>; 6015 hysteresis = <0>; 6016 type = "critical"; 6017 }; 6018 }; 6019 }; 6020 6021 modem2-thermal { 6022 polling-delay-passive = <0>; 6023 polling-delay = <0>; 6024 thermal-sensors = <&tsens2 11>; 6025 6026 trips { 6027 trip-point0 { 6028 temperature = <90000>; 6029 hysteresis = <2000>; 6030 type = "hot"; 6031 }; 6032 6033 modem2-critical { 6034 temperature = <110000>; 6035 hysteresis = <0>; 6036 type = "critical"; 6037 }; 6038 }; 6039 }; 6040 6041 modem3-thermal { 6042 polling-delay-passive = <0>; 6043 polling-delay = <0>; 6044 thermal-sensors = <&tsens2 12>; 6045 6046 trips { 6047 trip-point0 { 6048 temperature = <90000>; 6049 hysteresis = <2000>; 6050 type = "hot"; 6051 }; 6052 6053 modem3-critical { 6054 temperature = <110000>; 6055 hysteresis = <0>; 6056 type = "critical"; 6057 }; 6058 }; 6059 }; 6060 }; 6061 6062 timer { 6063 compatible = "arm,armv8-timer"; 6064 6065 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6066 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6067 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6068 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6069 }; 6070}; 6071