1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sm8650-camcc.h> 9#include <dt-bindings/clock/qcom,sm8650-dispcc.h> 10#include <dt-bindings/clock/qcom,sm8650-gcc.h> 11#include <dt-bindings/clock/qcom,sm8650-gpucc.h> 12#include <dt-bindings/clock/qcom,sm8650-tcsr.h> 13#include <dt-bindings/clock/qcom,sm8650-videocc.h> 14#include <dt-bindings/dma/qcom-gpi.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,icc.h> 18#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> 19#include <dt-bindings/interconnect/qcom,osm-l3.h> 20#include <dt-bindings/interrupt-controller/arm-gic.h> 21#include <dt-bindings/mailbox/qcom-ipcc.h> 22#include <dt-bindings/phy/phy-qcom-qmp.h> 23#include <dt-bindings/power/qcom,rpmhpd.h> 24#include <dt-bindings/power/qcom-rpmpd.h> 25#include <dt-bindings/reset/qcom,sm8650-gpucc.h> 26#include <dt-bindings/soc/qcom,gpr.h> 27#include <dt-bindings/soc/qcom,rpmh-rsc.h> 28#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 29#include <dt-bindings/thermal/thermal.h> 30 31/ { 32 interrupt-parent = <&intc>; 33 34 #address-cells = <2>; 35 #size-cells = <2>; 36 37 chosen { }; 38 39 clocks { 40 xo_board: xo-board { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 }; 44 45 sleep_clk: sleep-clk { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 }; 49 50 bi_tcxo_div2: bi-tcxo-div2-clk { 51 compatible = "fixed-factor-clock"; 52 #clock-cells = <0>; 53 54 clocks = <&rpmhcc RPMH_CXO_CLK>; 55 clock-mult = <1>; 56 clock-div = <2>; 57 }; 58 59 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 60 compatible = "fixed-factor-clock"; 61 #clock-cells = <0>; 62 63 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 64 clock-mult = <1>; 65 clock-div = <2>; 66 }; 67 }; 68 69 cpus { 70 #address-cells = <2>; 71 #size-cells = <0>; 72 73 cpu0: cpu@0 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a520"; 76 reg = <0 0>; 77 78 clocks = <&cpufreq_hw 0>; 79 80 power-domains = <&cpu_pd0>; 81 power-domain-names = "psci"; 82 83 enable-method = "psci"; 84 next-level-cache = <&l2_0>; 85 capacity-dmips-mhz = <1024>; 86 dynamic-power-coefficient = <100>; 87 88 qcom,freq-domain = <&cpufreq_hw 0>; 89 90 operating-points-v2 = <&cpu0_opp_table>; 91 92 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 93 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 94 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 95 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 96 <&epss_l3 MASTER_EPSS_L3_APPS 97 &epss_l3 SLAVE_EPSS_L3_SHARED>; 98 99 #cooling-cells = <2>; 100 101 l2_0: l2-cache { 102 compatible = "cache"; 103 cache-level = <2>; 104 cache-unified; 105 next-level-cache = <&l3_0>; 106 107 l3_0: l3-cache { 108 compatible = "cache"; 109 cache-level = <3>; 110 cache-unified; 111 }; 112 }; 113 }; 114 115 cpu1: cpu@100 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a520"; 118 reg = <0 0x100>; 119 120 clocks = <&cpufreq_hw 0>; 121 122 power-domains = <&cpu_pd1>; 123 power-domain-names = "psci"; 124 125 enable-method = "psci"; 126 next-level-cache = <&l2_0>; 127 capacity-dmips-mhz = <1024>; 128 dynamic-power-coefficient = <100>; 129 130 qcom,freq-domain = <&cpufreq_hw 0>; 131 132 operating-points-v2 = <&cpu0_opp_table>; 133 134 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 135 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 136 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 137 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 138 <&epss_l3 MASTER_EPSS_L3_APPS 139 &epss_l3 SLAVE_EPSS_L3_SHARED>; 140 141 #cooling-cells = <2>; 142 }; 143 144 cpu2: cpu@200 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-a720"; 147 reg = <0 0x200>; 148 149 clocks = <&cpufreq_hw 3>; 150 151 power-domains = <&cpu_pd2>; 152 power-domain-names = "psci"; 153 154 enable-method = "psci"; 155 next-level-cache = <&l2_200>; 156 capacity-dmips-mhz = <1792>; 157 dynamic-power-coefficient = <238>; 158 159 qcom,freq-domain = <&cpufreq_hw 3>; 160 161 operating-points-v2 = <&cpu2_opp_table>; 162 163 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 164 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 165 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 166 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 167 <&epss_l3 MASTER_EPSS_L3_APPS 168 &epss_l3 SLAVE_EPSS_L3_SHARED>; 169 170 #cooling-cells = <2>; 171 172 l2_200: l2-cache { 173 compatible = "cache"; 174 cache-level = <2>; 175 cache-unified; 176 next-level-cache = <&l3_0>; 177 }; 178 }; 179 180 cpu3: cpu@300 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a720"; 183 reg = <0 0x300>; 184 185 clocks = <&cpufreq_hw 3>; 186 187 power-domains = <&cpu_pd3>; 188 power-domain-names = "psci"; 189 190 enable-method = "psci"; 191 next-level-cache = <&l2_300>; 192 capacity-dmips-mhz = <1792>; 193 dynamic-power-coefficient = <238>; 194 195 qcom,freq-domain = <&cpufreq_hw 3>; 196 197 operating-points-v2 = <&cpu2_opp_table>; 198 199 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 200 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 201 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 203 <&epss_l3 MASTER_EPSS_L3_APPS 204 &epss_l3 SLAVE_EPSS_L3_SHARED>; 205 206 #cooling-cells = <2>; 207 208 l2_300: l2-cache { 209 compatible = "cache"; 210 cache-level = <2>; 211 cache-unified; 212 next-level-cache = <&l3_0>; 213 }; 214 }; 215 216 cpu4: cpu@400 { 217 device_type = "cpu"; 218 compatible = "arm,cortex-a720"; 219 reg = <0 0x400>; 220 221 clocks = <&cpufreq_hw 3>; 222 223 power-domains = <&cpu_pd4>; 224 power-domain-names = "psci"; 225 226 enable-method = "psci"; 227 next-level-cache = <&l2_400>; 228 capacity-dmips-mhz = <1792>; 229 dynamic-power-coefficient = <238>; 230 231 qcom,freq-domain = <&cpufreq_hw 3>; 232 233 operating-points-v2 = <&cpu2_opp_table>; 234 235 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 236 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 237 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 238 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 239 <&epss_l3 MASTER_EPSS_L3_APPS 240 &epss_l3 SLAVE_EPSS_L3_SHARED>; 241 242 #cooling-cells = <2>; 243 244 l2_400: l2-cache { 245 compatible = "cache"; 246 cache-level = <2>; 247 cache-unified; 248 next-level-cache = <&l3_0>; 249 }; 250 }; 251 252 cpu5: cpu@500 { 253 device_type = "cpu"; 254 compatible = "arm,cortex-a720"; 255 reg = <0 0x500>; 256 257 clocks = <&cpufreq_hw 1>; 258 259 power-domains = <&cpu_pd5>; 260 power-domain-names = "psci"; 261 262 enable-method = "psci"; 263 next-level-cache = <&l2_500>; 264 capacity-dmips-mhz = <1792>; 265 dynamic-power-coefficient = <238>; 266 267 qcom,freq-domain = <&cpufreq_hw 1>; 268 269 operating-points-v2 = <&cpu5_opp_table>; 270 271 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 272 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 273 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 274 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 275 <&epss_l3 MASTER_EPSS_L3_APPS 276 &epss_l3 SLAVE_EPSS_L3_SHARED>; 277 278 #cooling-cells = <2>; 279 280 l2_500: l2-cache { 281 compatible = "cache"; 282 cache-level = <2>; 283 cache-unified; 284 next-level-cache = <&l3_0>; 285 }; 286 }; 287 288 cpu6: cpu@600 { 289 device_type = "cpu"; 290 compatible = "arm,cortex-a720"; 291 reg = <0 0x600>; 292 293 clocks = <&cpufreq_hw 1>; 294 295 power-domains = <&cpu_pd6>; 296 power-domain-names = "psci"; 297 298 enable-method = "psci"; 299 next-level-cache = <&l2_600>; 300 capacity-dmips-mhz = <1792>; 301 dynamic-power-coefficient = <238>; 302 303 qcom,freq-domain = <&cpufreq_hw 1>; 304 305 operating-points-v2 = <&cpu5_opp_table>; 306 307 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 308 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 309 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 310 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 311 <&epss_l3 MASTER_EPSS_L3_APPS 312 &epss_l3 SLAVE_EPSS_L3_SHARED>; 313 314 #cooling-cells = <2>; 315 316 l2_600: l2-cache { 317 compatible = "cache"; 318 cache-level = <2>; 319 cache-unified; 320 next-level-cache = <&l3_0>; 321 }; 322 }; 323 324 cpu7: cpu@700 { 325 device_type = "cpu"; 326 compatible = "arm,cortex-x4"; 327 reg = <0 0x700>; 328 329 clocks = <&cpufreq_hw 2>; 330 331 power-domains = <&cpu_pd7>; 332 power-domain-names = "psci"; 333 334 enable-method = "psci"; 335 next-level-cache = <&l2_700>; 336 capacity-dmips-mhz = <1894>; 337 dynamic-power-coefficient = <588>; 338 339 qcom,freq-domain = <&cpufreq_hw 2>; 340 341 operating-points-v2 = <&cpu7_opp_table>; 342 343 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 344 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>, 345 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 346 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 347 <&epss_l3 MASTER_EPSS_L3_APPS 348 &epss_l3 SLAVE_EPSS_L3_SHARED>; 349 350 #cooling-cells = <2>; 351 352 l2_700: l2-cache { 353 compatible = "cache"; 354 cache-level = <2>; 355 cache-unified; 356 next-level-cache = <&l3_0>; 357 }; 358 }; 359 360 cpu-map { 361 cluster0 { 362 core0 { 363 cpu = <&cpu0>; 364 }; 365 366 core1 { 367 cpu = <&cpu1>; 368 }; 369 370 core2 { 371 cpu = <&cpu2>; 372 }; 373 374 core3 { 375 cpu = <&cpu3>; 376 }; 377 378 core4 { 379 cpu = <&cpu4>; 380 }; 381 382 core5 { 383 cpu = <&cpu5>; 384 }; 385 386 core6 { 387 cpu = <&cpu6>; 388 }; 389 390 core7 { 391 cpu = <&cpu7>; 392 }; 393 }; 394 }; 395 396 idle-states { 397 entry-method = "psci"; 398 399 silver_cpu_sleep_0: cpu-sleep-0-0 { 400 compatible = "arm,idle-state"; 401 idle-state-name = "silver-rail-power-collapse"; 402 arm,psci-suspend-param = <0x40000004>; 403 entry-latency-us = <550>; 404 exit-latency-us = <750>; 405 min-residency-us = <6700>; 406 local-timer-stop; 407 }; 408 409 gold_cpu_sleep_0: cpu-sleep-1-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "gold-rail-power-collapse"; 412 arm,psci-suspend-param = <0x40000004>; 413 entry-latency-us = <600>; 414 exit-latency-us = <1300>; 415 min-residency-us = <8136>; 416 local-timer-stop; 417 }; 418 419 gold_plus_cpu_sleep_0: cpu-sleep-2-0 { 420 compatible = "arm,idle-state"; 421 idle-state-name = "gold-plus-rail-power-collapse"; 422 arm,psci-suspend-param = <0x40000004>; 423 entry-latency-us = <500>; 424 exit-latency-us = <1350>; 425 min-residency-us = <7480>; 426 local-timer-stop; 427 }; 428 }; 429 430 domain-idle-states { 431 cluster_sleep_0: cluster-sleep-0 { 432 compatible = "domain-idle-state"; 433 arm,psci-suspend-param = <0x41000044>; 434 entry-latency-us = <750>; 435 exit-latency-us = <2350>; 436 min-residency-us = <9144>; 437 }; 438 439 cluster_sleep_1: cluster-sleep-1 { 440 compatible = "domain-idle-state"; 441 arm,psci-suspend-param = <0x4100c344>; 442 entry-latency-us = <2800>; 443 exit-latency-us = <4400>; 444 min-residency-us = <10150>; 445 }; 446 }; 447 }; 448 449 ete-0 { 450 compatible = "arm,embedded-trace-extension"; 451 452 cpu = <&cpu0>; 453 454 out-ports { 455 port { 456 ete0_out_funnel_ete: endpoint { 457 remote-endpoint = <&funnel_ete_in_ete0>; 458 }; 459 }; 460 }; 461 }; 462 463 ete-1 { 464 compatible = "arm,embedded-trace-extension"; 465 466 cpu = <&cpu1>; 467 468 out-ports { 469 port { 470 ete1_out_funnel_ete: endpoint { 471 remote-endpoint = <&funnel_ete_in_ete1>; 472 }; 473 }; 474 }; 475 }; 476 477 ete-2 { 478 compatible = "arm,embedded-trace-extension"; 479 480 cpu = <&cpu2>; 481 482 out-ports { 483 port { 484 ete2_out_funnel_ete: endpoint { 485 remote-endpoint = <&funnel_ete_in_ete2>; 486 }; 487 }; 488 }; 489 }; 490 491 ete-3 { 492 compatible = "arm,embedded-trace-extension"; 493 494 cpu = <&cpu3>; 495 496 out-ports { 497 port { 498 ete3_out_funnel_ete: endpoint { 499 remote-endpoint = <&funnel_ete_in_ete3>; 500 }; 501 }; 502 }; 503 }; 504 505 ete-4 { 506 compatible = "arm,embedded-trace-extension"; 507 508 cpu = <&cpu4>; 509 510 out-ports { 511 port { 512 ete4_out_funnel_ete: endpoint { 513 remote-endpoint = <&funnel_ete_in_ete4>; 514 }; 515 }; 516 }; 517 }; 518 519 ete-5 { 520 compatible = "arm,embedded-trace-extension"; 521 522 cpu = <&cpu5>; 523 524 out-ports { 525 port { 526 ete5_out_funnel_ete: endpoint { 527 remote-endpoint = <&funnel_ete_in_ete5>; 528 }; 529 }; 530 }; 531 }; 532 533 ete-6 { 534 compatible = "arm,embedded-trace-extension"; 535 536 cpu = <&cpu6>; 537 538 out-ports { 539 port { 540 ete6_out_funnel_ete: endpoint { 541 remote-endpoint = <&funnel_ete_in_ete6>; 542 }; 543 }; 544 }; 545 }; 546 547 ete-7 { 548 compatible = "arm,embedded-trace-extension"; 549 550 cpu = <&cpu7>; 551 552 out-ports { 553 port { 554 ete7_out_funnel_ete: endpoint { 555 remote-endpoint = <&funnel_ete_in_ete7>; 556 }; 557 }; 558 }; 559 }; 560 561 funnel-ete { 562 compatible = "arm,coresight-static-funnel"; 563 564 in-ports { 565 #address-cells = <1>; 566 #size-cells = <0>; 567 568 port@0 { 569 reg = <0>; 570 571 funnel_ete_in_ete0: endpoint { 572 remote-endpoint = <&ete0_out_funnel_ete>; 573 }; 574 }; 575 576 port@1 { 577 reg = <1>; 578 579 funnel_ete_in_ete1: endpoint { 580 remote-endpoint = <&ete1_out_funnel_ete>; 581 }; 582 }; 583 584 port@2 { 585 reg = <2>; 586 587 funnel_ete_in_ete2: endpoint { 588 remote-endpoint = <&ete2_out_funnel_ete>; 589 }; 590 }; 591 592 port@3 { 593 reg = <3>; 594 595 funnel_ete_in_ete3: endpoint { 596 remote-endpoint = <&ete3_out_funnel_ete>; 597 }; 598 }; 599 600 port@4 { 601 reg = <4>; 602 603 funnel_ete_in_ete4: endpoint { 604 remote-endpoint = <&ete4_out_funnel_ete>; 605 }; 606 }; 607 608 port@5 { 609 reg = <5>; 610 611 funnel_ete_in_ete5: endpoint { 612 remote-endpoint = <&ete5_out_funnel_ete>; 613 }; 614 }; 615 616 port@6 { 617 reg = <6>; 618 619 funnel_ete_in_ete6: endpoint { 620 remote-endpoint = <&ete6_out_funnel_ete>; 621 }; 622 }; 623 624 port@7 { 625 reg = <7>; 626 627 funnel_ete_in_ete7: endpoint { 628 remote-endpoint = <&ete7_out_funnel_ete>; 629 }; 630 }; 631 }; 632 633 out-ports { 634 port { 635 funnel_ete_out_funnel_apss: endpoint { 636 remote-endpoint = <&funnel_apss_in_funnel_ete>; 637 }; 638 }; 639 }; 640 }; 641 642 firmware { 643 scm: scm { 644 compatible = "qcom,scm-sm8650", "qcom,scm"; 645 qcom,dload-mode = <&tcsr 0x19000>; 646 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 647 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 648 }; 649 }; 650 651 clk_virt: interconnect-0 { 652 compatible = "qcom,sm8650-clk-virt"; 653 #interconnect-cells = <2>; 654 qcom,bcm-voters = <&apps_bcm_voter>; 655 }; 656 657 mc_virt: interconnect-1 { 658 compatible = "qcom,sm8650-mc-virt"; 659 #interconnect-cells = <2>; 660 qcom,bcm-voters = <&apps_bcm_voter>; 661 }; 662 663 qup_opp_table_100mhz: opp-table-qup100mhz { 664 compatible = "operating-points-v2"; 665 666 opp-75000000 { 667 opp-hz = /bits/ 64 <75000000>; 668 required-opps = <&rpmhpd_opp_low_svs>; 669 }; 670 671 opp-100000000 { 672 opp-hz = /bits/ 64 <100000000>; 673 required-opps = <&rpmhpd_opp_svs>; 674 }; 675 }; 676 677 qup_opp_table_120mhz: opp-table-qup120mhz { 678 compatible = "operating-points-v2"; 679 680 opp-75000000 { 681 opp-hz = /bits/ 64 <75000000>; 682 required-opps = <&rpmhpd_opp_low_svs>; 683 }; 684 685 opp-120000000 { 686 opp-hz = /bits/ 64 <120000000>; 687 required-opps = <&rpmhpd_opp_svs>; 688 }; 689 }; 690 691 qup_opp_table_128mhz: opp-table-qup128mhz { 692 compatible = "operating-points-v2"; 693 694 opp-75000000 { 695 opp-hz = /bits/ 64 <75000000>; 696 required-opps = <&rpmhpd_opp_low_svs>; 697 }; 698 699 opp-128000000 { 700 opp-hz = /bits/ 64 <128000000>; 701 required-opps = <&rpmhpd_opp_svs>; 702 }; 703 }; 704 705 qup_opp_table_240mhz: opp-table-qup240mhz { 706 compatible = "operating-points-v2"; 707 708 opp-150000000 { 709 opp-hz = /bits/ 64 <150000000>; 710 required-opps = <&rpmhpd_opp_low_svs>; 711 }; 712 713 opp-240000000 { 714 opp-hz = /bits/ 64 <240000000>; 715 required-opps = <&rpmhpd_opp_svs>; 716 }; 717 }; 718 719 memory@a0000000 { 720 device_type = "memory"; 721 /* We expect the bootloader to fill in the size */ 722 reg = <0 0xa0000000 0 0>; 723 }; 724 725 cpu0_opp_table: opp-table-cpu0 { 726 compatible = "operating-points-v2"; 727 opp-shared; 728 729 opp-307200000 { 730 opp-hz = /bits/ 64 <307200000>; 731 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 732 }; 733 734 opp-364800000 { 735 opp-hz = /bits/ 64 <364800000>; 736 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 737 }; 738 739 opp-460800000 { 740 opp-hz = /bits/ 64 <460800000>; 741 opp-peak-kBps = <(300000 * 16) (547000 * 4) (384000 * 32)>; 742 }; 743 744 opp-556800000 { 745 opp-hz = /bits/ 64 <556800000>; 746 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 747 }; 748 749 opp-672000000 { 750 opp-hz = /bits/ 64 <672000000>; 751 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 752 }; 753 754 opp-787200000 { 755 opp-hz = /bits/ 64 <787200000>; 756 opp-peak-kBps = <(300000 * 16) (547000 * 4) (729600 * 32)>; 757 }; 758 759 opp-902400000 { 760 opp-hz = /bits/ 64 <902400000>; 761 opp-peak-kBps = <(300000 * 16) (547000 * 4) (844800 * 32)>; 762 }; 763 764 opp-1017600000 { 765 opp-hz = /bits/ 64 <1017600000>; 766 opp-peak-kBps = <(466000 * 16) (547000 * 4) (940800 * 32)>; 767 }; 768 769 opp-1132800000 { 770 opp-hz = /bits/ 64 <1132800000>; 771 opp-peak-kBps = <(466000 * 16) (547000 * 4) (1036800 * 32)>; 772 }; 773 774 opp-1248000000 { 775 opp-hz = /bits/ 64 <1248000000>; 776 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1132800 * 32)>; 777 }; 778 779 opp-1344000000 { 780 opp-hz = /bits/ 64 <1344000000>; 781 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; 782 }; 783 784 opp-1440000000 { 785 opp-hz = /bits/ 64 <1440000000>; 786 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; 787 }; 788 789 opp-1459200000 { 790 opp-hz = /bits/ 64 <1459200000>; 791 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>; 792 }; 793 794 opp-1536000000 { 795 opp-hz = /bits/ 64 <1536000000>; 796 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>; 797 }; 798 799 opp-1574400000 { 800 opp-hz = /bits/ 64 <1574400000>; 801 opp-peak-kBps = <(466000 * 16) (768000 * 4) (1440000 * 32)>; 802 }; 803 804 opp-1651200000 { 805 opp-hz = /bits/ 64 <1651200000>; 806 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; 807 }; 808 809 opp-1689600000 { 810 opp-hz = /bits/ 64 <1689600000>; 811 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; 812 }; 813 814 opp-1747200000 { 815 opp-hz = /bits/ 64 <1747200000>; 816 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1440000 * 32)>; 817 }; 818 819 opp-1804800000 { 820 opp-hz = /bits/ 64 <1804800000>; 821 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>; 822 }; 823 824 opp-1843200000 { 825 opp-hz = /bits/ 64 <1843200000>; 826 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1555200 * 32)>; 827 }; 828 829 opp-1920000000 { 830 opp-hz = /bits/ 64 <1920000000>; 831 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>; 832 }; 833 834 opp-1939200000 { 835 opp-hz = /bits/ 64 <1939200000>; 836 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1651200 * 32)>; 837 }; 838 839 opp-2035200000 { 840 opp-hz = /bits/ 64 <2035200000>; 841 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>; 842 }; 843 844 opp-2150400000 { 845 opp-hz = /bits/ 64 <2150400000>; 846 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1843200 * 32)>; 847 }; 848 849 opp-2265600000 { 850 opp-hz = /bits/ 64 <2265600000>; 851 opp-peak-kBps = <(600000 * 16) (1555000 * 4) (2035200 * 32)>; 852 }; 853 }; 854 855 cpu2_opp_table: opp-table-cpu2 { 856 compatible = "operating-points-v2"; 857 opp-shared; 858 859 opp-460800000 { 860 opp-hz = /bits/ 64 <460800000>; 861 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 862 }; 863 864 opp-499200000 { 865 opp-hz = /bits/ 64 <499200000>; 866 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 867 }; 868 869 opp-576000000 { 870 opp-hz = /bits/ 64 <576000000>; 871 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 872 }; 873 874 opp-614400000 { 875 opp-hz = /bits/ 64 <614400000>; 876 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 877 }; 878 879 opp-691200000 { 880 opp-hz = /bits/ 64 <691200000>; 881 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 882 }; 883 884 opp-729600000 { 885 opp-hz = /bits/ 64 <729600000>; 886 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 887 }; 888 889 opp-806400000 { 890 opp-hz = /bits/ 64 <806400000>; 891 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 892 }; 893 894 opp-844800000 { 895 opp-hz = /bits/ 64 <844800000>; 896 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 897 }; 898 899 opp-902400000 { 900 opp-hz = /bits/ 64 <902400000>; 901 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 902 }; 903 904 opp-960000000 { 905 opp-hz = /bits/ 64 <960000000>; 906 opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>; 907 }; 908 909 opp-1036800000 { 910 opp-hz = /bits/ 64 <1036800000>; 911 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 912 }; 913 914 opp-1075200000 { 915 opp-hz = /bits/ 64 <1075200000>; 916 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 917 }; 918 919 opp-1152000000 { 920 opp-hz = /bits/ 64 <1152000000>; 921 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 922 }; 923 924 opp-1190400000 { 925 opp-hz = /bits/ 64 <1190400000>; 926 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; 927 }; 928 929 opp-1267200000 { 930 opp-hz = /bits/ 64 <1267200000>; 931 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 932 }; 933 934 opp-1286400000 { 935 opp-hz = /bits/ 64 <1286400000>; 936 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 937 }; 938 939 opp-1382400000 { 940 opp-hz = /bits/ 64 <1382400000>; 941 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 942 }; 943 944 opp-1401600000 { 945 opp-hz = /bits/ 64 <1401600000>; 946 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; 947 }; 948 949 opp-1497600000 { 950 opp-hz = /bits/ 64 <1497600000>; 951 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 952 }; 953 954 opp-1612800000 { 955 opp-hz = /bits/ 64 <1612800000>; 956 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 957 }; 958 959 opp-1708800000 { 960 opp-hz = /bits/ 64 <1708800000>; 961 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 962 }; 963 964 opp-1728000000 { 965 opp-hz = /bits/ 64 <1728000000>; 966 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 967 }; 968 969 opp-1824000000 { 970 opp-hz = /bits/ 64 <1824000000>; 971 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 972 }; 973 974 opp-1843200000 { 975 opp-hz = /bits/ 64 <1843200000>; 976 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 977 }; 978 979 opp-1920000000 { 980 opp-hz = /bits/ 64 <1920000000>; 981 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>; 982 }; 983 984 opp-1958400000 { 985 opp-hz = /bits/ 64 <1958400000>; 986 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 987 }; 988 989 opp-2035200000 { 990 opp-hz = /bits/ 64 <2035200000>; 991 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 992 }; 993 994 opp-2073600000 { 995 opp-hz = /bits/ 64 <2073600000>; 996 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 997 }; 998 999 opp-2131200000 { 1000 opp-hz = /bits/ 64 <2131200000>; 1001 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1002 }; 1003 1004 opp-2188800000 { 1005 opp-hz = /bits/ 64 <2188800000>; 1006 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1007 }; 1008 1009 opp-2246400000 { 1010 opp-hz = /bits/ 64 <2246400000>; 1011 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1012 }; 1013 1014 opp-2304000000 { 1015 opp-hz = /bits/ 64 <2304000000>; 1016 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1017 }; 1018 1019 opp-2323200000 { 1020 opp-hz = /bits/ 64 <2323200000>; 1021 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1022 }; 1023 1024 opp-2380800000 { 1025 opp-hz = /bits/ 64 <2380800000>; 1026 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1027 }; 1028 1029 opp-2400000000 { 1030 opp-hz = /bits/ 64 <2400000000>; 1031 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1032 }; 1033 1034 opp-2438400000 { 1035 opp-hz = /bits/ 64 <2438400000>; 1036 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1037 }; 1038 1039 opp-2515200000 { 1040 opp-hz = /bits/ 64 <2515200000>; 1041 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1042 }; 1043 1044 opp-2572800000 { 1045 opp-hz = /bits/ 64 <2572800000>; 1046 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1047 }; 1048 1049 opp-2630400000 { 1050 opp-hz = /bits/ 64 <2630400000>; 1051 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1052 }; 1053 1054 opp-2707200000 { 1055 opp-hz = /bits/ 64 <2707200000>; 1056 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1057 }; 1058 1059 opp-2764800000 { 1060 opp-hz = /bits/ 64 <2764800000>; 1061 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; 1062 }; 1063 1064 opp-2841600000 { 1065 opp-hz = /bits/ 64 <2841600000>; 1066 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1067 }; 1068 1069 opp-2899200000 { 1070 opp-hz = /bits/ 64 <2899200000>; 1071 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1072 }; 1073 1074 opp-2956800000 { 1075 opp-hz = /bits/ 64 <2956800000>; 1076 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1077 }; 1078 1079 opp-3014400000 { 1080 opp-hz = /bits/ 64 <3014400000>; 1081 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1082 }; 1083 1084 opp-3072000000 { 1085 opp-hz = /bits/ 64 <3072000000>; 1086 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1087 }; 1088 1089 opp-3148800000 { 1090 opp-hz = /bits/ 64 <3148800000>; 1091 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1092 }; 1093 }; 1094 1095 cpu5_opp_table: opp-table-cpu5 { 1096 compatible = "operating-points-v2"; 1097 opp-shared; 1098 1099 opp-460800000 { 1100 opp-hz = /bits/ 64 <460800000>; 1101 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1102 }; 1103 1104 opp-499200000 { 1105 opp-hz = /bits/ 64 <499200000>; 1106 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1107 }; 1108 1109 opp-576000000 { 1110 opp-hz = /bits/ 64 <576000000>; 1111 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1112 }; 1113 1114 opp-614400000 { 1115 opp-hz = /bits/ 64 <614400000>; 1116 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 1117 }; 1118 1119 opp-691200000 { 1120 opp-hz = /bits/ 64 <691200000>; 1121 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1122 }; 1123 1124 opp-729600000 { 1125 opp-hz = /bits/ 64 <729600000>; 1126 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1127 }; 1128 1129 opp-806400000 { 1130 opp-hz = /bits/ 64 <806400000>; 1131 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1132 }; 1133 1134 opp-844800000 { 1135 opp-hz = /bits/ 64 <844800000>; 1136 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1137 }; 1138 1139 opp-902400000 { 1140 opp-hz = /bits/ 64 <902400000>; 1141 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1142 }; 1143 1144 opp-960000000 { 1145 opp-hz = /bits/ 64 <960000000>; 1146 opp-peak-kBps = <(466000 * 16) (768000 * 4) (844800 * 32)>; 1147 }; 1148 1149 opp-1036800000 { 1150 opp-hz = /bits/ 64 <1036800000>; 1151 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1152 }; 1153 1154 opp-1075200000 { 1155 opp-hz = /bits/ 64 <1075200000>; 1156 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1157 }; 1158 1159 opp-1152000000 { 1160 opp-hz = /bits/ 64 <1152000000>; 1161 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1162 }; 1163 1164 opp-1190400000 { 1165 opp-hz = /bits/ 64 <1190400000>; 1166 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; 1167 }; 1168 1169 opp-1267200000 { 1170 opp-hz = /bits/ 64 <1267200000>; 1171 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1172 }; 1173 1174 opp-1286400000 { 1175 opp-hz = /bits/ 64 <1286400000>; 1176 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1177 }; 1178 1179 opp-1382400000 { 1180 opp-hz = /bits/ 64 <1382400000>; 1181 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1182 }; 1183 1184 opp-1401600000 { 1185 opp-hz = /bits/ 64 <1401600000>; 1186 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; 1187 }; 1188 1189 opp-1497600000 { 1190 opp-hz = /bits/ 64 <1497600000>; 1191 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1192 }; 1193 1194 opp-1612800000 { 1195 opp-hz = /bits/ 64 <1612800000>; 1196 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1197 }; 1198 1199 opp-1708800000 { 1200 opp-hz = /bits/ 64 <1708800000>; 1201 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1202 }; 1203 1204 opp-1728000000 { 1205 opp-hz = /bits/ 64 <1728000000>; 1206 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1207 }; 1208 1209 opp-1824000000 { 1210 opp-hz = /bits/ 64 <1824000000>; 1211 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1212 }; 1213 1214 opp-1843200000 { 1215 opp-hz = /bits/ 64 <1843200000>; 1216 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1217 }; 1218 1219 opp-1920000000 { 1220 opp-hz = /bits/ 64 <1920000000>; 1221 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1440000 * 32)>; 1222 }; 1223 1224 opp-1958400000 { 1225 opp-hz = /bits/ 64 <1958400000>; 1226 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1227 }; 1228 1229 opp-2035200000 { 1230 opp-hz = /bits/ 64 <2035200000>; 1231 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1232 }; 1233 1234 opp-2073600000 { 1235 opp-hz = /bits/ 64 <2073600000>; 1236 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1237 }; 1238 1239 opp-2131200000 { 1240 opp-hz = /bits/ 64 <2131200000>; 1241 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1242 }; 1243 1244 opp-2188800000 { 1245 opp-hz = /bits/ 64 <2188800000>; 1246 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1247 }; 1248 1249 opp-2246400000 { 1250 opp-hz = /bits/ 64 <2246400000>; 1251 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1252 }; 1253 1254 opp-2304000000 { 1255 opp-hz = /bits/ 64 <2304000000>; 1256 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1257 }; 1258 1259 opp-2323200000 { 1260 opp-hz = /bits/ 64 <2323200000>; 1261 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1262 }; 1263 1264 opp-2380800000 { 1265 opp-hz = /bits/ 64 <2380800000>; 1266 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1267 }; 1268 1269 opp-2400000000 { 1270 opp-hz = /bits/ 64 <2400000000>; 1271 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1272 }; 1273 1274 opp-2438400000 { 1275 opp-hz = /bits/ 64 <2438400000>; 1276 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1277 }; 1278 1279 opp-2515200000 { 1280 opp-hz = /bits/ 64 <2515200000>; 1281 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1282 }; 1283 1284 opp-2572800000 { 1285 opp-hz = /bits/ 64 <2572800000>; 1286 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1287 }; 1288 1289 opp-2630400000 { 1290 opp-hz = /bits/ 64 <2630400000>; 1291 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1292 }; 1293 1294 opp-2707200000 { 1295 opp-hz = /bits/ 64 <2707200000>; 1296 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1297 }; 1298 1299 opp-2764800000 { 1300 opp-hz = /bits/ 64 <2764800000>; 1301 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; 1302 }; 1303 1304 opp-2841600000 { 1305 opp-hz = /bits/ 64 <2841600000>; 1306 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1307 }; 1308 1309 opp-2899200000 { 1310 opp-hz = /bits/ 64 <2899200000>; 1311 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1312 }; 1313 1314 opp-2956800000 { 1315 opp-hz = /bits/ 64 <2956800000>; 1316 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1317 }; 1318 1319 opp-3014400000 { 1320 opp-hz = /bits/ 64 <3014400000>; 1321 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1322 }; 1323 1324 opp-3072000000 { 1325 opp-hz = /bits/ 64 <3072000000>; 1326 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1327 }; 1328 1329 opp-3148800000 { 1330 opp-hz = /bits/ 64 <3148800000>; 1331 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1332 }; 1333 }; 1334 1335 cpu7_opp_table: opp-table-cpu7 { 1336 compatible = "operating-points-v2"; 1337 opp-shared; 1338 1339 opp-480000000 { 1340 opp-hz = /bits/ 64 <480000000>; 1341 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1342 }; 1343 1344 opp-499200000 { 1345 opp-hz = /bits/ 64 <499200000>; 1346 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1347 }; 1348 1349 opp-576000000 { 1350 opp-hz = /bits/ 64 <576000000>; 1351 opp-peak-kBps = <(300000 * 16) (547000 * 4) (307200 * 32)>; 1352 }; 1353 1354 opp-614400000 { 1355 opp-hz = /bits/ 64 <614400000>; 1356 opp-peak-kBps = <(300000 * 16) (547000 * 4) (499200 * 32)>; 1357 }; 1358 1359 opp-672000000 { 1360 opp-hz = /bits/ 64 <672000000>; 1361 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1362 }; 1363 1364 opp-729600000 { 1365 opp-hz = /bits/ 64 <729600000>; 1366 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1367 }; 1368 1369 opp-787200000 { 1370 opp-hz = /bits/ 64 <787200000>; 1371 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1372 }; 1373 1374 opp-844800000 { 1375 opp-hz = /bits/ 64 <844800000>; 1376 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1377 }; 1378 1379 opp-902400000 { 1380 opp-hz = /bits/ 64 <902400000>; 1381 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1382 }; 1383 1384 opp-940800000 { 1385 opp-hz = /bits/ 64 <940800000>; 1386 opp-peak-kBps = <(466000 * 16) (768000 * 4) (499200 * 32)>; 1387 }; 1388 1389 opp-1017600000 { 1390 opp-hz = /bits/ 64 <1017600000>; 1391 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1392 }; 1393 1394 opp-1075200000 { 1395 opp-hz = /bits/ 64 <1075200000>; 1396 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1397 }; 1398 1399 opp-1132800000 { 1400 opp-hz = /bits/ 64 <1132800000>; 1401 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (844800 * 32)>; 1402 }; 1403 1404 opp-1190400000 { 1405 opp-hz = /bits/ 64 <1190400000>; 1406 opp-peak-kBps = <(466000 * 16) (1555000 * 4) (1036800 * 32)>; 1407 }; 1408 1409 opp-1248000000 { 1410 opp-hz = /bits/ 64 <1248000000>; 1411 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1412 }; 1413 1414 opp-1305600000 { 1415 opp-hz = /bits/ 64 <1305600000>; 1416 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1417 }; 1418 1419 opp-1363200000 { 1420 opp-hz = /bits/ 64 <1363200000>; 1421 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1036800 * 32)>; 1422 }; 1423 1424 opp-1420800000 { 1425 opp-hz = /bits/ 64 <1420800000>; 1426 opp-peak-kBps = <(600000 * 16) (2092000 * 4) (1248000 * 32)>; 1427 }; 1428 1429 opp-1478400000 { 1430 opp-hz = /bits/ 64 <1478400000>; 1431 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1432 }; 1433 1434 opp-1555200000 { 1435 opp-hz = /bits/ 64 <1555200000>; 1436 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1437 }; 1438 1439 opp-1593600000 { 1440 opp-hz = /bits/ 64 <1593600000>; 1441 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1442 }; 1443 1444 opp-1670400000 { 1445 opp-hz = /bits/ 64 <1670400000>; 1446 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1447 }; 1448 1449 opp-1708800000 { 1450 opp-hz = /bits/ 64 <1708800000>; 1451 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1452 }; 1453 1454 opp-1804800000 { 1455 opp-hz = /bits/ 64 <1804800000>; 1456 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1457 }; 1458 1459 opp-1824000000 { 1460 opp-hz = /bits/ 64 <1824000000>; 1461 opp-peak-kBps = <(806000 * 16) (2736000 * 4) (1248000 * 32)>; 1462 }; 1463 1464 opp-1939200000 { 1465 opp-hz = /bits/ 64 <1939200000>; 1466 opp-peak-kBps = <(806000 * 16) (3686000 * 4) (1440000 * 32)>; 1467 }; 1468 1469 opp-2035200000 { 1470 opp-hz = /bits/ 64 <2035200000>; 1471 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1472 }; 1473 1474 opp-2073600000 { 1475 opp-hz = /bits/ 64 <2073600000>; 1476 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1477 }; 1478 1479 opp-2112000000 { 1480 opp-hz = /bits/ 64 <2112000000>; 1481 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1482 }; 1483 1484 opp-2169600000 { 1485 opp-hz = /bits/ 64 <2169600000>; 1486 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1487 }; 1488 1489 opp-2208000000 { 1490 opp-hz = /bits/ 64 <2208000000>; 1491 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1492 }; 1493 1494 opp-2246400000 { 1495 opp-hz = /bits/ 64 <2246400000>; 1496 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1497 }; 1498 1499 opp-2304000000 { 1500 opp-hz = /bits/ 64 <2304000000>; 1501 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1502 }; 1503 1504 opp-2342400000 { 1505 opp-hz = /bits/ 64 <2342400000>; 1506 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1507 }; 1508 1509 opp-2380800000 { 1510 opp-hz = /bits/ 64 <2380800000>; 1511 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1512 }; 1513 1514 opp-2438400000 { 1515 opp-hz = /bits/ 64 <2438400000>; 1516 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1517 }; 1518 1519 opp-2457600000 { 1520 opp-hz = /bits/ 64 <2457600000>; 1521 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1522 }; 1523 1524 opp-2496000000 { 1525 opp-hz = /bits/ 64 <2496000000>; 1526 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1527 }; 1528 1529 opp-2553600000 { 1530 opp-hz = /bits/ 64 <2553600000>; 1531 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1440000 * 32)>; 1532 }; 1533 1534 opp-2630400000 { 1535 opp-hz = /bits/ 64 <2630400000>; 1536 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1537 }; 1538 1539 opp-2688000000 { 1540 opp-hz = /bits/ 64 <2688000000>; 1541 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1651200 * 32)>; 1542 }; 1543 1544 opp-2745600000 { 1545 opp-hz = /bits/ 64 <2745600000>; 1546 opp-peak-kBps = <(933000 * 16) (3686000 * 4) (1843200 * 32)>; 1547 }; 1548 1549 opp-2803200000 { 1550 opp-hz = /bits/ 64 <2803200000>; 1551 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1552 }; 1553 1554 opp-2880000000 { 1555 opp-hz = /bits/ 64 <2880000000>; 1556 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1557 }; 1558 1559 opp-2937600000 { 1560 opp-hz = /bits/ 64 <2937600000>; 1561 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1562 }; 1563 1564 opp-2995200000 { 1565 opp-hz = /bits/ 64 <2995200000>; 1566 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1567 }; 1568 1569 opp-3052800000 { 1570 opp-hz = /bits/ 64 <3052800000>; 1571 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (1843200 * 32)>; 1572 }; 1573 1574 opp-3187200000 { 1575 opp-hz = /bits/ 64 <3187200000>; 1576 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1577 }; 1578 1579 opp-3302400000 { 1580 opp-hz = /bits/ 64 <3302400000>; 1581 opp-peak-kBps = <(1066000 * 16) (4224000 * 4) (2035200 * 32)>; 1582 }; 1583 }; 1584 1585 pmu-a520 { 1586 compatible = "arm,cortex-a520-pmu"; 1587 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 1588 }; 1589 1590 pmu-a720 { 1591 compatible = "arm,cortex-a720-pmu"; 1592 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 1593 }; 1594 1595 pmu-x4 { 1596 compatible = "arm,cortex-x4-pmu"; 1597 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster2>; 1598 }; 1599 1600 psci { 1601 compatible = "arm,psci-1.0"; 1602 method = "smc"; 1603 1604 cpu_pd0: power-domain-cpu0 { 1605 #power-domain-cells = <0>; 1606 power-domains = <&cluster_pd>; 1607 domain-idle-states = <&silver_cpu_sleep_0>; 1608 }; 1609 1610 cpu_pd1: power-domain-cpu1 { 1611 #power-domain-cells = <0>; 1612 power-domains = <&cluster_pd>; 1613 domain-idle-states = <&silver_cpu_sleep_0>; 1614 }; 1615 1616 cpu_pd2: power-domain-cpu2 { 1617 #power-domain-cells = <0>; 1618 power-domains = <&cluster_pd>; 1619 domain-idle-states = <&gold_cpu_sleep_0>; 1620 }; 1621 1622 cpu_pd3: power-domain-cpu3 { 1623 #power-domain-cells = <0>; 1624 power-domains = <&cluster_pd>; 1625 domain-idle-states = <&gold_cpu_sleep_0>; 1626 }; 1627 1628 cpu_pd4: power-domain-cpu4 { 1629 #power-domain-cells = <0>; 1630 power-domains = <&cluster_pd>; 1631 domain-idle-states = <&gold_cpu_sleep_0>; 1632 }; 1633 1634 cpu_pd5: power-domain-cpu5 { 1635 #power-domain-cells = <0>; 1636 power-domains = <&cluster_pd>; 1637 domain-idle-states = <&gold_cpu_sleep_0>; 1638 }; 1639 1640 cpu_pd6: power-domain-cpu6 { 1641 #power-domain-cells = <0>; 1642 power-domains = <&cluster_pd>; 1643 domain-idle-states = <&gold_cpu_sleep_0>; 1644 }; 1645 1646 cpu_pd7: power-domain-cpu7 { 1647 #power-domain-cells = <0>; 1648 power-domains = <&cluster_pd>; 1649 domain-idle-states = <&gold_plus_cpu_sleep_0>; 1650 }; 1651 1652 cluster_pd: power-domain-cluster { 1653 #power-domain-cells = <0>; 1654 domain-idle-states = <&cluster_sleep_0>, 1655 <&cluster_sleep_1>; 1656 }; 1657 }; 1658 1659 reserved_memory: reserved-memory { 1660 #address-cells = <2>; 1661 #size-cells = <2>; 1662 ranges; 1663 1664 hyp_mem: hyp@80000000 { 1665 reg = <0 0x80000000 0 0xe00000>; 1666 no-map; 1667 }; 1668 1669 cpusys_vm_mem: cpusys-vm@80e00000 { 1670 reg = <0 0x80e00000 0 0x400000>; 1671 no-map; 1672 }; 1673 1674 /* Merged xbl_dtlog, xbl_ramdump and aop_image regions */ 1675 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 { 1676 reg = <0 0x81a00000 0 0x260000>; 1677 no-map; 1678 }; 1679 1680 aop_cmd_db_mem: aop-cmd-db@81c60000 { 1681 compatible = "qcom,cmd-db"; 1682 reg = <0 0x81c60000 0 0x20000>; 1683 no-map; 1684 }; 1685 1686 /* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */ 1687 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 1688 reg = <0 0x81c80000 0 0x75000>; 1689 no-map; 1690 }; 1691 1692 /* Secdata region can be reused by apps */ 1693 1694 smem: smem@81d00000 { 1695 compatible = "qcom,smem"; 1696 reg = <0 0x81d00000 0 0x200000>; 1697 hwlocks = <&tcsr_mutex 3>; 1698 no-map; 1699 }; 1700 1701 adsp_mhi_mem: adsp-mhi@81f00000 { 1702 reg = <0 0x81f00000 0 0x20000>; 1703 no-map; 1704 }; 1705 1706 pvmfw_mem: pvmfw@824a0000 { 1707 reg = <0 0x824a0000 0 0x100000>; 1708 no-map; 1709 }; 1710 1711 global_sync_mem: global-sync@82600000 { 1712 reg = <0 0x82600000 0 0x100000>; 1713 no-map; 1714 }; 1715 1716 tz_stat_mem: tz-stat@82700000 { 1717 reg = <0 0x82700000 0 0x100000>; 1718 no-map; 1719 }; 1720 1721 qdss_mem: qdss@82800000 { 1722 reg = <0 0x82800000 0 0x2000000>; 1723 no-map; 1724 }; 1725 1726 qlink_logging_mem: qlink-logging@84800000 { 1727 reg = <0 0x84800000 0 0x200000>; 1728 no-map; 1729 }; 1730 1731 mpss_dsm_mem: mpss-dsm@86b00000 { 1732 reg = <0 0x86b00000 0 0x4900000>; 1733 no-map; 1734 }; 1735 1736 mpss_dsm_mem_2: mpss-dsm-2@8b400000 { 1737 reg = <0 0x8b400000 0 0x800000>; 1738 no-map; 1739 }; 1740 1741 mpss_mem: mpss@8bc00000 { 1742 reg = <0 0x8bc00000 0 0xf400000>; 1743 no-map; 1744 }; 1745 1746 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { 1747 reg = <0 0x9b000000 0 0x80000>; 1748 no-map; 1749 }; 1750 1751 ipa_fw_mem: ipa-fw@9b080000 { 1752 reg = <0 0x9b080000 0 0x10000>; 1753 no-map; 1754 }; 1755 1756 ipa_gsi_mem: ipa-gsi@9b090000 { 1757 reg = <0 0x9b090000 0 0xa000>; 1758 no-map; 1759 }; 1760 1761 gpu_micro_code_mem: gpu-micro-code@9b09a000 { 1762 reg = <0 0x9b09a000 0 0x2000>; 1763 no-map; 1764 }; 1765 1766 spss_region_mem: spss@9b0a0000 { 1767 reg = <0 0x9b0a0000 0 0x1e0000>; 1768 no-map; 1769 }; 1770 1771 /* First part of the "SPU secure shared memory" region */ 1772 spu_tz_shared_mem: spu-tz-shared@9b280000 { 1773 reg = <0 0x9b280000 0 0x60000>; 1774 no-map; 1775 }; 1776 1777 /* Second part of the "SPU secure shared memory" region */ 1778 spu_modem_shared_mem: spu-modem-shared@9b2e0000 { 1779 reg = <0 0x9b2e0000 0 0x20000>; 1780 no-map; 1781 }; 1782 1783 camera_mem: camera@9b300000 { 1784 reg = <0 0x9b300000 0 0x800000>; 1785 no-map; 1786 }; 1787 1788 video_mem: video@9bb00000 { 1789 reg = <0 0x9bb00000 0 0x800000>; 1790 no-map; 1791 }; 1792 1793 cvp_mem: cvp@9c300000 { 1794 reg = <0 0x9c300000 0 0x700000>; 1795 no-map; 1796 }; 1797 1798 cdsp_mem: cdsp@9ca00000 { 1799 reg = <0 0x9ca00000 0 0x1400000>; 1800 no-map; 1801 }; 1802 1803 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 { 1804 reg = <0 0x9de00000 0 0x80000>; 1805 no-map; 1806 }; 1807 1808 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 { 1809 reg = <0 0x9de80000 0 0x80000>; 1810 no-map; 1811 }; 1812 1813 adspslpi_mem: adspslpi@9df00000 { 1814 reg = <0 0x9df00000 0 0x4080000>; 1815 no-map; 1816 }; 1817 1818 rmtfs_mem: rmtfs@d7c00000 { 1819 compatible = "qcom,rmtfs-mem"; 1820 reg = <0 0xd7c00000 0 0x400000>; 1821 no-map; 1822 1823 qcom,client-id = <1>; 1824 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 1825 }; 1826 1827 /* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */ 1828 tz_merged_mem: tz-merged@d8000000 { 1829 reg = <0 0xd8000000 0 0x800000>; 1830 no-map; 1831 }; 1832 1833 hwfence_shbuf: hwfence-shbuf@e6440000 { 1834 reg = <0 0xe6440000 0 0x2dd000>; 1835 no-map; 1836 }; 1837 1838 trust_ui_vm_mem: trust-ui-vm@f3800000 { 1839 reg = <0 0xf3800000 0 0x4400000>; 1840 no-map; 1841 }; 1842 1843 oem_vm_mem: oem-vm@f7c00000 { 1844 reg = <0 0xf7c00000 0 0x4c00000>; 1845 no-map; 1846 }; 1847 1848 llcc_lpi_mem: llcc-lpi@ff800000 { 1849 reg = <0 0xff800000 0 0x600000>; 1850 no-map; 1851 }; 1852 }; 1853 1854 smp2p-adsp { 1855 compatible = "qcom,smp2p"; 1856 1857 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1858 IPCC_MPROC_SIGNAL_SMP2P 1859 IRQ_TYPE_EDGE_RISING>; 1860 1861 mboxes = <&ipcc IPCC_CLIENT_LPASS 1862 IPCC_MPROC_SIGNAL_SMP2P>; 1863 1864 qcom,smem = <443>, <429>; 1865 qcom,local-pid = <0>; 1866 qcom,remote-pid = <2>; 1867 1868 smp2p_adsp_out: master-kernel { 1869 qcom,entry-name = "master-kernel"; 1870 #qcom,smem-state-cells = <1>; 1871 }; 1872 1873 smp2p_adsp_in: slave-kernel { 1874 qcom,entry-name = "slave-kernel"; 1875 interrupt-controller; 1876 #interrupt-cells = <2>; 1877 }; 1878 }; 1879 1880 smp2p-cdsp { 1881 compatible = "qcom,smp2p"; 1882 1883 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1884 IPCC_MPROC_SIGNAL_SMP2P 1885 IRQ_TYPE_EDGE_RISING>; 1886 1887 mboxes = <&ipcc IPCC_CLIENT_CDSP 1888 IPCC_MPROC_SIGNAL_SMP2P>; 1889 1890 qcom,smem = <94>, <432>; 1891 qcom,local-pid = <0>; 1892 qcom,remote-pid = <5>; 1893 1894 smp2p_cdsp_out: master-kernel { 1895 qcom,entry-name = "master-kernel"; 1896 #qcom,smem-state-cells = <1>; 1897 }; 1898 1899 smp2p_cdsp_in: slave-kernel { 1900 qcom,entry-name = "slave-kernel"; 1901 interrupt-controller; 1902 #interrupt-cells = <2>; 1903 }; 1904 }; 1905 1906 smp2p-modem { 1907 compatible = "qcom,smp2p"; 1908 1909 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1910 IPCC_MPROC_SIGNAL_SMP2P 1911 IRQ_TYPE_EDGE_RISING>; 1912 1913 mboxes = <&ipcc IPCC_CLIENT_MPSS 1914 IPCC_MPROC_SIGNAL_SMP2P>; 1915 1916 qcom,smem = <435>, <428>; 1917 qcom,local-pid = <0>; 1918 qcom,remote-pid = <1>; 1919 1920 smp2p_modem_out: master-kernel { 1921 qcom,entry-name = "master-kernel"; 1922 #qcom,smem-state-cells = <1>; 1923 }; 1924 1925 smp2p_modem_in: slave-kernel { 1926 qcom,entry-name = "slave-kernel"; 1927 interrupt-controller; 1928 #interrupt-cells = <2>; 1929 }; 1930 1931 ipa_smp2p_out: ipa-ap-to-modem { 1932 qcom,entry-name = "ipa"; 1933 #qcom,smem-state-cells = <1>; 1934 }; 1935 1936 ipa_smp2p_in: ipa-modem-to-ap { 1937 qcom,entry-name = "ipa"; 1938 interrupt-controller; 1939 #interrupt-cells = <2>; 1940 }; 1941 }; 1942 1943 soc: soc@0 { 1944 compatible = "simple-bus"; 1945 1946 #address-cells = <2>; 1947 #size-cells = <2>; 1948 dma-ranges = <0 0 0 0 0x10 0>; 1949 ranges = <0 0 0 0 0x10 0>; 1950 1951 gcc: clock-controller@100000 { 1952 compatible = "qcom,sm8650-gcc"; 1953 reg = <0 0x00100000 0 0x1f4200>; 1954 1955 clocks = <&bi_tcxo_div2>, 1956 <&bi_tcxo_ao_div2>, 1957 <&sleep_clk>, 1958 <&pcie0_phy>, 1959 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 1960 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 1961 <&ufs_mem_phy 0>, 1962 <&ufs_mem_phy 1>, 1963 <&ufs_mem_phy 2>, 1964 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 1965 1966 #clock-cells = <1>; 1967 #reset-cells = <1>; 1968 #power-domain-cells = <1>; 1969 }; 1970 1971 ipcc: mailbox@406000 { 1972 compatible = "qcom,sm8650-ipcc", "qcom,ipcc"; 1973 reg = <0 0x00406000 0 0x1000>; 1974 1975 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>; 1976 interrupt-controller; 1977 #interrupt-cells = <3>; 1978 1979 #mbox-cells = <2>; 1980 }; 1981 1982 gpi_dma2: dma-controller@800000 { 1983 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 1984 reg = <0 0x00800000 0 0x60000>; 1985 1986 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>, 1987 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>, 1988 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, 1989 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, 1990 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, 1991 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, 1992 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, 1993 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, 1994 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, 1995 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>, 1996 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>, 1997 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>; 1998 1999 dma-channels = <12>; 2000 dma-channel-mask = <0x3f>; 2001 #dma-cells = <3>; 2002 2003 iommus = <&apps_smmu 0x436 0>; 2004 2005 dma-coherent; 2006 2007 status = "disabled"; 2008 }; 2009 2010 qupv3_id_1: geniqup@8c0000 { 2011 compatible = "qcom,geni-se-qup"; 2012 reg = <0 0x008c0000 0 0x2000>; 2013 2014 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 2015 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 2016 clock-names = "m-ahb", 2017 "s-ahb"; 2018 2019 iommus = <&apps_smmu 0x423 0>; 2020 2021 dma-coherent; 2022 2023 #address-cells = <2>; 2024 #size-cells = <2>; 2025 ranges; 2026 2027 status = "disabled"; 2028 2029 i2c8: i2c@880000 { 2030 compatible = "qcom,geni-i2c"; 2031 reg = <0 0x00880000 0 0x4000>; 2032 2033 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 2034 2035 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 2036 clock-names = "se"; 2037 2038 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2039 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2040 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2041 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2042 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2043 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2044 interconnect-names = "qup-core", 2045 "qup-config", 2046 "qup-memory"; 2047 2048 power-domains = <&rpmhpd RPMHPD_CX>; 2049 2050 operating-points-v2 = <&qup_opp_table_120mhz>; 2051 2052 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 2053 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 2054 dma-names = "tx", 2055 "rx"; 2056 2057 pinctrl-0 = <&qup_i2c8_data_clk>; 2058 pinctrl-names = "default"; 2059 2060 #address-cells = <1>; 2061 #size-cells = <0>; 2062 2063 status = "disabled"; 2064 }; 2065 2066 spi8: spi@880000 { 2067 compatible = "qcom,geni-spi"; 2068 reg = <0 0x00880000 0 0x4000>; 2069 2070 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 2071 2072 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 2073 clock-names = "se"; 2074 2075 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2076 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2077 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2078 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2079 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2080 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2081 interconnect-names = "qup-core", 2082 "qup-config", 2083 "qup-memory"; 2084 2085 power-domains = <&rpmhpd RPMHPD_CX>; 2086 2087 operating-points-v2 = <&qup_opp_table_100mhz>; 2088 2089 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 2090 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 2091 dma-names = "tx", 2092 "rx"; 2093 2094 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 2095 pinctrl-names = "default"; 2096 2097 #address-cells = <1>; 2098 #size-cells = <0>; 2099 2100 status = "disabled"; 2101 }; 2102 2103 i2c9: i2c@884000 { 2104 compatible = "qcom,geni-i2c"; 2105 reg = <0 0x00884000 0 0x4000>; 2106 2107 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; 2108 2109 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 2110 clock-names = "se"; 2111 2112 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2113 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2114 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2115 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2116 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2117 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2118 interconnect-names = "qup-core", 2119 "qup-config", 2120 "qup-memory"; 2121 2122 power-domains = <&rpmhpd RPMHPD_CX>; 2123 2124 operating-points-v2 = <&qup_opp_table_120mhz>; 2125 2126 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 2127 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 2128 dma-names = "tx", 2129 "rx"; 2130 2131 pinctrl-0 = <&qup_i2c9_data_clk>; 2132 pinctrl-names = "default"; 2133 2134 #address-cells = <1>; 2135 #size-cells = <0>; 2136 2137 status = "disabled"; 2138 }; 2139 2140 spi9: spi@884000 { 2141 compatible = "qcom,geni-spi"; 2142 reg = <0 0x00884000 0 0x4000>; 2143 2144 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; 2145 2146 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 2147 clock-names = "se"; 2148 2149 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2150 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2151 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2152 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2153 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2154 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2155 interconnect-names = "qup-core", 2156 "qup-config", 2157 "qup-memory"; 2158 2159 power-domains = <&rpmhpd RPMHPD_CX>; 2160 2161 operating-points-v2 = <&qup_opp_table_120mhz>; 2162 2163 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 2164 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 2165 dma-names = "tx", 2166 "rx"; 2167 2168 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 2169 pinctrl-names = "default"; 2170 2171 #address-cells = <1>; 2172 #size-cells = <0>; 2173 2174 status = "disabled"; 2175 }; 2176 2177 i2c10: i2c@888000 { 2178 compatible = "qcom,geni-i2c"; 2179 reg = <0 0x00888000 0 0x4000>; 2180 2181 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; 2182 2183 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 2184 clock-names = "se"; 2185 2186 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2187 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2188 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2189 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2190 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2191 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2192 interconnect-names = "qup-core", 2193 "qup-config", 2194 "qup-memory"; 2195 2196 power-domains = <&rpmhpd RPMHPD_CX>; 2197 2198 operating-points-v2 = <&qup_opp_table_120mhz>; 2199 2200 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 2201 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 2202 dma-names = "tx", 2203 "rx"; 2204 2205 pinctrl-0 = <&qup_i2c10_data_clk>; 2206 pinctrl-names = "default"; 2207 2208 #address-cells = <1>; 2209 #size-cells = <0>; 2210 2211 status = "disabled"; 2212 }; 2213 2214 spi10: spi@888000 { 2215 compatible = "qcom,geni-spi"; 2216 reg = <0 0x00888000 0 0x4000>; 2217 2218 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; 2219 2220 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 2221 clock-names = "se"; 2222 2223 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2224 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2225 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2226 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2227 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2228 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2229 interconnect-names = "qup-core", 2230 "qup-config", 2231 "qup-memory"; 2232 2233 power-domains = <&rpmhpd RPMHPD_CX>; 2234 2235 operating-points-v2 = <&qup_opp_table_120mhz>; 2236 2237 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 2238 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 2239 dma-names = "tx", 2240 "rx"; 2241 2242 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 2243 pinctrl-names = "default"; 2244 2245 #address-cells = <1>; 2246 #size-cells = <0>; 2247 2248 status = "disabled"; 2249 }; 2250 2251 i2c11: i2c@88c000 { 2252 compatible = "qcom,geni-i2c"; 2253 reg = <0 0x0088c000 0 0x4000>; 2254 2255 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2256 2257 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 2258 clock-names = "se"; 2259 2260 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2261 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2262 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2263 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2264 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2265 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2266 interconnect-names = "qup-core", 2267 "qup-config", 2268 "qup-memory"; 2269 2270 power-domains = <&rpmhpd RPMHPD_CX>; 2271 2272 operating-points-v2 = <&qup_opp_table_120mhz>; 2273 2274 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 2275 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 2276 dma-names = "tx", 2277 "rx"; 2278 2279 pinctrl-0 = <&qup_i2c11_data_clk>; 2280 pinctrl-names = "default"; 2281 2282 #address-cells = <1>; 2283 #size-cells = <0>; 2284 2285 status = "disabled"; 2286 }; 2287 2288 spi11: spi@88c000 { 2289 compatible = "qcom,geni-spi"; 2290 reg = <0 0x0088c000 0 0x4000>; 2291 2292 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2293 2294 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 2295 clock-names = "se"; 2296 2297 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2298 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2299 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2300 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2301 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2302 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2303 interconnect-names = "qup-core", 2304 "qup-config", 2305 "qup-memory"; 2306 2307 power-domains = <&rpmhpd RPMHPD_CX>; 2308 2309 operating-points-v2 = <&qup_opp_table_120mhz>; 2310 2311 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 2312 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 2313 dma-names = "tx", 2314 "rx"; 2315 2316 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 2317 pinctrl-names = "default"; 2318 2319 #address-cells = <1>; 2320 #size-cells = <0>; 2321 2322 status = "disabled"; 2323 }; 2324 2325 i2c12: i2c@890000 { 2326 compatible = "qcom,geni-i2c"; 2327 reg = <0 0x00890000 0 0x4000>; 2328 2329 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2330 2331 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 2332 clock-names = "se"; 2333 2334 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2335 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2336 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2337 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2338 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2339 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2340 interconnect-names = "qup-core", 2341 "qup-config", 2342 "qup-memory"; 2343 2344 power-domains = <&rpmhpd RPMHPD_CX>; 2345 2346 operating-points-v2 = <&qup_opp_table_100mhz>; 2347 2348 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 2349 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 2350 dma-names = "tx", 2351 "rx"; 2352 2353 pinctrl-0 = <&qup_i2c12_data_clk>; 2354 pinctrl-names = "default"; 2355 2356 #address-cells = <1>; 2357 #size-cells = <0>; 2358 2359 status = "disabled"; 2360 }; 2361 2362 spi12: spi@890000 { 2363 compatible = "qcom,geni-spi"; 2364 reg = <0 0x00890000 0 0x4000>; 2365 2366 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2367 2368 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 2369 clock-names = "se"; 2370 2371 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2372 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2373 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2374 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2375 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2376 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2377 interconnect-names = "qup-core", 2378 "qup-config", 2379 "qup-memory"; 2380 2381 power-domains = <&rpmhpd RPMHPD_CX>; 2382 2383 operating-points-v2 = <&qup_opp_table_100mhz>; 2384 2385 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 2386 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 2387 dma-names = "tx", 2388 "rx"; 2389 2390 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 2391 pinctrl-names = "default"; 2392 2393 #address-cells = <1>; 2394 #size-cells = <0>; 2395 2396 status = "disabled"; 2397 }; 2398 2399 i2c13: i2c@894000 { 2400 compatible = "qcom,geni-i2c"; 2401 reg = <0 0x00894000 0 0x4000>; 2402 2403 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; 2404 2405 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 2406 clock-names = "se"; 2407 2408 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2409 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2410 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2411 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2412 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2413 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2414 interconnect-names = "qup-core", 2415 "qup-config", 2416 "qup-memory"; 2417 2418 power-domains = <&rpmhpd RPMHPD_CX>; 2419 2420 operating-points-v2 = <&qup_opp_table_100mhz>; 2421 2422 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 2423 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 2424 dma-names = "tx", 2425 "rx"; 2426 2427 pinctrl-0 = <&qup_i2c13_data_clk>; 2428 pinctrl-names = "default"; 2429 2430 #address-cells = <1>; 2431 #size-cells = <0>; 2432 2433 status = "disabled"; 2434 }; 2435 2436 spi13: spi@894000 { 2437 compatible = "qcom,geni-spi"; 2438 reg = <0 0x00894000 0 0x4000>; 2439 2440 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; 2441 2442 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 2443 clock-names = "se"; 2444 2445 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2446 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2447 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2448 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 2449 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 2450 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2451 interconnect-names = "qup-core", 2452 "qup-config", 2453 "qup-memory"; 2454 2455 power-domains = <&rpmhpd RPMHPD_CX>; 2456 2457 operating-points-v2 = <&qup_opp_table_100mhz>; 2458 2459 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 2460 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 2461 dma-names = "tx", 2462 "rx"; 2463 2464 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 2465 pinctrl-names = "default"; 2466 2467 #address-cells = <1>; 2468 #size-cells = <0>; 2469 2470 status = "disabled"; 2471 }; 2472 2473 uart14: serial@898000 { 2474 compatible = "qcom,geni-uart"; 2475 reg = <0 0x00898000 0 0x4000>; 2476 2477 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH 0>; 2478 2479 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 2480 clock-names = "se"; 2481 2482 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2483 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2484 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2485 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 2486 interconnect-names = "qup-core", 2487 "qup-config"; 2488 2489 power-domains = <&rpmhpd RPMHPD_CX>; 2490 2491 operating-points-v2 = <&qup_opp_table_128mhz>; 2492 2493 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 2494 pinctrl-names = "default"; 2495 2496 status = "disabled"; 2497 }; 2498 2499 uart15: serial@89c000 { 2500 compatible = "qcom,geni-debug-uart"; 2501 reg = <0 0x0089c000 0 0x4000>; 2502 2503 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 2504 2505 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 2506 clock-names = "se"; 2507 2508 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 2509 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 2510 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2511 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 2512 interconnect-names = "qup-core", 2513 "qup-config"; 2514 2515 power-domains = <&rpmhpd RPMHPD_CX>; 2516 2517 operating-points-v2 = <&qup_opp_table_100mhz>; 2518 2519 pinctrl-0 = <&qup_uart15_default>; 2520 pinctrl-names = "default"; 2521 2522 status = "disabled"; 2523 }; 2524 }; 2525 2526 i2c_master_hub_0: geniqup@9c0000 { 2527 compatible = "qcom,geni-se-i2c-master-hub"; 2528 reg = <0 0x009c0000 0 0x2000>; 2529 2530 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 2531 clock-names = "s-ahb"; 2532 2533 #address-cells = <2>; 2534 #size-cells = <2>; 2535 ranges; 2536 2537 status = "disabled"; 2538 2539 i2c_hub_0: i2c@980000 { 2540 compatible = "qcom,geni-i2c-master-hub"; 2541 reg = <0 0x00980000 0 0x4000>; 2542 2543 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>; 2544 2545 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 2546 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2547 clock-names = "se", 2548 "core"; 2549 2550 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2551 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2552 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2553 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2554 interconnect-names = "qup-core", 2555 "qup-config"; 2556 2557 power-domains = <&rpmhpd RPMHPD_CX>; 2558 2559 required-opps = <&rpmhpd_opp_low_svs>; 2560 2561 pinctrl-0 = <&hub_i2c0_data_clk>; 2562 pinctrl-names = "default"; 2563 2564 #address-cells = <1>; 2565 #size-cells = <0>; 2566 2567 status = "disabled"; 2568 }; 2569 2570 i2c_hub_1: i2c@984000 { 2571 compatible = "qcom,geni-i2c-master-hub"; 2572 reg = <0 0x00984000 0 0x4000>; 2573 2574 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH 0>; 2575 2576 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 2577 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2578 clock-names = "se", 2579 "core"; 2580 2581 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2582 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2583 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2584 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2585 interconnect-names = "qup-core", 2586 "qup-config"; 2587 2588 power-domains = <&rpmhpd RPMHPD_CX>; 2589 2590 required-opps = <&rpmhpd_opp_low_svs>; 2591 2592 pinctrl-0 = <&hub_i2c1_data_clk>; 2593 pinctrl-names = "default"; 2594 2595 #address-cells = <1>; 2596 #size-cells = <0>; 2597 2598 status = "disabled"; 2599 }; 2600 2601 i2c_hub_2: i2c@988000 { 2602 compatible = "qcom,geni-i2c-master-hub"; 2603 reg = <0 0x00988000 0 0x4000>; 2604 2605 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH 0>; 2606 2607 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 2608 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2609 clock-names = "se", 2610 "core"; 2611 2612 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2613 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2614 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2615 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2616 interconnect-names = "qup-core", 2617 "qup-config"; 2618 2619 power-domains = <&rpmhpd RPMHPD_CX>; 2620 2621 required-opps = <&rpmhpd_opp_low_svs>; 2622 2623 pinctrl-0 = <&hub_i2c2_data_clk>; 2624 pinctrl-names = "default"; 2625 2626 #address-cells = <1>; 2627 #size-cells = <0>; 2628 2629 status = "disabled"; 2630 }; 2631 2632 i2c_hub_3: i2c@98c000 { 2633 compatible = "qcom,geni-i2c-master-hub"; 2634 reg = <0 0x0098c000 0 0x4000>; 2635 2636 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>; 2637 2638 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 2639 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2640 clock-names = "se", 2641 "core"; 2642 2643 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2644 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2645 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2646 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2647 interconnect-names = "qup-core", 2648 "qup-config"; 2649 2650 power-domains = <&rpmhpd RPMHPD_CX>; 2651 2652 required-opps = <&rpmhpd_opp_low_svs>; 2653 2654 pinctrl-0 = <&hub_i2c3_data_clk>; 2655 pinctrl-names = "default"; 2656 2657 #address-cells = <1>; 2658 #size-cells = <0>; 2659 2660 status = "disabled"; 2661 }; 2662 2663 i2c_hub_4: i2c@990000 { 2664 compatible = "qcom,geni-i2c-master-hub"; 2665 reg = <0 0x00990000 0 0x4000>; 2666 2667 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>; 2668 2669 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 2670 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2671 clock-names = "se", 2672 "core"; 2673 2674 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2675 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2676 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2677 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2678 interconnect-names = "qup-core", 2679 "qup-config"; 2680 2681 power-domains = <&rpmhpd RPMHPD_CX>; 2682 2683 required-opps = <&rpmhpd_opp_low_svs>; 2684 2685 pinctrl-0 = <&hub_i2c4_data_clk>; 2686 pinctrl-names = "default"; 2687 2688 #address-cells = <1>; 2689 #size-cells = <0>; 2690 2691 status = "disabled"; 2692 }; 2693 2694 i2c_hub_5: i2c@994000 { 2695 compatible = "qcom,geni-i2c-master-hub"; 2696 reg = <0 0x00994000 0 0x4000>; 2697 2698 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH 0>; 2699 2700 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 2701 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2702 clock-names = "se", 2703 "core"; 2704 2705 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2706 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2707 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2708 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2709 interconnect-names = "qup-core", 2710 "qup-config"; 2711 2712 power-domains = <&rpmhpd RPMHPD_CX>; 2713 2714 required-opps = <&rpmhpd_opp_low_svs>; 2715 2716 pinctrl-0 = <&hub_i2c5_data_clk>; 2717 pinctrl-names = "default"; 2718 2719 #address-cells = <1>; 2720 #size-cells = <0>; 2721 2722 status = "disabled"; 2723 }; 2724 2725 i2c_hub_6: i2c@998000 { 2726 compatible = "qcom,geni-i2c-master-hub"; 2727 reg = <0 0x00998000 0 0x4000>; 2728 2729 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH 0>; 2730 2731 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 2732 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2733 clock-names = "se", 2734 "core"; 2735 2736 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2737 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2738 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2739 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2740 interconnect-names = "qup-core", 2741 "qup-config"; 2742 2743 power-domains = <&rpmhpd RPMHPD_CX>; 2744 2745 required-opps = <&rpmhpd_opp_low_svs>; 2746 2747 pinctrl-0 = <&hub_i2c6_data_clk>; 2748 pinctrl-names = "default"; 2749 2750 #address-cells = <1>; 2751 #size-cells = <0>; 2752 2753 status = "disabled"; 2754 }; 2755 2756 i2c_hub_7: i2c@99c000 { 2757 compatible = "qcom,geni-i2c-master-hub"; 2758 reg = <0 0x0099c000 0 0x4000>; 2759 2760 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; 2761 2762 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 2763 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2764 clock-names = "se", 2765 "core"; 2766 2767 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2768 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2769 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2770 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2771 interconnect-names = "qup-core", 2772 "qup-config"; 2773 2774 power-domains = <&rpmhpd RPMHPD_CX>; 2775 2776 required-opps = <&rpmhpd_opp_low_svs>; 2777 2778 pinctrl-0 = <&hub_i2c7_data_clk>; 2779 pinctrl-names = "default"; 2780 2781 #address-cells = <1>; 2782 #size-cells = <0>; 2783 2784 status = "disabled"; 2785 }; 2786 2787 i2c_hub_8: i2c@9a0000 { 2788 compatible = "qcom,geni-i2c-master-hub"; 2789 reg = <0 0x009a0000 0 0x4000>; 2790 2791 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH 0>; 2792 2793 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 2794 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2795 clock-names = "se", 2796 "core"; 2797 2798 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2799 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2800 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2801 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2802 interconnect-names = "qup-core", 2803 "qup-config"; 2804 2805 power-domains = <&rpmhpd RPMHPD_CX>; 2806 2807 required-opps = <&rpmhpd_opp_low_svs>; 2808 2809 pinctrl-0 = <&hub_i2c8_data_clk>; 2810 pinctrl-names = "default"; 2811 2812 #address-cells = <1>; 2813 #size-cells = <0>; 2814 2815 status = "disabled"; 2816 }; 2817 2818 i2c_hub_9: i2c@9a4000 { 2819 compatible = "qcom,geni-i2c-master-hub"; 2820 reg = <0 0x009a4000 0 0x4000>; 2821 2822 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH 0>; 2823 2824 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 2825 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 2826 clock-names = "se", 2827 "core"; 2828 2829 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2830 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2831 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2832 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 2833 interconnect-names = "qup-core", 2834 "qup-config"; 2835 2836 power-domains = <&rpmhpd RPMHPD_CX>; 2837 2838 required-opps = <&rpmhpd_opp_low_svs>; 2839 2840 pinctrl-0 = <&hub_i2c9_data_clk>; 2841 pinctrl-names = "default"; 2842 2843 #address-cells = <1>; 2844 #size-cells = <0>; 2845 2846 status = "disabled"; 2847 }; 2848 }; 2849 2850 gpi_dma1: dma-controller@a00000 { 2851 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 2852 reg = <0 0x00a00000 0 0x60000>; 2853 2854 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>, 2855 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>, 2856 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>, 2857 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>, 2858 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>, 2859 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>, 2860 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>, 2861 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>, 2862 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>, 2863 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>, 2864 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>, 2865 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 2866 2867 dma-channels = <12>; 2868 dma-channel-mask = <0xc>; 2869 #dma-cells = <3>; 2870 2871 iommus = <&apps_smmu 0xb6 0>; 2872 dma-coherent; 2873 2874 status = "disabled"; 2875 }; 2876 2877 qupv3_id_0: geniqup@ac0000 { 2878 compatible = "qcom,geni-se-qup"; 2879 reg = <0 0x00ac0000 0 0x2000>; 2880 2881 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 2882 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 2883 clock-names = "m-ahb", 2884 "s-ahb"; 2885 2886 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2887 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 2888 interconnect-names = "qup-core"; 2889 2890 iommus = <&apps_smmu 0xa3 0>; 2891 2892 dma-coherent; 2893 2894 #address-cells = <2>; 2895 #size-cells = <2>; 2896 ranges; 2897 2898 status = "disabled"; 2899 2900 i2c0: i2c@a80000 { 2901 compatible = "qcom,geni-i2c"; 2902 reg = <0 0x00a80000 0 0x4000>; 2903 2904 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 2905 2906 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2907 clock-names = "se"; 2908 2909 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2910 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2911 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2912 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2913 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2914 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2915 interconnect-names = "qup-core", 2916 "qup-config", 2917 "qup-memory"; 2918 2919 power-domains = <&rpmhpd RPMHPD_CX>; 2920 2921 operating-points-v2 = <&qup_opp_table_120mhz>; 2922 2923 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 2924 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 2925 dma-names = "tx", 2926 "rx"; 2927 2928 pinctrl-0 = <&qup_i2c0_data_clk>; 2929 pinctrl-names = "default"; 2930 2931 #address-cells = <1>; 2932 #size-cells = <0>; 2933 2934 status = "disabled"; 2935 }; 2936 2937 spi0: spi@a80000 { 2938 compatible = "qcom,geni-spi"; 2939 reg = <0 0x00a80000 0 0x4000>; 2940 2941 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 2942 2943 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2944 clock-names = "se"; 2945 2946 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2947 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2948 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2949 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2950 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2951 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2952 interconnect-names = "qup-core", 2953 "qup-config", 2954 "qup-memory"; 2955 2956 power-domains = <&rpmhpd RPMHPD_CX>; 2957 2958 operating-points-v2 = <&qup_opp_table_120mhz>; 2959 2960 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 2961 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 2962 dma-names = "tx", 2963 "rx"; 2964 2965 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2966 pinctrl-names = "default"; 2967 2968 #address-cells = <1>; 2969 #size-cells = <0>; 2970 2971 status = "disabled"; 2972 }; 2973 2974 i2c1: i2c@a84000 { 2975 compatible = "qcom,geni-i2c"; 2976 reg = <0 0x00a84000 0 0x4000>; 2977 2978 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 2979 2980 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2981 clock-names = "se"; 2982 2983 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2984 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2985 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2986 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2987 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2988 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2989 interconnect-names = "qup-core", 2990 "qup-config", 2991 "qup-memory"; 2992 2993 power-domains = <&rpmhpd RPMHPD_CX>; 2994 2995 operating-points-v2 = <&qup_opp_table_120mhz>; 2996 2997 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 2998 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 2999 dma-names = "tx", 3000 "rx"; 3001 3002 pinctrl-0 = <&qup_i2c1_data_clk>; 3003 pinctrl-names = "default"; 3004 3005 #address-cells = <1>; 3006 #size-cells = <0>; 3007 3008 status = "disabled"; 3009 }; 3010 3011 spi1: spi@a84000 { 3012 compatible = "qcom,geni-spi"; 3013 reg = <0 0x00a84000 0 0x4000>; 3014 3015 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 3016 3017 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 3018 clock-names = "se"; 3019 3020 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3021 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3022 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3023 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3024 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3025 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3026 interconnect-names = "qup-core", 3027 "qup-config", 3028 "qup-memory"; 3029 3030 power-domains = <&rpmhpd RPMHPD_CX>; 3031 3032 operating-points-v2 = <&qup_opp_table_120mhz>; 3033 3034 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 3035 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 3036 dma-names = "tx", 3037 "rx"; 3038 3039 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 3040 pinctrl-names = "default"; 3041 3042 #address-cells = <1>; 3043 #size-cells = <0>; 3044 3045 status = "disabled"; 3046 }; 3047 3048 i2c2: i2c@a88000 { 3049 compatible = "qcom,geni-i2c"; 3050 reg = <0 0x00a88000 0 0x4000>; 3051 3052 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 3053 3054 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 3055 clock-names = "se"; 3056 3057 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3058 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3059 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3060 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3061 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3062 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3063 interconnect-names = "qup-core", 3064 "qup-config", 3065 "qup-memory"; 3066 3067 power-domains = <&rpmhpd RPMHPD_CX>; 3068 3069 operating-points-v2 = <&qup_opp_table_240mhz>; 3070 3071 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 3072 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 3073 dma-names = "tx", 3074 "rx"; 3075 3076 pinctrl-0 = <&qup_i2c2_data_clk>; 3077 pinctrl-names = "default"; 3078 3079 #address-cells = <1>; 3080 #size-cells = <0>; 3081 3082 status = "disabled"; 3083 }; 3084 3085 spi2: spi@a88000 { 3086 compatible = "qcom,geni-spi"; 3087 reg = <0 0x00a88000 0 0x4000>; 3088 3089 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 3090 3091 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 3092 clock-names = "se"; 3093 3094 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3095 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3096 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3097 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3098 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3099 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3100 interconnect-names = "qup-core", 3101 "qup-config", 3102 "qup-memory"; 3103 3104 power-domains = <&rpmhpd RPMHPD_CX>; 3105 3106 operating-points-v2 = <&qup_opp_table_240mhz>; 3107 3108 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 3109 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 3110 dma-names = "tx", 3111 "rx"; 3112 3113 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 3114 pinctrl-names = "default"; 3115 3116 #address-cells = <1>; 3117 #size-cells = <0>; 3118 3119 status = "disabled"; 3120 }; 3121 3122 i2c3: i2c@a8c000 { 3123 compatible = "qcom,geni-i2c"; 3124 reg = <0 0x00a8c000 0 0x4000>; 3125 3126 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 3127 3128 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 3129 clock-names = "se"; 3130 3131 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3132 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3133 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3134 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3135 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3136 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3137 interconnect-names = "qup-core", 3138 "qup-config", 3139 "qup-memory"; 3140 3141 power-domains = <&rpmhpd RPMHPD_CX>; 3142 3143 operating-points-v2 = <&qup_opp_table_100mhz>; 3144 3145 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 3146 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 3147 dma-names = "tx", 3148 "rx"; 3149 3150 pinctrl-0 = <&qup_i2c3_data_clk>; 3151 pinctrl-names = "default"; 3152 3153 #address-cells = <1>; 3154 #size-cells = <0>; 3155 3156 status = "disabled"; 3157 }; 3158 3159 spi3: spi@a8c000 { 3160 compatible = "qcom,geni-spi"; 3161 reg = <0 0x00a8c000 0 0x4000>; 3162 3163 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 3164 3165 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 3166 clock-names = "se"; 3167 3168 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3169 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3170 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3171 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3172 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3173 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3174 interconnect-names = "qup-core", 3175 "qup-config", 3176 "qup-memory"; 3177 3178 power-domains = <&rpmhpd RPMHPD_CX>; 3179 3180 operating-points-v2 = <&qup_opp_table_100mhz>; 3181 3182 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 3183 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 3184 dma-names = "tx", 3185 "rx"; 3186 3187 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 3188 pinctrl-names = "default"; 3189 3190 #address-cells = <1>; 3191 #size-cells = <0>; 3192 3193 status = "disabled"; 3194 }; 3195 3196 i2c4: i2c@a90000 { 3197 compatible = "qcom,geni-i2c"; 3198 reg = <0 0x00a90000 0 0x4000>; 3199 3200 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; 3201 3202 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 3203 clock-names = "se"; 3204 3205 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3206 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3207 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3208 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3209 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3210 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3211 interconnect-names = "qup-core", 3212 "qup-config", 3213 "qup-memory"; 3214 3215 power-domains = <&rpmhpd RPMHPD_CX>; 3216 3217 operating-points-v2 = <&qup_opp_table_120mhz>; 3218 3219 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 3220 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 3221 dma-names = "tx", 3222 "rx"; 3223 3224 pinctrl-0 = <&qup_i2c4_data_clk>; 3225 pinctrl-names = "default"; 3226 3227 #address-cells = <1>; 3228 #size-cells = <0>; 3229 3230 status = "disabled"; 3231 }; 3232 3233 spi4: spi@a90000 { 3234 compatible = "qcom,geni-spi"; 3235 reg = <0 0x00a90000 0 0x4000>; 3236 3237 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; 3238 3239 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 3240 clock-names = "se"; 3241 3242 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3243 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3244 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3245 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3246 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3247 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3248 interconnect-names = "qup-core", 3249 "qup-config", 3250 "qup-memory"; 3251 3252 power-domains = <&rpmhpd RPMHPD_CX>; 3253 3254 operating-points-v2 = <&qup_opp_table_120mhz>; 3255 3256 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 3257 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 3258 dma-names = "tx", 3259 "rx"; 3260 3261 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 3262 pinctrl-names = "default"; 3263 3264 #address-cells = <1>; 3265 #size-cells = <0>; 3266 3267 status = "disabled"; 3268 }; 3269 3270 i2c5: i2c@a94000 { 3271 compatible = "qcom,geni-i2c"; 3272 reg = <0 0x00a94000 0 0x4000>; 3273 3274 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; 3275 3276 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 3277 clock-names = "se"; 3278 3279 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3280 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3281 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3282 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3283 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3284 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3285 interconnect-names = "qup-core", 3286 "qup-config", 3287 "qup-memory"; 3288 3289 power-domains = <&rpmhpd RPMHPD_CX>; 3290 3291 operating-points-v2 = <&qup_opp_table_100mhz>; 3292 3293 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 3294 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 3295 dma-names = "tx", 3296 "rx"; 3297 3298 pinctrl-0 = <&qup_i2c5_data_clk>; 3299 pinctrl-names = "default"; 3300 3301 #address-cells = <1>; 3302 #size-cells = <0>; 3303 3304 status = "disabled"; 3305 }; 3306 3307 spi5: spi@a94000 { 3308 compatible = "qcom,geni-spi"; 3309 reg = <0 0x00a94000 0 0x4000>; 3310 3311 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; 3312 3313 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 3314 clock-names = "se"; 3315 3316 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3317 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3318 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3319 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3320 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3321 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3322 interconnect-names = "qup-core", 3323 "qup-config", 3324 "qup-memory"; 3325 3326 power-domains = <&rpmhpd RPMHPD_CX>; 3327 3328 operating-points-v2 = <&qup_opp_table_100mhz>; 3329 3330 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 3331 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 3332 dma-names = "tx", 3333 "rx"; 3334 3335 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 3336 pinctrl-names = "default"; 3337 3338 #address-cells = <1>; 3339 #size-cells = <0>; 3340 3341 status = "disabled"; 3342 }; 3343 3344 i2c6: i2c@a98000 { 3345 compatible = "qcom,geni-i2c"; 3346 reg = <0 0x00a98000 0 0x4000>; 3347 3348 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 3349 3350 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 3351 clock-names = "se"; 3352 3353 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3354 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3355 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3356 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3357 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3358 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3359 interconnect-names = "qup-core", 3360 "qup-config", 3361 "qup-memory"; 3362 3363 power-domains = <&rpmhpd RPMHPD_CX>; 3364 3365 operating-points-v2 = <&qup_opp_table_120mhz>; 3366 3367 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 3368 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 3369 dma-names = "tx", 3370 "rx"; 3371 3372 pinctrl-0 = <&qup_i2c6_data_clk>; 3373 pinctrl-names = "default"; 3374 3375 #address-cells = <1>; 3376 #size-cells = <0>; 3377 3378 status = "disabled"; 3379 }; 3380 3381 spi6: spi@a98000 { 3382 compatible = "qcom,geni-spi"; 3383 reg = <0 0x00a98000 0 0x4000>; 3384 3385 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 3386 3387 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 3388 clock-names = "se"; 3389 3390 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3391 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3392 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3393 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3394 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3395 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3396 interconnect-names = "qup-core", 3397 "qup-config", 3398 "qup-memory"; 3399 3400 power-domains = <&rpmhpd RPMHPD_CX>; 3401 3402 operating-points-v2 = <&qup_opp_table_120mhz>; 3403 3404 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 3405 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 3406 dma-names = "tx", 3407 "rx"; 3408 3409 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 3410 pinctrl-names = "default"; 3411 3412 #address-cells = <1>; 3413 #size-cells = <0>; 3414 3415 status = "disabled"; 3416 }; 3417 3418 i2c7: i2c@a9c000 { 3419 compatible = "qcom,geni-i2c"; 3420 reg = <0 0x00a9c000 0 0x4000>; 3421 3422 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>; 3423 3424 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 3425 clock-names = "se"; 3426 3427 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3428 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3429 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3430 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3431 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3432 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3433 interconnect-names = "qup-core", 3434 "qup-config", 3435 "qup-memory"; 3436 3437 power-domains = <&rpmhpd RPMHPD_CX>; 3438 3439 operating-points-v2 = <&qup_opp_table_100mhz>; 3440 3441 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 3442 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 3443 dma-names = "tx", 3444 "rx"; 3445 3446 pinctrl-0 = <&qup_i2c7_data_clk>; 3447 pinctrl-names = "default"; 3448 3449 #address-cells = <1>; 3450 #size-cells = <0>; 3451 3452 status = "disabled"; 3453 }; 3454 3455 spi7: spi@a9c000 { 3456 compatible = "qcom,geni-spi"; 3457 reg = <0 0x00a9c000 0 0x4000>; 3458 3459 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>; 3460 3461 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 3462 clock-names = "se"; 3463 3464 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 3465 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 3466 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3467 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3468 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 3469 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3470 interconnect-names = "qup-core", 3471 "qup-config", 3472 "qup-memory"; 3473 3474 power-domains = <&rpmhpd RPMHPD_CX>; 3475 3476 operating-points-v2 = <&qup_opp_table_100mhz>; 3477 3478 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 3479 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 3480 dma-names = "tx", 3481 "rx"; 3482 3483 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 3484 pinctrl-names = "default"; 3485 3486 #address-cells = <1>; 3487 #size-cells = <0>; 3488 3489 status = "disabled"; 3490 }; 3491 }; 3492 3493 rng: rng@10c3000 { 3494 compatible = "qcom,sm8650-trng", "qcom,trng"; 3495 reg = <0 0x010c3000 0 0x1000>; 3496 }; 3497 3498 cnoc_main: interconnect@1500000 { 3499 compatible = "qcom,sm8650-cnoc-main"; 3500 reg = <0 0x01500000 0 0x14080>; 3501 3502 qcom,bcm-voters = <&apps_bcm_voter>; 3503 3504 #interconnect-cells = <2>; 3505 }; 3506 3507 config_noc: interconnect@1600000 { 3508 compatible = "qcom,sm8650-config-noc"; 3509 reg = <0 0x01600000 0 0x6200>; 3510 3511 qcom,bcm-voters = <&apps_bcm_voter>; 3512 3513 #interconnect-cells = <2>; 3514 }; 3515 3516 system_noc: interconnect@1680000 { 3517 compatible = "qcom,sm8650-system-noc"; 3518 reg = <0 0x01680000 0 0x1d080>; 3519 3520 qcom,bcm-voters = <&apps_bcm_voter>; 3521 3522 #interconnect-cells = <2>; 3523 }; 3524 3525 pcie_noc: interconnect@16c0000 { 3526 compatible = "qcom,sm8650-pcie-anoc"; 3527 reg = <0 0x016c0000 0 0x12200>; 3528 3529 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 3530 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 3531 3532 qcom,bcm-voters = <&apps_bcm_voter>; 3533 3534 #interconnect-cells = <2>; 3535 }; 3536 3537 aggre1_noc: interconnect@16e0000 { 3538 compatible = "qcom,sm8650-aggre1-noc"; 3539 reg = <0 0x016e0000 0 0x16400>; 3540 3541 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3542 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 3543 3544 qcom,bcm-voters = <&apps_bcm_voter>; 3545 3546 #interconnect-cells = <2>; 3547 }; 3548 3549 aggre2_noc: interconnect@1700000 { 3550 compatible = "qcom,sm8650-aggre2-noc"; 3551 reg = <0 0x01700000 0 0x1e400>; 3552 3553 clocks = <&rpmhcc RPMH_IPA_CLK>; 3554 3555 qcom,bcm-voters = <&apps_bcm_voter>; 3556 3557 #interconnect-cells = <2>; 3558 }; 3559 3560 mmss_noc: interconnect@1780000 { 3561 compatible = "qcom,sm8650-mmss-noc"; 3562 reg = <0 0x01780000 0 0x5b800>; 3563 3564 qcom,bcm-voters = <&apps_bcm_voter>; 3565 3566 #interconnect-cells = <2>; 3567 }; 3568 3569 pcie0: pcie@1c00000 { 3570 device_type = "pci"; 3571 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 3572 reg = <0 0x01c00000 0 0x3000>, 3573 <0 0x60000000 0 0xf1d>, 3574 <0 0x60000f20 0 0xa8>, 3575 <0 0x60001000 0 0x1000>, 3576 <0 0x60100000 0 0x100000>; 3577 reg-names = "parf", "dbi", "elbi", "atu", "config"; 3578 3579 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>, 3580 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>, 3581 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>, 3582 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>, 3583 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>, 3584 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>, 3585 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>, 3586 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>, 3587 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>; 3588 interrupt-names = "msi0", 3589 "msi1", 3590 "msi2", 3591 "msi3", 3592 "msi4", 3593 "msi5", 3594 "msi6", 3595 "msi7", 3596 "global"; 3597 3598 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 3599 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 3600 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 3601 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 3602 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 3603 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 3604 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 3605 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 3606 clock-names = "aux", 3607 "cfg", 3608 "bus_master", 3609 "bus_slave", 3610 "slave_q2a", 3611 "ddrss_sf_tbu", 3612 "noc_aggr", 3613 "cnoc_sf_axi"; 3614 3615 resets = <&gcc GCC_PCIE_0_BCR>; 3616 reset-names = "pci"; 3617 3618 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 3619 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3620 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3621 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 3622 interconnect-names = "pcie-mem", 3623 "cpu-pcie"; 3624 3625 power-domains = <&gcc PCIE_0_GDSC>; 3626 3627 operating-points-v2 = <&pcie0_opp_table>; 3628 3629 iommu-map = <0 &apps_smmu 0x1400 0x1>, 3630 <0x100 &apps_smmu 0x1401 0x1>; 3631 3632 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, 3633 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, 3634 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, 3635 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 3636 interrupt-map-mask = <0 0 0 0x7>; 3637 #interrupt-cells = <1>; 3638 3639 msi-map = <0x0 &gic_its 0x1400 0x1>, 3640 <0x100 &gic_its 0x1401 0x1>; 3641 msi-map-mask = <0xff00>; 3642 3643 linux,pci-domain = <0>; 3644 num-lanes = <2>; 3645 bus-range = <0 0xff>; 3646 3647 phys = <&pcie0_phy>; 3648 phy-names = "pciephy"; 3649 3650 #address-cells = <3>; 3651 #size-cells = <2>; 3652 ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, 3653 <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>; 3654 3655 dma-coherent; 3656 3657 status = "disabled"; 3658 3659 pcie0_opp_table: opp-table { 3660 compatible = "operating-points-v2"; 3661 3662 /* 2.5 GT/s x1 */ 3663 opp-2500000-1 { 3664 opp-hz = /bits/ 64 <2500000>; 3665 required-opps = <&rpmhpd_opp_low_svs>; 3666 opp-peak-kBps = <250000 1>; 3667 opp-level = <1>; 3668 }; 3669 3670 /* 2.5 GT/s x2 */ 3671 opp-5000000-1 { 3672 opp-hz = /bits/ 64 <5000000>; 3673 required-opps = <&rpmhpd_opp_low_svs>; 3674 opp-peak-kBps = <500000 1>; 3675 opp-level = <1>; 3676 }; 3677 3678 /* 5 GT/s x1 */ 3679 opp-5000000-2 { 3680 opp-hz = /bits/ 64 <5000000>; 3681 required-opps = <&rpmhpd_opp_low_svs>; 3682 opp-peak-kBps = <500000 1>; 3683 opp-level = <2>; 3684 }; 3685 3686 /* 5 GT/s x2 */ 3687 opp-10000000-2 { 3688 opp-hz = /bits/ 64 <10000000>; 3689 required-opps = <&rpmhpd_opp_low_svs>; 3690 opp-peak-kBps = <1000000 1>; 3691 opp-level = <2>; 3692 }; 3693 3694 /* 8 GT/s x1 */ 3695 opp-8000000-3 { 3696 opp-hz = /bits/ 64 <8000000>; 3697 required-opps = <&rpmhpd_opp_nom>; 3698 opp-peak-kBps = <984500 1>; 3699 opp-level = <3>; 3700 }; 3701 3702 /* 8 GT/s x2 */ 3703 opp-16000000-3 { 3704 opp-hz = /bits/ 64 <16000000>; 3705 required-opps = <&rpmhpd_opp_nom>; 3706 opp-peak-kBps = <1969000 1>; 3707 opp-level = <3>; 3708 }; 3709 }; 3710 3711 pcieport0: pcie@0 { 3712 device_type = "pci"; 3713 reg = <0x0 0x0 0x0 0x0 0x0>; 3714 bus-range = <0x01 0xff>; 3715 3716 #address-cells = <3>; 3717 #size-cells = <2>; 3718 ranges; 3719 }; 3720 }; 3721 3722 pcie0_phy: phy@1c06000 { 3723 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy"; 3724 reg = <0 0x01c06000 0 0x2000>; 3725 3726 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 3727 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 3728 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 3729 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 3730 <&gcc GCC_PCIE_0_PIPE_CLK>; 3731 clock-names = "aux", 3732 "cfg_ahb", 3733 "ref", 3734 "rchng", 3735 "pipe"; 3736 3737 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 3738 assigned-clock-rates = <100000000>; 3739 3740 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 3741 reset-names = "phy"; 3742 3743 power-domains = <&gcc PCIE_0_PHY_GDSC>; 3744 3745 #clock-cells = <0>; 3746 clock-output-names = "pcie0_pipe_clk"; 3747 3748 #phy-cells = <0>; 3749 3750 status = "disabled"; 3751 }; 3752 3753 pcie1: pcie@1c08000 { 3754 device_type = "pci"; 3755 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 3756 reg = <0 0x01c08000 0 0x3000>, 3757 <0 0x40000000 0 0xf1d>, 3758 <0 0x40000f20 0 0xa8>, 3759 <0 0x40001000 0 0x1000>, 3760 <0 0x40100000 0 0x100000>; 3761 reg-names = "parf", 3762 "dbi", 3763 "elbi", 3764 "atu", 3765 "config"; 3766 3767 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>, 3768 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>, 3769 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>, 3770 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 0>, 3771 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>, 3772 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 0>, 3773 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, 3774 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH 0>, 3775 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 3776 interrupt-names = "msi0", 3777 "msi1", 3778 "msi2", 3779 "msi3", 3780 "msi4", 3781 "msi5", 3782 "msi6", 3783 "msi7", 3784 "global"; 3785 3786 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 3787 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 3788 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 3789 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 3790 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 3791 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 3792 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 3793 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 3794 clock-names = "aux", 3795 "cfg", 3796 "bus_master", 3797 "bus_slave", 3798 "slave_q2a", 3799 "ddrss_sf_tbu", 3800 "noc_aggr", 3801 "cnoc_sf_axi"; 3802 3803 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 3804 assigned-clock-rates = <19200000>; 3805 3806 resets = <&gcc GCC_PCIE_1_BCR>, 3807 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 3808 reset-names = "pci", 3809 "link_down"; 3810 3811 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 3812 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3813 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3814 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3815 interconnect-names = "pcie-mem", 3816 "cpu-pcie"; 3817 3818 power-domains = <&gcc PCIE_1_GDSC>; 3819 3820 operating-points-v2 = <&pcie1_opp_table>; 3821 3822 iommu-map = <0 &apps_smmu 0x1480 0x1>, 3823 <0x100 &apps_smmu 0x1481 0x1>; 3824 3825 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, 3826 <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, 3827 <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, 3828 <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; 3829 interrupt-map-mask = <0 0 0 0x7>; 3830 #interrupt-cells = <1>; 3831 3832 msi-map = <0x0 &gic_its 0x1480 0x1>, 3833 <0x100 &gic_its 0x1481 0x1>; 3834 msi-map-mask = <0xff00>; 3835 3836 linux,pci-domain = <1>; 3837 num-lanes = <2>; 3838 bus-range = <0 0xff>; 3839 3840 phys = <&pcie1_phy>; 3841 phy-names = "pciephy"; 3842 3843 dma-coherent; 3844 3845 #address-cells = <3>; 3846 #size-cells = <2>; 3847 ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, 3848 <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; 3849 3850 status = "disabled"; 3851 3852 pcie1_opp_table: opp-table { 3853 compatible = "operating-points-v2"; 3854 3855 /* 2.5 GT/s x1 */ 3856 opp-2500000-1 { 3857 opp-hz = /bits/ 64 <2500000>; 3858 required-opps = <&rpmhpd_opp_low_svs>; 3859 opp-peak-kBps = <250000 1>; 3860 opp-level = <1>; 3861 }; 3862 3863 /* 2.5 GT/s x2 */ 3864 opp-5000000-1 { 3865 opp-hz = /bits/ 64 <5000000>; 3866 required-opps = <&rpmhpd_opp_low_svs>; 3867 opp-peak-kBps = <500000 1>; 3868 opp-level = <1>; 3869 }; 3870 3871 /* 5 GT/s x1 */ 3872 opp-5000000-2 { 3873 opp-hz = /bits/ 64 <5000000>; 3874 required-opps = <&rpmhpd_opp_low_svs>; 3875 opp-peak-kBps = <500000 1>; 3876 opp-level = <2>; 3877 }; 3878 3879 /* 5 GT/s x2 */ 3880 opp-10000000-2 { 3881 opp-hz = /bits/ 64 <10000000>; 3882 required-opps = <&rpmhpd_opp_low_svs>; 3883 opp-peak-kBps = <1000000 1>; 3884 opp-level = <2>; 3885 }; 3886 3887 /* 8 GT/s x1 */ 3888 opp-8000000-3 { 3889 opp-hz = /bits/ 64 <8000000>; 3890 required-opps = <&rpmhpd_opp_nom>; 3891 opp-peak-kBps = <984500 1>; 3892 opp-level = <3>; 3893 }; 3894 3895 /* 8 GT/s x2 */ 3896 opp-16000000-3 { 3897 opp-hz = /bits/ 64 <16000000>; 3898 required-opps = <&rpmhpd_opp_nom>; 3899 opp-peak-kBps = <1969000 1>; 3900 opp-level = <3>; 3901 }; 3902 3903 /* 16 GT/s x1 */ 3904 opp-16000000-4 { 3905 opp-hz = /bits/ 64 <16000000>; 3906 required-opps = <&rpmhpd_opp_nom>; 3907 opp-peak-kBps = <1969000 1>; 3908 opp-level = <4>; 3909 }; 3910 3911 /* 16 GT/s x2 */ 3912 opp-32000000-4 { 3913 opp-hz = /bits/ 64 <32000000>; 3914 required-opps = <&rpmhpd_opp_nom>; 3915 opp-peak-kBps = <3938000 1>; 3916 opp-level = <4>; 3917 }; 3918 }; 3919 3920 pcie@0 { 3921 device_type = "pci"; 3922 reg = <0x0 0x0 0x0 0x0 0x0>; 3923 bus-range = <0x01 0xff>; 3924 3925 #address-cells = <3>; 3926 #size-cells = <2>; 3927 ranges; 3928 }; 3929 }; 3930 3931 pcie1_phy: phy@1c0e000 { 3932 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy"; 3933 reg = <0 0x01c0e000 0 0x2000>; 3934 3935 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 3936 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 3937 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 3938 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 3939 <&gcc GCC_PCIE_1_PIPE_CLK>; 3940 clock-names = "aux", 3941 "cfg_ahb", 3942 "ref", 3943 "rchng", 3944 "pipe"; 3945 3946 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 3947 assigned-clock-rates = <100000000>; 3948 3949 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 3950 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 3951 reset-names = "phy", 3952 "phy_nocsr"; 3953 3954 power-domains = <&gcc PCIE_1_PHY_GDSC>; 3955 3956 #clock-cells = <1>; 3957 clock-output-names = "pcie1_pipe_clk"; 3958 3959 #phy-cells = <0>; 3960 3961 status = "disabled"; 3962 }; 3963 3964 ufs_mem_phy: phy@1d80000 { 3965 compatible = "qcom,sm8650-qmp-ufs-phy"; 3966 reg = <0 0x01d80000 0 0x2000>; 3967 3968 clocks = <&rpmhcc RPMH_CXO_CLK>, 3969 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 3970 <&tcsr TCSR_UFS_CLKREF_EN>; 3971 clock-names = "ref", 3972 "ref_aux", 3973 "qref"; 3974 3975 resets = <&ufs_mem_hc 0>; 3976 reset-names = "ufsphy"; 3977 3978 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 3979 3980 #clock-cells = <1>; 3981 #phy-cells = <0>; 3982 3983 status = "disabled"; 3984 }; 3985 3986 ufs_mem_hc: ufshc@1d84000 { 3987 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 3988 reg = <0 0x01d84000 0 0x3000>; 3989 3990 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 3991 3992 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 3993 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3994 <&gcc GCC_UFS_PHY_AHB_CLK>, 3995 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 3996 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 3997 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 3998 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 3999 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 4000 clock-names = "core_clk", 4001 "bus_aggr_clk", 4002 "iface_clk", 4003 "core_clk_unipro", 4004 "ref_clk", 4005 "tx_lane0_sync_clk", 4006 "rx_lane0_sync_clk", 4007 "rx_lane1_sync_clk"; 4008 4009 resets = <&gcc GCC_UFS_PHY_BCR>; 4010 reset-names = "rst"; 4011 4012 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 4013 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4014 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4015 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4016 interconnect-names = "ufs-ddr", 4017 "cpu-ufs"; 4018 4019 power-domains = <&gcc UFS_PHY_GDSC>; 4020 required-opps = <&rpmhpd_opp_nom>; 4021 4022 operating-points-v2 = <&ufs_opp_table>; 4023 4024 iommus = <&apps_smmu 0x60 0>; 4025 4026 dma-coherent; 4027 4028 lanes-per-direction = <2>; 4029 qcom,ice = <&ice>; 4030 4031 phys = <&ufs_mem_phy>; 4032 phy-names = "ufsphy"; 4033 4034 #reset-cells = <1>; 4035 4036 status = "disabled"; 4037 4038 ufs_opp_table: opp-table { 4039 compatible = "operating-points-v2"; 4040 4041 opp-100000000 { 4042 opp-hz = /bits/ 64 <100000000>, 4043 /bits/ 64 <0>, 4044 /bits/ 64 <0>, 4045 /bits/ 64 <100000000>, 4046 /bits/ 64 <0>, 4047 /bits/ 64 <0>, 4048 /bits/ 64 <0>, 4049 /bits/ 64 <0>; 4050 required-opps = <&rpmhpd_opp_low_svs>; 4051 }; 4052 4053 opp-201500000 { 4054 opp-hz = /bits/ 64 <201500000>, 4055 /bits/ 64 <0>, 4056 /bits/ 64 <0>, 4057 /bits/ 64 <201500000>, 4058 /bits/ 64 <0>, 4059 /bits/ 64 <0>, 4060 /bits/ 64 <0>, 4061 /bits/ 64 <0>; 4062 required-opps = <&rpmhpd_opp_svs>; 4063 }; 4064 4065 opp-403000000 { 4066 opp-hz = /bits/ 64 <403000000>, 4067 /bits/ 64 <0>, 4068 /bits/ 64 <0>, 4069 /bits/ 64 <403000000>, 4070 /bits/ 64 <0>, 4071 /bits/ 64 <0>, 4072 /bits/ 64 <0>, 4073 /bits/ 64 <0>; 4074 required-opps = <&rpmhpd_opp_nom>; 4075 }; 4076 }; 4077 }; 4078 4079 ice: crypto@1d88000 { 4080 compatible = "qcom,sm8650-inline-crypto-engine", 4081 "qcom,inline-crypto-engine"; 4082 reg = <0 0x01d88000 0 0x18000>; 4083 4084 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4085 }; 4086 4087 cryptobam: dma-controller@1dc4000 { 4088 compatible = "qcom,bam-v1.7.0"; 4089 reg = <0 0x01dc4000 0 0x28000>; 4090 4091 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; 4092 4093 #dma-cells = <1>; 4094 4095 iommus = <&apps_smmu 0x480 0>, 4096 <&apps_smmu 0x481 0>; 4097 4098 qcom,ee = <0>; 4099 qcom,num-ees = <4>; 4100 num-channels = <20>; 4101 qcom,controlled-remotely; 4102 }; 4103 4104 crypto: crypto@1dfa000 { 4105 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; 4106 reg = <0 0x01dfa000 0 0x6000>; 4107 4108 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 4109 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4110 interconnect-names = "memory"; 4111 4112 dmas = <&cryptobam 4>, <&cryptobam 5>; 4113 dma-names = "rx", "tx"; 4114 4115 iommus = <&apps_smmu 0x480 0>, 4116 <&apps_smmu 0x481 0>; 4117 }; 4118 4119 tcsr_mutex: hwlock@1f40000 { 4120 compatible = "qcom,tcsr-mutex"; 4121 reg = <0 0x01f40000 0 0x20000>; 4122 4123 #hwlock-cells = <1>; 4124 }; 4125 4126 tcsr: clock-controller@1fc0000 { 4127 compatible = "qcom,sm8650-tcsr", "syscon"; 4128 reg = <0 0x01fc0000 0 0xa0000>; 4129 4130 clocks = <&rpmhcc RPMH_CXO_CLK>; 4131 4132 #clock-cells = <1>; 4133 #reset-cells = <1>; 4134 }; 4135 4136 gpu: gpu@3d00000 { 4137 compatible = "qcom,adreno-43051401", "qcom,adreno"; 4138 reg = <0x0 0x03d00000 0x0 0x40000>, 4139 <0x0 0x03d9e000 0x0 0x2000>, 4140 <0x0 0x03d61000 0x0 0x800>; 4141 reg-names = "kgsl_3d0_reg_memory", 4142 "cx_mem", 4143 "cx_dbgc"; 4144 4145 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; 4146 4147 iommus = <&adreno_smmu 0 0x0>, 4148 <&adreno_smmu 1 0x0>; 4149 4150 operating-points-v2 = <&gpu_opp_table>; 4151 4152 qcom,gmu = <&gmu>; 4153 #cooling-cells = <2>; 4154 4155 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4156 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4157 interconnect-names = "gfx-mem"; 4158 4159 status = "disabled"; 4160 4161 gpu_zap_shader: zap-shader { 4162 memory-region = <&gpu_micro_code_mem>; 4163 }; 4164 4165 /* Speedbin needs more work on A740+, keep only lower freqs */ 4166 gpu_opp_table: opp-table { 4167 compatible = "operating-points-v2-adreno", 4168 "operating-points-v2"; 4169 4170 opp-231000000 { 4171 opp-hz = /bits/ 64 <231000000>; 4172 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 4173 opp-peak-kBps = <2136718>; 4174 qcom,opp-acd-level = <0xc82f5ffd>; 4175 }; 4176 4177 opp-310000000 { 4178 opp-hz = /bits/ 64 <310000000>; 4179 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4180 opp-peak-kBps = <2136718>; 4181 qcom,opp-acd-level = <0xc82c5ffd>; 4182 }; 4183 4184 opp-366000000 { 4185 opp-hz = /bits/ 64 <366000000>; 4186 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 4187 opp-peak-kBps = <6074218>; 4188 qcom,opp-acd-level = <0xc02e5ffd>; 4189 }; 4190 4191 opp-422000000 { 4192 opp-hz = /bits/ 64 <422000000>; 4193 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4194 opp-peak-kBps = <8171875>; 4195 qcom,opp-acd-level = <0xc02d5ffd>; 4196 }; 4197 4198 opp-500000000 { 4199 opp-hz = /bits/ 64 <500000000>; 4200 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4201 opp-peak-kBps = <8171875>; 4202 qcom,opp-acd-level = <0xc02a5ffd>; 4203 }; 4204 4205 opp-578000000 { 4206 opp-hz = /bits/ 64 <578000000>; 4207 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4208 opp-peak-kBps = <8171875>; 4209 qcom,opp-acd-level = <0x882c5ffd>; 4210 }; 4211 4212 opp-629000000 { 4213 opp-hz = /bits/ 64 <629000000>; 4214 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4215 opp-peak-kBps = <10687500>; 4216 qcom,opp-acd-level = <0x882a5ffd>; 4217 }; 4218 4219 opp-680000000 { 4220 opp-hz = /bits/ 64 <680000000>; 4221 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4222 opp-peak-kBps = <12449218>; 4223 qcom,opp-acd-level = <0x882a5ffd>; 4224 }; 4225 4226 opp-720000000 { 4227 opp-hz = /bits/ 64 <720000000>; 4228 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4229 opp-peak-kBps = <12449218>; 4230 qcom,opp-acd-level = <0x882a5ffd>; 4231 }; 4232 4233 opp-770000000 { 4234 opp-hz = /bits/ 64 <770000000>; 4235 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4236 opp-peak-kBps = <12449218>; 4237 qcom,opp-acd-level = <0x882a5ffd>; 4238 }; 4239 4240 opp-834000000 { 4241 opp-hz = /bits/ 64 <834000000>; 4242 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4243 opp-peak-kBps = <14398437>; 4244 qcom,opp-acd-level = <0x882a5ffd>; 4245 }; 4246 }; 4247 }; 4248 4249 gmu: gmu@3d6a000 { 4250 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; 4251 reg = <0x0 0x03d6a000 0x0 0x35000>, 4252 <0x0 0x03d50000 0x0 0x10000>, 4253 <0x0 0x0b280000 0x0 0x10000>; 4254 reg-names = "gmu", "rscc", "gmu_pdc"; 4255 4256 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>, 4257 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 4258 interrupt-names = "hfi", "gmu"; 4259 4260 clocks = <&gpucc GPU_CC_AHB_CLK>, 4261 <&gpucc GPU_CC_CX_GMU_CLK>, 4262 <&gpucc GPU_CC_CXO_CLK>, 4263 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4264 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4265 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4266 <&gpucc GPU_CC_DEMET_CLK>; 4267 clock-names = "ahb", 4268 "gmu", 4269 "cxo", 4270 "axi", 4271 "memnoc", 4272 "hub", 4273 "demet"; 4274 4275 power-domains = <&gpucc GPU_CX_GDSC>, 4276 <&gpucc GPU_GX_GDSC>; 4277 power-domain-names = "cx", 4278 "gx"; 4279 4280 iommus = <&adreno_smmu 5 0x0>; 4281 4282 qcom,qmp = <&aoss_qmp>; 4283 4284 operating-points-v2 = <&gmu_opp_table>; 4285 4286 gmu_opp_table: opp-table { 4287 compatible = "operating-points-v2"; 4288 4289 opp-260000000 { 4290 opp-hz = /bits/ 64 <260000000>; 4291 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4292 }; 4293 4294 opp-625000000 { 4295 opp-hz = /bits/ 64 <625000000>; 4296 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4297 }; 4298 }; 4299 }; 4300 4301 gpucc: clock-controller@3d90000 { 4302 compatible = "qcom,sm8650-gpucc"; 4303 reg = <0 0x03d90000 0 0xa000>; 4304 4305 clocks = <&bi_tcxo_div2>, 4306 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4307 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4308 4309 #clock-cells = <1>; 4310 #reset-cells = <1>; 4311 #power-domain-cells = <1>; 4312 }; 4313 4314 adreno_smmu: iommu@3da0000 { 4315 compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", 4316 "qcom,smmu-500", "arm,mmu-500"; 4317 reg = <0x0 0x03da0000 0x0 0x40000>; 4318 #iommu-cells = <2>; 4319 #global-interrupts = <1>; 4320 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>, 4321 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>, 4322 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>, 4323 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>, 4324 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>, 4325 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>, 4326 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>, 4327 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>, 4328 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>, 4329 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>, 4330 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>, 4331 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>, 4332 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>, 4333 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>, 4334 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>, 4335 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>, 4336 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>, 4337 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>, 4338 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>, 4339 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>, 4340 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, 4341 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>, 4342 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>, 4343 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>, 4344 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>, 4345 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>; 4346 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4347 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4348 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4349 <&gpucc GPU_CC_AHB_CLK>; 4350 clock-names = "hlos", 4351 "bus", 4352 "iface", 4353 "ahb"; 4354 power-domains = <&gpucc GPU_CX_GDSC>; 4355 dma-coherent; 4356 }; 4357 4358 ipa: ipa@3f40000 { 4359 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; 4360 4361 iommus = <&apps_smmu 0x4a0 0x0>, 4362 <&apps_smmu 0x4a2 0x0>; 4363 reg = <0 0x3f40000 0 0x10000>, 4364 <0 0x3f50000 0 0x5000>, 4365 <0 0x3e04000 0 0xfc000>; 4366 reg-names = "ipa-reg", 4367 "ipa-shared", 4368 "gsi"; 4369 4370 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>, 4371 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>, 4372 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4373 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 4374 interrupt-names = "ipa", 4375 "gsi", 4376 "ipa-clock-query", 4377 "ipa-setup-ready"; 4378 4379 clocks = <&rpmhcc RPMH_IPA_CLK>; 4380 clock-names = "core"; 4381 4382 interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS 4383 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4384 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4385 &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4386 interconnect-names = "memory", 4387 "config"; 4388 4389 qcom,qmp = <&aoss_qmp>; 4390 4391 qcom,smem-states = <&ipa_smp2p_out 0>, 4392 <&ipa_smp2p_out 1>; 4393 qcom,smem-state-names = "ipa-clock-enabled-valid", 4394 "ipa-clock-enabled"; 4395 4396 status = "disabled"; 4397 }; 4398 4399 remoteproc_mpss: remoteproc@4080000 { 4400 compatible = "qcom,sm8650-mpss-pas"; 4401 reg = <0x0 0x04080000 0x0 0x10000>; 4402 4403 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, 4404 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 4405 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 4406 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 4407 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 4408 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 4409 interrupt-names = "wdog", 4410 "fatal", 4411 "ready", 4412 "handover", 4413 "stop-ack", 4414 "shutdown-ack"; 4415 4416 clocks = <&rpmhcc RPMH_CXO_CLK>; 4417 clock-names = "xo"; 4418 4419 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 4420 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4421 4422 power-domains = <&rpmhpd RPMHPD_CX>, 4423 <&rpmhpd RPMHPD_MSS>; 4424 power-domain-names = "cx", 4425 "mss"; 4426 4427 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, 4428 <&mpss_dsm_mem>, <&mpss_dsm_mem_2>, 4429 <&qlink_logging_mem>; 4430 4431 qcom,qmp = <&aoss_qmp>; 4432 4433 qcom,smem-states = <&smp2p_modem_out 0>; 4434 qcom,smem-state-names = "stop"; 4435 4436 status = "disabled"; 4437 4438 glink-edge { 4439 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 4440 IPCC_MPROC_SIGNAL_GLINK_QMP 4441 IRQ_TYPE_EDGE_RISING>; 4442 4443 mboxes = <&ipcc IPCC_CLIENT_MPSS 4444 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4445 4446 qcom,remote-pid = <1>; 4447 4448 label = "mpss"; 4449 }; 4450 }; 4451 4452 remoteproc_adsp: remoteproc@6800000 { 4453 compatible = "qcom,sm8650-adsp-pas"; 4454 reg = <0x0 0x06800000 0x0 0x10000>; 4455 4456 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4457 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4458 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4459 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4460 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4461 interrupt-names = "wdog", 4462 "fatal", 4463 "ready", 4464 "handover", 4465 "stop-ack"; 4466 4467 clocks = <&rpmhcc RPMH_CXO_CLK>; 4468 clock-names = "xo"; 4469 4470 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 4471 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4472 4473 power-domains = <&rpmhpd RPMHPD_LCX>, 4474 <&rpmhpd RPMHPD_LMX>; 4475 power-domain-names = "lcx", 4476 "lmx"; 4477 4478 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 4479 4480 qcom,qmp = <&aoss_qmp>; 4481 4482 qcom,smem-states = <&smp2p_adsp_out 0>; 4483 qcom,smem-state-names = "stop"; 4484 4485 status = "disabled"; 4486 4487 remoteproc_adsp_glink: glink-edge { 4488 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4489 IPCC_MPROC_SIGNAL_GLINK_QMP 4490 IRQ_TYPE_EDGE_RISING>; 4491 4492 mboxes = <&ipcc IPCC_CLIENT_LPASS 4493 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4494 4495 qcom,remote-pid = <2>; 4496 4497 label = "lpass"; 4498 4499 fastrpc { 4500 compatible = "qcom,fastrpc"; 4501 4502 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4503 4504 label = "adsp"; 4505 4506 qcom,non-secure-domain; 4507 4508 #address-cells = <1>; 4509 #size-cells = <0>; 4510 4511 compute-cb@3 { 4512 compatible = "qcom,fastrpc-compute-cb"; 4513 reg = <3>; 4514 4515 iommus = <&apps_smmu 0x1003 0x80>, 4516 <&apps_smmu 0x1043 0x20>; 4517 dma-coherent; 4518 }; 4519 4520 compute-cb@4 { 4521 compatible = "qcom,fastrpc-compute-cb"; 4522 reg = <4>; 4523 4524 iommus = <&apps_smmu 0x1004 0x80>, 4525 <&apps_smmu 0x1044 0x20>; 4526 dma-coherent; 4527 }; 4528 4529 compute-cb@5 { 4530 compatible = "qcom,fastrpc-compute-cb"; 4531 reg = <5>; 4532 4533 iommus = <&apps_smmu 0x1005 0x80>, 4534 <&apps_smmu 0x1045 0x20>; 4535 dma-coherent; 4536 }; 4537 4538 compute-cb@6 { 4539 compatible = "qcom,fastrpc-compute-cb"; 4540 reg = <6>; 4541 4542 iommus = <&apps_smmu 0x1006 0x80>, 4543 <&apps_smmu 0x1046 0x20>; 4544 dma-coherent; 4545 }; 4546 4547 compute-cb@7 { 4548 compatible = "qcom,fastrpc-compute-cb"; 4549 reg = <7>; 4550 4551 iommus = <&apps_smmu 0x1007 0x40>, 4552 <&apps_smmu 0x1067 0x0>, 4553 <&apps_smmu 0x1087 0x0>; 4554 dma-coherent; 4555 }; 4556 }; 4557 4558 gpr { 4559 compatible = "qcom,gpr"; 4560 qcom,glink-channels = "adsp_apps"; 4561 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4562 qcom,intents = <512 20>; 4563 #address-cells = <1>; 4564 #size-cells = <0>; 4565 4566 q6apm: service@1 { 4567 compatible = "qcom,q6apm"; 4568 reg = <GPR_APM_MODULE_IID>; 4569 #sound-dai-cells = <0>; 4570 qcom,protection-domain = "avs/audio", 4571 "msm/adsp/audio_pd"; 4572 4573 q6apmbedai: bedais { 4574 compatible = "qcom,q6apm-lpass-dais"; 4575 #sound-dai-cells = <1>; 4576 }; 4577 4578 q6apmdai: dais { 4579 compatible = "qcom,q6apm-dais"; 4580 iommus = <&apps_smmu 0x1001 0x80>, 4581 <&apps_smmu 0x1061 0x0>; 4582 }; 4583 }; 4584 4585 q6prm: service@2 { 4586 compatible = "qcom,q6prm"; 4587 reg = <GPR_PRM_MODULE_IID>; 4588 qcom,protection-domain = "avs/audio", 4589 "msm/adsp/audio_pd"; 4590 4591 q6prmcc: clock-controller { 4592 compatible = "qcom,q6prm-lpass-clocks"; 4593 #clock-cells = <2>; 4594 }; 4595 }; 4596 }; 4597 }; 4598 }; 4599 4600 lpass_wsa2macro: codec@6aa0000 { 4601 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4602 reg = <0 0x06aa0000 0 0x1000>; 4603 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4604 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4605 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4606 <&lpass_vamacro>; 4607 clock-names = "mclk", 4608 "macro", 4609 "dcodec", 4610 "fsgen"; 4611 4612 #clock-cells = <0>; 4613 clock-output-names = "wsa2-mclk"; 4614 #sound-dai-cells = <1>; 4615 }; 4616 4617 swr3: soundwire@6ab0000 { 4618 compatible = "qcom,soundwire-v2.0.0"; 4619 reg = <0 0x06ab0000 0 0x10000>; 4620 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 4621 clocks = <&lpass_wsa2macro>; 4622 clock-names = "iface"; 4623 label = "WSA2"; 4624 4625 pinctrl-0 = <&wsa2_swr_active>; 4626 pinctrl-names = "default"; 4627 4628 qcom,din-ports = <4>; 4629 qcom,dout-ports = <9>; 4630 4631 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4632 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4633 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4634 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4635 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4636 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4637 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4638 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4639 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4640 4641 #address-cells = <2>; 4642 #size-cells = <0>; 4643 #sound-dai-cells = <1>; 4644 status = "disabled"; 4645 }; 4646 4647 lpass_rxmacro: codec@6ac0000 { 4648 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 4649 reg = <0 0x06ac0000 0 0x1000>; 4650 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4651 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4652 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4653 <&lpass_vamacro>; 4654 clock-names = "mclk", 4655 "macro", 4656 "dcodec", 4657 "fsgen"; 4658 4659 #clock-cells = <0>; 4660 clock-output-names = "mclk"; 4661 #sound-dai-cells = <1>; 4662 }; 4663 4664 swr1: soundwire@6ad0000 { 4665 compatible = "qcom,soundwire-v2.0.0"; 4666 reg = <0 0x06ad0000 0 0x10000>; 4667 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 4668 clocks = <&lpass_rxmacro>; 4669 clock-names = "iface"; 4670 label = "RX"; 4671 4672 pinctrl-0 = <&rx_swr_active>; 4673 pinctrl-names = "default"; 4674 4675 qcom,din-ports = <0>; 4676 qcom,dout-ports = <11>; 4677 4678 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>; 4679 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>; 4680 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 4681 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>; 4682 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>; 4683 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>; 4684 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>; 4685 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>; 4686 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; 4687 4688 #address-cells = <2>; 4689 #size-cells = <0>; 4690 #sound-dai-cells = <1>; 4691 status = "disabled"; 4692 }; 4693 4694 lpass_txmacro: codec@6ae0000 { 4695 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 4696 reg = <0 0x06ae0000 0 0x1000>; 4697 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4698 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4699 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4700 <&lpass_vamacro>; 4701 clock-names = "mclk", 4702 "macro", 4703 "dcodec", 4704 "fsgen"; 4705 4706 #clock-cells = <0>; 4707 clock-output-names = "mclk"; 4708 #sound-dai-cells = <1>; 4709 }; 4710 4711 lpass_wsamacro: codec@6b00000 { 4712 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4713 reg = <0 0x06b00000 0 0x1000>; 4714 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4715 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4716 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4717 <&lpass_vamacro>; 4718 clock-names = "mclk", 4719 "macro", 4720 "dcodec", 4721 "fsgen"; 4722 4723 #clock-cells = <0>; 4724 clock-output-names = "mclk"; 4725 #sound-dai-cells = <1>; 4726 }; 4727 4728 swr0: soundwire@6b10000 { 4729 compatible = "qcom,soundwire-v2.0.0"; 4730 reg = <0 0x06b10000 0 0x10000>; 4731 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 4732 clocks = <&lpass_wsamacro>; 4733 clock-names = "iface"; 4734 label = "WSA"; 4735 4736 pinctrl-0 = <&wsa_swr_active>; 4737 pinctrl-names = "default"; 4738 4739 qcom,din-ports = <4>; 4740 qcom,dout-ports = <9>; 4741 4742 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4743 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4744 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4745 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4746 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4747 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4748 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4749 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4750 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4751 4752 #address-cells = <2>; 4753 #size-cells = <0>; 4754 #sound-dai-cells = <1>; 4755 status = "disabled"; 4756 }; 4757 4758 swr2: soundwire@6d30000 { 4759 compatible = "qcom,soundwire-v2.0.0"; 4760 reg = <0 0x06d30000 0 0x10000>; 4761 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>, 4762 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>; 4763 interrupt-names = "core", "wakeup"; 4764 clocks = <&lpass_txmacro>; 4765 clock-names = "iface"; 4766 label = "TX"; 4767 4768 pinctrl-0 = <&tx_swr_active>; 4769 pinctrl-names = "default"; 4770 4771 qcom,din-ports = <4>; 4772 qcom,dout-ports = <0>; 4773 4774 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 4775 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 4776 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 4777 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 4778 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 4779 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 4780 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 4781 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 4782 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 4783 4784 #address-cells = <2>; 4785 #size-cells = <0>; 4786 #sound-dai-cells = <1>; 4787 status = "disabled"; 4788 }; 4789 4790 lpass_vamacro: codec@6d44000 { 4791 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 4792 reg = <0 0x06d44000 0 0x1000>; 4793 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4794 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4795 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4796 clock-names = "mclk", 4797 "macro", 4798 "dcodec"; 4799 4800 #clock-cells = <0>; 4801 clock-output-names = "fsgen"; 4802 #sound-dai-cells = <1>; 4803 }; 4804 4805 lpass_tlmm: pinctrl@6e80000 { 4806 compatible = "qcom,sm8650-lpass-lpi-pinctrl"; 4807 reg = <0 0x06e80000 0 0x20000>; 4808 4809 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4810 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4811 clock-names = "core", "audio"; 4812 4813 gpio-controller; 4814 #gpio-cells = <2>; 4815 gpio-ranges = <&lpass_tlmm 0 0 23>; 4816 4817 tx_swr_active: tx-swr-active-state { 4818 clk-pins { 4819 pins = "gpio0"; 4820 function = "swr_tx_clk"; 4821 drive-strength = <2>; 4822 slew-rate = <1>; 4823 bias-disable; 4824 }; 4825 4826 data-pins { 4827 pins = "gpio1", "gpio2", "gpio14"; 4828 function = "swr_tx_data"; 4829 drive-strength = <2>; 4830 slew-rate = <1>; 4831 bias-bus-hold; 4832 }; 4833 }; 4834 4835 rx_swr_active: rx-swr-active-state { 4836 clk-pins { 4837 pins = "gpio3"; 4838 function = "swr_rx_clk"; 4839 drive-strength = <2>; 4840 slew-rate = <1>; 4841 bias-disable; 4842 }; 4843 4844 data-pins { 4845 pins = "gpio4", "gpio5"; 4846 function = "swr_rx_data"; 4847 drive-strength = <2>; 4848 slew-rate = <1>; 4849 bias-bus-hold; 4850 }; 4851 }; 4852 4853 dmic01_default: dmic01-default-state { 4854 clk-pins { 4855 pins = "gpio6"; 4856 function = "dmic1_clk"; 4857 drive-strength = <8>; 4858 output-high; 4859 }; 4860 4861 data-pins { 4862 pins = "gpio7"; 4863 function = "dmic1_data"; 4864 drive-strength = <8>; 4865 input-enable; 4866 }; 4867 }; 4868 4869 dmic23_default: dmic23-default-state { 4870 clk-pins { 4871 pins = "gpio8"; 4872 function = "dmic2_clk"; 4873 drive-strength = <8>; 4874 output-high; 4875 }; 4876 4877 data-pins { 4878 pins = "gpio9"; 4879 function = "dmic2_data"; 4880 drive-strength = <8>; 4881 input-enable; 4882 }; 4883 }; 4884 4885 wsa_swr_active: wsa-swr-active-state { 4886 clk-pins { 4887 pins = "gpio10"; 4888 function = "wsa_swr_clk"; 4889 drive-strength = <2>; 4890 slew-rate = <1>; 4891 bias-disable; 4892 }; 4893 4894 data-pins { 4895 pins = "gpio11"; 4896 function = "wsa_swr_data"; 4897 drive-strength = <2>; 4898 slew-rate = <1>; 4899 bias-bus-hold; 4900 }; 4901 }; 4902 4903 wsa2_swr_active: wsa2-swr-active-state { 4904 clk-pins { 4905 pins = "gpio15"; 4906 function = "wsa2_swr_clk"; 4907 drive-strength = <2>; 4908 slew-rate = <1>; 4909 bias-disable; 4910 }; 4911 4912 data-pins { 4913 pins = "gpio16"; 4914 function = "wsa2_swr_data"; 4915 drive-strength = <2>; 4916 slew-rate = <1>; 4917 bias-bus-hold; 4918 }; 4919 }; 4920 }; 4921 4922 lpass_lpiaon_noc: interconnect@7400000 { 4923 compatible = "qcom,sm8650-lpass-lpiaon-noc"; 4924 reg = <0 0x07400000 0 0x19080>; 4925 4926 #interconnect-cells = <2>; 4927 4928 qcom,bcm-voters = <&apps_bcm_voter>; 4929 }; 4930 4931 lpass_lpicx_noc: interconnect@7430000 { 4932 compatible = "qcom,sm8650-lpass-lpicx-noc"; 4933 reg = <0 0x07430000 0 0x3a200>; 4934 4935 #interconnect-cells = <2>; 4936 4937 qcom,bcm-voters = <&apps_bcm_voter>; 4938 }; 4939 4940 lpass_ag_noc: interconnect@7e40000 { 4941 compatible = "qcom,sm8650-lpass-ag-noc"; 4942 reg = <0 0x07e40000 0 0xe080>; 4943 4944 #interconnect-cells = <2>; 4945 4946 qcom,bcm-voters = <&apps_bcm_voter>; 4947 }; 4948 4949 sdhc_2: mmc@8804000 { 4950 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; 4951 reg = <0 0x08804000 0 0x1000>; 4952 4953 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>, 4954 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH 0>; 4955 interrupt-names = "hc_irq", 4956 "pwr_irq"; 4957 4958 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4959 <&gcc GCC_SDCC2_APPS_CLK>, 4960 <&rpmhcc RPMH_CXO_CLK>; 4961 clock-names = "iface", 4962 "core", 4963 "xo"; 4964 4965 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 4966 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4967 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4968 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4969 interconnect-names = "sdhc-ddr", 4970 "cpu-sdhc"; 4971 4972 power-domains = <&rpmhpd RPMHPD_CX>; 4973 operating-points-v2 = <&sdhc2_opp_table>; 4974 4975 iommus = <&apps_smmu 0x540 0>; 4976 4977 bus-width = <4>; 4978 4979 /* Forbid SDR104/SDR50 - broken hw! */ 4980 sdhci-caps-mask = <0x3 0>; 4981 4982 qcom,dll-config = <0x0007642c>; 4983 qcom,ddr-config = <0x80040868>; 4984 4985 dma-coherent; 4986 4987 status = "disabled"; 4988 4989 sdhc2_opp_table: opp-table { 4990 compatible = "operating-points-v2"; 4991 4992 opp-19200000 { 4993 opp-hz = /bits/ 64 <19200000>; 4994 required-opps = <&rpmhpd_opp_min_svs>; 4995 }; 4996 4997 opp-50000000 { 4998 opp-hz = /bits/ 64 <50000000>; 4999 required-opps = <&rpmhpd_opp_low_svs>; 5000 }; 5001 5002 opp-100000000 { 5003 opp-hz = /bits/ 64 <100000000>; 5004 required-opps = <&rpmhpd_opp_svs>; 5005 }; 5006 5007 opp-202000000 { 5008 opp-hz = /bits/ 64 <202000000>; 5009 required-opps = <&rpmhpd_opp_svs_l1>; 5010 }; 5011 }; 5012 }; 5013 5014 usb_1_hsphy: phy@88e3000 { 5015 compatible = "qcom,sm8650-snps-eusb2-phy", 5016 "qcom,sm8550-snps-eusb2-phy"; 5017 reg = <0 0x088e3000 0 0x154>; 5018 5019 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 5020 clock-names = "ref"; 5021 5022 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 5023 5024 #phy-cells = <0>; 5025 5026 status = "disabled"; 5027 }; 5028 5029 usb_dp_qmpphy: phy@88e8000 { 5030 compatible = "qcom,sm8650-qmp-usb3-dp-phy"; 5031 reg = <0 0x088e8000 0 0x3000>; 5032 5033 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 5034 <&rpmhcc RPMH_CXO_CLK>, 5035 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 5036 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 5037 clock-names = "aux", 5038 "ref", 5039 "com_aux", 5040 "usb3_pipe"; 5041 5042 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 5043 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 5044 reset-names = "phy", 5045 "common"; 5046 5047 power-domains = <&gcc USB3_PHY_GDSC>; 5048 5049 #clock-cells = <1>; 5050 #phy-cells = <1>; 5051 5052 mode-switch; 5053 orientation-switch; 5054 5055 status = "disabled"; 5056 5057 ports { 5058 #address-cells = <1>; 5059 #size-cells = <0>; 5060 5061 port@0 { 5062 reg = <0>; 5063 5064 usb_dp_qmpphy_out: endpoint { 5065 }; 5066 }; 5067 5068 port@1 { 5069 reg = <1>; 5070 5071 usb_dp_qmpphy_usb_ss_in: endpoint { 5072 remote-endpoint = <&usb_1_dwc3_ss>; 5073 }; 5074 }; 5075 5076 port@2 { 5077 reg = <2>; 5078 5079 usb_dp_qmpphy_dp_in: endpoint { 5080 remote-endpoint = <&mdss_dp0_out>; 5081 }; 5082 }; 5083 }; 5084 }; 5085 5086 usb_1: usb@a600000 { 5087 compatible = "qcom,sm8650-dwc3", "qcom,snps-dwc3"; 5088 reg = <0 0x0a600000 0 0xfc100>; 5089 5090 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, 5091 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, 5092 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, 5093 <&pdc 14 IRQ_TYPE_EDGE_RISING>, 5094 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 5095 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 5096 interrupt-names = "dwc_usb3", 5097 "pwr_event", 5098 "hs_phy_irq", 5099 "dp_hs_phy_irq", 5100 "dm_hs_phy_irq", 5101 "ss_phy_irq"; 5102 5103 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5104 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5105 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5106 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5107 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5108 <&tcsr TCSR_USB3_CLKREF_EN>; 5109 clock-names = "cfg_noc", 5110 "core", 5111 "iface", 5112 "sleep", 5113 "mock_utmi", 5114 "xo"; 5115 5116 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5117 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5118 assigned-clock-rates = <19200000>, <200000000>; 5119 5120 resets = <&gcc GCC_USB30_PRIM_BCR>; 5121 5122 phys = <&usb_1_hsphy>, 5123 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 5124 phy-names = "usb2-phy", 5125 "usb3-phy"; 5126 5127 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 5128 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5129 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5130 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 5131 interconnect-names = "usb-ddr", 5132 "apps-usb"; 5133 5134 iommus = <&apps_smmu 0x40 0>; 5135 5136 power-domains = <&gcc USB30_PRIM_GDSC>; 5137 required-opps = <&rpmhpd_opp_nom>; 5138 5139 snps,hird-threshold = /bits/ 8 <0x0>; 5140 snps,usb2-gadget-lpm-disable; 5141 snps,dis_u2_susphy_quirk; 5142 snps,dis_enblslpm_quirk; 5143 snps,dis-u1-entry-quirk; 5144 snps,dis-u2-entry-quirk; 5145 snps,is-utmi-l1-suspend; 5146 snps,usb3_lpm_capable; 5147 snps,usb2-lpm-disable; 5148 snps,has-lpm-erratum; 5149 tx-fifo-resize; 5150 5151 dma-coherent; 5152 5153 status = "disabled"; 5154 5155 ports { 5156 #address-cells = <1>; 5157 #size-cells = <0>; 5158 5159 port@0 { 5160 reg = <0>; 5161 5162 usb_1_dwc3_hs: endpoint { 5163 }; 5164 }; 5165 5166 port@1 { 5167 reg = <1>; 5168 5169 usb_1_dwc3_ss: endpoint { 5170 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 5171 }; 5172 }; 5173 }; 5174 }; 5175 5176 iris: video-codec@aa00000 { 5177 compatible = "qcom,sm8650-iris"; 5178 reg = <0 0x0aa00000 0 0xf0000>; 5179 5180 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; 5181 5182 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 5183 <&videocc VIDEO_CC_MVS0_GDSC>, 5184 <&rpmhpd RPMHPD_MXC>, 5185 <&rpmhpd RPMHPD_MMCX>; 5186 power-domain-names = "venus", 5187 "vcodec0", 5188 "mxc", 5189 "mmcx"; 5190 5191 operating-points-v2 = <&iris_opp_table>; 5192 5193 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 5194 <&videocc VIDEO_CC_MVS0C_CLK>, 5195 <&videocc VIDEO_CC_MVS0_CLK>; 5196 clock-names = "iface", 5197 "core", 5198 "vcodec0_core"; 5199 5200 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5201 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5202 <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS 5203 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5204 interconnect-names = "cpu-cfg", 5205 "video-mem"; 5206 5207 memory-region = <&video_mem>; 5208 5209 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 5210 <&videocc VIDEO_CC_XO_CLK_ARES>, 5211 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 5212 reset-names = "bus", 5213 "xo", 5214 "core"; 5215 5216 iommus = <&apps_smmu 0x1940 0>, 5217 <&apps_smmu 0x1947 0>; 5218 5219 dma-coherent; 5220 5221 /* 5222 * IRIS firmware is signed by vendors, only 5223 * enable on boards where the proper signed firmware 5224 * is available. 5225 */ 5226 status = "disabled"; 5227 5228 iris_opp_table: opp-table { 5229 compatible = "operating-points-v2"; 5230 5231 opp-196000000 { 5232 opp-hz = /bits/ 64 <196000000>; 5233 required-opps = <&rpmhpd_opp_low_svs_d1>, 5234 <&rpmhpd_opp_low_svs_d1>; 5235 }; 5236 5237 opp-300000000 { 5238 opp-hz = /bits/ 64 <300000000>; 5239 required-opps = <&rpmhpd_opp_low_svs>, 5240 <&rpmhpd_opp_low_svs>; 5241 }; 5242 5243 opp-380000000 { 5244 opp-hz = /bits/ 64 <380000000>; 5245 required-opps = <&rpmhpd_opp_svs>, 5246 <&rpmhpd_opp_svs>; 5247 }; 5248 5249 opp-435000000 { 5250 opp-hz = /bits/ 64 <435000000>; 5251 required-opps = <&rpmhpd_opp_svs_l1>, 5252 <&rpmhpd_opp_svs_l1>; 5253 }; 5254 5255 opp-480000000 { 5256 opp-hz = /bits/ 64 <480000000>; 5257 required-opps = <&rpmhpd_opp_nom>, 5258 <&rpmhpd_opp_nom>; 5259 }; 5260 5261 opp-533333334 { 5262 opp-hz = /bits/ 64 <533333334>; 5263 required-opps = <&rpmhpd_opp_turbo>, 5264 <&rpmhpd_opp_turbo>; 5265 }; 5266 }; 5267 }; 5268 5269 videocc: clock-controller@aaf0000 { 5270 compatible = "qcom,sm8650-videocc"; 5271 reg = <0 0x0aaf0000 0 0x10000>; 5272 clocks = <&bi_tcxo_div2>, 5273 <&gcc GCC_VIDEO_AHB_CLK>; 5274 power-domains = <&rpmhpd RPMHPD_MMCX>, 5275 <&rpmhpd RPMHPD_MXC>; 5276 #clock-cells = <1>; 5277 #reset-cells = <1>; 5278 #power-domain-cells = <1>; 5279 }; 5280 5281 cci0: cci@ac15000 { 5282 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 5283 reg = <0 0x0ac15000 0 0x1000>; 5284 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>; 5285 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5286 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 5287 <&camcc CAM_CC_CPAS_AHB_CLK>, 5288 <&camcc CAM_CC_CCI_0_CLK>; 5289 clock-names = "camnoc_axi", 5290 "cpas_ahb", 5291 "cci"; 5292 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 5293 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 5294 pinctrl-names = "default", "sleep"; 5295 status = "disabled"; 5296 #address-cells = <1>; 5297 #size-cells = <0>; 5298 5299 cci0_i2c0: i2c-bus@0 { 5300 reg = <0>; 5301 clock-frequency = <1000000>; 5302 #address-cells = <1>; 5303 #size-cells = <0>; 5304 }; 5305 5306 cci0_i2c1: i2c-bus@1 { 5307 reg = <1>; 5308 clock-frequency = <1000000>; 5309 #address-cells = <1>; 5310 #size-cells = <0>; 5311 }; 5312 }; 5313 5314 cci1: cci@ac16000 { 5315 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 5316 reg = <0 0x0ac16000 0 0x1000>; 5317 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING 0>; 5318 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5319 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 5320 <&camcc CAM_CC_CPAS_AHB_CLK>, 5321 <&camcc CAM_CC_CCI_1_CLK>; 5322 clock-names = "camnoc_axi", 5323 "cpas_ahb", 5324 "cci"; 5325 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 5326 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 5327 pinctrl-names = "default", "sleep"; 5328 status = "disabled"; 5329 #address-cells = <1>; 5330 #size-cells = <0>; 5331 5332 cci1_i2c0: i2c-bus@0 { 5333 reg = <0>; 5334 clock-frequency = <1000000>; 5335 #address-cells = <1>; 5336 #size-cells = <0>; 5337 }; 5338 5339 cci1_i2c1: i2c-bus@1 { 5340 reg = <1>; 5341 clock-frequency = <1000000>; 5342 #address-cells = <1>; 5343 #size-cells = <0>; 5344 }; 5345 }; 5346 5347 cci2: cci@ac17000 { 5348 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 5349 reg = <0 0x0ac17000 0 0x1000>; 5350 interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING 0>; 5351 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5352 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 5353 <&camcc CAM_CC_CPAS_AHB_CLK>, 5354 <&camcc CAM_CC_CCI_2_CLK>; 5355 clock-names = "camnoc_axi", 5356 "cpas_ahb", 5357 "cci"; 5358 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 5359 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 5360 pinctrl-names = "default", "sleep"; 5361 status = "disabled"; 5362 #address-cells = <1>; 5363 #size-cells = <0>; 5364 5365 cci2_i2c0: i2c-bus@0 { 5366 reg = <0>; 5367 clock-frequency = <1000000>; 5368 #address-cells = <1>; 5369 #size-cells = <0>; 5370 }; 5371 5372 cci2_i2c1: i2c-bus@1 { 5373 reg = <1>; 5374 clock-frequency = <1000000>; 5375 #address-cells = <1>; 5376 #size-cells = <0>; 5377 }; 5378 }; 5379 5380 camcc: clock-controller@ade0000 { 5381 compatible = "qcom,sm8650-camcc"; 5382 reg = <0 0x0ade0000 0 0x20000>; 5383 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 5384 <&bi_tcxo_div2>, 5385 <&bi_tcxo_ao_div2>, 5386 <&sleep_clk>; 5387 power-domains = <&rpmhpd RPMHPD_MMCX>, 5388 <&rpmhpd RPMHPD_MXC>; 5389 #clock-cells = <1>; 5390 #reset-cells = <1>; 5391 #power-domain-cells = <1>; 5392 }; 5393 5394 mdss: display-subsystem@ae00000 { 5395 compatible = "qcom,sm8650-mdss"; 5396 reg = <0 0x0ae00000 0 0x1000>; 5397 reg-names = "mdss"; 5398 5399 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>; 5400 5401 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5402 <&gcc GCC_DISP_HF_AXI_CLK>, 5403 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5404 5405 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5406 5407 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 5408 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5409 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5410 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5411 interconnect-names = "mdp0-mem", 5412 "cpu-cfg"; 5413 5414 power-domains = <&dispcc MDSS_GDSC>; 5415 5416 iommus = <&apps_smmu 0x1c00 0x2>; 5417 5418 interrupt-controller; 5419 #interrupt-cells = <1>; 5420 5421 #address-cells = <2>; 5422 #size-cells = <2>; 5423 ranges; 5424 5425 status = "disabled"; 5426 5427 mdss_mdp: display-controller@ae01000 { 5428 compatible = "qcom,sm8650-dpu"; 5429 reg = <0 0x0ae01000 0 0x8f000>, 5430 <0 0x0aeb0000 0 0x3000>; 5431 reg-names = "mdp", 5432 "vbif"; 5433 5434 interrupts-extended = <&mdss 0>; 5435 5436 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5437 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5438 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5439 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5440 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5441 clock-names = "nrt_bus", 5442 "iface", 5443 "lut", 5444 "core", 5445 "vsync"; 5446 5447 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5448 assigned-clock-rates = <19200000>; 5449 5450 operating-points-v2 = <&mdp_opp_table>; 5451 5452 power-domains = <&rpmhpd RPMHPD_MMCX>; 5453 5454 ports { 5455 #address-cells = <1>; 5456 #size-cells = <0>; 5457 5458 port@0 { 5459 reg = <0>; 5460 5461 dpu_intf1_out: endpoint { 5462 remote-endpoint = <&mdss_dsi0_in>; 5463 }; 5464 }; 5465 5466 port@1 { 5467 reg = <1>; 5468 5469 dpu_intf2_out: endpoint { 5470 remote-endpoint = <&mdss_dsi1_in>; 5471 }; 5472 }; 5473 5474 port@2 { 5475 reg = <2>; 5476 5477 dpu_intf0_out: endpoint { 5478 remote-endpoint = <&mdss_dp0_in>; 5479 }; 5480 }; 5481 }; 5482 5483 mdp_opp_table: opp-table { 5484 compatible = "operating-points-v2"; 5485 5486 opp-200000000 { 5487 opp-hz = /bits/ 64 <200000000>; 5488 required-opps = <&rpmhpd_opp_low_svs>; 5489 }; 5490 5491 opp-325000000 { 5492 opp-hz = /bits/ 64 <325000000>; 5493 required-opps = <&rpmhpd_opp_svs>; 5494 }; 5495 5496 opp-375000000 { 5497 opp-hz = /bits/ 64 <375000000>; 5498 required-opps = <&rpmhpd_opp_svs_l1>; 5499 }; 5500 5501 opp-514000000 { 5502 opp-hz = /bits/ 64 <514000000>; 5503 required-opps = <&rpmhpd_opp_nom>; 5504 }; 5505 }; 5506 }; 5507 5508 mdss_dsi0: dsi@ae94000 { 5509 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5510 reg = <0 0x0ae94000 0 0x400>; 5511 reg-names = "dsi_ctrl"; 5512 5513 interrupts-extended = <&mdss 4>; 5514 5515 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 5516 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 5517 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 5518 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 5519 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5520 <&gcc GCC_DISP_HF_AXI_CLK>; 5521 clock-names = "byte", 5522 "byte_intf", 5523 "pixel", 5524 "core", 5525 "iface", 5526 "bus"; 5527 5528 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 5529 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 5530 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5531 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 5532 5533 operating-points-v2 = <&mdss_dsi_opp_table>; 5534 5535 power-domains = <&rpmhpd RPMHPD_MMCX>; 5536 5537 phys = <&mdss_dsi0_phy>; 5538 phy-names = "dsi"; 5539 5540 #address-cells = <1>; 5541 #size-cells = <0>; 5542 5543 status = "disabled"; 5544 5545 ports { 5546 #address-cells = <1>; 5547 #size-cells = <0>; 5548 5549 port@0 { 5550 reg = <0>; 5551 5552 mdss_dsi0_in: endpoint { 5553 remote-endpoint = <&dpu_intf1_out>; 5554 }; 5555 }; 5556 5557 port@1 { 5558 reg = <1>; 5559 5560 mdss_dsi0_out: endpoint { 5561 }; 5562 }; 5563 }; 5564 5565 mdss_dsi_opp_table: opp-table { 5566 compatible = "operating-points-v2"; 5567 5568 opp-187500000 { 5569 opp-hz = /bits/ 64 <187500000>; 5570 required-opps = <&rpmhpd_opp_low_svs>; 5571 }; 5572 5573 opp-300000000 { 5574 opp-hz = /bits/ 64 <300000000>; 5575 required-opps = <&rpmhpd_opp_svs>; 5576 }; 5577 5578 opp-358000000 { 5579 opp-hz = /bits/ 64 <358000000>; 5580 required-opps = <&rpmhpd_opp_svs_l1>; 5581 }; 5582 }; 5583 }; 5584 5585 mdss_dsi0_phy: phy@ae95000 { 5586 compatible = "qcom,sm8650-dsi-phy-4nm"; 5587 reg = <0 0x0ae95000 0 0x200>, 5588 <0 0x0ae95200 0 0x280>, 5589 <0 0x0ae95500 0 0x400>; 5590 reg-names = "dsi_phy", 5591 "dsi_phy_lane", 5592 "dsi_pll"; 5593 5594 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5595 <&rpmhcc RPMH_CXO_CLK>; 5596 clock-names = "iface", 5597 "ref"; 5598 5599 #clock-cells = <1>; 5600 #phy-cells = <0>; 5601 5602 status = "disabled"; 5603 }; 5604 5605 mdss_dsi1: dsi@ae96000 { 5606 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5607 reg = <0 0x0ae96000 0 0x400>; 5608 reg-names = "dsi_ctrl"; 5609 5610 interrupts-extended = <&mdss 5>; 5611 5612 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 5613 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 5614 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 5615 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 5616 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5617 <&gcc GCC_DISP_HF_AXI_CLK>; 5618 clock-names = "byte", 5619 "byte_intf", 5620 "pixel", 5621 "core", 5622 "iface", 5623 "bus"; 5624 5625 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 5626 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 5627 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 5628 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 5629 5630 operating-points-v2 = <&mdss_dsi_opp_table>; 5631 5632 power-domains = <&rpmhpd RPMHPD_MMCX>; 5633 5634 phys = <&mdss_dsi1_phy>; 5635 phy-names = "dsi"; 5636 5637 #address-cells = <1>; 5638 #size-cells = <0>; 5639 5640 status = "disabled"; 5641 5642 ports { 5643 #address-cells = <1>; 5644 #size-cells = <0>; 5645 5646 port@0 { 5647 reg = <0>; 5648 5649 mdss_dsi1_in: endpoint { 5650 remote-endpoint = <&dpu_intf2_out>; 5651 }; 5652 }; 5653 5654 port@1 { 5655 reg = <1>; 5656 5657 mdss_dsi1_out: endpoint { 5658 }; 5659 }; 5660 }; 5661 }; 5662 5663 mdss_dsi1_phy: phy@ae97000 { 5664 compatible = "qcom,sm8650-dsi-phy-4nm"; 5665 reg = <0 0x0ae97000 0 0x200>, 5666 <0 0x0ae97200 0 0x280>, 5667 <0 0x0ae97500 0 0x400>; 5668 reg-names = "dsi_phy", 5669 "dsi_phy_lane", 5670 "dsi_pll"; 5671 5672 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5673 <&rpmhcc RPMH_CXO_CLK>; 5674 clock-names = "iface", 5675 "ref"; 5676 5677 #clock-cells = <1>; 5678 #phy-cells = <0>; 5679 5680 status = "disabled"; 5681 }; 5682 5683 mdss_dp0: displayport-controller@af54000 { 5684 compatible = "qcom,sm8650-dp"; 5685 reg = <0 0xaf54000 0 0x104>, 5686 <0 0xaf54200 0 0xc0>, 5687 <0 0xaf55000 0 0x770>, 5688 <0 0xaf56000 0 0x9c>, 5689 <0 0xaf57000 0 0x9c>; 5690 5691 interrupts-extended = <&mdss 12>; 5692 5693 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5694 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 5695 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 5696 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5697 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5698 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 5699 clock-names = "core_iface", 5700 "core_aux", 5701 "ctrl_link", 5702 "ctrl_link_iface", 5703 "stream_pixel", 5704 "stream_1_pixel"; 5705 5706 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5707 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5708 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 5709 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5710 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5711 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5712 5713 operating-points-v2 = <&dp_opp_table>; 5714 5715 power-domains = <&rpmhpd RPMHPD_MMCX>; 5716 5717 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 5718 phy-names = "dp"; 5719 5720 #sound-dai-cells = <0>; 5721 5722 status = "disabled"; 5723 5724 dp_opp_table: opp-table { 5725 compatible = "operating-points-v2"; 5726 5727 opp-162000000 { 5728 opp-hz = /bits/ 64 <162000000>; 5729 required-opps = <&rpmhpd_opp_low_svs_d1>; 5730 }; 5731 5732 opp-270000000 { 5733 opp-hz = /bits/ 64 <270000000>; 5734 required-opps = <&rpmhpd_opp_low_svs>; 5735 }; 5736 5737 opp-540000000 { 5738 opp-hz = /bits/ 64 <540000000>; 5739 required-opps = <&rpmhpd_opp_svs_l1>; 5740 }; 5741 5742 opp-810000000 { 5743 opp-hz = /bits/ 64 <810000000>; 5744 required-opps = <&rpmhpd_opp_nom>; 5745 }; 5746 }; 5747 5748 ports { 5749 #address-cells = <1>; 5750 #size-cells = <0>; 5751 5752 port@0 { 5753 reg = <0>; 5754 5755 mdss_dp0_in: endpoint { 5756 remote-endpoint = <&dpu_intf0_out>; 5757 }; 5758 }; 5759 5760 port@1 { 5761 reg = <1>; 5762 5763 mdss_dp0_out: endpoint { 5764 data-lanes = <0 1 2 3>; 5765 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 5766 }; 5767 }; 5768 }; 5769 }; 5770 }; 5771 5772 dispcc: clock-controller@af00000 { 5773 compatible = "qcom,sm8650-dispcc"; 5774 reg = <0 0x0af00000 0 0x20000>; 5775 5776 clocks = <&bi_tcxo_div2>, 5777 <&bi_tcxo_ao_div2>, 5778 <&gcc GCC_DISP_AHB_CLK>, 5779 <&sleep_clk>, 5780 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5781 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 5782 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 5783 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 5784 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5785 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5786 <0>, /* dp1 */ 5787 <0>, 5788 <0>, /* dp2 */ 5789 <0>, 5790 <0>, /* dp3 */ 5791 <0>; 5792 5793 power-domains = <&rpmhpd RPMHPD_MMCX>; 5794 required-opps = <&rpmhpd_opp_low_svs>; 5795 5796 #clock-cells = <1>; 5797 #reset-cells = <1>; 5798 #power-domain-cells = <1>; 5799 }; 5800 5801 pdc: interrupt-controller@b220000 { 5802 compatible = "qcom,sm8650-pdc", "qcom,pdc"; 5803 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 5804 5805 interrupt-parent = <&intc>; 5806 5807 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 5808 <125 63 1>, <126 716 12>, 5809 <138 251 5>, <143 244 4>; 5810 5811 #interrupt-cells = <2>; 5812 interrupt-controller; 5813 }; 5814 5815 tsens0: thermal-sensor@c228000 { 5816 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 5817 reg = <0 0x0c228000 0 0x1000>, /* TM */ 5818 <0 0x0c222000 0 0x1000>; /* SROT */ 5819 5820 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>, 5821 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 5822 interrupt-names = "uplow", 5823 "critical"; 5824 5825 #qcom,sensors = <15>; 5826 5827 #thermal-sensor-cells = <1>; 5828 }; 5829 5830 tsens1: thermal-sensor@c229000 { 5831 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 5832 reg = <0 0x0c229000 0 0x1000>, /* TM */ 5833 <0 0x0c223000 0 0x1000>; /* SROT */ 5834 5835 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>, 5836 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 5837 interrupt-names = "uplow", 5838 "critical"; 5839 5840 #qcom,sensors = <16>; 5841 5842 #thermal-sensor-cells = <1>; 5843 }; 5844 5845 tsens2: thermal-sensor@c22a000 { 5846 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 5847 reg = <0 0x0c22a000 0 0x1000>, /* TM */ 5848 <0 0x0c224000 0 0x1000>; /* SROT */ 5849 5850 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>, 5851 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 5852 interrupt-names = "uplow", 5853 "critical"; 5854 5855 #qcom,sensors = <13>; 5856 5857 #thermal-sensor-cells = <1>; 5858 }; 5859 5860 aoss_qmp: power-management@c300000 { 5861 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; 5862 reg = <0 0x0c300000 0 0x400>; 5863 5864 interrupt-parent = <&ipcc>; 5865 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 5866 IRQ_TYPE_EDGE_RISING>; 5867 5868 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5869 5870 #clock-cells = <0>; 5871 }; 5872 5873 sram@c3f0000 { 5874 compatible = "qcom,rpmh-stats"; 5875 reg = <0 0x0c3f0000 0 0x400>; 5876 qcom,qmp = <&aoss_qmp>; 5877 }; 5878 5879 spmi_bus: spmi@c400000 { 5880 compatible = "qcom,spmi-pmic-arb"; 5881 reg = <0 0x0c400000 0 0x3000>, 5882 <0 0x0c500000 0 0x400000>, 5883 <0 0x0c440000 0 0x80000>, 5884 <0 0x0c4c0000 0 0x20000>, 5885 <0 0x0c42d000 0 0x4000>; 5886 reg-names = "core", 5887 "chnls", 5888 "obsrvr", 5889 "intr", 5890 "cnfg"; 5891 5892 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5893 interrupt-names = "periph_irq"; 5894 5895 qcom,ee = <0>; 5896 qcom,channel = <0>; 5897 qcom,bus-id = <0>; 5898 5899 interrupt-controller; 5900 #interrupt-cells = <4>; 5901 5902 #address-cells = <2>; 5903 #size-cells = <0>; 5904 }; 5905 5906 tlmm: pinctrl@f100000 { 5907 compatible = "qcom,sm8650-tlmm"; 5908 reg = <0 0x0f100000 0 0x300000>; 5909 5910 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; 5911 5912 gpio-controller; 5913 #gpio-cells = <2>; 5914 5915 interrupt-controller; 5916 #interrupt-cells = <2>; 5917 5918 gpio-ranges = <&tlmm 0 0 211>; 5919 5920 wakeup-parent = <&pdc>; 5921 5922 cci0_0_default: cci0-0-default-state { 5923 sda-pins { 5924 pins = "gpio113"; 5925 function = "cci_i2c_sda"; 5926 drive-strength = <2>; 5927 bias-pull-up = <2200>; 5928 }; 5929 5930 scl-pins { 5931 pins = "gpio114"; 5932 function = "cci_i2c_scl"; 5933 drive-strength = <2>; 5934 bias-pull-up = <2200>; 5935 }; 5936 }; 5937 5938 cci0_0_sleep: cci0-0-sleep-state { 5939 sda-pins { 5940 pins = "gpio113"; 5941 function = "cci_i2c_sda"; 5942 drive-strength = <2>; 5943 bias-pull-down; 5944 }; 5945 5946 scl-pins { 5947 pins = "gpio114"; 5948 function = "cci_i2c_scl"; 5949 drive-strength = <2>; 5950 bias-pull-down; 5951 }; 5952 }; 5953 5954 cci0_1_default: cci0-1-default-state { 5955 sda-pins { 5956 pins = "gpio115"; 5957 function = "cci_i2c_sda"; 5958 drive-strength = <2>; 5959 bias-pull-up = <2200>; 5960 }; 5961 5962 scl-pins { 5963 pins = "gpio116"; 5964 function = "cci_i2c_scl"; 5965 drive-strength = <2>; 5966 bias-pull-up = <2200>; 5967 }; 5968 }; 5969 5970 cci0_1_sleep: cci0-1-sleep-state { 5971 sda-pins { 5972 pins = "gpio115"; 5973 function = "cci_i2c_sda"; 5974 drive-strength = <2>; 5975 bias-pull-down; 5976 }; 5977 5978 scl-pins { 5979 pins = "gpio116"; 5980 function = "cci_i2c_scl"; 5981 drive-strength = <2>; 5982 bias-pull-down; 5983 }; 5984 }; 5985 5986 cci1_0_default: cci1-0-default-state { 5987 sda-pins { 5988 pins = "gpio117"; 5989 function = "cci_i2c_sda"; 5990 drive-strength = <2>; 5991 bias-pull-up = <2200>; 5992 }; 5993 5994 scl-pins { 5995 pins = "gpio118"; 5996 function = "cci_i2c_scl"; 5997 drive-strength = <2>; 5998 bias-pull-up = <2200>; 5999 }; 6000 }; 6001 6002 cci1_0_sleep: cci1-0-sleep-state { 6003 sda-pins { 6004 pins = "gpio117"; 6005 function = "cci_i2c_sda"; 6006 drive-strength = <2>; 6007 bias-pull-down; 6008 }; 6009 6010 scl-pins { 6011 pins = "gpio118"; 6012 function = "cci_i2c_scl"; 6013 drive-strength = <2>; 6014 bias-pull-down; 6015 }; 6016 }; 6017 6018 cci1_1_default: cci1-1-default-state { 6019 sda-pins { 6020 pins = "gpio12"; 6021 function = "cci_i2c_sda"; 6022 drive-strength = <2>; 6023 bias-pull-up = <2200>; 6024 }; 6025 6026 scl-pins { 6027 pins = "gpio13"; 6028 function = "cci_i2c_scl"; 6029 drive-strength = <2>; 6030 bias-pull-up = <2200>; 6031 }; 6032 }; 6033 6034 cci1_1_sleep: cci1-1-sleep-state { 6035 sda-pins { 6036 pins = "gpio12"; 6037 function = "cci_i2c_sda"; 6038 drive-strength = <2>; 6039 bias-pull-down; 6040 }; 6041 6042 scl-pins { 6043 pins = "gpio13"; 6044 function = "cci_i2c_scl"; 6045 drive-strength = <2>; 6046 bias-pull-down; 6047 }; 6048 }; 6049 6050 cci2_0_default: cci2-0-default-state { 6051 sda-pins { 6052 pins = "gpio112"; 6053 function = "cci_i2c_sda"; 6054 drive-strength = <2>; 6055 bias-pull-up = <2200>; 6056 }; 6057 6058 scl-pins { 6059 pins = "gpio153"; 6060 function = "cci_i2c_scl"; 6061 drive-strength = <2>; 6062 bias-pull-up = <2200>; 6063 }; 6064 }; 6065 6066 cci2_0_sleep: cci2-0-sleep-state { 6067 sda-pins { 6068 pins = "gpio112"; 6069 function = "cci_i2c_sda"; 6070 drive-strength = <2>; 6071 bias-pull-down; 6072 }; 6073 6074 scl-pins { 6075 pins = "gpio153"; 6076 function = "cci_i2c_scl"; 6077 drive-strength = <2>; 6078 bias-pull-down; 6079 }; 6080 }; 6081 6082 cci2_1_default: cci2-1-default-state { 6083 sda-pins { 6084 pins = "gpio119"; 6085 function = "cci_i2c_sda"; 6086 drive-strength = <2>; 6087 bias-pull-up = <2200>; 6088 }; 6089 6090 scl-pins { 6091 pins = "gpio120"; 6092 function = "cci_i2c_scl"; 6093 drive-strength = <2>; 6094 bias-pull-up = <2200>; 6095 }; 6096 }; 6097 6098 cci2_1_sleep: cci2-1-sleep-state { 6099 sda-pins { 6100 pins = "gpio119"; 6101 function = "cci_i2c_sda"; 6102 drive-strength = <2>; 6103 bias-pull-down; 6104 }; 6105 6106 scl-pins { 6107 pins = "gpio120"; 6108 function = "cci_i2c_scl"; 6109 drive-strength = <2>; 6110 bias-pull-down; 6111 }; 6112 }; 6113 6114 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 6115 /* SDA, SCL */ 6116 pins = "gpio64", "gpio65"; 6117 function = "i2chub0_se0"; 6118 drive-strength = <2>; 6119 bias-pull-up; 6120 }; 6121 6122 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 6123 /* SDA, SCL */ 6124 pins = "gpio66", "gpio67"; 6125 function = "i2chub0_se1"; 6126 drive-strength = <2>; 6127 bias-pull-up; 6128 }; 6129 6130 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 6131 /* SDA, SCL */ 6132 pins = "gpio68", "gpio69"; 6133 function = "i2chub0_se2"; 6134 drive-strength = <2>; 6135 bias-pull-up; 6136 }; 6137 6138 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 6139 /* SDA, SCL */ 6140 pins = "gpio70", "gpio71"; 6141 function = "i2chub0_se3"; 6142 drive-strength = <2>; 6143 bias-pull-up; 6144 }; 6145 6146 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 6147 /* SDA, SCL */ 6148 pins = "gpio72", "gpio73"; 6149 function = "i2chub0_se4"; 6150 drive-strength = <2>; 6151 bias-pull-up; 6152 }; 6153 6154 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 6155 /* SDA, SCL */ 6156 pins = "gpio74", "gpio75"; 6157 function = "i2chub0_se5"; 6158 drive-strength = <2>; 6159 bias-pull-up; 6160 }; 6161 6162 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 6163 /* SDA, SCL */ 6164 pins = "gpio76", "gpio77"; 6165 function = "i2chub0_se6"; 6166 drive-strength = <2>; 6167 bias-pull-up; 6168 }; 6169 6170 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 6171 /* SDA, SCL */ 6172 pins = "gpio78", "gpio79"; 6173 function = "i2chub0_se7"; 6174 drive-strength = <2>; 6175 bias-pull-up; 6176 }; 6177 6178 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 6179 /* SDA, SCL */ 6180 pins = "gpio206", "gpio207"; 6181 function = "i2chub0_se8"; 6182 drive-strength = <2>; 6183 bias-pull-up; 6184 }; 6185 6186 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 6187 /* SDA, SCL */ 6188 pins = "gpio80", "gpio81"; 6189 function = "i2chub0_se9"; 6190 drive-strength = <2>; 6191 bias-pull-up; 6192 }; 6193 6194 pcie0_default_state: pcie0-default-state { 6195 perst-pins { 6196 pins = "gpio94"; 6197 function = "gpio"; 6198 drive-strength = <2>; 6199 bias-pull-down; 6200 }; 6201 6202 clkreq-pins { 6203 pins = "gpio95"; 6204 function = "pcie0_clk_req_n"; 6205 drive-strength = <2>; 6206 bias-pull-up; 6207 }; 6208 6209 wake-pins { 6210 pins = "gpio96"; 6211 function = "gpio"; 6212 drive-strength = <2>; 6213 bias-pull-up; 6214 }; 6215 }; 6216 6217 pcie1_default_state: pcie1-default-state { 6218 perst-pins { 6219 pins = "gpio97"; 6220 function = "gpio"; 6221 drive-strength = <2>; 6222 bias-pull-down; 6223 }; 6224 6225 clkreq-pins { 6226 pins = "gpio98"; 6227 function = "pcie1_clk_req_n"; 6228 drive-strength = <2>; 6229 bias-pull-up; 6230 }; 6231 6232 wake-pins { 6233 pins = "gpio99"; 6234 function = "gpio"; 6235 drive-strength = <2>; 6236 bias-pull-up; 6237 }; 6238 }; 6239 6240 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 6241 /* SDA, SCL */ 6242 pins = "gpio32", "gpio33"; 6243 function = "qup1_se0"; 6244 drive-strength = <2>; 6245 bias-pull-up; 6246 }; 6247 6248 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 6249 /* SDA, SCL */ 6250 pins = "gpio36", "gpio37"; 6251 function = "qup1_se1"; 6252 drive-strength = <2>; 6253 bias-pull-up; 6254 }; 6255 6256 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 6257 /* SDA, SCL */ 6258 pins = "gpio40", "gpio41"; 6259 function = "qup1_se2"; 6260 drive-strength = <2>; 6261 bias-pull-up; 6262 }; 6263 6264 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 6265 /* SDA, SCL */ 6266 pins = "gpio44", "gpio45"; 6267 function = "qup1_se3"; 6268 drive-strength = <2>; 6269 bias-pull-up; 6270 }; 6271 6272 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 6273 /* SDA, SCL */ 6274 pins = "gpio48", "gpio49"; 6275 function = "qup1_se4"; 6276 drive-strength = <2>; 6277 bias-pull-up; 6278 }; 6279 6280 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 6281 /* SDA, SCL */ 6282 pins = "gpio52", "gpio53"; 6283 function = "qup1_se5"; 6284 drive-strength = <2>; 6285 bias-pull-up; 6286 }; 6287 6288 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 6289 /* SDA, SCL */ 6290 pins = "gpio56", "gpio57"; 6291 function = "qup1_se6"; 6292 drive-strength = <2>; 6293 bias-pull-up; 6294 }; 6295 6296 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 6297 /* SDA, SCL */ 6298 pins = "gpio60", "gpio61"; 6299 function = "qup1_se7"; 6300 drive-strength = <2>; 6301 bias-pull-up; 6302 }; 6303 6304 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 6305 /* SDA, SCL */ 6306 pins = "gpio0", "gpio1"; 6307 function = "qup2_se0"; 6308 drive-strength = <2>; 6309 bias-pull-up; 6310 }; 6311 6312 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 6313 /* SDA, SCL */ 6314 pins = "gpio4", "gpio5"; 6315 function = "qup2_se1"; 6316 drive-strength = <2>; 6317 bias-pull-up; 6318 }; 6319 6320 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 6321 /* SDA, SCL */ 6322 pins = "gpio8", "gpio9"; 6323 function = "qup2_se2"; 6324 drive-strength = <2>; 6325 bias-pull-up; 6326 }; 6327 6328 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 6329 /* SDA, SCL */ 6330 pins = "gpio12", "gpio13"; 6331 function = "qup2_se3"; 6332 drive-strength = <2>; 6333 bias-pull-up; 6334 }; 6335 6336 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 6337 /* SDA, SCL */ 6338 pins = "gpio16", "gpio17"; 6339 function = "qup2_se4"; 6340 drive-strength = <2>; 6341 bias-pull-up; 6342 }; 6343 6344 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 6345 /* SDA, SCL */ 6346 pins = "gpio20", "gpio21"; 6347 function = "qup2_se5"; 6348 drive-strength = <2>; 6349 bias-pull-up; 6350 }; 6351 6352 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 6353 /* SDA, SCL */ 6354 pins = "gpio24", "gpio25"; 6355 function = "qup2_se6"; 6356 drive-strength = <2>; 6357 bias-pull-up; 6358 }; 6359 6360 qup_spi0_cs: qup-spi0-cs-state { 6361 pins = "gpio35"; 6362 function = "qup1_se0"; 6363 drive-strength = <6>; 6364 bias-disable; 6365 }; 6366 6367 qup_spi0_data_clk: qup-spi0-data-clk-state { 6368 /* MISO, MOSI, CLK */ 6369 pins = "gpio32", "gpio33", "gpio34"; 6370 function = "qup1_se0"; 6371 drive-strength = <6>; 6372 bias-disable; 6373 }; 6374 6375 qup_spi1_cs: qup-spi1-cs-state { 6376 pins = "gpio39"; 6377 function = "qup1_se1"; 6378 drive-strength = <6>; 6379 bias-disable; 6380 }; 6381 6382 qup_spi1_data_clk: qup-spi1-data-clk-state { 6383 /* MISO, MOSI, CLK */ 6384 pins = "gpio36", "gpio37", "gpio38"; 6385 function = "qup1_se1"; 6386 drive-strength = <6>; 6387 bias-disable; 6388 }; 6389 6390 qup_spi2_cs: qup-spi2-cs-state { 6391 pins = "gpio43"; 6392 function = "qup1_se2"; 6393 drive-strength = <6>; 6394 bias-disable; 6395 }; 6396 6397 qup_spi2_data_clk: qup-spi2-data-clk-state { 6398 /* MISO, MOSI, CLK */ 6399 pins = "gpio40", "gpio41", "gpio42"; 6400 function = "qup1_se2"; 6401 drive-strength = <6>; 6402 bias-disable; 6403 }; 6404 6405 qup_spi3_cs: qup-spi3-cs-state { 6406 pins = "gpio47"; 6407 function = "qup1_se3"; 6408 drive-strength = <6>; 6409 bias-disable; 6410 }; 6411 6412 qup_spi3_data_clk: qup-spi3-data-clk-state { 6413 /* MISO, MOSI, CLK */ 6414 pins = "gpio44", "gpio45", "gpio46"; 6415 function = "qup1_se3"; 6416 drive-strength = <6>; 6417 bias-disable; 6418 }; 6419 6420 qup_spi4_cs: qup-spi4-cs-state { 6421 pins = "gpio51"; 6422 function = "qup1_se4"; 6423 drive-strength = <6>; 6424 bias-disable; 6425 }; 6426 6427 qup_spi4_data_clk: qup-spi4-data-clk-state { 6428 /* MISO, MOSI, CLK */ 6429 pins = "gpio48", "gpio49", "gpio50"; 6430 function = "qup1_se4"; 6431 drive-strength = <6>; 6432 bias-disable; 6433 }; 6434 6435 qup_spi5_cs: qup-spi5-cs-state { 6436 pins = "gpio55"; 6437 function = "qup1_se5"; 6438 drive-strength = <6>; 6439 bias-disable; 6440 }; 6441 6442 qup_spi5_data_clk: qup-spi5-data-clk-state { 6443 /* MISO, MOSI, CLK */ 6444 pins = "gpio52", "gpio53", "gpio54"; 6445 function = "qup1_se5"; 6446 drive-strength = <6>; 6447 bias-disable; 6448 }; 6449 6450 qup_spi6_cs: qup-spi6-cs-state { 6451 pins = "gpio59"; 6452 function = "qup1_se6"; 6453 drive-strength = <6>; 6454 bias-disable; 6455 }; 6456 6457 qup_spi6_data_clk: qup-spi6-data-clk-state { 6458 /* MISO, MOSI, CLK */ 6459 pins = "gpio56", "gpio57", "gpio58"; 6460 function = "qup1_se6"; 6461 drive-strength = <6>; 6462 bias-disable; 6463 }; 6464 6465 qup_spi7_cs: qup-spi7-cs-state { 6466 pins = "gpio63"; 6467 function = "qup1_se7"; 6468 drive-strength = <6>; 6469 bias-disable; 6470 }; 6471 6472 qup_spi7_data_clk: qup-spi7-data-clk-state { 6473 /* MISO, MOSI, CLK */ 6474 pins = "gpio60", "gpio61", "gpio62"; 6475 function = "qup1_se7"; 6476 drive-strength = <6>; 6477 bias-disable; 6478 }; 6479 6480 qup_spi8_cs: qup-spi8-cs-state { 6481 pins = "gpio3"; 6482 function = "qup2_se0"; 6483 drive-strength = <6>; 6484 bias-disable; 6485 }; 6486 6487 qup_spi8_data_clk: qup-spi8-data-clk-state { 6488 /* MISO, MOSI, CLK */ 6489 pins = "gpio0", "gpio1", "gpio2"; 6490 function = "qup2_se0"; 6491 drive-strength = <6>; 6492 bias-disable; 6493 }; 6494 6495 qup_spi9_cs: qup-spi9-cs-state { 6496 pins = "gpio7"; 6497 function = "qup2_se1"; 6498 drive-strength = <6>; 6499 bias-disable; 6500 }; 6501 6502 qup_spi9_data_clk: qup-spi9-data-clk-state { 6503 /* MISO, MOSI, CLK */ 6504 pins = "gpio4", "gpio5", "gpio6"; 6505 function = "qup2_se1"; 6506 drive-strength = <6>; 6507 bias-disable; 6508 }; 6509 6510 qup_spi10_cs: qup-spi10-cs-state { 6511 pins = "gpio11"; 6512 function = "qup2_se2"; 6513 drive-strength = <6>; 6514 bias-disable; 6515 }; 6516 6517 qup_spi10_data_clk: qup-spi10-data-clk-state { 6518 /* MISO, MOSI, CLK */ 6519 pins = "gpio8", "gpio9", "gpio10"; 6520 function = "qup2_se2"; 6521 drive-strength = <6>; 6522 bias-disable; 6523 }; 6524 6525 qup_spi11_cs: qup-spi11-cs-state { 6526 pins = "gpio15"; 6527 function = "qup2_se3"; 6528 drive-strength = <6>; 6529 bias-disable; 6530 }; 6531 6532 qup_spi11_data_clk: qup-spi11-data-clk-state { 6533 /* MISO, MOSI, CLK */ 6534 pins = "gpio12", "gpio13", "gpio14"; 6535 function = "qup2_se3"; 6536 drive-strength = <6>; 6537 bias-disable; 6538 }; 6539 6540 qup_spi12_cs: qup-spi12-cs-state { 6541 pins = "gpio19"; 6542 function = "qup2_se4"; 6543 drive-strength = <6>; 6544 bias-disable; 6545 }; 6546 6547 qup_spi12_data_clk: qup-spi12-data-clk-state { 6548 /* MISO, MOSI, CLK */ 6549 pins = "gpio16", "gpio17", "gpio18"; 6550 function = "qup2_se4"; 6551 drive-strength = <6>; 6552 bias-disable; 6553 }; 6554 6555 qup_spi13_cs: qup-spi13-cs-state { 6556 pins = "gpio23"; 6557 function = "qup2_se5"; 6558 drive-strength = <6>; 6559 bias-disable; 6560 }; 6561 6562 qup_spi13_data_clk: qup-spi13-data-clk-state { 6563 /* MISO, MOSI, CLK */ 6564 pins = "gpio20", "gpio21", "gpio22"; 6565 function = "qup2_se5"; 6566 drive-strength = <6>; 6567 bias-disable; 6568 }; 6569 6570 qup_spi14_cs: qup-spi14-cs-state { 6571 pins = "gpio27"; 6572 function = "qup2_se6"; 6573 drive-strength = <6>; 6574 bias-disable; 6575 }; 6576 6577 qup_spi14_data_clk: qup-spi14-data-clk-state { 6578 /* MISO, MOSI, CLK */ 6579 pins = "gpio24", "gpio25", "gpio26"; 6580 function = "qup2_se6"; 6581 drive-strength = <6>; 6582 bias-disable; 6583 }; 6584 6585 qup_uart14_default: qup-uart14-default-state { 6586 /* TX, RX */ 6587 pins = "gpio26", "gpio27"; 6588 function = "qup2_se6"; 6589 drive-strength = <2>; 6590 bias-pull-up; 6591 }; 6592 6593 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 6594 /* CTS, RTS */ 6595 pins = "gpio24", "gpio25"; 6596 function = "qup2_se6"; 6597 drive-strength = <2>; 6598 bias-pull-down; 6599 }; 6600 6601 qup_uart15_default: qup-uart15-default-state { 6602 /* TX, RX */ 6603 pins = "gpio30", "gpio31"; 6604 function = "qup2_se7"; 6605 drive-strength = <2>; 6606 bias-disable; 6607 }; 6608 6609 sdc2_sleep: sdc2-sleep-state { 6610 clk-pins { 6611 pins = "sdc2_clk"; 6612 drive-strength = <2>; 6613 bias-disable; 6614 }; 6615 6616 cmd-pins { 6617 pins = "sdc2_cmd"; 6618 drive-strength = <2>; 6619 bias-pull-up; 6620 }; 6621 6622 data-pins { 6623 pins = "sdc2_data"; 6624 drive-strength = <2>; 6625 bias-pull-up; 6626 }; 6627 }; 6628 6629 sdc2_default: sdc2-default-state { 6630 clk-pins { 6631 pins = "sdc2_clk"; 6632 drive-strength = <16>; 6633 bias-disable; 6634 }; 6635 6636 cmd-pins { 6637 pins = "sdc2_cmd"; 6638 drive-strength = <10>; 6639 bias-pull-up; 6640 }; 6641 6642 data-pins { 6643 pins = "sdc2_data"; 6644 drive-strength = <10>; 6645 bias-pull-up; 6646 }; 6647 }; 6648 }; 6649 6650 funnel@10042000 { 6651 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6652 6653 reg = <0x0 0x10042000 0x0 0x1000>; 6654 6655 clocks = <&aoss_qmp>; 6656 clock-names = "apb_pclk"; 6657 6658 in-ports { 6659 #address-cells = <1>; 6660 #size-cells = <0>; 6661 6662 port@4 { 6663 reg = <4>; 6664 6665 funnel_in1_in_funnel_apss: endpoint { 6666 remote-endpoint = <&funnel_apss_out_funnel_in1>; 6667 }; 6668 }; 6669 }; 6670 6671 out-ports { 6672 port { 6673 funnel_in1_out_funnel_qdss: endpoint { 6674 remote-endpoint = <&funnel_qdss_in_funnel_in1>; 6675 }; 6676 }; 6677 }; 6678 }; 6679 6680 funnel@10045000 { 6681 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6682 6683 reg = <0x0 0x10045000 0x0 0x1000>; 6684 6685 clocks = <&aoss_qmp>; 6686 clock-names = "apb_pclk"; 6687 6688 in-ports { 6689 #address-cells = <1>; 6690 #size-cells = <0>; 6691 6692 port@1 { 6693 reg = <1>; 6694 6695 funnel_qdss_in_funnel_in1: endpoint { 6696 remote-endpoint = <&funnel_in1_out_funnel_qdss>; 6697 }; 6698 }; 6699 }; 6700 6701 out-ports { 6702 port { 6703 funnel_qdss_out_funnel_aoss: endpoint { 6704 remote-endpoint = <&funnel_aoss_in_funnel_qdss>; 6705 }; 6706 }; 6707 }; 6708 }; 6709 6710 funnel@10b04000 { 6711 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6712 6713 reg = <0x0 0x10b04000 0x0 0x1000>; 6714 6715 clocks = <&aoss_qmp>; 6716 clock-names = "apb_pclk"; 6717 6718 in-ports { 6719 #address-cells = <1>; 6720 #size-cells = <0>; 6721 6722 port@7 { 6723 reg = <7>; 6724 6725 funnel_aoss_in_funnel_qdss: endpoint { 6726 remote-endpoint = <&funnel_qdss_out_funnel_aoss>; 6727 }; 6728 }; 6729 }; 6730 6731 out-ports { 6732 port { 6733 funnel_aoss_out_tmc_etf: endpoint { 6734 remote-endpoint = <&tmc_etf_in_funnel_aoss>; 6735 }; 6736 }; 6737 }; 6738 }; 6739 6740 tmc@10b05000 { 6741 compatible = "arm,coresight-tmc", "arm,primecell"; 6742 6743 reg = <0x0 0x10b05000 0x0 0x1000>; 6744 6745 clocks = <&aoss_qmp>; 6746 clock-names = "apb_pclk"; 6747 6748 in-ports { 6749 port { 6750 tmc_etf_in_funnel_aoss: endpoint { 6751 remote-endpoint = <&funnel_aoss_out_tmc_etf>; 6752 }; 6753 }; 6754 }; 6755 }; 6756 6757 funnel@13810000 { 6758 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6759 6760 reg = <0x0 0x13810000 0x0 0x1000>; 6761 6762 clocks = <&aoss_qmp>; 6763 clock-names = "apb_pclk"; 6764 6765 in-ports { 6766 port { 6767 funnel_apss_in_funnel_ete: endpoint { 6768 remote-endpoint = <&funnel_ete_out_funnel_apss>; 6769 }; 6770 }; 6771 }; 6772 6773 out-ports { 6774 port { 6775 funnel_apss_out_funnel_in1: endpoint { 6776 remote-endpoint = <&funnel_in1_in_funnel_apss>; 6777 }; 6778 }; 6779 }; 6780 }; 6781 6782 apps_smmu: iommu@15000000 { 6783 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6784 reg = <0 0x15000000 0 0x100000>; 6785 6786 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, 6787 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, 6788 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, 6789 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, 6790 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, 6791 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 6792 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, 6793 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 6794 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 6795 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, 6796 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, 6797 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 6798 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 6799 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 6800 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, 6801 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, 6802 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, 6803 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, 6804 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 6805 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, 6806 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, 6807 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, 6808 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, 6809 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, 6810 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, 6811 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, 6812 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, 6813 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, 6814 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, 6815 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, 6816 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, 6817 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, 6818 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, 6819 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, 6820 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, 6821 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, 6822 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, 6823 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, 6824 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, 6825 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, 6826 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, 6827 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, 6828 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, 6829 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, 6830 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, 6831 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, 6832 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, 6833 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, 6834 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, 6835 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, 6836 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, 6837 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, 6838 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, 6839 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, 6840 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, 6841 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, 6842 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, 6843 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, 6844 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, 6845 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, 6846 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, 6847 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>, 6848 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>, 6849 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>, 6850 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>, 6851 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>, 6852 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>, 6853 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 6854 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 6855 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>, 6856 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>, 6857 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>, 6858 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>, 6859 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>, 6860 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>, 6861 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>, 6862 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>, 6863 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>, 6864 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, 6865 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, 6866 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, 6867 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, 6868 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, 6869 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>, 6870 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>, 6871 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>, 6872 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>, 6873 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>, 6874 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>, 6875 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>, 6876 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>, 6877 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>, 6878 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>, 6879 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>, 6880 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>, 6881 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>, 6882 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>; 6883 6884 #iommu-cells = <2>; 6885 #global-interrupts = <1>; 6886 6887 dma-coherent; 6888 }; 6889 6890 intc: interrupt-controller@17100000 { 6891 compatible = "arm,gic-v3"; 6892 reg = <0 0x17100000 0 0x10000>, /* GICD */ 6893 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 6894 6895 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>; 6896 6897 #interrupt-cells = <4>; 6898 interrupt-controller; 6899 6900 #redistributor-regions = <1>; 6901 redistributor-stride = <0 0x40000>; 6902 6903 #address-cells = <2>; 6904 #size-cells = <2>; 6905 ranges; 6906 6907 ppi-partitions { 6908 ppi_cluster0: interrupt-partition-0 { 6909 affinity = <&cpu0 &cpu1>; 6910 }; 6911 6912 ppi_cluster1: interrupt-partition-1 { 6913 affinity = <&cpu2 &cpu3 &cpu4 &cpu5 &cpu6>; 6914 }; 6915 6916 ppi_cluster2: interrupt-partition-2 { 6917 affinity = <&cpu7>; 6918 }; 6919 }; 6920 6921 gic_its: msi-controller@17140000 { 6922 compatible = "arm,gic-v3-its"; 6923 reg = <0 0x17140000 0 0x20000>; 6924 6925 msi-controller; 6926 #msi-cells = <1>; 6927 }; 6928 }; 6929 6930 timer@17420000 { 6931 compatible = "arm,armv7-timer-mem"; 6932 reg = <0 0x17420000 0 0x1000>; 6933 6934 ranges = <0 0 0 0x20000000>; 6935 #address-cells = <1>; 6936 #size-cells = <1>; 6937 6938 frame@17421000 { 6939 reg = <0x17421000 0x1000>, 6940 <0x17422000 0x1000>; 6941 6942 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, 6943 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 6944 6945 frame-number = <0>; 6946 }; 6947 6948 frame@17423000 { 6949 reg = <0x17423000 0x1000>; 6950 6951 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 6952 6953 frame-number = <1>; 6954 6955 status = "disabled"; 6956 }; 6957 6958 frame@17425000 { 6959 reg = <0x17425000 0x1000>; 6960 6961 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 6962 6963 frame-number = <2>; 6964 6965 status = "disabled"; 6966 }; 6967 6968 frame@17427000 { 6969 reg = <0x17427000 0x1000>; 6970 6971 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 6972 6973 frame-number = <3>; 6974 6975 status = "disabled"; 6976 }; 6977 6978 frame@17429000 { 6979 reg = <0x17429000 0x1000>; 6980 6981 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 6982 6983 frame-number = <4>; 6984 6985 status = "disabled"; 6986 }; 6987 6988 frame@1742b000 { 6989 reg = <0x1742b000 0x1000>; 6990 6991 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; 6992 6993 frame-number = <5>; 6994 6995 status = "disabled"; 6996 }; 6997 6998 frame@1742d000 { 6999 reg = <0x1742d000 0x1000>; 7000 7001 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 7002 7003 frame-number = <6>; 7004 7005 status = "disabled"; 7006 }; 7007 }; 7008 7009 apps_rsc: rsc@17a00000 { 7010 compatible = "qcom,rpmh-rsc"; 7011 reg = <0 0x17a00000 0 0x10000>, 7012 <0 0x17a10000 0 0x10000>, 7013 <0 0x17a20000 0 0x10000>; 7014 reg-names = "drv-0", 7015 "drv-1", 7016 "drv-2"; 7017 7018 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, 7019 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, 7020 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; 7021 7022 power-domains = <&cluster_pd>; 7023 7024 qcom,tcs-offset = <0xd00>; 7025 qcom,drv-id = <2>; 7026 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 7027 <WAKE_TCS 2>, <CONTROL_TCS 0>; 7028 7029 label = "apps_rsc"; 7030 7031 apps_bcm_voter: bcm-voter { 7032 compatible = "qcom,bcm-voter"; 7033 }; 7034 7035 rpmhcc: clock-controller { 7036 compatible = "qcom,sm8650-rpmh-clk"; 7037 7038 clocks = <&xo_board>; 7039 clock-names = "xo"; 7040 7041 #clock-cells = <1>; 7042 }; 7043 7044 rpmhpd: power-controller { 7045 compatible = "qcom,sm8650-rpmhpd"; 7046 7047 operating-points-v2 = <&rpmhpd_opp_table>; 7048 7049 #power-domain-cells = <1>; 7050 7051 rpmhpd_opp_table: opp-table { 7052 compatible = "operating-points-v2"; 7053 7054 rpmhpd_opp_ret: opp-16 { 7055 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 7056 }; 7057 7058 rpmhpd_opp_min_svs: opp-48 { 7059 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 7060 }; 7061 7062 rpmhpd_opp_low_svs_d2: opp-52 { 7063 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 7064 }; 7065 7066 rpmhpd_opp_low_svs_d1: opp-56 { 7067 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 7068 }; 7069 7070 rpmhpd_opp_low_svs_d0: opp-60 { 7071 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 7072 }; 7073 7074 rpmhpd_opp_low_svs: opp-64 { 7075 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 7076 }; 7077 7078 rpmhpd_opp_low_svs_l1: opp-80 { 7079 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 7080 }; 7081 7082 rpmhpd_opp_svs: opp-128 { 7083 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 7084 }; 7085 7086 rpmhpd_opp_svs_l0: opp-144 { 7087 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 7088 }; 7089 7090 rpmhpd_opp_svs_l1: opp-192 { 7091 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 7092 }; 7093 7094 rpmhpd_opp_nom: opp-256 { 7095 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 7096 }; 7097 7098 rpmhpd_opp_nom_l1: opp-320 { 7099 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 7100 }; 7101 7102 rpmhpd_opp_nom_l2: opp-336 { 7103 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 7104 }; 7105 7106 rpmhpd_opp_turbo: opp-384 { 7107 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 7108 }; 7109 7110 rpmhpd_opp_turbo_l1: opp-416 { 7111 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 7112 }; 7113 }; 7114 }; 7115 }; 7116 7117 epss_l3: interconnect@17d90000 { 7118 compatible = "qcom,sm8650-epss-l3", "qcom,epss-l3"; 7119 reg = <0 0x17d90000 0 0x1000>; 7120 7121 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 7122 clock-names = "xo", "alternate"; 7123 7124 #interconnect-cells = <1>; 7125 }; 7126 7127 cpufreq_hw: cpufreq@17d91000 { 7128 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss"; 7129 reg = <0 0x17d91000 0 0x1000>, 7130 <0 0x17d92000 0 0x1000>, 7131 <0 0x17d93000 0 0x1000>, 7132 <0 0x17d94000 0 0x1000>; 7133 reg-names = "freq-domain0", 7134 "freq-domain1", 7135 "freq-domain2", 7136 "freq-domain3"; 7137 7138 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, 7139 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>, 7140 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, 7141 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH 0>; 7142 interrupt-names = "dcvsh-irq-0", 7143 "dcvsh-irq-1", 7144 "dcvsh-irq-2", 7145 "dcvsh-irq-3"; 7146 7147 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 7148 clock-names = "xo", "alternate"; 7149 7150 #freq-domain-cells = <1>; 7151 #clock-cells = <1>; 7152 }; 7153 7154 pmu@24091000 { 7155 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 7156 reg = <0 0x24091000 0 0x1000>; 7157 7158 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 7159 7160 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 7161 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 7162 7163 operating-points-v2 = <&llcc_bwmon_opp_table>; 7164 7165 llcc_bwmon_opp_table: opp-table { 7166 compatible = "operating-points-v2"; 7167 7168 opp-0 { 7169 opp-peak-kBps = <2086000>; 7170 }; 7171 7172 opp-1 { 7173 opp-peak-kBps = <2929000>; 7174 }; 7175 7176 opp-2 { 7177 opp-peak-kBps = <5931000>; 7178 }; 7179 7180 opp-3 { 7181 opp-peak-kBps = <6515000>; 7182 }; 7183 7184 opp-4 { 7185 opp-peak-kBps = <7980000>; 7186 }; 7187 7188 opp-5 { 7189 opp-peak-kBps = <10437000>; 7190 }; 7191 7192 opp-6 { 7193 opp-peak-kBps = <12157000>; 7194 }; 7195 7196 opp-7 { 7197 opp-peak-kBps = <14060000>; 7198 }; 7199 7200 opp-8 { 7201 opp-peak-kBps = <16113000>; 7202 }; 7203 }; 7204 }; 7205 7206 pmu@240b7400 { 7207 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; 7208 reg = <0 0x240b7400 0 0x600>; 7209 7210 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>; 7211 7212 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 7213 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 7214 7215 operating-points-v2 = <&cpu_bwmon_opp_table>; 7216 7217 cpu_bwmon_opp_table: opp-table { 7218 compatible = "operating-points-v2"; 7219 7220 opp-0 { 7221 opp-peak-kBps = <4577000>; 7222 }; 7223 7224 opp-1 { 7225 opp-peak-kBps = <7110000>; 7226 }; 7227 7228 opp-2 { 7229 opp-peak-kBps = <9155000>; 7230 }; 7231 7232 opp-3 { 7233 opp-peak-kBps = <12298000>; 7234 }; 7235 7236 opp-4 { 7237 opp-peak-kBps = <14236000>; 7238 }; 7239 7240 opp-5 { 7241 opp-peak-kBps = <16265000>; 7242 }; 7243 }; 7244 }; 7245 7246 gem_noc: interconnect@24100000 { 7247 compatible = "qcom,sm8650-gem-noc"; 7248 reg = <0 0x24100000 0 0xc5080>; 7249 7250 qcom,bcm-voters = <&apps_bcm_voter>; 7251 7252 #interconnect-cells = <2>; 7253 }; 7254 7255 system-cache-controller@25000000 { 7256 compatible = "qcom,sm8650-llcc"; 7257 reg = <0 0x25000000 0 0x200000>, 7258 <0 0x25400000 0 0x200000>, 7259 <0 0x25200000 0 0x200000>, 7260 <0 0x25600000 0 0x200000>, 7261 <0 0x25800000 0 0x200000>, 7262 <0 0x25a00000 0 0x200000>; 7263 reg-names = "llcc0_base", 7264 "llcc1_base", 7265 "llcc2_base", 7266 "llcc3_base", 7267 "llcc_broadcast_base", 7268 "llcc_broadcast_and_base"; 7269 7270 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH 0>; 7271 }; 7272 7273 nsp_noc: interconnect@320c0000 { 7274 compatible = "qcom,sm8650-nsp-noc"; 7275 reg = <0 0x320c0000 0 0xf080>; 7276 7277 qcom,bcm-voters = <&apps_bcm_voter>; 7278 7279 #interconnect-cells = <2>; 7280 }; 7281 7282 remoteproc_cdsp: remoteproc@32300000 { 7283 compatible = "qcom,sm8650-cdsp-pas"; 7284 reg = <0x0 0x32300000 0x0 0x10000>; 7285 7286 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, 7287 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 7288 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 7289 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 7290 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 7291 interrupt-names = "wdog", 7292 "fatal", 7293 "ready", 7294 "handover", 7295 "stop-ack"; 7296 7297 clocks = <&rpmhcc RPMH_CXO_CLK>; 7298 clock-names = "xo"; 7299 7300 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 7301 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7302 7303 power-domains = <&rpmhpd RPMHPD_CX>, 7304 <&rpmhpd RPMHPD_MXC>, 7305 <&rpmhpd RPMHPD_NSP>; 7306 power-domain-names = "cx", 7307 "mxc", 7308 "nsp"; 7309 7310 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; 7311 7312 qcom,qmp = <&aoss_qmp>; 7313 7314 qcom,smem-states = <&smp2p_cdsp_out 0>; 7315 qcom,smem-state-names = "stop"; 7316 7317 status = "disabled"; 7318 7319 glink-edge { 7320 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 7321 IPCC_MPROC_SIGNAL_GLINK_QMP 7322 IRQ_TYPE_EDGE_RISING>; 7323 7324 mboxes = <&ipcc IPCC_CLIENT_CDSP 7325 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7326 7327 qcom,remote-pid = <5>; 7328 7329 label = "cdsp"; 7330 7331 fastrpc { 7332 compatible = "qcom,fastrpc"; 7333 7334 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7335 7336 label = "cdsp"; 7337 7338 qcom,non-secure-domain; 7339 7340 #address-cells = <1>; 7341 #size-cells = <0>; 7342 7343 compute-cb@1 { 7344 compatible = "qcom,fastrpc-compute-cb"; 7345 reg = <1>; 7346 7347 iommus = <&apps_smmu 0x1961 0x0>, 7348 <&apps_smmu 0x0c01 0x20>, 7349 <&apps_smmu 0x19c1 0x0>; 7350 dma-coherent; 7351 }; 7352 7353 compute-cb@2 { 7354 compatible = "qcom,fastrpc-compute-cb"; 7355 reg = <2>; 7356 7357 iommus = <&apps_smmu 0x1962 0x0>, 7358 <&apps_smmu 0x0c02 0x20>, 7359 <&apps_smmu 0x19c2 0x0>; 7360 dma-coherent; 7361 }; 7362 7363 compute-cb@3 { 7364 compatible = "qcom,fastrpc-compute-cb"; 7365 reg = <3>; 7366 7367 iommus = <&apps_smmu 0x1963 0x0>, 7368 <&apps_smmu 0x0c03 0x20>, 7369 <&apps_smmu 0x19c3 0x0>; 7370 dma-coherent; 7371 }; 7372 7373 compute-cb@4 { 7374 compatible = "qcom,fastrpc-compute-cb"; 7375 reg = <4>; 7376 7377 iommus = <&apps_smmu 0x1964 0x0>, 7378 <&apps_smmu 0x0c04 0x20>, 7379 <&apps_smmu 0x19c4 0x0>; 7380 dma-coherent; 7381 }; 7382 7383 compute-cb@5 { 7384 compatible = "qcom,fastrpc-compute-cb"; 7385 reg = <5>; 7386 7387 iommus = <&apps_smmu 0x1965 0x0>, 7388 <&apps_smmu 0x0c05 0x20>, 7389 <&apps_smmu 0x19c5 0x0>; 7390 dma-coherent; 7391 }; 7392 7393 compute-cb@6 { 7394 compatible = "qcom,fastrpc-compute-cb"; 7395 reg = <6>; 7396 7397 iommus = <&apps_smmu 0x1966 0x0>, 7398 <&apps_smmu 0x0c06 0x20>, 7399 <&apps_smmu 0x19c6 0x0>; 7400 dma-coherent; 7401 }; 7402 7403 compute-cb@7 { 7404 compatible = "qcom,fastrpc-compute-cb"; 7405 reg = <7>; 7406 7407 iommus = <&apps_smmu 0x1967 0x0>, 7408 <&apps_smmu 0x0c07 0x20>, 7409 <&apps_smmu 0x19c7 0x0>; 7410 dma-coherent; 7411 }; 7412 7413 compute-cb@8 { 7414 compatible = "qcom,fastrpc-compute-cb"; 7415 reg = <8>; 7416 7417 iommus = <&apps_smmu 0x1968 0x0>, 7418 <&apps_smmu 0x0c08 0x20>, 7419 <&apps_smmu 0x19c8 0x0>; 7420 dma-coherent; 7421 }; 7422 7423 /* note: secure cb9 in downstream */ 7424 7425 compute-cb@12 { 7426 compatible = "qcom,fastrpc-compute-cb"; 7427 reg = <12>; 7428 7429 iommus = <&apps_smmu 0x196c 0x0>, 7430 <&apps_smmu 0x0c0c 0x20>, 7431 <&apps_smmu 0x19cc 0x0>; 7432 dma-coherent; 7433 }; 7434 7435 compute-cb@13 { 7436 compatible = "qcom,fastrpc-compute-cb"; 7437 reg = <13>; 7438 7439 iommus = <&apps_smmu 0x196d 0x0>, 7440 <&apps_smmu 0x0c0d 0x20>, 7441 <&apps_smmu 0x19cd 0x0>; 7442 dma-coherent; 7443 }; 7444 7445 compute-cb@14 { 7446 compatible = "qcom,fastrpc-compute-cb"; 7447 reg = <14>; 7448 7449 iommus = <&apps_smmu 0x196e 0x0>, 7450 <&apps_smmu 0x0c0e 0x20>, 7451 <&apps_smmu 0x19ce 0x0>; 7452 dma-coherent; 7453 }; 7454 }; 7455 }; 7456 }; 7457 }; 7458 7459 thermal-zones { 7460 aoss0-thermal { 7461 thermal-sensors = <&tsens0 0>; 7462 7463 trips { 7464 aoss0-hot { 7465 temperature = <110000>; 7466 hysteresis = <1000>; 7467 type = "hot"; 7468 }; 7469 7470 aoss0-critical { 7471 temperature = <115000>; 7472 hysteresis = <0>; 7473 type = "critical"; 7474 }; 7475 }; 7476 }; 7477 7478 cpuss0-thermal { 7479 thermal-sensors = <&tsens0 1>; 7480 7481 trips { 7482 cpuss0-hot { 7483 temperature = <110000>; 7484 hysteresis = <1000>; 7485 type = "hot"; 7486 }; 7487 7488 cpuss0-critical { 7489 temperature = <115000>; 7490 hysteresis = <0>; 7491 type = "critical"; 7492 }; 7493 }; 7494 }; 7495 7496 cpuss1-thermal { 7497 thermal-sensors = <&tsens0 2>; 7498 7499 trips { 7500 cpuss1-hot { 7501 temperature = <110000>; 7502 hysteresis = <1000>; 7503 type = "hot"; 7504 }; 7505 7506 cpuss1-critical { 7507 temperature = <115000>; 7508 hysteresis = <0>; 7509 type = "critical"; 7510 }; 7511 }; 7512 }; 7513 7514 cpuss2-thermal { 7515 thermal-sensors = <&tsens0 3>; 7516 7517 trips { 7518 cpuss2-hot { 7519 temperature = <110000>; 7520 hysteresis = <1000>; 7521 type = "hot"; 7522 }; 7523 7524 cpuss2-critical { 7525 temperature = <115000>; 7526 hysteresis = <0>; 7527 type = "critical"; 7528 }; 7529 }; 7530 }; 7531 7532 cpuss3-thermal { 7533 thermal-sensors = <&tsens0 4>; 7534 7535 trips { 7536 cpuss3-hot { 7537 temperature = <110000>; 7538 hysteresis = <1000>; 7539 type = "hot"; 7540 }; 7541 7542 cpuss3-critical { 7543 temperature = <115000>; 7544 hysteresis = <0>; 7545 type = "critical"; 7546 }; 7547 }; 7548 }; 7549 7550 cpu2-top-thermal { 7551 thermal-sensors = <&tsens0 5>; 7552 7553 trips { 7554 cpu2-critical { 7555 temperature = <110000>; 7556 hysteresis = <1000>; 7557 type = "critical"; 7558 }; 7559 }; 7560 }; 7561 7562 cpu2-bottom-thermal { 7563 thermal-sensors = <&tsens0 6>; 7564 7565 trips { 7566 cpu2-critical { 7567 temperature = <110000>; 7568 hysteresis = <1000>; 7569 type = "critical"; 7570 }; 7571 }; 7572 }; 7573 7574 cpu3-top-thermal { 7575 thermal-sensors = <&tsens0 7>; 7576 7577 trips { 7578 cpu3-critical { 7579 temperature = <110000>; 7580 hysteresis = <1000>; 7581 type = "critical"; 7582 }; 7583 }; 7584 }; 7585 7586 cpu3-bottom-thermal { 7587 thermal-sensors = <&tsens0 8>; 7588 7589 trips { 7590 cpu3-critical { 7591 temperature = <110000>; 7592 hysteresis = <1000>; 7593 type = "critical"; 7594 }; 7595 }; 7596 }; 7597 7598 cpu4-top-thermal { 7599 thermal-sensors = <&tsens0 9>; 7600 7601 trips { 7602 cpu4-critical { 7603 temperature = <110000>; 7604 hysteresis = <1000>; 7605 type = "critical"; 7606 }; 7607 }; 7608 }; 7609 7610 cpu4-bottom-thermal { 7611 thermal-sensors = <&tsens0 10>; 7612 7613 trips { 7614 cpu4-critical { 7615 temperature = <110000>; 7616 hysteresis = <1000>; 7617 type = "critical"; 7618 }; 7619 }; 7620 }; 7621 7622 cpu5-top-thermal { 7623 thermal-sensors = <&tsens0 11>; 7624 7625 trips { 7626 cpu5-critical { 7627 temperature = <110000>; 7628 hysteresis = <1000>; 7629 type = "critical"; 7630 }; 7631 }; 7632 }; 7633 7634 cpu5-bottom-thermal { 7635 thermal-sensors = <&tsens0 12>; 7636 7637 trips { 7638 cpu5-critical { 7639 temperature = <110000>; 7640 hysteresis = <1000>; 7641 type = "critical"; 7642 }; 7643 }; 7644 }; 7645 7646 cpu6-top-thermal { 7647 thermal-sensors = <&tsens0 13>; 7648 7649 trips { 7650 cpu6-critical { 7651 temperature = <110000>; 7652 hysteresis = <1000>; 7653 type = "critical"; 7654 }; 7655 }; 7656 }; 7657 7658 cpu6-bottom-thermal { 7659 thermal-sensors = <&tsens0 14>; 7660 7661 trips { 7662 cpu6-critical { 7663 temperature = <110000>; 7664 hysteresis = <1000>; 7665 type = "critical"; 7666 }; 7667 }; 7668 }; 7669 7670 aoss1-thermal { 7671 thermal-sensors = <&tsens1 0>; 7672 7673 trips { 7674 aoss1-hot { 7675 temperature = <110000>; 7676 hysteresis = <1000>; 7677 type = "hot"; 7678 }; 7679 7680 aoss1-critical { 7681 temperature = <115000>; 7682 hysteresis = <0>; 7683 type = "critical"; 7684 }; 7685 }; 7686 }; 7687 7688 cpu7-top-thermal { 7689 thermal-sensors = <&tsens1 1>; 7690 7691 trips { 7692 cpu7-critical { 7693 temperature = <110000>; 7694 hysteresis = <1000>; 7695 type = "critical"; 7696 }; 7697 }; 7698 }; 7699 7700 cpu7-middle-thermal { 7701 thermal-sensors = <&tsens1 2>; 7702 7703 trips { 7704 cpu7-critical { 7705 temperature = <110000>; 7706 hysteresis = <1000>; 7707 type = "critical"; 7708 }; 7709 }; 7710 }; 7711 7712 cpu7-bottom-thermal { 7713 thermal-sensors = <&tsens1 3>; 7714 7715 trips { 7716 cpu7-critical { 7717 temperature = <110000>; 7718 hysteresis = <1000>; 7719 type = "critical"; 7720 }; 7721 }; 7722 }; 7723 7724 cpu0-thermal { 7725 thermal-sensors = <&tsens1 4>; 7726 7727 trips { 7728 cpu0-critical { 7729 temperature = <110000>; 7730 hysteresis = <1000>; 7731 type = "critical"; 7732 }; 7733 }; 7734 }; 7735 7736 cpu1-thermal { 7737 thermal-sensors = <&tsens1 5>; 7738 7739 trips { 7740 cpu1-critical { 7741 temperature = <110000>; 7742 hysteresis = <1000>; 7743 type = "critical"; 7744 }; 7745 }; 7746 }; 7747 7748 nsphvx0-thermal { 7749 thermal-sensors = <&tsens2 6>; 7750 7751 trips { 7752 nsphvx0-hot { 7753 temperature = <110000>; 7754 hysteresis = <1000>; 7755 type = "hot"; 7756 }; 7757 7758 nsphvx0-critical { 7759 temperature = <115000>; 7760 hysteresis = <0>; 7761 type = "critical"; 7762 }; 7763 }; 7764 }; 7765 7766 nsphvx1-thermal { 7767 thermal-sensors = <&tsens2 7>; 7768 7769 trips { 7770 nsphvx1-hot { 7771 temperature = <110000>; 7772 hysteresis = <1000>; 7773 type = "hot"; 7774 }; 7775 7776 nsphvx1-critical { 7777 temperature = <115000>; 7778 hysteresis = <0>; 7779 type = "critical"; 7780 }; 7781 }; 7782 }; 7783 7784 nsphmx0-thermal { 7785 thermal-sensors = <&tsens2 8>; 7786 7787 trips { 7788 nsphmx0-hot { 7789 temperature = <110000>; 7790 hysteresis = <1000>; 7791 type = "hot"; 7792 }; 7793 7794 nsphmx0-critical { 7795 temperature = <115000>; 7796 hysteresis = <0>; 7797 type = "critical"; 7798 }; 7799 }; 7800 }; 7801 7802 nsphmx1-thermal { 7803 thermal-sensors = <&tsens2 9>; 7804 7805 trips { 7806 nsphmx1-hot { 7807 temperature = <110000>; 7808 hysteresis = <1000>; 7809 type = "hot"; 7810 }; 7811 7812 nsphmx1-critical { 7813 temperature = <115000>; 7814 hysteresis = <0>; 7815 type = "critical"; 7816 }; 7817 }; 7818 }; 7819 7820 nsphmx2-thermal { 7821 thermal-sensors = <&tsens2 10>; 7822 7823 trips { 7824 nsphmx2-hot { 7825 temperature = <110000>; 7826 hysteresis = <1000>; 7827 type = "hot"; 7828 }; 7829 7830 nsphmx2-critical { 7831 temperature = <115000>; 7832 hysteresis = <0>; 7833 type = "critical"; 7834 }; 7835 }; 7836 }; 7837 7838 nsphmx3-thermal { 7839 thermal-sensors = <&tsens2 11>; 7840 7841 trips { 7842 nsphmx3-hot { 7843 temperature = <110000>; 7844 hysteresis = <1000>; 7845 type = "hot"; 7846 }; 7847 7848 nsphmx3-critical { 7849 temperature = <115000>; 7850 hysteresis = <0>; 7851 type = "critical"; 7852 }; 7853 }; 7854 }; 7855 7856 video-thermal { 7857 thermal-sensors = <&tsens1 12>; 7858 7859 trips { 7860 video-hot { 7861 temperature = <110000>; 7862 hysteresis = <1000>; 7863 type = "hot"; 7864 }; 7865 7866 video-critical { 7867 temperature = <115000>; 7868 hysteresis = <0>; 7869 type = "critical"; 7870 }; 7871 }; 7872 }; 7873 7874 ddr-thermal { 7875 thermal-sensors = <&tsens1 13>; 7876 7877 trips { 7878 ddr-hot { 7879 temperature = <110000>; 7880 hysteresis = <1000>; 7881 type = "hot"; 7882 }; 7883 7884 ddr-critical { 7885 temperature = <115000>; 7886 hysteresis = <0>; 7887 type = "critical"; 7888 }; 7889 }; 7890 }; 7891 7892 camera0-thermal { 7893 thermal-sensors = <&tsens1 14>; 7894 7895 trips { 7896 camera0-hot { 7897 temperature = <110000>; 7898 hysteresis = <1000>; 7899 type = "hot"; 7900 }; 7901 7902 camera0-critical { 7903 temperature = <115000>; 7904 hysteresis = <0>; 7905 type = "critical"; 7906 }; 7907 }; 7908 }; 7909 7910 camera1-thermal { 7911 thermal-sensors = <&tsens1 15>; 7912 7913 trips { 7914 camera1-hot { 7915 temperature = <110000>; 7916 hysteresis = <1000>; 7917 type = "hot"; 7918 }; 7919 7920 camera1-critical { 7921 temperature = <115000>; 7922 hysteresis = <0>; 7923 type = "critical"; 7924 }; 7925 }; 7926 }; 7927 7928 aoss2-thermal { 7929 thermal-sensors = <&tsens2 0>; 7930 7931 trips { 7932 aoss2-hot { 7933 temperature = <110000>; 7934 hysteresis = <1000>; 7935 type = "hot"; 7936 }; 7937 7938 aoss2-critical { 7939 temperature = <115000>; 7940 hysteresis = <0>; 7941 type = "critical"; 7942 }; 7943 }; 7944 }; 7945 7946 gpuss0-thermal { 7947 polling-delay-passive = <10>; 7948 7949 thermal-sensors = <&tsens2 1>; 7950 7951 cooling-maps { 7952 map0 { 7953 trip = <&gpu0_alert0>; 7954 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7955 }; 7956 }; 7957 7958 trips { 7959 gpu0_alert0: trip-point0 { 7960 temperature = <95000>; 7961 hysteresis = <1000>; 7962 type = "passive"; 7963 }; 7964 7965 trip-point1 { 7966 temperature = <110000>; 7967 hysteresis = <1000>; 7968 type = "hot"; 7969 }; 7970 7971 trip-point2 { 7972 temperature = <115000>; 7973 hysteresis = <0>; 7974 type = "critical"; 7975 }; 7976 }; 7977 }; 7978 7979 gpuss1-thermal { 7980 polling-delay-passive = <10>; 7981 7982 thermal-sensors = <&tsens2 2>; 7983 7984 cooling-maps { 7985 map0 { 7986 trip = <&gpu1_alert0>; 7987 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7988 }; 7989 }; 7990 7991 trips { 7992 gpu1_alert0: trip-point0 { 7993 temperature = <95000>; 7994 hysteresis = <1000>; 7995 type = "passive"; 7996 }; 7997 7998 trip-point1 { 7999 temperature = <110000>; 8000 hysteresis = <1000>; 8001 type = "hot"; 8002 }; 8003 8004 trip-point2 { 8005 temperature = <115000>; 8006 hysteresis = <0>; 8007 type = "critical"; 8008 }; 8009 }; 8010 }; 8011 8012 gpuss2-thermal { 8013 polling-delay-passive = <10>; 8014 8015 thermal-sensors = <&tsens2 3>; 8016 8017 cooling-maps { 8018 map0 { 8019 trip = <&gpu2_alert0>; 8020 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8021 }; 8022 }; 8023 8024 trips { 8025 gpu2_alert0: trip-point0 { 8026 temperature = <95000>; 8027 hysteresis = <1000>; 8028 type = "passive"; 8029 }; 8030 8031 trip-point1 { 8032 temperature = <110000>; 8033 hysteresis = <1000>; 8034 type = "hot"; 8035 }; 8036 8037 trip-point2 { 8038 temperature = <115000>; 8039 hysteresis = <0>; 8040 type = "critical"; 8041 }; 8042 }; 8043 }; 8044 8045 gpuss3-thermal { 8046 polling-delay-passive = <10>; 8047 8048 thermal-sensors = <&tsens2 4>; 8049 8050 cooling-maps { 8051 map0 { 8052 trip = <&gpu3_alert0>; 8053 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8054 }; 8055 }; 8056 8057 trips { 8058 gpu3_alert0: trip-point0 { 8059 temperature = <95000>; 8060 hysteresis = <1000>; 8061 type = "passive"; 8062 }; 8063 8064 trip-point1 { 8065 temperature = <110000>; 8066 hysteresis = <1000>; 8067 type = "hot"; 8068 }; 8069 8070 trip-point2 { 8071 temperature = <115000>; 8072 hysteresis = <0>; 8073 type = "critical"; 8074 }; 8075 }; 8076 }; 8077 8078 gpuss4-thermal { 8079 polling-delay-passive = <10>; 8080 8081 thermal-sensors = <&tsens2 5>; 8082 8083 cooling-maps { 8084 map0 { 8085 trip = <&gpu4_alert0>; 8086 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8087 }; 8088 }; 8089 8090 trips { 8091 gpu4_alert0: trip-point0 { 8092 temperature = <95000>; 8093 hysteresis = <1000>; 8094 type = "passive"; 8095 }; 8096 8097 trip-point1 { 8098 temperature = <110000>; 8099 hysteresis = <1000>; 8100 type = "hot"; 8101 }; 8102 8103 trip-point2 { 8104 temperature = <115000>; 8105 hysteresis = <0>; 8106 type = "critical"; 8107 }; 8108 }; 8109 }; 8110 8111 gpuss5-thermal { 8112 polling-delay-passive = <10>; 8113 8114 thermal-sensors = <&tsens2 6>; 8115 8116 cooling-maps { 8117 map0 { 8118 trip = <&gpu5_alert0>; 8119 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8120 }; 8121 }; 8122 8123 trips { 8124 gpu5_alert0: trip-point0 { 8125 temperature = <95000>; 8126 hysteresis = <1000>; 8127 type = "passive"; 8128 }; 8129 8130 trip-point1 { 8131 temperature = <110000>; 8132 hysteresis = <1000>; 8133 type = "hot"; 8134 }; 8135 8136 trip-point2 { 8137 temperature = <115000>; 8138 hysteresis = <0>; 8139 type = "critical"; 8140 }; 8141 }; 8142 }; 8143 8144 gpuss6-thermal { 8145 polling-delay-passive = <10>; 8146 8147 thermal-sensors = <&tsens2 7>; 8148 8149 cooling-maps { 8150 map0 { 8151 trip = <&gpu6_alert0>; 8152 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8153 }; 8154 }; 8155 8156 trips { 8157 gpu6_alert0: trip-point0 { 8158 temperature = <95000>; 8159 hysteresis = <1000>; 8160 type = "passive"; 8161 }; 8162 8163 trip-point1 { 8164 temperature = <110000>; 8165 hysteresis = <1000>; 8166 type = "hot"; 8167 }; 8168 8169 trip-point2 { 8170 temperature = <115000>; 8171 hysteresis = <0>; 8172 type = "critical"; 8173 }; 8174 }; 8175 }; 8176 8177 gpuss7-thermal { 8178 polling-delay-passive = <10>; 8179 8180 thermal-sensors = <&tsens2 8>; 8181 8182 cooling-maps { 8183 map0 { 8184 trip = <&gpu7_alert0>; 8185 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8186 }; 8187 }; 8188 8189 trips { 8190 gpu7_alert0: trip-point0 { 8191 temperature = <95000>; 8192 hysteresis = <1000>; 8193 type = "passive"; 8194 }; 8195 8196 trip-point1 { 8197 temperature = <110000>; 8198 hysteresis = <1000>; 8199 type = "hot"; 8200 }; 8201 8202 trip-point2 { 8203 temperature = <115000>; 8204 hysteresis = <0>; 8205 type = "critical"; 8206 }; 8207 }; 8208 }; 8209 8210 modem0-thermal { 8211 thermal-sensors = <&tsens2 9>; 8212 8213 trips { 8214 modem0-hot { 8215 temperature = <110000>; 8216 hysteresis = <1000>; 8217 type = "hot"; 8218 }; 8219 8220 modem0-critical { 8221 temperature = <115000>; 8222 hysteresis = <0>; 8223 type = "critical"; 8224 }; 8225 }; 8226 }; 8227 8228 modem1-thermal { 8229 thermal-sensors = <&tsens2 10>; 8230 8231 trips { 8232 modem1-hot { 8233 temperature = <110000>; 8234 hysteresis = <1000>; 8235 type = "hot"; 8236 }; 8237 8238 modem1-critical { 8239 temperature = <115000>; 8240 hysteresis = <0>; 8241 type = "critical"; 8242 }; 8243 }; 8244 }; 8245 8246 modem2-thermal { 8247 thermal-sensors = <&tsens2 11>; 8248 8249 trips { 8250 modem2-hot { 8251 temperature = <110000>; 8252 hysteresis = <1000>; 8253 type = "hot"; 8254 }; 8255 8256 modem2-critical { 8257 temperature = <115000>; 8258 hysteresis = <0>; 8259 type = "critical"; 8260 }; 8261 }; 8262 }; 8263 8264 modem3-thermal { 8265 thermal-sensors = <&tsens2 12>; 8266 8267 trips { 8268 modem3-hot { 8269 temperature = <110000>; 8270 hysteresis = <1000>; 8271 type = "hot"; 8272 }; 8273 8274 modem3-critical { 8275 temperature = <115000>; 8276 hysteresis = <0>; 8277 type = "critical"; 8278 }; 8279 }; 8280 }; 8281 }; 8282 8283 timer { 8284 compatible = "arm,armv8-timer"; 8285 8286 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 8287 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 8288 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 8289 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 8290 }; 8291}; 8292