1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8650-camcc.h> 8#include <dt-bindings/clock/qcom,sm8650-dispcc.h> 9#include <dt-bindings/clock/qcom,sm8650-gcc.h> 10#include <dt-bindings/clock/qcom,sm8650-gpucc.h> 11#include <dt-bindings/clock/qcom,sm8650-tcsr.h> 12#include <dt-bindings/clock/qcom,sm8650-videocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interconnect/qcom,icc.h> 17#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/phy/phy-qcom-qmp.h> 21#include <dt-bindings/power/qcom,rpmhpd.h> 22#include <dt-bindings/power/qcom-rpmpd.h> 23#include <dt-bindings/reset/qcom,sm8650-gpucc.h> 24#include <dt-bindings/soc/qcom,gpr.h> 25#include <dt-bindings/soc/qcom,rpmh-rsc.h> 26#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 chosen { }; 36 37 clocks { 38 xo_board: xo-board { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 }; 47 48 bi_tcxo_div2: bi-tcxo-div2-clk { 49 compatible = "fixed-factor-clock"; 50 #clock-cells = <0>; 51 52 clocks = <&rpmhcc RPMH_CXO_CLK>; 53 clock-mult = <1>; 54 clock-div = <2>; 55 }; 56 57 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 58 compatible = "fixed-factor-clock"; 59 #clock-cells = <0>; 60 61 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 62 clock-mult = <1>; 63 clock-div = <2>; 64 }; 65 }; 66 67 cpus { 68 #address-cells = <2>; 69 #size-cells = <0>; 70 71 CPU0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a520"; 74 reg = <0 0>; 75 76 clocks = <&cpufreq_hw 0>; 77 78 power-domains = <&CPU_PD0>; 79 power-domain-names = "psci"; 80 81 enable-method = "psci"; 82 next-level-cache = <&L2_0>; 83 capacity-dmips-mhz = <1024>; 84 dynamic-power-coefficient = <100>; 85 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 88 #cooling-cells = <2>; 89 90 L2_0: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 next-level-cache = <&L3_0>; 95 96 L3_0: l3-cache { 97 compatible = "cache"; 98 cache-level = <3>; 99 cache-unified; 100 }; 101 }; 102 }; 103 104 CPU1: cpu@100 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a520"; 107 reg = <0 0x100>; 108 109 clocks = <&cpufreq_hw 0>; 110 111 power-domains = <&CPU_PD1>; 112 power-domain-names = "psci"; 113 114 enable-method = "psci"; 115 next-level-cache = <&L2_0>; 116 capacity-dmips-mhz = <1024>; 117 dynamic-power-coefficient = <100>; 118 119 qcom,freq-domain = <&cpufreq_hw 0>; 120 121 #cooling-cells = <2>; 122 }; 123 124 CPU2: cpu@200 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a720"; 127 reg = <0 0x200>; 128 129 clocks = <&cpufreq_hw 3>; 130 131 power-domains = <&CPU_PD2>; 132 power-domain-names = "psci"; 133 134 enable-method = "psci"; 135 next-level-cache = <&L2_200>; 136 capacity-dmips-mhz = <1792>; 137 dynamic-power-coefficient = <238>; 138 139 qcom,freq-domain = <&cpufreq_hw 3>; 140 141 #cooling-cells = <2>; 142 143 L2_200: l2-cache { 144 compatible = "cache"; 145 cache-level = <2>; 146 cache-unified; 147 next-level-cache = <&L3_0>; 148 }; 149 }; 150 151 CPU3: cpu@300 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a720"; 154 reg = <0 0x300>; 155 156 clocks = <&cpufreq_hw 3>; 157 158 power-domains = <&CPU_PD3>; 159 power-domain-names = "psci"; 160 161 enable-method = "psci"; 162 next-level-cache = <&L2_200>; 163 capacity-dmips-mhz = <1792>; 164 dynamic-power-coefficient = <238>; 165 166 qcom,freq-domain = <&cpufreq_hw 3>; 167 168 #cooling-cells = <2>; 169 }; 170 171 CPU4: cpu@400 { 172 device_type = "cpu"; 173 compatible = "arm,cortex-a720"; 174 reg = <0 0x400>; 175 176 clocks = <&cpufreq_hw 3>; 177 178 power-domains = <&CPU_PD4>; 179 power-domain-names = "psci"; 180 181 enable-method = "psci"; 182 next-level-cache = <&L2_400>; 183 capacity-dmips-mhz = <1792>; 184 dynamic-power-coefficient = <238>; 185 186 qcom,freq-domain = <&cpufreq_hw 3>; 187 188 #cooling-cells = <2>; 189 190 L2_400: l2-cache { 191 compatible = "cache"; 192 cache-level = <2>; 193 cache-unified; 194 next-level-cache = <&L3_0>; 195 }; 196 }; 197 198 CPU5: cpu@500 { 199 device_type = "cpu"; 200 compatible = "arm,cortex-a720"; 201 reg = <0 0x500>; 202 203 clocks = <&cpufreq_hw 1>; 204 205 power-domains = <&CPU_PD5>; 206 power-domain-names = "psci"; 207 208 enable-method = "psci"; 209 next-level-cache = <&L2_500>; 210 capacity-dmips-mhz = <1792>; 211 dynamic-power-coefficient = <238>; 212 213 qcom,freq-domain = <&cpufreq_hw 1>; 214 215 #cooling-cells = <2>; 216 217 L2_500: l2-cache { 218 compatible = "cache"; 219 cache-level = <2>; 220 cache-unified; 221 next-level-cache = <&L3_0>; 222 }; 223 }; 224 225 CPU6: cpu@600 { 226 device_type = "cpu"; 227 compatible = "arm,cortex-a720"; 228 reg = <0 0x600>; 229 230 clocks = <&cpufreq_hw 1>; 231 232 power-domains = <&CPU_PD6>; 233 power-domain-names = "psci"; 234 235 enable-method = "psci"; 236 next-level-cache = <&L2_600>; 237 capacity-dmips-mhz = <1792>; 238 dynamic-power-coefficient = <238>; 239 240 qcom,freq-domain = <&cpufreq_hw 1>; 241 242 #cooling-cells = <2>; 243 244 L2_600: l2-cache { 245 compatible = "cache"; 246 cache-level = <2>; 247 cache-unified; 248 next-level-cache = <&L3_0>; 249 }; 250 }; 251 252 CPU7: cpu@700 { 253 device_type = "cpu"; 254 compatible = "arm,cortex-x4"; 255 reg = <0 0x700>; 256 257 clocks = <&cpufreq_hw 2>; 258 259 power-domains = <&CPU_PD7>; 260 power-domain-names = "psci"; 261 262 enable-method = "psci"; 263 next-level-cache = <&L2_700>; 264 capacity-dmips-mhz = <1894>; 265 dynamic-power-coefficient = <588>; 266 267 qcom,freq-domain = <&cpufreq_hw 2>; 268 269 #cooling-cells = <2>; 270 271 L2_700: l2-cache { 272 compatible = "cache"; 273 cache-level = <2>; 274 cache-unified; 275 next-level-cache = <&L3_0>; 276 }; 277 }; 278 279 cpu-map { 280 cluster0 { 281 core0 { 282 cpu = <&CPU0>; 283 }; 284 285 core1 { 286 cpu = <&CPU1>; 287 }; 288 289 core2 { 290 cpu = <&CPU2>; 291 }; 292 293 core3 { 294 cpu = <&CPU3>; 295 }; 296 297 core4 { 298 cpu = <&CPU4>; 299 }; 300 301 core5 { 302 cpu = <&CPU5>; 303 }; 304 305 core6 { 306 cpu = <&CPU6>; 307 }; 308 309 core7 { 310 cpu = <&CPU7>; 311 }; 312 }; 313 }; 314 315 idle-states { 316 entry-method = "psci"; 317 318 SILVER_CPU_SLEEP_0: cpu-sleep-0-0 { 319 compatible = "arm,idle-state"; 320 idle-state-name = "silver-rail-power-collapse"; 321 arm,psci-suspend-param = <0x40000004>; 322 entry-latency-us = <550>; 323 exit-latency-us = <750>; 324 min-residency-us = <6700>; 325 local-timer-stop; 326 }; 327 328 GOLD_CPU_SLEEP_0: cpu-sleep-1-0 { 329 compatible = "arm,idle-state"; 330 idle-state-name = "gold-rail-power-collapse"; 331 arm,psci-suspend-param = <0x40000004>; 332 entry-latency-us = <600>; 333 exit-latency-us = <1300>; 334 min-residency-us = <8136>; 335 local-timer-stop; 336 }; 337 338 GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 { 339 compatible = "arm,idle-state"; 340 idle-state-name = "gold-plus-rail-power-collapse"; 341 arm,psci-suspend-param = <0x40000004>; 342 entry-latency-us = <500>; 343 exit-latency-us = <1350>; 344 min-residency-us = <7480>; 345 local-timer-stop; 346 }; 347 }; 348 349 domain-idle-states { 350 CLUSTER_SLEEP_0: cluster-sleep-0 { 351 compatible = "domain-idle-state"; 352 arm,psci-suspend-param = <0x41000044>; 353 entry-latency-us = <750>; 354 exit-latency-us = <2350>; 355 min-residency-us = <9144>; 356 }; 357 358 CLUSTER_SLEEP_1: cluster-sleep-1 { 359 compatible = "domain-idle-state"; 360 arm,psci-suspend-param = <0x4100c344>; 361 entry-latency-us = <2800>; 362 exit-latency-us = <4400>; 363 min-residency-us = <10150>; 364 }; 365 }; 366 }; 367 368 firmware { 369 scm: scm { 370 compatible = "qcom,scm-sm8650", "qcom,scm"; 371 qcom,dload-mode = <&tcsr 0x19000>; 372 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 373 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 374 }; 375 }; 376 377 clk_virt: interconnect-0 { 378 compatible = "qcom,sm8650-clk-virt"; 379 #interconnect-cells = <2>; 380 qcom,bcm-voters = <&apps_bcm_voter>; 381 }; 382 383 mc_virt: interconnect-1 { 384 compatible = "qcom,sm8650-mc-virt"; 385 #interconnect-cells = <2>; 386 qcom,bcm-voters = <&apps_bcm_voter>; 387 }; 388 389 memory@a0000000 { 390 device_type = "memory"; 391 /* We expect the bootloader to fill in the size */ 392 reg = <0 0xa0000000 0 0>; 393 }; 394 395 pmu-a520 { 396 compatible = "arm,cortex-a520-pmu"; 397 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 398 }; 399 400 pmu-a720 { 401 compatible = "arm,cortex-a720-pmu"; 402 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 403 }; 404 405 pmu-x4 { 406 compatible = "arm,cortex-x4-pmu"; 407 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 408 }; 409 410 psci { 411 compatible = "arm,psci-1.0"; 412 method = "smc"; 413 414 CPU_PD0: power-domain-cpu0 { 415 #power-domain-cells = <0>; 416 power-domains = <&CLUSTER_PD>; 417 domain-idle-states = <&SILVER_CPU_SLEEP_0>; 418 }; 419 420 CPU_PD1: power-domain-cpu1 { 421 #power-domain-cells = <0>; 422 power-domains = <&CLUSTER_PD>; 423 domain-idle-states = <&SILVER_CPU_SLEEP_0>; 424 }; 425 426 CPU_PD2: power-domain-cpu2 { 427 #power-domain-cells = <0>; 428 power-domains = <&CLUSTER_PD>; 429 domain-idle-states = <&SILVER_CPU_SLEEP_0>; 430 }; 431 432 CPU_PD3: power-domain-cpu3 { 433 #power-domain-cells = <0>; 434 power-domains = <&CLUSTER_PD>; 435 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 436 }; 437 438 CPU_PD4: power-domain-cpu4 { 439 #power-domain-cells = <0>; 440 power-domains = <&CLUSTER_PD>; 441 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 442 }; 443 444 CPU_PD5: power-domain-cpu5 { 445 #power-domain-cells = <0>; 446 power-domains = <&CLUSTER_PD>; 447 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 448 }; 449 450 CPU_PD6: power-domain-cpu6 { 451 #power-domain-cells = <0>; 452 power-domains = <&CLUSTER_PD>; 453 domain-idle-states = <&GOLD_CPU_SLEEP_0>; 454 }; 455 456 CPU_PD7: power-domain-cpu7 { 457 #power-domain-cells = <0>; 458 power-domains = <&CLUSTER_PD>; 459 domain-idle-states = <&GOLD_PLUS_CPU_SLEEP_0>; 460 }; 461 462 CLUSTER_PD: power-domain-cluster { 463 #power-domain-cells = <0>; 464 domain-idle-states = <&CLUSTER_SLEEP_0>, 465 <&CLUSTER_SLEEP_1>; 466 }; 467 }; 468 469 reserved_memory: reserved-memory { 470 #address-cells = <2>; 471 #size-cells = <2>; 472 ranges; 473 474 hyp_mem: hyp@80000000 { 475 reg = <0 0x80000000 0 0xe00000>; 476 no-map; 477 }; 478 479 cpusys_vm_mem: cpusys-vm@80e00000 { 480 reg = <0 0x80e00000 0 0x400000>; 481 no-map; 482 }; 483 484 /* Merged xbl_dtlog, xbl_ramdump and aop_image regions */ 485 xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 { 486 reg = <0 0x81a00000 0 0x260000>; 487 no-map; 488 }; 489 490 aop_cmd_db_mem: aop-cmd-db@81c60000 { 491 compatible = "qcom,cmd-db"; 492 reg = <0 0x81c60000 0 0x20000>; 493 no-map; 494 }; 495 496 /* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */ 497 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 498 reg = <0 0x81c80000 0 0x75000>; 499 no-map; 500 }; 501 502 /* Secdata region can be reused by apps */ 503 504 smem: smem@81d00000 { 505 compatible = "qcom,smem"; 506 reg = <0 0x81d00000 0 0x200000>; 507 hwlocks = <&tcsr_mutex 3>; 508 no-map; 509 }; 510 511 adsp_mhi_mem: adsp-mhi@81f00000 { 512 reg = <0 0x81f00000 0 0x20000>; 513 no-map; 514 }; 515 516 pvmfw_mem: pvmfw@824a0000 { 517 reg = <0 0x824a0000 0 0x100000>; 518 no-map; 519 }; 520 521 global_sync_mem: global-sync@82600000 { 522 reg = <0 0x82600000 0 0x100000>; 523 no-map; 524 }; 525 526 tz_stat_mem: tz-stat@82700000 { 527 reg = <0 0x82700000 0 0x100000>; 528 no-map; 529 }; 530 531 qdss_mem: qdss@82800000 { 532 reg = <0 0x82800000 0 0x2000000>; 533 no-map; 534 }; 535 536 qlink_logging_mem: qlink-logging@84800000 { 537 reg = <0 0x84800000 0 0x200000>; 538 no-map; 539 }; 540 541 mpss_dsm_mem: mpss-dsm@86b00000 { 542 reg = <0 0x86b00000 0 0x4900000>; 543 no-map; 544 }; 545 546 mpss_dsm_mem_2: mpss-dsm-2@8b400000 { 547 reg = <0 0x8b400000 0 0x800000>; 548 no-map; 549 }; 550 551 mpss_mem: mpss@8bc00000 { 552 reg = <0 0x8bc00000 0 0xf400000>; 553 no-map; 554 }; 555 556 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { 557 reg = <0 0x9b000000 0 0x80000>; 558 no-map; 559 }; 560 561 ipa_fw_mem: ipa-fw@9b080000 { 562 reg = <0 0x9b080000 0 0x10000>; 563 no-map; 564 }; 565 566 ipa_gsi_mem: ipa-gsi@9b090000 { 567 reg = <0 0x9b090000 0 0xa000>; 568 no-map; 569 }; 570 571 gpu_micro_code_mem: gpu-micro-code@9b09a000 { 572 reg = <0 0x9b09a000 0 0x2000>; 573 no-map; 574 }; 575 576 spss_region_mem: spss@9b0a0000 { 577 reg = <0 0x9b0a0000 0 0x1e0000>; 578 no-map; 579 }; 580 581 /* First part of the "SPU secure shared memory" region */ 582 spu_tz_shared_mem: spu-tz-shared@9b280000 { 583 reg = <0 0x9b280000 0 0x60000>; 584 no-map; 585 }; 586 587 /* Second part of the "SPU secure shared memory" region */ 588 spu_modem_shared_mem: spu-modem-shared@9b2e0000 { 589 reg = <0 0x9b2e0000 0 0x20000>; 590 no-map; 591 }; 592 593 camera_mem: camera@9b300000 { 594 reg = <0 0x9b300000 0 0x800000>; 595 no-map; 596 }; 597 598 video_mem: video@9bb00000 { 599 reg = <0 0x9bb00000 0 0x800000>; 600 no-map; 601 }; 602 603 cvp_mem: cvp@9c300000 { 604 reg = <0 0x9c300000 0 0x700000>; 605 no-map; 606 }; 607 608 cdsp_mem: cdsp@9ca00000 { 609 reg = <0 0x9ca00000 0 0x1400000>; 610 no-map; 611 }; 612 613 q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 { 614 reg = <0 0x9de00000 0 0x80000>; 615 no-map; 616 }; 617 618 q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 { 619 reg = <0 0x9de80000 0 0x80000>; 620 no-map; 621 }; 622 623 adspslpi_mem: adspslpi@9df00000 { 624 reg = <0 0x9df00000 0 0x4080000>; 625 no-map; 626 }; 627 628 rmtfs_mem: rmtfs@d7c00000 { 629 compatible = "qcom,rmtfs-mem"; 630 reg = <0 0xd7c00000 0 0x400000>; 631 no-map; 632 633 qcom,client-id = <1>; 634 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 635 }; 636 637 /* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */ 638 tz_merged_mem: tz-merged@d8000000 { 639 reg = <0 0xd8000000 0 0x800000>; 640 no-map; 641 }; 642 643 hwfence_shbuf: hwfence-shbuf@e6440000 { 644 reg = <0 0xe6440000 0 0x2dd000>; 645 no-map; 646 }; 647 648 trust_ui_vm_mem: trust-ui-vm@f3800000 { 649 reg = <0 0xf3800000 0 0x4400000>; 650 no-map; 651 }; 652 653 oem_vm_mem: oem-vm@f7c00000 { 654 reg = <0 0xf7c00000 0 0x4c00000>; 655 no-map; 656 }; 657 658 llcc_lpi_mem: llcc-lpi@ff800000 { 659 reg = <0 0xff800000 0 0x600000>; 660 no-map; 661 }; 662 }; 663 664 smp2p-adsp { 665 compatible = "qcom,smp2p"; 666 667 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 668 IPCC_MPROC_SIGNAL_SMP2P 669 IRQ_TYPE_EDGE_RISING>; 670 671 mboxes = <&ipcc IPCC_CLIENT_LPASS 672 IPCC_MPROC_SIGNAL_SMP2P>; 673 674 qcom,smem = <443>, <429>; 675 qcom,local-pid = <0>; 676 qcom,remote-pid = <2>; 677 678 smp2p_adsp_out: master-kernel { 679 qcom,entry-name = "master-kernel"; 680 #qcom,smem-state-cells = <1>; 681 }; 682 683 smp2p_adsp_in: slave-kernel { 684 qcom,entry-name = "slave-kernel"; 685 interrupt-controller; 686 #interrupt-cells = <2>; 687 }; 688 }; 689 690 smp2p-cdsp { 691 compatible = "qcom,smp2p"; 692 693 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 694 IPCC_MPROC_SIGNAL_SMP2P 695 IRQ_TYPE_EDGE_RISING>; 696 697 mboxes = <&ipcc IPCC_CLIENT_CDSP 698 IPCC_MPROC_SIGNAL_SMP2P>; 699 700 qcom,smem = <94>, <432>; 701 qcom,local-pid = <0>; 702 qcom,remote-pid = <5>; 703 704 smp2p_cdsp_out: master-kernel { 705 qcom,entry-name = "master-kernel"; 706 #qcom,smem-state-cells = <1>; 707 }; 708 709 smp2p_cdsp_in: slave-kernel { 710 qcom,entry-name = "slave-kernel"; 711 interrupt-controller; 712 #interrupt-cells = <2>; 713 }; 714 }; 715 716 smp2p-modem { 717 compatible = "qcom,smp2p"; 718 719 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 720 IPCC_MPROC_SIGNAL_SMP2P 721 IRQ_TYPE_EDGE_RISING>; 722 723 mboxes = <&ipcc IPCC_CLIENT_MPSS 724 IPCC_MPROC_SIGNAL_SMP2P>; 725 726 qcom,smem = <435>, <428>; 727 qcom,local-pid = <0>; 728 qcom,remote-pid = <1>; 729 730 smp2p_modem_out: master-kernel { 731 qcom,entry-name = "master-kernel"; 732 #qcom,smem-state-cells = <1>; 733 }; 734 735 smp2p_modem_in: slave-kernel { 736 qcom,entry-name = "slave-kernel"; 737 interrupt-controller; 738 #interrupt-cells = <2>; 739 }; 740 741 ipa_smp2p_out: ipa-ap-to-modem { 742 qcom,entry-name = "ipa"; 743 #qcom,smem-state-cells = <1>; 744 }; 745 746 ipa_smp2p_in: ipa-modem-to-ap { 747 qcom,entry-name = "ipa"; 748 interrupt-controller; 749 #interrupt-cells = <2>; 750 }; 751 }; 752 753 soc: soc@0 { 754 compatible = "simple-bus"; 755 756 #address-cells = <2>; 757 #size-cells = <2>; 758 dma-ranges = <0 0 0 0 0x10 0>; 759 ranges = <0 0 0 0 0x10 0>; 760 761 gcc: clock-controller@100000 { 762 compatible = "qcom,sm8650-gcc"; 763 reg = <0 0x00100000 0 0x1f4200>; 764 765 clocks = <&bi_tcxo_div2>, 766 <&bi_tcxo_ao_div2>, 767 <&sleep_clk>, 768 <&pcie0_phy>, 769 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 770 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 771 <&ufs_mem_phy 0>, 772 <&ufs_mem_phy 1>, 773 <&ufs_mem_phy 2>, 774 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 775 776 #clock-cells = <1>; 777 #reset-cells = <1>; 778 #power-domain-cells = <1>; 779 }; 780 781 ipcc: mailbox@406000 { 782 compatible = "qcom,sm8650-ipcc", "qcom,ipcc"; 783 reg = <0 0x00406000 0 0x1000>; 784 785 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 786 interrupt-controller; 787 #interrupt-cells = <3>; 788 789 #mbox-cells = <2>; 790 }; 791 792 gpi_dma2: dma-controller@800000 { 793 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 794 reg = <0 0x00800000 0 0x60000>; 795 796 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 808 809 dma-channels = <12>; 810 dma-channel-mask = <0x3f>; 811 #dma-cells = <3>; 812 813 iommus = <&apps_smmu 0x436 0>; 814 815 dma-coherent; 816 817 status = "disabled"; 818 }; 819 820 qupv3_id_1: geniqup@8c0000 { 821 compatible = "qcom,geni-se-qup"; 822 reg = <0 0x008c0000 0 0x2000>; 823 824 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 825 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 826 clock-names = "m-ahb", 827 "s-ahb"; 828 829 iommus = <&apps_smmu 0x423 0>; 830 831 dma-coherent; 832 833 #address-cells = <2>; 834 #size-cells = <2>; 835 ranges; 836 837 status = "disabled"; 838 839 i2c8: i2c@880000 { 840 compatible = "qcom,geni-i2c"; 841 reg = <0 0x00880000 0 0x4000>; 842 843 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 844 845 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 846 clock-names = "se"; 847 848 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 849 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 850 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 851 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 852 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 853 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 854 interconnect-names = "qup-core", 855 "qup-config", 856 "qup-memory"; 857 858 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 859 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 860 dma-names = "tx", 861 "rx"; 862 863 pinctrl-0 = <&qup_i2c8_data_clk>; 864 pinctrl-names = "default"; 865 866 #address-cells = <1>; 867 #size-cells = <0>; 868 869 status = "disabled"; 870 }; 871 872 spi8: spi@880000 { 873 compatible = "qcom,geni-spi"; 874 reg = <0 0x00880000 0 0x4000>; 875 876 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 877 878 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 879 clock-names = "se"; 880 881 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 882 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 883 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 884 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 885 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 886 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 887 interconnect-names = "qup-core", 888 "qup-config", 889 "qup-memory"; 890 891 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 892 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 893 dma-names = "tx", 894 "rx"; 895 896 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 897 pinctrl-names = "default"; 898 899 #address-cells = <1>; 900 #size-cells = <0>; 901 902 status = "disabled"; 903 }; 904 905 i2c9: i2c@884000 { 906 compatible = "qcom,geni-i2c"; 907 reg = <0 0x00884000 0 0x4000>; 908 909 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 910 911 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 912 clock-names = "se"; 913 914 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 915 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 916 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 917 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 918 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 919 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 920 interconnect-names = "qup-core", 921 "qup-config", 922 "qup-memory"; 923 924 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 925 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 926 dma-names = "tx", 927 "rx"; 928 929 pinctrl-0 = <&qup_i2c9_data_clk>; 930 pinctrl-names = "default"; 931 932 #address-cells = <1>; 933 #size-cells = <0>; 934 935 status = "disabled"; 936 }; 937 938 spi9: spi@884000 { 939 compatible = "qcom,geni-spi"; 940 reg = <0 0x00884000 0 0x4000>; 941 942 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 943 944 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 945 clock-names = "se"; 946 947 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 948 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 949 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 950 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 951 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 952 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 953 interconnect-names = "qup-core", 954 "qup-config", 955 "qup-memory"; 956 957 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 958 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 959 dma-names = "tx", 960 "rx"; 961 962 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 963 pinctrl-names = "default"; 964 965 #address-cells = <1>; 966 #size-cells = <0>; 967 968 status = "disabled"; 969 }; 970 971 i2c10: i2c@888000 { 972 compatible = "qcom,geni-i2c"; 973 reg = <0 0x00888000 0 0x4000>; 974 975 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 976 977 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 978 clock-names = "se"; 979 980 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 981 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 982 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 983 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 984 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 985 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 986 interconnect-names = "qup-core", 987 "qup-config", 988 "qup-memory"; 989 990 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 991 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 992 dma-names = "tx", 993 "rx"; 994 995 pinctrl-0 = <&qup_i2c10_data_clk>; 996 pinctrl-names = "default"; 997 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 1001 status = "disabled"; 1002 }; 1003 1004 spi10: spi@888000 { 1005 compatible = "qcom,geni-spi"; 1006 reg = <0 0x00888000 0 0x4000>; 1007 1008 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1009 1010 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1011 clock-names = "se"; 1012 1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1014 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1015 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1016 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1017 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1018 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1019 interconnect-names = "qup-core", 1020 "qup-config", 1021 "qup-memory"; 1022 1023 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1024 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1025 dma-names = "tx", 1026 "rx"; 1027 1028 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1029 pinctrl-names = "default"; 1030 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 1034 status = "disabled"; 1035 }; 1036 1037 i2c11: i2c@88c000 { 1038 compatible = "qcom,geni-i2c"; 1039 reg = <0 0x0088c000 0 0x4000>; 1040 1041 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1042 1043 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1044 clock-names = "se"; 1045 1046 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1047 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1048 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1049 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1050 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1051 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1052 interconnect-names = "qup-core", 1053 "qup-config", 1054 "qup-memory"; 1055 1056 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1057 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1058 dma-names = "tx", 1059 "rx"; 1060 1061 pinctrl-0 = <&qup_i2c11_data_clk>; 1062 pinctrl-names = "default"; 1063 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 1067 status = "disabled"; 1068 }; 1069 1070 spi11: spi@88c000 { 1071 compatible = "qcom,geni-spi"; 1072 reg = <0 0x0088c000 0 0x4000>; 1073 1074 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1075 1076 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1077 clock-names = "se"; 1078 1079 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1080 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1081 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1082 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1083 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1084 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1085 interconnect-names = "qup-core", 1086 "qup-config", 1087 "qup-memory"; 1088 1089 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1090 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1091 dma-names = "tx", 1092 "rx"; 1093 1094 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1095 pinctrl-names = "default"; 1096 1097 #address-cells = <1>; 1098 #size-cells = <0>; 1099 1100 status = "disabled"; 1101 }; 1102 1103 i2c12: i2c@890000 { 1104 compatible = "qcom,geni-i2c"; 1105 reg = <0 0x00890000 0 0x4000>; 1106 1107 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1108 1109 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1110 clock-names = "se"; 1111 1112 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1113 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1114 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1115 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1116 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1117 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1118 interconnect-names = "qup-core", 1119 "qup-config", 1120 "qup-memory"; 1121 1122 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1123 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1124 dma-names = "tx", 1125 "rx"; 1126 1127 pinctrl-0 = <&qup_i2c12_data_clk>; 1128 pinctrl-names = "default"; 1129 1130 #address-cells = <1>; 1131 #size-cells = <0>; 1132 1133 status = "disabled"; 1134 }; 1135 1136 spi12: spi@890000 { 1137 compatible = "qcom,geni-spi"; 1138 reg = <0 0x00890000 0 0x4000>; 1139 1140 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1141 1142 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1143 clock-names = "se"; 1144 1145 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1146 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1147 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1148 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1149 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1150 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1151 interconnect-names = "qup-core", 1152 "qup-config", 1153 "qup-memory"; 1154 1155 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1156 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1157 dma-names = "tx", 1158 "rx"; 1159 1160 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1161 pinctrl-names = "default"; 1162 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 1166 status = "disabled"; 1167 }; 1168 1169 i2c13: i2c@894000 { 1170 compatible = "qcom,geni-i2c"; 1171 reg = <0 0x00894000 0 0x4000>; 1172 1173 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1174 1175 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1176 clock-names = "se"; 1177 1178 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1179 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1180 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1181 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1182 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1183 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1184 interconnect-names = "qup-core", 1185 "qup-config", 1186 "qup-memory"; 1187 1188 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1189 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1190 dma-names = "tx", 1191 "rx"; 1192 1193 pinctrl-0 = <&qup_i2c13_data_clk>; 1194 pinctrl-names = "default"; 1195 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 1199 status = "disabled"; 1200 }; 1201 1202 spi13: spi@894000 { 1203 compatible = "qcom,geni-spi"; 1204 reg = <0 0x00894000 0 0x4000>; 1205 1206 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1207 1208 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1209 clock-names = "se"; 1210 1211 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1212 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1213 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1214 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1215 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1216 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1217 interconnect-names = "qup-core", 1218 "qup-config", 1219 "qup-memory"; 1220 1221 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1222 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1223 dma-names = "tx", 1224 "rx"; 1225 1226 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1227 pinctrl-names = "default"; 1228 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 1232 status = "disabled"; 1233 }; 1234 1235 uart14: serial@898000 { 1236 compatible = "qcom,geni-uart"; 1237 reg = <0 0x00898000 0 0x4000>; 1238 1239 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1240 1241 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1242 clock-names = "se"; 1243 1244 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1245 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1246 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1247 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1248 interconnect-names = "qup-core", 1249 "qup-config"; 1250 1251 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1252 pinctrl-names = "default"; 1253 1254 status = "disabled"; 1255 }; 1256 1257 uart15: serial@89c000 { 1258 compatible = "qcom,geni-debug-uart"; 1259 reg = <0 0x0089c000 0 0x4000>; 1260 1261 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1262 1263 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1264 clock-names = "se"; 1265 1266 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1267 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1268 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1269 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1270 interconnect-names = "qup-core", 1271 "qup-config"; 1272 1273 pinctrl-0 = <&qup_uart15_default>; 1274 pinctrl-names = "default"; 1275 1276 status = "disabled"; 1277 }; 1278 }; 1279 1280 i2c_master_hub_0: geniqup@9c0000 { 1281 compatible = "qcom,geni-se-i2c-master-hub"; 1282 reg = <0 0x009c0000 0 0x2000>; 1283 1284 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1285 clock-names = "s-ahb"; 1286 1287 #address-cells = <2>; 1288 #size-cells = <2>; 1289 ranges; 1290 1291 status = "disabled"; 1292 1293 i2c_hub_0: i2c@980000 { 1294 compatible = "qcom,geni-i2c-master-hub"; 1295 reg = <0 0x00980000 0 0x4000>; 1296 1297 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1298 1299 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1300 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1301 clock-names = "se", 1302 "core"; 1303 1304 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1305 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1306 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1307 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1308 interconnect-names = "qup-core", 1309 "qup-config"; 1310 1311 pinctrl-0 = <&hub_i2c0_data_clk>; 1312 pinctrl-names = "default"; 1313 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 1317 status = "disabled"; 1318 }; 1319 1320 i2c_hub_1: i2c@984000 { 1321 compatible = "qcom,geni-i2c-master-hub"; 1322 reg = <0 0x00984000 0 0x4000>; 1323 1324 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1325 1326 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1327 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1328 clock-names = "se", 1329 "core"; 1330 1331 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1332 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1333 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1334 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1335 interconnect-names = "qup-core", 1336 "qup-config"; 1337 1338 pinctrl-0 = <&hub_i2c1_data_clk>; 1339 pinctrl-names = "default"; 1340 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 1344 status = "disabled"; 1345 }; 1346 1347 i2c_hub_2: i2c@988000 { 1348 compatible = "qcom,geni-i2c-master-hub"; 1349 reg = <0 0x00988000 0 0x4000>; 1350 1351 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1352 1353 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1354 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1355 clock-names = "se", 1356 "core"; 1357 1358 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1359 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1360 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1361 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1362 interconnect-names = "qup-core", 1363 "qup-config"; 1364 1365 pinctrl-0 = <&hub_i2c2_data_clk>; 1366 pinctrl-names = "default"; 1367 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 1371 status = "disabled"; 1372 }; 1373 1374 i2c_hub_3: i2c@98c000 { 1375 compatible = "qcom,geni-i2c-master-hub"; 1376 reg = <0 0x0098c000 0 0x4000>; 1377 1378 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1379 1380 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1381 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1382 clock-names = "se", 1383 "core"; 1384 1385 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1386 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1387 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1388 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1389 interconnect-names = "qup-core", 1390 "qup-config"; 1391 1392 pinctrl-0 = <&hub_i2c3_data_clk>; 1393 pinctrl-names = "default"; 1394 1395 #address-cells = <1>; 1396 #size-cells = <0>; 1397 1398 status = "disabled"; 1399 }; 1400 1401 i2c_hub_4: i2c@990000 { 1402 compatible = "qcom,geni-i2c-master-hub"; 1403 reg = <0 0x00990000 0 0x4000>; 1404 1405 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1406 1407 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1408 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1409 clock-names = "se", 1410 "core"; 1411 1412 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1413 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1414 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1415 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1416 interconnect-names = "qup-core", 1417 "qup-config"; 1418 1419 pinctrl-0 = <&hub_i2c4_data_clk>; 1420 pinctrl-names = "default"; 1421 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 1425 status = "disabled"; 1426 }; 1427 1428 i2c_hub_5: i2c@994000 { 1429 compatible = "qcom,geni-i2c-master-hub"; 1430 reg = <0 0x00994000 0 0x4000>; 1431 1432 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1433 1434 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1435 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1436 clock-names = "se", 1437 "core"; 1438 1439 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1440 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1441 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1442 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1443 interconnect-names = "qup-core", 1444 "qup-config"; 1445 1446 pinctrl-0 = <&hub_i2c5_data_clk>; 1447 pinctrl-names = "default"; 1448 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 1452 status = "disabled"; 1453 }; 1454 1455 i2c_hub_6: i2c@998000 { 1456 compatible = "qcom,geni-i2c-master-hub"; 1457 reg = <0 0x00998000 0 0x4000>; 1458 1459 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1460 1461 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1462 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1463 clock-names = "se", 1464 "core"; 1465 1466 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1467 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1468 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1469 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1470 interconnect-names = "qup-core", 1471 "qup-config"; 1472 1473 pinctrl-0 = <&hub_i2c6_data_clk>; 1474 pinctrl-names = "default"; 1475 1476 #address-cells = <1>; 1477 #size-cells = <0>; 1478 1479 status = "disabled"; 1480 }; 1481 1482 i2c_hub_7: i2c@99c000 { 1483 compatible = "qcom,geni-i2c-master-hub"; 1484 reg = <0 0x0099c000 0 0x4000>; 1485 1486 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1487 1488 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1489 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1490 clock-names = "se", 1491 "core"; 1492 1493 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1494 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1495 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1496 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1497 interconnect-names = "qup-core", 1498 "qup-config"; 1499 1500 pinctrl-0 = <&hub_i2c7_data_clk>; 1501 pinctrl-names = "default"; 1502 1503 #address-cells = <1>; 1504 #size-cells = <0>; 1505 1506 status = "disabled"; 1507 }; 1508 1509 i2c_hub_8: i2c@9a0000 { 1510 compatible = "qcom,geni-i2c-master-hub"; 1511 reg = <0 0x009a0000 0 0x4000>; 1512 1513 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1514 1515 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1516 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1517 clock-names = "se", 1518 "core"; 1519 1520 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1521 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1522 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1523 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1524 interconnect-names = "qup-core", 1525 "qup-config"; 1526 1527 pinctrl-0 = <&hub_i2c8_data_clk>; 1528 pinctrl-names = "default"; 1529 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 1533 status = "disabled"; 1534 }; 1535 1536 i2c_hub_9: i2c@9a4000 { 1537 compatible = "qcom,geni-i2c-master-hub"; 1538 reg = <0 0x009a4000 0 0x4000>; 1539 1540 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1541 1542 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1543 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1544 clock-names = "se", 1545 "core"; 1546 1547 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1548 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1549 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1550 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1551 interconnect-names = "qup-core", 1552 "qup-config"; 1553 1554 pinctrl-0 = <&hub_i2c9_data_clk>; 1555 pinctrl-names = "default"; 1556 1557 #address-cells = <1>; 1558 #size-cells = <0>; 1559 1560 status = "disabled"; 1561 }; 1562 }; 1563 1564 gpi_dma1: dma-controller@a00000 { 1565 compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; 1566 reg = <0 0x00a00000 0 0x60000>; 1567 1568 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1580 1581 dma-channels = <12>; 1582 dma-channel-mask = <0xc>; 1583 #dma-cells = <3>; 1584 1585 iommus = <&apps_smmu 0xb6 0>; 1586 dma-coherent; 1587 1588 status = "disabled"; 1589 }; 1590 1591 qupv3_id_0: geniqup@ac0000 { 1592 compatible = "qcom,geni-se-qup"; 1593 reg = <0 0x00ac0000 0 0x2000>; 1594 1595 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1596 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1597 clock-names = "m-ahb", 1598 "s-ahb"; 1599 1600 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1601 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 1602 interconnect-names = "qup-core"; 1603 1604 iommus = <&apps_smmu 0xa3 0>; 1605 1606 dma-coherent; 1607 1608 #address-cells = <2>; 1609 #size-cells = <2>; 1610 ranges; 1611 1612 status = "disabled"; 1613 1614 i2c0: i2c@a80000 { 1615 compatible = "qcom,geni-i2c"; 1616 reg = <0 0x00a80000 0 0x4000>; 1617 1618 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1619 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1621 clock-names = "se"; 1622 1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1624 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1625 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1626 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1627 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1628 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1629 interconnect-names = "qup-core", 1630 "qup-config", 1631 "qup-memory"; 1632 1633 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1634 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1635 dma-names = "tx", 1636 "rx"; 1637 1638 pinctrl-0 = <&qup_i2c0_data_clk>; 1639 pinctrl-names = "default"; 1640 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 1644 status = "disabled"; 1645 }; 1646 1647 spi0: spi@a80000 { 1648 compatible = "qcom,geni-spi"; 1649 reg = <0 0x00a80000 0 0x4000>; 1650 1651 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1652 1653 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1654 clock-names = "se"; 1655 1656 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1657 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1658 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1659 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1660 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1661 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1662 interconnect-names = "qup-core", 1663 "qup-config", 1664 "qup-memory"; 1665 1666 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1667 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1668 dma-names = "tx", 1669 "rx"; 1670 1671 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1672 pinctrl-names = "default"; 1673 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 1677 status = "disabled"; 1678 }; 1679 1680 i2c1: i2c@a84000 { 1681 compatible = "qcom,geni-i2c"; 1682 reg = <0 0x00a84000 0 0x4000>; 1683 1684 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1685 1686 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1687 clock-names = "se"; 1688 1689 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1690 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1691 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1692 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1693 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1694 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1695 interconnect-names = "qup-core", 1696 "qup-config", 1697 "qup-memory"; 1698 1699 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1700 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1701 dma-names = "tx", 1702 "rx"; 1703 1704 pinctrl-0 = <&qup_i2c1_data_clk>; 1705 pinctrl-names = "default"; 1706 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 1710 status = "disabled"; 1711 }; 1712 1713 spi1: spi@a84000 { 1714 compatible = "qcom,geni-spi"; 1715 reg = <0 0x00a84000 0 0x4000>; 1716 1717 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1718 1719 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1720 clock-names = "se"; 1721 1722 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1723 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1724 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1725 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1726 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1727 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1728 interconnect-names = "qup-core", 1729 "qup-config", 1730 "qup-memory"; 1731 1732 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1733 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1734 dma-names = "tx", 1735 "rx"; 1736 1737 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1738 pinctrl-names = "default"; 1739 1740 #address-cells = <1>; 1741 #size-cells = <0>; 1742 1743 status = "disabled"; 1744 }; 1745 1746 i2c2: i2c@a88000 { 1747 compatible = "qcom,geni-i2c"; 1748 reg = <0 0x00a88000 0 0x4000>; 1749 1750 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1751 1752 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1753 clock-names = "se"; 1754 1755 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1756 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1757 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1758 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1759 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1760 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1761 interconnect-names = "qup-core", 1762 "qup-config", 1763 "qup-memory"; 1764 1765 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1766 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1767 dma-names = "tx", 1768 "rx"; 1769 1770 pinctrl-0 = <&qup_i2c2_data_clk>; 1771 pinctrl-names = "default"; 1772 1773 #address-cells = <1>; 1774 #size-cells = <0>; 1775 1776 status = "disabled"; 1777 }; 1778 1779 spi2: spi@a88000 { 1780 compatible = "qcom,geni-spi"; 1781 reg = <0 0x00a88000 0 0x4000>; 1782 1783 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1784 1785 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1786 clock-names = "se"; 1787 1788 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1789 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1790 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1791 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1792 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1793 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1794 interconnect-names = "qup-core", 1795 "qup-config", 1796 "qup-memory"; 1797 1798 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1799 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1800 dma-names = "tx", 1801 "rx"; 1802 1803 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1804 pinctrl-names = "default"; 1805 1806 #address-cells = <1>; 1807 #size-cells = <0>; 1808 1809 status = "disabled"; 1810 }; 1811 1812 i2c3: i2c@a8c000 { 1813 compatible = "qcom,geni-i2c"; 1814 reg = <0 0x00a8c000 0 0x4000>; 1815 1816 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1817 1818 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1819 clock-names = "se"; 1820 1821 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1822 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1823 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1824 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1825 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1826 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1827 interconnect-names = "qup-core", 1828 "qup-config", 1829 "qup-memory"; 1830 1831 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1832 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1833 dma-names = "tx", 1834 "rx"; 1835 1836 pinctrl-0 = <&qup_i2c3_data_clk>; 1837 pinctrl-names = "default"; 1838 1839 #address-cells = <1>; 1840 #size-cells = <0>; 1841 1842 status = "disabled"; 1843 }; 1844 1845 spi3: spi@a8c000 { 1846 compatible = "qcom,geni-spi"; 1847 reg = <0 0x00a8c000 0 0x4000>; 1848 1849 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1850 1851 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1852 clock-names = "se"; 1853 1854 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1855 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1856 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1857 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1858 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1859 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1860 interconnect-names = "qup-core", 1861 "qup-config", 1862 "qup-memory"; 1863 1864 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1865 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1866 dma-names = "tx", 1867 "rx"; 1868 1869 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1870 pinctrl-names = "default"; 1871 1872 #address-cells = <1>; 1873 #size-cells = <0>; 1874 1875 status = "disabled"; 1876 }; 1877 1878 i2c4: i2c@a90000 { 1879 compatible = "qcom,geni-i2c"; 1880 reg = <0 0x00a90000 0 0x4000>; 1881 1882 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1883 1884 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1885 clock-names = "se"; 1886 1887 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1888 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1889 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1890 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1891 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1892 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1893 interconnect-names = "qup-core", 1894 "qup-config", 1895 "qup-memory"; 1896 1897 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1898 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1899 dma-names = "tx", 1900 "rx"; 1901 1902 pinctrl-0 = <&qup_i2c4_data_clk>; 1903 pinctrl-names = "default"; 1904 1905 #address-cells = <1>; 1906 #size-cells = <0>; 1907 1908 status = "disabled"; 1909 }; 1910 1911 spi4: spi@a90000 { 1912 compatible = "qcom,geni-spi"; 1913 reg = <0 0x00a90000 0 0x4000>; 1914 1915 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1916 1917 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1918 clock-names = "se"; 1919 1920 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1921 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1922 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1923 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1924 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1925 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1926 interconnect-names = "qup-core", 1927 "qup-config", 1928 "qup-memory"; 1929 1930 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1931 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1932 dma-names = "tx", 1933 "rx"; 1934 1935 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1936 pinctrl-names = "default"; 1937 1938 #address-cells = <1>; 1939 #size-cells = <0>; 1940 1941 status = "disabled"; 1942 }; 1943 1944 i2c5: i2c@a94000 { 1945 compatible = "qcom,geni-i2c"; 1946 reg = <0 0x00a94000 0 0x4000>; 1947 1948 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1949 1950 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1951 clock-names = "se"; 1952 1953 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1954 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1955 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1956 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1957 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1958 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1959 interconnect-names = "qup-core", 1960 "qup-config", 1961 "qup-memory"; 1962 1963 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1964 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1965 dma-names = "tx", 1966 "rx"; 1967 1968 pinctrl-0 = <&qup_i2c5_data_clk>; 1969 pinctrl-names = "default"; 1970 1971 #address-cells = <1>; 1972 #size-cells = <0>; 1973 1974 status = "disabled"; 1975 }; 1976 1977 spi5: spi@a94000 { 1978 compatible = "qcom,geni-spi"; 1979 reg = <0 0x00a94000 0 0x4000>; 1980 1981 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1982 1983 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1984 clock-names = "se"; 1985 1986 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1987 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1988 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1989 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1990 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1991 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1992 interconnect-names = "qup-core", 1993 "qup-config", 1994 "qup-memory"; 1995 1996 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1997 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1998 dma-names = "tx", 1999 "rx"; 2000 2001 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2002 pinctrl-names = "default"; 2003 2004 #address-cells = <1>; 2005 #size-cells = <0>; 2006 2007 status = "disabled"; 2008 }; 2009 2010 i2c6: i2c@a98000 { 2011 compatible = "qcom,geni-i2c"; 2012 reg = <0 0x00a98000 0 0x4000>; 2013 2014 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 2015 2016 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2017 clock-names = "se"; 2018 2019 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2020 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2021 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2022 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2023 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2024 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2025 interconnect-names = "qup-core", 2026 "qup-config", 2027 "qup-memory"; 2028 2029 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2030 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2031 dma-names = "tx", 2032 "rx"; 2033 2034 pinctrl-0 = <&qup_i2c6_data_clk>; 2035 pinctrl-names = "default"; 2036 2037 #address-cells = <1>; 2038 #size-cells = <0>; 2039 2040 status = "disabled"; 2041 }; 2042 2043 spi6: spi@a98000 { 2044 compatible = "qcom,geni-spi"; 2045 reg = <0 0x00a98000 0 0x4000>; 2046 2047 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 2048 2049 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2050 clock-names = "se"; 2051 2052 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2053 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2054 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2055 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2056 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2057 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2058 interconnect-names = "qup-core", 2059 "qup-config", 2060 "qup-memory"; 2061 2062 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2063 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2064 dma-names = "tx", 2065 "rx"; 2066 2067 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2068 pinctrl-names = "default"; 2069 2070 #address-cells = <1>; 2071 #size-cells = <0>; 2072 2073 status = "disabled"; 2074 }; 2075 2076 i2c7: i2c@a9c000 { 2077 compatible = "qcom,geni-i2c"; 2078 reg = <0 0x00a9c000 0 0x4000>; 2079 2080 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 2081 2082 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2083 clock-names = "se"; 2084 2085 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2086 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2087 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2088 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2089 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2090 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2091 interconnect-names = "qup-core", 2092 "qup-config", 2093 "qup-memory"; 2094 2095 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2096 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2097 dma-names = "tx", 2098 "rx"; 2099 2100 pinctrl-0 = <&qup_i2c7_data_clk>; 2101 pinctrl-names = "default"; 2102 2103 #address-cells = <1>; 2104 #size-cells = <0>; 2105 2106 status = "disabled"; 2107 }; 2108 2109 spi7: spi@a9c000 { 2110 compatible = "qcom,geni-spi"; 2111 reg = <0 0x00a9c000 0 0x4000>; 2112 2113 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 2114 2115 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2116 clock-names = "se"; 2117 2118 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2119 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2120 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2121 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2122 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2123 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2124 interconnect-names = "qup-core", 2125 "qup-config", 2126 "qup-memory"; 2127 2128 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2129 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2130 dma-names = "tx", 2131 "rx"; 2132 2133 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2134 pinctrl-names = "default"; 2135 2136 #address-cells = <1>; 2137 #size-cells = <0>; 2138 2139 status = "disabled"; 2140 }; 2141 }; 2142 2143 cnoc_main: interconnect@1500000 { 2144 compatible = "qcom,sm8650-cnoc-main"; 2145 reg = <0 0x01500000 0 0x14080>; 2146 2147 qcom,bcm-voters = <&apps_bcm_voter>; 2148 2149 #interconnect-cells = <2>; 2150 }; 2151 2152 config_noc: interconnect@1600000 { 2153 compatible = "qcom,sm8650-config-noc"; 2154 reg = <0 0x01600000 0 0x6200>; 2155 2156 qcom,bcm-voters = <&apps_bcm_voter>; 2157 2158 #interconnect-cells = <2>; 2159 }; 2160 2161 system_noc: interconnect@1680000 { 2162 compatible = "qcom,sm8650-system-noc"; 2163 reg = <0 0x01680000 0 0x1d080>; 2164 2165 qcom,bcm-voters = <&apps_bcm_voter>; 2166 2167 #interconnect-cells = <2>; 2168 }; 2169 2170 pcie_noc: interconnect@16c0000 { 2171 compatible = "qcom,sm8650-pcie-anoc"; 2172 reg = <0 0x016c0000 0 0x12200>; 2173 2174 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2175 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 2176 2177 qcom,bcm-voters = <&apps_bcm_voter>; 2178 2179 #interconnect-cells = <2>; 2180 }; 2181 2182 aggre1_noc: interconnect@16e0000 { 2183 compatible = "qcom,sm8650-aggre1-noc"; 2184 reg = <0 0x016e0000 0 0x16400>; 2185 2186 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2187 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2188 2189 qcom,bcm-voters = <&apps_bcm_voter>; 2190 2191 #interconnect-cells = <2>; 2192 }; 2193 2194 aggre2_noc: interconnect@1700000 { 2195 compatible = "qcom,sm8650-aggre2-noc"; 2196 reg = <0 0x01700000 0 0x1e400>; 2197 2198 clocks = <&rpmhcc RPMH_IPA_CLK>; 2199 2200 qcom,bcm-voters = <&apps_bcm_voter>; 2201 2202 #interconnect-cells = <2>; 2203 }; 2204 2205 mmss_noc: interconnect@1780000 { 2206 compatible = "qcom,sm8650-mmss-noc"; 2207 reg = <0 0x01780000 0 0x5b800>; 2208 2209 qcom,bcm-voters = <&apps_bcm_voter>; 2210 2211 #interconnect-cells = <2>; 2212 }; 2213 2214 rng: rng@10c3000 { 2215 compatible = "qcom,sm8650-trng", "qcom,trng"; 2216 reg = <0 0x010c3000 0 0x1000>; 2217 }; 2218 2219 pcie0: pcie@1c00000 { 2220 device_type = "pci"; 2221 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 2222 reg = <0 0x01c00000 0 0x3000>, 2223 <0 0x60000000 0 0xf1d>, 2224 <0 0x60000f20 0 0xa8>, 2225 <0 0x60001000 0 0x1000>, 2226 <0 0x60100000 0 0x100000>; 2227 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2228 2229 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2231 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2236 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2237 interrupt-names = "msi0", 2238 "msi1", 2239 "msi2", 2240 "msi3", 2241 "msi4", 2242 "msi5", 2243 "msi6", 2244 "msi7"; 2245 2246 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2247 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2248 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2249 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2250 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2251 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2252 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2253 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2254 clock-names = "aux", 2255 "cfg", 2256 "bus_master", 2257 "bus_slave", 2258 "slave_q2a", 2259 "ddrss_sf_tbu", 2260 "noc_aggr", 2261 "cnoc_sf_axi"; 2262 2263 resets = <&gcc GCC_PCIE_0_BCR>; 2264 reset-names = "pci"; 2265 2266 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2267 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2268 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2269 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 2270 interconnect-names = "pcie-mem", 2271 "cpu-pcie"; 2272 2273 power-domains = <&gcc PCIE_0_GDSC>; 2274 2275 iommu-map = <0 &apps_smmu 0x1400 0x1>, 2276 <0x100 &apps_smmu 0x1401 0x1>; 2277 2278 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 2279 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 2280 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 2281 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 2282 interrupt-map-mask = <0 0 0 0x7>; 2283 #interrupt-cells = <1>; 2284 2285 msi-map = <0x0 &gic_its 0x1400 0x1>, 2286 <0x100 &gic_its 0x1401 0x1>; 2287 msi-map-mask = <0xff00>; 2288 2289 linux,pci-domain = <0>; 2290 num-lanes = <2>; 2291 bus-range = <0 0xff>; 2292 2293 phys = <&pcie0_phy>; 2294 phy-names = "pciephy"; 2295 2296 #address-cells = <3>; 2297 #size-cells = <2>; 2298 ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, 2299 <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>; 2300 2301 dma-coherent; 2302 2303 status = "disabled"; 2304 2305 pcieport0: pcie@0 { 2306 device_type = "pci"; 2307 reg = <0x0 0x0 0x0 0x0 0x0>; 2308 bus-range = <0x01 0xff>; 2309 2310 #address-cells = <3>; 2311 #size-cells = <2>; 2312 ranges; 2313 }; 2314 }; 2315 2316 pcie0_phy: phy@1c06000 { 2317 compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy"; 2318 reg = <0 0x01c06000 0 0x2000>; 2319 2320 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2321 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2322 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 2323 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2324 <&gcc GCC_PCIE_0_PIPE_CLK>; 2325 clock-names = "aux", 2326 "cfg_ahb", 2327 "ref", 2328 "rchng", 2329 "pipe"; 2330 2331 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2332 assigned-clock-rates = <100000000>; 2333 2334 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2335 reset-names = "phy"; 2336 2337 power-domains = <&gcc PCIE_0_PHY_GDSC>; 2338 2339 #clock-cells = <0>; 2340 clock-output-names = "pcie0_pipe_clk"; 2341 2342 #phy-cells = <0>; 2343 2344 status = "disabled"; 2345 }; 2346 2347 pcie1: pcie@1c08000 { 2348 device_type = "pci"; 2349 compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; 2350 reg = <0 0x01c08000 0 0x3000>, 2351 <0 0x40000000 0 0xf1d>, 2352 <0 0x40000f20 0 0xa8>, 2353 <0 0x40001000 0 0x1000>, 2354 <0 0x40100000 0 0x100000>; 2355 reg-names = "parf", 2356 "dbi", 2357 "elbi", 2358 "atu", 2359 "config"; 2360 2361 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2362 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2363 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2364 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2365 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2366 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2367 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2368 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2369 interrupt-names = "msi0", 2370 "msi1", 2371 "msi2", 2372 "msi3", 2373 "msi4", 2374 "msi5", 2375 "msi6", 2376 "msi7"; 2377 2378 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2379 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2380 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2381 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2382 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2383 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2384 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2385 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2386 clock-names = "aux", 2387 "cfg", 2388 "bus_master", 2389 "bus_slave", 2390 "slave_q2a", 2391 "ddrss_sf_tbu", 2392 "noc_aggr", 2393 "cnoc_sf_axi"; 2394 2395 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2396 assigned-clock-rates = <19200000>; 2397 2398 resets = <&gcc GCC_PCIE_1_BCR>, 2399 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2400 reset-names = "pci", 2401 "link_down"; 2402 2403 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2404 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2405 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2406 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; 2407 interconnect-names = "pcie-mem", 2408 "cpu-pcie"; 2409 2410 power-domains = <&gcc PCIE_1_GDSC>; 2411 2412 iommu-map = <0 &apps_smmu 0x1480 0x1>, 2413 <0x100 &apps_smmu 0x1481 0x1>; 2414 2415 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2416 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2417 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2418 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2419 interrupt-map-mask = <0 0 0 0x7>; 2420 #interrupt-cells = <1>; 2421 2422 msi-map = <0x0 &gic_its 0x1480 0x1>, 2423 <0x100 &gic_its 0x1481 0x1>; 2424 msi-map-mask = <0xff00>; 2425 2426 linux,pci-domain = <1>; 2427 num-lanes = <2>; 2428 bus-range = <0 0xff>; 2429 2430 phys = <&pcie1_phy>; 2431 phy-names = "pciephy"; 2432 2433 dma-coherent; 2434 2435 #address-cells = <3>; 2436 #size-cells = <2>; 2437 ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, 2438 <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; 2439 2440 status = "disabled"; 2441 2442 pcie@0 { 2443 device_type = "pci"; 2444 reg = <0x0 0x0 0x0 0x0 0x0>; 2445 bus-range = <0x01 0xff>; 2446 2447 #address-cells = <3>; 2448 #size-cells = <2>; 2449 ranges; 2450 }; 2451 }; 2452 2453 pcie1_phy: phy@1c0e000 { 2454 compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy"; 2455 reg = <0 0x01c0e000 0 0x2000>; 2456 2457 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2458 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2459 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 2460 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2461 <&gcc GCC_PCIE_1_PIPE_CLK>; 2462 clock-names = "aux", 2463 "cfg_ahb", 2464 "ref", 2465 "rchng", 2466 "pipe"; 2467 2468 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2469 assigned-clock-rates = <100000000>; 2470 2471 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 2472 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 2473 reset-names = "phy", 2474 "phy_nocsr"; 2475 2476 power-domains = <&gcc PCIE_1_PHY_GDSC>; 2477 2478 #clock-cells = <1>; 2479 clock-output-names = "pcie1_pipe_clk"; 2480 2481 #phy-cells = <0>; 2482 2483 status = "disabled"; 2484 }; 2485 2486 cryptobam: dma-controller@1dc4000 { 2487 compatible = "qcom,bam-v1.7.0"; 2488 reg = <0 0x01dc4000 0 0x28000>; 2489 2490 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2491 2492 #dma-cells = <1>; 2493 2494 iommus = <&apps_smmu 0x480 0>, 2495 <&apps_smmu 0x481 0>; 2496 2497 qcom,ee = <0>; 2498 qcom,controlled-remotely; 2499 }; 2500 2501 crypto: crypto@1dfa000 { 2502 compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; 2503 reg = <0 0x01dfa000 0 0x6000>; 2504 2505 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 2506 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2507 interconnect-names = "memory"; 2508 2509 dmas = <&cryptobam 4>, <&cryptobam 5>; 2510 dma-names = "rx", "tx"; 2511 2512 iommus = <&apps_smmu 0x480 0>, 2513 <&apps_smmu 0x481 0>; 2514 }; 2515 2516 ufs_mem_phy: phy@1d80000 { 2517 compatible = "qcom,sm8650-qmp-ufs-phy"; 2518 reg = <0 0x01d80000 0 0x2000>; 2519 2520 clocks = <&rpmhcc RPMH_CXO_CLK>, 2521 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2522 <&tcsr TCSR_UFS_CLKREF_EN>; 2523 clock-names = "ref", 2524 "ref_aux", 2525 "qref"; 2526 2527 resets = <&ufs_mem_hc 0>; 2528 reset-names = "ufsphy"; 2529 2530 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 2531 2532 #clock-cells = <1>; 2533 #phy-cells = <0>; 2534 2535 status = "disabled"; 2536 }; 2537 2538 ufs_mem_hc: ufs@1d84000 { 2539 compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2540 reg = <0 0x01d84000 0 0x3000>; 2541 2542 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2543 2544 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2545 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2546 <&gcc GCC_UFS_PHY_AHB_CLK>, 2547 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2548 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 2549 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2550 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2551 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2552 clock-names = "core_clk", 2553 "bus_aggr_clk", 2554 "iface_clk", 2555 "core_clk_unipro", 2556 "ref_clk", 2557 "tx_lane0_sync_clk", 2558 "rx_lane0_sync_clk", 2559 "rx_lane1_sync_clk"; 2560 freq-table-hz = <100000000 403000000>, 2561 <0 0>, 2562 <0 0>, 2563 <100000000 403000000>, 2564 <100000000 403000000>, 2565 <0 0>, 2566 <0 0>, 2567 <0 0>; 2568 2569 resets = <&gcc GCC_UFS_PHY_BCR>; 2570 reset-names = "rst"; 2571 2572 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2573 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2574 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2575 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2576 interconnect-names = "ufs-ddr", 2577 "cpu-ufs"; 2578 2579 power-domains = <&gcc UFS_PHY_GDSC>; 2580 required-opps = <&rpmhpd_opp_nom>; 2581 2582 iommus = <&apps_smmu 0x60 0>; 2583 2584 lanes-per-direction = <2>; 2585 qcom,ice = <&ice>; 2586 2587 phys = <&ufs_mem_phy>; 2588 phy-names = "ufsphy"; 2589 2590 #reset-cells = <1>; 2591 2592 status = "disabled"; 2593 }; 2594 2595 ice: crypto@1d88000 { 2596 compatible = "qcom,sm8650-inline-crypto-engine", 2597 "qcom,inline-crypto-engine"; 2598 reg = <0 0x01d88000 0 0x8000>; 2599 2600 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2601 }; 2602 2603 tcsr_mutex: hwlock@1f40000 { 2604 compatible = "qcom,tcsr-mutex"; 2605 reg = <0 0x01f40000 0 0x20000>; 2606 2607 #hwlock-cells = <1>; 2608 }; 2609 2610 tcsr: clock-controller@1fc0000 { 2611 compatible = "qcom,sm8650-tcsr", "syscon"; 2612 reg = <0 0x01fc0000 0 0xa0000>; 2613 2614 clocks = <&rpmhcc RPMH_CXO_CLK>; 2615 2616 #clock-cells = <1>; 2617 #reset-cells = <1>; 2618 }; 2619 2620 gpu: gpu@3d00000 { 2621 compatible = "qcom,adreno-43051401", "qcom,adreno"; 2622 reg = <0x0 0x03d00000 0x0 0x40000>, 2623 <0x0 0x03d9e000 0x0 0x2000>, 2624 <0x0 0x03d61000 0x0 0x800>; 2625 reg-names = "kgsl_3d0_reg_memory", 2626 "cx_mem", 2627 "cx_dbgc"; 2628 2629 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2630 2631 iommus = <&adreno_smmu 0 0x0>, 2632 <&adreno_smmu 1 0x0>; 2633 2634 operating-points-v2 = <&gpu_opp_table>; 2635 2636 qcom,gmu = <&gmu>; 2637 #cooling-cells = <2>; 2638 2639 status = "disabled"; 2640 2641 zap-shader { 2642 memory-region = <&gpu_micro_code_mem>; 2643 }; 2644 2645 /* Speedbin needs more work on A740+, keep only lower freqs */ 2646 gpu_opp_table: opp-table { 2647 compatible = "operating-points-v2"; 2648 2649 opp-231000000 { 2650 opp-hz = /bits/ 64 <231000000>; 2651 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 2652 }; 2653 2654 opp-310000000 { 2655 opp-hz = /bits/ 64 <310000000>; 2656 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2657 }; 2658 2659 opp-366000000 { 2660 opp-hz = /bits/ 64 <366000000>; 2661 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 2662 }; 2663 2664 opp-422000000 { 2665 opp-hz = /bits/ 64 <422000000>; 2666 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2667 }; 2668 2669 opp-500000000 { 2670 opp-hz = /bits/ 64 <500000000>; 2671 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2672 }; 2673 2674 opp-578000000 { 2675 opp-hz = /bits/ 64 <578000000>; 2676 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2677 }; 2678 2679 opp-629000000 { 2680 opp-hz = /bits/ 64 <629000000>; 2681 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2682 }; 2683 2684 opp-680000000 { 2685 opp-hz = /bits/ 64 <680000000>; 2686 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2687 }; 2688 2689 opp-720000000 { 2690 opp-hz = /bits/ 64 <720000000>; 2691 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2692 }; 2693 2694 opp-770000000 { 2695 opp-hz = /bits/ 64 <770000000>; 2696 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2697 }; 2698 2699 opp-834000000 { 2700 opp-hz = /bits/ 64 <834000000>; 2701 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2702 }; 2703 }; 2704 }; 2705 2706 gmu: gmu@3d6a000 { 2707 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; 2708 reg = <0x0 0x03d6a000 0x0 0x35000>, 2709 <0x0 0x03d50000 0x0 0x10000>, 2710 <0x0 0x0b280000 0x0 0x10000>; 2711 reg-names = "gmu", "rscc", "gmu_pdc"; 2712 2713 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2715 interrupt-names = "hfi", "gmu"; 2716 2717 clocks = <&gpucc GPU_CC_AHB_CLK>, 2718 <&gpucc GPU_CC_CX_GMU_CLK>, 2719 <&gpucc GPU_CC_CXO_CLK>, 2720 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2721 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2722 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2723 <&gpucc GPU_CC_DEMET_CLK>; 2724 clock-names = "ahb", 2725 "gmu", 2726 "cxo", 2727 "axi", 2728 "memnoc", 2729 "hub", 2730 "demet"; 2731 2732 power-domains = <&gpucc GPU_CX_GDSC>, 2733 <&gpucc GPU_GX_GDSC>; 2734 power-domain-names = "cx", 2735 "gx"; 2736 2737 iommus = <&adreno_smmu 5 0x0>; 2738 2739 qcom,qmp = <&aoss_qmp>; 2740 2741 operating-points-v2 = <&gmu_opp_table>; 2742 2743 gmu_opp_table: opp-table { 2744 compatible = "operating-points-v2"; 2745 2746 opp-260000000 { 2747 opp-hz = /bits/ 64 <260000000>; 2748 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2749 }; 2750 2751 opp-625000000 { 2752 opp-hz = /bits/ 64 <625000000>; 2753 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2754 }; 2755 }; 2756 }; 2757 2758 gpucc: clock-controller@3d90000 { 2759 compatible = "qcom,sm8650-gpucc"; 2760 reg = <0 0x03d90000 0 0xa000>; 2761 2762 clocks = <&bi_tcxo_div2>, 2763 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2764 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2765 2766 #clock-cells = <1>; 2767 #reset-cells = <1>; 2768 #power-domain-cells = <1>; 2769 }; 2770 2771 adreno_smmu: iommu@3da0000 { 2772 compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", 2773 "qcom,smmu-500", "arm,mmu-500"; 2774 reg = <0x0 0x03da0000 0x0 0x40000>; 2775 #iommu-cells = <2>; 2776 #global-interrupts = <1>; 2777 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2778 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>, 2779 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2780 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2781 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2782 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2783 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2784 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2785 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2786 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2787 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2788 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2789 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2790 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2791 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2792 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2793 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2794 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2795 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2796 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2797 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2798 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2799 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2800 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2801 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2802 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 2803 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2804 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2805 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2806 <&gpucc GPU_CC_AHB_CLK>; 2807 clock-names = "hlos", 2808 "bus", 2809 "iface", 2810 "ahb"; 2811 power-domains = <&gpucc GPU_CX_GDSC>; 2812 dma-coherent; 2813 }; 2814 2815 ipa: ipa@3f40000 { 2816 compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; 2817 2818 iommus = <&apps_smmu 0x4a0 0x0>, 2819 <&apps_smmu 0x4a2 0x0>; 2820 reg = <0 0x3f40000 0 0x10000>, 2821 <0 0x3f50000 0 0x5000>, 2822 <0 0x3e04000 0 0xfc000>; 2823 reg-names = "ipa-reg", 2824 "ipa-shared", 2825 "gsi"; 2826 2827 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2828 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2829 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2830 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2831 interrupt-names = "ipa", 2832 "gsi", 2833 "ipa-clock-query", 2834 "ipa-setup-ready"; 2835 2836 clocks = <&rpmhcc RPMH_IPA_CLK>; 2837 clock-names = "core"; 2838 2839 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2840 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2841 interconnect-names = "memory", 2842 "config"; 2843 2844 qcom,qmp = <&aoss_qmp>; 2845 2846 qcom,smem-states = <&ipa_smp2p_out 0>, 2847 <&ipa_smp2p_out 1>; 2848 qcom,smem-state-names = "ipa-clock-enabled-valid", 2849 "ipa-clock-enabled"; 2850 2851 status = "disabled"; 2852 }; 2853 2854 remoteproc_mpss: remoteproc@4080000 { 2855 compatible = "qcom,sm8650-mpss-pas"; 2856 reg = <0 0x04080000 0 0x4040>; 2857 2858 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2859 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2860 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2861 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2862 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2863 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2864 interrupt-names = "wdog", 2865 "fatal", 2866 "ready", 2867 "handover", 2868 "stop-ack", 2869 "shutdown-ack"; 2870 2871 clocks = <&rpmhcc RPMH_CXO_CLK>; 2872 clock-names = "xo"; 2873 2874 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 2875 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2876 2877 power-domains = <&rpmhpd RPMHPD_CX>, 2878 <&rpmhpd RPMHPD_MSS>; 2879 power-domain-names = "cx", 2880 "mss"; 2881 2882 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, 2883 <&mpss_dsm_mem>, <&mpss_dsm_mem_2>, 2884 <&qlink_logging_mem>; 2885 2886 qcom,qmp = <&aoss_qmp>; 2887 2888 qcom,smem-states = <&smp2p_modem_out 0>; 2889 qcom,smem-state-names = "stop"; 2890 2891 status = "disabled"; 2892 2893 glink-edge { 2894 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2895 IPCC_MPROC_SIGNAL_GLINK_QMP 2896 IRQ_TYPE_EDGE_RISING>; 2897 2898 mboxes = <&ipcc IPCC_CLIENT_MPSS 2899 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2900 2901 qcom,remote-pid = <1>; 2902 2903 label = "mpss"; 2904 }; 2905 }; 2906 2907 lpass_wsa2macro: codec@6aa0000 { 2908 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 2909 reg = <0 0x06aa0000 0 0x1000>; 2910 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2911 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2912 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2913 <&lpass_vamacro>; 2914 clock-names = "mclk", 2915 "macro", 2916 "dcodec", 2917 "fsgen"; 2918 2919 #clock-cells = <0>; 2920 clock-output-names = "wsa2-mclk"; 2921 #sound-dai-cells = <1>; 2922 }; 2923 2924 swr3: soundwire@6ab0000 { 2925 compatible = "qcom,soundwire-v2.0.0"; 2926 reg = <0 0x06ab0000 0 0x10000>; 2927 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2928 clocks = <&lpass_wsa2macro>; 2929 clock-names = "iface"; 2930 label = "WSA2"; 2931 2932 pinctrl-0 = <&wsa2_swr_active>; 2933 pinctrl-names = "default"; 2934 2935 qcom,din-ports = <4>; 2936 qcom,dout-ports = <9>; 2937 2938 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2939 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2940 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2941 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2942 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2943 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2944 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2945 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2946 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2947 2948 #address-cells = <2>; 2949 #size-cells = <0>; 2950 #sound-dai-cells = <1>; 2951 status = "disabled"; 2952 }; 2953 2954 lpass_rxmacro: codec@6ac0000 { 2955 compatible = "qcom,sm8650-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 2956 reg = <0 0x06ac0000 0 0x1000>; 2957 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2958 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2959 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2960 <&lpass_vamacro>; 2961 clock-names = "mclk", 2962 "macro", 2963 "dcodec", 2964 "fsgen"; 2965 2966 #clock-cells = <0>; 2967 clock-output-names = "mclk"; 2968 #sound-dai-cells = <1>; 2969 }; 2970 2971 swr1: soundwire@6ad0000 { 2972 compatible = "qcom,soundwire-v2.0.0"; 2973 reg = <0 0x06ad0000 0 0x10000>; 2974 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2975 clocks = <&lpass_rxmacro>; 2976 clock-names = "iface"; 2977 label = "RX"; 2978 2979 pinctrl-0 = <&rx_swr_active>; 2980 pinctrl-names = "default"; 2981 2982 qcom,din-ports = <0>; 2983 qcom,dout-ports = <11>; 2984 2985 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>; 2986 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>; 2987 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 2988 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>; 2989 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>; 2990 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>; 2991 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>; 2992 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>; 2993 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; 2994 2995 #address-cells = <2>; 2996 #size-cells = <0>; 2997 #sound-dai-cells = <1>; 2998 status = "disabled"; 2999 }; 3000 3001 lpass_txmacro: codec@6ae0000 { 3002 compatible = "qcom,sm8650-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 3003 reg = <0 0x06ae0000 0 0x1000>; 3004 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3005 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3006 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3007 <&lpass_vamacro>; 3008 clock-names = "mclk", 3009 "macro", 3010 "dcodec", 3011 "fsgen"; 3012 3013 #clock-cells = <0>; 3014 clock-output-names = "mclk"; 3015 #sound-dai-cells = <1>; 3016 }; 3017 3018 lpass_wsamacro: codec@6b00000 { 3019 compatible = "qcom,sm8650-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 3020 reg = <0 0x06b00000 0 0x1000>; 3021 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3022 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3023 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3024 <&lpass_vamacro>; 3025 clock-names = "mclk", 3026 "macro", 3027 "dcodec", 3028 "fsgen"; 3029 3030 #clock-cells = <0>; 3031 clock-output-names = "mclk"; 3032 #sound-dai-cells = <1>; 3033 }; 3034 3035 swr0: soundwire@6b10000 { 3036 compatible = "qcom,soundwire-v2.0.0"; 3037 reg = <0 0x06b10000 0 0x10000>; 3038 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 3039 clocks = <&lpass_wsamacro>; 3040 clock-names = "iface"; 3041 label = "WSA"; 3042 3043 pinctrl-0 = <&wsa_swr_active>; 3044 pinctrl-names = "default"; 3045 3046 qcom,din-ports = <4>; 3047 qcom,dout-ports = <9>; 3048 3049 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3050 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3051 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3052 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3053 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3054 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3055 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3056 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3057 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3058 3059 #address-cells = <2>; 3060 #size-cells = <0>; 3061 #sound-dai-cells = <1>; 3062 status = "disabled"; 3063 }; 3064 3065 swr2: soundwire@6d30000 { 3066 compatible = "qcom,soundwire-v2.0.0"; 3067 reg = <0 0x06d30000 0 0x10000>; 3068 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 3069 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 3070 interrupt-names = "core", "wakeup"; 3071 clocks = <&lpass_txmacro>; 3072 clock-names = "iface"; 3073 label = "TX"; 3074 3075 pinctrl-0 = <&tx_swr_active>; 3076 pinctrl-names = "default"; 3077 3078 qcom,din-ports = <4>; 3079 qcom,dout-ports = <0>; 3080 3081 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3082 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 3083 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3084 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3085 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3086 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3087 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3088 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3089 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 3090 3091 #address-cells = <2>; 3092 #size-cells = <0>; 3093 #sound-dai-cells = <1>; 3094 status = "disabled"; 3095 }; 3096 3097 lpass_vamacro: codec@6d44000 { 3098 compatible = "qcom,sm8650-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 3099 reg = <0 0x06d44000 0 0x1000>; 3100 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3101 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3102 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3103 clock-names = "mclk", 3104 "macro", 3105 "dcodec"; 3106 3107 #clock-cells = <0>; 3108 clock-output-names = "fsgen"; 3109 #sound-dai-cells = <1>; 3110 }; 3111 3112 lpass_tlmm: pinctrl@6e80000 { 3113 compatible = "qcom,sm8650-lpass-lpi-pinctrl"; 3114 reg = <0 0x06e80000 0 0x20000>; 3115 3116 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3117 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3118 clock-names = "core", "audio"; 3119 3120 gpio-controller; 3121 #gpio-cells = <2>; 3122 gpio-ranges = <&lpass_tlmm 0 0 23>; 3123 3124 tx_swr_active: tx-swr-active-state { 3125 clk-pins { 3126 pins = "gpio0"; 3127 function = "swr_tx_clk"; 3128 drive-strength = <2>; 3129 slew-rate = <1>; 3130 bias-disable; 3131 }; 3132 3133 data-pins { 3134 pins = "gpio1", "gpio2", "gpio14"; 3135 function = "swr_tx_data"; 3136 drive-strength = <2>; 3137 slew-rate = <1>; 3138 bias-bus-hold; 3139 }; 3140 }; 3141 3142 rx_swr_active: rx-swr-active-state { 3143 clk-pins { 3144 pins = "gpio3"; 3145 function = "swr_rx_clk"; 3146 drive-strength = <2>; 3147 slew-rate = <1>; 3148 bias-disable; 3149 }; 3150 3151 data-pins { 3152 pins = "gpio4", "gpio5"; 3153 function = "swr_rx_data"; 3154 drive-strength = <2>; 3155 slew-rate = <1>; 3156 bias-bus-hold; 3157 }; 3158 }; 3159 3160 dmic01_default: dmic01-default-state { 3161 clk-pins { 3162 pins = "gpio6"; 3163 function = "dmic1_clk"; 3164 drive-strength = <8>; 3165 output-high; 3166 }; 3167 3168 data-pins { 3169 pins = "gpio7"; 3170 function = "dmic1_data"; 3171 drive-strength = <8>; 3172 input-enable; 3173 }; 3174 }; 3175 3176 dmic23_default: dmic23-default-state { 3177 clk-pins { 3178 pins = "gpio8"; 3179 function = "dmic2_clk"; 3180 drive-strength = <8>; 3181 output-high; 3182 }; 3183 3184 data-pins { 3185 pins = "gpio9"; 3186 function = "dmic2_data"; 3187 drive-strength = <8>; 3188 input-enable; 3189 }; 3190 }; 3191 3192 wsa_swr_active: wsa-swr-active-state { 3193 clk-pins { 3194 pins = "gpio10"; 3195 function = "wsa_swr_clk"; 3196 drive-strength = <2>; 3197 slew-rate = <1>; 3198 bias-disable; 3199 }; 3200 3201 data-pins { 3202 pins = "gpio11"; 3203 function = "wsa_swr_data"; 3204 drive-strength = <2>; 3205 slew-rate = <1>; 3206 bias-bus-hold; 3207 }; 3208 }; 3209 3210 wsa2_swr_active: wsa2-swr-active-state { 3211 clk-pins { 3212 pins = "gpio15"; 3213 function = "wsa2_swr_clk"; 3214 drive-strength = <2>; 3215 slew-rate = <1>; 3216 bias-disable; 3217 }; 3218 3219 data-pins { 3220 pins = "gpio16"; 3221 function = "wsa2_swr_data"; 3222 drive-strength = <2>; 3223 slew-rate = <1>; 3224 bias-bus-hold; 3225 }; 3226 }; 3227 }; 3228 3229 lpass_lpiaon_noc: interconnect@7400000 { 3230 compatible = "qcom,sm8650-lpass-lpiaon-noc"; 3231 reg = <0 0x07400000 0 0x19080>; 3232 3233 #interconnect-cells = <2>; 3234 3235 qcom,bcm-voters = <&apps_bcm_voter>; 3236 }; 3237 3238 lpass_lpicx_noc: interconnect@7430000 { 3239 compatible = "qcom,sm8650-lpass-lpicx-noc"; 3240 reg = <0 0x07430000 0 0x3a200>; 3241 3242 #interconnect-cells = <2>; 3243 3244 qcom,bcm-voters = <&apps_bcm_voter>; 3245 }; 3246 3247 lpass_ag_noc: interconnect@7e40000 { 3248 compatible = "qcom,sm8650-lpass-ag-noc"; 3249 reg = <0 0x07e40000 0 0xe080>; 3250 3251 #interconnect-cells = <2>; 3252 3253 qcom,bcm-voters = <&apps_bcm_voter>; 3254 }; 3255 3256 sdhc_2: mmc@8804000 { 3257 compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; 3258 reg = <0 0x08804000 0 0x1000>; 3259 3260 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3262 interrupt-names = "hc_irq", 3263 "pwr_irq"; 3264 3265 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3266 <&gcc GCC_SDCC2_APPS_CLK>, 3267 <&rpmhcc RPMH_CXO_CLK>; 3268 clock-names = "iface", 3269 "core", 3270 "xo"; 3271 3272 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3273 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3274 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3275 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; 3276 interconnect-names = "sdhc-ddr", 3277 "cpu-sdhc"; 3278 3279 power-domains = <&rpmhpd RPMHPD_CX>; 3280 operating-points-v2 = <&sdhc2_opp_table>; 3281 3282 iommus = <&apps_smmu 0x540 0>; 3283 3284 bus-width = <4>; 3285 3286 /* Forbid SDR104/SDR50 - broken hw! */ 3287 sdhci-caps-mask = <0x3 0>; 3288 3289 qcom,dll-config = <0x0007642c>; 3290 qcom,ddr-config = <0x80040868>; 3291 3292 dma-coherent; 3293 3294 status = "disabled"; 3295 3296 sdhc2_opp_table: opp-table { 3297 compatible = "operating-points-v2"; 3298 3299 opp-19200000 { 3300 opp-hz = /bits/ 64 <19200000>; 3301 required-opps = <&rpmhpd_opp_min_svs>; 3302 }; 3303 3304 opp-50000000 { 3305 opp-hz = /bits/ 64 <50000000>; 3306 required-opps = <&rpmhpd_opp_low_svs>; 3307 }; 3308 3309 opp-100000000 { 3310 opp-hz = /bits/ 64 <100000000>; 3311 required-opps = <&rpmhpd_opp_svs>; 3312 }; 3313 3314 opp-202000000 { 3315 opp-hz = /bits/ 64 <202000000>; 3316 required-opps = <&rpmhpd_opp_svs_l1>; 3317 }; 3318 }; 3319 }; 3320 3321 videocc: clock-controller@aaf0000 { 3322 compatible = "qcom,sm8650-videocc"; 3323 reg = <0 0x0aaf0000 0 0x10000>; 3324 clocks = <&bi_tcxo_div2>, 3325 <&gcc GCC_VIDEO_AHB_CLK>; 3326 power-domains = <&rpmhpd RPMHPD_MMCX>; 3327 #clock-cells = <1>; 3328 #reset-cells = <1>; 3329 #power-domain-cells = <1>; 3330 }; 3331 3332 cci0: cci@ac15000 { 3333 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 3334 reg = <0 0x0ac15000 0 0x1000>; 3335 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>; 3336 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3337 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 3338 <&camcc CAM_CC_CPAS_AHB_CLK>, 3339 <&camcc CAM_CC_CCI_0_CLK>; 3340 clock-names = "camnoc_axi", 3341 "cpas_ahb", 3342 "cci"; 3343 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 3344 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 3345 pinctrl-names = "default", "sleep"; 3346 status = "disabled"; 3347 #address-cells = <1>; 3348 #size-cells = <0>; 3349 3350 cci0_i2c0: i2c-bus@0 { 3351 reg = <0>; 3352 clock-frequency = <1000000>; 3353 #address-cells = <1>; 3354 #size-cells = <0>; 3355 }; 3356 3357 cci0_i2c1: i2c-bus@1 { 3358 reg = <1>; 3359 clock-frequency = <1000000>; 3360 #address-cells = <1>; 3361 #size-cells = <0>; 3362 }; 3363 }; 3364 3365 cci1: cci@ac16000 { 3366 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 3367 reg = <0 0x0ac16000 0 0x1000>; 3368 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>; 3369 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3370 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 3371 <&camcc CAM_CC_CPAS_AHB_CLK>, 3372 <&camcc CAM_CC_CCI_1_CLK>; 3373 clock-names = "camnoc_axi", 3374 "cpas_ahb", 3375 "cci"; 3376 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 3377 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 3378 pinctrl-names = "default", "sleep"; 3379 status = "disabled"; 3380 #address-cells = <1>; 3381 #size-cells = <0>; 3382 3383 cci1_i2c0: i2c-bus@0 { 3384 reg = <0>; 3385 clock-frequency = <1000000>; 3386 #address-cells = <1>; 3387 #size-cells = <0>; 3388 }; 3389 3390 cci1_i2c1: i2c-bus@1 { 3391 reg = <1>; 3392 clock-frequency = <1000000>; 3393 #address-cells = <1>; 3394 #size-cells = <0>; 3395 }; 3396 }; 3397 3398 cci2: cci@ac17000 { 3399 compatible = "qcom,sm8650-cci", "qcom,msm8996-cci"; 3400 reg = <0 0x0ac17000 0 0x1000>; 3401 interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>; 3402 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3403 clocks = <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, 3404 <&camcc CAM_CC_CPAS_AHB_CLK>, 3405 <&camcc CAM_CC_CCI_2_CLK>; 3406 clock-names = "camnoc_axi", 3407 "cpas_ahb", 3408 "cci"; 3409 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 3410 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 3411 pinctrl-names = "default", "sleep"; 3412 status = "disabled"; 3413 #address-cells = <1>; 3414 #size-cells = <0>; 3415 3416 cci2_i2c0: i2c-bus@0 { 3417 reg = <0>; 3418 clock-frequency = <1000000>; 3419 #address-cells = <1>; 3420 #size-cells = <0>; 3421 }; 3422 3423 cci2_i2c1: i2c-bus@1 { 3424 reg = <1>; 3425 clock-frequency = <1000000>; 3426 #address-cells = <1>; 3427 #size-cells = <0>; 3428 }; 3429 }; 3430 3431 camcc: clock-controller@ade0000 { 3432 compatible = "qcom,sm8650-camcc"; 3433 reg = <0 0x0ade0000 0 0x20000>; 3434 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3435 <&bi_tcxo_div2>, 3436 <&bi_tcxo_ao_div2>, 3437 <&sleep_clk>; 3438 power-domains = <&rpmhpd RPMHPD_MMCX>; 3439 #clock-cells = <1>; 3440 #reset-cells = <1>; 3441 #power-domain-cells = <1>; 3442 }; 3443 3444 mdss: display-subsystem@ae00000 { 3445 compatible = "qcom,sm8650-mdss"; 3446 reg = <0 0x0ae00000 0 0x1000>; 3447 reg-names = "mdss"; 3448 3449 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3450 3451 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3452 <&gcc GCC_DISP_HF_AXI_CLK>, 3453 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3454 3455 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3456 3457 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 3458 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 3459 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 3460 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3461 interconnect-names = "mdp0-mem", 3462 "mdp1-mem"; 3463 3464 power-domains = <&dispcc MDSS_GDSC>; 3465 3466 iommus = <&apps_smmu 0x1c00 0x2>; 3467 3468 interrupt-controller; 3469 #interrupt-cells = <1>; 3470 3471 #address-cells = <2>; 3472 #size-cells = <2>; 3473 ranges; 3474 3475 status = "disabled"; 3476 3477 mdss_mdp: display-controller@ae01000 { 3478 compatible = "qcom,sm8650-dpu"; 3479 reg = <0 0x0ae01000 0 0x8f000>, 3480 <0 0x0aeb0000 0 0x2008>; 3481 reg-names = "mdp", 3482 "vbif"; 3483 3484 interrupts-extended = <&mdss 0>; 3485 3486 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3487 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3488 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3489 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3490 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3491 clock-names = "nrt_bus", 3492 "iface", 3493 "lut", 3494 "core", 3495 "vsync"; 3496 3497 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3498 assigned-clock-rates = <19200000>; 3499 3500 operating-points-v2 = <&mdp_opp_table>; 3501 3502 power-domains = <&rpmhpd RPMHPD_MMCX>; 3503 3504 ports { 3505 #address-cells = <1>; 3506 #size-cells = <0>; 3507 3508 port@0 { 3509 reg = <0>; 3510 3511 dpu_intf1_out: endpoint { 3512 remote-endpoint = <&mdss_dsi0_in>; 3513 }; 3514 }; 3515 3516 port@1 { 3517 reg = <1>; 3518 3519 dpu_intf2_out: endpoint { 3520 remote-endpoint = <&mdss_dsi1_in>; 3521 }; 3522 }; 3523 3524 port@2 { 3525 reg = <2>; 3526 3527 dpu_intf0_out: endpoint { 3528 remote-endpoint = <&mdss_dp0_in>; 3529 }; 3530 }; 3531 }; 3532 3533 mdp_opp_table: opp-table { 3534 compatible = "operating-points-v2"; 3535 3536 opp-200000000 { 3537 opp-hz = /bits/ 64 <200000000>; 3538 required-opps = <&rpmhpd_opp_low_svs>; 3539 }; 3540 3541 opp-325000000 { 3542 opp-hz = /bits/ 64 <325000000>; 3543 required-opps = <&rpmhpd_opp_svs>; 3544 }; 3545 3546 opp-375000000 { 3547 opp-hz = /bits/ 64 <375000000>; 3548 required-opps = <&rpmhpd_opp_svs_l1>; 3549 }; 3550 3551 opp-514000000 { 3552 opp-hz = /bits/ 64 <514000000>; 3553 required-opps = <&rpmhpd_opp_nom>; 3554 }; 3555 }; 3556 }; 3557 3558 mdss_dsi0: dsi@ae94000 { 3559 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3560 reg = <0 0x0ae94000 0 0x400>; 3561 reg-names = "dsi_ctrl"; 3562 3563 interrupts-extended = <&mdss 4>; 3564 3565 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3566 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3567 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3568 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3569 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3570 <&gcc GCC_DISP_HF_AXI_CLK>; 3571 clock-names = "byte", 3572 "byte_intf", 3573 "pixel", 3574 "core", 3575 "iface", 3576 "bus"; 3577 3578 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3579 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3580 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3581 <&mdss_dsi0_phy 1>; 3582 3583 operating-points-v2 = <&mdss_dsi_opp_table>; 3584 3585 power-domains = <&rpmhpd RPMHPD_MMCX>; 3586 3587 phys = <&mdss_dsi0_phy>; 3588 phy-names = "dsi"; 3589 3590 #address-cells = <1>; 3591 #size-cells = <0>; 3592 3593 status = "disabled"; 3594 3595 ports { 3596 #address-cells = <1>; 3597 #size-cells = <0>; 3598 3599 port@0 { 3600 reg = <0>; 3601 3602 mdss_dsi0_in: endpoint { 3603 remote-endpoint = <&dpu_intf1_out>; 3604 }; 3605 }; 3606 3607 port@1 { 3608 reg = <1>; 3609 3610 mdss_dsi0_out: endpoint { 3611 }; 3612 }; 3613 }; 3614 3615 mdss_dsi_opp_table: opp-table { 3616 compatible = "operating-points-v2"; 3617 3618 opp-187500000 { 3619 opp-hz = /bits/ 64 <187500000>; 3620 required-opps = <&rpmhpd_opp_low_svs>; 3621 }; 3622 3623 opp-300000000 { 3624 opp-hz = /bits/ 64 <300000000>; 3625 required-opps = <&rpmhpd_opp_svs>; 3626 }; 3627 3628 opp-358000000 { 3629 opp-hz = /bits/ 64 <358000000>; 3630 required-opps = <&rpmhpd_opp_svs_l1>; 3631 }; 3632 }; 3633 }; 3634 3635 mdss_dsi0_phy: phy@ae95000 { 3636 compatible = "qcom,sm8650-dsi-phy-4nm"; 3637 reg = <0 0x0ae95000 0 0x200>, 3638 <0 0x0ae95200 0 0x280>, 3639 <0 0x0ae95500 0 0x400>; 3640 reg-names = "dsi_phy", 3641 "dsi_phy_lane", 3642 "dsi_pll"; 3643 3644 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3645 <&rpmhcc RPMH_CXO_CLK>; 3646 clock-names = "iface", 3647 "ref"; 3648 3649 #clock-cells = <1>; 3650 #phy-cells = <0>; 3651 3652 status = "disabled"; 3653 }; 3654 3655 mdss_dsi1: dsi@ae96000 { 3656 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3657 reg = <0 0x0ae96000 0 0x400>; 3658 reg-names = "dsi_ctrl"; 3659 3660 interrupts-extended = <&mdss 5>; 3661 3662 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3663 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3664 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3665 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3666 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3667 <&gcc GCC_DISP_HF_AXI_CLK>; 3668 clock-names = "byte", 3669 "byte_intf", 3670 "pixel", 3671 "core", 3672 "iface", 3673 "bus"; 3674 3675 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3676 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3677 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3678 <&mdss_dsi1_phy 1>; 3679 3680 operating-points-v2 = <&mdss_dsi_opp_table>; 3681 3682 power-domains = <&rpmhpd RPMHPD_MMCX>; 3683 3684 phys = <&mdss_dsi1_phy>; 3685 phy-names = "dsi"; 3686 3687 #address-cells = <1>; 3688 #size-cells = <0>; 3689 3690 status = "disabled"; 3691 3692 ports { 3693 #address-cells = <1>; 3694 #size-cells = <0>; 3695 3696 port@0 { 3697 reg = <0>; 3698 3699 mdss_dsi1_in: endpoint { 3700 remote-endpoint = <&dpu_intf2_out>; 3701 }; 3702 }; 3703 3704 port@1 { 3705 reg = <1>; 3706 3707 mdss_dsi1_out: endpoint { 3708 }; 3709 }; 3710 }; 3711 }; 3712 3713 mdss_dsi1_phy: phy@ae97000 { 3714 compatible = "qcom,sm8650-dsi-phy-4nm"; 3715 reg = <0 0x0ae97000 0 0x200>, 3716 <0 0x0ae97200 0 0x280>, 3717 <0 0x0ae97500 0 0x400>; 3718 reg-names = "dsi_phy", 3719 "dsi_phy_lane", 3720 "dsi_pll"; 3721 3722 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3723 <&rpmhcc RPMH_CXO_CLK>; 3724 clock-names = "iface", 3725 "ref"; 3726 3727 #clock-cells = <1>; 3728 #phy-cells = <0>; 3729 3730 status = "disabled"; 3731 }; 3732 3733 mdss_dp0: displayport-controller@af54000 { 3734 compatible = "qcom,sm8650-dp"; 3735 reg = <0 0xaf54000 0 0x104>, 3736 <0 0xaf54200 0 0xc0>, 3737 <0 0xaf55000 0 0x770>, 3738 <0 0xaf56000 0 0x9c>, 3739 <0 0xaf57000 0 0x9c>; 3740 3741 interrupts-extended = <&mdss 12>; 3742 3743 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3744 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3745 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3746 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3747 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3748 clock-names = "core_iface", 3749 "core_aux", 3750 "ctrl_link", 3751 "ctrl_link_iface", 3752 "stream_pixel"; 3753 3754 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3755 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3756 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3757 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3758 3759 operating-points-v2 = <&dp_opp_table>; 3760 3761 power-domains = <&rpmhpd RPMHPD_MMCX>; 3762 3763 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 3764 phy-names = "dp"; 3765 3766 #sound-dai-cells = <0>; 3767 3768 status = "disabled"; 3769 3770 dp_opp_table: opp-table { 3771 compatible = "operating-points-v2"; 3772 3773 opp-162000000 { 3774 opp-hz = /bits/ 64 <162000000>; 3775 required-opps = <&rpmhpd_opp_low_svs_d1>; 3776 }; 3777 3778 opp-270000000 { 3779 opp-hz = /bits/ 64 <270000000>; 3780 required-opps = <&rpmhpd_opp_low_svs>; 3781 }; 3782 3783 opp-540000000 { 3784 opp-hz = /bits/ 64 <540000000>; 3785 required-opps = <&rpmhpd_opp_svs_l1>; 3786 }; 3787 3788 opp-810000000 { 3789 opp-hz = /bits/ 64 <810000000>; 3790 required-opps = <&rpmhpd_opp_nom>; 3791 }; 3792 }; 3793 3794 ports { 3795 #address-cells = <1>; 3796 #size-cells = <0>; 3797 3798 port@0 { 3799 reg = <0>; 3800 3801 mdss_dp0_in: endpoint { 3802 remote-endpoint = <&dpu_intf0_out>; 3803 }; 3804 }; 3805 3806 port@1 { 3807 reg = <1>; 3808 3809 mdss_dp0_out: endpoint { 3810 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 3811 }; 3812 }; 3813 }; 3814 }; 3815 }; 3816 3817 dispcc: clock-controller@af00000 { 3818 compatible = "qcom,sm8650-dispcc"; 3819 reg = <0 0x0af00000 0 0x20000>; 3820 3821 clocks = <&bi_tcxo_div2>, 3822 <&bi_tcxo_ao_div2>, 3823 <&gcc GCC_DISP_AHB_CLK>, 3824 <&sleep_clk>, 3825 <&mdss_dsi0_phy 0>, 3826 <&mdss_dsi0_phy 1>, 3827 <&mdss_dsi1_phy 0>, 3828 <&mdss_dsi1_phy 1>, 3829 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3830 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3831 <0>, /* dp1 */ 3832 <0>, 3833 <0>, /* dp2 */ 3834 <0>, 3835 <0>, /* dp3 */ 3836 <0>; 3837 3838 power-domains = <&rpmhpd RPMHPD_MMCX>; 3839 required-opps = <&rpmhpd_opp_low_svs>; 3840 3841 #clock-cells = <1>; 3842 #reset-cells = <1>; 3843 #power-domain-cells = <1>; 3844 3845 status = "disabled"; 3846 }; 3847 3848 usb_1_hsphy: phy@88e3000 { 3849 compatible = "qcom,sm8650-snps-eusb2-phy", 3850 "qcom,sm8550-snps-eusb2-phy"; 3851 reg = <0 0x088e3000 0 0x154>; 3852 3853 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 3854 clock-names = "ref"; 3855 3856 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3857 3858 #phy-cells = <0>; 3859 3860 status = "disabled"; 3861 }; 3862 3863 usb_dp_qmpphy: phy@88e8000 { 3864 compatible = "qcom,sm8650-qmp-usb3-dp-phy"; 3865 reg = <0 0x088e8000 0 0x3000>; 3866 3867 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3868 <&rpmhcc RPMH_CXO_CLK>, 3869 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3870 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3871 clock-names = "aux", 3872 "ref", 3873 "com_aux", 3874 "usb3_pipe"; 3875 3876 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3877 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 3878 reset-names = "phy", 3879 "common"; 3880 3881 power-domains = <&gcc USB3_PHY_GDSC>; 3882 3883 #clock-cells = <1>; 3884 #phy-cells = <1>; 3885 3886 orientation-switch; 3887 3888 status = "disabled"; 3889 3890 ports { 3891 #address-cells = <1>; 3892 #size-cells = <0>; 3893 3894 port@0 { 3895 reg = <0>; 3896 3897 usb_dp_qmpphy_out: endpoint { 3898 }; 3899 }; 3900 3901 port@1 { 3902 reg = <1>; 3903 3904 usb_dp_qmpphy_usb_ss_in: endpoint { 3905 remote-endpoint = <&usb_1_dwc3_ss>; 3906 }; 3907 }; 3908 3909 port@2 { 3910 reg = <2>; 3911 3912 usb_dp_qmpphy_dp_in: endpoint { 3913 remote-endpoint = <&mdss_dp0_out>; 3914 }; 3915 }; 3916 }; 3917 }; 3918 3919 usb_1: usb@a6f8800 { 3920 compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; 3921 reg = <0 0x0a6f8800 0 0x400>; 3922 3923 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3924 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3925 <&pdc 14 IRQ_TYPE_EDGE_RISING>, 3926 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 3927 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3928 interrupt-names = "pwr_event", 3929 "hs_phy_irq", 3930 "dp_hs_phy_irq", 3931 "dm_hs_phy_irq", 3932 "ss_phy_irq"; 3933 3934 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3935 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3936 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3937 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3938 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3939 <&tcsr TCSR_USB3_CLKREF_EN>; 3940 clock-names = "cfg_noc", 3941 "core", 3942 "iface", 3943 "sleep", 3944 "mock_utmi", 3945 "xo"; 3946 3947 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3948 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3949 assigned-clock-rates = <19200000>, <200000000>; 3950 3951 resets = <&gcc GCC_USB30_PRIM_BCR>; 3952 3953 power-domains = <&gcc USB30_PRIM_GDSC>; 3954 required-opps = <&rpmhpd_opp_nom>; 3955 3956 #address-cells = <2>; 3957 #size-cells = <2>; 3958 ranges; 3959 3960 status = "disabled"; 3961 3962 usb_1_dwc3: usb@a600000 { 3963 compatible = "snps,dwc3"; 3964 reg = <0 0x0a600000 0 0xcd00>; 3965 3966 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3967 3968 iommus = <&apps_smmu 0x40 0>; 3969 3970 phys = <&usb_1_hsphy>, 3971 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 3972 phy-names = "usb2-phy", 3973 "usb3-phy"; 3974 3975 snps,hird-threshold = /bits/ 8 <0x0>; 3976 snps,usb2-gadget-lpm-disable; 3977 snps,dis_u2_susphy_quirk; 3978 snps,dis_enblslpm_quirk; 3979 snps,dis-u1-entry-quirk; 3980 snps,dis-u2-entry-quirk; 3981 snps,is-utmi-l1-suspend; 3982 snps,usb3_lpm_capable; 3983 snps,usb2-lpm-disable; 3984 snps,has-lpm-erratum; 3985 tx-fifo-resize; 3986 3987 dma-coherent; 3988 3989 ports { 3990 #address-cells = <1>; 3991 #size-cells = <0>; 3992 3993 port@0 { 3994 reg = <0>; 3995 3996 usb_1_dwc3_hs: endpoint { 3997 }; 3998 }; 3999 4000 port@1 { 4001 reg = <1>; 4002 4003 usb_1_dwc3_ss: endpoint { 4004 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 4005 }; 4006 }; 4007 }; 4008 }; 4009 }; 4010 4011 pdc: interrupt-controller@b220000 { 4012 compatible = "qcom,sm8650-pdc", "qcom,pdc"; 4013 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 4014 4015 interrupt-parent = <&intc>; 4016 4017 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4018 <125 63 1>, <126 716 12>, 4019 <138 251 5>, <143 244 4>; 4020 4021 #interrupt-cells = <2>; 4022 interrupt-controller; 4023 }; 4024 4025 tsens0: thermal-sensor@c228000 { 4026 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 4027 reg = <0 0x0c228000 0 0x1000>, /* TM */ 4028 <0 0x0c222000 0 0x1000>; /* SROT */ 4029 4030 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4031 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 4032 interrupt-names = "uplow", 4033 "critical"; 4034 4035 #qcom,sensors = <15>; 4036 4037 #thermal-sensor-cells = <1>; 4038 }; 4039 4040 tsens1: thermal-sensor@c229000 { 4041 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 4042 reg = <0 0x0c229000 0 0x1000>, /* TM */ 4043 <0 0x0c223000 0 0x1000>; /* SROT */ 4044 4045 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4046 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 4047 interrupt-names = "uplow", 4048 "critical"; 4049 4050 #qcom,sensors = <16>; 4051 4052 #thermal-sensor-cells = <1>; 4053 }; 4054 4055 tsens2: thermal-sensor@c22a000 { 4056 compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; 4057 reg = <0 0x0c22a000 0 0x1000>, /* TM */ 4058 <0 0x0c224000 0 0x1000>; /* SROT */ 4059 4060 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 4062 interrupt-names = "uplow", 4063 "critical"; 4064 4065 #qcom,sensors = <13>; 4066 4067 #thermal-sensor-cells = <1>; 4068 }; 4069 4070 aoss_qmp: power-management@c300000 { 4071 compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; 4072 reg = <0 0x0c300000 0 0x400>; 4073 4074 interrupt-parent = <&ipcc>; 4075 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4076 IRQ_TYPE_EDGE_RISING>; 4077 4078 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4079 4080 #clock-cells = <0>; 4081 }; 4082 4083 sram@c3f0000 { 4084 compatible = "qcom,rpmh-stats"; 4085 reg = <0 0x0c3f0000 0 0x400>; 4086 }; 4087 4088 spmi_bus: spmi@c400000 { 4089 compatible = "qcom,spmi-pmic-arb"; 4090 reg = <0 0x0c400000 0 0x3000>, 4091 <0 0x0c500000 0 0x400000>, 4092 <0 0x0c440000 0 0x80000>, 4093 <0 0x0c4c0000 0 0x20000>, 4094 <0 0x0c42d000 0 0x4000>; 4095 reg-names = "core", 4096 "chnls", 4097 "obsrvr", 4098 "intr", 4099 "cnfg"; 4100 4101 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4102 interrupt-names = "periph_irq"; 4103 4104 qcom,ee = <0>; 4105 qcom,channel = <0>; 4106 qcom,bus-id = <0>; 4107 4108 interrupt-controller; 4109 #interrupt-cells = <4>; 4110 4111 #address-cells = <2>; 4112 #size-cells = <0>; 4113 }; 4114 4115 tlmm: pinctrl@f100000 { 4116 compatible = "qcom,sm8650-tlmm"; 4117 reg = <0 0x0f100000 0 0x300000>; 4118 4119 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4120 4121 gpio-controller; 4122 #gpio-cells = <2>; 4123 4124 interrupt-controller; 4125 #interrupt-cells = <2>; 4126 4127 gpio-ranges = <&tlmm 0 0 211>; 4128 4129 wakeup-parent = <&pdc>; 4130 4131 cci0_0_default: cci0-0-default-state { 4132 sda-pins { 4133 pins = "gpio113"; 4134 function = "cci_i2c_sda"; 4135 drive-strength = <2>; 4136 bias-pull-up = <2200>; 4137 }; 4138 4139 scl-pins { 4140 pins = "gpio114"; 4141 function = "cci_i2c_scl"; 4142 drive-strength = <2>; 4143 bias-pull-up = <2200>; 4144 }; 4145 }; 4146 4147 cci0_0_sleep: cci0-0-sleep-state { 4148 sda-pins { 4149 pins = "gpio113"; 4150 function = "cci_i2c_sda"; 4151 drive-strength = <2>; 4152 bias-pull-down; 4153 }; 4154 4155 scl-pins { 4156 pins = "gpio114"; 4157 function = "cci_i2c_scl"; 4158 drive-strength = <2>; 4159 bias-pull-down; 4160 }; 4161 }; 4162 4163 cci0_1_default: cci0-1-default-state { 4164 sda-pins { 4165 pins = "gpio115"; 4166 function = "cci_i2c_sda"; 4167 drive-strength = <2>; 4168 bias-pull-up = <2200>; 4169 }; 4170 4171 scl-pins { 4172 pins = "gpio116"; 4173 function = "cci_i2c_scl"; 4174 drive-strength = <2>; 4175 bias-pull-up = <2200>; 4176 }; 4177 }; 4178 4179 cci0_1_sleep: cci0-1-sleep-state { 4180 sda-pins { 4181 pins = "gpio115"; 4182 function = "cci_i2c_sda"; 4183 drive-strength = <2>; 4184 bias-pull-down; 4185 }; 4186 4187 scl-pins { 4188 pins = "gpio116"; 4189 function = "cci_i2c_scl"; 4190 drive-strength = <2>; 4191 bias-pull-down; 4192 }; 4193 }; 4194 4195 cci1_0_default: cci1-0-default-state { 4196 sda-pins { 4197 pins = "gpio117"; 4198 function = "cci_i2c_sda"; 4199 drive-strength = <2>; 4200 bias-pull-up = <2200>; 4201 }; 4202 4203 scl-pins { 4204 pins = "gpio118"; 4205 function = "cci_i2c_scl"; 4206 drive-strength = <2>; 4207 bias-pull-up = <2200>; 4208 }; 4209 }; 4210 4211 cci1_0_sleep: cci1-0-sleep-state { 4212 sda-pins { 4213 pins = "gpio117"; 4214 function = "cci_i2c_sda"; 4215 drive-strength = <2>; 4216 bias-pull-down; 4217 }; 4218 4219 scl-pins { 4220 pins = "gpio118"; 4221 function = "cci_i2c_scl"; 4222 drive-strength = <2>; 4223 bias-pull-down; 4224 }; 4225 }; 4226 4227 cci1_1_default: cci1-1-default-state { 4228 sda-pins { 4229 pins = "gpio12"; 4230 function = "cci_i2c_sda"; 4231 drive-strength = <2>; 4232 bias-pull-up = <2200>; 4233 }; 4234 4235 scl-pins { 4236 pins = "gpio13"; 4237 function = "cci_i2c_scl"; 4238 drive-strength = <2>; 4239 bias-pull-up = <2200>; 4240 }; 4241 }; 4242 4243 cci1_1_sleep: cci1-1-sleep-state { 4244 sda-pins { 4245 pins = "gpio12"; 4246 function = "cci_i2c_sda"; 4247 drive-strength = <2>; 4248 bias-pull-down; 4249 }; 4250 4251 scl-pins { 4252 pins = "gpio13"; 4253 function = "cci_i2c_scl"; 4254 drive-strength = <2>; 4255 bias-pull-down; 4256 }; 4257 }; 4258 4259 cci2_0_default: cci2-0-default-state { 4260 sda-pins { 4261 pins = "gpio112"; 4262 function = "cci_i2c_sda"; 4263 drive-strength = <2>; 4264 bias-pull-up = <2200>; 4265 }; 4266 4267 scl-pins { 4268 pins = "gpio153"; 4269 function = "cci_i2c_scl"; 4270 drive-strength = <2>; 4271 bias-pull-up = <2200>; 4272 }; 4273 }; 4274 4275 cci2_0_sleep: cci2-0-sleep-state { 4276 sda-pins { 4277 pins = "gpio112"; 4278 function = "cci_i2c_sda"; 4279 drive-strength = <2>; 4280 bias-pull-down; 4281 }; 4282 4283 scl-pins { 4284 pins = "gpio153"; 4285 function = "cci_i2c_scl"; 4286 drive-strength = <2>; 4287 bias-pull-down; 4288 }; 4289 }; 4290 4291 cci2_1_default: cci2-1-default-state { 4292 sda-pins { 4293 pins = "gpio119"; 4294 function = "cci_i2c_sda"; 4295 drive-strength = <2>; 4296 bias-pull-up = <2200>; 4297 }; 4298 4299 scl-pins { 4300 pins = "gpio120"; 4301 function = "cci_i2c_scl"; 4302 drive-strength = <2>; 4303 bias-pull-up = <2200>; 4304 }; 4305 }; 4306 4307 cci2_1_sleep: cci2-1-sleep-state { 4308 sda-pins { 4309 pins = "gpio119"; 4310 function = "cci_i2c_sda"; 4311 drive-strength = <2>; 4312 bias-pull-down; 4313 }; 4314 4315 scl-pins { 4316 pins = "gpio120"; 4317 function = "cci_i2c_scl"; 4318 drive-strength = <2>; 4319 bias-pull-down; 4320 }; 4321 }; 4322 4323 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 4324 /* SDA, SCL */ 4325 pins = "gpio64", "gpio65"; 4326 function = "i2chub0_se0"; 4327 drive-strength = <2>; 4328 bias-pull-up; 4329 }; 4330 4331 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 4332 /* SDA, SCL */ 4333 pins = "gpio66", "gpio67"; 4334 function = "i2chub0_se1"; 4335 drive-strength = <2>; 4336 bias-pull-up; 4337 }; 4338 4339 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 4340 /* SDA, SCL */ 4341 pins = "gpio68", "gpio69"; 4342 function = "i2chub0_se2"; 4343 drive-strength = <2>; 4344 bias-pull-up; 4345 }; 4346 4347 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 4348 /* SDA, SCL */ 4349 pins = "gpio70", "gpio71"; 4350 function = "i2chub0_se3"; 4351 drive-strength = <2>; 4352 bias-pull-up; 4353 }; 4354 4355 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 4356 /* SDA, SCL */ 4357 pins = "gpio72", "gpio73"; 4358 function = "i2chub0_se4"; 4359 drive-strength = <2>; 4360 bias-pull-up; 4361 }; 4362 4363 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 4364 /* SDA, SCL */ 4365 pins = "gpio74", "gpio75"; 4366 function = "i2chub0_se5"; 4367 drive-strength = <2>; 4368 bias-pull-up; 4369 }; 4370 4371 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 4372 /* SDA, SCL */ 4373 pins = "gpio76", "gpio77"; 4374 function = "i2chub0_se6"; 4375 drive-strength = <2>; 4376 bias-pull-up; 4377 }; 4378 4379 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 4380 /* SDA, SCL */ 4381 pins = "gpio78", "gpio79"; 4382 function = "i2chub0_se7"; 4383 drive-strength = <2>; 4384 bias-pull-up; 4385 }; 4386 4387 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 4388 /* SDA, SCL */ 4389 pins = "gpio206", "gpio207"; 4390 function = "i2chub0_se8"; 4391 drive-strength = <2>; 4392 bias-pull-up; 4393 }; 4394 4395 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 4396 /* SDA, SCL */ 4397 pins = "gpio80", "gpio81"; 4398 function = "i2chub0_se9"; 4399 drive-strength = <2>; 4400 bias-pull-up; 4401 }; 4402 4403 pcie0_default_state: pcie0-default-state { 4404 perst-pins { 4405 pins = "gpio94"; 4406 function = "gpio"; 4407 drive-strength = <2>; 4408 bias-pull-down; 4409 }; 4410 4411 clkreq-pins { 4412 pins = "gpio95"; 4413 function = "pcie0_clk_req_n"; 4414 drive-strength = <2>; 4415 bias-pull-up; 4416 }; 4417 4418 wake-pins { 4419 pins = "gpio96"; 4420 function = "gpio"; 4421 drive-strength = <2>; 4422 bias-pull-up; 4423 }; 4424 }; 4425 4426 pcie1_default_state: pcie1-default-state { 4427 perst-pins { 4428 pins = "gpio97"; 4429 function = "gpio"; 4430 drive-strength = <2>; 4431 bias-pull-down; 4432 }; 4433 4434 clkreq-pins { 4435 pins = "gpio98"; 4436 function = "pcie1_clk_req_n"; 4437 drive-strength = <2>; 4438 bias-pull-up; 4439 }; 4440 4441 wake-pins { 4442 pins = "gpio99"; 4443 function = "gpio"; 4444 drive-strength = <2>; 4445 bias-pull-up; 4446 }; 4447 }; 4448 4449 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4450 /* SDA, SCL */ 4451 pins = "gpio32", "gpio33"; 4452 function = "qup1_se0"; 4453 drive-strength = <2>; 4454 bias-pull-up; 4455 }; 4456 4457 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4458 /* SDA, SCL */ 4459 pins = "gpio36", "gpio37"; 4460 function = "qup1_se1"; 4461 drive-strength = <2>; 4462 bias-pull-up; 4463 }; 4464 4465 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4466 /* SDA, SCL */ 4467 pins = "gpio40", "gpio41"; 4468 function = "qup1_se2"; 4469 drive-strength = <2>; 4470 bias-pull-up; 4471 }; 4472 4473 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4474 /* SDA, SCL */ 4475 pins = "gpio44", "gpio45"; 4476 function = "qup1_se3"; 4477 drive-strength = <2>; 4478 bias-pull-up; 4479 }; 4480 4481 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4482 /* SDA, SCL */ 4483 pins = "gpio48", "gpio49"; 4484 function = "qup1_se4"; 4485 drive-strength = <2>; 4486 bias-pull-up; 4487 }; 4488 4489 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4490 /* SDA, SCL */ 4491 pins = "gpio52", "gpio53"; 4492 function = "qup1_se5"; 4493 drive-strength = <2>; 4494 bias-pull-up; 4495 }; 4496 4497 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4498 /* SDA, SCL */ 4499 pins = "gpio56", "gpio57"; 4500 function = "qup1_se6"; 4501 drive-strength = <2>; 4502 bias-pull-up; 4503 }; 4504 4505 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4506 /* SDA, SCL */ 4507 pins = "gpio60", "gpio61"; 4508 function = "qup1_se7"; 4509 drive-strength = <2>; 4510 bias-pull-up; 4511 }; 4512 4513 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4514 /* SDA, SCL */ 4515 pins = "gpio0", "gpio1"; 4516 function = "qup2_se0"; 4517 drive-strength = <2>; 4518 bias-pull-up; 4519 }; 4520 4521 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4522 /* SDA, SCL */ 4523 pins = "gpio4", "gpio5"; 4524 function = "qup2_se1"; 4525 drive-strength = <2>; 4526 bias-pull-up; 4527 }; 4528 4529 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4530 /* SDA, SCL */ 4531 pins = "gpio8", "gpio9"; 4532 function = "qup2_se2"; 4533 drive-strength = <2>; 4534 bias-pull-up; 4535 }; 4536 4537 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4538 /* SDA, SCL */ 4539 pins = "gpio12", "gpio13"; 4540 function = "qup2_se3"; 4541 drive-strength = <2>; 4542 bias-pull-up; 4543 }; 4544 4545 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4546 /* SDA, SCL */ 4547 pins = "gpio16", "gpio17"; 4548 function = "qup2_se4"; 4549 drive-strength = <2>; 4550 bias-pull-up; 4551 }; 4552 4553 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4554 /* SDA, SCL */ 4555 pins = "gpio20", "gpio21"; 4556 function = "qup2_se5"; 4557 drive-strength = <2>; 4558 bias-pull-up; 4559 }; 4560 4561 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4562 /* SDA, SCL */ 4563 pins = "gpio24", "gpio25"; 4564 function = "qup2_se6"; 4565 drive-strength = <2>; 4566 bias-pull-up; 4567 }; 4568 4569 qup_spi0_cs: qup-spi0-cs-state { 4570 pins = "gpio35"; 4571 function = "qup1_se0"; 4572 drive-strength = <6>; 4573 bias-disable; 4574 }; 4575 4576 qup_spi0_data_clk: qup-spi0-data-clk-state { 4577 /* MISO, MOSI, CLK */ 4578 pins = "gpio32", "gpio33", "gpio34"; 4579 function = "qup1_se0"; 4580 drive-strength = <6>; 4581 bias-disable; 4582 }; 4583 4584 qup_spi1_cs: qup-spi1-cs-state { 4585 pins = "gpio39"; 4586 function = "qup1_se1"; 4587 drive-strength = <6>; 4588 bias-disable; 4589 }; 4590 4591 qup_spi1_data_clk: qup-spi1-data-clk-state { 4592 /* MISO, MOSI, CLK */ 4593 pins = "gpio36", "gpio37", "gpio38"; 4594 function = "qup1_se1"; 4595 drive-strength = <6>; 4596 bias-disable; 4597 }; 4598 4599 qup_spi2_cs: qup-spi2-cs-state { 4600 pins = "gpio43"; 4601 function = "qup1_se2"; 4602 drive-strength = <6>; 4603 bias-disable; 4604 }; 4605 4606 qup_spi2_data_clk: qup-spi2-data-clk-state { 4607 /* MISO, MOSI, CLK */ 4608 pins = "gpio40", "gpio41", "gpio42"; 4609 function = "qup1_se2"; 4610 drive-strength = <6>; 4611 bias-disable; 4612 }; 4613 4614 qup_spi3_cs: qup-spi3-cs-state { 4615 pins = "gpio47"; 4616 function = "qup1_se3"; 4617 drive-strength = <6>; 4618 bias-disable; 4619 }; 4620 4621 qup_spi3_data_clk: qup-spi3-data-clk-state { 4622 /* MISO, MOSI, CLK */ 4623 pins = "gpio44", "gpio45", "gpio46"; 4624 function = "qup1_se3"; 4625 drive-strength = <6>; 4626 bias-disable; 4627 }; 4628 4629 qup_spi4_cs: qup-spi4-cs-state { 4630 pins = "gpio51"; 4631 function = "qup1_se4"; 4632 drive-strength = <6>; 4633 bias-disable; 4634 }; 4635 4636 qup_spi4_data_clk: qup-spi4-data-clk-state { 4637 /* MISO, MOSI, CLK */ 4638 pins = "gpio48", "gpio49", "gpio50"; 4639 function = "qup1_se4"; 4640 drive-strength = <6>; 4641 bias-disable; 4642 }; 4643 4644 qup_spi5_cs: qup-spi5-cs-state { 4645 pins = "gpio55"; 4646 function = "qup1_se5"; 4647 drive-strength = <6>; 4648 bias-disable; 4649 }; 4650 4651 qup_spi5_data_clk: qup-spi5-data-clk-state { 4652 /* MISO, MOSI, CLK */ 4653 pins = "gpio52", "gpio53", "gpio54"; 4654 function = "qup1_se5"; 4655 drive-strength = <6>; 4656 bias-disable; 4657 }; 4658 4659 qup_spi6_cs: qup-spi6-cs-state { 4660 pins = "gpio59"; 4661 function = "qup1_se6"; 4662 drive-strength = <6>; 4663 bias-disable; 4664 }; 4665 4666 qup_spi6_data_clk: qup-spi6-data-clk-state { 4667 /* MISO, MOSI, CLK */ 4668 pins = "gpio56", "gpio57", "gpio58"; 4669 function = "qup1_se6"; 4670 drive-strength = <6>; 4671 bias-disable; 4672 }; 4673 4674 qup_spi7_cs: qup-spi7-cs-state { 4675 pins = "gpio63"; 4676 function = "qup1_se7"; 4677 drive-strength = <6>; 4678 bias-disable; 4679 }; 4680 4681 qup_spi7_data_clk: qup-spi7-data-clk-state { 4682 /* MISO, MOSI, CLK */ 4683 pins = "gpio60", "gpio61", "gpio62"; 4684 function = "qup1_se7"; 4685 drive-strength = <6>; 4686 bias-disable; 4687 }; 4688 4689 qup_spi8_cs: qup-spi8-cs-state { 4690 pins = "gpio3"; 4691 function = "qup2_se0"; 4692 drive-strength = <6>; 4693 bias-disable; 4694 }; 4695 4696 qup_spi8_data_clk: qup-spi8-data-clk-state { 4697 /* MISO, MOSI, CLK */ 4698 pins = "gpio0", "gpio1", "gpio2"; 4699 function = "qup2_se0"; 4700 drive-strength = <6>; 4701 bias-disable; 4702 }; 4703 4704 qup_spi9_cs: qup-spi9-cs-state { 4705 pins = "gpio7"; 4706 function = "qup2_se1"; 4707 drive-strength = <6>; 4708 bias-disable; 4709 }; 4710 4711 qup_spi9_data_clk: qup-spi9-data-clk-state { 4712 /* MISO, MOSI, CLK */ 4713 pins = "gpio4", "gpio5", "gpio6"; 4714 function = "qup2_se1"; 4715 drive-strength = <6>; 4716 bias-disable; 4717 }; 4718 4719 qup_spi10_cs: qup-spi10-cs-state { 4720 pins = "gpio11"; 4721 function = "qup2_se2"; 4722 drive-strength = <6>; 4723 bias-disable; 4724 }; 4725 4726 qup_spi10_data_clk: qup-spi10-data-clk-state { 4727 /* MISO, MOSI, CLK */ 4728 pins = "gpio8", "gpio9", "gpio10"; 4729 function = "qup2_se2"; 4730 drive-strength = <6>; 4731 bias-disable; 4732 }; 4733 4734 qup_spi11_cs: qup-spi11-cs-state { 4735 pins = "gpio15"; 4736 function = "qup2_se3"; 4737 drive-strength = <6>; 4738 bias-disable; 4739 }; 4740 4741 qup_spi11_data_clk: qup-spi11-data-clk-state { 4742 /* MISO, MOSI, CLK */ 4743 pins = "gpio12", "gpio13", "gpio14"; 4744 function = "qup2_se3"; 4745 drive-strength = <6>; 4746 bias-disable; 4747 }; 4748 4749 qup_spi12_cs: qup-spi12-cs-state { 4750 pins = "gpio19"; 4751 function = "qup2_se4"; 4752 drive-strength = <6>; 4753 bias-disable; 4754 }; 4755 4756 qup_spi12_data_clk: qup-spi12-data-clk-state { 4757 /* MISO, MOSI, CLK */ 4758 pins = "gpio16", "gpio17", "gpio18"; 4759 function = "qup2_se4"; 4760 drive-strength = <6>; 4761 bias-disable; 4762 }; 4763 4764 qup_spi13_cs: qup-spi13-cs-state { 4765 pins = "gpio23"; 4766 function = "qup2_se5"; 4767 drive-strength = <6>; 4768 bias-disable; 4769 }; 4770 4771 qup_spi13_data_clk: qup-spi13-data-clk-state { 4772 /* MISO, MOSI, CLK */ 4773 pins = "gpio20", "gpio21", "gpio22"; 4774 function = "qup2_se5"; 4775 drive-strength = <6>; 4776 bias-disable; 4777 }; 4778 4779 qup_spi14_cs: qup-spi14-cs-state { 4780 pins = "gpio27"; 4781 function = "qup2_se6"; 4782 drive-strength = <6>; 4783 bias-disable; 4784 }; 4785 4786 qup_spi14_data_clk: qup-spi14-data-clk-state { 4787 /* MISO, MOSI, CLK */ 4788 pins = "gpio24", "gpio25", "gpio26"; 4789 function = "qup2_se6"; 4790 drive-strength = <6>; 4791 bias-disable; 4792 }; 4793 4794 qup_uart14_default: qup-uart14-default-state { 4795 /* TX, RX */ 4796 pins = "gpio26", "gpio27"; 4797 function = "qup2_se6"; 4798 drive-strength = <2>; 4799 bias-pull-up; 4800 }; 4801 4802 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 4803 /* CTS, RTS */ 4804 pins = "gpio24", "gpio25"; 4805 function = "qup2_se6"; 4806 drive-strength = <2>; 4807 bias-pull-down; 4808 }; 4809 4810 qup_uart15_default: qup-uart15-default-state { 4811 /* TX, RX */ 4812 pins = "gpio30", "gpio31"; 4813 function = "qup2_se7"; 4814 drive-strength = <2>; 4815 bias-disable; 4816 }; 4817 4818 sdc2_sleep: sdc2-sleep-state { 4819 clk-pins { 4820 pins = "sdc2_clk"; 4821 drive-strength = <2>; 4822 bias-disable; 4823 }; 4824 4825 cmd-pins { 4826 pins = "sdc2_cmd"; 4827 drive-strength = <2>; 4828 bias-pull-up; 4829 }; 4830 4831 data-pins { 4832 pins = "sdc2_data"; 4833 drive-strength = <2>; 4834 bias-pull-up; 4835 }; 4836 }; 4837 4838 sdc2_default: sdc2-default-state { 4839 clk-pins { 4840 pins = "sdc2_clk"; 4841 drive-strength = <16>; 4842 bias-disable; 4843 }; 4844 4845 cmd-pins { 4846 pins = "sdc2_cmd"; 4847 drive-strength = <10>; 4848 bias-pull-up; 4849 }; 4850 4851 data-pins { 4852 pins = "sdc2_data"; 4853 drive-strength = <10>; 4854 bias-pull-up; 4855 }; 4856 }; 4857 }; 4858 4859 apps_smmu: iommu@15000000 { 4860 compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4861 reg = <0 0x15000000 0 0x100000>; 4862 4863 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4864 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4865 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4866 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4867 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4868 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4869 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4870 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4871 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4872 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4873 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4874 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4875 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4876 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4877 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4878 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4879 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4880 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4881 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4882 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4883 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4884 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4885 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4886 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4887 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4888 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4889 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4890 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4891 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4892 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4893 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4894 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4895 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4896 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4897 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4898 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4899 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4900 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4901 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4902 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4903 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4904 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4905 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4906 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4907 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4908 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4909 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4910 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4911 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4912 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4913 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4914 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4915 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4916 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4917 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4918 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4919 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4920 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4921 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4922 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4923 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4924 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4925 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4926 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4927 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4928 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4929 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4930 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4931 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4932 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4933 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4934 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4935 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4936 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4937 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4938 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4939 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4940 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4941 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4942 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4943 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4944 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4945 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4946 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4947 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4948 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4949 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4950 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4951 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4952 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4953 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4954 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4955 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4956 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4957 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4958 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4959 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 4960 4961 #iommu-cells = <2>; 4962 #global-interrupts = <1>; 4963 4964 dma-coherent; 4965 }; 4966 4967 intc: interrupt-controller@17100000 { 4968 compatible = "arm,gic-v3"; 4969 reg = <0 0x17100000 0 0x10000>, /* GICD */ 4970 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 4971 4972 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4973 4974 #interrupt-cells = <3>; 4975 interrupt-controller; 4976 4977 #redistributor-regions = <1>; 4978 redistributor-stride = <0 0x40000>; 4979 4980 #address-cells = <2>; 4981 #size-cells = <2>; 4982 ranges; 4983 4984 gic_its: msi-controller@17140000 { 4985 compatible = "arm,gic-v3-its"; 4986 reg = <0 0x17140000 0 0x20000>; 4987 4988 msi-controller; 4989 #msi-cells = <1>; 4990 }; 4991 }; 4992 4993 timer@17420000 { 4994 compatible = "arm,armv7-timer-mem"; 4995 reg = <0 0x17420000 0 0x1000>; 4996 4997 ranges = <0 0 0 0x20000000>; 4998 #address-cells = <1>; 4999 #size-cells = <1>; 5000 5001 frame@17421000 { 5002 reg = <0x17421000 0x1000>, 5003 <0x17422000 0x1000>; 5004 5005 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5006 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5007 5008 frame-number = <0>; 5009 }; 5010 5011 frame@17423000 { 5012 reg = <0x17423000 0x1000>; 5013 5014 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5015 5016 frame-number = <1>; 5017 5018 status = "disabled"; 5019 }; 5020 5021 frame@17425000 { 5022 reg = <0x17425000 0x1000>; 5023 5024 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5025 5026 frame-number = <2>; 5027 5028 status = "disabled"; 5029 }; 5030 5031 frame@17427000 { 5032 reg = <0x17427000 0x1000>; 5033 5034 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5035 5036 frame-number = <3>; 5037 5038 status = "disabled"; 5039 }; 5040 5041 frame@17429000 { 5042 reg = <0x17429000 0x1000>; 5043 5044 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5045 5046 frame-number = <4>; 5047 5048 status = "disabled"; 5049 }; 5050 5051 frame@1742b000 { 5052 reg = <0x1742b000 0x1000>; 5053 5054 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5055 5056 frame-number = <5>; 5057 5058 status = "disabled"; 5059 }; 5060 5061 frame@1742d000 { 5062 reg = <0x1742d000 0x1000>; 5063 5064 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5065 5066 frame-number = <6>; 5067 5068 status = "disabled"; 5069 }; 5070 }; 5071 5072 apps_rsc: rsc@17a00000 { 5073 compatible = "qcom,rpmh-rsc"; 5074 reg = <0 0x17a00000 0 0x10000>, 5075 <0 0x17a10000 0 0x10000>, 5076 <0 0x17a20000 0 0x10000>, 5077 <0 0x17a30000 0 0x10000>; 5078 reg-names = "drv-0", 5079 "drv-1", 5080 "drv-2"; 5081 5082 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5085 5086 power-domains = <&CLUSTER_PD>; 5087 5088 qcom,tcs-offset = <0xd00>; 5089 qcom,drv-id = <2>; 5090 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 5091 <WAKE_TCS 2>, <CONTROL_TCS 0>; 5092 5093 label = "apps_rsc"; 5094 5095 apps_bcm_voter: bcm-voter { 5096 compatible = "qcom,bcm-voter"; 5097 }; 5098 5099 rpmhcc: clock-controller { 5100 compatible = "qcom,sm8650-rpmh-clk"; 5101 5102 clocks = <&xo_board>; 5103 clock-names = "xo"; 5104 5105 #clock-cells = <1>; 5106 }; 5107 5108 rpmhpd: power-controller { 5109 compatible = "qcom,sm8650-rpmhpd"; 5110 5111 operating-points-v2 = <&rpmhpd_opp_table>; 5112 5113 #power-domain-cells = <1>; 5114 5115 rpmhpd_opp_table: opp-table { 5116 compatible = "operating-points-v2"; 5117 5118 rpmhpd_opp_ret: opp-16 { 5119 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5120 }; 5121 5122 rpmhpd_opp_min_svs: opp-48 { 5123 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5124 }; 5125 5126 rpmhpd_opp_low_svs_d2: opp-52 { 5127 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5128 }; 5129 5130 rpmhpd_opp_low_svs_d1: opp-56 { 5131 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5132 }; 5133 5134 rpmhpd_opp_low_svs_d0: opp-60 { 5135 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5136 }; 5137 5138 rpmhpd_opp_low_svs: opp-64 { 5139 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5140 }; 5141 5142 rpmhpd_opp_low_svs_l1: opp-80 { 5143 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5144 }; 5145 5146 rpmhpd_opp_svs: opp-128 { 5147 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5148 }; 5149 5150 rpmhpd_opp_svs_l0: opp-144 { 5151 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5152 }; 5153 5154 rpmhpd_opp_svs_l1: opp-192 { 5155 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5156 }; 5157 5158 rpmhpd_opp_nom: opp-256 { 5159 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5160 }; 5161 5162 rpmhpd_opp_nom_l1: opp-320 { 5163 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5164 }; 5165 5166 rpmhpd_opp_nom_l2: opp-336 { 5167 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5168 }; 5169 5170 rpmhpd_opp_turbo: opp-384 { 5171 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5172 }; 5173 5174 rpmhpd_opp_turbo_l1: opp-416 { 5175 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5176 }; 5177 }; 5178 }; 5179 }; 5180 5181 cpufreq_hw: cpufreq@17d91000 { 5182 compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss"; 5183 reg = <0 0x17d91000 0 0x1000>, 5184 <0 0x17d92000 0 0x1000>, 5185 <0 0x17d93000 0 0x1000>, 5186 <0 0x17d94000 0 0x1000>; 5187 reg-names = "freq-domain0", 5188 "freq-domain1", 5189 "freq-domain2", 5190 "freq-domain3"; 5191 5192 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5193 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5194 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 5195 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 5196 interrupt-names = "dcvsh-irq-0", 5197 "dcvsh-irq-1", 5198 "dcvsh-irq-2", 5199 "dcvsh-irq-3"; 5200 5201 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 5202 clock-names = "xo", "alternate"; 5203 5204 #freq-domain-cells = <1>; 5205 #clock-cells = <1>; 5206 }; 5207 5208 pmu@24091000 { 5209 compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 5210 reg = <0 0x24091000 0 0x1000>; 5211 5212 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 5213 5214 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 5215 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5216 5217 operating-points-v2 = <&llcc_bwmon_opp_table>; 5218 5219 llcc_bwmon_opp_table: opp-table { 5220 compatible = "operating-points-v2"; 5221 5222 opp-0 { 5223 opp-peak-kBps = <2086000>; 5224 }; 5225 5226 opp-1 { 5227 opp-peak-kBps = <2929000>; 5228 }; 5229 5230 opp-2 { 5231 opp-peak-kBps = <5931000>; 5232 }; 5233 5234 opp-3 { 5235 opp-peak-kBps = <6515000>; 5236 }; 5237 5238 opp-4 { 5239 opp-peak-kBps = <7980000>; 5240 }; 5241 5242 opp-5 { 5243 opp-peak-kBps = <10437000>; 5244 }; 5245 5246 opp-6 { 5247 opp-peak-kBps = <12157000>; 5248 }; 5249 5250 opp-7 { 5251 opp-peak-kBps = <14060000>; 5252 }; 5253 5254 opp-8 { 5255 opp-peak-kBps = <16113000>; 5256 }; 5257 }; 5258 }; 5259 5260 pmu@240b7400 { 5261 compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; 5262 reg = <0 0x240b7400 0 0x600>; 5263 5264 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5265 5266 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5267 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5268 5269 operating-points-v2 = <&cpu_bwmon_opp_table>; 5270 5271 cpu_bwmon_opp_table: opp-table { 5272 compatible = "operating-points-v2"; 5273 5274 opp-0 { 5275 opp-peak-kBps = <4577000>; 5276 }; 5277 5278 opp-1 { 5279 opp-peak-kBps = <7110000>; 5280 }; 5281 5282 opp-2 { 5283 opp-peak-kBps = <9155000>; 5284 }; 5285 5286 opp-3 { 5287 opp-peak-kBps = <12298000>; 5288 }; 5289 5290 opp-4 { 5291 opp-peak-kBps = <14236000>; 5292 }; 5293 5294 opp-5 { 5295 opp-peak-kBps = <16265000>; 5296 }; 5297 }; 5298 }; 5299 5300 gem_noc: interconnect@24100000 { 5301 compatible = "qcom,sm8650-gem-noc"; 5302 reg = <0 0x24100000 0 0xc5080>; 5303 5304 qcom,bcm-voters = <&apps_bcm_voter>; 5305 5306 #interconnect-cells = <2>; 5307 }; 5308 5309 system-cache-controller@25000000 { 5310 compatible = "qcom,sm8650-llcc"; 5311 reg = <0 0x25000000 0 0x200000>, 5312 <0 0x25400000 0 0x200000>, 5313 <0 0x25200000 0 0x200000>, 5314 <0 0x25600000 0 0x200000>, 5315 <0 0x25800000 0 0x200000>, 5316 <0 0x25a00000 0 0x200000>; 5317 reg-names = "llcc0_base", 5318 "llcc1_base", 5319 "llcc2_base", 5320 "llcc3_base", 5321 "llcc_broadcast_base", 5322 "llcc_broadcast_and_base"; 5323 5324 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 5325 }; 5326 5327 remoteproc_adsp: remoteproc@30000000 { 5328 compatible = "qcom,sm8650-adsp-pas"; 5329 reg = <0 0x30000000 0 0x100>; 5330 5331 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 5332 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5333 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5334 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5335 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5336 interrupt-names = "wdog", 5337 "fatal", 5338 "ready", 5339 "handover", 5340 "stop-ack"; 5341 5342 clocks = <&rpmhcc RPMH_CXO_CLK>; 5343 clock-names = "xo"; 5344 5345 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 5346 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5347 5348 power-domains = <&rpmhpd RPMHPD_LCX>, 5349 <&rpmhpd RPMHPD_LMX>; 5350 power-domain-names = "lcx", 5351 "lmx"; 5352 5353 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 5354 5355 qcom,qmp = <&aoss_qmp>; 5356 5357 qcom,smem-states = <&smp2p_adsp_out 0>; 5358 qcom,smem-state-names = "stop"; 5359 5360 status = "disabled"; 5361 5362 remoteproc_adsp_glink: glink-edge { 5363 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5364 IPCC_MPROC_SIGNAL_GLINK_QMP 5365 IRQ_TYPE_EDGE_RISING>; 5366 5367 mboxes = <&ipcc IPCC_CLIENT_LPASS 5368 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5369 5370 qcom,remote-pid = <2>; 5371 5372 label = "lpass"; 5373 5374 fastrpc { 5375 compatible = "qcom,fastrpc"; 5376 5377 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5378 5379 label = "adsp"; 5380 5381 qcom,non-secure-domain; 5382 5383 #address-cells = <1>; 5384 #size-cells = <0>; 5385 5386 compute-cb@3 { 5387 compatible = "qcom,fastrpc-compute-cb"; 5388 reg = <3>; 5389 5390 iommus = <&apps_smmu 0x1003 0x80>, 5391 <&apps_smmu 0x1043 0x20>; 5392 dma-coherent; 5393 }; 5394 5395 compute-cb@4 { 5396 compatible = "qcom,fastrpc-compute-cb"; 5397 reg = <4>; 5398 5399 iommus = <&apps_smmu 0x1004 0x80>, 5400 <&apps_smmu 0x1044 0x20>; 5401 dma-coherent; 5402 }; 5403 5404 compute-cb@5 { 5405 compatible = "qcom,fastrpc-compute-cb"; 5406 reg = <5>; 5407 5408 iommus = <&apps_smmu 0x1005 0x80>, 5409 <&apps_smmu 0x1045 0x20>; 5410 dma-coherent; 5411 }; 5412 5413 compute-cb@6 { 5414 compatible = "qcom,fastrpc-compute-cb"; 5415 reg = <6>; 5416 5417 iommus = <&apps_smmu 0x1006 0x80>, 5418 <&apps_smmu 0x1046 0x20>; 5419 dma-coherent; 5420 }; 5421 5422 compute-cb@7 { 5423 compatible = "qcom,fastrpc-compute-cb"; 5424 reg = <7>; 5425 5426 iommus = <&apps_smmu 0x1007 0x40>, 5427 <&apps_smmu 0x1067 0x0>, 5428 <&apps_smmu 0x1087 0x0>; 5429 dma-coherent; 5430 }; 5431 }; 5432 5433 gpr { 5434 compatible = "qcom,gpr"; 5435 qcom,glink-channels = "adsp_apps"; 5436 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 5437 qcom,intents = <512 20>; 5438 #address-cells = <1>; 5439 #size-cells = <0>; 5440 5441 q6apm: service@1 { 5442 compatible = "qcom,q6apm"; 5443 reg = <GPR_APM_MODULE_IID>; 5444 #sound-dai-cells = <0>; 5445 qcom,protection-domain = "avs/audio", 5446 "msm/adsp/audio_pd"; 5447 5448 q6apmbedai: bedais { 5449 compatible = "qcom,q6apm-lpass-dais"; 5450 #sound-dai-cells = <1>; 5451 }; 5452 5453 q6apmdai: dais { 5454 compatible = "qcom,q6apm-dais"; 5455 iommus = <&apps_smmu 0x1001 0x80>, 5456 <&apps_smmu 0x1061 0x0>; 5457 }; 5458 }; 5459 5460 q6prm: service@2 { 5461 compatible = "qcom,q6prm"; 5462 reg = <GPR_PRM_MODULE_IID>; 5463 qcom,protection-domain = "avs/audio", 5464 "msm/adsp/audio_pd"; 5465 5466 q6prmcc: clock-controller { 5467 compatible = "qcom,q6prm-lpass-clocks"; 5468 #clock-cells = <2>; 5469 }; 5470 }; 5471 }; 5472 }; 5473 }; 5474 5475 nsp_noc: interconnect@320c0000 { 5476 compatible = "qcom,sm8650-nsp-noc"; 5477 reg = <0 0x320c0000 0 0xf080>; 5478 5479 qcom,bcm-voters = <&apps_bcm_voter>; 5480 5481 #interconnect-cells = <2>; 5482 }; 5483 5484 remoteproc_cdsp: remoteproc@32300000 { 5485 compatible = "qcom,sm8650-cdsp-pas"; 5486 reg = <0 0x32300000 0 0x1400000>; 5487 5488 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5489 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 5490 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 5491 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 5492 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 5493 interrupt-names = "wdog", 5494 "fatal", 5495 "ready", 5496 "handover", 5497 "stop-ack"; 5498 5499 clocks = <&rpmhcc RPMH_CXO_CLK>; 5500 clock-names = "xo"; 5501 5502 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 5503 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5504 5505 power-domains = <&rpmhpd RPMHPD_CX>, 5506 <&rpmhpd RPMHPD_MXC>, 5507 <&rpmhpd RPMHPD_NSP>; 5508 power-domain-names = "cx", 5509 "mxc", 5510 "nsp"; 5511 5512 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; 5513 5514 qcom,qmp = <&aoss_qmp>; 5515 5516 qcom,smem-states = <&smp2p_cdsp_out 0>; 5517 qcom,smem-state-names = "stop"; 5518 5519 status = "disabled"; 5520 5521 glink-edge { 5522 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5523 IPCC_MPROC_SIGNAL_GLINK_QMP 5524 IRQ_TYPE_EDGE_RISING>; 5525 5526 mboxes = <&ipcc IPCC_CLIENT_CDSP 5527 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5528 5529 qcom,remote-pid = <5>; 5530 5531 label = "cdsp"; 5532 5533 fastrpc { 5534 compatible = "qcom,fastrpc"; 5535 5536 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5537 5538 label = "cdsp"; 5539 5540 qcom,non-secure-domain; 5541 5542 #address-cells = <1>; 5543 #size-cells = <0>; 5544 5545 compute-cb@1 { 5546 compatible = "qcom,fastrpc-compute-cb"; 5547 reg = <1>; 5548 5549 iommus = <&apps_smmu 0x1961 0x0>, 5550 <&apps_smmu 0x0c01 0x20>, 5551 <&apps_smmu 0x19c1 0x0>; 5552 dma-coherent; 5553 }; 5554 5555 compute-cb@2 { 5556 compatible = "qcom,fastrpc-compute-cb"; 5557 reg = <2>; 5558 5559 iommus = <&apps_smmu 0x1962 0x0>, 5560 <&apps_smmu 0x0c02 0x20>, 5561 <&apps_smmu 0x19c2 0x0>; 5562 dma-coherent; 5563 }; 5564 5565 compute-cb@3 { 5566 compatible = "qcom,fastrpc-compute-cb"; 5567 reg = <3>; 5568 5569 iommus = <&apps_smmu 0x1963 0x0>, 5570 <&apps_smmu 0x0c03 0x20>, 5571 <&apps_smmu 0x19c3 0x0>; 5572 dma-coherent; 5573 }; 5574 5575 compute-cb@4 { 5576 compatible = "qcom,fastrpc-compute-cb"; 5577 reg = <4>; 5578 5579 iommus = <&apps_smmu 0x1964 0x0>, 5580 <&apps_smmu 0x0c04 0x20>, 5581 <&apps_smmu 0x19c4 0x0>; 5582 dma-coherent; 5583 }; 5584 5585 compute-cb@5 { 5586 compatible = "qcom,fastrpc-compute-cb"; 5587 reg = <5>; 5588 5589 iommus = <&apps_smmu 0x1965 0x0>, 5590 <&apps_smmu 0x0c05 0x20>, 5591 <&apps_smmu 0x19c5 0x0>; 5592 dma-coherent; 5593 }; 5594 5595 compute-cb@6 { 5596 compatible = "qcom,fastrpc-compute-cb"; 5597 reg = <6>; 5598 5599 iommus = <&apps_smmu 0x1966 0x0>, 5600 <&apps_smmu 0x0c06 0x20>, 5601 <&apps_smmu 0x19c6 0x0>; 5602 dma-coherent; 5603 }; 5604 5605 compute-cb@7 { 5606 compatible = "qcom,fastrpc-compute-cb"; 5607 reg = <7>; 5608 5609 iommus = <&apps_smmu 0x1967 0x0>, 5610 <&apps_smmu 0x0c07 0x20>, 5611 <&apps_smmu 0x19c7 0x0>; 5612 dma-coherent; 5613 }; 5614 5615 compute-cb@8 { 5616 compatible = "qcom,fastrpc-compute-cb"; 5617 reg = <8>; 5618 5619 iommus = <&apps_smmu 0x1968 0x0>, 5620 <&apps_smmu 0x0c08 0x20>, 5621 <&apps_smmu 0x19c8 0x0>; 5622 dma-coherent; 5623 }; 5624 5625 /* note: secure cb9 in downstream */ 5626 5627 compute-cb@10 { 5628 compatible = "qcom,fastrpc-compute-cb"; 5629 reg = <12>; 5630 5631 iommus = <&apps_smmu 0x196c 0x0>, 5632 <&apps_smmu 0x0c0c 0x20>, 5633 <&apps_smmu 0x19cc 0x0>; 5634 dma-coherent; 5635 }; 5636 5637 compute-cb@11 { 5638 compatible = "qcom,fastrpc-compute-cb"; 5639 reg = <13>; 5640 5641 iommus = <&apps_smmu 0x196d 0x0>, 5642 <&apps_smmu 0x0c0d 0x20>, 5643 <&apps_smmu 0x19cd 0x0>; 5644 dma-coherent; 5645 }; 5646 5647 compute-cb@12 { 5648 compatible = "qcom,fastrpc-compute-cb"; 5649 reg = <14>; 5650 5651 iommus = <&apps_smmu 0x196e 0x0>, 5652 <&apps_smmu 0x0c0e 0x20>, 5653 <&apps_smmu 0x19ce 0x0>; 5654 dma-coherent; 5655 }; 5656 }; 5657 }; 5658 }; 5659 }; 5660 5661 thermal-zones { 5662 aoss0-thermal { 5663 thermal-sensors = <&tsens0 0>; 5664 5665 trips { 5666 trip-point0 { 5667 temperature = <90000>; 5668 hysteresis = <2000>; 5669 type = "hot"; 5670 }; 5671 5672 aoss0-critical { 5673 temperature = <110000>; 5674 hysteresis = <0>; 5675 type = "critical"; 5676 }; 5677 }; 5678 }; 5679 5680 cpuss0-thermal { 5681 thermal-sensors = <&tsens0 1>; 5682 5683 trips { 5684 trip-point0 { 5685 temperature = <90000>; 5686 hysteresis = <2000>; 5687 type = "hot"; 5688 }; 5689 5690 cpuss0-critical { 5691 temperature = <110000>; 5692 hysteresis = <0>; 5693 type = "critical"; 5694 }; 5695 }; 5696 }; 5697 5698 cpuss1-thermal { 5699 thermal-sensors = <&tsens0 2>; 5700 5701 trips { 5702 trip-point0 { 5703 temperature = <90000>; 5704 hysteresis = <2000>; 5705 type = "hot"; 5706 }; 5707 5708 cpuss1-critical { 5709 temperature = <110000>; 5710 hysteresis = <0>; 5711 type = "critical"; 5712 }; 5713 }; 5714 }; 5715 5716 cpuss2-thermal { 5717 thermal-sensors = <&tsens0 3>; 5718 5719 trips { 5720 trip-point0 { 5721 temperature = <90000>; 5722 hysteresis = <2000>; 5723 type = "hot"; 5724 }; 5725 5726 cpuss2-critical { 5727 temperature = <110000>; 5728 hysteresis = <0>; 5729 type = "critical"; 5730 }; 5731 }; 5732 }; 5733 5734 cpuss3-thermal { 5735 thermal-sensors = <&tsens0 4>; 5736 5737 trips { 5738 trip-point0 { 5739 temperature = <90000>; 5740 hysteresis = <2000>; 5741 type = "hot"; 5742 }; 5743 5744 cpuss3-critical { 5745 temperature = <110000>; 5746 hysteresis = <0>; 5747 type = "critical"; 5748 }; 5749 }; 5750 }; 5751 5752 cpu2-top-thermal { 5753 thermal-sensors = <&tsens0 5>; 5754 5755 trips { 5756 trip-point0 { 5757 temperature = <90000>; 5758 hysteresis = <2000>; 5759 type = "passive"; 5760 }; 5761 5762 trip-point1 { 5763 temperature = <95000>; 5764 hysteresis = <2000>; 5765 type = "passive"; 5766 }; 5767 5768 cpu2-critical { 5769 temperature = <110000>; 5770 hysteresis = <1000>; 5771 type = "critical"; 5772 }; 5773 }; 5774 }; 5775 5776 cpu2-bottom-thermal { 5777 thermal-sensors = <&tsens0 6>; 5778 5779 trips { 5780 trip-point0 { 5781 temperature = <90000>; 5782 hysteresis = <2000>; 5783 type = "passive"; 5784 }; 5785 5786 trip-point1 { 5787 temperature = <95000>; 5788 hysteresis = <2000>; 5789 type = "passive"; 5790 }; 5791 5792 cpu2-critical { 5793 temperature = <110000>; 5794 hysteresis = <1000>; 5795 type = "critical"; 5796 }; 5797 }; 5798 }; 5799 5800 cpu3-top-thermal { 5801 thermal-sensors = <&tsens0 7>; 5802 5803 trips { 5804 trip-point0 { 5805 temperature = <90000>; 5806 hysteresis = <2000>; 5807 type = "passive"; 5808 }; 5809 5810 trip-point1 { 5811 temperature = <95000>; 5812 hysteresis = <2000>; 5813 type = "passive"; 5814 }; 5815 5816 cpu3-critical { 5817 temperature = <110000>; 5818 hysteresis = <1000>; 5819 type = "critical"; 5820 }; 5821 }; 5822 }; 5823 5824 cpu3-bottom-thermal { 5825 thermal-sensors = <&tsens0 8>; 5826 5827 trips { 5828 trip-point0 { 5829 temperature = <90000>; 5830 hysteresis = <2000>; 5831 type = "passive"; 5832 }; 5833 5834 trip-point1 { 5835 temperature = <95000>; 5836 hysteresis = <2000>; 5837 type = "passive"; 5838 }; 5839 5840 cpu3-critical { 5841 temperature = <110000>; 5842 hysteresis = <1000>; 5843 type = "critical"; 5844 }; 5845 }; 5846 }; 5847 5848 cpu4-top-thermal { 5849 thermal-sensors = <&tsens0 9>; 5850 5851 trips { 5852 trip-point0 { 5853 temperature = <90000>; 5854 hysteresis = <2000>; 5855 type = "passive"; 5856 }; 5857 5858 trip-point1 { 5859 temperature = <95000>; 5860 hysteresis = <2000>; 5861 type = "passive"; 5862 }; 5863 5864 cpu4-critical { 5865 temperature = <110000>; 5866 hysteresis = <1000>; 5867 type = "critical"; 5868 }; 5869 }; 5870 }; 5871 5872 cpu4-bottom-thermal { 5873 thermal-sensors = <&tsens0 10>; 5874 5875 trips { 5876 trip-point0 { 5877 temperature = <90000>; 5878 hysteresis = <2000>; 5879 type = "passive"; 5880 }; 5881 5882 trip-point1 { 5883 temperature = <95000>; 5884 hysteresis = <2000>; 5885 type = "passive"; 5886 }; 5887 5888 cpu4-critical { 5889 temperature = <110000>; 5890 hysteresis = <1000>; 5891 type = "critical"; 5892 }; 5893 }; 5894 }; 5895 5896 cpu5-top-thermal { 5897 thermal-sensors = <&tsens0 11>; 5898 5899 trips { 5900 trip-point0 { 5901 temperature = <90000>; 5902 hysteresis = <2000>; 5903 type = "passive"; 5904 }; 5905 5906 trip-point1 { 5907 temperature = <95000>; 5908 hysteresis = <2000>; 5909 type = "passive"; 5910 }; 5911 5912 cpu5-critical { 5913 temperature = <110000>; 5914 hysteresis = <1000>; 5915 type = "critical"; 5916 }; 5917 }; 5918 }; 5919 5920 cpu5-bottom-thermal { 5921 thermal-sensors = <&tsens0 12>; 5922 5923 trips { 5924 trip-point0 { 5925 temperature = <90000>; 5926 hysteresis = <2000>; 5927 type = "passive"; 5928 }; 5929 5930 trip-point1 { 5931 temperature = <95000>; 5932 hysteresis = <2000>; 5933 type = "passive"; 5934 }; 5935 5936 cpu5-critical { 5937 temperature = <110000>; 5938 hysteresis = <1000>; 5939 type = "critical"; 5940 }; 5941 }; 5942 }; 5943 5944 cpu6-top-thermal { 5945 thermal-sensors = <&tsens0 13>; 5946 5947 trips { 5948 trip-point0 { 5949 temperature = <90000>; 5950 hysteresis = <2000>; 5951 type = "passive"; 5952 }; 5953 5954 trip-point1 { 5955 temperature = <95000>; 5956 hysteresis = <2000>; 5957 type = "passive"; 5958 }; 5959 5960 cpu6-critical { 5961 temperature = <110000>; 5962 hysteresis = <1000>; 5963 type = "critical"; 5964 }; 5965 }; 5966 }; 5967 5968 cpu6-bottom-thermal { 5969 thermal-sensors = <&tsens0 14>; 5970 5971 trips { 5972 trip-point0 { 5973 temperature = <90000>; 5974 hysteresis = <2000>; 5975 type = "passive"; 5976 }; 5977 5978 trip-point1 { 5979 temperature = <95000>; 5980 hysteresis = <2000>; 5981 type = "passive"; 5982 }; 5983 5984 cpu6-critical { 5985 temperature = <110000>; 5986 hysteresis = <1000>; 5987 type = "critical"; 5988 }; 5989 }; 5990 }; 5991 5992 aoss1-thermal { 5993 thermal-sensors = <&tsens1 0>; 5994 5995 trips { 5996 trip-point0 { 5997 temperature = <90000>; 5998 hysteresis = <2000>; 5999 type = "hot"; 6000 }; 6001 6002 aoss1-critical { 6003 temperature = <110000>; 6004 hysteresis = <0>; 6005 type = "critical"; 6006 }; 6007 }; 6008 }; 6009 6010 cpu7-top-thermal { 6011 thermal-sensors = <&tsens1 1>; 6012 6013 trips { 6014 trip-point0 { 6015 temperature = <90000>; 6016 hysteresis = <2000>; 6017 type = "passive"; 6018 }; 6019 6020 trip-point1 { 6021 temperature = <95000>; 6022 hysteresis = <2000>; 6023 type = "passive"; 6024 }; 6025 6026 cpu7-critical { 6027 temperature = <110000>; 6028 hysteresis = <1000>; 6029 type = "critical"; 6030 }; 6031 }; 6032 }; 6033 6034 cpu7-middle-thermal { 6035 thermal-sensors = <&tsens1 2>; 6036 6037 trips { 6038 trip-point0 { 6039 temperature = <90000>; 6040 hysteresis = <2000>; 6041 type = "passive"; 6042 }; 6043 6044 trip-point1 { 6045 temperature = <95000>; 6046 hysteresis = <2000>; 6047 type = "passive"; 6048 }; 6049 6050 cpu7-critical { 6051 temperature = <110000>; 6052 hysteresis = <1000>; 6053 type = "critical"; 6054 }; 6055 }; 6056 }; 6057 6058 cpu7-bottom-thermal { 6059 thermal-sensors = <&tsens1 3>; 6060 6061 trips { 6062 trip-point0 { 6063 temperature = <90000>; 6064 hysteresis = <2000>; 6065 type = "passive"; 6066 }; 6067 6068 trip-point1 { 6069 temperature = <95000>; 6070 hysteresis = <2000>; 6071 type = "passive"; 6072 }; 6073 6074 cpu7-critical { 6075 temperature = <110000>; 6076 hysteresis = <1000>; 6077 type = "critical"; 6078 }; 6079 }; 6080 }; 6081 6082 cpu0-thermal { 6083 thermal-sensors = <&tsens1 4>; 6084 6085 trips { 6086 trip-point0 { 6087 temperature = <90000>; 6088 hysteresis = <2000>; 6089 type = "passive"; 6090 }; 6091 6092 trip-point1 { 6093 temperature = <95000>; 6094 hysteresis = <2000>; 6095 type = "passive"; 6096 }; 6097 6098 cpu0-critical { 6099 temperature = <110000>; 6100 hysteresis = <1000>; 6101 type = "critical"; 6102 }; 6103 }; 6104 }; 6105 6106 cpu1-thermal { 6107 thermal-sensors = <&tsens1 5>; 6108 6109 trips { 6110 trip-point0 { 6111 temperature = <90000>; 6112 hysteresis = <2000>; 6113 type = "passive"; 6114 }; 6115 6116 trip-point1 { 6117 temperature = <95000>; 6118 hysteresis = <2000>; 6119 type = "passive"; 6120 }; 6121 6122 cpu1-critical { 6123 temperature = <110000>; 6124 hysteresis = <1000>; 6125 type = "critical"; 6126 }; 6127 }; 6128 }; 6129 6130 nsphvx0-thermal { 6131 polling-delay-passive = <10>; 6132 6133 thermal-sensors = <&tsens2 6>; 6134 6135 trips { 6136 trip-point0 { 6137 temperature = <90000>; 6138 hysteresis = <2000>; 6139 type = "hot"; 6140 }; 6141 6142 nsphvx1-critical { 6143 temperature = <110000>; 6144 hysteresis = <0>; 6145 type = "critical"; 6146 }; 6147 }; 6148 }; 6149 6150 nsphvx1-thermal { 6151 polling-delay-passive = <10>; 6152 6153 thermal-sensors = <&tsens2 7>; 6154 6155 trips { 6156 trip-point0 { 6157 temperature = <90000>; 6158 hysteresis = <2000>; 6159 type = "hot"; 6160 }; 6161 6162 nsphvx1-critical { 6163 temperature = <110000>; 6164 hysteresis = <0>; 6165 type = "critical"; 6166 }; 6167 }; 6168 }; 6169 6170 nsphmx0-thermal { 6171 polling-delay-passive = <10>; 6172 6173 thermal-sensors = <&tsens2 8>; 6174 6175 trips { 6176 trip-point0 { 6177 temperature = <90000>; 6178 hysteresis = <2000>; 6179 type = "hot"; 6180 }; 6181 6182 nsphmx0-critical { 6183 temperature = <110000>; 6184 hysteresis = <0>; 6185 type = "critical"; 6186 }; 6187 }; 6188 }; 6189 6190 nsphmx1-thermal { 6191 polling-delay-passive = <10>; 6192 6193 thermal-sensors = <&tsens2 9>; 6194 6195 trips { 6196 trip-point0 { 6197 temperature = <90000>; 6198 hysteresis = <2000>; 6199 type = "hot"; 6200 }; 6201 6202 nsphmx1-critical { 6203 temperature = <110000>; 6204 hysteresis = <0>; 6205 type = "critical"; 6206 }; 6207 }; 6208 }; 6209 6210 nsphmx2-thermal { 6211 polling-delay-passive = <10>; 6212 6213 thermal-sensors = <&tsens2 10>; 6214 6215 trips { 6216 trip-point0 { 6217 temperature = <90000>; 6218 hysteresis = <2000>; 6219 type = "hot"; 6220 }; 6221 6222 nsphmx2-critical { 6223 temperature = <110000>; 6224 hysteresis = <0>; 6225 type = "critical"; 6226 }; 6227 }; 6228 }; 6229 6230 nsphmx3-thermal { 6231 polling-delay-passive = <10>; 6232 6233 thermal-sensors = <&tsens2 11>; 6234 6235 trips { 6236 trip-point0 { 6237 temperature = <90000>; 6238 hysteresis = <2000>; 6239 type = "hot"; 6240 }; 6241 6242 nsphmx3-critical { 6243 temperature = <110000>; 6244 hysteresis = <0>; 6245 type = "critical"; 6246 }; 6247 }; 6248 }; 6249 6250 video-thermal { 6251 polling-delay-passive = <10>; 6252 6253 thermal-sensors = <&tsens1 12>; 6254 6255 trips { 6256 trip-point0 { 6257 temperature = <90000>; 6258 hysteresis = <2000>; 6259 type = "hot"; 6260 }; 6261 6262 video-critical { 6263 temperature = <110000>; 6264 hysteresis = <0>; 6265 type = "critical"; 6266 }; 6267 }; 6268 }; 6269 6270 ddr-thermal { 6271 polling-delay-passive = <10>; 6272 6273 thermal-sensors = <&tsens1 13>; 6274 6275 trips { 6276 trip-point0 { 6277 temperature = <90000>; 6278 hysteresis = <2000>; 6279 type = "hot"; 6280 }; 6281 6282 ddr-critical { 6283 temperature = <110000>; 6284 hysteresis = <0>; 6285 type = "critical"; 6286 }; 6287 }; 6288 }; 6289 6290 camera0-thermal { 6291 thermal-sensors = <&tsens1 14>; 6292 6293 trips { 6294 trip-point0 { 6295 temperature = <90000>; 6296 hysteresis = <2000>; 6297 type = "hot"; 6298 }; 6299 6300 camera0-critical { 6301 temperature = <110000>; 6302 hysteresis = <0>; 6303 type = "critical"; 6304 }; 6305 }; 6306 }; 6307 6308 camera1-thermal { 6309 thermal-sensors = <&tsens1 15>; 6310 6311 trips { 6312 trip-point0 { 6313 temperature = <90000>; 6314 hysteresis = <2000>; 6315 type = "hot"; 6316 }; 6317 6318 camera1-critical { 6319 temperature = <110000>; 6320 hysteresis = <0>; 6321 type = "critical"; 6322 }; 6323 }; 6324 }; 6325 6326 aoss2-thermal { 6327 thermal-sensors = <&tsens2 0>; 6328 6329 trips { 6330 trip-point0 { 6331 temperature = <90000>; 6332 hysteresis = <2000>; 6333 type = "hot"; 6334 }; 6335 6336 aoss2-critical { 6337 temperature = <110000>; 6338 hysteresis = <0>; 6339 type = "critical"; 6340 }; 6341 }; 6342 }; 6343 6344 gpuss0-thermal { 6345 polling-delay-passive = <10>; 6346 6347 thermal-sensors = <&tsens2 1>; 6348 6349 cooling-maps { 6350 map0 { 6351 trip = <&gpu0_alert0>; 6352 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6353 }; 6354 }; 6355 6356 trips { 6357 gpu0_alert0: trip-point0 { 6358 temperature = <85000>; 6359 hysteresis = <1000>; 6360 type = "passive"; 6361 }; 6362 6363 trip-point1 { 6364 temperature = <90000>; 6365 hysteresis = <1000>; 6366 type = "hot"; 6367 }; 6368 6369 trip-point2 { 6370 temperature = <110000>; 6371 hysteresis = <1000>; 6372 type = "critical"; 6373 }; 6374 }; 6375 }; 6376 6377 gpuss1-thermal { 6378 polling-delay-passive = <10>; 6379 6380 thermal-sensors = <&tsens2 2>; 6381 6382 cooling-maps { 6383 map0 { 6384 trip = <&gpu1_alert0>; 6385 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6386 }; 6387 }; 6388 6389 trips { 6390 gpu1_alert0: trip-point0 { 6391 temperature = <85000>; 6392 hysteresis = <1000>; 6393 type = "passive"; 6394 }; 6395 6396 trip-point1 { 6397 temperature = <90000>; 6398 hysteresis = <1000>; 6399 type = "hot"; 6400 }; 6401 6402 trip-point2 { 6403 temperature = <110000>; 6404 hysteresis = <1000>; 6405 type = "critical"; 6406 }; 6407 }; 6408 }; 6409 6410 gpuss2-thermal { 6411 polling-delay-passive = <10>; 6412 6413 thermal-sensors = <&tsens2 3>; 6414 6415 cooling-maps { 6416 map0 { 6417 trip = <&gpu2_alert0>; 6418 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6419 }; 6420 }; 6421 6422 trips { 6423 gpu2_alert0: trip-point0 { 6424 temperature = <85000>; 6425 hysteresis = <1000>; 6426 type = "passive"; 6427 }; 6428 6429 trip-point1 { 6430 temperature = <90000>; 6431 hysteresis = <1000>; 6432 type = "hot"; 6433 }; 6434 6435 trip-point2 { 6436 temperature = <110000>; 6437 hysteresis = <1000>; 6438 type = "critical"; 6439 }; 6440 }; 6441 }; 6442 6443 gpuss3-thermal { 6444 polling-delay-passive = <10>; 6445 6446 thermal-sensors = <&tsens2 4>; 6447 6448 cooling-maps { 6449 map0 { 6450 trip = <&gpu3_alert0>; 6451 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6452 }; 6453 }; 6454 6455 trips { 6456 gpu3_alert0: trip-point0 { 6457 temperature = <85000>; 6458 hysteresis = <1000>; 6459 type = "passive"; 6460 }; 6461 6462 trip-point1 { 6463 temperature = <90000>; 6464 hysteresis = <1000>; 6465 type = "hot"; 6466 }; 6467 6468 trip-point2 { 6469 temperature = <110000>; 6470 hysteresis = <1000>; 6471 type = "critical"; 6472 }; 6473 }; 6474 }; 6475 6476 gpuss4-thermal { 6477 polling-delay-passive = <10>; 6478 6479 thermal-sensors = <&tsens2 5>; 6480 6481 cooling-maps { 6482 map0 { 6483 trip = <&gpu4_alert0>; 6484 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6485 }; 6486 }; 6487 6488 trips { 6489 gpu4_alert0: trip-point0 { 6490 temperature = <85000>; 6491 hysteresis = <1000>; 6492 type = "passive"; 6493 }; 6494 6495 trip-point1 { 6496 temperature = <90000>; 6497 hysteresis = <1000>; 6498 type = "hot"; 6499 }; 6500 6501 trip-point2 { 6502 temperature = <110000>; 6503 hysteresis = <1000>; 6504 type = "critical"; 6505 }; 6506 }; 6507 }; 6508 6509 gpuss5-thermal { 6510 polling-delay-passive = <10>; 6511 6512 thermal-sensors = <&tsens2 6>; 6513 6514 cooling-maps { 6515 map0 { 6516 trip = <&gpu5_alert0>; 6517 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6518 }; 6519 }; 6520 6521 trips { 6522 gpu5_alert0: trip-point0 { 6523 temperature = <85000>; 6524 hysteresis = <1000>; 6525 type = "passive"; 6526 }; 6527 6528 trip-point1 { 6529 temperature = <90000>; 6530 hysteresis = <1000>; 6531 type = "hot"; 6532 }; 6533 6534 trip-point2 { 6535 temperature = <110000>; 6536 hysteresis = <1000>; 6537 type = "critical"; 6538 }; 6539 }; 6540 }; 6541 6542 gpuss6-thermal { 6543 polling-delay-passive = <10>; 6544 6545 thermal-sensors = <&tsens2 7>; 6546 6547 cooling-maps { 6548 map0 { 6549 trip = <&gpu6_alert0>; 6550 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6551 }; 6552 }; 6553 6554 trips { 6555 gpu6_alert0: trip-point0 { 6556 temperature = <85000>; 6557 hysteresis = <1000>; 6558 type = "passive"; 6559 }; 6560 6561 trip-point1 { 6562 temperature = <90000>; 6563 hysteresis = <1000>; 6564 type = "hot"; 6565 }; 6566 6567 trip-point2 { 6568 temperature = <110000>; 6569 hysteresis = <1000>; 6570 type = "critical"; 6571 }; 6572 }; 6573 }; 6574 6575 gpuss7-thermal { 6576 polling-delay-passive = <10>; 6577 6578 thermal-sensors = <&tsens2 8>; 6579 6580 cooling-maps { 6581 map0 { 6582 trip = <&gpu7_alert0>; 6583 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6584 }; 6585 }; 6586 6587 trips { 6588 gpu7_alert0: trip-point0 { 6589 temperature = <85000>; 6590 hysteresis = <1000>; 6591 type = "passive"; 6592 }; 6593 6594 trip-point1 { 6595 temperature = <90000>; 6596 hysteresis = <1000>; 6597 type = "hot"; 6598 }; 6599 6600 trip-point2 { 6601 temperature = <110000>; 6602 hysteresis = <1000>; 6603 type = "critical"; 6604 }; 6605 }; 6606 }; 6607 6608 modem0-thermal { 6609 thermal-sensors = <&tsens2 9>; 6610 6611 trips { 6612 trip-point0 { 6613 temperature = <90000>; 6614 hysteresis = <2000>; 6615 type = "hot"; 6616 }; 6617 6618 modem0-critical { 6619 temperature = <110000>; 6620 hysteresis = <0>; 6621 type = "critical"; 6622 }; 6623 }; 6624 }; 6625 6626 modem1-thermal { 6627 thermal-sensors = <&tsens2 10>; 6628 6629 trips { 6630 trip-point0 { 6631 temperature = <90000>; 6632 hysteresis = <2000>; 6633 type = "hot"; 6634 }; 6635 6636 modem1-critical { 6637 temperature = <110000>; 6638 hysteresis = <0>; 6639 type = "critical"; 6640 }; 6641 }; 6642 }; 6643 6644 modem2-thermal { 6645 thermal-sensors = <&tsens2 11>; 6646 6647 trips { 6648 trip-point0 { 6649 temperature = <90000>; 6650 hysteresis = <2000>; 6651 type = "hot"; 6652 }; 6653 6654 modem2-critical { 6655 temperature = <110000>; 6656 hysteresis = <0>; 6657 type = "critical"; 6658 }; 6659 }; 6660 }; 6661 6662 modem3-thermal { 6663 thermal-sensors = <&tsens2 12>; 6664 6665 trips { 6666 trip-point0 { 6667 temperature = <90000>; 6668 hysteresis = <2000>; 6669 type = "hot"; 6670 }; 6671 6672 modem3-critical { 6673 temperature = <110000>; 6674 hysteresis = <0>; 6675 type = "critical"; 6676 }; 6677 }; 6678 }; 6679 }; 6680 6681 timer { 6682 compatible = "arm,armv8-timer"; 6683 6684 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6685 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6686 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6687 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6688 }; 6689}; 6690