1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sm8450-videocc.h> 9#include <dt-bindings/clock/qcom,sm8550-camcc.h> 10#include <dt-bindings/clock/qcom,sm8550-gcc.h> 11#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 12#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 13#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 14#include <dt-bindings/dma/qcom-gpi.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/interconnect/qcom,icc.h> 19#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/power/qcom,rpmhpd.h> 23#include <dt-bindings/soc/qcom,gpr.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 26#include <dt-bindings/phy/phy-qcom-qmp.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 chosen { }; 36 37 clocks { 38 xo_board: xo-board { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 }; 47 48 bi_tcxo_div2: bi-tcxo-div2-clk { 49 #clock-cells = <0>; 50 compatible = "fixed-factor-clock"; 51 clocks = <&rpmhcc RPMH_CXO_CLK>; 52 clock-mult = <1>; 53 clock-div = <2>; 54 }; 55 56 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 57 #clock-cells = <0>; 58 compatible = "fixed-factor-clock"; 59 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 60 clock-mult = <1>; 61 clock-div = <2>; 62 }; 63 }; 64 65 cpus { 66 #address-cells = <2>; 67 #size-cells = <0>; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a510"; 72 reg = <0 0>; 73 clocks = <&cpufreq_hw 0>; 74 enable-method = "psci"; 75 next-level-cache = <&l2_0>; 76 power-domains = <&cpu_pd0>; 77 power-domain-names = "psci"; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 capacity-dmips-mhz = <326>; 80 dynamic-power-coefficient = <251>; 81 #cooling-cells = <2>; 82 l2_0: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 cache-unified; 86 next-level-cache = <&l3_0>; 87 l3_0: l3-cache { 88 compatible = "cache"; 89 cache-level = <3>; 90 cache-unified; 91 }; 92 }; 93 }; 94 95 cpu1: cpu@100 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a510"; 98 reg = <0 0x100>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 next-level-cache = <&l2_100>; 102 power-domains = <&cpu_pd1>; 103 power-domain-names = "psci"; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 capacity-dmips-mhz = <326>; 106 dynamic-power-coefficient = <251>; 107 #cooling-cells = <2>; 108 l2_100: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&l3_0>; 113 }; 114 }; 115 116 cpu2: cpu@200 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a510"; 119 reg = <0 0x200>; 120 clocks = <&cpufreq_hw 0>; 121 enable-method = "psci"; 122 next-level-cache = <&l2_200>; 123 power-domains = <&cpu_pd2>; 124 power-domain-names = "psci"; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 capacity-dmips-mhz = <326>; 127 dynamic-power-coefficient = <251>; 128 #cooling-cells = <2>; 129 l2_200: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 next-level-cache = <&l3_0>; 134 }; 135 }; 136 137 cpu3: cpu@300 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a715"; 140 reg = <0 0x300>; 141 clocks = <&cpufreq_hw 1>; 142 enable-method = "psci"; 143 next-level-cache = <&l2_300>; 144 power-domains = <&cpu_pd3>; 145 power-domain-names = "psci"; 146 qcom,freq-domain = <&cpufreq_hw 1>; 147 capacity-dmips-mhz = <693>; 148 dynamic-power-coefficient = <447>; 149 #cooling-cells = <2>; 150 l2_300: l2-cache { 151 compatible = "cache"; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&l3_0>; 155 }; 156 }; 157 158 cpu4: cpu@400 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a715"; 161 reg = <0 0x400>; 162 clocks = <&cpufreq_hw 1>; 163 enable-method = "psci"; 164 next-level-cache = <&l2_400>; 165 power-domains = <&cpu_pd4>; 166 power-domain-names = "psci"; 167 qcom,freq-domain = <&cpufreq_hw 1>; 168 capacity-dmips-mhz = <693>; 169 dynamic-power-coefficient = <447>; 170 #cooling-cells = <2>; 171 l2_400: l2-cache { 172 compatible = "cache"; 173 cache-level = <2>; 174 cache-unified; 175 next-level-cache = <&l3_0>; 176 }; 177 }; 178 179 cpu5: cpu@500 { 180 device_type = "cpu"; 181 compatible = "arm,cortex-a710"; 182 reg = <0 0x500>; 183 clocks = <&cpufreq_hw 1>; 184 enable-method = "psci"; 185 next-level-cache = <&l2_500>; 186 power-domains = <&cpu_pd5>; 187 power-domain-names = "psci"; 188 qcom,freq-domain = <&cpufreq_hw 1>; 189 capacity-dmips-mhz = <693>; 190 dynamic-power-coefficient = <447>; 191 #cooling-cells = <2>; 192 l2_500: l2-cache { 193 compatible = "cache"; 194 cache-level = <2>; 195 cache-unified; 196 next-level-cache = <&l3_0>; 197 }; 198 }; 199 200 cpu6: cpu@600 { 201 device_type = "cpu"; 202 compatible = "arm,cortex-a710"; 203 reg = <0 0x600>; 204 clocks = <&cpufreq_hw 1>; 205 enable-method = "psci"; 206 next-level-cache = <&l2_600>; 207 power-domains = <&cpu_pd6>; 208 power-domain-names = "psci"; 209 qcom,freq-domain = <&cpufreq_hw 1>; 210 capacity-dmips-mhz = <693>; 211 dynamic-power-coefficient = <447>; 212 #cooling-cells = <2>; 213 l2_600: l2-cache { 214 compatible = "cache"; 215 cache-level = <2>; 216 cache-unified; 217 next-level-cache = <&l3_0>; 218 }; 219 }; 220 221 cpu7: cpu@700 { 222 device_type = "cpu"; 223 compatible = "arm,cortex-x3"; 224 reg = <0 0x700>; 225 clocks = <&cpufreq_hw 2>; 226 enable-method = "psci"; 227 next-level-cache = <&l2_700>; 228 power-domains = <&cpu_pd7>; 229 power-domain-names = "psci"; 230 qcom,freq-domain = <&cpufreq_hw 2>; 231 capacity-dmips-mhz = <1024>; 232 dynamic-power-coefficient = <1057>; 233 #cooling-cells = <2>; 234 l2_700: l2-cache { 235 compatible = "cache"; 236 cache-level = <2>; 237 cache-unified; 238 next-level-cache = <&l3_0>; 239 }; 240 }; 241 242 cpu-map { 243 cluster0 { 244 core0 { 245 cpu = <&cpu0>; 246 }; 247 248 core1 { 249 cpu = <&cpu1>; 250 }; 251 252 core2 { 253 cpu = <&cpu2>; 254 }; 255 256 core3 { 257 cpu = <&cpu3>; 258 }; 259 260 core4 { 261 cpu = <&cpu4>; 262 }; 263 264 core5 { 265 cpu = <&cpu5>; 266 }; 267 268 core6 { 269 cpu = <&cpu6>; 270 }; 271 272 core7 { 273 cpu = <&cpu7>; 274 }; 275 }; 276 }; 277 278 idle-states { 279 entry-method = "psci"; 280 281 little_cpu_sleep_0: cpu-sleep-0-0 { 282 compatible = "arm,idle-state"; 283 idle-state-name = "silver-rail-power-collapse"; 284 arm,psci-suspend-param = <0x40000004>; 285 entry-latency-us = <550>; 286 exit-latency-us = <750>; 287 min-residency-us = <6700>; 288 local-timer-stop; 289 }; 290 291 big_cpu_sleep_0: cpu-sleep-1-0 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "gold-rail-power-collapse"; 294 arm,psci-suspend-param = <0x40000004>; 295 entry-latency-us = <600>; 296 exit-latency-us = <1300>; 297 min-residency-us = <8136>; 298 local-timer-stop; 299 }; 300 301 prime_cpu_sleep_0: cpu-sleep-2-0 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "goldplus-rail-power-collapse"; 304 arm,psci-suspend-param = <0x40000004>; 305 entry-latency-us = <500>; 306 exit-latency-us = <1350>; 307 min-residency-us = <7480>; 308 local-timer-stop; 309 }; 310 }; 311 312 domain-idle-states { 313 cluster_sleep_0: cluster-sleep-0 { 314 compatible = "domain-idle-state"; 315 arm,psci-suspend-param = <0x41000044>; 316 entry-latency-us = <750>; 317 exit-latency-us = <2350>; 318 min-residency-us = <9144>; 319 }; 320 321 cluster_sleep_1: cluster-sleep-1 { 322 compatible = "domain-idle-state"; 323 arm,psci-suspend-param = <0x4100c344>; 324 entry-latency-us = <2800>; 325 exit-latency-us = <4400>; 326 min-residency-us = <10150>; 327 }; 328 }; 329 }; 330 331 firmware { 332 scm: scm { 333 compatible = "qcom,scm-sm8550", "qcom,scm"; 334 qcom,dload-mode = <&tcsr 0x19000>; 335 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 336 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 337 }; 338 }; 339 340 clk_virt: interconnect-0 { 341 compatible = "qcom,sm8550-clk-virt"; 342 #interconnect-cells = <2>; 343 qcom,bcm-voters = <&apps_bcm_voter>; 344 }; 345 346 mc_virt: interconnect-1 { 347 compatible = "qcom,sm8550-mc-virt"; 348 #interconnect-cells = <2>; 349 qcom,bcm-voters = <&apps_bcm_voter>; 350 }; 351 352 qup_opp_table_100mhz: opp-table-qup100mhz { 353 compatible = "operating-points-v2"; 354 355 opp-75000000 { 356 opp-hz = /bits/ 64 <75000000>; 357 required-opps = <&rpmhpd_opp_low_svs>; 358 }; 359 360 opp-100000000 { 361 opp-hz = /bits/ 64 <100000000>; 362 required-opps = <&rpmhpd_opp_svs>; 363 }; 364 }; 365 366 qup_opp_table_120mhz: opp-table-qup120mhz { 367 compatible = "operating-points-v2"; 368 369 opp-75000000 { 370 opp-hz = /bits/ 64 <75000000>; 371 required-opps = <&rpmhpd_opp_low_svs>; 372 }; 373 374 opp-120000000 { 375 opp-hz = /bits/ 64 <120000000>; 376 required-opps = <&rpmhpd_opp_svs>; 377 }; 378 }; 379 380 qup_opp_table_125mhz: opp-table-qup125mhz { 381 compatible = "operating-points-v2"; 382 383 opp-75000000 { 384 opp-hz = /bits/ 64 <75000000>; 385 required-opps = <&rpmhpd_opp_low_svs>; 386 }; 387 388 opp-125000000 { 389 opp-hz = /bits/ 64 <125000000>; 390 required-opps = <&rpmhpd_opp_svs>; 391 }; 392 }; 393 394 memory@a0000000 { 395 device_type = "memory"; 396 /* We expect the bootloader to fill in the size */ 397 reg = <0 0xa0000000 0 0>; 398 }; 399 400 pmu-a510 { 401 compatible = "arm,cortex-a510-pmu"; 402 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 403 }; 404 405 pmu-a710 { 406 compatible = "arm,cortex-a710-pmu"; 407 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 408 }; 409 410 pmu-a715 { 411 compatible = "arm,cortex-a715-pmu"; 412 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster2>; 413 }; 414 415 pmu-x3 { 416 compatible = "arm,cortex-x3-pmu"; 417 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster3>; 418 }; 419 420 psci { 421 compatible = "arm,psci-1.0"; 422 method = "smc"; 423 424 cpu_pd0: power-domain-cpu0 { 425 #power-domain-cells = <0>; 426 power-domains = <&cluster_pd>; 427 domain-idle-states = <&little_cpu_sleep_0>; 428 }; 429 430 cpu_pd1: power-domain-cpu1 { 431 #power-domain-cells = <0>; 432 power-domains = <&cluster_pd>; 433 domain-idle-states = <&little_cpu_sleep_0>; 434 }; 435 436 cpu_pd2: power-domain-cpu2 { 437 #power-domain-cells = <0>; 438 power-domains = <&cluster_pd>; 439 domain-idle-states = <&little_cpu_sleep_0>; 440 }; 441 442 cpu_pd3: power-domain-cpu3 { 443 #power-domain-cells = <0>; 444 power-domains = <&cluster_pd>; 445 domain-idle-states = <&big_cpu_sleep_0>; 446 }; 447 448 cpu_pd4: power-domain-cpu4 { 449 #power-domain-cells = <0>; 450 power-domains = <&cluster_pd>; 451 domain-idle-states = <&big_cpu_sleep_0>; 452 }; 453 454 cpu_pd5: power-domain-cpu5 { 455 #power-domain-cells = <0>; 456 power-domains = <&cluster_pd>; 457 domain-idle-states = <&big_cpu_sleep_0>; 458 }; 459 460 cpu_pd6: power-domain-cpu6 { 461 #power-domain-cells = <0>; 462 power-domains = <&cluster_pd>; 463 domain-idle-states = <&big_cpu_sleep_0>; 464 }; 465 466 cpu_pd7: power-domain-cpu7 { 467 #power-domain-cells = <0>; 468 power-domains = <&cluster_pd>; 469 domain-idle-states = <&prime_cpu_sleep_0>; 470 }; 471 472 cluster_pd: power-domain-cluster { 473 #power-domain-cells = <0>; 474 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; 475 }; 476 }; 477 478 reserved_memory: reserved-memory { 479 #address-cells = <2>; 480 #size-cells = <2>; 481 ranges; 482 483 hyp_mem: hyp-region@80000000 { 484 reg = <0 0x80000000 0 0xa00000>; 485 no-map; 486 }; 487 488 cpusys_vm_mem: cpusys-vm-region@80a00000 { 489 reg = <0 0x80a00000 0 0x400000>; 490 no-map; 491 }; 492 493 hyp_tags_mem: hyp-tags-region@80e00000 { 494 reg = <0 0x80e00000 0 0x3d0000>; 495 no-map; 496 }; 497 498 xbl_sc_mem: xbl-sc-region@d8100000 { 499 reg = <0 0xd8100000 0 0x40000>; 500 no-map; 501 }; 502 503 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 504 reg = <0 0x811d0000 0 0x30000>; 505 no-map; 506 }; 507 508 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 509 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 510 reg = <0 0x81a00000 0 0x260000>; 511 no-map; 512 }; 513 514 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 515 compatible = "qcom,cmd-db"; 516 reg = <0 0x81c60000 0 0x20000>; 517 no-map; 518 }; 519 520 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 521 aop_config_merged_mem: aop-config-merged-region@81c80000 { 522 reg = <0 0x81c80000 0 0x74000>; 523 no-map; 524 }; 525 526 /* secdata region can be reused by apps */ 527 smem: smem@81d00000 { 528 compatible = "qcom,smem"; 529 reg = <0 0x81d00000 0 0x200000>; 530 hwlocks = <&tcsr_mutex 3>; 531 no-map; 532 }; 533 534 adsp_mhi_mem: adsp-mhi-region@81f00000 { 535 reg = <0 0x81f00000 0 0x20000>; 536 no-map; 537 }; 538 539 global_sync_mem: global-sync-region@82600000 { 540 reg = <0 0x82600000 0 0x100000>; 541 no-map; 542 }; 543 544 tz_stat_mem: tz-stat-region@82700000 { 545 reg = <0 0x82700000 0 0x100000>; 546 no-map; 547 }; 548 549 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 550 reg = <0 0x82800000 0 0x4600000>; 551 no-map; 552 }; 553 554 mpss_mem: mpss-region@8a800000 { 555 reg = <0 0x8a800000 0 0x10800000>; 556 no-map; 557 }; 558 559 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 560 reg = <0 0x9b000000 0 0x80000>; 561 no-map; 562 }; 563 564 ipa_fw_mem: ipa-fw-region@9b080000 { 565 reg = <0 0x9b080000 0 0x10000>; 566 no-map; 567 }; 568 569 ipa_gsi_mem: ipa-gsi-region@9b090000 { 570 reg = <0 0x9b090000 0 0xa000>; 571 no-map; 572 }; 573 574 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 575 reg = <0 0x9b09a000 0 0x2000>; 576 no-map; 577 }; 578 579 spss_region_mem: spss-region@9b100000 { 580 reg = <0 0x9b100000 0 0x180000>; 581 no-map; 582 }; 583 584 /* First part of the "SPU secure shared memory" region */ 585 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 586 reg = <0 0x9b280000 0 0x60000>; 587 no-map; 588 }; 589 590 /* Second part of the "SPU secure shared memory" region */ 591 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 592 reg = <0 0x9b2e0000 0 0x20000>; 593 no-map; 594 }; 595 596 camera_mem: camera-region@9b300000 { 597 reg = <0 0x9b300000 0 0x800000>; 598 no-map; 599 }; 600 601 video_mem: video-region@9bb00000 { 602 reg = <0 0x9bb00000 0 0x700000>; 603 no-map; 604 }; 605 606 cvp_mem: cvp-region@9c200000 { 607 reg = <0 0x9c200000 0 0x700000>; 608 no-map; 609 }; 610 611 cdsp_mem: cdsp-region@9c900000 { 612 reg = <0 0x9c900000 0 0x2000000>; 613 no-map; 614 }; 615 616 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 617 reg = <0 0x9e900000 0 0x80000>; 618 no-map; 619 }; 620 621 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 622 reg = <0 0x9e980000 0 0x80000>; 623 no-map; 624 }; 625 626 adspslpi_mem: adspslpi-region@9ea00000 { 627 reg = <0 0x9ea00000 0 0x4080000>; 628 no-map; 629 }; 630 631 /* uefi region can be reused by apps */ 632 633 /* Linux kernel image is loaded at 0xa8000000 */ 634 635 rmtfs_mem: rmtfs-region@d4a80000 { 636 compatible = "qcom,rmtfs-mem"; 637 reg = <0x0 0xd4a80000 0x0 0x280000>; 638 no-map; 639 640 qcom,client-id = <1>; 641 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 642 }; 643 644 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 645 reg = <0 0xd4d00000 0 0x3300000>; 646 no-map; 647 }; 648 649 tz_reserved_mem: tz-reserved-region@d8000000 { 650 reg = <0 0xd8000000 0 0x100000>; 651 no-map; 652 }; 653 654 cpucp_fw_mem: cpucp-fw-region@d8140000 { 655 reg = <0 0xd8140000 0 0x1c0000>; 656 no-map; 657 }; 658 659 qtee_mem: qtee-region@d8300000 { 660 reg = <0 0xd8300000 0 0x500000>; 661 no-map; 662 }; 663 664 ta_mem: ta-region@d8800000 { 665 reg = <0 0xd8800000 0 0x8a00000>; 666 no-map; 667 }; 668 669 tz_tags_mem: tz-tags-region@e1200000 { 670 reg = <0 0xe1200000 0 0x2740000>; 671 no-map; 672 }; 673 674 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 675 reg = <0 0xe6440000 0 0x279000>; 676 no-map; 677 }; 678 679 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 680 reg = <0 0xf3600000 0 0x4aee000>; 681 no-map; 682 }; 683 684 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 685 reg = <0 0xf80ee000 0 0x1000>; 686 no-map; 687 }; 688 689 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 690 reg = <0 0xf80ef000 0 0x9000>; 691 no-map; 692 }; 693 694 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 695 reg = <0 0xf80f8000 0 0x4000>; 696 no-map; 697 }; 698 699 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 700 reg = <0 0xf80fc000 0 0x4000>; 701 no-map; 702 }; 703 704 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 705 reg = <0 0xf8100000 0 0x100000>; 706 no-map; 707 }; 708 709 oem_vm_mem: oem-vm-region@f8400000 { 710 reg = <0 0xf8400000 0 0x4800000>; 711 no-map; 712 }; 713 714 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 715 reg = <0 0xfcc00000 0 0x4000>; 716 no-map; 717 }; 718 719 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 720 reg = <0 0xfcc04000 0 0x100000>; 721 no-map; 722 }; 723 724 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 725 reg = <0 0xfce00000 0 0x2900000>; 726 no-map; 727 }; 728 729 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 730 reg = <0 0xff700000 0 0x100000>; 731 no-map; 732 }; 733 }; 734 735 smp2p-adsp { 736 compatible = "qcom,smp2p"; 737 qcom,smem = <443>, <429>; 738 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 739 IPCC_MPROC_SIGNAL_SMP2P 740 IRQ_TYPE_EDGE_RISING>; 741 mboxes = <&ipcc IPCC_CLIENT_LPASS 742 IPCC_MPROC_SIGNAL_SMP2P>; 743 744 qcom,local-pid = <0>; 745 qcom,remote-pid = <2>; 746 747 smp2p_adsp_out: master-kernel { 748 qcom,entry-name = "master-kernel"; 749 #qcom,smem-state-cells = <1>; 750 }; 751 752 smp2p_adsp_in: slave-kernel { 753 qcom,entry-name = "slave-kernel"; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 }; 757 }; 758 759 smp2p-cdsp { 760 compatible = "qcom,smp2p"; 761 qcom,smem = <94>, <432>; 762 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 763 IPCC_MPROC_SIGNAL_SMP2P 764 IRQ_TYPE_EDGE_RISING>; 765 mboxes = <&ipcc IPCC_CLIENT_CDSP 766 IPCC_MPROC_SIGNAL_SMP2P>; 767 768 qcom,local-pid = <0>; 769 qcom,remote-pid = <5>; 770 771 smp2p_cdsp_out: master-kernel { 772 qcom,entry-name = "master-kernel"; 773 #qcom,smem-state-cells = <1>; 774 }; 775 776 smp2p_cdsp_in: slave-kernel { 777 qcom,entry-name = "slave-kernel"; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 }; 782 783 smp2p-modem { 784 compatible = "qcom,smp2p"; 785 qcom,smem = <435>, <428>; 786 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 787 IPCC_MPROC_SIGNAL_SMP2P 788 IRQ_TYPE_EDGE_RISING>; 789 mboxes = <&ipcc IPCC_CLIENT_MPSS 790 IPCC_MPROC_SIGNAL_SMP2P>; 791 792 qcom,local-pid = <0>; 793 qcom,remote-pid = <1>; 794 795 smp2p_modem_out: master-kernel { 796 qcom,entry-name = "master-kernel"; 797 #qcom,smem-state-cells = <1>; 798 }; 799 800 smp2p_modem_in: slave-kernel { 801 qcom,entry-name = "slave-kernel"; 802 interrupt-controller; 803 #interrupt-cells = <2>; 804 }; 805 806 ipa_smp2p_out: ipa-ap-to-modem { 807 qcom,entry-name = "ipa"; 808 #qcom,smem-state-cells = <1>; 809 }; 810 811 ipa_smp2p_in: ipa-modem-to-ap { 812 qcom,entry-name = "ipa"; 813 interrupt-controller; 814 #interrupt-cells = <2>; 815 }; 816 }; 817 818 soc: soc@0 { 819 compatible = "simple-bus"; 820 ranges = <0 0 0 0 0x10 0>; 821 dma-ranges = <0 0 0 0 0x10 0>; 822 823 #address-cells = <2>; 824 #size-cells = <2>; 825 826 gcc: clock-controller@100000 { 827 compatible = "qcom,sm8550-gcc"; 828 reg = <0 0x00100000 0 0x1f4200>; 829 #clock-cells = <1>; 830 #reset-cells = <1>; 831 #power-domain-cells = <1>; 832 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 833 <&pcie0_phy>, 834 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 835 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 836 <&ufs_mem_phy 0>, 837 <&ufs_mem_phy 1>, 838 <&ufs_mem_phy 2>, 839 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 840 }; 841 842 ipcc: mailbox@408000 { 843 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 844 reg = <0 0x00408000 0 0x1000>; 845 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>; 846 interrupt-controller; 847 #interrupt-cells = <3>; 848 #mbox-cells = <2>; 849 }; 850 851 gpi_dma2: dma-controller@800000 { 852 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 853 #dma-cells = <3>; 854 reg = <0 0x00800000 0 0x60000>; 855 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>, 856 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>, 857 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, 858 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, 859 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, 860 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, 861 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, 862 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, 863 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, 864 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>, 865 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>, 866 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>; 867 dma-channels = <12>; 868 dma-channel-mask = <0x3e>; 869 iommus = <&apps_smmu 0x436 0>; 870 dma-coherent; 871 status = "disabled"; 872 }; 873 874 qupv3_id_1: geniqup@8c0000 { 875 compatible = "qcom,geni-se-qup"; 876 reg = <0 0x008c0000 0 0x2000>; 877 ranges; 878 clock-names = "m-ahb", "s-ahb"; 879 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 880 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 881 iommus = <&apps_smmu 0x423 0>; 882 dma-coherent; 883 #address-cells = <2>; 884 #size-cells = <2>; 885 status = "disabled"; 886 887 i2c8: i2c@880000 { 888 compatible = "qcom,geni-i2c"; 889 reg = <0 0x00880000 0 0x4000>; 890 clock-names = "se"; 891 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 892 pinctrl-names = "default"; 893 pinctrl-0 = <&qup_i2c8_data_clk>; 894 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 898 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 899 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 900 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 901 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 902 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 903 interconnect-names = "qup-core", "qup-config", "qup-memory"; 904 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 905 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 906 dma-names = "tx", "rx"; 907 power-domains = <&rpmhpd RPMHPD_CX>; 908 operating-points-v2 = <&qup_opp_table_120mhz>; 909 status = "disabled"; 910 }; 911 912 spi8: spi@880000 { 913 compatible = "qcom,geni-spi"; 914 reg = <0 0x00880000 0 0x4000>; 915 clock-names = "se"; 916 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 917 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 918 pinctrl-names = "default"; 919 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 920 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 921 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 922 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 923 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 924 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 925 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 926 interconnect-names = "qup-core", "qup-config", "qup-memory"; 927 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 928 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 929 dma-names = "tx", "rx"; 930 power-domains = <&rpmhpd RPMHPD_CX>; 931 operating-points-v2 = <&qup_opp_table_120mhz>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 status = "disabled"; 935 }; 936 937 i2c9: i2c@884000 { 938 compatible = "qcom,geni-i2c"; 939 reg = <0 0x00884000 0 0x4000>; 940 clock-names = "se"; 941 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&qup_i2c9_data_clk>; 944 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 948 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 949 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 950 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 951 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 952 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 953 interconnect-names = "qup-core", "qup-config", "qup-memory"; 954 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 955 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 956 dma-names = "tx", "rx"; 957 power-domains = <&rpmhpd RPMHPD_CX>; 958 operating-points-v2 = <&qup_opp_table_120mhz>; 959 status = "disabled"; 960 }; 961 962 spi9: spi@884000 { 963 compatible = "qcom,geni-spi"; 964 reg = <0 0x00884000 0 0x4000>; 965 clock-names = "se"; 966 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 967 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 970 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 971 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 972 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 973 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 974 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 975 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 976 interconnect-names = "qup-core", "qup-config", "qup-memory"; 977 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 978 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 979 dma-names = "tx", "rx"; 980 power-domains = <&rpmhpd RPMHPD_CX>; 981 operating-points-v2 = <&qup_opp_table_120mhz>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 i2c10: i2c@888000 { 988 compatible = "qcom,geni-i2c"; 989 reg = <0 0x00888000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&qup_i2c10_data_clk>; 994 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 998 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 999 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1000 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1001 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1002 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1003 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1004 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1005 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1006 dma-names = "tx", "rx"; 1007 power-domains = <&rpmhpd RPMHPD_CX>; 1008 operating-points-v2 = <&qup_opp_table_120mhz>; 1009 status = "disabled"; 1010 }; 1011 1012 spi10: spi@888000 { 1013 compatible = "qcom,geni-spi"; 1014 reg = <0 0x00888000 0 0x4000>; 1015 clock-names = "se"; 1016 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1017 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1020 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1021 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1022 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1023 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1024 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1025 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1026 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1027 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1028 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1029 dma-names = "tx", "rx"; 1030 power-domains = <&rpmhpd RPMHPD_CX>; 1031 operating-points-v2 = <&qup_opp_table_120mhz>; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 i2c11: i2c@88c000 { 1038 compatible = "qcom,geni-i2c"; 1039 reg = <0 0x0088c000 0 0x4000>; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1042 pinctrl-names = "default"; 1043 pinctrl-0 = <&qup_i2c11_data_clk>; 1044 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1048 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1049 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1050 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1051 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1052 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1053 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1054 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1055 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1056 dma-names = "tx", "rx"; 1057 power-domains = <&rpmhpd RPMHPD_CX>; 1058 operating-points-v2 = <&qup_opp_table_120mhz>; 1059 status = "disabled"; 1060 }; 1061 1062 spi11: spi@88c000 { 1063 compatible = "qcom,geni-spi"; 1064 reg = <0 0x0088c000 0 0x4000>; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1067 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1070 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1071 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1072 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1073 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1074 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1075 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1076 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1077 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1078 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1079 dma-names = "tx", "rx"; 1080 power-domains = <&rpmhpd RPMHPD_CX>; 1081 operating-points-v2 = <&qup_opp_table_120mhz>; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 status = "disabled"; 1085 }; 1086 1087 i2c12: i2c@890000 { 1088 compatible = "qcom,geni-i2c"; 1089 reg = <0 0x00890000 0 0x4000>; 1090 clock-names = "se"; 1091 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1092 pinctrl-names = "default"; 1093 pinctrl-0 = <&qup_i2c12_data_clk>; 1094 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1098 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1099 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1100 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1101 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1102 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1103 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1104 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1105 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1106 dma-names = "tx", "rx"; 1107 power-domains = <&rpmhpd RPMHPD_CX>; 1108 operating-points-v2 = <&qup_opp_table_120mhz>; 1109 status = "disabled"; 1110 }; 1111 1112 spi12: spi@890000 { 1113 compatible = "qcom,geni-spi"; 1114 reg = <0 0x00890000 0 0x4000>; 1115 clock-names = "se"; 1116 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1117 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1120 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1121 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1122 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1123 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1124 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1125 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1126 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1127 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1128 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1129 dma-names = "tx", "rx"; 1130 power-domains = <&rpmhpd RPMHPD_CX>; 1131 operating-points-v2 = <&qup_opp_table_120mhz>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 status = "disabled"; 1135 }; 1136 1137 i2c13: i2c@894000 { 1138 compatible = "qcom,geni-i2c"; 1139 reg = <0 0x00894000 0 0x4000>; 1140 clock-names = "se"; 1141 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1142 pinctrl-names = "default"; 1143 pinctrl-0 = <&qup_i2c13_data_clk>; 1144 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1148 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1149 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1150 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1151 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1152 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1153 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1154 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1155 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1156 dma-names = "tx", "rx"; 1157 power-domains = <&rpmhpd RPMHPD_CX>; 1158 operating-points-v2 = <&qup_opp_table_120mhz>; 1159 status = "disabled"; 1160 }; 1161 1162 spi13: spi@894000 { 1163 compatible = "qcom,geni-spi"; 1164 reg = <0 0x00894000 0 0x4000>; 1165 clock-names = "se"; 1166 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1167 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1171 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1172 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1173 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1174 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1176 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1177 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1178 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1179 dma-names = "tx", "rx"; 1180 power-domains = <&rpmhpd RPMHPD_CX>; 1181 operating-points-v2 = <&qup_opp_table_120mhz>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 status = "disabled"; 1185 }; 1186 1187 uart14: serial@898000 { 1188 compatible = "qcom,geni-uart"; 1189 reg = <0 0x898000 0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1194 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH 0>; 1195 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1196 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1197 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1198 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1199 interconnect-names = "qup-core", "qup-config"; 1200 power-domains = <&rpmhpd RPMHPD_CX>; 1201 operating-points-v2 = <&qup_opp_table_125mhz>; 1202 status = "disabled"; 1203 }; 1204 1205 i2c15: i2c@89c000 { 1206 compatible = "qcom,geni-i2c"; 1207 reg = <0 0x0089c000 0 0x4000>; 1208 clock-names = "se"; 1209 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1210 pinctrl-names = "default"; 1211 pinctrl-0 = <&qup_i2c15_data_clk>; 1212 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1216 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1217 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1218 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1219 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1220 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1221 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1222 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1223 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1224 dma-names = "tx", "rx"; 1225 power-domains = <&rpmhpd RPMHPD_CX>; 1226 operating-points-v2 = <&qup_opp_table_100mhz>; 1227 status = "disabled"; 1228 }; 1229 1230 spi15: spi@89c000 { 1231 compatible = "qcom,geni-spi"; 1232 reg = <0 0x0089c000 0 0x4000>; 1233 clock-names = "se"; 1234 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1235 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 1236 pinctrl-names = "default"; 1237 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1238 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1239 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1240 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1241 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1242 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1243 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1244 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1245 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1246 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1247 dma-names = "tx", "rx"; 1248 power-domains = <&rpmhpd RPMHPD_CX>; 1249 operating-points-v2 = <&qup_opp_table_100mhz>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 status = "disabled"; 1253 }; 1254 1255 uart15: serial@89c000 { 1256 compatible = "qcom,geni-uart"; 1257 reg = <0 0x0089c000 0 0x4000>; 1258 clock-names = "se"; 1259 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&qup_uart15_default>; 1262 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 1263 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1264 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1265 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1266 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1267 interconnect-names = "qup-core", "qup-config"; 1268 status = "disabled"; 1269 }; 1270 }; 1271 1272 i2c_master_hub_0: geniqup@9c0000 { 1273 compatible = "qcom,geni-se-i2c-master-hub"; 1274 reg = <0x0 0x009c0000 0x0 0x2000>; 1275 clock-names = "s-ahb"; 1276 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1277 #address-cells = <2>; 1278 #size-cells = <2>; 1279 ranges; 1280 status = "disabled"; 1281 1282 i2c_hub_0: i2c@980000 { 1283 compatible = "qcom,geni-i2c-master-hub"; 1284 reg = <0x0 0x00980000 0x0 0x4000>; 1285 clock-names = "se", "core"; 1286 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1287 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1288 pinctrl-names = "default"; 1289 pinctrl-0 = <&hub_i2c0_data_clk>; 1290 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>; 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1294 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1295 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1296 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1297 interconnect-names = "qup-core", "qup-config"; 1298 power-domains = <&rpmhpd RPMHPD_CX>; 1299 required-opps = <&rpmhpd_opp_low_svs>; 1300 status = "disabled"; 1301 }; 1302 1303 i2c_hub_1: i2c@984000 { 1304 compatible = "qcom,geni-i2c-master-hub"; 1305 reg = <0x0 0x00984000 0x0 0x4000>; 1306 clock-names = "se", "core"; 1307 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1308 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1309 pinctrl-names = "default"; 1310 pinctrl-0 = <&hub_i2c1_data_clk>; 1311 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH 0>; 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1315 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1316 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1317 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1318 interconnect-names = "qup-core", "qup-config"; 1319 power-domains = <&rpmhpd RPMHPD_CX>; 1320 required-opps = <&rpmhpd_opp_low_svs>; 1321 status = "disabled"; 1322 }; 1323 1324 i2c_hub_2: i2c@988000 { 1325 compatible = "qcom,geni-i2c-master-hub"; 1326 reg = <0x0 0x00988000 0x0 0x4000>; 1327 clock-names = "se", "core"; 1328 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1329 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1330 pinctrl-names = "default"; 1331 pinctrl-0 = <&hub_i2c2_data_clk>; 1332 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH 0>; 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1336 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1337 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1338 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1339 interconnect-names = "qup-core", "qup-config"; 1340 power-domains = <&rpmhpd RPMHPD_CX>; 1341 required-opps = <&rpmhpd_opp_low_svs>; 1342 status = "disabled"; 1343 }; 1344 1345 i2c_hub_3: i2c@98c000 { 1346 compatible = "qcom,geni-i2c-master-hub"; 1347 reg = <0x0 0x0098c000 0x0 0x4000>; 1348 clock-names = "se", "core"; 1349 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1350 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1351 pinctrl-names = "default"; 1352 pinctrl-0 = <&hub_i2c3_data_clk>; 1353 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>; 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1357 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1358 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1359 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1360 interconnect-names = "qup-core", "qup-config"; 1361 power-domains = <&rpmhpd RPMHPD_CX>; 1362 required-opps = <&rpmhpd_opp_low_svs>; 1363 status = "disabled"; 1364 }; 1365 1366 i2c_hub_4: i2c@990000 { 1367 compatible = "qcom,geni-i2c-master-hub"; 1368 reg = <0x0 0x00990000 0x0 0x4000>; 1369 clock-names = "se", "core"; 1370 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1371 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1372 pinctrl-names = "default"; 1373 pinctrl-0 = <&hub_i2c4_data_clk>; 1374 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>; 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1378 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1379 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1380 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1381 interconnect-names = "qup-core", "qup-config"; 1382 power-domains = <&rpmhpd RPMHPD_CX>; 1383 required-opps = <&rpmhpd_opp_low_svs>; 1384 status = "disabled"; 1385 }; 1386 1387 i2c_hub_5: i2c@994000 { 1388 compatible = "qcom,geni-i2c-master-hub"; 1389 reg = <0 0x00994000 0 0x4000>; 1390 clock-names = "se", "core"; 1391 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1392 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1393 pinctrl-names = "default"; 1394 pinctrl-0 = <&hub_i2c5_data_clk>; 1395 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH 0>; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1399 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1400 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1401 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1402 interconnect-names = "qup-core", "qup-config"; 1403 power-domains = <&rpmhpd RPMHPD_CX>; 1404 required-opps = <&rpmhpd_opp_low_svs>; 1405 status = "disabled"; 1406 }; 1407 1408 i2c_hub_6: i2c@998000 { 1409 compatible = "qcom,geni-i2c-master-hub"; 1410 reg = <0 0x00998000 0 0x4000>; 1411 clock-names = "se", "core"; 1412 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1413 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1414 pinctrl-names = "default"; 1415 pinctrl-0 = <&hub_i2c6_data_clk>; 1416 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH 0>; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1420 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1421 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1422 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1423 interconnect-names = "qup-core", "qup-config"; 1424 power-domains = <&rpmhpd RPMHPD_CX>; 1425 required-opps = <&rpmhpd_opp_low_svs>; 1426 status = "disabled"; 1427 }; 1428 1429 i2c_hub_7: i2c@99c000 { 1430 compatible = "qcom,geni-i2c-master-hub"; 1431 reg = <0 0x0099c000 0 0x4000>; 1432 clock-names = "se", "core"; 1433 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1434 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&hub_i2c7_data_clk>; 1437 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1441 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1442 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1443 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1444 interconnect-names = "qup-core", "qup-config"; 1445 power-domains = <&rpmhpd RPMHPD_CX>; 1446 required-opps = <&rpmhpd_opp_low_svs>; 1447 status = "disabled"; 1448 }; 1449 1450 i2c_hub_8: i2c@9a0000 { 1451 compatible = "qcom,geni-i2c-master-hub"; 1452 reg = <0 0x009a0000 0 0x4000>; 1453 clock-names = "se", "core"; 1454 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1455 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1456 pinctrl-names = "default"; 1457 pinctrl-0 = <&hub_i2c8_data_clk>; 1458 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH 0>; 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1462 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1463 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1464 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1465 interconnect-names = "qup-core", "qup-config"; 1466 power-domains = <&rpmhpd RPMHPD_CX>; 1467 required-opps = <&rpmhpd_opp_low_svs>; 1468 status = "disabled"; 1469 }; 1470 1471 i2c_hub_9: i2c@9a4000 { 1472 compatible = "qcom,geni-i2c-master-hub"; 1473 reg = <0 0x009a4000 0 0x4000>; 1474 clock-names = "se", "core"; 1475 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1476 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1477 pinctrl-names = "default"; 1478 pinctrl-0 = <&hub_i2c9_data_clk>; 1479 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH 0>; 1480 #address-cells = <1>; 1481 #size-cells = <0>; 1482 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1483 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1484 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1485 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1486 interconnect-names = "qup-core", "qup-config"; 1487 power-domains = <&rpmhpd RPMHPD_CX>; 1488 required-opps = <&rpmhpd_opp_low_svs>; 1489 status = "disabled"; 1490 }; 1491 }; 1492 1493 gpi_dma1: dma-controller@a00000 { 1494 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1495 #dma-cells = <3>; 1496 reg = <0 0x00a00000 0 0x60000>; 1497 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>, 1498 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>, 1499 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>, 1500 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>, 1501 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>, 1502 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>, 1503 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>, 1504 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>, 1505 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>, 1506 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>, 1507 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>, 1508 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 1509 dma-channels = <12>; 1510 dma-channel-mask = <0x1e>; 1511 iommus = <&apps_smmu 0xb6 0>; 1512 dma-coherent; 1513 status = "disabled"; 1514 }; 1515 1516 qupv3_id_0: geniqup@ac0000 { 1517 compatible = "qcom,geni-se-qup"; 1518 reg = <0 0x00ac0000 0 0x2000>; 1519 ranges; 1520 clock-names = "m-ahb", "s-ahb"; 1521 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1522 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1523 iommus = <&apps_smmu 0xa3 0>; 1524 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1525 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 1526 interconnect-names = "qup-core"; 1527 dma-coherent; 1528 #address-cells = <2>; 1529 #size-cells = <2>; 1530 status = "disabled"; 1531 1532 i2c0: i2c@a80000 { 1533 compatible = "qcom,geni-i2c"; 1534 reg = <0 0x00a80000 0 0x4000>; 1535 clock-names = "se"; 1536 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1537 pinctrl-names = "default"; 1538 pinctrl-0 = <&qup_i2c0_data_clk>; 1539 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1543 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1544 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1545 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1546 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1547 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1548 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1549 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1550 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1551 dma-names = "tx", "rx"; 1552 power-domains = <&rpmhpd RPMHPD_CX>; 1553 operating-points-v2 = <&qup_opp_table_120mhz>; 1554 status = "disabled"; 1555 }; 1556 1557 spi0: spi@a80000 { 1558 compatible = "qcom,geni-spi"; 1559 reg = <0 0x00a80000 0 0x4000>; 1560 clock-names = "se"; 1561 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1562 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1563 pinctrl-names = "default"; 1564 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1565 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1566 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1567 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1568 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1569 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1570 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1571 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1572 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1573 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1574 dma-names = "tx", "rx"; 1575 power-domains = <&rpmhpd RPMHPD_CX>; 1576 operating-points-v2 = <&qup_opp_table_120mhz>; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 status = "disabled"; 1580 }; 1581 1582 i2c1: i2c@a84000 { 1583 compatible = "qcom,geni-i2c"; 1584 reg = <0 0x00a84000 0 0x4000>; 1585 clock-names = "se"; 1586 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1587 pinctrl-names = "default"; 1588 pinctrl-0 = <&qup_i2c1_data_clk>; 1589 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 1590 #address-cells = <1>; 1591 #size-cells = <0>; 1592 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1593 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1594 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1595 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1596 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1597 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1598 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1599 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1600 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1601 dma-names = "tx", "rx"; 1602 power-domains = <&rpmhpd RPMHPD_CX>; 1603 operating-points-v2 = <&qup_opp_table_120mhz>; 1604 status = "disabled"; 1605 }; 1606 1607 spi1: spi@a84000 { 1608 compatible = "qcom,geni-spi"; 1609 reg = <0 0x00a84000 0 0x4000>; 1610 clock-names = "se"; 1611 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1612 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 1613 pinctrl-names = "default"; 1614 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1615 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1616 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1617 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1618 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1619 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1620 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1621 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1622 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1623 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1624 dma-names = "tx", "rx"; 1625 power-domains = <&rpmhpd RPMHPD_CX>; 1626 operating-points-v2 = <&qup_opp_table_120mhz>; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 i2c2: i2c@a88000 { 1633 compatible = "qcom,geni-i2c"; 1634 reg = <0 0x00a88000 0 0x4000>; 1635 clock-names = "se"; 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1637 pinctrl-names = "default"; 1638 pinctrl-0 = <&qup_i2c2_data_clk>; 1639 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1643 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1644 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1645 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1646 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1647 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1648 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1649 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1650 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1651 dma-names = "tx", "rx"; 1652 power-domains = <&rpmhpd RPMHPD_CX>; 1653 operating-points-v2 = <&qup_opp_table_100mhz>; 1654 status = "disabled"; 1655 }; 1656 1657 spi2: spi@a88000 { 1658 compatible = "qcom,geni-spi"; 1659 reg = <0 0x00a88000 0 0x4000>; 1660 clock-names = "se"; 1661 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1662 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1663 pinctrl-names = "default"; 1664 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1665 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1666 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1667 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1668 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1669 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1670 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1671 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1672 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1673 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1674 dma-names = "tx", "rx"; 1675 power-domains = <&rpmhpd RPMHPD_CX>; 1676 operating-points-v2 = <&qup_opp_table_100mhz>; 1677 #address-cells = <1>; 1678 #size-cells = <0>; 1679 status = "disabled"; 1680 }; 1681 1682 i2c3: i2c@a8c000 { 1683 compatible = "qcom,geni-i2c"; 1684 reg = <0 0x00a8c000 0 0x4000>; 1685 clock-names = "se"; 1686 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&qup_i2c3_data_clk>; 1689 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1693 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1694 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1695 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1696 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1697 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1698 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1699 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1700 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1701 dma-names = "tx", "rx"; 1702 power-domains = <&rpmhpd RPMHPD_CX>; 1703 operating-points-v2 = <&qup_opp_table_100mhz>; 1704 status = "disabled"; 1705 }; 1706 1707 spi3: spi@a8c000 { 1708 compatible = "qcom,geni-spi"; 1709 reg = <0 0x00a8c000 0 0x4000>; 1710 clock-names = "se"; 1711 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1712 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1713 pinctrl-names = "default"; 1714 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1715 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1716 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1717 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1718 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1719 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1720 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1721 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1722 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1723 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1724 dma-names = "tx", "rx"; 1725 power-domains = <&rpmhpd RPMHPD_CX>; 1726 operating-points-v2 = <&qup_opp_table_100mhz>; 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 status = "disabled"; 1730 }; 1731 1732 i2c4: i2c@a90000 { 1733 compatible = "qcom,geni-i2c"; 1734 reg = <0 0x00a90000 0 0x4000>; 1735 clock-names = "se"; 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1737 pinctrl-names = "default"; 1738 pinctrl-0 = <&qup_i2c4_data_clk>; 1739 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; 1740 #address-cells = <1>; 1741 #size-cells = <0>; 1742 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1743 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1744 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1745 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1746 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1747 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1748 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1749 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1750 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1751 dma-names = "tx", "rx"; 1752 power-domains = <&rpmhpd RPMHPD_CX>; 1753 operating-points-v2 = <&qup_opp_table_100mhz>; 1754 status = "disabled"; 1755 }; 1756 1757 spi4: spi@a90000 { 1758 compatible = "qcom,geni-spi"; 1759 reg = <0 0x00a90000 0 0x4000>; 1760 clock-names = "se"; 1761 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1762 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; 1763 pinctrl-names = "default"; 1764 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1765 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1766 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1767 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1768 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1769 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1770 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1771 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1772 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1773 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1774 dma-names = "tx", "rx"; 1775 power-domains = <&rpmhpd RPMHPD_CX>; 1776 operating-points-v2 = <&qup_opp_table_100mhz>; 1777 #address-cells = <1>; 1778 #size-cells = <0>; 1779 status = "disabled"; 1780 }; 1781 1782 i2c5: i2c@a94000 { 1783 compatible = "qcom,geni-i2c"; 1784 reg = <0 0x00a94000 0 0x4000>; 1785 clock-names = "se"; 1786 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1787 pinctrl-names = "default"; 1788 pinctrl-0 = <&qup_i2c5_data_clk>; 1789 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; 1790 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1791 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1792 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1793 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1794 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1795 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1796 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1797 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1798 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1799 dma-names = "tx", "rx"; 1800 power-domains = <&rpmhpd RPMHPD_CX>; 1801 operating-points-v2 = <&qup_opp_table_100mhz>; 1802 #address-cells = <1>; 1803 #size-cells = <0>; 1804 status = "disabled"; 1805 }; 1806 1807 spi5: spi@a94000 { 1808 compatible = "qcom,geni-spi"; 1809 reg = <0 0x00a94000 0 0x4000>; 1810 clock-names = "se"; 1811 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1812 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; 1813 pinctrl-names = "default"; 1814 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1815 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1816 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1817 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1818 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1819 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1820 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1821 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1822 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1823 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1824 dma-names = "tx", "rx"; 1825 power-domains = <&rpmhpd RPMHPD_CX>; 1826 operating-points-v2 = <&qup_opp_table_100mhz>; 1827 #address-cells = <1>; 1828 #size-cells = <0>; 1829 status = "disabled"; 1830 }; 1831 1832 i2c6: i2c@a98000 { 1833 compatible = "qcom,geni-i2c"; 1834 reg = <0 0x00a98000 0 0x4000>; 1835 clock-names = "se"; 1836 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1837 pinctrl-names = "default"; 1838 pinctrl-0 = <&qup_i2c6_data_clk>; 1839 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 1840 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1841 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1842 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1843 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1844 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1845 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1846 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1847 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1848 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1849 dma-names = "tx", "rx"; 1850 power-domains = <&rpmhpd RPMHPD_CX>; 1851 operating-points-v2 = <&qup_opp_table_100mhz>; 1852 #address-cells = <1>; 1853 #size-cells = <0>; 1854 status = "disabled"; 1855 }; 1856 1857 spi6: spi@a98000 { 1858 compatible = "qcom,geni-spi"; 1859 reg = <0 0x00a98000 0 0x4000>; 1860 clock-names = "se"; 1861 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1862 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 1863 pinctrl-names = "default"; 1864 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1865 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1866 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1867 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1868 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1869 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1870 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1871 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1872 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1873 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1874 dma-names = "tx", "rx"; 1875 power-domains = <&rpmhpd RPMHPD_CX>; 1876 operating-points-v2 = <&qup_opp_table_100mhz>; 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 status = "disabled"; 1880 }; 1881 1882 uart7: serial@a9c000 { 1883 compatible = "qcom,geni-debug-uart"; 1884 reg = <0 0x00a9c000 0 0x4000>; 1885 clock-names = "se"; 1886 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1887 pinctrl-names = "default"; 1888 pinctrl-0 = <&qup_uart7_default>; 1889 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>; 1890 interconnect-names = "qup-core", "qup-config"; 1891 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1892 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1893 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1894 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1895 power-domains = <&rpmhpd RPMHPD_CX>; 1896 operating-points-v2 = <&qup_opp_table_100mhz>; 1897 status = "disabled"; 1898 }; 1899 }; 1900 1901 cnoc_main: interconnect@1500000 { 1902 compatible = "qcom,sm8550-cnoc-main"; 1903 reg = <0 0x01500000 0 0x13080>; 1904 #interconnect-cells = <2>; 1905 qcom,bcm-voters = <&apps_bcm_voter>; 1906 }; 1907 1908 config_noc: interconnect@1600000 { 1909 compatible = "qcom,sm8550-config-noc"; 1910 reg = <0 0x01600000 0 0x6200>; 1911 #interconnect-cells = <2>; 1912 qcom,bcm-voters = <&apps_bcm_voter>; 1913 }; 1914 1915 system_noc: interconnect@1680000 { 1916 compatible = "qcom,sm8550-system-noc"; 1917 reg = <0 0x01680000 0 0x1d080>; 1918 #interconnect-cells = <2>; 1919 qcom,bcm-voters = <&apps_bcm_voter>; 1920 }; 1921 1922 pcie_noc: interconnect@16c0000 { 1923 compatible = "qcom,sm8550-pcie-anoc"; 1924 reg = <0 0x016c0000 0 0x12200>; 1925 #interconnect-cells = <2>; 1926 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1927 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1928 qcom,bcm-voters = <&apps_bcm_voter>; 1929 }; 1930 1931 aggre1_noc: interconnect@16e0000 { 1932 compatible = "qcom,sm8550-aggre1-noc"; 1933 reg = <0 0x016e0000 0 0x14400>; 1934 #interconnect-cells = <2>; 1935 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1936 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1937 qcom,bcm-voters = <&apps_bcm_voter>; 1938 }; 1939 1940 aggre2_noc: interconnect@1700000 { 1941 compatible = "qcom,sm8550-aggre2-noc"; 1942 reg = <0 0x01700000 0 0x1e400>; 1943 #interconnect-cells = <2>; 1944 clocks = <&rpmhcc RPMH_IPA_CLK>; 1945 qcom,bcm-voters = <&apps_bcm_voter>; 1946 }; 1947 1948 mmss_noc: interconnect@1780000 { 1949 compatible = "qcom,sm8550-mmss-noc"; 1950 reg = <0 0x01780000 0 0x5b800>; 1951 #interconnect-cells = <2>; 1952 qcom,bcm-voters = <&apps_bcm_voter>; 1953 }; 1954 1955 rng: rng@10c3000 { 1956 compatible = "qcom,sm8550-trng", "qcom,trng"; 1957 reg = <0 0x010c3000 0 0x1000>; 1958 }; 1959 1960 pcie0: pcie@1c00000 { 1961 device_type = "pci"; 1962 compatible = "qcom,pcie-sm8550"; 1963 reg = <0 0x01c00000 0 0x3000>, 1964 <0 0x60000000 0 0xf1d>, 1965 <0 0x60000f20 0 0xa8>, 1966 <0 0x60001000 0 0x1000>, 1967 <0 0x60100000 0 0x100000>; 1968 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1969 #address-cells = <3>; 1970 #size-cells = <2>; 1971 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1972 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1973 bus-range = <0x00 0xff>; 1974 1975 dma-coherent; 1976 1977 linux,pci-domain = <0>; 1978 num-lanes = <2>; 1979 1980 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>, 1981 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>, 1982 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>, 1983 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>, 1984 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>, 1985 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>, 1986 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>, 1987 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>, 1988 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>; 1989 interrupt-names = "msi0", 1990 "msi1", 1991 "msi2", 1992 "msi3", 1993 "msi4", 1994 "msi5", 1995 "msi6", 1996 "msi7", 1997 "global"; 1998 #interrupt-cells = <1>; 1999 interrupt-map-mask = <0 0 0 0x7>; 2000 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */ 2001 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ 2002 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ 2003 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ 2004 2005 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2006 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2007 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2008 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2009 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2010 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2011 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 2012 clock-names = "aux", 2013 "cfg", 2014 "bus_master", 2015 "bus_slave", 2016 "slave_q2a", 2017 "ddrss_sf_tbu", 2018 "noc_aggr"; 2019 2020 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2021 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2022 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2023 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2024 interconnect-names = "pcie-mem", "cpu-pcie"; 2025 2026 msi-map = <0x0 &gic_its 0x1400 0x1>, 2027 <0x100 &gic_its 0x1401 0x1>; 2028 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 2029 <0x100 &apps_smmu 0x1401 0x1>; 2030 2031 resets = <&gcc GCC_PCIE_0_BCR>; 2032 reset-names = "pci"; 2033 2034 power-domains = <&gcc PCIE_0_GDSC>; 2035 2036 phys = <&pcie0_phy>; 2037 phy-names = "pciephy"; 2038 2039 operating-points-v2 = <&pcie0_opp_table>; 2040 2041 status = "disabled"; 2042 2043 pcie0_opp_table: opp-table { 2044 compatible = "operating-points-v2"; 2045 2046 /* 2.5 GT/s x1 */ 2047 opp-2500000-1 { 2048 opp-hz = /bits/ 64 <2500000>; 2049 required-opps = <&rpmhpd_opp_low_svs>; 2050 opp-peak-kBps = <250000 1>; 2051 opp-level = <1>; 2052 }; 2053 2054 /* 2.5 GT/s x2 */ 2055 opp-5000000-1 { 2056 opp-hz = /bits/ 64 <5000000>; 2057 required-opps = <&rpmhpd_opp_low_svs>; 2058 opp-peak-kBps = <500000 1>; 2059 opp-level = <1>; 2060 }; 2061 2062 /* 5 GT/s x1 */ 2063 opp-5000000-2 { 2064 opp-hz = /bits/ 64 <5000000>; 2065 required-opps = <&rpmhpd_opp_low_svs>; 2066 opp-peak-kBps = <500000 1>; 2067 opp-level = <2>; 2068 }; 2069 2070 /* 5 GT/s x2 */ 2071 opp-10000000-2 { 2072 opp-hz = /bits/ 64 <10000000>; 2073 required-opps = <&rpmhpd_opp_low_svs>; 2074 opp-peak-kBps = <1000000 1>; 2075 opp-level = <2>; 2076 }; 2077 2078 /* 8 GT/s x1 */ 2079 opp-8000000-3 { 2080 opp-hz = /bits/ 64 <8000000>; 2081 required-opps = <&rpmhpd_opp_nom>; 2082 opp-peak-kBps = <984500 1>; 2083 opp-level = <3>; 2084 }; 2085 2086 /* 8 GT/s x2 */ 2087 opp-16000000-3 { 2088 opp-hz = /bits/ 64 <16000000>; 2089 required-opps = <&rpmhpd_opp_nom>; 2090 opp-peak-kBps = <1969000 1>; 2091 opp-level = <3>; 2092 }; 2093 }; 2094 2095 pcieport0: pcie@0 { 2096 device_type = "pci"; 2097 reg = <0x0 0x0 0x0 0x0 0x0>; 2098 bus-range = <0x01 0xff>; 2099 2100 #address-cells = <3>; 2101 #size-cells = <2>; 2102 ranges; 2103 }; 2104 }; 2105 2106 pcie0_phy: phy@1c06000 { 2107 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 2108 reg = <0 0x01c06000 0 0x2000>; 2109 2110 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2111 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2112 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 2113 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2114 <&gcc GCC_PCIE_0_PIPE_CLK>; 2115 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2116 "pipe"; 2117 2118 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2119 reset-names = "phy"; 2120 2121 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2122 assigned-clock-rates = <100000000>; 2123 2124 power-domains = <&gcc PCIE_0_PHY_GDSC>; 2125 2126 #clock-cells = <0>; 2127 clock-output-names = "pcie0_pipe_clk"; 2128 2129 #phy-cells = <0>; 2130 2131 status = "disabled"; 2132 }; 2133 2134 pcie1: pcie@1c08000 { 2135 device_type = "pci"; 2136 compatible = "qcom,pcie-sm8550"; 2137 reg = <0x0 0x01c08000 0x0 0x3000>, 2138 <0x0 0x40000000 0x0 0xf1d>, 2139 <0x0 0x40000f20 0x0 0xa8>, 2140 <0x0 0x40001000 0x0 0x1000>, 2141 <0x0 0x40100000 0x0 0x100000>; 2142 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2143 #address-cells = <3>; 2144 #size-cells = <2>; 2145 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2146 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2147 bus-range = <0x00 0xff>; 2148 2149 dma-coherent; 2150 2151 linux,pci-domain = <1>; 2152 num-lanes = <2>; 2153 2154 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>, 2155 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>, 2156 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>, 2157 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 0>, 2158 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>, 2159 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 0>, 2160 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, 2161 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH 0>, 2162 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 2163 interrupt-names = "msi0", 2164 "msi1", 2165 "msi2", 2166 "msi3", 2167 "msi4", 2168 "msi5", 2169 "msi6", 2170 "msi7", 2171 "global"; 2172 #interrupt-cells = <1>; 2173 interrupt-map-mask = <0 0 0 0x7>; 2174 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */ 2175 <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ 2176 <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ 2177 <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ 2178 2179 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2180 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2181 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2182 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2183 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2184 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2185 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2186 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2187 clock-names = "aux", 2188 "cfg", 2189 "bus_master", 2190 "bus_slave", 2191 "slave_q2a", 2192 "ddrss_sf_tbu", 2193 "noc_aggr", 2194 "cnoc_sf_axi"; 2195 2196 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2197 assigned-clock-rates = <19200000>; 2198 2199 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2200 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2201 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2202 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2203 interconnect-names = "pcie-mem", "cpu-pcie"; 2204 2205 msi-map = <0x0 &gic_its 0x1480 0x1>, 2206 <0x100 &gic_its 0x1481 0x1>; 2207 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 2208 <0x100 &apps_smmu 0x1481 0x1>; 2209 2210 resets = <&gcc GCC_PCIE_1_BCR>, 2211 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2212 reset-names = "pci", "link_down"; 2213 2214 power-domains = <&gcc PCIE_1_GDSC>; 2215 2216 phys = <&pcie1_phy>; 2217 phy-names = "pciephy"; 2218 2219 operating-points-v2 = <&pcie1_opp_table>; 2220 2221 status = "disabled"; 2222 2223 pcie1_opp_table: opp-table { 2224 compatible = "operating-points-v2"; 2225 2226 /* 2.5 GT/s x1 */ 2227 opp-2500000-1 { 2228 opp-hz = /bits/ 64 <2500000>; 2229 required-opps = <&rpmhpd_opp_low_svs>; 2230 opp-peak-kBps = <250000 1>; 2231 opp-level = <1>; 2232 }; 2233 2234 /* 2.5 GT/s x2 */ 2235 opp-5000000-1 { 2236 opp-hz = /bits/ 64 <5000000>; 2237 required-opps = <&rpmhpd_opp_low_svs>; 2238 opp-peak-kBps = <500000 1>; 2239 opp-level = <1>; 2240 }; 2241 2242 /* 5 GT/s x1 */ 2243 opp-5000000-2 { 2244 opp-hz = /bits/ 64 <5000000>; 2245 required-opps = <&rpmhpd_opp_low_svs>; 2246 opp-peak-kBps = <500000 1>; 2247 opp-level = <2>; 2248 }; 2249 2250 /* 5 GT/s x2 */ 2251 opp-10000000-2 { 2252 opp-hz = /bits/ 64 <10000000>; 2253 required-opps = <&rpmhpd_opp_low_svs>; 2254 opp-peak-kBps = <1000000 1>; 2255 opp-level = <2>; 2256 }; 2257 2258 /* 8 GT/s x1 */ 2259 opp-8000000-3 { 2260 opp-hz = /bits/ 64 <8000000>; 2261 required-opps = <&rpmhpd_opp_nom>; 2262 opp-peak-kBps = <984500 1>; 2263 opp-level = <3>; 2264 }; 2265 2266 /* 8 GT/s x2 */ 2267 opp-16000000-3 { 2268 opp-hz = /bits/ 64 <16000000>; 2269 required-opps = <&rpmhpd_opp_nom>; 2270 opp-peak-kBps = <1969000 1>; 2271 opp-level = <3>; 2272 }; 2273 2274 /* 16 GT/s x1 */ 2275 opp-16000000-4 { 2276 opp-hz = /bits/ 64 <16000000>; 2277 required-opps = <&rpmhpd_opp_nom>; 2278 opp-peak-kBps = <1969000 1>; 2279 opp-level = <4>; 2280 }; 2281 2282 /* 16 GT/s x2 */ 2283 opp-32000000-4 { 2284 opp-hz = /bits/ 64 <32000000>; 2285 required-opps = <&rpmhpd_opp_nom>; 2286 opp-peak-kBps = <3938000 1>; 2287 opp-level = <4>; 2288 }; 2289 }; 2290 2291 pcie@0 { 2292 device_type = "pci"; 2293 reg = <0x0 0x0 0x0 0x0 0x0>; 2294 bus-range = <0x01 0xff>; 2295 2296 #address-cells = <3>; 2297 #size-cells = <2>; 2298 ranges; 2299 }; 2300 }; 2301 2302 pcie1_phy: phy@1c0e000 { 2303 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 2304 reg = <0x0 0x01c0e000 0x0 0x2000>; 2305 2306 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2307 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2308 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 2309 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2310 <&gcc GCC_PCIE_1_PIPE_CLK>; 2311 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2312 "pipe"; 2313 2314 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 2315 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 2316 reset-names = "phy", "phy_nocsr"; 2317 2318 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2319 assigned-clock-rates = <100000000>; 2320 2321 power-domains = <&gcc PCIE_1_PHY_GDSC>; 2322 2323 #clock-cells = <1>; 2324 clock-output-names = "pcie1_pipe_clk"; 2325 2326 #phy-cells = <0>; 2327 2328 status = "disabled"; 2329 }; 2330 2331 cryptobam: dma-controller@1dc4000 { 2332 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2333 reg = <0x0 0x01dc4000 0x0 0x28000>; 2334 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; 2335 #dma-cells = <1>; 2336 qcom,ee = <0>; 2337 qcom,num-ees = <4>; 2338 num-channels = <20>; 2339 qcom,controlled-remotely; 2340 iommus = <&apps_smmu 0x480 0x0>, 2341 <&apps_smmu 0x481 0x0>; 2342 }; 2343 2344 crypto: crypto@1dfa000 { 2345 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 2346 reg = <0x0 0x01dfa000 0x0 0x6000>; 2347 dmas = <&cryptobam 4>, <&cryptobam 5>; 2348 dma-names = "rx", "tx"; 2349 iommus = <&apps_smmu 0x480 0x0>, 2350 <&apps_smmu 0x481 0x0>; 2351 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 2352 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2353 interconnect-names = "memory"; 2354 }; 2355 2356 ufs_mem_phy: phy@1d80000 { 2357 compatible = "qcom,sm8550-qmp-ufs-phy"; 2358 reg = <0x0 0x01d80000 0x0 0x2000>; 2359 clocks = <&rpmhcc RPMH_CXO_CLK>, 2360 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2361 <&tcsr TCSR_UFS_CLKREF_EN>; 2362 clock-names = "ref", 2363 "ref_aux", 2364 "qref"; 2365 2366 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 2367 2368 resets = <&ufs_mem_hc 0>; 2369 reset-names = "ufsphy"; 2370 2371 #clock-cells = <1>; 2372 #phy-cells = <0>; 2373 2374 status = "disabled"; 2375 }; 2376 2377 ufs_mem_hc: ufshc@1d84000 { 2378 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 2379 "jedec,ufs-2.0"; 2380 reg = <0x0 0x01d84000 0x0 0x3000>; 2381 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 2382 phys = <&ufs_mem_phy>; 2383 phy-names = "ufsphy"; 2384 lanes-per-direction = <2>; 2385 #reset-cells = <1>; 2386 resets = <&gcc GCC_UFS_PHY_BCR>; 2387 reset-names = "rst"; 2388 2389 power-domains = <&gcc UFS_PHY_GDSC>; 2390 required-opps = <&rpmhpd_opp_nom>; 2391 2392 iommus = <&apps_smmu 0x60 0x0>; 2393 dma-coherent; 2394 2395 operating-points-v2 = <&ufs_opp_table>; 2396 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2397 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2398 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2399 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2400 2401 interconnect-names = "ufs-ddr", "cpu-ufs"; 2402 clock-names = "core_clk", 2403 "bus_aggr_clk", 2404 "iface_clk", 2405 "core_clk_unipro", 2406 "ref_clk", 2407 "tx_lane0_sync_clk", 2408 "rx_lane0_sync_clk", 2409 "rx_lane1_sync_clk"; 2410 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2411 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2412 <&gcc GCC_UFS_PHY_AHB_CLK>, 2413 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2414 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 2415 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2416 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2417 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2418 qcom,ice = <&ice>; 2419 2420 status = "disabled"; 2421 2422 ufs_opp_table: opp-table { 2423 compatible = "operating-points-v2"; 2424 2425 opp-75000000 { 2426 opp-hz = /bits/ 64 <75000000>, 2427 /bits/ 64 <0>, 2428 /bits/ 64 <0>, 2429 /bits/ 64 <75000000>, 2430 /bits/ 64 <0>, 2431 /bits/ 64 <0>, 2432 /bits/ 64 <0>, 2433 /bits/ 64 <0>; 2434 required-opps = <&rpmhpd_opp_low_svs>; 2435 }; 2436 2437 opp-150000000 { 2438 opp-hz = /bits/ 64 <150000000>, 2439 /bits/ 64 <0>, 2440 /bits/ 64 <0>, 2441 /bits/ 64 <150000000>, 2442 /bits/ 64 <0>, 2443 /bits/ 64 <0>, 2444 /bits/ 64 <0>, 2445 /bits/ 64 <0>; 2446 required-opps = <&rpmhpd_opp_svs>; 2447 }; 2448 2449 opp-300000000 { 2450 opp-hz = /bits/ 64 <300000000>, 2451 /bits/ 64 <0>, 2452 /bits/ 64 <0>, 2453 /bits/ 64 <300000000>, 2454 /bits/ 64 <0>, 2455 /bits/ 64 <0>, 2456 /bits/ 64 <0>, 2457 /bits/ 64 <0>; 2458 required-opps = <&rpmhpd_opp_nom>; 2459 }; 2460 }; 2461 }; 2462 2463 ice: crypto@1d88000 { 2464 compatible = "qcom,sm8550-inline-crypto-engine", 2465 "qcom,inline-crypto-engine"; 2466 reg = <0 0x01d88000 0 0x18000>; 2467 2468 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2469 }; 2470 2471 tcsr_mutex: hwlock@1f40000 { 2472 compatible = "qcom,tcsr-mutex"; 2473 reg = <0 0x01f40000 0 0x20000>; 2474 #hwlock-cells = <1>; 2475 }; 2476 2477 tcsr: clock-controller@1fc0000 { 2478 compatible = "qcom,sm8550-tcsr", "syscon"; 2479 reg = <0 0x01fc0000 0 0x30000>; 2480 clocks = <&rpmhcc RPMH_CXO_CLK>; 2481 #clock-cells = <1>; 2482 #reset-cells = <1>; 2483 }; 2484 2485 gpu: gpu@3d00000 { 2486 compatible = "qcom,adreno-43050a01", "qcom,adreno"; 2487 reg = <0x0 0x03d00000 0x0 0x40000>, 2488 <0x0 0x03d9e000 0x0 0x1000>, 2489 <0x0 0x03d61000 0x0 0x800>; 2490 reg-names = "kgsl_3d0_reg_memory", 2491 "cx_mem", 2492 "cx_dbgc"; 2493 2494 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; 2495 2496 iommus = <&adreno_smmu 0 0x0>, 2497 <&adreno_smmu 1 0x0>; 2498 2499 operating-points-v2 = <&gpu_opp_table>; 2500 2501 qcom,gmu = <&gmu>; 2502 #cooling-cells = <2>; 2503 2504 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 2505 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2506 interconnect-names = "gfx-mem"; 2507 2508 status = "disabled"; 2509 2510 gpu_zap_shader: zap-shader { 2511 memory-region = <&gpu_micro_code_mem>; 2512 }; 2513 2514 /* Speedbin needs more work on A740+, keep only lower freqs */ 2515 gpu_opp_table: opp-table { 2516 compatible = "operating-points-v2"; 2517 2518 opp-680000000 { 2519 opp-hz = /bits/ 64 <680000000>; 2520 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2521 opp-peak-kBps = <16500000>; 2522 qcom,opp-acd-level = <0x882e5ffd>; 2523 }; 2524 2525 opp-615000000 { 2526 opp-hz = /bits/ 64 <615000000>; 2527 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2528 opp-peak-kBps = <12449218>; 2529 qcom,opp-acd-level = <0xa82f5ffd>; 2530 }; 2531 2532 opp-550000000 { 2533 opp-hz = /bits/ 64 <550000000>; 2534 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2535 opp-peak-kBps = <10687500>; 2536 qcom,opp-acd-level = <0xe0285ffd>; 2537 }; 2538 2539 opp-475000000 { 2540 opp-hz = /bits/ 64 <475000000>; 2541 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2542 opp-peak-kBps = <6074218>; 2543 qcom,opp-acd-level = <0xe0285ffd>; 2544 }; 2545 2546 opp-401000000 { 2547 opp-hz = /bits/ 64 <401000000>; 2548 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2549 opp-peak-kBps = <6074218>; 2550 qcom,opp-acd-level = <0xc02a5ffd>; 2551 }; 2552 2553 opp-348000000 { 2554 opp-hz = /bits/ 64 <348000000>; 2555 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 2556 opp-peak-kBps = <6074218>; 2557 qcom,opp-acd-level = <0xe02b5ffd>; 2558 }; 2559 2560 opp-295000000 { 2561 opp-hz = /bits/ 64 <295000000>; 2562 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2563 opp-peak-kBps = <6074218>; 2564 qcom,opp-acd-level = <0xe02d5ffd>; 2565 }; 2566 2567 opp-220000000 { 2568 opp-hz = /bits/ 64 <220000000>; 2569 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 2570 opp-peak-kBps = <2136718>; 2571 qcom,opp-acd-level = <0xc02f5ffd>; 2572 }; 2573 }; 2574 }; 2575 2576 gmu: gmu@3d6a000 { 2577 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu"; 2578 reg = <0x0 0x03d6a000 0x0 0x35000>, 2579 <0x0 0x03d50000 0x0 0x10000>, 2580 <0x0 0x0b280000 0x0 0x10000>; 2581 reg-names = "gmu", "rscc", "gmu_pdc"; 2582 2583 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>, 2584 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 2585 interrupt-names = "hfi", "gmu"; 2586 2587 clocks = <&gpucc GPU_CC_AHB_CLK>, 2588 <&gpucc GPU_CC_CX_GMU_CLK>, 2589 <&gpucc GPU_CC_CXO_CLK>, 2590 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2591 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2592 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2593 <&gpucc GPU_CC_DEMET_CLK>; 2594 clock-names = "ahb", 2595 "gmu", 2596 "cxo", 2597 "axi", 2598 "memnoc", 2599 "hub", 2600 "demet"; 2601 2602 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2603 <&gpucc GPU_CC_GX_GDSC>; 2604 power-domain-names = "cx", 2605 "gx"; 2606 2607 iommus = <&adreno_smmu 5 0x0>; 2608 2609 qcom,qmp = <&aoss_qmp>; 2610 2611 operating-points-v2 = <&gmu_opp_table>; 2612 2613 gmu_opp_table: opp-table { 2614 compatible = "operating-points-v2"; 2615 2616 opp-500000000 { 2617 opp-hz = /bits/ 64 <500000000>; 2618 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2619 }; 2620 2621 opp-200000000 { 2622 opp-hz = /bits/ 64 <200000000>; 2623 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2624 }; 2625 }; 2626 }; 2627 2628 gpucc: clock-controller@3d90000 { 2629 compatible = "qcom,sm8550-gpucc"; 2630 reg = <0 0x03d90000 0 0xa000>; 2631 clocks = <&bi_tcxo_div2>, 2632 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2633 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2634 #clock-cells = <1>; 2635 #reset-cells = <1>; 2636 #power-domain-cells = <1>; 2637 }; 2638 2639 adreno_smmu: iommu@3da0000 { 2640 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", 2641 "qcom,smmu-500", "arm,mmu-500"; 2642 reg = <0x0 0x03da0000 0x0 0x40000>; 2643 #iommu-cells = <2>; 2644 #global-interrupts = <1>; 2645 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>, 2646 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>, 2647 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>, 2648 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>, 2649 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>, 2650 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>, 2651 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>, 2652 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>, 2653 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>, 2654 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>, 2655 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>, 2656 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>, 2657 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>, 2658 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>, 2659 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>, 2660 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>, 2661 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>, 2662 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>, 2663 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>, 2664 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>, 2665 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, 2666 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>, 2667 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>, 2668 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>, 2669 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>, 2670 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>; 2671 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2672 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2673 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2674 <&gpucc GPU_CC_AHB_CLK>; 2675 clock-names = "hlos", 2676 "bus", 2677 "iface", 2678 "ahb"; 2679 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2680 dma-coherent; 2681 }; 2682 2683 ipa: ipa@3f40000 { 2684 compatible = "qcom,sm8550-ipa"; 2685 2686 iommus = <&apps_smmu 0x4a0 0x0>, 2687 <&apps_smmu 0x4a2 0x0>; 2688 reg = <0 0x3f40000 0 0x10000>, 2689 <0 0x3f50000 0 0x5000>, 2690 <0 0x3e04000 0 0xfc000>; 2691 reg-names = "ipa-reg", 2692 "ipa-shared", 2693 "gsi"; 2694 2695 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>, 2696 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>, 2697 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2698 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2699 interrupt-names = "ipa", 2700 "gsi", 2701 "ipa-clock-query", 2702 "ipa-setup-ready"; 2703 2704 clocks = <&rpmhcc RPMH_IPA_CLK>; 2705 clock-names = "core"; 2706 2707 interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS 2708 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2709 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2710 &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2711 interconnect-names = "memory", 2712 "config"; 2713 2714 qcom,qmp = <&aoss_qmp>; 2715 2716 qcom,smem-states = <&ipa_smp2p_out 0>, 2717 <&ipa_smp2p_out 1>; 2718 qcom,smem-state-names = "ipa-clock-enabled-valid", 2719 "ipa-clock-enabled"; 2720 2721 sram = <&ipa_modem_tables>; 2722 2723 status = "disabled"; 2724 }; 2725 2726 remoteproc_mpss: remoteproc@4080000 { 2727 compatible = "qcom,sm8550-mpss-pas"; 2728 reg = <0x0 0x04080000 0x0 0x10000>; 2729 2730 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, 2731 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2732 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2733 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2734 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2735 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2736 interrupt-names = "wdog", "fatal", "ready", "handover", 2737 "stop-ack", "shutdown-ack"; 2738 2739 clocks = <&rpmhcc RPMH_CXO_CLK>; 2740 clock-names = "xo"; 2741 2742 power-domains = <&rpmhpd RPMHPD_CX>, 2743 <&rpmhpd RPMHPD_MSS>; 2744 power-domain-names = "cx", "mss"; 2745 2746 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 2747 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2748 2749 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 2750 2751 qcom,qmp = <&aoss_qmp>; 2752 2753 qcom,smem-states = <&smp2p_modem_out 0>; 2754 qcom,smem-state-names = "stop"; 2755 2756 status = "disabled"; 2757 2758 glink-edge { 2759 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2760 IPCC_MPROC_SIGNAL_GLINK_QMP 2761 IRQ_TYPE_EDGE_RISING>; 2762 mboxes = <&ipcc IPCC_CLIENT_MPSS 2763 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2764 label = "mpss"; 2765 qcom,remote-pid = <1>; 2766 }; 2767 }; 2768 2769 remoteproc_adsp: remoteproc@6800000 { 2770 compatible = "qcom,sm8550-adsp-pas"; 2771 reg = <0x0 0x06800000 0x0 0x10000>; 2772 2773 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2774 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2775 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2776 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2777 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2778 interrupt-names = "wdog", "fatal", "ready", 2779 "handover", "stop-ack"; 2780 2781 clocks = <&rpmhcc RPMH_CXO_CLK>; 2782 clock-names = "xo"; 2783 2784 power-domains = <&rpmhpd RPMHPD_LCX>, 2785 <&rpmhpd RPMHPD_LMX>; 2786 power-domain-names = "lcx", "lmx"; 2787 2788 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 2789 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2790 2791 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2792 2793 qcom,qmp = <&aoss_qmp>; 2794 2795 qcom,smem-states = <&smp2p_adsp_out 0>; 2796 qcom,smem-state-names = "stop"; 2797 2798 status = "disabled"; 2799 2800 remoteproc_adsp_glink: glink-edge { 2801 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2802 IPCC_MPROC_SIGNAL_GLINK_QMP 2803 IRQ_TYPE_EDGE_RISING>; 2804 mboxes = <&ipcc IPCC_CLIENT_LPASS 2805 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2806 2807 label = "lpass"; 2808 qcom,remote-pid = <2>; 2809 2810 fastrpc { 2811 compatible = "qcom,fastrpc"; 2812 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2813 label = "adsp"; 2814 qcom,non-secure-domain; 2815 #address-cells = <1>; 2816 #size-cells = <0>; 2817 2818 compute-cb@3 { 2819 compatible = "qcom,fastrpc-compute-cb"; 2820 reg = <3>; 2821 iommus = <&apps_smmu 0x1003 0x80>, 2822 <&apps_smmu 0x1063 0x0>; 2823 dma-coherent; 2824 }; 2825 2826 compute-cb@4 { 2827 compatible = "qcom,fastrpc-compute-cb"; 2828 reg = <4>; 2829 iommus = <&apps_smmu 0x1004 0x80>, 2830 <&apps_smmu 0x1064 0x0>; 2831 dma-coherent; 2832 }; 2833 2834 compute-cb@5 { 2835 compatible = "qcom,fastrpc-compute-cb"; 2836 reg = <5>; 2837 iommus = <&apps_smmu 0x1005 0x80>, 2838 <&apps_smmu 0x1065 0x0>; 2839 dma-coherent; 2840 }; 2841 2842 compute-cb@6 { 2843 compatible = "qcom,fastrpc-compute-cb"; 2844 reg = <6>; 2845 iommus = <&apps_smmu 0x1006 0x80>, 2846 <&apps_smmu 0x1066 0x0>; 2847 dma-coherent; 2848 }; 2849 2850 compute-cb@7 { 2851 compatible = "qcom,fastrpc-compute-cb"; 2852 reg = <7>; 2853 iommus = <&apps_smmu 0x1007 0x80>, 2854 <&apps_smmu 0x1067 0x0>; 2855 dma-coherent; 2856 }; 2857 }; 2858 2859 gpr { 2860 compatible = "qcom,gpr"; 2861 qcom,glink-channels = "adsp_apps"; 2862 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2863 qcom,intents = <512 20>; 2864 #address-cells = <1>; 2865 #size-cells = <0>; 2866 2867 q6apm: service@1 { 2868 compatible = "qcom,q6apm"; 2869 reg = <GPR_APM_MODULE_IID>; 2870 #sound-dai-cells = <0>; 2871 qcom,protection-domain = "avs/audio", 2872 "msm/adsp/audio_pd"; 2873 2874 q6apmdai: dais { 2875 compatible = "qcom,q6apm-dais"; 2876 iommus = <&apps_smmu 0x1001 0x80>, 2877 <&apps_smmu 0x1061 0x0>; 2878 }; 2879 2880 q6apmbedai: bedais { 2881 compatible = "qcom,q6apm-lpass-dais"; 2882 #sound-dai-cells = <1>; 2883 }; 2884 }; 2885 2886 q6prm: service@2 { 2887 compatible = "qcom,q6prm"; 2888 reg = <GPR_PRM_MODULE_IID>; 2889 qcom,protection-domain = "avs/audio", 2890 "msm/adsp/audio_pd"; 2891 2892 q6prmcc: clock-controller { 2893 compatible = "qcom,q6prm-lpass-clocks"; 2894 #clock-cells = <2>; 2895 }; 2896 }; 2897 }; 2898 }; 2899 }; 2900 2901 lpass_wsa2macro: codec@6aa0000 { 2902 compatible = "qcom,sm8550-lpass-wsa-macro"; 2903 reg = <0 0x06aa0000 0 0x1000>; 2904 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2905 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2906 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2907 <&lpass_vamacro>; 2908 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2909 2910 #clock-cells = <0>; 2911 clock-output-names = "wsa2-mclk"; 2912 #sound-dai-cells = <1>; 2913 }; 2914 2915 swr3: soundwire@6ab0000 { 2916 compatible = "qcom,soundwire-v2.0.0"; 2917 reg = <0 0x06ab0000 0 0x10000>; 2918 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 2919 clocks = <&lpass_wsa2macro>; 2920 clock-names = "iface"; 2921 label = "WSA2"; 2922 2923 pinctrl-0 = <&wsa2_swr_active>; 2924 pinctrl-names = "default"; 2925 2926 qcom,din-ports = <4>; 2927 qcom,dout-ports = <9>; 2928 2929 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2930 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2931 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2932 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2933 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2934 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2935 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2936 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2937 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2938 2939 #address-cells = <2>; 2940 #size-cells = <0>; 2941 #sound-dai-cells = <1>; 2942 status = "disabled"; 2943 }; 2944 2945 lpass_rxmacro: codec@6ac0000 { 2946 compatible = "qcom,sm8550-lpass-rx-macro"; 2947 reg = <0 0x06ac0000 0 0x1000>; 2948 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2949 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2950 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2951 <&lpass_vamacro>; 2952 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2953 2954 #clock-cells = <0>; 2955 clock-output-names = "mclk"; 2956 #sound-dai-cells = <1>; 2957 }; 2958 2959 swr1: soundwire@6ad0000 { 2960 compatible = "qcom,soundwire-v2.0.0"; 2961 reg = <0 0x06ad0000 0 0x10000>; 2962 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 2963 clocks = <&lpass_rxmacro>; 2964 clock-names = "iface"; 2965 label = "RX"; 2966 2967 pinctrl-0 = <&rx_swr_active>; 2968 pinctrl-names = "default"; 2969 2970 qcom,din-ports = <1>; 2971 qcom,dout-ports = <11>; 2972 2973 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>; 2974 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2975 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2976 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2977 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2978 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>; 2979 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2980 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2981 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2982 2983 #address-cells = <2>; 2984 #size-cells = <0>; 2985 #sound-dai-cells = <1>; 2986 status = "disabled"; 2987 }; 2988 2989 lpass_txmacro: codec@6ae0000 { 2990 compatible = "qcom,sm8550-lpass-tx-macro"; 2991 reg = <0 0x06ae0000 0 0x1000>; 2992 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2993 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2994 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2995 <&lpass_vamacro>; 2996 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2997 2998 #clock-cells = <0>; 2999 clock-output-names = "mclk"; 3000 #sound-dai-cells = <1>; 3001 }; 3002 3003 lpass_wsamacro: codec@6b00000 { 3004 compatible = "qcom,sm8550-lpass-wsa-macro"; 3005 reg = <0 0x06b00000 0 0x1000>; 3006 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3007 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3008 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3009 <&lpass_vamacro>; 3010 clock-names = "mclk", "macro", "dcodec", "fsgen"; 3011 3012 #clock-cells = <0>; 3013 clock-output-names = "mclk"; 3014 #sound-dai-cells = <1>; 3015 }; 3016 3017 swr0: soundwire@6b10000 { 3018 compatible = "qcom,soundwire-v2.0.0"; 3019 reg = <0 0x06b10000 0 0x10000>; 3020 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 3021 clocks = <&lpass_wsamacro>; 3022 clock-names = "iface"; 3023 label = "WSA"; 3024 3025 pinctrl-0 = <&wsa_swr_active>; 3026 pinctrl-names = "default"; 3027 3028 qcom,din-ports = <4>; 3029 qcom,dout-ports = <9>; 3030 3031 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3032 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3033 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3034 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3035 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3036 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3037 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3038 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3039 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3040 3041 #address-cells = <2>; 3042 #size-cells = <0>; 3043 #sound-dai-cells = <1>; 3044 status = "disabled"; 3045 }; 3046 3047 swr2: soundwire@6d30000 { 3048 compatible = "qcom,soundwire-v2.0.0"; 3049 reg = <0 0x06d30000 0 0x10000>; 3050 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>, 3051 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>; 3052 interrupt-names = "core", "wakeup"; 3053 clocks = <&lpass_txmacro>; 3054 clock-names = "iface"; 3055 label = "TX"; 3056 3057 pinctrl-0 = <&tx_swr_active>; 3058 pinctrl-names = "default"; 3059 3060 qcom,din-ports = <4>; 3061 qcom,dout-ports = <0>; 3062 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3063 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 3064 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3065 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3066 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3067 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3068 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3069 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3070 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 3071 3072 #address-cells = <2>; 3073 #size-cells = <0>; 3074 #sound-dai-cells = <1>; 3075 status = "disabled"; 3076 }; 3077 3078 lpass_vamacro: codec@6d44000 { 3079 compatible = "qcom,sm8550-lpass-va-macro"; 3080 reg = <0 0x06d44000 0 0x1000>; 3081 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3082 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3083 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3084 clock-names = "mclk", "macro", "dcodec"; 3085 3086 #clock-cells = <0>; 3087 clock-output-names = "fsgen"; 3088 #sound-dai-cells = <1>; 3089 }; 3090 3091 lpass_tlmm: pinctrl@6e80000 { 3092 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 3093 reg = <0 0x06e80000 0 0x20000>, 3094 <0 0x07250000 0 0x10000>; 3095 gpio-controller; 3096 #gpio-cells = <2>; 3097 gpio-ranges = <&lpass_tlmm 0 0 23>; 3098 3099 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3100 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3101 clock-names = "core", "audio"; 3102 3103 tx_swr_active: tx-swr-active-state { 3104 clk-pins { 3105 pins = "gpio0"; 3106 function = "swr_tx_clk"; 3107 drive-strength = <2>; 3108 slew-rate = <1>; 3109 bias-disable; 3110 }; 3111 3112 data-pins { 3113 pins = "gpio1", "gpio2", "gpio14"; 3114 function = "swr_tx_data"; 3115 drive-strength = <2>; 3116 slew-rate = <1>; 3117 bias-bus-hold; 3118 }; 3119 }; 3120 3121 rx_swr_active: rx-swr-active-state { 3122 clk-pins { 3123 pins = "gpio3"; 3124 function = "swr_rx_clk"; 3125 drive-strength = <2>; 3126 slew-rate = <1>; 3127 bias-disable; 3128 }; 3129 3130 data-pins { 3131 pins = "gpio4", "gpio5"; 3132 function = "swr_rx_data"; 3133 drive-strength = <2>; 3134 slew-rate = <1>; 3135 bias-bus-hold; 3136 }; 3137 }; 3138 3139 dmic01_default: dmic01-default-state { 3140 clk-pins { 3141 pins = "gpio6"; 3142 function = "dmic1_clk"; 3143 drive-strength = <8>; 3144 output-high; 3145 }; 3146 3147 data-pins { 3148 pins = "gpio7"; 3149 function = "dmic1_data"; 3150 drive-strength = <8>; 3151 input-enable; 3152 }; 3153 }; 3154 3155 dmic23_default: dmic23-default-state { 3156 clk-pins { 3157 pins = "gpio8"; 3158 function = "dmic2_clk"; 3159 drive-strength = <8>; 3160 output-high; 3161 }; 3162 3163 data-pins { 3164 pins = "gpio9"; 3165 function = "dmic2_data"; 3166 drive-strength = <8>; 3167 input-enable; 3168 }; 3169 }; 3170 3171 wsa_swr_active: wsa-swr-active-state { 3172 clk-pins { 3173 pins = "gpio10"; 3174 function = "wsa_swr_clk"; 3175 drive-strength = <2>; 3176 slew-rate = <1>; 3177 bias-disable; 3178 }; 3179 3180 data-pins { 3181 pins = "gpio11"; 3182 function = "wsa_swr_data"; 3183 drive-strength = <2>; 3184 slew-rate = <1>; 3185 bias-bus-hold; 3186 }; 3187 }; 3188 3189 wsa2_swr_active: wsa2-swr-active-state { 3190 clk-pins { 3191 pins = "gpio15"; 3192 function = "wsa2_swr_clk"; 3193 drive-strength = <2>; 3194 slew-rate = <1>; 3195 bias-disable; 3196 }; 3197 3198 data-pins { 3199 pins = "gpio16"; 3200 function = "wsa2_swr_data"; 3201 drive-strength = <2>; 3202 slew-rate = <1>; 3203 bias-bus-hold; 3204 }; 3205 }; 3206 }; 3207 3208 lpass_lpiaon_noc: interconnect@7400000 { 3209 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 3210 reg = <0 0x07400000 0 0x19080>; 3211 #interconnect-cells = <2>; 3212 qcom,bcm-voters = <&apps_bcm_voter>; 3213 }; 3214 3215 lpass_lpicx_noc: interconnect@7430000 { 3216 compatible = "qcom,sm8550-lpass-lpicx-noc"; 3217 reg = <0 0x07430000 0 0x3a200>; 3218 #interconnect-cells = <2>; 3219 qcom,bcm-voters = <&apps_bcm_voter>; 3220 }; 3221 3222 lpass_ag_noc: interconnect@7e40000 { 3223 compatible = "qcom,sm8550-lpass-ag-noc"; 3224 reg = <0 0x07e40000 0 0xe080>; 3225 #interconnect-cells = <2>; 3226 qcom,bcm-voters = <&apps_bcm_voter>; 3227 }; 3228 3229 sdhc_2: mmc@8804000 { 3230 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 3231 reg = <0 0x08804000 0 0x1000>; 3232 3233 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>, 3234 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH 0>; 3235 interrupt-names = "hc_irq", "pwr_irq"; 3236 3237 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3238 <&gcc GCC_SDCC2_APPS_CLK>, 3239 <&bi_tcxo_div2>; 3240 clock-names = "iface", "core", "xo"; 3241 iommus = <&apps_smmu 0x540 0>; 3242 qcom,dll-config = <0x0007642c>; 3243 qcom,ddr-config = <0x80040868>; 3244 power-domains = <&rpmhpd RPMHPD_CX>; 3245 operating-points-v2 = <&sdhc2_opp_table>; 3246 3247 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3248 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3249 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3250 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 3251 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 3252 bus-width = <4>; 3253 max-sd-hs-hz = <37500000>; 3254 dma-coherent; 3255 3256 status = "disabled"; 3257 3258 sdhc2_opp_table: opp-table { 3259 compatible = "operating-points-v2"; 3260 3261 opp-19200000 { 3262 opp-hz = /bits/ 64 <19200000>; 3263 required-opps = <&rpmhpd_opp_min_svs>; 3264 }; 3265 3266 opp-50000000 { 3267 opp-hz = /bits/ 64 <50000000>; 3268 required-opps = <&rpmhpd_opp_low_svs>; 3269 }; 3270 3271 opp-100000000 { 3272 opp-hz = /bits/ 64 <100000000>; 3273 required-opps = <&rpmhpd_opp_svs>; 3274 }; 3275 3276 opp-202000000 { 3277 opp-hz = /bits/ 64 <202000000>; 3278 required-opps = <&rpmhpd_opp_svs_l1>; 3279 }; 3280 }; 3281 }; 3282 3283 iris: video-codec@aa00000 { 3284 compatible = "qcom,sm8550-iris"; 3285 3286 reg = <0 0x0aa00000 0 0xf0000>; 3287 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; 3288 3289 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 3290 <&videocc VIDEO_CC_MVS0_GDSC>, 3291 <&rpmhpd RPMHPD_MXC>, 3292 <&rpmhpd RPMHPD_MMCX>; 3293 power-domain-names = "venus", 3294 "vcodec0", 3295 "mxc", 3296 "mmcx"; 3297 operating-points-v2 = <&iris_opp_table>; 3298 3299 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3300 <&videocc VIDEO_CC_MVS0C_CLK>, 3301 <&videocc VIDEO_CC_MVS0_CLK>; 3302 clock-names = "iface", 3303 "core", 3304 "vcodec0_core"; 3305 3306 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3307 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 3308 <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS 3309 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3310 interconnect-names = "cpu-cfg", 3311 "video-mem"; 3312 3313 memory-region = <&video_mem>; 3314 3315 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 3316 reset-names = "bus"; 3317 3318 iommus = <&apps_smmu 0x1940 0>, 3319 <&apps_smmu 0x1947 0>; 3320 dma-coherent; 3321 3322 /* 3323 * IRIS firmware is signed by vendors, only 3324 * enable on boards where the proper signed firmware 3325 * is available. 3326 */ 3327 status = "disabled"; 3328 3329 iris_opp_table: opp-table { 3330 compatible = "operating-points-v2"; 3331 3332 opp-240000000 { 3333 opp-hz = /bits/ 64 <240000000>; 3334 required-opps = <&rpmhpd_opp_svs>, 3335 <&rpmhpd_opp_low_svs>; 3336 }; 3337 3338 opp-338000000 { 3339 opp-hz = /bits/ 64 <338000000>; 3340 required-opps = <&rpmhpd_opp_svs>, 3341 <&rpmhpd_opp_svs>; 3342 }; 3343 3344 opp-366000000 { 3345 opp-hz = /bits/ 64 <366000000>; 3346 required-opps = <&rpmhpd_opp_svs>, 3347 <&rpmhpd_opp_svs_l1>; 3348 }; 3349 3350 opp-444000000 { 3351 opp-hz = /bits/ 64 <444000000>; 3352 required-opps = <&rpmhpd_opp_svs_l1>, 3353 <&rpmhpd_opp_nom>; 3354 }; 3355 3356 opp-533333334 { 3357 opp-hz = /bits/ 64 <533333334>; 3358 required-opps = <&rpmhpd_opp_nom>, 3359 <&rpmhpd_opp_turbo>; 3360 }; 3361 }; 3362 }; 3363 3364 videocc: clock-controller@aaf0000 { 3365 compatible = "qcom,sm8550-videocc"; 3366 reg = <0 0x0aaf0000 0 0x10000>; 3367 clocks = <&bi_tcxo_div2>, 3368 <&gcc GCC_VIDEO_AHB_CLK>; 3369 power-domains = <&rpmhpd RPMHPD_MMCX>, 3370 <&rpmhpd RPMHPD_MXC>; 3371 required-opps = <&rpmhpd_opp_low_svs>, 3372 <&rpmhpd_opp_low_svs>; 3373 #clock-cells = <1>; 3374 #reset-cells = <1>; 3375 #power-domain-cells = <1>; 3376 }; 3377 3378 cci0: cci@ac15000 { 3379 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 3380 reg = <0 0x0ac15000 0 0x1000>; 3381 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>; 3382 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3383 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3384 <&camcc CAM_CC_CPAS_AHB_CLK>, 3385 <&camcc CAM_CC_CCI_0_CLK>; 3386 clock-names = "camnoc_axi", 3387 "cpas_ahb", 3388 "cci"; 3389 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 3390 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 3391 pinctrl-names = "default", "sleep"; 3392 status = "disabled"; 3393 #address-cells = <1>; 3394 #size-cells = <0>; 3395 3396 cci0_i2c0: i2c-bus@0 { 3397 reg = <0>; 3398 clock-frequency = <1000000>; 3399 #address-cells = <1>; 3400 #size-cells = <0>; 3401 }; 3402 3403 cci0_i2c1: i2c-bus@1 { 3404 reg = <1>; 3405 clock-frequency = <1000000>; 3406 #address-cells = <1>; 3407 #size-cells = <0>; 3408 }; 3409 }; 3410 3411 cci1: cci@ac16000 { 3412 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 3413 reg = <0 0x0ac16000 0 0x1000>; 3414 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING 0>; 3415 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3416 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3417 <&camcc CAM_CC_CPAS_AHB_CLK>, 3418 <&camcc CAM_CC_CCI_1_CLK>; 3419 clock-names = "camnoc_axi", 3420 "cpas_ahb", 3421 "cci"; 3422 pinctrl-0 = <&cci1_0_default>; 3423 pinctrl-1 = <&cci1_0_sleep>; 3424 pinctrl-names = "default", "sleep"; 3425 status = "disabled"; 3426 #address-cells = <1>; 3427 #size-cells = <0>; 3428 3429 cci1_i2c0: i2c-bus@0 { 3430 reg = <0>; 3431 clock-frequency = <1000000>; 3432 #address-cells = <1>; 3433 #size-cells = <0>; 3434 }; 3435 }; 3436 3437 cci2: cci@ac17000 { 3438 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 3439 reg = <0 0x0ac17000 0 0x1000>; 3440 interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING 0>; 3441 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3442 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3443 <&camcc CAM_CC_CPAS_AHB_CLK>, 3444 <&camcc CAM_CC_CCI_2_CLK>; 3445 clock-names = "camnoc_axi", 3446 "cpas_ahb", 3447 "cci"; 3448 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 3449 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 3450 pinctrl-names = "default", "sleep"; 3451 status = "disabled"; 3452 #address-cells = <1>; 3453 #size-cells = <0>; 3454 3455 cci2_i2c0: i2c-bus@0 { 3456 reg = <0>; 3457 clock-frequency = <1000000>; 3458 #address-cells = <1>; 3459 #size-cells = <0>; 3460 }; 3461 3462 cci2_i2c1: i2c-bus@1 { 3463 reg = <1>; 3464 clock-frequency = <1000000>; 3465 #address-cells = <1>; 3466 #size-cells = <0>; 3467 }; 3468 }; 3469 3470 camss: isp@acb7000 { 3471 compatible = "qcom,sm8550-camss"; 3472 3473 reg = <0x0 0x0acb7000 0x0 0x0d00>, 3474 <0x0 0x0acb9000 0x0 0x0d00>, 3475 <0x0 0x0acbb000 0x0 0x0d00>, 3476 <0x0 0x0acca000 0x0 0x0a00>, 3477 <0x0 0x0acce000 0x0 0x0a00>, 3478 <0x0 0x0acb6000 0x0 0x1000>, 3479 <0x0 0x0ace4000 0x0 0x2000>, 3480 <0x0 0x0ace6000 0x0 0x2000>, 3481 <0x0 0x0ace8000 0x0 0x2000>, 3482 <0x0 0x0acea000 0x0 0x2000>, 3483 <0x0 0x0acec000 0x0 0x2000>, 3484 <0x0 0x0acee000 0x0 0x2000>, 3485 <0x0 0x0acf0000 0x0 0x2000>, 3486 <0x0 0x0acf2000 0x0 0x2000>, 3487 <0x0 0x0ac62000 0x0 0xf000>, 3488 <0x0 0x0ac71000 0x0 0xf000>, 3489 <0x0 0x0ac80000 0x0 0xf000>, 3490 <0x0 0x0accb000 0x0 0x1800>, 3491 <0x0 0x0accf000 0x0 0x1800>; 3492 reg-names = "csid0", 3493 "csid1", 3494 "csid2", 3495 "csid_lite0", 3496 "csid_lite1", 3497 "csid_wrapper", 3498 "csiphy0", 3499 "csiphy1", 3500 "csiphy2", 3501 "csiphy3", 3502 "csiphy4", 3503 "csiphy5", 3504 "csiphy6", 3505 "csiphy7", 3506 "vfe0", 3507 "vfe1", 3508 "vfe2", 3509 "vfe_lite0", 3510 "vfe_lite1"; 3511 3512 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3513 <&camcc CAM_CC_CPAS_AHB_CLK>, 3514 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 3515 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 3516 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 3517 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 3518 <&camcc CAM_CC_CPAS_IFE_2_CLK>, 3519 <&camcc CAM_CC_CSID_CLK>, 3520 <&camcc CAM_CC_CSIPHY0_CLK>, 3521 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 3522 <&camcc CAM_CC_CSIPHY1_CLK>, 3523 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 3524 <&camcc CAM_CC_CSIPHY2_CLK>, 3525 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 3526 <&camcc CAM_CC_CSIPHY3_CLK>, 3527 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 3528 <&camcc CAM_CC_CSIPHY4_CLK>, 3529 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 3530 <&camcc CAM_CC_CSIPHY5_CLK>, 3531 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 3532 <&camcc CAM_CC_CSIPHY6_CLK>, 3533 <&camcc CAM_CC_CSI6PHYTIMER_CLK>, 3534 <&camcc CAM_CC_CSIPHY7_CLK>, 3535 <&camcc CAM_CC_CSI7PHYTIMER_CLK>, 3536 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 3537 <&gcc GCC_CAMERA_HF_AXI_CLK>, 3538 <&camcc CAM_CC_IFE_0_CLK>, 3539 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 3540 <&camcc CAM_CC_IFE_1_CLK>, 3541 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 3542 <&camcc CAM_CC_IFE_2_CLK>, 3543 <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, 3544 <&camcc CAM_CC_IFE_LITE_CLK>, 3545 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 3546 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 3547 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 3548 clock-names = "camnoc_axi", 3549 "cpas_ahb", 3550 "cpas_fast_ahb_clk", 3551 "cpas_ife_lite", 3552 "cpas_vfe0", 3553 "cpas_vfe1", 3554 "cpas_vfe2", 3555 "csid", 3556 "csiphy0", 3557 "csiphy0_timer", 3558 "csiphy1", 3559 "csiphy1_timer", 3560 "csiphy2", 3561 "csiphy2_timer", 3562 "csiphy3", 3563 "csiphy3_timer", 3564 "csiphy4", 3565 "csiphy4_timer", 3566 "csiphy5", 3567 "csiphy5_timer", 3568 "csiphy6", 3569 "csiphy6_timer", 3570 "csiphy7", 3571 "csiphy7_timer", 3572 "csiphy_rx", 3573 "gcc_axi_hf", 3574 "vfe0", 3575 "vfe0_fast_ahb", 3576 "vfe1", 3577 "vfe1_fast_ahb", 3578 "vfe2", 3579 "vfe2_fast_ahb", 3580 "vfe_lite", 3581 "vfe_lite_ahb", 3582 "vfe_lite_cphy_rx", 3583 "vfe_lite_csid"; 3584 3585 interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING 0>, 3586 <GIC_SPI 603 IRQ_TYPE_EDGE_RISING 0>, 3587 <GIC_SPI 431 IRQ_TYPE_EDGE_RISING 0>, 3588 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING 0>, 3589 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING 0>, 3590 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>, 3591 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>, 3592 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>, 3593 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING 0>, 3594 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING 0>, 3595 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING 0>, 3596 <GIC_SPI 278 IRQ_TYPE_EDGE_RISING 0>, 3597 <GIC_SPI 277 IRQ_TYPE_EDGE_RISING 0>, 3598 <GIC_SPI 602 IRQ_TYPE_EDGE_RISING 0>, 3599 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING 0>, 3600 <GIC_SPI 688 IRQ_TYPE_EDGE_RISING 0>, 3601 <GIC_SPI 606 IRQ_TYPE_EDGE_RISING 0>, 3602 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING 0>; 3603 interrupt-names = "csid0", 3604 "csid1", 3605 "csid2", 3606 "csid_lite0", 3607 "csid_lite1", 3608 "csiphy0", 3609 "csiphy1", 3610 "csiphy2", 3611 "csiphy3", 3612 "csiphy4", 3613 "csiphy5", 3614 "csiphy6", 3615 "csiphy7", 3616 "vfe0", 3617 "vfe1", 3618 "vfe2", 3619 "vfe_lite0", 3620 "vfe_lite1"; 3621 3622 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3623 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 3624 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 3625 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3626 interconnect-names = "ahb", 3627 "hf_0_mnoc"; 3628 3629 iommus = <&apps_smmu 0x800 0x20>; 3630 3631 power-domains = <&camcc CAM_CC_IFE_0_GDSC>, 3632 <&camcc CAM_CC_IFE_1_GDSC>, 3633 <&camcc CAM_CC_IFE_2_GDSC>, 3634 <&camcc CAM_CC_TITAN_TOP_GDSC>; 3635 power-domain-names = "ife0", 3636 "ife1", 3637 "ife2", 3638 "top"; 3639 3640 status = "disabled"; 3641 3642 ports { 3643 #address-cells = <1>; 3644 #size-cells = <0>; 3645 3646 port@0 { 3647 reg = <0>; 3648 }; 3649 3650 port@1 { 3651 reg = <1>; 3652 }; 3653 3654 port@2 { 3655 reg = <2>; 3656 }; 3657 3658 port@3 { 3659 reg = <3>; 3660 }; 3661 3662 port@4 { 3663 reg = <4>; 3664 }; 3665 3666 port@5 { 3667 reg = <5>; 3668 }; 3669 3670 port@6 { 3671 reg = <6>; 3672 }; 3673 3674 port@7 { 3675 reg = <7>; 3676 }; 3677 }; 3678 }; 3679 3680 camcc: clock-controller@ade0000 { 3681 compatible = "qcom,sm8550-camcc"; 3682 reg = <0 0x0ade0000 0 0x20000>; 3683 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3684 <&bi_tcxo_div2>, 3685 <&bi_tcxo_ao_div2>, 3686 <&sleep_clk>; 3687 power-domains = <&rpmhpd RPMHPD_MMCX>, 3688 <&rpmhpd RPMHPD_MXC>; 3689 required-opps = <&rpmhpd_opp_low_svs>, 3690 <&rpmhpd_opp_low_svs>; 3691 #clock-cells = <1>; 3692 #reset-cells = <1>; 3693 #power-domain-cells = <1>; 3694 }; 3695 3696 mdss: display-subsystem@ae00000 { 3697 compatible = "qcom,sm8550-mdss"; 3698 reg = <0 0x0ae00000 0 0x1000>; 3699 reg-names = "mdss"; 3700 3701 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>; 3702 interrupt-controller; 3703 #interrupt-cells = <1>; 3704 3705 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3706 <&gcc GCC_DISP_AHB_CLK>, 3707 <&gcc GCC_DISP_HF_AXI_CLK>, 3708 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3709 3710 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3711 3712 power-domains = <&dispcc MDSS_GDSC>; 3713 3714 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 3715 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3716 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3717 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3718 interconnect-names = "mdp0-mem", "cpu-cfg"; 3719 3720 iommus = <&apps_smmu 0x1c00 0x2>; 3721 3722 #address-cells = <2>; 3723 #size-cells = <2>; 3724 ranges; 3725 3726 status = "disabled"; 3727 3728 mdss_mdp: display-controller@ae01000 { 3729 compatible = "qcom,sm8550-dpu"; 3730 reg = <0 0x0ae01000 0 0x8f000>, 3731 <0 0x0aeb0000 0 0x3000>; 3732 reg-names = "mdp", "vbif"; 3733 3734 interrupt-parent = <&mdss>; 3735 interrupts = <0>; 3736 3737 clocks = <&gcc GCC_DISP_AHB_CLK>, 3738 <&gcc GCC_DISP_HF_AXI_CLK>, 3739 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3740 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3741 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3742 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3743 clock-names = "bus", 3744 "nrt_bus", 3745 "iface", 3746 "lut", 3747 "core", 3748 "vsync"; 3749 3750 power-domains = <&rpmhpd RPMHPD_MMCX>; 3751 3752 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3753 assigned-clock-rates = <19200000>; 3754 3755 operating-points-v2 = <&mdp_opp_table>; 3756 3757 ports { 3758 #address-cells = <1>; 3759 #size-cells = <0>; 3760 3761 port@0 { 3762 reg = <0>; 3763 dpu_intf1_out: endpoint { 3764 remote-endpoint = <&mdss_dsi0_in>; 3765 }; 3766 }; 3767 3768 port@1 { 3769 reg = <1>; 3770 dpu_intf2_out: endpoint { 3771 remote-endpoint = <&mdss_dsi1_in>; 3772 }; 3773 }; 3774 3775 port@2 { 3776 reg = <2>; 3777 dpu_intf0_out: endpoint { 3778 remote-endpoint = <&mdss_dp0_in>; 3779 }; 3780 }; 3781 }; 3782 3783 mdp_opp_table: opp-table { 3784 compatible = "operating-points-v2"; 3785 3786 opp-200000000 { 3787 opp-hz = /bits/ 64 <200000000>; 3788 required-opps = <&rpmhpd_opp_low_svs>; 3789 }; 3790 3791 opp-325000000 { 3792 opp-hz = /bits/ 64 <325000000>; 3793 required-opps = <&rpmhpd_opp_svs>; 3794 }; 3795 3796 opp-375000000 { 3797 opp-hz = /bits/ 64 <375000000>; 3798 required-opps = <&rpmhpd_opp_svs_l1>; 3799 }; 3800 3801 opp-514000000 { 3802 opp-hz = /bits/ 64 <514000000>; 3803 required-opps = <&rpmhpd_opp_nom>; 3804 }; 3805 }; 3806 }; 3807 3808 mdss_dp0: displayport-controller@ae90000 { 3809 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 3810 reg = <0 0xae90000 0 0x200>, 3811 <0 0xae90200 0 0x200>, 3812 <0 0xae90400 0 0xc00>, 3813 <0 0xae91000 0 0x400>, 3814 <0 0xae91400 0 0x400>; 3815 interrupt-parent = <&mdss>; 3816 interrupts = <12>; 3817 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3818 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3819 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3820 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3821 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 3822 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 3823 clock-names = "core_iface", 3824 "core_aux", 3825 "ctrl_link", 3826 "ctrl_link_iface", 3827 "stream_pixel", 3828 "stream_1_pixel"; 3829 3830 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3831 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 3832 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 3833 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3834 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3835 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3836 3837 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 3838 phy-names = "dp"; 3839 3840 #sound-dai-cells = <0>; 3841 3842 operating-points-v2 = <&dp_opp_table>; 3843 power-domains = <&rpmhpd RPMHPD_MMCX>; 3844 3845 status = "disabled"; 3846 3847 ports { 3848 #address-cells = <1>; 3849 #size-cells = <0>; 3850 3851 port@0 { 3852 reg = <0>; 3853 mdss_dp0_in: endpoint { 3854 remote-endpoint = <&dpu_intf0_out>; 3855 }; 3856 }; 3857 3858 port@1 { 3859 reg = <1>; 3860 mdss_dp0_out: endpoint { 3861 data-lanes = <0 1 2 3>; 3862 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 3863 }; 3864 }; 3865 }; 3866 3867 dp_opp_table: opp-table { 3868 compatible = "operating-points-v2"; 3869 3870 opp-162000000 { 3871 opp-hz = /bits/ 64 <162000000>; 3872 required-opps = <&rpmhpd_opp_low_svs_d1>; 3873 }; 3874 3875 opp-270000000 { 3876 opp-hz = /bits/ 64 <270000000>; 3877 required-opps = <&rpmhpd_opp_low_svs>; 3878 }; 3879 3880 opp-540000000 { 3881 opp-hz = /bits/ 64 <540000000>; 3882 required-opps = <&rpmhpd_opp_svs_l1>; 3883 }; 3884 3885 opp-810000000 { 3886 opp-hz = /bits/ 64 <810000000>; 3887 required-opps = <&rpmhpd_opp_nom>; 3888 }; 3889 }; 3890 }; 3891 3892 mdss_dsi0: dsi@ae94000 { 3893 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3894 reg = <0 0x0ae94000 0 0x400>; 3895 reg-names = "dsi_ctrl"; 3896 3897 interrupt-parent = <&mdss>; 3898 interrupts = <4>; 3899 3900 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3901 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3902 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3903 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3904 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3905 <&gcc GCC_DISP_HF_AXI_CLK>; 3906 clock-names = "byte", 3907 "byte_intf", 3908 "pixel", 3909 "core", 3910 "iface", 3911 "bus"; 3912 3913 power-domains = <&rpmhpd RPMHPD_MMCX>; 3914 3915 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3916 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3917 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3918 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 3919 3920 operating-points-v2 = <&mdss_dsi_opp_table>; 3921 3922 phys = <&mdss_dsi0_phy>; 3923 phy-names = "dsi"; 3924 3925 #address-cells = <1>; 3926 #size-cells = <0>; 3927 3928 status = "disabled"; 3929 3930 ports { 3931 #address-cells = <1>; 3932 #size-cells = <0>; 3933 3934 port@0 { 3935 reg = <0>; 3936 mdss_dsi0_in: endpoint { 3937 remote-endpoint = <&dpu_intf1_out>; 3938 }; 3939 }; 3940 3941 port@1 { 3942 reg = <1>; 3943 mdss_dsi0_out: endpoint { 3944 }; 3945 }; 3946 }; 3947 3948 mdss_dsi_opp_table: opp-table { 3949 compatible = "operating-points-v2"; 3950 3951 opp-187500000 { 3952 opp-hz = /bits/ 64 <187500000>; 3953 required-opps = <&rpmhpd_opp_low_svs>; 3954 }; 3955 3956 opp-300000000 { 3957 opp-hz = /bits/ 64 <300000000>; 3958 required-opps = <&rpmhpd_opp_svs>; 3959 }; 3960 3961 opp-358000000 { 3962 opp-hz = /bits/ 64 <358000000>; 3963 required-opps = <&rpmhpd_opp_svs_l1>; 3964 }; 3965 }; 3966 }; 3967 3968 mdss_dsi0_phy: phy@ae95000 { 3969 compatible = "qcom,sm8550-dsi-phy-4nm"; 3970 reg = <0 0x0ae95000 0 0x200>, 3971 <0 0x0ae95200 0 0x280>, 3972 <0 0x0ae95500 0 0x400>; 3973 reg-names = "dsi_phy", 3974 "dsi_phy_lane", 3975 "dsi_pll"; 3976 3977 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3978 <&rpmhcc RPMH_CXO_CLK>; 3979 clock-names = "iface", "ref"; 3980 3981 #clock-cells = <1>; 3982 #phy-cells = <0>; 3983 3984 status = "disabled"; 3985 }; 3986 3987 mdss_dsi1: dsi@ae96000 { 3988 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3989 reg = <0 0x0ae96000 0 0x400>; 3990 reg-names = "dsi_ctrl"; 3991 3992 interrupt-parent = <&mdss>; 3993 interrupts = <5>; 3994 3995 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3996 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3997 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3998 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3999 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4000 <&gcc GCC_DISP_HF_AXI_CLK>; 4001 clock-names = "byte", 4002 "byte_intf", 4003 "pixel", 4004 "core", 4005 "iface", 4006 "bus"; 4007 4008 power-domains = <&rpmhpd RPMHPD_MMCX>; 4009 4010 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 4011 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4012 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4013 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 4014 4015 operating-points-v2 = <&mdss_dsi_opp_table>; 4016 4017 phys = <&mdss_dsi1_phy>; 4018 phy-names = "dsi"; 4019 4020 #address-cells = <1>; 4021 #size-cells = <0>; 4022 4023 status = "disabled"; 4024 4025 ports { 4026 #address-cells = <1>; 4027 #size-cells = <0>; 4028 4029 port@0 { 4030 reg = <0>; 4031 mdss_dsi1_in: endpoint { 4032 remote-endpoint = <&dpu_intf2_out>; 4033 }; 4034 }; 4035 4036 port@1 { 4037 reg = <1>; 4038 mdss_dsi1_out: endpoint { 4039 }; 4040 }; 4041 }; 4042 }; 4043 4044 mdss_dsi1_phy: phy@ae97000 { 4045 compatible = "qcom,sm8550-dsi-phy-4nm"; 4046 reg = <0 0x0ae97000 0 0x200>, 4047 <0 0x0ae97200 0 0x280>, 4048 <0 0x0ae97500 0 0x400>; 4049 reg-names = "dsi_phy", 4050 "dsi_phy_lane", 4051 "dsi_pll"; 4052 4053 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4054 <&rpmhcc RPMH_CXO_CLK>; 4055 clock-names = "iface", "ref"; 4056 4057 #clock-cells = <1>; 4058 #phy-cells = <0>; 4059 4060 status = "disabled"; 4061 }; 4062 }; 4063 4064 dispcc: clock-controller@af00000 { 4065 compatible = "qcom,sm8550-dispcc"; 4066 reg = <0 0x0af00000 0 0x20000>; 4067 clocks = <&bi_tcxo_div2>, 4068 <&bi_tcxo_ao_div2>, 4069 <&gcc GCC_DISP_AHB_CLK>, 4070 <&sleep_clk>, 4071 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4072 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 4073 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4074 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 4075 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4076 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4077 <0>, /* dp1 */ 4078 <0>, 4079 <0>, /* dp2 */ 4080 <0>, 4081 <0>, /* dp3 */ 4082 <0>; 4083 power-domains = <&rpmhpd RPMHPD_MMCX>; 4084 required-opps = <&rpmhpd_opp_low_svs>; 4085 #clock-cells = <1>; 4086 #reset-cells = <1>; 4087 #power-domain-cells = <1>; 4088 }; 4089 4090 usb_1_hsphy: phy@88e3000 { 4091 compatible = "qcom,sm8550-snps-eusb2-phy"; 4092 reg = <0x0 0x088e3000 0x0 0x154>; 4093 #phy-cells = <0>; 4094 4095 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 4096 clock-names = "ref"; 4097 4098 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4099 4100 status = "disabled"; 4101 }; 4102 4103 usb_dp_qmpphy: phy@88e8000 { 4104 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 4105 reg = <0x0 0x088e8000 0x0 0x3000>; 4106 4107 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4108 <&rpmhcc RPMH_CXO_CLK>, 4109 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4110 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4111 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 4112 4113 power-domains = <&gcc USB3_PHY_GDSC>; 4114 4115 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4116 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 4117 reset-names = "phy", "common"; 4118 4119 #clock-cells = <1>; 4120 #phy-cells = <1>; 4121 4122 mode-switch; 4123 orientation-switch; 4124 4125 status = "disabled"; 4126 4127 ports { 4128 #address-cells = <1>; 4129 #size-cells = <0>; 4130 4131 port@0 { 4132 reg = <0>; 4133 4134 usb_dp_qmpphy_out: endpoint { 4135 }; 4136 }; 4137 4138 port@1 { 4139 reg = <1>; 4140 4141 usb_dp_qmpphy_usb_ss_in: endpoint { 4142 remote-endpoint = <&usb_1_dwc3_ss>; 4143 }; 4144 }; 4145 4146 port@2 { 4147 reg = <2>; 4148 4149 usb_dp_qmpphy_dp_in: endpoint { 4150 remote-endpoint = <&mdss_dp0_out>; 4151 }; 4152 }; 4153 }; 4154 }; 4155 4156 usb_1: usb@a600000 { 4157 compatible = "qcom,sm8550-dwc3", "qcom,snps-dwc3"; 4158 reg = <0x0 0x0a600000 0x0 0xfc100>; 4159 4160 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4161 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4162 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4163 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4164 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4165 <&tcsr TCSR_USB3_CLKREF_EN>; 4166 clock-names = "cfg_noc", 4167 "core", 4168 "iface", 4169 "sleep", 4170 "mock_utmi", 4171 "xo"; 4172 4173 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4174 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4175 assigned-clock-rates = <19200000>, <200000000>; 4176 4177 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, 4178 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, 4179 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, 4180 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4181 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4182 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4183 interrupt-names = "dwc_usb3", 4184 "pwr_event", 4185 "hs_phy_irq", 4186 "dp_hs_phy_irq", 4187 "dm_hs_phy_irq", 4188 "ss_phy_irq"; 4189 4190 power-domains = <&gcc USB30_PRIM_GDSC>; 4191 required-opps = <&rpmhpd_opp_nom>; 4192 4193 resets = <&gcc GCC_USB30_PRIM_BCR>; 4194 4195 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 4196 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4197 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4198 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 4199 interconnect-names = "usb-ddr", "apps-usb"; 4200 4201 iommus = <&apps_smmu 0x40 0x0>; 4202 4203 phys = <&usb_1_hsphy>, 4204 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 4205 phy-names = "usb2-phy", "usb3-phy"; 4206 4207 snps,hird-threshold = /bits/ 8 <0x0>; 4208 snps,usb2-gadget-lpm-disable; 4209 snps,dis_u2_susphy_quirk; 4210 snps,dis_enblslpm_quirk; 4211 snps,dis-u1-entry-quirk; 4212 snps,dis-u2-entry-quirk; 4213 snps,is-utmi-l1-suspend; 4214 snps,usb3_lpm_capable; 4215 snps,usb2-lpm-disable; 4216 snps,has-lpm-erratum; 4217 tx-fifo-resize; 4218 4219 dma-coherent; 4220 4221 usb-role-switch; 4222 4223 status = "disabled"; 4224 4225 ports { 4226 #address-cells = <1>; 4227 #size-cells = <0>; 4228 4229 port@0 { 4230 reg = <0>; 4231 4232 usb_1_dwc3_hs: endpoint { 4233 }; 4234 }; 4235 4236 port@1 { 4237 reg = <1>; 4238 4239 usb_1_dwc3_ss: endpoint { 4240 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 4241 }; 4242 }; 4243 }; 4244 }; 4245 4246 pdc: interrupt-controller@b220000 { 4247 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 4248 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 4249 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4250 <125 63 1>, <126 716 12>, 4251 <138 251 5>; 4252 #interrupt-cells = <2>; 4253 interrupt-parent = <&intc>; 4254 interrupt-controller; 4255 }; 4256 4257 tsens0: thermal-sensor@c271000 { 4258 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 4259 reg = <0 0x0c271000 0 0x1000>, /* TM */ 4260 <0 0x0c222000 0 0x1000>; /* SROT */ 4261 #qcom,sensors = <16>; 4262 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>, 4263 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 4264 interrupt-names = "uplow", "critical"; 4265 #thermal-sensor-cells = <1>; 4266 }; 4267 4268 tsens1: thermal-sensor@c272000 { 4269 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 4270 reg = <0 0x0c272000 0 0x1000>, /* TM */ 4271 <0 0x0c223000 0 0x1000>; /* SROT */ 4272 #qcom,sensors = <16>; 4273 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>, 4274 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 4275 interrupt-names = "uplow", "critical"; 4276 #thermal-sensor-cells = <1>; 4277 }; 4278 4279 tsens2: thermal-sensor@c273000 { 4280 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 4281 reg = <0 0x0c273000 0 0x1000>, /* TM */ 4282 <0 0x0c224000 0 0x1000>; /* SROT */ 4283 #qcom,sensors = <16>; 4284 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>, 4285 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 4286 interrupt-names = "uplow", "critical"; 4287 #thermal-sensor-cells = <1>; 4288 }; 4289 4290 aoss_qmp: power-management@c300000 { 4291 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 4292 reg = <0 0x0c300000 0 0x400>; 4293 interrupt-parent = <&ipcc>; 4294 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4295 IRQ_TYPE_EDGE_RISING>; 4296 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4297 4298 #clock-cells = <0>; 4299 }; 4300 4301 sram@c3f0000 { 4302 compatible = "qcom,rpmh-stats"; 4303 reg = <0 0x0c3f0000 0 0x400>; 4304 qcom,qmp = <&aoss_qmp>; 4305 }; 4306 4307 spmi_bus: spmi@c400000 { 4308 compatible = "qcom,spmi-pmic-arb"; 4309 reg = <0 0x0c400000 0 0x3000>, 4310 <0 0x0c500000 0 0x400000>, 4311 <0 0x0c440000 0 0x80000>, 4312 <0 0x0c4c0000 0 0x20000>, 4313 <0 0x0c42d000 0 0x4000>; 4314 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4315 interrupt-names = "periph_irq"; 4316 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4317 qcom,ee = <0>; 4318 qcom,channel = <0>; 4319 qcom,bus-id = <0>; 4320 #address-cells = <2>; 4321 #size-cells = <0>; 4322 interrupt-controller; 4323 #interrupt-cells = <4>; 4324 }; 4325 4326 tlmm: pinctrl@f100000 { 4327 compatible = "qcom,sm8550-tlmm"; 4328 reg = <0 0x0f100000 0 0x300000>; 4329 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; 4330 gpio-controller; 4331 #gpio-cells = <2>; 4332 interrupt-controller; 4333 #interrupt-cells = <2>; 4334 gpio-ranges = <&tlmm 0 0 211>; 4335 wakeup-parent = <&pdc>; 4336 4337 cam0_default: cam0-default-state { 4338 mclk-pins { 4339 pins = "gpio100"; 4340 function = "cam_mclk"; 4341 drive-strength = <2>; 4342 bias-disable; 4343 }; 4344 }; 4345 4346 cam0_sleep: cam0-sleep-state { 4347 mclk-pins { 4348 pins = "gpio100"; 4349 function = "cam_mclk"; 4350 drive-strength = <2>; 4351 bias-pull-down; 4352 }; 4353 }; 4354 4355 cam1_default: cam1-default-state { 4356 mclk-pins { 4357 pins = "gpio101"; 4358 function = "cam_mclk"; 4359 drive-strength = <2>; 4360 bias-disable; 4361 }; 4362 }; 4363 4364 cam1_sleep: cam1-sleep-state { 4365 mclk-pins { 4366 pins = "gpio101"; 4367 function = "cam_mclk"; 4368 drive-strength = <2>; 4369 bias-pull-down; 4370 }; 4371 }; 4372 4373 cam2_default: cam2-default-state { 4374 mclk-pins { 4375 pins = "gpio102"; 4376 function = "cam_mclk"; 4377 drive-strength = <2>; 4378 bias-disable; 4379 }; 4380 }; 4381 4382 cam2_sleep: cam2-sleep-state { 4383 mclk-pins { 4384 pins = "gpio102"; 4385 function = "cam_mclk"; 4386 drive-strength = <2>; 4387 bias-pull-down; 4388 }; 4389 }; 4390 4391 cam3_default: cam3-default-state { 4392 mclk-pins { 4393 pins = "gpio103"; 4394 function = "cam_mclk"; 4395 drive-strength = <2>; 4396 bias-disable; 4397 }; 4398 }; 4399 4400 cam3_sleep: cam3-sleep-state { 4401 mclk-pins { 4402 pins = "gpio103"; 4403 function = "cam_mclk"; 4404 drive-strength = <2>; 4405 bias-pull-down; 4406 }; 4407 }; 4408 4409 cam4_default: cam4-default-state { 4410 mclk-pins { 4411 pins = "gpio104"; 4412 function = "cam_aon_mclk4"; 4413 drive-strength = <2>; 4414 bias-disable; 4415 }; 4416 }; 4417 4418 cam4_sleep: cam4-sleep-state { 4419 mclk-pins { 4420 pins = "gpio104"; 4421 function = "cam_aon_mclk4"; 4422 drive-strength = <2>; 4423 bias-pull-down; 4424 }; 4425 }; 4426 4427 cam5_default: cam5-default-state { 4428 mclk-pins { 4429 pins = "gpio105"; 4430 function = "cam_mclk"; 4431 drive-strength = <2>; 4432 bias-disable; 4433 }; 4434 }; 4435 4436 cam5_sleep: cam5-sleep-state { 4437 mclk-pins { 4438 pins = "gpio105"; 4439 function = "cam_mclk"; 4440 drive-strength = <2>; 4441 bias-pull-down; 4442 }; 4443 }; 4444 4445 cam6_default: cam6-default-state { 4446 mclk-pins { 4447 pins = "gpio106"; 4448 function = "cam_mclk"; 4449 drive-strength = <2>; 4450 bias-disable; 4451 }; 4452 }; 4453 4454 cam6_sleep: cam6-sleep-state { 4455 mclk-pins { 4456 pins = "gpio106"; 4457 function = "cam_mclk"; 4458 drive-strength = <2>; 4459 bias-pull-down; 4460 }; 4461 }; 4462 4463 cam7_default: cam7-default-state { 4464 mclk-pins { 4465 pins = "gpio107"; 4466 function = "cam_mclk"; 4467 drive-strength = <2>; 4468 bias-disable; 4469 }; 4470 }; 4471 4472 cam7_sleep: cam7-sleep-state { 4473 mclk-pins { 4474 pins = "gpio107"; 4475 function = "cam_mclk"; 4476 drive-strength = <2>; 4477 bias-pull-down; 4478 }; 4479 }; 4480 4481 cci0_0_default: cci0-0-default-state { 4482 sda-pins { 4483 pins = "gpio110"; 4484 function = "cci_i2c_sda"; 4485 drive-strength = <2>; 4486 bias-pull-up = <2200>; 4487 }; 4488 4489 scl-pins { 4490 pins = "gpio111"; 4491 function = "cci_i2c_scl"; 4492 drive-strength = <2>; 4493 bias-pull-up = <2200>; 4494 }; 4495 }; 4496 4497 cci0_0_sleep: cci0-0-sleep-state { 4498 sda-pins { 4499 pins = "gpio110"; 4500 function = "cci_i2c_sda"; 4501 drive-strength = <2>; 4502 bias-pull-down; 4503 }; 4504 4505 scl-pins { 4506 pins = "gpio111"; 4507 function = "cci_i2c_scl"; 4508 drive-strength = <2>; 4509 bias-pull-down; 4510 }; 4511 }; 4512 4513 cci0_1_default: cci0-1-default-state { 4514 sda-pins { 4515 pins = "gpio112"; 4516 function = "cci_i2c_sda"; 4517 drive-strength = <2>; 4518 bias-pull-up = <2200>; 4519 }; 4520 4521 scl-pins { 4522 pins = "gpio113"; 4523 function = "cci_i2c_scl"; 4524 drive-strength = <2>; 4525 bias-pull-up = <2200>; 4526 }; 4527 }; 4528 4529 cci0_1_sleep: cci0-1-sleep-state { 4530 sda-pins { 4531 pins = "gpio112"; 4532 function = "cci_i2c_sda"; 4533 drive-strength = <2>; 4534 bias-pull-down; 4535 }; 4536 4537 scl-pins { 4538 pins = "gpio113"; 4539 function = "cci_i2c_scl"; 4540 drive-strength = <2>; 4541 bias-pull-down; 4542 }; 4543 }; 4544 4545 cci1_0_default: cci1-0-default-state { 4546 sda-pins { 4547 pins = "gpio114"; 4548 function = "cci_i2c_sda"; 4549 drive-strength = <2>; 4550 bias-pull-up = <2200>; 4551 }; 4552 4553 scl-pins { 4554 pins = "gpio115"; 4555 function = "cci_i2c_scl"; 4556 drive-strength = <2>; 4557 bias-pull-up = <2200>; 4558 }; 4559 }; 4560 4561 cci1_0_sleep: cci1-0-sleep-state { 4562 sda-pins { 4563 pins = "gpio114"; 4564 function = "cci_i2c_sda"; 4565 drive-strength = <2>; 4566 bias-pull-down; 4567 }; 4568 4569 scl-pins { 4570 pins = "gpio115"; 4571 function = "cci_i2c_scl"; 4572 drive-strength = <2>; 4573 bias-pull-down; 4574 }; 4575 }; 4576 4577 cci2_0_default: cci2-0-default-state { 4578 sda-pins { 4579 pins = "gpio74"; 4580 function = "cci_i2c_sda"; 4581 drive-strength = <2>; 4582 bias-pull-up = <2200>; 4583 }; 4584 4585 scl-pins { 4586 pins = "gpio75"; 4587 function = "cci_i2c_scl"; 4588 drive-strength = <2>; 4589 bias-pull-up = <2200>; 4590 }; 4591 }; 4592 4593 cci2_0_sleep: cci2-0-sleep-state { 4594 sda-pins { 4595 pins = "gpio74"; 4596 function = "cci_i2c_sda"; 4597 drive-strength = <2>; 4598 bias-pull-down; 4599 }; 4600 4601 scl-pins { 4602 pins = "gpio75"; 4603 function = "cci_i2c_scl"; 4604 drive-strength = <2>; 4605 bias-pull-down; 4606 }; 4607 }; 4608 4609 cci2_1_default: cci2-1-default-state { 4610 sda-pins { 4611 pins = "gpio0"; 4612 function = "cci_i2c_sda"; 4613 drive-strength = <2>; 4614 bias-pull-up = <2200>; 4615 }; 4616 4617 scl-pins { 4618 pins = "gpio1"; 4619 function = "cci_i2c_scl"; 4620 drive-strength = <2>; 4621 bias-pull-up = <2200>; 4622 }; 4623 }; 4624 4625 cci2_1_sleep: cci2-1-sleep-state { 4626 sda-pins { 4627 pins = "gpio0"; 4628 function = "cci_i2c_sda"; 4629 drive-strength = <2>; 4630 bias-pull-down; 4631 }; 4632 4633 scl-pins { 4634 pins = "gpio1"; 4635 function = "cci_i2c_scl"; 4636 drive-strength = <2>; 4637 bias-pull-down; 4638 }; 4639 }; 4640 4641 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 4642 /* SDA, SCL */ 4643 pins = "gpio16", "gpio17"; 4644 function = "i2chub0_se0"; 4645 drive-strength = <2>; 4646 bias-pull-up; 4647 }; 4648 4649 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 4650 /* SDA, SCL */ 4651 pins = "gpio18", "gpio19"; 4652 function = "i2chub0_se1"; 4653 drive-strength = <2>; 4654 bias-pull-up; 4655 }; 4656 4657 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 4658 /* SDA, SCL */ 4659 pins = "gpio20", "gpio21"; 4660 function = "i2chub0_se2"; 4661 drive-strength = <2>; 4662 bias-pull-up; 4663 }; 4664 4665 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 4666 /* SDA, SCL */ 4667 pins = "gpio22", "gpio23"; 4668 function = "i2chub0_se3"; 4669 drive-strength = <2>; 4670 bias-pull-up; 4671 }; 4672 4673 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 4674 /* SDA, SCL */ 4675 pins = "gpio4", "gpio5"; 4676 function = "i2chub0_se4"; 4677 drive-strength = <2>; 4678 bias-pull-up; 4679 }; 4680 4681 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 4682 /* SDA, SCL */ 4683 pins = "gpio6", "gpio7"; 4684 function = "i2chub0_se5"; 4685 drive-strength = <2>; 4686 bias-pull-up; 4687 }; 4688 4689 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 4690 /* SDA, SCL */ 4691 pins = "gpio8", "gpio9"; 4692 function = "i2chub0_se6"; 4693 drive-strength = <2>; 4694 bias-pull-up; 4695 }; 4696 4697 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 4698 /* SDA, SCL */ 4699 pins = "gpio10", "gpio11"; 4700 function = "i2chub0_se7"; 4701 drive-strength = <2>; 4702 bias-pull-up; 4703 }; 4704 4705 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 4706 /* SDA, SCL */ 4707 pins = "gpio206", "gpio207"; 4708 function = "i2chub0_se8"; 4709 drive-strength = <2>; 4710 bias-pull-up; 4711 }; 4712 4713 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 4714 /* SDA, SCL */ 4715 pins = "gpio84", "gpio85"; 4716 function = "i2chub0_se9"; 4717 drive-strength = <2>; 4718 bias-pull-up; 4719 }; 4720 4721 pcie0_default_state: pcie0-default-state { 4722 perst-pins { 4723 pins = "gpio94"; 4724 function = "gpio"; 4725 drive-strength = <2>; 4726 bias-pull-down; 4727 }; 4728 4729 clkreq-pins { 4730 pins = "gpio95"; 4731 function = "pcie0_clk_req_n"; 4732 drive-strength = <2>; 4733 bias-pull-up; 4734 }; 4735 4736 wake-pins { 4737 pins = "gpio96"; 4738 function = "gpio"; 4739 drive-strength = <2>; 4740 bias-pull-up; 4741 }; 4742 }; 4743 4744 pcie1_default_state: pcie1-default-state { 4745 perst-pins { 4746 pins = "gpio97"; 4747 function = "gpio"; 4748 drive-strength = <2>; 4749 bias-pull-down; 4750 }; 4751 4752 clkreq-pins { 4753 pins = "gpio98"; 4754 function = "pcie1_clk_req_n"; 4755 drive-strength = <2>; 4756 bias-pull-up; 4757 }; 4758 4759 wake-pins { 4760 pins = "gpio99"; 4761 function = "gpio"; 4762 drive-strength = <2>; 4763 bias-pull-up; 4764 }; 4765 }; 4766 4767 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4768 /* SDA, SCL */ 4769 pins = "gpio28", "gpio29"; 4770 function = "qup1_se0"; 4771 drive-strength = <2>; 4772 bias-pull-up = <2200>; 4773 }; 4774 4775 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4776 /* SDA, SCL */ 4777 pins = "gpio32", "gpio33"; 4778 function = "qup1_se1"; 4779 drive-strength = <2>; 4780 bias-pull-up = <2200>; 4781 }; 4782 4783 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4784 /* SDA, SCL */ 4785 pins = "gpio36", "gpio37"; 4786 function = "qup1_se2"; 4787 drive-strength = <2>; 4788 bias-pull-up = <2200>; 4789 }; 4790 4791 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4792 /* SDA, SCL */ 4793 pins = "gpio40", "gpio41"; 4794 function = "qup1_se3"; 4795 drive-strength = <2>; 4796 bias-pull-up = <2200>; 4797 }; 4798 4799 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4800 /* SDA, SCL */ 4801 pins = "gpio44", "gpio45"; 4802 function = "qup1_se4"; 4803 drive-strength = <2>; 4804 bias-pull-up = <2200>; 4805 }; 4806 4807 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4808 /* SDA, SCL */ 4809 pins = "gpio52", "gpio53"; 4810 function = "qup1_se5"; 4811 drive-strength = <2>; 4812 bias-pull-up = <2200>; 4813 }; 4814 4815 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4816 /* SDA, SCL */ 4817 pins = "gpio48", "gpio49"; 4818 function = "qup1_se6"; 4819 drive-strength = <2>; 4820 bias-pull-up = <2200>; 4821 }; 4822 4823 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4824 scl-pins { 4825 pins = "gpio57"; 4826 function = "qup2_se0_l1_mira"; 4827 drive-strength = <2>; 4828 bias-pull-up = <2200>; 4829 }; 4830 4831 sda-pins { 4832 pins = "gpio56"; 4833 function = "qup2_se0_l0_mira"; 4834 drive-strength = <2>; 4835 bias-pull-up = <2200>; 4836 }; 4837 }; 4838 4839 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4840 /* SDA, SCL */ 4841 pins = "gpio60", "gpio61"; 4842 function = "qup2_se1"; 4843 drive-strength = <2>; 4844 bias-pull-up = <2200>; 4845 }; 4846 4847 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4848 /* SDA, SCL */ 4849 pins = "gpio64", "gpio65"; 4850 function = "qup2_se2"; 4851 drive-strength = <2>; 4852 bias-pull-up = <2200>; 4853 }; 4854 4855 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4856 /* SDA, SCL */ 4857 pins = "gpio68", "gpio69"; 4858 function = "qup2_se3"; 4859 drive-strength = <2>; 4860 bias-pull-up = <2200>; 4861 }; 4862 4863 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4864 /* SDA, SCL */ 4865 pins = "gpio2", "gpio3"; 4866 function = "qup2_se4"; 4867 drive-strength = <2>; 4868 bias-pull-up = <2200>; 4869 }; 4870 4871 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4872 /* SDA, SCL */ 4873 pins = "gpio80", "gpio81"; 4874 function = "qup2_se5"; 4875 drive-strength = <2>; 4876 bias-pull-up = <2200>; 4877 }; 4878 4879 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4880 /* SDA, SCL */ 4881 pins = "gpio72", "gpio106"; 4882 function = "qup2_se7"; 4883 drive-strength = <2>; 4884 bias-pull-up = <2200>; 4885 }; 4886 4887 qup_spi0_cs: qup-spi0-cs-state { 4888 pins = "gpio31"; 4889 function = "qup1_se0"; 4890 drive-strength = <6>; 4891 bias-disable; 4892 }; 4893 4894 qup_spi0_data_clk: qup-spi0-data-clk-state { 4895 /* MISO, MOSI, CLK */ 4896 pins = "gpio28", "gpio29", "gpio30"; 4897 function = "qup1_se0"; 4898 drive-strength = <6>; 4899 bias-disable; 4900 }; 4901 4902 qup_spi1_cs: qup-spi1-cs-state { 4903 pins = "gpio35"; 4904 function = "qup1_se1"; 4905 drive-strength = <6>; 4906 bias-disable; 4907 }; 4908 4909 qup_spi1_data_clk: qup-spi1-data-clk-state { 4910 /* MISO, MOSI, CLK */ 4911 pins = "gpio32", "gpio33", "gpio34"; 4912 function = "qup1_se1"; 4913 drive-strength = <6>; 4914 bias-disable; 4915 }; 4916 4917 qup_spi2_cs: qup-spi2-cs-state { 4918 pins = "gpio39"; 4919 function = "qup1_se2"; 4920 drive-strength = <6>; 4921 bias-disable; 4922 }; 4923 4924 qup_spi2_data_clk: qup-spi2-data-clk-state { 4925 /* MISO, MOSI, CLK */ 4926 pins = "gpio36", "gpio37", "gpio38"; 4927 function = "qup1_se2"; 4928 drive-strength = <6>; 4929 bias-disable; 4930 }; 4931 4932 qup_spi3_cs: qup-spi3-cs-state { 4933 pins = "gpio43"; 4934 function = "qup1_se3"; 4935 drive-strength = <6>; 4936 bias-disable; 4937 }; 4938 4939 qup_spi3_data_clk: qup-spi3-data-clk-state { 4940 /* MISO, MOSI, CLK */ 4941 pins = "gpio40", "gpio41", "gpio42"; 4942 function = "qup1_se3"; 4943 drive-strength = <6>; 4944 bias-disable; 4945 }; 4946 4947 qup_spi4_cs: qup-spi4-cs-state { 4948 pins = "gpio47"; 4949 function = "qup1_se4"; 4950 drive-strength = <6>; 4951 bias-disable; 4952 }; 4953 4954 qup_spi4_data_clk: qup-spi4-data-clk-state { 4955 /* MISO, MOSI, CLK */ 4956 pins = "gpio44", "gpio45", "gpio46"; 4957 function = "qup1_se4"; 4958 drive-strength = <6>; 4959 bias-disable; 4960 }; 4961 4962 qup_spi5_cs: qup-spi5-cs-state { 4963 pins = "gpio55"; 4964 function = "qup1_se5"; 4965 drive-strength = <6>; 4966 bias-disable; 4967 }; 4968 4969 qup_spi5_data_clk: qup-spi5-data-clk-state { 4970 /* MISO, MOSI, CLK */ 4971 pins = "gpio52", "gpio53", "gpio54"; 4972 function = "qup1_se5"; 4973 drive-strength = <6>; 4974 bias-disable; 4975 }; 4976 4977 qup_spi6_cs: qup-spi6-cs-state { 4978 pins = "gpio51"; 4979 function = "qup1_se6"; 4980 drive-strength = <6>; 4981 bias-disable; 4982 }; 4983 4984 qup_spi6_data_clk: qup-spi6-data-clk-state { 4985 /* MISO, MOSI, CLK */ 4986 pins = "gpio48", "gpio49", "gpio50"; 4987 function = "qup1_se6"; 4988 drive-strength = <6>; 4989 bias-disable; 4990 }; 4991 4992 qup_spi8_cs: qup-spi8-cs-state { 4993 pins = "gpio59"; 4994 function = "qup2_se0_l3_mira"; 4995 drive-strength = <6>; 4996 bias-disable; 4997 }; 4998 4999 qup_spi8_data_clk: qup-spi8-data-clk-state { 5000 /* MISO, MOSI, CLK */ 5001 pins = "gpio56", "gpio57", "gpio58"; 5002 function = "qup2_se0_l2_mira"; 5003 drive-strength = <6>; 5004 bias-disable; 5005 }; 5006 5007 qup_spi9_cs: qup-spi9-cs-state { 5008 pins = "gpio63"; 5009 function = "qup2_se1"; 5010 drive-strength = <6>; 5011 bias-disable; 5012 }; 5013 5014 qup_spi9_data_clk: qup-spi9-data-clk-state { 5015 /* MISO, MOSI, CLK */ 5016 pins = "gpio60", "gpio61", "gpio62"; 5017 function = "qup2_se1"; 5018 drive-strength = <6>; 5019 bias-disable; 5020 }; 5021 5022 qup_spi10_cs: qup-spi10-cs-state { 5023 pins = "gpio67"; 5024 function = "qup2_se2"; 5025 drive-strength = <6>; 5026 bias-disable; 5027 }; 5028 5029 qup_spi10_data_clk: qup-spi10-data-clk-state { 5030 /* MISO, MOSI, CLK */ 5031 pins = "gpio64", "gpio65", "gpio66"; 5032 function = "qup2_se2"; 5033 drive-strength = <6>; 5034 bias-disable; 5035 }; 5036 5037 qup_spi11_cs: qup-spi11-cs-state { 5038 pins = "gpio71"; 5039 function = "qup2_se3"; 5040 drive-strength = <6>; 5041 bias-disable; 5042 }; 5043 5044 qup_spi11_data_clk: qup-spi11-data-clk-state { 5045 /* MISO, MOSI, CLK */ 5046 pins = "gpio68", "gpio69", "gpio70"; 5047 function = "qup2_se3"; 5048 drive-strength = <6>; 5049 bias-disable; 5050 }; 5051 5052 qup_spi12_cs: qup-spi12-cs-state { 5053 pins = "gpio119"; 5054 function = "qup2_se4"; 5055 drive-strength = <6>; 5056 bias-disable; 5057 }; 5058 5059 qup_spi12_data_clk: qup-spi12-data-clk-state { 5060 /* MISO, MOSI, CLK */ 5061 pins = "gpio2", "gpio3", "gpio118"; 5062 function = "qup2_se4"; 5063 drive-strength = <6>; 5064 bias-disable; 5065 }; 5066 5067 qup_spi13_cs: qup-spi13-cs-state { 5068 pins = "gpio83"; 5069 function = "qup2_se5"; 5070 drive-strength = <6>; 5071 bias-disable; 5072 }; 5073 5074 qup_spi13_data_clk: qup-spi13-data-clk-state { 5075 /* MISO, MOSI, CLK */ 5076 pins = "gpio80", "gpio81", "gpio82"; 5077 function = "qup2_se5"; 5078 drive-strength = <6>; 5079 bias-disable; 5080 }; 5081 5082 qup_spi15_cs: qup-spi15-cs-state { 5083 pins = "gpio75"; 5084 function = "qup2_se7"; 5085 drive-strength = <6>; 5086 bias-disable; 5087 }; 5088 5089 qup_spi15_data_clk: qup-spi15-data-clk-state { 5090 /* MISO, MOSI, CLK */ 5091 pins = "gpio72", "gpio106", "gpio74"; 5092 function = "qup2_se7"; 5093 drive-strength = <6>; 5094 bias-disable; 5095 }; 5096 5097 qup_uart7_default: qup-uart7-default-state { 5098 /* TX, RX */ 5099 pins = "gpio26", "gpio27"; 5100 function = "qup1_se7"; 5101 drive-strength = <2>; 5102 bias-disable; 5103 }; 5104 5105 qup_uart14_default: qup-uart14-default-state { 5106 /* TX, RX */ 5107 pins = "gpio78", "gpio79"; 5108 function = "qup2_se6"; 5109 drive-strength = <2>; 5110 bias-pull-up; 5111 }; 5112 5113 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 5114 /* CTS, RTS */ 5115 pins = "gpio76", "gpio77"; 5116 function = "qup2_se6"; 5117 drive-strength = <2>; 5118 bias-pull-down; 5119 }; 5120 5121 qup_uart15_default: qup-uart15-default-state { 5122 /* TX, RX */ 5123 pins = "gpio74", "gpio75"; 5124 function = "qup2_se7"; 5125 drive-strength = <2>; 5126 bias-pull-up; 5127 }; 5128 5129 sdc2_sleep: sdc2-sleep-state { 5130 clk-pins { 5131 pins = "sdc2_clk"; 5132 bias-disable; 5133 drive-strength = <2>; 5134 }; 5135 5136 cmd-pins { 5137 pins = "sdc2_cmd"; 5138 bias-pull-up; 5139 drive-strength = <2>; 5140 }; 5141 5142 data-pins { 5143 pins = "sdc2_data"; 5144 bias-pull-up; 5145 drive-strength = <2>; 5146 }; 5147 }; 5148 5149 sdc2_default: sdc2-default-state { 5150 clk-pins { 5151 pins = "sdc2_clk"; 5152 bias-disable; 5153 drive-strength = <16>; 5154 }; 5155 5156 cmd-pins { 5157 pins = "sdc2_cmd"; 5158 bias-pull-up; 5159 drive-strength = <10>; 5160 }; 5161 5162 data-pins { 5163 pins = "sdc2_data"; 5164 bias-pull-up; 5165 drive-strength = <10>; 5166 }; 5167 }; 5168 }; 5169 5170 sram@14680000 { 5171 compatible = "qcom,sm8550-imem", "syscon", "simple-mfd"; 5172 reg = <0 0x14680000 0 0x2c000>; 5173 5174 #address-cells = <1>; 5175 #size-cells = <1>; 5176 5177 ranges = <0 0 0x14680000 0x2c000>; 5178 5179 ipa_modem_tables: modem-tables@8000 { 5180 reg = <0x8000 0x2000>; 5181 }; 5182 }; 5183 5184 apps_smmu: iommu@15000000 { 5185 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5186 reg = <0 0x15000000 0 0x100000>; 5187 #iommu-cells = <2>; 5188 #global-interrupts = <1>; 5189 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, 5190 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, 5191 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, 5192 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, 5193 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, 5194 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 5195 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, 5196 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 5197 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 5198 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, 5199 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, 5200 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 5201 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 5202 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 5203 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, 5204 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, 5205 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, 5206 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, 5207 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 5208 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, 5209 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, 5210 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, 5211 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, 5212 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, 5213 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, 5214 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, 5215 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, 5216 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, 5217 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, 5218 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, 5219 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, 5220 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, 5221 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, 5222 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, 5223 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, 5224 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, 5225 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, 5226 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, 5227 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, 5228 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, 5229 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, 5230 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, 5231 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, 5232 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, 5233 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, 5234 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, 5235 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, 5236 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, 5237 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, 5238 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, 5239 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, 5240 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, 5241 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, 5242 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, 5243 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, 5244 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, 5245 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, 5246 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, 5247 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, 5248 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, 5249 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, 5250 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>, 5251 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>, 5252 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>, 5253 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>, 5254 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>, 5255 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>, 5256 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 5257 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 5258 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>, 5259 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>, 5260 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>, 5261 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>, 5262 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>, 5263 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>, 5264 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>, 5265 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>, 5266 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>, 5267 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, 5268 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, 5269 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, 5270 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, 5271 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, 5272 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>, 5273 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>, 5274 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>, 5275 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>, 5276 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>, 5277 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>, 5278 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>, 5279 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>, 5280 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>, 5281 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>, 5282 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>, 5283 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>, 5284 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>, 5285 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>; 5286 dma-coherent; 5287 }; 5288 5289 intc: interrupt-controller@17100000 { 5290 compatible = "arm,gic-v3"; 5291 reg = <0 0x17100000 0 0x10000>, /* GICD */ 5292 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 5293 ranges; 5294 #interrupt-cells = <4>; 5295 interrupt-controller; 5296 #redistributor-regions = <1>; 5297 redistributor-stride = <0 0x40000>; 5298 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>; 5299 #address-cells = <2>; 5300 #size-cells = <2>; 5301 5302 ppi-partitions { 5303 ppi_cluster0: interrupt-partition-0 { 5304 affinity = <&cpu0 &cpu1 &cpu2>; 5305 }; 5306 5307 ppi_cluster1: interrupt-partition-1 { 5308 affinity = <&cpu3 &cpu4>; 5309 }; 5310 5311 ppi_cluster2: interrupt-partition-2 { 5312 affinity = <&cpu5 &cpu6>; 5313 }; 5314 5315 ppi_cluster3: interrupt-partition-3 { 5316 affinity = <&cpu7>; 5317 }; 5318 }; 5319 5320 gic_its: msi-controller@17140000 { 5321 compatible = "arm,gic-v3-its"; 5322 reg = <0 0x17140000 0 0x40000>; 5323 msi-controller; 5324 #msi-cells = <1>; 5325 }; 5326 }; 5327 5328 timer@17420000 { 5329 compatible = "arm,armv7-timer-mem"; 5330 reg = <0 0x17420000 0 0x1000>; 5331 ranges = <0 0 0 0x20000000>; 5332 #address-cells = <1>; 5333 #size-cells = <1>; 5334 5335 frame@17421000 { 5336 reg = <0x17421000 0x1000>, 5337 <0x17422000 0x1000>; 5338 frame-number = <0>; 5339 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, 5340 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 5341 }; 5342 5343 frame@17423000 { 5344 reg = <0x17423000 0x1000>; 5345 frame-number = <1>; 5346 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 5347 status = "disabled"; 5348 }; 5349 5350 frame@17425000 { 5351 reg = <0x17425000 0x1000>; 5352 frame-number = <2>; 5353 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 5354 status = "disabled"; 5355 }; 5356 5357 frame@17427000 { 5358 reg = <0x17427000 0x1000>; 5359 frame-number = <3>; 5360 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 5361 status = "disabled"; 5362 }; 5363 5364 frame@17429000 { 5365 reg = <0x17429000 0x1000>; 5366 frame-number = <4>; 5367 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 5368 status = "disabled"; 5369 }; 5370 5371 frame@1742b000 { 5372 reg = <0x1742b000 0x1000>; 5373 frame-number = <5>; 5374 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; 5375 status = "disabled"; 5376 }; 5377 5378 frame@1742d000 { 5379 reg = <0x1742d000 0x1000>; 5380 frame-number = <6>; 5381 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 5382 status = "disabled"; 5383 }; 5384 }; 5385 5386 apps_rsc: rsc@17a00000 { 5387 label = "apps_rsc"; 5388 compatible = "qcom,rpmh-rsc"; 5389 reg = <0 0x17a00000 0 0x10000>, 5390 <0 0x17a10000 0 0x10000>, 5391 <0 0x17a20000 0 0x10000>, 5392 <0 0x17a30000 0 0x10000>; 5393 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 5394 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, 5395 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, 5396 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; 5397 qcom,tcs-offset = <0xd00>; 5398 qcom,drv-id = <2>; 5399 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 5400 <WAKE_TCS 2>, <CONTROL_TCS 0>; 5401 power-domains = <&cluster_pd>; 5402 5403 apps_bcm_voter: bcm-voter { 5404 compatible = "qcom,bcm-voter"; 5405 }; 5406 5407 rpmhcc: clock-controller { 5408 compatible = "qcom,sm8550-rpmh-clk"; 5409 #clock-cells = <1>; 5410 clock-names = "xo"; 5411 clocks = <&xo_board>; 5412 }; 5413 5414 rpmhpd: power-controller { 5415 compatible = "qcom,sm8550-rpmhpd"; 5416 #power-domain-cells = <1>; 5417 operating-points-v2 = <&rpmhpd_opp_table>; 5418 5419 rpmhpd_opp_table: opp-table { 5420 compatible = "operating-points-v2"; 5421 5422 rpmhpd_opp_ret: opp-16 { 5423 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5424 }; 5425 5426 rpmhpd_opp_min_svs: opp-48 { 5427 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5428 }; 5429 5430 rpmhpd_opp_low_svs_d2: opp-52 { 5431 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5432 }; 5433 5434 rpmhpd_opp_low_svs_d1: opp-56 { 5435 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5436 }; 5437 5438 rpmhpd_opp_low_svs_d0: opp-60 { 5439 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5440 }; 5441 5442 rpmhpd_opp_low_svs: opp-64 { 5443 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5444 }; 5445 5446 rpmhpd_opp_low_svs_l1: opp-80 { 5447 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5448 }; 5449 5450 rpmhpd_opp_svs: opp-128 { 5451 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5452 }; 5453 5454 rpmhpd_opp_svs_l0: opp-144 { 5455 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5456 }; 5457 5458 rpmhpd_opp_svs_l1: opp-192 { 5459 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5460 }; 5461 5462 rpmhpd_opp_nom: opp-256 { 5463 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5464 }; 5465 5466 rpmhpd_opp_nom_l1: opp-320 { 5467 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5468 }; 5469 5470 rpmhpd_opp_nom_l2: opp-336 { 5471 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5472 }; 5473 5474 rpmhpd_opp_turbo: opp-384 { 5475 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5476 }; 5477 5478 rpmhpd_opp_turbo_l1: opp-416 { 5479 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5480 }; 5481 }; 5482 }; 5483 }; 5484 5485 cpufreq_hw: cpufreq@17d91000 { 5486 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 5487 reg = <0 0x17d91000 0 0x1000>, 5488 <0 0x17d92000 0 0x1000>, 5489 <0 0x17d93000 0 0x1000>; 5490 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 5491 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 5492 clock-names = "xo", "alternate"; 5493 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, 5494 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>, 5495 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 5496 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5497 #freq-domain-cells = <1>; 5498 #clock-cells = <1>; 5499 }; 5500 5501 pmu@24091000 { 5502 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 5503 reg = <0 0x24091000 0 0x1000>; 5504 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 5505 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 5506 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5507 5508 operating-points-v2 = <&llcc_bwmon_opp_table>; 5509 5510 llcc_bwmon_opp_table: opp-table { 5511 compatible = "operating-points-v2"; 5512 5513 opp-0 { 5514 opp-peak-kBps = <2086000>; 5515 }; 5516 5517 opp-1 { 5518 opp-peak-kBps = <2929000>; 5519 }; 5520 5521 opp-2 { 5522 opp-peak-kBps = <5931000>; 5523 }; 5524 5525 opp-3 { 5526 opp-peak-kBps = <6515000>; 5527 }; 5528 5529 opp-4 { 5530 opp-peak-kBps = <7980000>; 5531 }; 5532 5533 opp-5 { 5534 opp-peak-kBps = <10437000>; 5535 }; 5536 5537 opp-6 { 5538 opp-peak-kBps = <12157000>; 5539 }; 5540 5541 opp-7 { 5542 opp-peak-kBps = <14060000>; 5543 }; 5544 5545 opp-8 { 5546 opp-peak-kBps = <16113000>; 5547 }; 5548 }; 5549 }; 5550 5551 pmu@240b6400 { 5552 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 5553 reg = <0 0x240b6400 0 0x600>; 5554 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>; 5555 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5556 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5557 5558 operating-points-v2 = <&cpu_bwmon_opp_table>; 5559 5560 cpu_bwmon_opp_table: opp-table { 5561 compatible = "operating-points-v2"; 5562 5563 opp-0 { 5564 opp-peak-kBps = <4577000>; 5565 }; 5566 5567 opp-1 { 5568 opp-peak-kBps = <7110000>; 5569 }; 5570 5571 opp-2 { 5572 opp-peak-kBps = <9155000>; 5573 }; 5574 5575 opp-3 { 5576 opp-peak-kBps = <12298000>; 5577 }; 5578 5579 opp-4 { 5580 opp-peak-kBps = <14236000>; 5581 }; 5582 5583 opp-5 { 5584 opp-peak-kBps = <16265000>; 5585 }; 5586 }; 5587 }; 5588 5589 gem_noc: interconnect@24100000 { 5590 compatible = "qcom,sm8550-gem-noc"; 5591 reg = <0 0x24100000 0 0xbb800>; 5592 #interconnect-cells = <2>; 5593 qcom,bcm-voters = <&apps_bcm_voter>; 5594 }; 5595 5596 system-cache-controller@25000000 { 5597 compatible = "qcom,sm8550-llcc"; 5598 reg = <0 0x25000000 0 0x200000>, 5599 <0 0x25200000 0 0x200000>, 5600 <0 0x25400000 0 0x200000>, 5601 <0 0x25600000 0 0x200000>, 5602 <0 0x25800000 0 0x200000>, 5603 <0 0x25a00000 0 0x200000>; 5604 reg-names = "llcc0_base", 5605 "llcc1_base", 5606 "llcc2_base", 5607 "llcc3_base", 5608 "llcc_broadcast_base", 5609 "llcc_broadcast_and_base"; 5610 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH 0>; 5611 }; 5612 5613 nsp_noc: interconnect@320c0000 { 5614 compatible = "qcom,sm8550-nsp-noc"; 5615 reg = <0 0x320c0000 0 0xe080>; 5616 #interconnect-cells = <2>; 5617 qcom,bcm-voters = <&apps_bcm_voter>; 5618 }; 5619 5620 remoteproc_cdsp: remoteproc@32300000 { 5621 compatible = "qcom,sm8550-cdsp-pas"; 5622 reg = <0x0 0x32300000 0x0 0x10000>; 5623 5624 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, 5625 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 5626 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 5627 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 5628 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 5629 interrupt-names = "wdog", "fatal", "ready", 5630 "handover", "stop-ack"; 5631 5632 clocks = <&rpmhcc RPMH_CXO_CLK>; 5633 clock-names = "xo"; 5634 5635 power-domains = <&rpmhpd RPMHPD_CX>, 5636 <&rpmhpd RPMHPD_MXC>, 5637 <&rpmhpd RPMHPD_NSP>; 5638 power-domain-names = "cx", "mxc", "nsp"; 5639 5640 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 5641 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5642 5643 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 5644 5645 qcom,qmp = <&aoss_qmp>; 5646 5647 qcom,smem-states = <&smp2p_cdsp_out 0>; 5648 qcom,smem-state-names = "stop"; 5649 5650 status = "disabled"; 5651 5652 glink-edge { 5653 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5654 IPCC_MPROC_SIGNAL_GLINK_QMP 5655 IRQ_TYPE_EDGE_RISING>; 5656 mboxes = <&ipcc IPCC_CLIENT_CDSP 5657 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5658 5659 label = "cdsp"; 5660 qcom,remote-pid = <5>; 5661 5662 fastrpc { 5663 compatible = "qcom,fastrpc"; 5664 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5665 label = "cdsp"; 5666 qcom,non-secure-domain; 5667 #address-cells = <1>; 5668 #size-cells = <0>; 5669 5670 compute-cb@1 { 5671 compatible = "qcom,fastrpc-compute-cb"; 5672 reg = <1>; 5673 iommus = <&apps_smmu 0x1961 0x0>, 5674 <&apps_smmu 0x0c01 0x20>, 5675 <&apps_smmu 0x19c1 0x10>; 5676 dma-coherent; 5677 }; 5678 5679 compute-cb@2 { 5680 compatible = "qcom,fastrpc-compute-cb"; 5681 reg = <2>; 5682 iommus = <&apps_smmu 0x1962 0x0>, 5683 <&apps_smmu 0x0c02 0x20>, 5684 <&apps_smmu 0x19c2 0x10>; 5685 dma-coherent; 5686 }; 5687 5688 compute-cb@3 { 5689 compatible = "qcom,fastrpc-compute-cb"; 5690 reg = <3>; 5691 iommus = <&apps_smmu 0x1963 0x0>, 5692 <&apps_smmu 0x0c03 0x20>, 5693 <&apps_smmu 0x19c3 0x10>; 5694 dma-coherent; 5695 }; 5696 5697 compute-cb@4 { 5698 compatible = "qcom,fastrpc-compute-cb"; 5699 reg = <4>; 5700 iommus = <&apps_smmu 0x1964 0x0>, 5701 <&apps_smmu 0x0c04 0x20>, 5702 <&apps_smmu 0x19c4 0x10>; 5703 dma-coherent; 5704 }; 5705 5706 compute-cb@5 { 5707 compatible = "qcom,fastrpc-compute-cb"; 5708 reg = <5>; 5709 iommus = <&apps_smmu 0x1965 0x0>, 5710 <&apps_smmu 0x0c05 0x20>, 5711 <&apps_smmu 0x19c5 0x10>; 5712 dma-coherent; 5713 }; 5714 5715 compute-cb@6 { 5716 compatible = "qcom,fastrpc-compute-cb"; 5717 reg = <6>; 5718 iommus = <&apps_smmu 0x1966 0x0>, 5719 <&apps_smmu 0x0c06 0x20>, 5720 <&apps_smmu 0x19c6 0x10>; 5721 dma-coherent; 5722 }; 5723 5724 compute-cb@7 { 5725 compatible = "qcom,fastrpc-compute-cb"; 5726 reg = <7>; 5727 iommus = <&apps_smmu 0x1967 0x0>, 5728 <&apps_smmu 0x0c07 0x20>, 5729 <&apps_smmu 0x19c7 0x10>; 5730 dma-coherent; 5731 }; 5732 5733 compute-cb@8 { 5734 compatible = "qcom,fastrpc-compute-cb"; 5735 reg = <8>; 5736 iommus = <&apps_smmu 0x1968 0x0>, 5737 <&apps_smmu 0x0c08 0x20>, 5738 <&apps_smmu 0x19c8 0x10>; 5739 dma-coherent; 5740 }; 5741 5742 /* note: secure cb9 in downstream */ 5743 }; 5744 }; 5745 }; 5746 }; 5747 5748 thermal-zones { 5749 aoss0-thermal { 5750 thermal-sensors = <&tsens0 0>; 5751 5752 trips { 5753 thermal-engine-config { 5754 temperature = <125000>; 5755 hysteresis = <1000>; 5756 type = "passive"; 5757 }; 5758 5759 reset-mon-config { 5760 temperature = <115000>; 5761 hysteresis = <5000>; 5762 type = "passive"; 5763 }; 5764 }; 5765 }; 5766 5767 cpuss0-thermal { 5768 thermal-sensors = <&tsens0 1>; 5769 5770 trips { 5771 thermal-engine-config { 5772 temperature = <125000>; 5773 hysteresis = <1000>; 5774 type = "passive"; 5775 }; 5776 5777 reset-mon-config { 5778 temperature = <115000>; 5779 hysteresis = <5000>; 5780 type = "passive"; 5781 }; 5782 }; 5783 }; 5784 5785 cpuss1-thermal { 5786 thermal-sensors = <&tsens0 2>; 5787 5788 trips { 5789 thermal-engine-config { 5790 temperature = <125000>; 5791 hysteresis = <1000>; 5792 type = "passive"; 5793 }; 5794 5795 reset-mon-config { 5796 temperature = <115000>; 5797 hysteresis = <5000>; 5798 type = "passive"; 5799 }; 5800 }; 5801 }; 5802 5803 cpuss2-thermal { 5804 thermal-sensors = <&tsens0 3>; 5805 5806 trips { 5807 thermal-engine-config { 5808 temperature = <125000>; 5809 hysteresis = <1000>; 5810 type = "passive"; 5811 }; 5812 5813 reset-mon-config { 5814 temperature = <115000>; 5815 hysteresis = <5000>; 5816 type = "passive"; 5817 }; 5818 }; 5819 }; 5820 5821 cpuss3-thermal { 5822 thermal-sensors = <&tsens0 4>; 5823 5824 trips { 5825 thermal-engine-config { 5826 temperature = <125000>; 5827 hysteresis = <1000>; 5828 type = "passive"; 5829 }; 5830 5831 reset-mon-config { 5832 temperature = <115000>; 5833 hysteresis = <5000>; 5834 type = "passive"; 5835 }; 5836 }; 5837 }; 5838 5839 cpu3-top-thermal { 5840 thermal-sensors = <&tsens0 5>; 5841 5842 trips { 5843 cpu3_top_alert0: trip-point0 { 5844 temperature = <90000>; 5845 hysteresis = <2000>; 5846 type = "passive"; 5847 }; 5848 5849 cpu3_top_alert1: trip-point1 { 5850 temperature = <95000>; 5851 hysteresis = <2000>; 5852 type = "passive"; 5853 }; 5854 5855 cpu3_top_crit: cpu-critical { 5856 temperature = <110000>; 5857 hysteresis = <1000>; 5858 type = "critical"; 5859 }; 5860 }; 5861 }; 5862 5863 cpu3-bottom-thermal { 5864 thermal-sensors = <&tsens0 6>; 5865 5866 trips { 5867 cpu3_bottom_alert0: trip-point0 { 5868 temperature = <90000>; 5869 hysteresis = <2000>; 5870 type = "passive"; 5871 }; 5872 5873 cpu3_bottom_alert1: trip-point1 { 5874 temperature = <95000>; 5875 hysteresis = <2000>; 5876 type = "passive"; 5877 }; 5878 5879 cpu3_bottom_crit: cpu-critical { 5880 temperature = <110000>; 5881 hysteresis = <1000>; 5882 type = "critical"; 5883 }; 5884 }; 5885 }; 5886 5887 cpu4-top-thermal { 5888 thermal-sensors = <&tsens0 7>; 5889 5890 trips { 5891 cpu4_top_alert0: trip-point0 { 5892 temperature = <90000>; 5893 hysteresis = <2000>; 5894 type = "passive"; 5895 }; 5896 5897 cpu4_top_alert1: trip-point1 { 5898 temperature = <95000>; 5899 hysteresis = <2000>; 5900 type = "passive"; 5901 }; 5902 5903 cpu4_top_crit: cpu-critical { 5904 temperature = <110000>; 5905 hysteresis = <1000>; 5906 type = "critical"; 5907 }; 5908 }; 5909 }; 5910 5911 cpu4-bottom-thermal { 5912 thermal-sensors = <&tsens0 8>; 5913 5914 trips { 5915 cpu4_bottom_alert0: trip-point0 { 5916 temperature = <90000>; 5917 hysteresis = <2000>; 5918 type = "passive"; 5919 }; 5920 5921 cpu4_bottom_alert1: trip-point1 { 5922 temperature = <95000>; 5923 hysteresis = <2000>; 5924 type = "passive"; 5925 }; 5926 5927 cpu4_bottom_crit: cpu-critical { 5928 temperature = <110000>; 5929 hysteresis = <1000>; 5930 type = "critical"; 5931 }; 5932 }; 5933 }; 5934 5935 cpu5-top-thermal { 5936 thermal-sensors = <&tsens0 9>; 5937 5938 trips { 5939 cpu5_top_alert0: trip-point0 { 5940 temperature = <90000>; 5941 hysteresis = <2000>; 5942 type = "passive"; 5943 }; 5944 5945 cpu5_top_alert1: trip-point1 { 5946 temperature = <95000>; 5947 hysteresis = <2000>; 5948 type = "passive"; 5949 }; 5950 5951 cpu5_top_crit: cpu-critical { 5952 temperature = <110000>; 5953 hysteresis = <1000>; 5954 type = "critical"; 5955 }; 5956 }; 5957 }; 5958 5959 cpu5-bottom-thermal { 5960 thermal-sensors = <&tsens0 10>; 5961 5962 trips { 5963 cpu5_bottom_alert0: trip-point0 { 5964 temperature = <90000>; 5965 hysteresis = <2000>; 5966 type = "passive"; 5967 }; 5968 5969 cpu5_bottom_alert1: trip-point1 { 5970 temperature = <95000>; 5971 hysteresis = <2000>; 5972 type = "passive"; 5973 }; 5974 5975 cpu5_bottom_crit: cpu-critical { 5976 temperature = <110000>; 5977 hysteresis = <1000>; 5978 type = "critical"; 5979 }; 5980 }; 5981 }; 5982 5983 cpu6-top-thermal { 5984 thermal-sensors = <&tsens0 11>; 5985 5986 trips { 5987 cpu6_top_alert0: trip-point0 { 5988 temperature = <90000>; 5989 hysteresis = <2000>; 5990 type = "passive"; 5991 }; 5992 5993 cpu6_top_alert1: trip-point1 { 5994 temperature = <95000>; 5995 hysteresis = <2000>; 5996 type = "passive"; 5997 }; 5998 5999 cpu6_top_crit: cpu-critical { 6000 temperature = <110000>; 6001 hysteresis = <1000>; 6002 type = "critical"; 6003 }; 6004 }; 6005 }; 6006 6007 cpu6-bottom-thermal { 6008 thermal-sensors = <&tsens0 12>; 6009 6010 trips { 6011 cpu6_bottom_alert0: trip-point0 { 6012 temperature = <90000>; 6013 hysteresis = <2000>; 6014 type = "passive"; 6015 }; 6016 6017 cpu6_bottom_alert1: trip-point1 { 6018 temperature = <95000>; 6019 hysteresis = <2000>; 6020 type = "passive"; 6021 }; 6022 6023 cpu6_bottom_crit: cpu-critical { 6024 temperature = <110000>; 6025 hysteresis = <1000>; 6026 type = "critical"; 6027 }; 6028 }; 6029 }; 6030 6031 cpu7-top-thermal { 6032 thermal-sensors = <&tsens0 13>; 6033 6034 trips { 6035 cpu7_top_alert0: trip-point0 { 6036 temperature = <90000>; 6037 hysteresis = <2000>; 6038 type = "passive"; 6039 }; 6040 6041 cpu7_top_alert1: trip-point1 { 6042 temperature = <95000>; 6043 hysteresis = <2000>; 6044 type = "passive"; 6045 }; 6046 6047 cpu7_top_crit: cpu-critical { 6048 temperature = <110000>; 6049 hysteresis = <1000>; 6050 type = "critical"; 6051 }; 6052 }; 6053 }; 6054 6055 cpu7-middle-thermal { 6056 thermal-sensors = <&tsens0 14>; 6057 6058 trips { 6059 cpu7_middle_alert0: trip-point0 { 6060 temperature = <90000>; 6061 hysteresis = <2000>; 6062 type = "passive"; 6063 }; 6064 6065 cpu7_middle_alert1: trip-point1 { 6066 temperature = <95000>; 6067 hysteresis = <2000>; 6068 type = "passive"; 6069 }; 6070 6071 cpu7_middle_crit: cpu-critical { 6072 temperature = <110000>; 6073 hysteresis = <1000>; 6074 type = "critical"; 6075 }; 6076 }; 6077 }; 6078 6079 cpu7-bottom-thermal { 6080 thermal-sensors = <&tsens0 15>; 6081 6082 trips { 6083 cpu7_bottom_alert0: trip-point0 { 6084 temperature = <90000>; 6085 hysteresis = <2000>; 6086 type = "passive"; 6087 }; 6088 6089 cpu7_bottom_alert1: trip-point1 { 6090 temperature = <95000>; 6091 hysteresis = <2000>; 6092 type = "passive"; 6093 }; 6094 6095 cpu7_bottom_crit: cpu-critical { 6096 temperature = <110000>; 6097 hysteresis = <1000>; 6098 type = "critical"; 6099 }; 6100 }; 6101 }; 6102 6103 aoss1-thermal { 6104 thermal-sensors = <&tsens1 0>; 6105 6106 trips { 6107 thermal-engine-config { 6108 temperature = <125000>; 6109 hysteresis = <1000>; 6110 type = "passive"; 6111 }; 6112 6113 reset-mon-config { 6114 temperature = <115000>; 6115 hysteresis = <5000>; 6116 type = "passive"; 6117 }; 6118 }; 6119 }; 6120 6121 cpu0-thermal { 6122 thermal-sensors = <&tsens1 1>; 6123 6124 trips { 6125 cpu0_alert0: trip-point0 { 6126 temperature = <90000>; 6127 hysteresis = <2000>; 6128 type = "passive"; 6129 }; 6130 6131 cpu0_alert1: trip-point1 { 6132 temperature = <95000>; 6133 hysteresis = <2000>; 6134 type = "passive"; 6135 }; 6136 6137 cpu0_crit: cpu-critical { 6138 temperature = <110000>; 6139 hysteresis = <1000>; 6140 type = "critical"; 6141 }; 6142 }; 6143 }; 6144 6145 cpu1-thermal { 6146 thermal-sensors = <&tsens1 2>; 6147 6148 trips { 6149 cpu1_alert0: trip-point0 { 6150 temperature = <90000>; 6151 hysteresis = <2000>; 6152 type = "passive"; 6153 }; 6154 6155 cpu1_alert1: trip-point1 { 6156 temperature = <95000>; 6157 hysteresis = <2000>; 6158 type = "passive"; 6159 }; 6160 6161 cpu1_crit: cpu-critical { 6162 temperature = <110000>; 6163 hysteresis = <1000>; 6164 type = "critical"; 6165 }; 6166 }; 6167 }; 6168 6169 cpu2-thermal { 6170 thermal-sensors = <&tsens1 3>; 6171 6172 trips { 6173 cpu2_alert0: trip-point0 { 6174 temperature = <90000>; 6175 hysteresis = <2000>; 6176 type = "passive"; 6177 }; 6178 6179 cpu2_alert1: trip-point1 { 6180 temperature = <95000>; 6181 hysteresis = <2000>; 6182 type = "passive"; 6183 }; 6184 6185 cpu2_crit: cpu-critical { 6186 temperature = <110000>; 6187 hysteresis = <1000>; 6188 type = "critical"; 6189 }; 6190 }; 6191 }; 6192 6193 cdsp0-thermal { 6194 polling-delay-passive = <10>; 6195 6196 thermal-sensors = <&tsens2 4>; 6197 6198 trips { 6199 thermal-engine-config { 6200 temperature = <125000>; 6201 hysteresis = <1000>; 6202 type = "passive"; 6203 }; 6204 6205 thermal-hal-config { 6206 temperature = <125000>; 6207 hysteresis = <1000>; 6208 type = "passive"; 6209 }; 6210 6211 reset-mon-config { 6212 temperature = <115000>; 6213 hysteresis = <5000>; 6214 type = "passive"; 6215 }; 6216 6217 cdsp0_junction_config: junction-config { 6218 temperature = <95000>; 6219 hysteresis = <5000>; 6220 type = "passive"; 6221 }; 6222 }; 6223 }; 6224 6225 cdsp1-thermal { 6226 polling-delay-passive = <10>; 6227 6228 thermal-sensors = <&tsens2 5>; 6229 6230 trips { 6231 thermal-engine-config { 6232 temperature = <125000>; 6233 hysteresis = <1000>; 6234 type = "passive"; 6235 }; 6236 6237 thermal-hal-config { 6238 temperature = <125000>; 6239 hysteresis = <1000>; 6240 type = "passive"; 6241 }; 6242 6243 reset-mon-config { 6244 temperature = <115000>; 6245 hysteresis = <5000>; 6246 type = "passive"; 6247 }; 6248 6249 cdsp1_junction_config: junction-config { 6250 temperature = <95000>; 6251 hysteresis = <5000>; 6252 type = "passive"; 6253 }; 6254 }; 6255 }; 6256 6257 cdsp2-thermal { 6258 polling-delay-passive = <10>; 6259 6260 thermal-sensors = <&tsens2 6>; 6261 6262 trips { 6263 thermal-engine-config { 6264 temperature = <125000>; 6265 hysteresis = <1000>; 6266 type = "passive"; 6267 }; 6268 6269 thermal-hal-config { 6270 temperature = <125000>; 6271 hysteresis = <1000>; 6272 type = "passive"; 6273 }; 6274 6275 reset-mon-config { 6276 temperature = <115000>; 6277 hysteresis = <5000>; 6278 type = "passive"; 6279 }; 6280 6281 cdsp2_junction_config: junction-config { 6282 temperature = <95000>; 6283 hysteresis = <5000>; 6284 type = "passive"; 6285 }; 6286 }; 6287 }; 6288 6289 cdsp3-thermal { 6290 polling-delay-passive = <10>; 6291 6292 thermal-sensors = <&tsens2 7>; 6293 6294 trips { 6295 thermal-engine-config { 6296 temperature = <125000>; 6297 hysteresis = <1000>; 6298 type = "passive"; 6299 }; 6300 6301 thermal-hal-config { 6302 temperature = <125000>; 6303 hysteresis = <1000>; 6304 type = "passive"; 6305 }; 6306 6307 reset-mon-config { 6308 temperature = <115000>; 6309 hysteresis = <5000>; 6310 type = "passive"; 6311 }; 6312 6313 cdsp3_junction_config: junction-config { 6314 temperature = <95000>; 6315 hysteresis = <5000>; 6316 type = "passive"; 6317 }; 6318 }; 6319 }; 6320 6321 video-thermal { 6322 thermal-sensors = <&tsens1 8>; 6323 6324 trips { 6325 thermal-engine-config { 6326 temperature = <125000>; 6327 hysteresis = <1000>; 6328 type = "passive"; 6329 }; 6330 6331 reset-mon-config { 6332 temperature = <115000>; 6333 hysteresis = <5000>; 6334 type = "passive"; 6335 }; 6336 }; 6337 }; 6338 6339 mem-thermal { 6340 polling-delay-passive = <10>; 6341 6342 thermal-sensors = <&tsens1 9>; 6343 6344 trips { 6345 thermal-engine-config { 6346 temperature = <125000>; 6347 hysteresis = <1000>; 6348 type = "passive"; 6349 }; 6350 6351 ddr_config0: ddr0-config { 6352 temperature = <90000>; 6353 hysteresis = <5000>; 6354 type = "passive"; 6355 }; 6356 6357 reset-mon-config { 6358 temperature = <115000>; 6359 hysteresis = <5000>; 6360 type = "passive"; 6361 }; 6362 }; 6363 }; 6364 6365 modem0-thermal { 6366 thermal-sensors = <&tsens1 10>; 6367 6368 trips { 6369 thermal-engine-config { 6370 temperature = <125000>; 6371 hysteresis = <1000>; 6372 type = "passive"; 6373 }; 6374 6375 mdmss0_config0: mdmss0-config0 { 6376 temperature = <102000>; 6377 hysteresis = <3000>; 6378 type = "passive"; 6379 }; 6380 6381 mdmss0_config1: mdmss0-config1 { 6382 temperature = <105000>; 6383 hysteresis = <3000>; 6384 type = "passive"; 6385 }; 6386 6387 reset-mon-config { 6388 temperature = <115000>; 6389 hysteresis = <5000>; 6390 type = "passive"; 6391 }; 6392 }; 6393 }; 6394 6395 modem1-thermal { 6396 thermal-sensors = <&tsens1 11>; 6397 6398 trips { 6399 thermal-engine-config { 6400 temperature = <125000>; 6401 hysteresis = <1000>; 6402 type = "passive"; 6403 }; 6404 6405 mdmss1_config0: mdmss1-config0 { 6406 temperature = <102000>; 6407 hysteresis = <3000>; 6408 type = "passive"; 6409 }; 6410 6411 mdmss1_config1: mdmss1-config1 { 6412 temperature = <105000>; 6413 hysteresis = <3000>; 6414 type = "passive"; 6415 }; 6416 6417 reset-mon-config { 6418 temperature = <115000>; 6419 hysteresis = <5000>; 6420 type = "passive"; 6421 }; 6422 }; 6423 }; 6424 6425 modem2-thermal { 6426 thermal-sensors = <&tsens1 12>; 6427 6428 trips { 6429 thermal-engine-config { 6430 temperature = <125000>; 6431 hysteresis = <1000>; 6432 type = "passive"; 6433 }; 6434 6435 mdmss2_config0: mdmss2-config0 { 6436 temperature = <102000>; 6437 hysteresis = <3000>; 6438 type = "passive"; 6439 }; 6440 6441 mdmss2_config1: mdmss2-config1 { 6442 temperature = <105000>; 6443 hysteresis = <3000>; 6444 type = "passive"; 6445 }; 6446 6447 reset-mon-config { 6448 temperature = <115000>; 6449 hysteresis = <5000>; 6450 type = "passive"; 6451 }; 6452 }; 6453 }; 6454 6455 modem3-thermal { 6456 thermal-sensors = <&tsens1 13>; 6457 6458 trips { 6459 thermal-engine-config { 6460 temperature = <125000>; 6461 hysteresis = <1000>; 6462 type = "passive"; 6463 }; 6464 6465 mdmss3_config0: mdmss3-config0 { 6466 temperature = <102000>; 6467 hysteresis = <3000>; 6468 type = "passive"; 6469 }; 6470 6471 mdmss3_config1: mdmss3-config1 { 6472 temperature = <105000>; 6473 hysteresis = <3000>; 6474 type = "passive"; 6475 }; 6476 6477 reset-mon-config { 6478 temperature = <115000>; 6479 hysteresis = <5000>; 6480 type = "passive"; 6481 }; 6482 }; 6483 }; 6484 6485 camera0-thermal { 6486 thermal-sensors = <&tsens1 14>; 6487 6488 trips { 6489 thermal-engine-config { 6490 temperature = <125000>; 6491 hysteresis = <1000>; 6492 type = "passive"; 6493 }; 6494 6495 reset-mon-config { 6496 temperature = <115000>; 6497 hysteresis = <5000>; 6498 type = "passive"; 6499 }; 6500 }; 6501 }; 6502 6503 camera1-thermal { 6504 thermal-sensors = <&tsens1 15>; 6505 6506 trips { 6507 thermal-engine-config { 6508 temperature = <125000>; 6509 hysteresis = <1000>; 6510 type = "passive"; 6511 }; 6512 6513 reset-mon-config { 6514 temperature = <115000>; 6515 hysteresis = <5000>; 6516 type = "passive"; 6517 }; 6518 }; 6519 }; 6520 6521 aoss2-thermal { 6522 thermal-sensors = <&tsens2 0>; 6523 6524 trips { 6525 thermal-engine-config { 6526 temperature = <125000>; 6527 hysteresis = <1000>; 6528 type = "passive"; 6529 }; 6530 6531 reset-mon-config { 6532 temperature = <115000>; 6533 hysteresis = <5000>; 6534 type = "passive"; 6535 }; 6536 }; 6537 }; 6538 6539 gpuss-0-thermal { 6540 polling-delay-passive = <10>; 6541 6542 thermal-sensors = <&tsens2 1>; 6543 6544 cooling-maps { 6545 map0 { 6546 trip = <&gpu0_alert0>; 6547 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6548 }; 6549 }; 6550 6551 trips { 6552 gpu0_alert0: trip-point0 { 6553 temperature = <85000>; 6554 hysteresis = <1000>; 6555 type = "passive"; 6556 }; 6557 6558 trip-point1 { 6559 temperature = <90000>; 6560 hysteresis = <1000>; 6561 type = "hot"; 6562 }; 6563 6564 trip-point2 { 6565 temperature = <110000>; 6566 hysteresis = <1000>; 6567 type = "critical"; 6568 }; 6569 }; 6570 }; 6571 6572 gpuss-1-thermal { 6573 polling-delay-passive = <10>; 6574 6575 thermal-sensors = <&tsens2 2>; 6576 6577 cooling-maps { 6578 map0 { 6579 trip = <&gpu1_alert0>; 6580 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6581 }; 6582 }; 6583 6584 trips { 6585 gpu1_alert0: trip-point0 { 6586 temperature = <85000>; 6587 hysteresis = <1000>; 6588 type = "passive"; 6589 }; 6590 6591 trip-point1 { 6592 temperature = <90000>; 6593 hysteresis = <1000>; 6594 type = "hot"; 6595 }; 6596 6597 trip-point2 { 6598 temperature = <110000>; 6599 hysteresis = <1000>; 6600 type = "critical"; 6601 }; 6602 }; 6603 }; 6604 6605 gpuss-2-thermal { 6606 polling-delay-passive = <10>; 6607 6608 thermal-sensors = <&tsens2 3>; 6609 6610 cooling-maps { 6611 map0 { 6612 trip = <&gpu2_alert0>; 6613 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6614 }; 6615 }; 6616 6617 trips { 6618 gpu2_alert0: trip-point0 { 6619 temperature = <85000>; 6620 hysteresis = <1000>; 6621 type = "passive"; 6622 }; 6623 6624 trip-point1 { 6625 temperature = <90000>; 6626 hysteresis = <1000>; 6627 type = "hot"; 6628 }; 6629 6630 trip-point2 { 6631 temperature = <110000>; 6632 hysteresis = <1000>; 6633 type = "critical"; 6634 }; 6635 }; 6636 }; 6637 6638 gpuss-3-thermal { 6639 polling-delay-passive = <10>; 6640 6641 thermal-sensors = <&tsens2 4>; 6642 6643 cooling-maps { 6644 map0 { 6645 trip = <&gpu3_alert0>; 6646 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6647 }; 6648 }; 6649 6650 trips { 6651 gpu3_alert0: trip-point0 { 6652 temperature = <85000>; 6653 hysteresis = <1000>; 6654 type = "passive"; 6655 }; 6656 6657 trip-point1 { 6658 temperature = <90000>; 6659 hysteresis = <1000>; 6660 type = "hot"; 6661 }; 6662 6663 trip-point2 { 6664 temperature = <110000>; 6665 hysteresis = <1000>; 6666 type = "critical"; 6667 }; 6668 }; 6669 }; 6670 6671 gpuss-4-thermal { 6672 polling-delay-passive = <10>; 6673 6674 thermal-sensors = <&tsens2 5>; 6675 6676 cooling-maps { 6677 map0 { 6678 trip = <&gpu4_alert0>; 6679 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6680 }; 6681 }; 6682 6683 trips { 6684 gpu4_alert0: trip-point0 { 6685 temperature = <85000>; 6686 hysteresis = <1000>; 6687 type = "passive"; 6688 }; 6689 6690 trip-point1 { 6691 temperature = <90000>; 6692 hysteresis = <1000>; 6693 type = "hot"; 6694 }; 6695 6696 trip-point2 { 6697 temperature = <110000>; 6698 hysteresis = <1000>; 6699 type = "critical"; 6700 }; 6701 }; 6702 }; 6703 6704 gpuss-5-thermal { 6705 polling-delay-passive = <10>; 6706 6707 thermal-sensors = <&tsens2 6>; 6708 6709 cooling-maps { 6710 map0 { 6711 trip = <&gpu5_alert0>; 6712 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6713 }; 6714 }; 6715 6716 trips { 6717 gpu5_alert0: trip-point0 { 6718 temperature = <85000>; 6719 hysteresis = <1000>; 6720 type = "passive"; 6721 }; 6722 6723 trip-point1 { 6724 temperature = <90000>; 6725 hysteresis = <1000>; 6726 type = "hot"; 6727 }; 6728 6729 trip-point2 { 6730 temperature = <110000>; 6731 hysteresis = <1000>; 6732 type = "critical"; 6733 }; 6734 }; 6735 }; 6736 6737 gpuss-6-thermal { 6738 polling-delay-passive = <10>; 6739 6740 thermal-sensors = <&tsens2 7>; 6741 6742 cooling-maps { 6743 map0 { 6744 trip = <&gpu6_alert0>; 6745 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6746 }; 6747 }; 6748 6749 trips { 6750 gpu6_alert0: trip-point0 { 6751 temperature = <85000>; 6752 hysteresis = <1000>; 6753 type = "passive"; 6754 }; 6755 6756 trip-point1 { 6757 temperature = <90000>; 6758 hysteresis = <1000>; 6759 type = "hot"; 6760 }; 6761 6762 trip-point2 { 6763 temperature = <110000>; 6764 hysteresis = <1000>; 6765 type = "critical"; 6766 }; 6767 }; 6768 }; 6769 6770 gpuss-7-thermal { 6771 polling-delay-passive = <10>; 6772 6773 thermal-sensors = <&tsens2 8>; 6774 6775 cooling-maps { 6776 map0 { 6777 trip = <&gpu7_alert0>; 6778 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6779 }; 6780 }; 6781 6782 trips { 6783 gpu7_alert0: trip-point0 { 6784 temperature = <85000>; 6785 hysteresis = <1000>; 6786 type = "passive"; 6787 }; 6788 6789 trip-point1 { 6790 temperature = <90000>; 6791 hysteresis = <1000>; 6792 type = "hot"; 6793 }; 6794 6795 trip-point2 { 6796 temperature = <110000>; 6797 hysteresis = <1000>; 6798 type = "critical"; 6799 }; 6800 }; 6801 }; 6802 }; 6803 6804 timer { 6805 compatible = "arm,armv8-timer"; 6806 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 6807 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 6808 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 6809 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 6810 }; 6811}; 6812