1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sm8450-videocc.h> 9#include <dt-bindings/clock/qcom,sm8550-camcc.h> 10#include <dt-bindings/clock/qcom,sm8550-gcc.h> 11#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 12#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 13#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 14#include <dt-bindings/dma/qcom-gpi.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/interconnect/qcom,icc.h> 19#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/power/qcom,rpmhpd.h> 23#include <dt-bindings/soc/qcom,gpr.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 26#include <dt-bindings/phy/phy-qcom-qmp.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 chosen { }; 36 37 clocks { 38 xo_board: xo-board { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 }; 47 48 bi_tcxo_div2: bi-tcxo-div2-clk { 49 #clock-cells = <0>; 50 compatible = "fixed-factor-clock"; 51 clocks = <&rpmhcc RPMH_CXO_CLK>; 52 clock-mult = <1>; 53 clock-div = <2>; 54 }; 55 56 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 57 #clock-cells = <0>; 58 compatible = "fixed-factor-clock"; 59 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 60 clock-mult = <1>; 61 clock-div = <2>; 62 }; 63 }; 64 65 cpus { 66 #address-cells = <2>; 67 #size-cells = <0>; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a510"; 72 reg = <0 0>; 73 clocks = <&cpufreq_hw 0>; 74 enable-method = "psci"; 75 next-level-cache = <&l2_0>; 76 power-domains = <&cpu_pd0>; 77 power-domain-names = "psci"; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 capacity-dmips-mhz = <1024>; 80 dynamic-power-coefficient = <100>; 81 #cooling-cells = <2>; 82 l2_0: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 cache-unified; 86 next-level-cache = <&l3_0>; 87 l3_0: l3-cache { 88 compatible = "cache"; 89 cache-level = <3>; 90 cache-unified; 91 }; 92 }; 93 }; 94 95 cpu1: cpu@100 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a510"; 98 reg = <0 0x100>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 next-level-cache = <&l2_100>; 102 power-domains = <&cpu_pd1>; 103 power-domain-names = "psci"; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 capacity-dmips-mhz = <1024>; 106 dynamic-power-coefficient = <100>; 107 #cooling-cells = <2>; 108 l2_100: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&l3_0>; 113 }; 114 }; 115 116 cpu2: cpu@200 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a510"; 119 reg = <0 0x200>; 120 clocks = <&cpufreq_hw 0>; 121 enable-method = "psci"; 122 next-level-cache = <&l2_200>; 123 power-domains = <&cpu_pd2>; 124 power-domain-names = "psci"; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 capacity-dmips-mhz = <1024>; 127 dynamic-power-coefficient = <100>; 128 #cooling-cells = <2>; 129 l2_200: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 next-level-cache = <&l3_0>; 134 }; 135 }; 136 137 cpu3: cpu@300 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a715"; 140 reg = <0 0x300>; 141 clocks = <&cpufreq_hw 1>; 142 enable-method = "psci"; 143 next-level-cache = <&l2_300>; 144 power-domains = <&cpu_pd3>; 145 power-domain-names = "psci"; 146 qcom,freq-domain = <&cpufreq_hw 1>; 147 capacity-dmips-mhz = <1792>; 148 dynamic-power-coefficient = <270>; 149 #cooling-cells = <2>; 150 l2_300: l2-cache { 151 compatible = "cache"; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&l3_0>; 155 }; 156 }; 157 158 cpu4: cpu@400 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a715"; 161 reg = <0 0x400>; 162 clocks = <&cpufreq_hw 1>; 163 enable-method = "psci"; 164 next-level-cache = <&l2_400>; 165 power-domains = <&cpu_pd4>; 166 power-domain-names = "psci"; 167 qcom,freq-domain = <&cpufreq_hw 1>; 168 capacity-dmips-mhz = <1792>; 169 dynamic-power-coefficient = <270>; 170 #cooling-cells = <2>; 171 l2_400: l2-cache { 172 compatible = "cache"; 173 cache-level = <2>; 174 cache-unified; 175 next-level-cache = <&l3_0>; 176 }; 177 }; 178 179 cpu5: cpu@500 { 180 device_type = "cpu"; 181 compatible = "arm,cortex-a710"; 182 reg = <0 0x500>; 183 clocks = <&cpufreq_hw 1>; 184 enable-method = "psci"; 185 next-level-cache = <&l2_500>; 186 power-domains = <&cpu_pd5>; 187 power-domain-names = "psci"; 188 qcom,freq-domain = <&cpufreq_hw 1>; 189 capacity-dmips-mhz = <1792>; 190 dynamic-power-coefficient = <270>; 191 #cooling-cells = <2>; 192 l2_500: l2-cache { 193 compatible = "cache"; 194 cache-level = <2>; 195 cache-unified; 196 next-level-cache = <&l3_0>; 197 }; 198 }; 199 200 cpu6: cpu@600 { 201 device_type = "cpu"; 202 compatible = "arm,cortex-a710"; 203 reg = <0 0x600>; 204 clocks = <&cpufreq_hw 1>; 205 enable-method = "psci"; 206 next-level-cache = <&l2_600>; 207 power-domains = <&cpu_pd6>; 208 power-domain-names = "psci"; 209 qcom,freq-domain = <&cpufreq_hw 1>; 210 capacity-dmips-mhz = <1792>; 211 dynamic-power-coefficient = <270>; 212 #cooling-cells = <2>; 213 l2_600: l2-cache { 214 compatible = "cache"; 215 cache-level = <2>; 216 cache-unified; 217 next-level-cache = <&l3_0>; 218 }; 219 }; 220 221 cpu7: cpu@700 { 222 device_type = "cpu"; 223 compatible = "arm,cortex-x3"; 224 reg = <0 0x700>; 225 clocks = <&cpufreq_hw 2>; 226 enable-method = "psci"; 227 next-level-cache = <&l2_700>; 228 power-domains = <&cpu_pd7>; 229 power-domain-names = "psci"; 230 qcom,freq-domain = <&cpufreq_hw 2>; 231 capacity-dmips-mhz = <1894>; 232 dynamic-power-coefficient = <588>; 233 #cooling-cells = <2>; 234 l2_700: l2-cache { 235 compatible = "cache"; 236 cache-level = <2>; 237 cache-unified; 238 next-level-cache = <&l3_0>; 239 }; 240 }; 241 242 cpu-map { 243 cluster0 { 244 core0 { 245 cpu = <&cpu0>; 246 }; 247 248 core1 { 249 cpu = <&cpu1>; 250 }; 251 252 core2 { 253 cpu = <&cpu2>; 254 }; 255 256 core3 { 257 cpu = <&cpu3>; 258 }; 259 260 core4 { 261 cpu = <&cpu4>; 262 }; 263 264 core5 { 265 cpu = <&cpu5>; 266 }; 267 268 core6 { 269 cpu = <&cpu6>; 270 }; 271 272 core7 { 273 cpu = <&cpu7>; 274 }; 275 }; 276 }; 277 278 idle-states { 279 entry-method = "psci"; 280 281 little_cpu_sleep_0: cpu-sleep-0-0 { 282 compatible = "arm,idle-state"; 283 idle-state-name = "silver-rail-power-collapse"; 284 arm,psci-suspend-param = <0x40000004>; 285 entry-latency-us = <550>; 286 exit-latency-us = <750>; 287 min-residency-us = <6700>; 288 local-timer-stop; 289 }; 290 291 big_cpu_sleep_0: cpu-sleep-1-0 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "gold-rail-power-collapse"; 294 arm,psci-suspend-param = <0x40000004>; 295 entry-latency-us = <600>; 296 exit-latency-us = <1300>; 297 min-residency-us = <8136>; 298 local-timer-stop; 299 }; 300 301 prime_cpu_sleep_0: cpu-sleep-2-0 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "goldplus-rail-power-collapse"; 304 arm,psci-suspend-param = <0x40000004>; 305 entry-latency-us = <500>; 306 exit-latency-us = <1350>; 307 min-residency-us = <7480>; 308 local-timer-stop; 309 }; 310 }; 311 312 domain-idle-states { 313 cluster_sleep_0: cluster-sleep-0 { 314 compatible = "domain-idle-state"; 315 arm,psci-suspend-param = <0x41000044>; 316 entry-latency-us = <750>; 317 exit-latency-us = <2350>; 318 min-residency-us = <9144>; 319 }; 320 321 cluster_sleep_1: cluster-sleep-1 { 322 compatible = "domain-idle-state"; 323 arm,psci-suspend-param = <0x4100c344>; 324 entry-latency-us = <2800>; 325 exit-latency-us = <4400>; 326 min-residency-us = <10150>; 327 }; 328 }; 329 }; 330 331 firmware { 332 scm: scm { 333 compatible = "qcom,scm-sm8550", "qcom,scm"; 334 qcom,dload-mode = <&tcsr 0x19000>; 335 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 336 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 337 }; 338 }; 339 340 clk_virt: interconnect-0 { 341 compatible = "qcom,sm8550-clk-virt"; 342 #interconnect-cells = <2>; 343 qcom,bcm-voters = <&apps_bcm_voter>; 344 }; 345 346 mc_virt: interconnect-1 { 347 compatible = "qcom,sm8550-mc-virt"; 348 #interconnect-cells = <2>; 349 qcom,bcm-voters = <&apps_bcm_voter>; 350 }; 351 352 qup_opp_table_100mhz: opp-table-qup100mhz { 353 compatible = "operating-points-v2"; 354 355 opp-75000000 { 356 opp-hz = /bits/ 64 <75000000>; 357 required-opps = <&rpmhpd_opp_low_svs>; 358 }; 359 360 opp-100000000 { 361 opp-hz = /bits/ 64 <100000000>; 362 required-opps = <&rpmhpd_opp_svs>; 363 }; 364 }; 365 366 qup_opp_table_120mhz: opp-table-qup120mhz { 367 compatible = "operating-points-v2"; 368 369 opp-75000000 { 370 opp-hz = /bits/ 64 <75000000>; 371 required-opps = <&rpmhpd_opp_low_svs>; 372 }; 373 374 opp-120000000 { 375 opp-hz = /bits/ 64 <120000000>; 376 required-opps = <&rpmhpd_opp_svs>; 377 }; 378 }; 379 380 qup_opp_table_125mhz: opp-table-qup125mhz { 381 compatible = "operating-points-v2"; 382 383 opp-75000000 { 384 opp-hz = /bits/ 64 <75000000>; 385 required-opps = <&rpmhpd_opp_low_svs>; 386 }; 387 388 opp-125000000 { 389 opp-hz = /bits/ 64 <125000000>; 390 required-opps = <&rpmhpd_opp_svs>; 391 }; 392 }; 393 394 memory@a0000000 { 395 device_type = "memory"; 396 /* We expect the bootloader to fill in the size */ 397 reg = <0 0xa0000000 0 0>; 398 }; 399 400 pmu-a510 { 401 compatible = "arm,cortex-a510-pmu"; 402 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 403 }; 404 405 pmu-a710 { 406 compatible = "arm,cortex-a710-pmu"; 407 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 408 }; 409 410 pmu-a715 { 411 compatible = "arm,cortex-a715-pmu"; 412 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 413 }; 414 415 pmu-x3 { 416 compatible = "arm,cortex-x3-pmu"; 417 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 418 }; 419 420 psci { 421 compatible = "arm,psci-1.0"; 422 method = "smc"; 423 424 cpu_pd0: power-domain-cpu0 { 425 #power-domain-cells = <0>; 426 power-domains = <&cluster_pd>; 427 domain-idle-states = <&little_cpu_sleep_0>; 428 }; 429 430 cpu_pd1: power-domain-cpu1 { 431 #power-domain-cells = <0>; 432 power-domains = <&cluster_pd>; 433 domain-idle-states = <&little_cpu_sleep_0>; 434 }; 435 436 cpu_pd2: power-domain-cpu2 { 437 #power-domain-cells = <0>; 438 power-domains = <&cluster_pd>; 439 domain-idle-states = <&little_cpu_sleep_0>; 440 }; 441 442 cpu_pd3: power-domain-cpu3 { 443 #power-domain-cells = <0>; 444 power-domains = <&cluster_pd>; 445 domain-idle-states = <&big_cpu_sleep_0>; 446 }; 447 448 cpu_pd4: power-domain-cpu4 { 449 #power-domain-cells = <0>; 450 power-domains = <&cluster_pd>; 451 domain-idle-states = <&big_cpu_sleep_0>; 452 }; 453 454 cpu_pd5: power-domain-cpu5 { 455 #power-domain-cells = <0>; 456 power-domains = <&cluster_pd>; 457 domain-idle-states = <&big_cpu_sleep_0>; 458 }; 459 460 cpu_pd6: power-domain-cpu6 { 461 #power-domain-cells = <0>; 462 power-domains = <&cluster_pd>; 463 domain-idle-states = <&big_cpu_sleep_0>; 464 }; 465 466 cpu_pd7: power-domain-cpu7 { 467 #power-domain-cells = <0>; 468 power-domains = <&cluster_pd>; 469 domain-idle-states = <&prime_cpu_sleep_0>; 470 }; 471 472 cluster_pd: power-domain-cluster { 473 #power-domain-cells = <0>; 474 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; 475 }; 476 }; 477 478 reserved_memory: reserved-memory { 479 #address-cells = <2>; 480 #size-cells = <2>; 481 ranges; 482 483 hyp_mem: hyp-region@80000000 { 484 reg = <0 0x80000000 0 0xa00000>; 485 no-map; 486 }; 487 488 cpusys_vm_mem: cpusys-vm-region@80a00000 { 489 reg = <0 0x80a00000 0 0x400000>; 490 no-map; 491 }; 492 493 hyp_tags_mem: hyp-tags-region@80e00000 { 494 reg = <0 0x80e00000 0 0x3d0000>; 495 no-map; 496 }; 497 498 xbl_sc_mem: xbl-sc-region@d8100000 { 499 reg = <0 0xd8100000 0 0x40000>; 500 no-map; 501 }; 502 503 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 504 reg = <0 0x811d0000 0 0x30000>; 505 no-map; 506 }; 507 508 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 509 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 510 reg = <0 0x81a00000 0 0x260000>; 511 no-map; 512 }; 513 514 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 515 compatible = "qcom,cmd-db"; 516 reg = <0 0x81c60000 0 0x20000>; 517 no-map; 518 }; 519 520 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 521 aop_config_merged_mem: aop-config-merged-region@81c80000 { 522 reg = <0 0x81c80000 0 0x74000>; 523 no-map; 524 }; 525 526 /* secdata region can be reused by apps */ 527 smem: smem@81d00000 { 528 compatible = "qcom,smem"; 529 reg = <0 0x81d00000 0 0x200000>; 530 hwlocks = <&tcsr_mutex 3>; 531 no-map; 532 }; 533 534 adsp_mhi_mem: adsp-mhi-region@81f00000 { 535 reg = <0 0x81f00000 0 0x20000>; 536 no-map; 537 }; 538 539 global_sync_mem: global-sync-region@82600000 { 540 reg = <0 0x82600000 0 0x100000>; 541 no-map; 542 }; 543 544 tz_stat_mem: tz-stat-region@82700000 { 545 reg = <0 0x82700000 0 0x100000>; 546 no-map; 547 }; 548 549 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 550 reg = <0 0x82800000 0 0x4600000>; 551 no-map; 552 }; 553 554 mpss_mem: mpss-region@8a800000 { 555 reg = <0 0x8a800000 0 0x10800000>; 556 no-map; 557 }; 558 559 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 560 reg = <0 0x9b000000 0 0x80000>; 561 no-map; 562 }; 563 564 ipa_fw_mem: ipa-fw-region@9b080000 { 565 reg = <0 0x9b080000 0 0x10000>; 566 no-map; 567 }; 568 569 ipa_gsi_mem: ipa-gsi-region@9b090000 { 570 reg = <0 0x9b090000 0 0xa000>; 571 no-map; 572 }; 573 574 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 575 reg = <0 0x9b09a000 0 0x2000>; 576 no-map; 577 }; 578 579 spss_region_mem: spss-region@9b100000 { 580 reg = <0 0x9b100000 0 0x180000>; 581 no-map; 582 }; 583 584 /* First part of the "SPU secure shared memory" region */ 585 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 586 reg = <0 0x9b280000 0 0x60000>; 587 no-map; 588 }; 589 590 /* Second part of the "SPU secure shared memory" region */ 591 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 592 reg = <0 0x9b2e0000 0 0x20000>; 593 no-map; 594 }; 595 596 camera_mem: camera-region@9b300000 { 597 reg = <0 0x9b300000 0 0x800000>; 598 no-map; 599 }; 600 601 video_mem: video-region@9bb00000 { 602 reg = <0 0x9bb00000 0 0x700000>; 603 no-map; 604 }; 605 606 cvp_mem: cvp-region@9c200000 { 607 reg = <0 0x9c200000 0 0x700000>; 608 no-map; 609 }; 610 611 cdsp_mem: cdsp-region@9c900000 { 612 reg = <0 0x9c900000 0 0x2000000>; 613 no-map; 614 }; 615 616 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 617 reg = <0 0x9e900000 0 0x80000>; 618 no-map; 619 }; 620 621 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 622 reg = <0 0x9e980000 0 0x80000>; 623 no-map; 624 }; 625 626 adspslpi_mem: adspslpi-region@9ea00000 { 627 reg = <0 0x9ea00000 0 0x4080000>; 628 no-map; 629 }; 630 631 /* uefi region can be reused by apps */ 632 633 /* Linux kernel image is loaded at 0xa8000000 */ 634 635 rmtfs_mem: rmtfs-region@d4a80000 { 636 compatible = "qcom,rmtfs-mem"; 637 reg = <0x0 0xd4a80000 0x0 0x280000>; 638 no-map; 639 640 qcom,client-id = <1>; 641 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 642 }; 643 644 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 645 reg = <0 0xd4d00000 0 0x3300000>; 646 no-map; 647 }; 648 649 tz_reserved_mem: tz-reserved-region@d8000000 { 650 reg = <0 0xd8000000 0 0x100000>; 651 no-map; 652 }; 653 654 cpucp_fw_mem: cpucp-fw-region@d8140000 { 655 reg = <0 0xd8140000 0 0x1c0000>; 656 no-map; 657 }; 658 659 qtee_mem: qtee-region@d8300000 { 660 reg = <0 0xd8300000 0 0x500000>; 661 no-map; 662 }; 663 664 ta_mem: ta-region@d8800000 { 665 reg = <0 0xd8800000 0 0x8a00000>; 666 no-map; 667 }; 668 669 tz_tags_mem: tz-tags-region@e1200000 { 670 reg = <0 0xe1200000 0 0x2740000>; 671 no-map; 672 }; 673 674 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 675 reg = <0 0xe6440000 0 0x279000>; 676 no-map; 677 }; 678 679 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 680 reg = <0 0xf3600000 0 0x4aee000>; 681 no-map; 682 }; 683 684 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 685 reg = <0 0xf80ee000 0 0x1000>; 686 no-map; 687 }; 688 689 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 690 reg = <0 0xf80ef000 0 0x9000>; 691 no-map; 692 }; 693 694 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 695 reg = <0 0xf80f8000 0 0x4000>; 696 no-map; 697 }; 698 699 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 700 reg = <0 0xf80fc000 0 0x4000>; 701 no-map; 702 }; 703 704 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 705 reg = <0 0xf8100000 0 0x100000>; 706 no-map; 707 }; 708 709 oem_vm_mem: oem-vm-region@f8400000 { 710 reg = <0 0xf8400000 0 0x4800000>; 711 no-map; 712 }; 713 714 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 715 reg = <0 0xfcc00000 0 0x4000>; 716 no-map; 717 }; 718 719 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 720 reg = <0 0xfcc04000 0 0x100000>; 721 no-map; 722 }; 723 724 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 725 reg = <0 0xfce00000 0 0x2900000>; 726 no-map; 727 }; 728 729 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 730 reg = <0 0xff700000 0 0x100000>; 731 no-map; 732 }; 733 }; 734 735 smp2p-adsp { 736 compatible = "qcom,smp2p"; 737 qcom,smem = <443>, <429>; 738 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 739 IPCC_MPROC_SIGNAL_SMP2P 740 IRQ_TYPE_EDGE_RISING>; 741 mboxes = <&ipcc IPCC_CLIENT_LPASS 742 IPCC_MPROC_SIGNAL_SMP2P>; 743 744 qcom,local-pid = <0>; 745 qcom,remote-pid = <2>; 746 747 smp2p_adsp_out: master-kernel { 748 qcom,entry-name = "master-kernel"; 749 #qcom,smem-state-cells = <1>; 750 }; 751 752 smp2p_adsp_in: slave-kernel { 753 qcom,entry-name = "slave-kernel"; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 }; 757 }; 758 759 smp2p-cdsp { 760 compatible = "qcom,smp2p"; 761 qcom,smem = <94>, <432>; 762 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 763 IPCC_MPROC_SIGNAL_SMP2P 764 IRQ_TYPE_EDGE_RISING>; 765 mboxes = <&ipcc IPCC_CLIENT_CDSP 766 IPCC_MPROC_SIGNAL_SMP2P>; 767 768 qcom,local-pid = <0>; 769 qcom,remote-pid = <5>; 770 771 smp2p_cdsp_out: master-kernel { 772 qcom,entry-name = "master-kernel"; 773 #qcom,smem-state-cells = <1>; 774 }; 775 776 smp2p_cdsp_in: slave-kernel { 777 qcom,entry-name = "slave-kernel"; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 }; 782 783 smp2p-modem { 784 compatible = "qcom,smp2p"; 785 qcom,smem = <435>, <428>; 786 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 787 IPCC_MPROC_SIGNAL_SMP2P 788 IRQ_TYPE_EDGE_RISING>; 789 mboxes = <&ipcc IPCC_CLIENT_MPSS 790 IPCC_MPROC_SIGNAL_SMP2P>; 791 792 qcom,local-pid = <0>; 793 qcom,remote-pid = <1>; 794 795 smp2p_modem_out: master-kernel { 796 qcom,entry-name = "master-kernel"; 797 #qcom,smem-state-cells = <1>; 798 }; 799 800 smp2p_modem_in: slave-kernel { 801 qcom,entry-name = "slave-kernel"; 802 interrupt-controller; 803 #interrupt-cells = <2>; 804 }; 805 806 ipa_smp2p_out: ipa-ap-to-modem { 807 qcom,entry-name = "ipa"; 808 #qcom,smem-state-cells = <1>; 809 }; 810 811 ipa_smp2p_in: ipa-modem-to-ap { 812 qcom,entry-name = "ipa"; 813 interrupt-controller; 814 #interrupt-cells = <2>; 815 }; 816 }; 817 818 soc: soc@0 { 819 compatible = "simple-bus"; 820 ranges = <0 0 0 0 0x10 0>; 821 dma-ranges = <0 0 0 0 0x10 0>; 822 823 #address-cells = <2>; 824 #size-cells = <2>; 825 826 gcc: clock-controller@100000 { 827 compatible = "qcom,sm8550-gcc"; 828 reg = <0 0x00100000 0 0x1f4200>; 829 #clock-cells = <1>; 830 #reset-cells = <1>; 831 #power-domain-cells = <1>; 832 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 833 <&pcie0_phy>, 834 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 835 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 836 <&ufs_mem_phy 0>, 837 <&ufs_mem_phy 1>, 838 <&ufs_mem_phy 2>, 839 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 840 }; 841 842 ipcc: mailbox@408000 { 843 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 844 reg = <0 0x00408000 0 0x1000>; 845 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 846 interrupt-controller; 847 #interrupt-cells = <3>; 848 #mbox-cells = <2>; 849 }; 850 851 gpi_dma2: dma-controller@800000 { 852 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 853 #dma-cells = <3>; 854 reg = <0 0x00800000 0 0x60000>; 855 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 867 dma-channels = <12>; 868 dma-channel-mask = <0x3e>; 869 iommus = <&apps_smmu 0x436 0>; 870 dma-coherent; 871 status = "disabled"; 872 }; 873 874 qupv3_id_1: geniqup@8c0000 { 875 compatible = "qcom,geni-se-qup"; 876 reg = <0 0x008c0000 0 0x2000>; 877 ranges; 878 clock-names = "m-ahb", "s-ahb"; 879 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 880 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 881 iommus = <&apps_smmu 0x423 0>; 882 dma-coherent; 883 #address-cells = <2>; 884 #size-cells = <2>; 885 status = "disabled"; 886 887 i2c8: i2c@880000 { 888 compatible = "qcom,geni-i2c"; 889 reg = <0 0x00880000 0 0x4000>; 890 clock-names = "se"; 891 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 892 pinctrl-names = "default"; 893 pinctrl-0 = <&qup_i2c8_data_clk>; 894 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 898 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 899 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 900 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 901 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 902 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 903 interconnect-names = "qup-core", "qup-config", "qup-memory"; 904 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 905 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 906 dma-names = "tx", "rx"; 907 power-domains = <&rpmhpd RPMHPD_CX>; 908 operating-points-v2 = <&qup_opp_table_120mhz>; 909 status = "disabled"; 910 }; 911 912 spi8: spi@880000 { 913 compatible = "qcom,geni-spi"; 914 reg = <0 0x00880000 0 0x4000>; 915 clock-names = "se"; 916 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 917 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 918 pinctrl-names = "default"; 919 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 920 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 921 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 922 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 923 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 924 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 925 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 926 interconnect-names = "qup-core", "qup-config", "qup-memory"; 927 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 928 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 929 dma-names = "tx", "rx"; 930 power-domains = <&rpmhpd RPMHPD_CX>; 931 operating-points-v2 = <&qup_opp_table_120mhz>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 status = "disabled"; 935 }; 936 937 i2c9: i2c@884000 { 938 compatible = "qcom,geni-i2c"; 939 reg = <0 0x00884000 0 0x4000>; 940 clock-names = "se"; 941 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&qup_i2c9_data_clk>; 944 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 948 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 949 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 950 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 951 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 952 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 953 interconnect-names = "qup-core", "qup-config", "qup-memory"; 954 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 955 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 956 dma-names = "tx", "rx"; 957 power-domains = <&rpmhpd RPMHPD_CX>; 958 operating-points-v2 = <&qup_opp_table_120mhz>; 959 status = "disabled"; 960 }; 961 962 spi9: spi@884000 { 963 compatible = "qcom,geni-spi"; 964 reg = <0 0x00884000 0 0x4000>; 965 clock-names = "se"; 966 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 967 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 970 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 971 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 972 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 973 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 974 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 975 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 976 interconnect-names = "qup-core", "qup-config", "qup-memory"; 977 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 978 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 979 dma-names = "tx", "rx"; 980 power-domains = <&rpmhpd RPMHPD_CX>; 981 operating-points-v2 = <&qup_opp_table_120mhz>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 i2c10: i2c@888000 { 988 compatible = "qcom,geni-i2c"; 989 reg = <0 0x00888000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&qup_i2c10_data_clk>; 994 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 998 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 999 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1000 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1001 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1002 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1003 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1004 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1005 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1006 dma-names = "tx", "rx"; 1007 power-domains = <&rpmhpd RPMHPD_CX>; 1008 operating-points-v2 = <&qup_opp_table_120mhz>; 1009 status = "disabled"; 1010 }; 1011 1012 spi10: spi@888000 { 1013 compatible = "qcom,geni-spi"; 1014 reg = <0 0x00888000 0 0x4000>; 1015 clock-names = "se"; 1016 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1017 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1020 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1021 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1022 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1023 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1024 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1025 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1026 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1027 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1028 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1029 dma-names = "tx", "rx"; 1030 power-domains = <&rpmhpd RPMHPD_CX>; 1031 operating-points-v2 = <&qup_opp_table_120mhz>; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 i2c11: i2c@88c000 { 1038 compatible = "qcom,geni-i2c"; 1039 reg = <0 0x0088c000 0 0x4000>; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1042 pinctrl-names = "default"; 1043 pinctrl-0 = <&qup_i2c11_data_clk>; 1044 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1048 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1049 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1050 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1051 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1052 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1053 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1054 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1055 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1056 dma-names = "tx", "rx"; 1057 power-domains = <&rpmhpd RPMHPD_CX>; 1058 operating-points-v2 = <&qup_opp_table_120mhz>; 1059 status = "disabled"; 1060 }; 1061 1062 spi11: spi@88c000 { 1063 compatible = "qcom,geni-spi"; 1064 reg = <0 0x0088c000 0 0x4000>; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1067 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1070 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1071 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1072 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1073 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1074 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1075 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1076 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1077 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1078 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1079 dma-names = "tx", "rx"; 1080 power-domains = <&rpmhpd RPMHPD_CX>; 1081 operating-points-v2 = <&qup_opp_table_120mhz>; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 status = "disabled"; 1085 }; 1086 1087 i2c12: i2c@890000 { 1088 compatible = "qcom,geni-i2c"; 1089 reg = <0 0x00890000 0 0x4000>; 1090 clock-names = "se"; 1091 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1092 pinctrl-names = "default"; 1093 pinctrl-0 = <&qup_i2c12_data_clk>; 1094 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1098 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1099 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1100 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1101 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1102 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1103 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1104 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1105 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1106 dma-names = "tx", "rx"; 1107 power-domains = <&rpmhpd RPMHPD_CX>; 1108 operating-points-v2 = <&qup_opp_table_120mhz>; 1109 status = "disabled"; 1110 }; 1111 1112 spi12: spi@890000 { 1113 compatible = "qcom,geni-spi"; 1114 reg = <0 0x00890000 0 0x4000>; 1115 clock-names = "se"; 1116 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1117 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1120 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1121 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1122 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1123 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1124 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1125 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1126 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1127 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1128 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1129 dma-names = "tx", "rx"; 1130 power-domains = <&rpmhpd RPMHPD_CX>; 1131 operating-points-v2 = <&qup_opp_table_120mhz>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 status = "disabled"; 1135 }; 1136 1137 i2c13: i2c@894000 { 1138 compatible = "qcom,geni-i2c"; 1139 reg = <0 0x00894000 0 0x4000>; 1140 clock-names = "se"; 1141 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1142 pinctrl-names = "default"; 1143 pinctrl-0 = <&qup_i2c13_data_clk>; 1144 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1148 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1149 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1150 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1151 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1152 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1153 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1154 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1155 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1156 dma-names = "tx", "rx"; 1157 power-domains = <&rpmhpd RPMHPD_CX>; 1158 operating-points-v2 = <&qup_opp_table_120mhz>; 1159 status = "disabled"; 1160 }; 1161 1162 spi13: spi@894000 { 1163 compatible = "qcom,geni-spi"; 1164 reg = <0 0x00894000 0 0x4000>; 1165 clock-names = "se"; 1166 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1167 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1171 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1172 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1173 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1174 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1176 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1177 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1178 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1179 dma-names = "tx", "rx"; 1180 power-domains = <&rpmhpd RPMHPD_CX>; 1181 operating-points-v2 = <&qup_opp_table_120mhz>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 status = "disabled"; 1185 }; 1186 1187 uart14: serial@898000 { 1188 compatible = "qcom,geni-uart"; 1189 reg = <0 0x898000 0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1194 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1195 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1196 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1197 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1198 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1199 interconnect-names = "qup-core", "qup-config"; 1200 power-domains = <&rpmhpd RPMHPD_CX>; 1201 operating-points-v2 = <&qup_opp_table_125mhz>; 1202 status = "disabled"; 1203 }; 1204 1205 i2c15: i2c@89c000 { 1206 compatible = "qcom,geni-i2c"; 1207 reg = <0 0x0089c000 0 0x4000>; 1208 clock-names = "se"; 1209 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1210 pinctrl-names = "default"; 1211 pinctrl-0 = <&qup_i2c15_data_clk>; 1212 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1216 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1217 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1218 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1219 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1220 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1221 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1222 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1223 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1224 dma-names = "tx", "rx"; 1225 power-domains = <&rpmhpd RPMHPD_CX>; 1226 operating-points-v2 = <&qup_opp_table_100mhz>; 1227 status = "disabled"; 1228 }; 1229 1230 spi15: spi@89c000 { 1231 compatible = "qcom,geni-spi"; 1232 reg = <0 0x0089c000 0 0x4000>; 1233 clock-names = "se"; 1234 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1235 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1236 pinctrl-names = "default"; 1237 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1238 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1239 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1240 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1241 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1242 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1243 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1244 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1245 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1246 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1247 dma-names = "tx", "rx"; 1248 power-domains = <&rpmhpd RPMHPD_CX>; 1249 operating-points-v2 = <&qup_opp_table_100mhz>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 status = "disabled"; 1253 }; 1254 }; 1255 1256 i2c_master_hub_0: geniqup@9c0000 { 1257 compatible = "qcom,geni-se-i2c-master-hub"; 1258 reg = <0x0 0x009c0000 0x0 0x2000>; 1259 clock-names = "s-ahb"; 1260 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1261 #address-cells = <2>; 1262 #size-cells = <2>; 1263 ranges; 1264 status = "disabled"; 1265 1266 i2c_hub_0: i2c@980000 { 1267 compatible = "qcom,geni-i2c-master-hub"; 1268 reg = <0x0 0x00980000 0x0 0x4000>; 1269 clock-names = "se", "core"; 1270 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1271 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&hub_i2c0_data_clk>; 1274 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1278 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1279 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1280 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1281 interconnect-names = "qup-core", "qup-config"; 1282 power-domains = <&rpmhpd RPMHPD_CX>; 1283 required-opps = <&rpmhpd_opp_low_svs>; 1284 status = "disabled"; 1285 }; 1286 1287 i2c_hub_1: i2c@984000 { 1288 compatible = "qcom,geni-i2c-master-hub"; 1289 reg = <0x0 0x00984000 0x0 0x4000>; 1290 clock-names = "se", "core"; 1291 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1292 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&hub_i2c1_data_clk>; 1295 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1299 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1300 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1301 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1302 interconnect-names = "qup-core", "qup-config"; 1303 power-domains = <&rpmhpd RPMHPD_CX>; 1304 required-opps = <&rpmhpd_opp_low_svs>; 1305 status = "disabled"; 1306 }; 1307 1308 i2c_hub_2: i2c@988000 { 1309 compatible = "qcom,geni-i2c-master-hub"; 1310 reg = <0x0 0x00988000 0x0 0x4000>; 1311 clock-names = "se", "core"; 1312 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1313 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1314 pinctrl-names = "default"; 1315 pinctrl-0 = <&hub_i2c2_data_clk>; 1316 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1320 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1321 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1322 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1323 interconnect-names = "qup-core", "qup-config"; 1324 power-domains = <&rpmhpd RPMHPD_CX>; 1325 required-opps = <&rpmhpd_opp_low_svs>; 1326 status = "disabled"; 1327 }; 1328 1329 i2c_hub_3: i2c@98c000 { 1330 compatible = "qcom,geni-i2c-master-hub"; 1331 reg = <0x0 0x0098c000 0x0 0x4000>; 1332 clock-names = "se", "core"; 1333 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1334 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1335 pinctrl-names = "default"; 1336 pinctrl-0 = <&hub_i2c3_data_clk>; 1337 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1341 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1342 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1343 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1344 interconnect-names = "qup-core", "qup-config"; 1345 power-domains = <&rpmhpd RPMHPD_CX>; 1346 required-opps = <&rpmhpd_opp_low_svs>; 1347 status = "disabled"; 1348 }; 1349 1350 i2c_hub_4: i2c@990000 { 1351 compatible = "qcom,geni-i2c-master-hub"; 1352 reg = <0x0 0x00990000 0x0 0x4000>; 1353 clock-names = "se", "core"; 1354 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1355 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1356 pinctrl-names = "default"; 1357 pinctrl-0 = <&hub_i2c4_data_clk>; 1358 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1362 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1363 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1364 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1365 interconnect-names = "qup-core", "qup-config"; 1366 power-domains = <&rpmhpd RPMHPD_CX>; 1367 required-opps = <&rpmhpd_opp_low_svs>; 1368 status = "disabled"; 1369 }; 1370 1371 i2c_hub_5: i2c@994000 { 1372 compatible = "qcom,geni-i2c-master-hub"; 1373 reg = <0 0x00994000 0 0x4000>; 1374 clock-names = "se", "core"; 1375 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1376 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1377 pinctrl-names = "default"; 1378 pinctrl-0 = <&hub_i2c5_data_clk>; 1379 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1383 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1384 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1385 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1386 interconnect-names = "qup-core", "qup-config"; 1387 power-domains = <&rpmhpd RPMHPD_CX>; 1388 required-opps = <&rpmhpd_opp_low_svs>; 1389 status = "disabled"; 1390 }; 1391 1392 i2c_hub_6: i2c@998000 { 1393 compatible = "qcom,geni-i2c-master-hub"; 1394 reg = <0 0x00998000 0 0x4000>; 1395 clock-names = "se", "core"; 1396 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1397 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1398 pinctrl-names = "default"; 1399 pinctrl-0 = <&hub_i2c6_data_clk>; 1400 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1404 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1405 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1406 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1407 interconnect-names = "qup-core", "qup-config"; 1408 power-domains = <&rpmhpd RPMHPD_CX>; 1409 required-opps = <&rpmhpd_opp_low_svs>; 1410 status = "disabled"; 1411 }; 1412 1413 i2c_hub_7: i2c@99c000 { 1414 compatible = "qcom,geni-i2c-master-hub"; 1415 reg = <0 0x0099c000 0 0x4000>; 1416 clock-names = "se", "core"; 1417 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1418 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1419 pinctrl-names = "default"; 1420 pinctrl-0 = <&hub_i2c7_data_clk>; 1421 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1425 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1426 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1427 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1428 interconnect-names = "qup-core", "qup-config"; 1429 power-domains = <&rpmhpd RPMHPD_CX>; 1430 required-opps = <&rpmhpd_opp_low_svs>; 1431 status = "disabled"; 1432 }; 1433 1434 i2c_hub_8: i2c@9a0000 { 1435 compatible = "qcom,geni-i2c-master-hub"; 1436 reg = <0 0x009a0000 0 0x4000>; 1437 clock-names = "se", "core"; 1438 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1439 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&hub_i2c8_data_clk>; 1442 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1446 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1447 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1448 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1449 interconnect-names = "qup-core", "qup-config"; 1450 power-domains = <&rpmhpd RPMHPD_CX>; 1451 required-opps = <&rpmhpd_opp_low_svs>; 1452 status = "disabled"; 1453 }; 1454 1455 i2c_hub_9: i2c@9a4000 { 1456 compatible = "qcom,geni-i2c-master-hub"; 1457 reg = <0 0x009a4000 0 0x4000>; 1458 clock-names = "se", "core"; 1459 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1460 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&hub_i2c9_data_clk>; 1463 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1467 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1468 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1469 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1470 interconnect-names = "qup-core", "qup-config"; 1471 power-domains = <&rpmhpd RPMHPD_CX>; 1472 required-opps = <&rpmhpd_opp_low_svs>; 1473 status = "disabled"; 1474 }; 1475 }; 1476 1477 gpi_dma1: dma-controller@a00000 { 1478 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1479 #dma-cells = <3>; 1480 reg = <0 0x00a00000 0 0x60000>; 1481 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1493 dma-channels = <12>; 1494 dma-channel-mask = <0x1e>; 1495 iommus = <&apps_smmu 0xb6 0>; 1496 dma-coherent; 1497 status = "disabled"; 1498 }; 1499 1500 qupv3_id_0: geniqup@ac0000 { 1501 compatible = "qcom,geni-se-qup"; 1502 reg = <0 0x00ac0000 0 0x2000>; 1503 ranges; 1504 clock-names = "m-ahb", "s-ahb"; 1505 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1506 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1507 iommus = <&apps_smmu 0xa3 0>; 1508 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1509 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 1510 interconnect-names = "qup-core"; 1511 dma-coherent; 1512 #address-cells = <2>; 1513 #size-cells = <2>; 1514 status = "disabled"; 1515 1516 i2c0: i2c@a80000 { 1517 compatible = "qcom,geni-i2c"; 1518 reg = <0 0x00a80000 0 0x4000>; 1519 clock-names = "se"; 1520 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1521 pinctrl-names = "default"; 1522 pinctrl-0 = <&qup_i2c0_data_clk>; 1523 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1524 #address-cells = <1>; 1525 #size-cells = <0>; 1526 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1527 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1528 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1529 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1530 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1531 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1532 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1533 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1534 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1535 dma-names = "tx", "rx"; 1536 power-domains = <&rpmhpd RPMHPD_CX>; 1537 operating-points-v2 = <&qup_opp_table_120mhz>; 1538 status = "disabled"; 1539 }; 1540 1541 spi0: spi@a80000 { 1542 compatible = "qcom,geni-spi"; 1543 reg = <0 0x00a80000 0 0x4000>; 1544 clock-names = "se"; 1545 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1546 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1547 pinctrl-names = "default"; 1548 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1549 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1550 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1551 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1552 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1553 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1554 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1555 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1556 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1557 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1558 dma-names = "tx", "rx"; 1559 power-domains = <&rpmhpd RPMHPD_CX>; 1560 operating-points-v2 = <&qup_opp_table_120mhz>; 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 status = "disabled"; 1564 }; 1565 1566 i2c1: i2c@a84000 { 1567 compatible = "qcom,geni-i2c"; 1568 reg = <0 0x00a84000 0 0x4000>; 1569 clock-names = "se"; 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1571 pinctrl-names = "default"; 1572 pinctrl-0 = <&qup_i2c1_data_clk>; 1573 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1574 #address-cells = <1>; 1575 #size-cells = <0>; 1576 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1577 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1578 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1579 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1580 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1581 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1582 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1583 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1584 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1585 dma-names = "tx", "rx"; 1586 power-domains = <&rpmhpd RPMHPD_CX>; 1587 operating-points-v2 = <&qup_opp_table_120mhz>; 1588 status = "disabled"; 1589 }; 1590 1591 spi1: spi@a84000 { 1592 compatible = "qcom,geni-spi"; 1593 reg = <0 0x00a84000 0 0x4000>; 1594 clock-names = "se"; 1595 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1596 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1597 pinctrl-names = "default"; 1598 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1599 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1600 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1601 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1602 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1603 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1604 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1605 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1606 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1607 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1608 dma-names = "tx", "rx"; 1609 power-domains = <&rpmhpd RPMHPD_CX>; 1610 operating-points-v2 = <&qup_opp_table_120mhz>; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 status = "disabled"; 1614 }; 1615 1616 i2c2: i2c@a88000 { 1617 compatible = "qcom,geni-i2c"; 1618 reg = <0 0x00a88000 0 0x4000>; 1619 clock-names = "se"; 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1621 pinctrl-names = "default"; 1622 pinctrl-0 = <&qup_i2c2_data_clk>; 1623 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1624 #address-cells = <1>; 1625 #size-cells = <0>; 1626 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1627 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1628 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1629 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1630 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1631 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1632 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1633 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1634 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1635 dma-names = "tx", "rx"; 1636 power-domains = <&rpmhpd RPMHPD_CX>; 1637 operating-points-v2 = <&qup_opp_table_100mhz>; 1638 status = "disabled"; 1639 }; 1640 1641 spi2: spi@a88000 { 1642 compatible = "qcom,geni-spi"; 1643 reg = <0 0x00a88000 0 0x4000>; 1644 clock-names = "se"; 1645 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1646 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1647 pinctrl-names = "default"; 1648 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1649 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1650 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1651 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1652 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1653 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1654 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1655 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1656 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1657 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1658 dma-names = "tx", "rx"; 1659 power-domains = <&rpmhpd RPMHPD_CX>; 1660 operating-points-v2 = <&qup_opp_table_100mhz>; 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 status = "disabled"; 1664 }; 1665 1666 i2c3: i2c@a8c000 { 1667 compatible = "qcom,geni-i2c"; 1668 reg = <0 0x00a8c000 0 0x4000>; 1669 clock-names = "se"; 1670 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1671 pinctrl-names = "default"; 1672 pinctrl-0 = <&qup_i2c3_data_clk>; 1673 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1677 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1678 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1679 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1680 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1681 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1682 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1683 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1684 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1685 dma-names = "tx", "rx"; 1686 power-domains = <&rpmhpd RPMHPD_CX>; 1687 operating-points-v2 = <&qup_opp_table_100mhz>; 1688 status = "disabled"; 1689 }; 1690 1691 spi3: spi@a8c000 { 1692 compatible = "qcom,geni-spi"; 1693 reg = <0 0x00a8c000 0 0x4000>; 1694 clock-names = "se"; 1695 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1696 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1697 pinctrl-names = "default"; 1698 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1699 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1700 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1701 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1702 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1703 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1704 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1705 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1706 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1707 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1708 dma-names = "tx", "rx"; 1709 power-domains = <&rpmhpd RPMHPD_CX>; 1710 operating-points-v2 = <&qup_opp_table_100mhz>; 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 status = "disabled"; 1714 }; 1715 1716 i2c4: i2c@a90000 { 1717 compatible = "qcom,geni-i2c"; 1718 reg = <0 0x00a90000 0 0x4000>; 1719 clock-names = "se"; 1720 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1721 pinctrl-names = "default"; 1722 pinctrl-0 = <&qup_i2c4_data_clk>; 1723 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1724 #address-cells = <1>; 1725 #size-cells = <0>; 1726 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1727 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1728 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1729 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1730 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1731 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1732 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1733 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1734 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1735 dma-names = "tx", "rx"; 1736 power-domains = <&rpmhpd RPMHPD_CX>; 1737 operating-points-v2 = <&qup_opp_table_100mhz>; 1738 status = "disabled"; 1739 }; 1740 1741 spi4: spi@a90000 { 1742 compatible = "qcom,geni-spi"; 1743 reg = <0 0x00a90000 0 0x4000>; 1744 clock-names = "se"; 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1746 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1747 pinctrl-names = "default"; 1748 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1749 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1750 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1751 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1752 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1753 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1754 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1755 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1756 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1757 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1758 dma-names = "tx", "rx"; 1759 power-domains = <&rpmhpd RPMHPD_CX>; 1760 operating-points-v2 = <&qup_opp_table_100mhz>; 1761 #address-cells = <1>; 1762 #size-cells = <0>; 1763 status = "disabled"; 1764 }; 1765 1766 i2c5: i2c@a94000 { 1767 compatible = "qcom,geni-i2c"; 1768 reg = <0 0x00a94000 0 0x4000>; 1769 clock-names = "se"; 1770 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1771 pinctrl-names = "default"; 1772 pinctrl-0 = <&qup_i2c5_data_clk>; 1773 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1774 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1775 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1776 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1777 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1778 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1779 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1780 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1781 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1782 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1783 dma-names = "tx", "rx"; 1784 power-domains = <&rpmhpd RPMHPD_CX>; 1785 operating-points-v2 = <&qup_opp_table_100mhz>; 1786 #address-cells = <1>; 1787 #size-cells = <0>; 1788 status = "disabled"; 1789 }; 1790 1791 spi5: spi@a94000 { 1792 compatible = "qcom,geni-spi"; 1793 reg = <0 0x00a94000 0 0x4000>; 1794 clock-names = "se"; 1795 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1796 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1797 pinctrl-names = "default"; 1798 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1799 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1800 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1801 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1802 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1803 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1804 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1805 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1806 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1807 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1808 dma-names = "tx", "rx"; 1809 power-domains = <&rpmhpd RPMHPD_CX>; 1810 operating-points-v2 = <&qup_opp_table_100mhz>; 1811 #address-cells = <1>; 1812 #size-cells = <0>; 1813 status = "disabled"; 1814 }; 1815 1816 i2c6: i2c@a98000 { 1817 compatible = "qcom,geni-i2c"; 1818 reg = <0 0x00a98000 0 0x4000>; 1819 clock-names = "se"; 1820 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1821 pinctrl-names = "default"; 1822 pinctrl-0 = <&qup_i2c6_data_clk>; 1823 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1824 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1825 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1826 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1827 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1828 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1829 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1830 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1831 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1832 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1833 dma-names = "tx", "rx"; 1834 power-domains = <&rpmhpd RPMHPD_CX>; 1835 operating-points-v2 = <&qup_opp_table_100mhz>; 1836 #address-cells = <1>; 1837 #size-cells = <0>; 1838 status = "disabled"; 1839 }; 1840 1841 spi6: spi@a98000 { 1842 compatible = "qcom,geni-spi"; 1843 reg = <0 0x00a98000 0 0x4000>; 1844 clock-names = "se"; 1845 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1846 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1847 pinctrl-names = "default"; 1848 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1849 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1850 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1851 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1852 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1853 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1854 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1855 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1856 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1857 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1858 dma-names = "tx", "rx"; 1859 power-domains = <&rpmhpd RPMHPD_CX>; 1860 operating-points-v2 = <&qup_opp_table_100mhz>; 1861 #address-cells = <1>; 1862 #size-cells = <0>; 1863 status = "disabled"; 1864 }; 1865 1866 uart7: serial@a9c000 { 1867 compatible = "qcom,geni-debug-uart"; 1868 reg = <0 0x00a9c000 0 0x4000>; 1869 clock-names = "se"; 1870 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1871 pinctrl-names = "default"; 1872 pinctrl-0 = <&qup_uart7_default>; 1873 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1874 interconnect-names = "qup-core", "qup-config"; 1875 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1876 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1877 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1878 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1879 power-domains = <&rpmhpd RPMHPD_CX>; 1880 operating-points-v2 = <&qup_opp_table_100mhz>; 1881 status = "disabled"; 1882 }; 1883 }; 1884 1885 cnoc_main: interconnect@1500000 { 1886 compatible = "qcom,sm8550-cnoc-main"; 1887 reg = <0 0x01500000 0 0x13080>; 1888 #interconnect-cells = <2>; 1889 qcom,bcm-voters = <&apps_bcm_voter>; 1890 }; 1891 1892 config_noc: interconnect@1600000 { 1893 compatible = "qcom,sm8550-config-noc"; 1894 reg = <0 0x01600000 0 0x6200>; 1895 #interconnect-cells = <2>; 1896 qcom,bcm-voters = <&apps_bcm_voter>; 1897 }; 1898 1899 system_noc: interconnect@1680000 { 1900 compatible = "qcom,sm8550-system-noc"; 1901 reg = <0 0x01680000 0 0x1d080>; 1902 #interconnect-cells = <2>; 1903 qcom,bcm-voters = <&apps_bcm_voter>; 1904 }; 1905 1906 pcie_noc: interconnect@16c0000 { 1907 compatible = "qcom,sm8550-pcie-anoc"; 1908 reg = <0 0x016c0000 0 0x12200>; 1909 #interconnect-cells = <2>; 1910 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1911 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1912 qcom,bcm-voters = <&apps_bcm_voter>; 1913 }; 1914 1915 aggre1_noc: interconnect@16e0000 { 1916 compatible = "qcom,sm8550-aggre1-noc"; 1917 reg = <0 0x016e0000 0 0x14400>; 1918 #interconnect-cells = <2>; 1919 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1920 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1921 qcom,bcm-voters = <&apps_bcm_voter>; 1922 }; 1923 1924 aggre2_noc: interconnect@1700000 { 1925 compatible = "qcom,sm8550-aggre2-noc"; 1926 reg = <0 0x01700000 0 0x1e400>; 1927 #interconnect-cells = <2>; 1928 clocks = <&rpmhcc RPMH_IPA_CLK>; 1929 qcom,bcm-voters = <&apps_bcm_voter>; 1930 }; 1931 1932 mmss_noc: interconnect@1780000 { 1933 compatible = "qcom,sm8550-mmss-noc"; 1934 reg = <0 0x01780000 0 0x5b800>; 1935 #interconnect-cells = <2>; 1936 qcom,bcm-voters = <&apps_bcm_voter>; 1937 }; 1938 1939 rng: rng@10c3000 { 1940 compatible = "qcom,sm8550-trng", "qcom,trng"; 1941 reg = <0 0x010c3000 0 0x1000>; 1942 }; 1943 1944 pcie0: pcie@1c00000 { 1945 device_type = "pci"; 1946 compatible = "qcom,pcie-sm8550"; 1947 reg = <0 0x01c00000 0 0x3000>, 1948 <0 0x60000000 0 0xf1d>, 1949 <0 0x60000f20 0 0xa8>, 1950 <0 0x60001000 0 0x1000>, 1951 <0 0x60100000 0 0x100000>; 1952 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1953 #address-cells = <3>; 1954 #size-cells = <2>; 1955 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1956 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1957 bus-range = <0x00 0xff>; 1958 1959 dma-coherent; 1960 1961 linux,pci-domain = <0>; 1962 num-lanes = <2>; 1963 1964 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1973 interrupt-names = "msi0", 1974 "msi1", 1975 "msi2", 1976 "msi3", 1977 "msi4", 1978 "msi5", 1979 "msi6", 1980 "msi7", 1981 "global"; 1982 #interrupt-cells = <1>; 1983 interrupt-map-mask = <0 0 0 0x7>; 1984 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1985 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1986 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1987 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1988 1989 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1990 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1991 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1992 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1993 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1994 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1995 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1996 clock-names = "aux", 1997 "cfg", 1998 "bus_master", 1999 "bus_slave", 2000 "slave_q2a", 2001 "ddrss_sf_tbu", 2002 "noc_aggr"; 2003 2004 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2005 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2006 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2007 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2008 interconnect-names = "pcie-mem", "cpu-pcie"; 2009 2010 msi-map = <0x0 &gic_its 0x1400 0x1>, 2011 <0x100 &gic_its 0x1401 0x1>; 2012 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 2013 <0x100 &apps_smmu 0x1401 0x1>; 2014 2015 resets = <&gcc GCC_PCIE_0_BCR>; 2016 reset-names = "pci"; 2017 2018 power-domains = <&gcc PCIE_0_GDSC>; 2019 2020 phys = <&pcie0_phy>; 2021 phy-names = "pciephy"; 2022 2023 operating-points-v2 = <&pcie0_opp_table>; 2024 2025 status = "disabled"; 2026 2027 pcie0_opp_table: opp-table { 2028 compatible = "operating-points-v2"; 2029 2030 /* GEN 1 x1 */ 2031 opp-2500000 { 2032 opp-hz = /bits/ 64 <2500000>; 2033 required-opps = <&rpmhpd_opp_low_svs>; 2034 opp-peak-kBps = <250000 1>; 2035 }; 2036 2037 /* GEN 1 x2 and GEN 2 x1 */ 2038 opp-5000000 { 2039 opp-hz = /bits/ 64 <5000000>; 2040 required-opps = <&rpmhpd_opp_low_svs>; 2041 opp-peak-kBps = <500000 1>; 2042 }; 2043 2044 /* GEN 2 x2 */ 2045 opp-10000000 { 2046 opp-hz = /bits/ 64 <10000000>; 2047 required-opps = <&rpmhpd_opp_low_svs>; 2048 opp-peak-kBps = <1000000 1>; 2049 }; 2050 2051 /* GEN 3 x1 */ 2052 opp-8000000 { 2053 opp-hz = /bits/ 64 <8000000>; 2054 required-opps = <&rpmhpd_opp_nom>; 2055 opp-peak-kBps = <984500 1>; 2056 }; 2057 2058 /* GEN 3 x2 */ 2059 opp-16000000 { 2060 opp-hz = /bits/ 64 <16000000>; 2061 required-opps = <&rpmhpd_opp_nom>; 2062 opp-peak-kBps = <1969000 1>; 2063 }; 2064 }; 2065 2066 pcieport0: pcie@0 { 2067 device_type = "pci"; 2068 reg = <0x0 0x0 0x0 0x0 0x0>; 2069 bus-range = <0x01 0xff>; 2070 2071 #address-cells = <3>; 2072 #size-cells = <2>; 2073 ranges; 2074 }; 2075 }; 2076 2077 pcie0_phy: phy@1c06000 { 2078 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 2079 reg = <0 0x01c06000 0 0x2000>; 2080 2081 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2082 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2083 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 2084 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2085 <&gcc GCC_PCIE_0_PIPE_CLK>; 2086 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2087 "pipe"; 2088 2089 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2090 reset-names = "phy"; 2091 2092 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2093 assigned-clock-rates = <100000000>; 2094 2095 power-domains = <&gcc PCIE_0_PHY_GDSC>; 2096 2097 #clock-cells = <0>; 2098 clock-output-names = "pcie0_pipe_clk"; 2099 2100 #phy-cells = <0>; 2101 2102 status = "disabled"; 2103 }; 2104 2105 pcie1: pcie@1c08000 { 2106 device_type = "pci"; 2107 compatible = "qcom,pcie-sm8550"; 2108 reg = <0x0 0x01c08000 0x0 0x3000>, 2109 <0x0 0x40000000 0x0 0xf1d>, 2110 <0x0 0x40000f20 0x0 0xa8>, 2111 <0x0 0x40001000 0x0 0x1000>, 2112 <0x0 0x40100000 0x0 0x100000>; 2113 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2114 #address-cells = <3>; 2115 #size-cells = <2>; 2116 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2117 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2118 bus-range = <0x00 0xff>; 2119 2120 dma-coherent; 2121 2122 linux,pci-domain = <1>; 2123 num-lanes = <2>; 2124 2125 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2128 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2131 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2134 interrupt-names = "msi0", 2135 "msi1", 2136 "msi2", 2137 "msi3", 2138 "msi4", 2139 "msi5", 2140 "msi6", 2141 "msi7", 2142 "global"; 2143 #interrupt-cells = <1>; 2144 interrupt-map-mask = <0 0 0 0x7>; 2145 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2146 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2147 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2148 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2149 2150 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2151 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2152 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2153 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2154 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2155 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2156 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2157 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2158 clock-names = "aux", 2159 "cfg", 2160 "bus_master", 2161 "bus_slave", 2162 "slave_q2a", 2163 "ddrss_sf_tbu", 2164 "noc_aggr", 2165 "cnoc_sf_axi"; 2166 2167 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2168 assigned-clock-rates = <19200000>; 2169 2170 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2171 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2172 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2173 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2174 interconnect-names = "pcie-mem", "cpu-pcie"; 2175 2176 msi-map = <0x0 &gic_its 0x1480 0x1>, 2177 <0x100 &gic_its 0x1481 0x1>; 2178 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 2179 <0x100 &apps_smmu 0x1481 0x1>; 2180 2181 resets = <&gcc GCC_PCIE_1_BCR>, 2182 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2183 reset-names = "pci", "link_down"; 2184 2185 power-domains = <&gcc PCIE_1_GDSC>; 2186 2187 phys = <&pcie1_phy>; 2188 phy-names = "pciephy"; 2189 2190 operating-points-v2 = <&pcie1_opp_table>; 2191 2192 status = "disabled"; 2193 2194 pcie1_opp_table: opp-table { 2195 compatible = "operating-points-v2"; 2196 2197 /* GEN 1 x1 */ 2198 opp-2500000 { 2199 opp-hz = /bits/ 64 <2500000>; 2200 required-opps = <&rpmhpd_opp_low_svs>; 2201 opp-peak-kBps = <250000 1>; 2202 }; 2203 2204 /* GEN 1 x2 and GEN 2 x1 */ 2205 opp-5000000 { 2206 opp-hz = /bits/ 64 <5000000>; 2207 required-opps = <&rpmhpd_opp_low_svs>; 2208 opp-peak-kBps = <500000 1>; 2209 }; 2210 2211 /* GEN 2 x2 */ 2212 opp-10000000 { 2213 opp-hz = /bits/ 64 <10000000>; 2214 required-opps = <&rpmhpd_opp_low_svs>; 2215 opp-peak-kBps = <1000000 1>; 2216 }; 2217 2218 /* GEN 3 x1 */ 2219 opp-8000000 { 2220 opp-hz = /bits/ 64 <8000000>; 2221 required-opps = <&rpmhpd_opp_nom>; 2222 opp-peak-kBps = <984500 1>; 2223 }; 2224 2225 /* GEN 3 x2 and GEN 4 x1 */ 2226 opp-16000000 { 2227 opp-hz = /bits/ 64 <16000000>; 2228 required-opps = <&rpmhpd_opp_nom>; 2229 opp-peak-kBps = <1969000 1>; 2230 }; 2231 2232 /* GEN 4 x2 */ 2233 opp-32000000 { 2234 opp-hz = /bits/ 64 <32000000>; 2235 required-opps = <&rpmhpd_opp_nom>; 2236 opp-peak-kBps = <3938000 1>; 2237 }; 2238 }; 2239 2240 pcie@0 { 2241 device_type = "pci"; 2242 reg = <0x0 0x0 0x0 0x0 0x0>; 2243 bus-range = <0x01 0xff>; 2244 2245 #address-cells = <3>; 2246 #size-cells = <2>; 2247 ranges; 2248 }; 2249 }; 2250 2251 pcie1_phy: phy@1c0e000 { 2252 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 2253 reg = <0x0 0x01c0e000 0x0 0x2000>; 2254 2255 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2256 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2257 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 2258 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2259 <&gcc GCC_PCIE_1_PIPE_CLK>; 2260 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2261 "pipe"; 2262 2263 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 2264 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 2265 reset-names = "phy", "phy_nocsr"; 2266 2267 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2268 assigned-clock-rates = <100000000>; 2269 2270 power-domains = <&gcc PCIE_1_PHY_GDSC>; 2271 2272 #clock-cells = <1>; 2273 clock-output-names = "pcie1_pipe_clk"; 2274 2275 #phy-cells = <0>; 2276 2277 status = "disabled"; 2278 }; 2279 2280 cryptobam: dma-controller@1dc4000 { 2281 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2282 reg = <0x0 0x01dc4000 0x0 0x28000>; 2283 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2284 #dma-cells = <1>; 2285 qcom,ee = <0>; 2286 qcom,num-ees = <4>; 2287 num-channels = <20>; 2288 qcom,controlled-remotely; 2289 iommus = <&apps_smmu 0x480 0x0>, 2290 <&apps_smmu 0x481 0x0>; 2291 }; 2292 2293 crypto: crypto@1dfa000 { 2294 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 2295 reg = <0x0 0x01dfa000 0x0 0x6000>; 2296 dmas = <&cryptobam 4>, <&cryptobam 5>; 2297 dma-names = "rx", "tx"; 2298 iommus = <&apps_smmu 0x480 0x0>, 2299 <&apps_smmu 0x481 0x0>; 2300 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 2301 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2302 interconnect-names = "memory"; 2303 }; 2304 2305 ufs_mem_phy: phy@1d80000 { 2306 compatible = "qcom,sm8550-qmp-ufs-phy"; 2307 reg = <0x0 0x01d80000 0x0 0x2000>; 2308 clocks = <&rpmhcc RPMH_CXO_CLK>, 2309 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2310 <&tcsr TCSR_UFS_CLKREF_EN>; 2311 clock-names = "ref", 2312 "ref_aux", 2313 "qref"; 2314 2315 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 2316 2317 resets = <&ufs_mem_hc 0>; 2318 reset-names = "ufsphy"; 2319 2320 #clock-cells = <1>; 2321 #phy-cells = <0>; 2322 2323 status = "disabled"; 2324 }; 2325 2326 ufs_mem_hc: ufshc@1d84000 { 2327 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 2328 "jedec,ufs-2.0"; 2329 reg = <0x0 0x01d84000 0x0 0x3000>; 2330 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2331 phys = <&ufs_mem_phy>; 2332 phy-names = "ufsphy"; 2333 lanes-per-direction = <2>; 2334 #reset-cells = <1>; 2335 resets = <&gcc GCC_UFS_PHY_BCR>; 2336 reset-names = "rst"; 2337 2338 power-domains = <&gcc UFS_PHY_GDSC>; 2339 required-opps = <&rpmhpd_opp_nom>; 2340 2341 iommus = <&apps_smmu 0x60 0x0>; 2342 dma-coherent; 2343 2344 operating-points-v2 = <&ufs_opp_table>; 2345 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2346 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2347 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2348 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2349 2350 interconnect-names = "ufs-ddr", "cpu-ufs"; 2351 clock-names = "core_clk", 2352 "bus_aggr_clk", 2353 "iface_clk", 2354 "core_clk_unipro", 2355 "ref_clk", 2356 "tx_lane0_sync_clk", 2357 "rx_lane0_sync_clk", 2358 "rx_lane1_sync_clk"; 2359 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2360 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2361 <&gcc GCC_UFS_PHY_AHB_CLK>, 2362 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2363 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 2364 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2365 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2366 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2367 qcom,ice = <&ice>; 2368 2369 status = "disabled"; 2370 2371 ufs_opp_table: opp-table { 2372 compatible = "operating-points-v2"; 2373 2374 opp-75000000 { 2375 opp-hz = /bits/ 64 <75000000>, 2376 /bits/ 64 <0>, 2377 /bits/ 64 <0>, 2378 /bits/ 64 <75000000>, 2379 /bits/ 64 <0>, 2380 /bits/ 64 <0>, 2381 /bits/ 64 <0>, 2382 /bits/ 64 <0>; 2383 required-opps = <&rpmhpd_opp_low_svs>; 2384 }; 2385 2386 opp-150000000 { 2387 opp-hz = /bits/ 64 <150000000>, 2388 /bits/ 64 <0>, 2389 /bits/ 64 <0>, 2390 /bits/ 64 <150000000>, 2391 /bits/ 64 <0>, 2392 /bits/ 64 <0>, 2393 /bits/ 64 <0>, 2394 /bits/ 64 <0>; 2395 required-opps = <&rpmhpd_opp_svs>; 2396 }; 2397 2398 opp-300000000 { 2399 opp-hz = /bits/ 64 <300000000>, 2400 /bits/ 64 <0>, 2401 /bits/ 64 <0>, 2402 /bits/ 64 <300000000>, 2403 /bits/ 64 <0>, 2404 /bits/ 64 <0>, 2405 /bits/ 64 <0>, 2406 /bits/ 64 <0>; 2407 required-opps = <&rpmhpd_opp_nom>; 2408 }; 2409 }; 2410 }; 2411 2412 ice: crypto@1d88000 { 2413 compatible = "qcom,sm8550-inline-crypto-engine", 2414 "qcom,inline-crypto-engine"; 2415 reg = <0 0x01d88000 0 0x18000>; 2416 2417 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2418 }; 2419 2420 tcsr_mutex: hwlock@1f40000 { 2421 compatible = "qcom,tcsr-mutex"; 2422 reg = <0 0x01f40000 0 0x20000>; 2423 #hwlock-cells = <1>; 2424 }; 2425 2426 tcsr: clock-controller@1fc0000 { 2427 compatible = "qcom,sm8550-tcsr", "syscon"; 2428 reg = <0 0x01fc0000 0 0x30000>; 2429 clocks = <&rpmhcc RPMH_CXO_CLK>; 2430 #clock-cells = <1>; 2431 #reset-cells = <1>; 2432 }; 2433 2434 gpu: gpu@3d00000 { 2435 compatible = "qcom,adreno-43050a01", "qcom,adreno"; 2436 reg = <0x0 0x03d00000 0x0 0x40000>, 2437 <0x0 0x03d9e000 0x0 0x1000>, 2438 <0x0 0x03d61000 0x0 0x800>; 2439 reg-names = "kgsl_3d0_reg_memory", 2440 "cx_mem", 2441 "cx_dbgc"; 2442 2443 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2444 2445 iommus = <&adreno_smmu 0 0x0>, 2446 <&adreno_smmu 1 0x0>; 2447 2448 operating-points-v2 = <&gpu_opp_table>; 2449 2450 qcom,gmu = <&gmu>; 2451 #cooling-cells = <2>; 2452 2453 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 2454 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2455 interconnect-names = "gfx-mem"; 2456 2457 status = "disabled"; 2458 2459 zap-shader { 2460 memory-region = <&gpu_micro_code_mem>; 2461 }; 2462 2463 /* Speedbin needs more work on A740+, keep only lower freqs */ 2464 gpu_opp_table: opp-table { 2465 compatible = "operating-points-v2"; 2466 2467 opp-680000000 { 2468 opp-hz = /bits/ 64 <680000000>; 2469 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2470 opp-peak-kBps = <16500000>; 2471 }; 2472 2473 opp-615000000 { 2474 opp-hz = /bits/ 64 <615000000>; 2475 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2476 opp-peak-kBps = <12449218>; 2477 }; 2478 2479 opp-550000000 { 2480 opp-hz = /bits/ 64 <550000000>; 2481 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2482 opp-peak-kBps = <10687500>; 2483 }; 2484 2485 opp-475000000 { 2486 opp-hz = /bits/ 64 <475000000>; 2487 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2488 opp-peak-kBps = <6074218>; 2489 }; 2490 2491 opp-401000000 { 2492 opp-hz = /bits/ 64 <401000000>; 2493 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2494 opp-peak-kBps = <6074218>; 2495 }; 2496 2497 opp-348000000 { 2498 opp-hz = /bits/ 64 <348000000>; 2499 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 2500 opp-peak-kBps = <6074218>; 2501 }; 2502 2503 opp-295000000 { 2504 opp-hz = /bits/ 64 <295000000>; 2505 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2506 opp-peak-kBps = <6074218>; 2507 }; 2508 2509 opp-220000000 { 2510 opp-hz = /bits/ 64 <220000000>; 2511 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 2512 opp-peak-kBps = <2136718>; 2513 }; 2514 }; 2515 }; 2516 2517 gmu: gmu@3d6a000 { 2518 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu"; 2519 reg = <0x0 0x03d6a000 0x0 0x35000>, 2520 <0x0 0x03d50000 0x0 0x10000>, 2521 <0x0 0x0b280000 0x0 0x10000>; 2522 reg-names = "gmu", "rscc", "gmu_pdc"; 2523 2524 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2525 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2526 interrupt-names = "hfi", "gmu"; 2527 2528 clocks = <&gpucc GPU_CC_AHB_CLK>, 2529 <&gpucc GPU_CC_CX_GMU_CLK>, 2530 <&gpucc GPU_CC_CXO_CLK>, 2531 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2532 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2533 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2534 <&gpucc GPU_CC_DEMET_CLK>; 2535 clock-names = "ahb", 2536 "gmu", 2537 "cxo", 2538 "axi", 2539 "memnoc", 2540 "hub", 2541 "demet"; 2542 2543 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2544 <&gpucc GPU_CC_GX_GDSC>; 2545 power-domain-names = "cx", 2546 "gx"; 2547 2548 iommus = <&adreno_smmu 5 0x0>; 2549 2550 qcom,qmp = <&aoss_qmp>; 2551 2552 operating-points-v2 = <&gmu_opp_table>; 2553 2554 gmu_opp_table: opp-table { 2555 compatible = "operating-points-v2"; 2556 2557 opp-500000000 { 2558 opp-hz = /bits/ 64 <500000000>; 2559 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2560 }; 2561 2562 opp-200000000 { 2563 opp-hz = /bits/ 64 <200000000>; 2564 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2565 }; 2566 }; 2567 }; 2568 2569 gpucc: clock-controller@3d90000 { 2570 compatible = "qcom,sm8550-gpucc"; 2571 reg = <0 0x03d90000 0 0xa000>; 2572 clocks = <&bi_tcxo_div2>, 2573 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2574 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2575 #clock-cells = <1>; 2576 #reset-cells = <1>; 2577 #power-domain-cells = <1>; 2578 }; 2579 2580 adreno_smmu: iommu@3da0000 { 2581 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", 2582 "qcom,smmu-500", "arm,mmu-500"; 2583 reg = <0x0 0x03da0000 0x0 0x40000>; 2584 #iommu-cells = <2>; 2585 #global-interrupts = <1>; 2586 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2587 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>, 2588 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2589 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2590 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2591 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2592 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2593 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2594 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2595 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2596 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2597 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2598 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2599 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2600 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2601 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2602 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2603 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2604 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2605 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2606 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2607 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2608 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2609 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2610 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2611 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 2612 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2613 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2614 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2615 <&gpucc GPU_CC_AHB_CLK>; 2616 clock-names = "hlos", 2617 "bus", 2618 "iface", 2619 "ahb"; 2620 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2621 dma-coherent; 2622 }; 2623 2624 ipa: ipa@3f40000 { 2625 compatible = "qcom,sm8550-ipa"; 2626 2627 iommus = <&apps_smmu 0x4a0 0x0>, 2628 <&apps_smmu 0x4a2 0x0>; 2629 reg = <0 0x3f40000 0 0x10000>, 2630 <0 0x3f50000 0 0x5000>, 2631 <0 0x3e04000 0 0xfc000>; 2632 reg-names = "ipa-reg", 2633 "ipa-shared", 2634 "gsi"; 2635 2636 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2637 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2638 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2639 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2640 interrupt-names = "ipa", 2641 "gsi", 2642 "ipa-clock-query", 2643 "ipa-setup-ready"; 2644 2645 clocks = <&rpmhcc RPMH_IPA_CLK>; 2646 clock-names = "core"; 2647 2648 interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS 2649 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2650 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2651 &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2652 interconnect-names = "memory", 2653 "config"; 2654 2655 qcom,qmp = <&aoss_qmp>; 2656 2657 qcom,smem-states = <&ipa_smp2p_out 0>, 2658 <&ipa_smp2p_out 1>; 2659 qcom,smem-state-names = "ipa-clock-enabled-valid", 2660 "ipa-clock-enabled"; 2661 2662 status = "disabled"; 2663 }; 2664 2665 remoteproc_mpss: remoteproc@4080000 { 2666 compatible = "qcom,sm8550-mpss-pas"; 2667 reg = <0x0 0x04080000 0x0 0x10000>; 2668 2669 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2670 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2671 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2672 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2673 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2674 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2675 interrupt-names = "wdog", "fatal", "ready", "handover", 2676 "stop-ack", "shutdown-ack"; 2677 2678 clocks = <&rpmhcc RPMH_CXO_CLK>; 2679 clock-names = "xo"; 2680 2681 power-domains = <&rpmhpd RPMHPD_CX>, 2682 <&rpmhpd RPMHPD_MSS>; 2683 power-domain-names = "cx", "mss"; 2684 2685 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 2686 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2687 2688 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 2689 2690 qcom,qmp = <&aoss_qmp>; 2691 2692 qcom,smem-states = <&smp2p_modem_out 0>; 2693 qcom,smem-state-names = "stop"; 2694 2695 status = "disabled"; 2696 2697 glink-edge { 2698 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2699 IPCC_MPROC_SIGNAL_GLINK_QMP 2700 IRQ_TYPE_EDGE_RISING>; 2701 mboxes = <&ipcc IPCC_CLIENT_MPSS 2702 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2703 label = "mpss"; 2704 qcom,remote-pid = <1>; 2705 }; 2706 }; 2707 2708 remoteproc_adsp: remoteproc@6800000 { 2709 compatible = "qcom,sm8550-adsp-pas"; 2710 reg = <0x0 0x06800000 0x0 0x10000>; 2711 2712 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2713 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2714 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2715 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2716 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2717 interrupt-names = "wdog", "fatal", "ready", 2718 "handover", "stop-ack"; 2719 2720 clocks = <&rpmhcc RPMH_CXO_CLK>; 2721 clock-names = "xo"; 2722 2723 power-domains = <&rpmhpd RPMHPD_LCX>, 2724 <&rpmhpd RPMHPD_LMX>; 2725 power-domain-names = "lcx", "lmx"; 2726 2727 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 2728 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2729 2730 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2731 2732 qcom,qmp = <&aoss_qmp>; 2733 2734 qcom,smem-states = <&smp2p_adsp_out 0>; 2735 qcom,smem-state-names = "stop"; 2736 2737 status = "disabled"; 2738 2739 remoteproc_adsp_glink: glink-edge { 2740 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2741 IPCC_MPROC_SIGNAL_GLINK_QMP 2742 IRQ_TYPE_EDGE_RISING>; 2743 mboxes = <&ipcc IPCC_CLIENT_LPASS 2744 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2745 2746 label = "lpass"; 2747 qcom,remote-pid = <2>; 2748 2749 fastrpc { 2750 compatible = "qcom,fastrpc"; 2751 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2752 label = "adsp"; 2753 qcom,non-secure-domain; 2754 #address-cells = <1>; 2755 #size-cells = <0>; 2756 2757 compute-cb@3 { 2758 compatible = "qcom,fastrpc-compute-cb"; 2759 reg = <3>; 2760 iommus = <&apps_smmu 0x1003 0x80>, 2761 <&apps_smmu 0x1063 0x0>; 2762 dma-coherent; 2763 }; 2764 2765 compute-cb@4 { 2766 compatible = "qcom,fastrpc-compute-cb"; 2767 reg = <4>; 2768 iommus = <&apps_smmu 0x1004 0x80>, 2769 <&apps_smmu 0x1064 0x0>; 2770 dma-coherent; 2771 }; 2772 2773 compute-cb@5 { 2774 compatible = "qcom,fastrpc-compute-cb"; 2775 reg = <5>; 2776 iommus = <&apps_smmu 0x1005 0x80>, 2777 <&apps_smmu 0x1065 0x0>; 2778 dma-coherent; 2779 }; 2780 2781 compute-cb@6 { 2782 compatible = "qcom,fastrpc-compute-cb"; 2783 reg = <6>; 2784 iommus = <&apps_smmu 0x1006 0x80>, 2785 <&apps_smmu 0x1066 0x0>; 2786 dma-coherent; 2787 }; 2788 2789 compute-cb@7 { 2790 compatible = "qcom,fastrpc-compute-cb"; 2791 reg = <7>; 2792 iommus = <&apps_smmu 0x1007 0x80>, 2793 <&apps_smmu 0x1067 0x0>; 2794 dma-coherent; 2795 }; 2796 }; 2797 2798 gpr { 2799 compatible = "qcom,gpr"; 2800 qcom,glink-channels = "adsp_apps"; 2801 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2802 qcom,intents = <512 20>; 2803 #address-cells = <1>; 2804 #size-cells = <0>; 2805 2806 q6apm: service@1 { 2807 compatible = "qcom,q6apm"; 2808 reg = <GPR_APM_MODULE_IID>; 2809 #sound-dai-cells = <0>; 2810 qcom,protection-domain = "avs/audio", 2811 "msm/adsp/audio_pd"; 2812 2813 q6apmdai: dais { 2814 compatible = "qcom,q6apm-dais"; 2815 iommus = <&apps_smmu 0x1001 0x80>, 2816 <&apps_smmu 0x1061 0x0>; 2817 }; 2818 2819 q6apmbedai: bedais { 2820 compatible = "qcom,q6apm-lpass-dais"; 2821 #sound-dai-cells = <1>; 2822 }; 2823 }; 2824 2825 q6prm: service@2 { 2826 compatible = "qcom,q6prm"; 2827 reg = <GPR_PRM_MODULE_IID>; 2828 qcom,protection-domain = "avs/audio", 2829 "msm/adsp/audio_pd"; 2830 2831 q6prmcc: clock-controller { 2832 compatible = "qcom,q6prm-lpass-clocks"; 2833 #clock-cells = <2>; 2834 }; 2835 }; 2836 }; 2837 }; 2838 }; 2839 2840 lpass_wsa2macro: codec@6aa0000 { 2841 compatible = "qcom,sm8550-lpass-wsa-macro"; 2842 reg = <0 0x06aa0000 0 0x1000>; 2843 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2844 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2845 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2846 <&lpass_vamacro>; 2847 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2848 2849 #clock-cells = <0>; 2850 clock-output-names = "wsa2-mclk"; 2851 #sound-dai-cells = <1>; 2852 }; 2853 2854 swr3: soundwire@6ab0000 { 2855 compatible = "qcom,soundwire-v2.0.0"; 2856 reg = <0 0x06ab0000 0 0x10000>; 2857 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2858 clocks = <&lpass_wsa2macro>; 2859 clock-names = "iface"; 2860 label = "WSA2"; 2861 2862 pinctrl-0 = <&wsa2_swr_active>; 2863 pinctrl-names = "default"; 2864 2865 qcom,din-ports = <4>; 2866 qcom,dout-ports = <9>; 2867 2868 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2869 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2870 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2871 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2872 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2873 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2874 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2875 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2876 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2877 2878 #address-cells = <2>; 2879 #size-cells = <0>; 2880 #sound-dai-cells = <1>; 2881 status = "disabled"; 2882 }; 2883 2884 lpass_rxmacro: codec@6ac0000 { 2885 compatible = "qcom,sm8550-lpass-rx-macro"; 2886 reg = <0 0x06ac0000 0 0x1000>; 2887 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2888 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2889 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2890 <&lpass_vamacro>; 2891 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2892 2893 #clock-cells = <0>; 2894 clock-output-names = "mclk"; 2895 #sound-dai-cells = <1>; 2896 }; 2897 2898 swr1: soundwire@6ad0000 { 2899 compatible = "qcom,soundwire-v2.0.0"; 2900 reg = <0 0x06ad0000 0 0x10000>; 2901 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2902 clocks = <&lpass_rxmacro>; 2903 clock-names = "iface"; 2904 label = "RX"; 2905 2906 pinctrl-0 = <&rx_swr_active>; 2907 pinctrl-names = "default"; 2908 2909 qcom,din-ports = <1>; 2910 qcom,dout-ports = <11>; 2911 2912 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>; 2913 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2914 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2915 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2916 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2917 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>; 2918 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2919 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2920 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2921 2922 #address-cells = <2>; 2923 #size-cells = <0>; 2924 #sound-dai-cells = <1>; 2925 status = "disabled"; 2926 }; 2927 2928 lpass_txmacro: codec@6ae0000 { 2929 compatible = "qcom,sm8550-lpass-tx-macro"; 2930 reg = <0 0x06ae0000 0 0x1000>; 2931 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2932 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2933 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2934 <&lpass_vamacro>; 2935 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2936 2937 #clock-cells = <0>; 2938 clock-output-names = "mclk"; 2939 #sound-dai-cells = <1>; 2940 }; 2941 2942 lpass_wsamacro: codec@6b00000 { 2943 compatible = "qcom,sm8550-lpass-wsa-macro"; 2944 reg = <0 0x06b00000 0 0x1000>; 2945 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2946 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2947 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2948 <&lpass_vamacro>; 2949 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2950 2951 #clock-cells = <0>; 2952 clock-output-names = "mclk"; 2953 #sound-dai-cells = <1>; 2954 }; 2955 2956 swr0: soundwire@6b10000 { 2957 compatible = "qcom,soundwire-v2.0.0"; 2958 reg = <0 0x06b10000 0 0x10000>; 2959 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2960 clocks = <&lpass_wsamacro>; 2961 clock-names = "iface"; 2962 label = "WSA"; 2963 2964 pinctrl-0 = <&wsa_swr_active>; 2965 pinctrl-names = "default"; 2966 2967 qcom,din-ports = <4>; 2968 qcom,dout-ports = <9>; 2969 2970 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2971 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2972 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2973 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2974 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2975 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2976 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2977 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2978 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2979 2980 #address-cells = <2>; 2981 #size-cells = <0>; 2982 #sound-dai-cells = <1>; 2983 status = "disabled"; 2984 }; 2985 2986 swr2: soundwire@6d30000 { 2987 compatible = "qcom,soundwire-v2.0.0"; 2988 reg = <0 0x06d30000 0 0x10000>; 2989 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2990 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2991 interrupt-names = "core", "wakeup"; 2992 clocks = <&lpass_txmacro>; 2993 clock-names = "iface"; 2994 label = "TX"; 2995 2996 pinctrl-0 = <&tx_swr_active>; 2997 pinctrl-names = "default"; 2998 2999 qcom,din-ports = <4>; 3000 qcom,dout-ports = <0>; 3001 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3002 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 3003 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3004 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3005 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3006 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3007 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3008 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3009 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 3010 3011 #address-cells = <2>; 3012 #size-cells = <0>; 3013 #sound-dai-cells = <1>; 3014 status = "disabled"; 3015 }; 3016 3017 lpass_vamacro: codec@6d44000 { 3018 compatible = "qcom,sm8550-lpass-va-macro"; 3019 reg = <0 0x06d44000 0 0x1000>; 3020 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3021 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3022 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3023 clock-names = "mclk", "macro", "dcodec"; 3024 3025 #clock-cells = <0>; 3026 clock-output-names = "fsgen"; 3027 #sound-dai-cells = <1>; 3028 }; 3029 3030 lpass_tlmm: pinctrl@6e80000 { 3031 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 3032 reg = <0 0x06e80000 0 0x20000>, 3033 <0 0x07250000 0 0x10000>; 3034 gpio-controller; 3035 #gpio-cells = <2>; 3036 gpio-ranges = <&lpass_tlmm 0 0 23>; 3037 3038 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3039 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3040 clock-names = "core", "audio"; 3041 3042 tx_swr_active: tx-swr-active-state { 3043 clk-pins { 3044 pins = "gpio0"; 3045 function = "swr_tx_clk"; 3046 drive-strength = <2>; 3047 slew-rate = <1>; 3048 bias-disable; 3049 }; 3050 3051 data-pins { 3052 pins = "gpio1", "gpio2", "gpio14"; 3053 function = "swr_tx_data"; 3054 drive-strength = <2>; 3055 slew-rate = <1>; 3056 bias-bus-hold; 3057 }; 3058 }; 3059 3060 rx_swr_active: rx-swr-active-state { 3061 clk-pins { 3062 pins = "gpio3"; 3063 function = "swr_rx_clk"; 3064 drive-strength = <2>; 3065 slew-rate = <1>; 3066 bias-disable; 3067 }; 3068 3069 data-pins { 3070 pins = "gpio4", "gpio5"; 3071 function = "swr_rx_data"; 3072 drive-strength = <2>; 3073 slew-rate = <1>; 3074 bias-bus-hold; 3075 }; 3076 }; 3077 3078 dmic01_default: dmic01-default-state { 3079 clk-pins { 3080 pins = "gpio6"; 3081 function = "dmic1_clk"; 3082 drive-strength = <8>; 3083 output-high; 3084 }; 3085 3086 data-pins { 3087 pins = "gpio7"; 3088 function = "dmic1_data"; 3089 drive-strength = <8>; 3090 input-enable; 3091 }; 3092 }; 3093 3094 dmic23_default: dmic23-default-state { 3095 clk-pins { 3096 pins = "gpio8"; 3097 function = "dmic2_clk"; 3098 drive-strength = <8>; 3099 output-high; 3100 }; 3101 3102 data-pins { 3103 pins = "gpio9"; 3104 function = "dmic2_data"; 3105 drive-strength = <8>; 3106 input-enable; 3107 }; 3108 }; 3109 3110 wsa_swr_active: wsa-swr-active-state { 3111 clk-pins { 3112 pins = "gpio10"; 3113 function = "wsa_swr_clk"; 3114 drive-strength = <2>; 3115 slew-rate = <1>; 3116 bias-disable; 3117 }; 3118 3119 data-pins { 3120 pins = "gpio11"; 3121 function = "wsa_swr_data"; 3122 drive-strength = <2>; 3123 slew-rate = <1>; 3124 bias-bus-hold; 3125 }; 3126 }; 3127 3128 wsa2_swr_active: wsa2-swr-active-state { 3129 clk-pins { 3130 pins = "gpio15"; 3131 function = "wsa2_swr_clk"; 3132 drive-strength = <2>; 3133 slew-rate = <1>; 3134 bias-disable; 3135 }; 3136 3137 data-pins { 3138 pins = "gpio16"; 3139 function = "wsa2_swr_data"; 3140 drive-strength = <2>; 3141 slew-rate = <1>; 3142 bias-bus-hold; 3143 }; 3144 }; 3145 }; 3146 3147 lpass_lpiaon_noc: interconnect@7400000 { 3148 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 3149 reg = <0 0x07400000 0 0x19080>; 3150 #interconnect-cells = <2>; 3151 qcom,bcm-voters = <&apps_bcm_voter>; 3152 }; 3153 3154 lpass_lpicx_noc: interconnect@7430000 { 3155 compatible = "qcom,sm8550-lpass-lpicx-noc"; 3156 reg = <0 0x07430000 0 0x3a200>; 3157 #interconnect-cells = <2>; 3158 qcom,bcm-voters = <&apps_bcm_voter>; 3159 }; 3160 3161 lpass_ag_noc: interconnect@7e40000 { 3162 compatible = "qcom,sm8550-lpass-ag-noc"; 3163 reg = <0 0x07e40000 0 0xe080>; 3164 #interconnect-cells = <2>; 3165 qcom,bcm-voters = <&apps_bcm_voter>; 3166 }; 3167 3168 sdhc_2: mmc@8804000 { 3169 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 3170 reg = <0 0x08804000 0 0x1000>; 3171 3172 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3174 interrupt-names = "hc_irq", "pwr_irq"; 3175 3176 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3177 <&gcc GCC_SDCC2_APPS_CLK>, 3178 <&rpmhcc RPMH_CXO_CLK>; 3179 clock-names = "iface", "core", "xo"; 3180 iommus = <&apps_smmu 0x540 0>; 3181 qcom,dll-config = <0x0007642c>; 3182 qcom,ddr-config = <0x80040868>; 3183 power-domains = <&rpmhpd RPMHPD_CX>; 3184 operating-points-v2 = <&sdhc2_opp_table>; 3185 3186 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3187 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3188 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3189 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 3190 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 3191 bus-width = <4>; 3192 dma-coherent; 3193 3194 /* Forbid SDR104/SDR50 - broken hw! */ 3195 sdhci-caps-mask = <0x3 0>; 3196 3197 status = "disabled"; 3198 3199 sdhc2_opp_table: opp-table { 3200 compatible = "operating-points-v2"; 3201 3202 opp-19200000 { 3203 opp-hz = /bits/ 64 <19200000>; 3204 required-opps = <&rpmhpd_opp_min_svs>; 3205 }; 3206 3207 opp-50000000 { 3208 opp-hz = /bits/ 64 <50000000>; 3209 required-opps = <&rpmhpd_opp_low_svs>; 3210 }; 3211 3212 opp-100000000 { 3213 opp-hz = /bits/ 64 <100000000>; 3214 required-opps = <&rpmhpd_opp_svs>; 3215 }; 3216 3217 opp-202000000 { 3218 opp-hz = /bits/ 64 <202000000>; 3219 required-opps = <&rpmhpd_opp_svs_l1>; 3220 }; 3221 }; 3222 }; 3223 3224 iris: video-codec@aa00000 { 3225 compatible = "qcom,sm8550-iris"; 3226 3227 reg = <0 0x0aa00000 0 0xf0000>; 3228 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3229 3230 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 3231 <&videocc VIDEO_CC_MVS0_GDSC>, 3232 <&rpmhpd RPMHPD_MXC>, 3233 <&rpmhpd RPMHPD_MMCX>; 3234 power-domain-names = "venus", 3235 "vcodec0", 3236 "mxc", 3237 "mmcx"; 3238 operating-points-v2 = <&iris_opp_table>; 3239 3240 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3241 <&videocc VIDEO_CC_MVS0C_CLK>, 3242 <&videocc VIDEO_CC_MVS0_CLK>; 3243 clock-names = "iface", 3244 "core", 3245 "vcodec0_core"; 3246 3247 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3248 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 3249 <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS 3250 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3251 interconnect-names = "cpu-cfg", 3252 "video-mem"; 3253 3254 memory-region = <&video_mem>; 3255 3256 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 3257 reset-names = "bus"; 3258 3259 iommus = <&apps_smmu 0x1940 0>, 3260 <&apps_smmu 0x1947 0>; 3261 dma-coherent; 3262 3263 /* 3264 * IRIS firmware is signed by vendors, only 3265 * enable in boards where the proper signed firmware 3266 * is available. 3267 */ 3268 status = "disabled"; 3269 3270 iris_opp_table: opp-table { 3271 compatible = "operating-points-v2"; 3272 3273 opp-240000000 { 3274 opp-hz = /bits/ 64 <240000000>; 3275 required-opps = <&rpmhpd_opp_svs>, 3276 <&rpmhpd_opp_low_svs>; 3277 }; 3278 3279 opp-338000000 { 3280 opp-hz = /bits/ 64 <338000000>; 3281 required-opps = <&rpmhpd_opp_svs>, 3282 <&rpmhpd_opp_svs>; 3283 }; 3284 3285 opp-366000000 { 3286 opp-hz = /bits/ 64 <366000000>; 3287 required-opps = <&rpmhpd_opp_svs_l1>, 3288 <&rpmhpd_opp_svs_l1>; 3289 }; 3290 3291 opp-444000000 { 3292 opp-hz = /bits/ 64 <444000000>; 3293 required-opps = <&rpmhpd_opp_nom>, 3294 <&rpmhpd_opp_nom>; 3295 }; 3296 3297 opp-533333334 { 3298 opp-hz = /bits/ 64 <533333334>; 3299 required-opps = <&rpmhpd_opp_turbo>, 3300 <&rpmhpd_opp_turbo>; 3301 }; 3302 }; 3303 }; 3304 3305 videocc: clock-controller@aaf0000 { 3306 compatible = "qcom,sm8550-videocc"; 3307 reg = <0 0x0aaf0000 0 0x10000>; 3308 clocks = <&bi_tcxo_div2>, 3309 <&gcc GCC_VIDEO_AHB_CLK>; 3310 power-domains = <&rpmhpd RPMHPD_MMCX>; 3311 required-opps = <&rpmhpd_opp_low_svs>; 3312 #clock-cells = <1>; 3313 #reset-cells = <1>; 3314 #power-domain-cells = <1>; 3315 }; 3316 3317 cci0: cci@ac15000 { 3318 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 3319 reg = <0 0x0ac15000 0 0x1000>; 3320 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>; 3321 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3322 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3323 <&camcc CAM_CC_CPAS_AHB_CLK>, 3324 <&camcc CAM_CC_CCI_0_CLK>; 3325 clock-names = "camnoc_axi", 3326 "cpas_ahb", 3327 "cci"; 3328 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 3329 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 3330 pinctrl-names = "default", "sleep"; 3331 status = "disabled"; 3332 #address-cells = <1>; 3333 #size-cells = <0>; 3334 3335 cci0_i2c0: i2c-bus@0 { 3336 reg = <0>; 3337 clock-frequency = <1000000>; 3338 #address-cells = <1>; 3339 #size-cells = <0>; 3340 }; 3341 3342 cci0_i2c1: i2c-bus@1 { 3343 reg = <1>; 3344 clock-frequency = <1000000>; 3345 #address-cells = <1>; 3346 #size-cells = <0>; 3347 }; 3348 }; 3349 3350 cci1: cci@ac16000 { 3351 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 3352 reg = <0 0x0ac16000 0 0x1000>; 3353 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>; 3354 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3355 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3356 <&camcc CAM_CC_CPAS_AHB_CLK>, 3357 <&camcc CAM_CC_CCI_1_CLK>; 3358 clock-names = "camnoc_axi", 3359 "cpas_ahb", 3360 "cci"; 3361 pinctrl-0 = <&cci1_0_default>; 3362 pinctrl-1 = <&cci1_0_sleep>; 3363 pinctrl-names = "default", "sleep"; 3364 status = "disabled"; 3365 #address-cells = <1>; 3366 #size-cells = <0>; 3367 3368 cci1_i2c0: i2c-bus@0 { 3369 reg = <0>; 3370 clock-frequency = <1000000>; 3371 #address-cells = <1>; 3372 #size-cells = <0>; 3373 }; 3374 }; 3375 3376 cci2: cci@ac17000 { 3377 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 3378 reg = <0 0x0ac17000 0 0x1000>; 3379 interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>; 3380 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3381 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3382 <&camcc CAM_CC_CPAS_AHB_CLK>, 3383 <&camcc CAM_CC_CCI_2_CLK>; 3384 clock-names = "camnoc_axi", 3385 "cpas_ahb", 3386 "cci"; 3387 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 3388 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 3389 pinctrl-names = "default", "sleep"; 3390 status = "disabled"; 3391 #address-cells = <1>; 3392 #size-cells = <0>; 3393 3394 cci2_i2c0: i2c-bus@0 { 3395 reg = <0>; 3396 clock-frequency = <1000000>; 3397 #address-cells = <1>; 3398 #size-cells = <0>; 3399 }; 3400 3401 cci2_i2c1: i2c-bus@1 { 3402 reg = <1>; 3403 clock-frequency = <1000000>; 3404 #address-cells = <1>; 3405 #size-cells = <0>; 3406 }; 3407 }; 3408 3409 camcc: clock-controller@ade0000 { 3410 compatible = "qcom,sm8550-camcc"; 3411 reg = <0 0x0ade0000 0 0x20000>; 3412 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3413 <&bi_tcxo_div2>, 3414 <&bi_tcxo_ao_div2>, 3415 <&sleep_clk>; 3416 power-domains = <&rpmhpd SM8550_MMCX>; 3417 required-opps = <&rpmhpd_opp_low_svs>; 3418 #clock-cells = <1>; 3419 #reset-cells = <1>; 3420 #power-domain-cells = <1>; 3421 }; 3422 3423 mdss: display-subsystem@ae00000 { 3424 compatible = "qcom,sm8550-mdss"; 3425 reg = <0 0x0ae00000 0 0x1000>; 3426 reg-names = "mdss"; 3427 3428 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3429 interrupt-controller; 3430 #interrupt-cells = <1>; 3431 3432 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3433 <&gcc GCC_DISP_AHB_CLK>, 3434 <&gcc GCC_DISP_HF_AXI_CLK>, 3435 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3436 3437 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3438 3439 power-domains = <&dispcc MDSS_GDSC>; 3440 3441 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 3442 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3443 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3444 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3445 interconnect-names = "mdp0-mem", "cpu-cfg"; 3446 3447 iommus = <&apps_smmu 0x1c00 0x2>; 3448 3449 #address-cells = <2>; 3450 #size-cells = <2>; 3451 ranges; 3452 3453 status = "disabled"; 3454 3455 mdss_mdp: display-controller@ae01000 { 3456 compatible = "qcom,sm8550-dpu"; 3457 reg = <0 0x0ae01000 0 0x8f000>, 3458 <0 0x0aeb0000 0 0x3000>; 3459 reg-names = "mdp", "vbif"; 3460 3461 interrupt-parent = <&mdss>; 3462 interrupts = <0>; 3463 3464 clocks = <&gcc GCC_DISP_AHB_CLK>, 3465 <&gcc GCC_DISP_HF_AXI_CLK>, 3466 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3467 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3468 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3469 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3470 clock-names = "bus", 3471 "nrt_bus", 3472 "iface", 3473 "lut", 3474 "core", 3475 "vsync"; 3476 3477 power-domains = <&rpmhpd RPMHPD_MMCX>; 3478 3479 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3480 assigned-clock-rates = <19200000>; 3481 3482 operating-points-v2 = <&mdp_opp_table>; 3483 3484 ports { 3485 #address-cells = <1>; 3486 #size-cells = <0>; 3487 3488 port@0 { 3489 reg = <0>; 3490 dpu_intf1_out: endpoint { 3491 remote-endpoint = <&mdss_dsi0_in>; 3492 }; 3493 }; 3494 3495 port@1 { 3496 reg = <1>; 3497 dpu_intf2_out: endpoint { 3498 remote-endpoint = <&mdss_dsi1_in>; 3499 }; 3500 }; 3501 3502 port@2 { 3503 reg = <2>; 3504 dpu_intf0_out: endpoint { 3505 remote-endpoint = <&mdss_dp0_in>; 3506 }; 3507 }; 3508 }; 3509 3510 mdp_opp_table: opp-table { 3511 compatible = "operating-points-v2"; 3512 3513 opp-200000000 { 3514 opp-hz = /bits/ 64 <200000000>; 3515 required-opps = <&rpmhpd_opp_low_svs>; 3516 }; 3517 3518 opp-325000000 { 3519 opp-hz = /bits/ 64 <325000000>; 3520 required-opps = <&rpmhpd_opp_svs>; 3521 }; 3522 3523 opp-375000000 { 3524 opp-hz = /bits/ 64 <375000000>; 3525 required-opps = <&rpmhpd_opp_svs_l1>; 3526 }; 3527 3528 opp-514000000 { 3529 opp-hz = /bits/ 64 <514000000>; 3530 required-opps = <&rpmhpd_opp_nom>; 3531 }; 3532 }; 3533 }; 3534 3535 mdss_dp0: displayport-controller@ae90000 { 3536 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 3537 reg = <0 0xae90000 0 0x200>, 3538 <0 0xae90200 0 0x200>, 3539 <0 0xae90400 0 0xc00>, 3540 <0 0xae91000 0 0x400>, 3541 <0 0xae91400 0 0x400>; 3542 interrupt-parent = <&mdss>; 3543 interrupts = <12>; 3544 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3545 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3546 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3547 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3548 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3549 clock-names = "core_iface", 3550 "core_aux", 3551 "ctrl_link", 3552 "ctrl_link_iface", 3553 "stream_pixel"; 3554 3555 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3556 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3557 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3558 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3559 3560 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 3561 phy-names = "dp"; 3562 3563 #sound-dai-cells = <0>; 3564 3565 operating-points-v2 = <&dp_opp_table>; 3566 power-domains = <&rpmhpd RPMHPD_MMCX>; 3567 3568 status = "disabled"; 3569 3570 ports { 3571 #address-cells = <1>; 3572 #size-cells = <0>; 3573 3574 port@0 { 3575 reg = <0>; 3576 mdss_dp0_in: endpoint { 3577 remote-endpoint = <&dpu_intf0_out>; 3578 }; 3579 }; 3580 3581 port@1 { 3582 reg = <1>; 3583 mdss_dp0_out: endpoint { 3584 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 3585 }; 3586 }; 3587 }; 3588 3589 dp_opp_table: opp-table { 3590 compatible = "operating-points-v2"; 3591 3592 opp-162000000 { 3593 opp-hz = /bits/ 64 <162000000>; 3594 required-opps = <&rpmhpd_opp_low_svs_d1>; 3595 }; 3596 3597 opp-270000000 { 3598 opp-hz = /bits/ 64 <270000000>; 3599 required-opps = <&rpmhpd_opp_low_svs>; 3600 }; 3601 3602 opp-540000000 { 3603 opp-hz = /bits/ 64 <540000000>; 3604 required-opps = <&rpmhpd_opp_svs_l1>; 3605 }; 3606 3607 opp-810000000 { 3608 opp-hz = /bits/ 64 <810000000>; 3609 required-opps = <&rpmhpd_opp_nom>; 3610 }; 3611 }; 3612 }; 3613 3614 mdss_dsi0: dsi@ae94000 { 3615 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3616 reg = <0 0x0ae94000 0 0x400>; 3617 reg-names = "dsi_ctrl"; 3618 3619 interrupt-parent = <&mdss>; 3620 interrupts = <4>; 3621 3622 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3623 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3624 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3625 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3626 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3627 <&gcc GCC_DISP_HF_AXI_CLK>; 3628 clock-names = "byte", 3629 "byte_intf", 3630 "pixel", 3631 "core", 3632 "iface", 3633 "bus"; 3634 3635 power-domains = <&rpmhpd RPMHPD_MMCX>; 3636 3637 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3638 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3639 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3640 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 3641 3642 operating-points-v2 = <&mdss_dsi_opp_table>; 3643 3644 phys = <&mdss_dsi0_phy>; 3645 phy-names = "dsi"; 3646 3647 #address-cells = <1>; 3648 #size-cells = <0>; 3649 3650 status = "disabled"; 3651 3652 ports { 3653 #address-cells = <1>; 3654 #size-cells = <0>; 3655 3656 port@0 { 3657 reg = <0>; 3658 mdss_dsi0_in: endpoint { 3659 remote-endpoint = <&dpu_intf1_out>; 3660 }; 3661 }; 3662 3663 port@1 { 3664 reg = <1>; 3665 mdss_dsi0_out: endpoint { 3666 }; 3667 }; 3668 }; 3669 3670 mdss_dsi_opp_table: opp-table { 3671 compatible = "operating-points-v2"; 3672 3673 opp-187500000 { 3674 opp-hz = /bits/ 64 <187500000>; 3675 required-opps = <&rpmhpd_opp_low_svs>; 3676 }; 3677 3678 opp-300000000 { 3679 opp-hz = /bits/ 64 <300000000>; 3680 required-opps = <&rpmhpd_opp_svs>; 3681 }; 3682 3683 opp-358000000 { 3684 opp-hz = /bits/ 64 <358000000>; 3685 required-opps = <&rpmhpd_opp_svs_l1>; 3686 }; 3687 }; 3688 }; 3689 3690 mdss_dsi0_phy: phy@ae95000 { 3691 compatible = "qcom,sm8550-dsi-phy-4nm"; 3692 reg = <0 0x0ae95000 0 0x200>, 3693 <0 0x0ae95200 0 0x280>, 3694 <0 0x0ae95500 0 0x400>; 3695 reg-names = "dsi_phy", 3696 "dsi_phy_lane", 3697 "dsi_pll"; 3698 3699 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3700 <&rpmhcc RPMH_CXO_CLK>; 3701 clock-names = "iface", "ref"; 3702 3703 #clock-cells = <1>; 3704 #phy-cells = <0>; 3705 3706 status = "disabled"; 3707 }; 3708 3709 mdss_dsi1: dsi@ae96000 { 3710 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3711 reg = <0 0x0ae96000 0 0x400>; 3712 reg-names = "dsi_ctrl"; 3713 3714 interrupt-parent = <&mdss>; 3715 interrupts = <5>; 3716 3717 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3718 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3719 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3720 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3721 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3722 <&gcc GCC_DISP_HF_AXI_CLK>; 3723 clock-names = "byte", 3724 "byte_intf", 3725 "pixel", 3726 "core", 3727 "iface", 3728 "bus"; 3729 3730 power-domains = <&rpmhpd RPMHPD_MMCX>; 3731 3732 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3733 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3734 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3735 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 3736 3737 operating-points-v2 = <&mdss_dsi_opp_table>; 3738 3739 phys = <&mdss_dsi1_phy>; 3740 phy-names = "dsi"; 3741 3742 #address-cells = <1>; 3743 #size-cells = <0>; 3744 3745 status = "disabled"; 3746 3747 ports { 3748 #address-cells = <1>; 3749 #size-cells = <0>; 3750 3751 port@0 { 3752 reg = <0>; 3753 mdss_dsi1_in: endpoint { 3754 remote-endpoint = <&dpu_intf2_out>; 3755 }; 3756 }; 3757 3758 port@1 { 3759 reg = <1>; 3760 mdss_dsi1_out: endpoint { 3761 }; 3762 }; 3763 }; 3764 }; 3765 3766 mdss_dsi1_phy: phy@ae97000 { 3767 compatible = "qcom,sm8550-dsi-phy-4nm"; 3768 reg = <0 0x0ae97000 0 0x200>, 3769 <0 0x0ae97200 0 0x280>, 3770 <0 0x0ae97500 0 0x400>; 3771 reg-names = "dsi_phy", 3772 "dsi_phy_lane", 3773 "dsi_pll"; 3774 3775 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3776 <&rpmhcc RPMH_CXO_CLK>; 3777 clock-names = "iface", "ref"; 3778 3779 #clock-cells = <1>; 3780 #phy-cells = <0>; 3781 3782 status = "disabled"; 3783 }; 3784 }; 3785 3786 dispcc: clock-controller@af00000 { 3787 compatible = "qcom,sm8550-dispcc"; 3788 reg = <0 0x0af00000 0 0x20000>; 3789 clocks = <&bi_tcxo_div2>, 3790 <&bi_tcxo_ao_div2>, 3791 <&gcc GCC_DISP_AHB_CLK>, 3792 <&sleep_clk>, 3793 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3794 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3795 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3796 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 3797 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3798 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3799 <0>, /* dp1 */ 3800 <0>, 3801 <0>, /* dp2 */ 3802 <0>, 3803 <0>, /* dp3 */ 3804 <0>; 3805 power-domains = <&rpmhpd RPMHPD_MMCX>; 3806 required-opps = <&rpmhpd_opp_low_svs>; 3807 #clock-cells = <1>; 3808 #reset-cells = <1>; 3809 #power-domain-cells = <1>; 3810 }; 3811 3812 usb_1_hsphy: phy@88e3000 { 3813 compatible = "qcom,sm8550-snps-eusb2-phy"; 3814 reg = <0x0 0x088e3000 0x0 0x154>; 3815 #phy-cells = <0>; 3816 3817 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 3818 clock-names = "ref"; 3819 3820 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3821 3822 status = "disabled"; 3823 }; 3824 3825 usb_dp_qmpphy: phy@88e8000 { 3826 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 3827 reg = <0x0 0x088e8000 0x0 0x3000>; 3828 3829 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3830 <&rpmhcc RPMH_CXO_CLK>, 3831 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3832 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3833 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3834 3835 power-domains = <&gcc USB3_PHY_GDSC>; 3836 3837 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3838 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 3839 reset-names = "phy", "common"; 3840 3841 #clock-cells = <1>; 3842 #phy-cells = <1>; 3843 3844 orientation-switch; 3845 3846 status = "disabled"; 3847 3848 ports { 3849 #address-cells = <1>; 3850 #size-cells = <0>; 3851 3852 port@0 { 3853 reg = <0>; 3854 3855 usb_dp_qmpphy_out: endpoint { 3856 }; 3857 }; 3858 3859 port@1 { 3860 reg = <1>; 3861 3862 usb_dp_qmpphy_usb_ss_in: endpoint { 3863 remote-endpoint = <&usb_1_dwc3_ss>; 3864 }; 3865 }; 3866 3867 port@2 { 3868 reg = <2>; 3869 3870 usb_dp_qmpphy_dp_in: endpoint { 3871 remote-endpoint = <&mdss_dp0_out>; 3872 }; 3873 }; 3874 }; 3875 }; 3876 3877 usb_1: usb@a6f8800 { 3878 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 3879 reg = <0x0 0x0a6f8800 0x0 0x400>; 3880 #address-cells = <2>; 3881 #size-cells = <2>; 3882 ranges; 3883 3884 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3885 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3886 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3887 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3888 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3889 <&tcsr TCSR_USB3_CLKREF_EN>; 3890 clock-names = "cfg_noc", 3891 "core", 3892 "iface", 3893 "sleep", 3894 "mock_utmi", 3895 "xo"; 3896 3897 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3898 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3899 assigned-clock-rates = <19200000>, <200000000>; 3900 3901 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3902 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3903 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3904 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3905 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3906 interrupt-names = "pwr_event", 3907 "hs_phy_irq", 3908 "dp_hs_phy_irq", 3909 "dm_hs_phy_irq", 3910 "ss_phy_irq"; 3911 3912 power-domains = <&gcc USB30_PRIM_GDSC>; 3913 required-opps = <&rpmhpd_opp_nom>; 3914 3915 resets = <&gcc GCC_USB30_PRIM_BCR>; 3916 3917 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 3918 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3919 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3920 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 3921 interconnect-names = "usb-ddr", "apps-usb"; 3922 3923 status = "disabled"; 3924 3925 usb_1_dwc3: usb@a600000 { 3926 compatible = "snps,dwc3"; 3927 reg = <0x0 0x0a600000 0x0 0xcd00>; 3928 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3929 iommus = <&apps_smmu 0x40 0x0>; 3930 phys = <&usb_1_hsphy>, 3931 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 3932 phy-names = "usb2-phy", "usb3-phy"; 3933 snps,hird-threshold = /bits/ 8 <0x0>; 3934 snps,usb2-gadget-lpm-disable; 3935 snps,dis_u2_susphy_quirk; 3936 snps,dis_enblslpm_quirk; 3937 snps,dis-u1-entry-quirk; 3938 snps,dis-u2-entry-quirk; 3939 snps,is-utmi-l1-suspend; 3940 snps,usb3_lpm_capable; 3941 snps,usb2-lpm-disable; 3942 snps,has-lpm-erratum; 3943 tx-fifo-resize; 3944 dma-coherent; 3945 usb-role-switch; 3946 3947 ports { 3948 #address-cells = <1>; 3949 #size-cells = <0>; 3950 3951 port@0 { 3952 reg = <0>; 3953 3954 usb_1_dwc3_hs: endpoint { 3955 }; 3956 }; 3957 3958 port@1 { 3959 reg = <1>; 3960 3961 usb_1_dwc3_ss: endpoint { 3962 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 3963 }; 3964 }; 3965 }; 3966 }; 3967 }; 3968 3969 pdc: interrupt-controller@b220000 { 3970 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 3971 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3972 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3973 <125 63 1>, <126 716 12>, 3974 <138 251 5>; 3975 #interrupt-cells = <2>; 3976 interrupt-parent = <&intc>; 3977 interrupt-controller; 3978 }; 3979 3980 tsens0: thermal-sensor@c271000 { 3981 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3982 reg = <0 0x0c271000 0 0x1000>, /* TM */ 3983 <0 0x0c222000 0 0x1000>; /* SROT */ 3984 #qcom,sensors = <16>; 3985 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3986 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 3987 interrupt-names = "uplow", "critical"; 3988 #thermal-sensor-cells = <1>; 3989 }; 3990 3991 tsens1: thermal-sensor@c272000 { 3992 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3993 reg = <0 0x0c272000 0 0x1000>, /* TM */ 3994 <0 0x0c223000 0 0x1000>; /* SROT */ 3995 #qcom,sensors = <16>; 3996 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3997 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 3998 interrupt-names = "uplow", "critical"; 3999 #thermal-sensor-cells = <1>; 4000 }; 4001 4002 tsens2: thermal-sensor@c273000 { 4003 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 4004 reg = <0 0x0c273000 0 0x1000>, /* TM */ 4005 <0 0x0c224000 0 0x1000>; /* SROT */ 4006 #qcom,sensors = <16>; 4007 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 4008 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 4009 interrupt-names = "uplow", "critical"; 4010 #thermal-sensor-cells = <1>; 4011 }; 4012 4013 aoss_qmp: power-management@c300000 { 4014 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 4015 reg = <0 0x0c300000 0 0x400>; 4016 interrupt-parent = <&ipcc>; 4017 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4018 IRQ_TYPE_EDGE_RISING>; 4019 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4020 4021 #clock-cells = <0>; 4022 }; 4023 4024 sram@c3f0000 { 4025 compatible = "qcom,rpmh-stats"; 4026 reg = <0 0x0c3f0000 0 0x400>; 4027 }; 4028 4029 spmi_bus: spmi@c400000 { 4030 compatible = "qcom,spmi-pmic-arb"; 4031 reg = <0 0x0c400000 0 0x3000>, 4032 <0 0x0c500000 0 0x400000>, 4033 <0 0x0c440000 0 0x80000>, 4034 <0 0x0c4c0000 0 0x20000>, 4035 <0 0x0c42d000 0 0x4000>; 4036 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4037 interrupt-names = "periph_irq"; 4038 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4039 qcom,ee = <0>; 4040 qcom,channel = <0>; 4041 qcom,bus-id = <0>; 4042 #address-cells = <2>; 4043 #size-cells = <0>; 4044 interrupt-controller; 4045 #interrupt-cells = <4>; 4046 }; 4047 4048 tlmm: pinctrl@f100000 { 4049 compatible = "qcom,sm8550-tlmm"; 4050 reg = <0 0x0f100000 0 0x300000>; 4051 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4052 gpio-controller; 4053 #gpio-cells = <2>; 4054 interrupt-controller; 4055 #interrupt-cells = <2>; 4056 gpio-ranges = <&tlmm 0 0 211>; 4057 wakeup-parent = <&pdc>; 4058 4059 cci0_0_default: cci0-0-default-state { 4060 sda-pins { 4061 pins = "gpio110"; 4062 function = "cci_i2c_sda"; 4063 drive-strength = <2>; 4064 bias-pull-up = <2200>; 4065 }; 4066 4067 scl-pins { 4068 pins = "gpio111"; 4069 function = "cci_i2c_scl"; 4070 drive-strength = <2>; 4071 bias-pull-up = <2200>; 4072 }; 4073 }; 4074 4075 cci0_0_sleep: cci0-0-sleep-state { 4076 sda-pins { 4077 pins = "gpio110"; 4078 function = "cci_i2c_sda"; 4079 drive-strength = <2>; 4080 bias-pull-down; 4081 }; 4082 4083 scl-pins { 4084 pins = "gpio111"; 4085 function = "cci_i2c_scl"; 4086 drive-strength = <2>; 4087 bias-pull-down; 4088 }; 4089 }; 4090 4091 cci0_1_default: cci0-1-default-state { 4092 sda-pins { 4093 pins = "gpio112"; 4094 function = "cci_i2c_sda"; 4095 drive-strength = <2>; 4096 bias-pull-up = <2200>; 4097 }; 4098 4099 scl-pins { 4100 pins = "gpio113"; 4101 function = "cci_i2c_scl"; 4102 drive-strength = <2>; 4103 bias-pull-up = <2200>; 4104 }; 4105 }; 4106 4107 cci0_1_sleep: cci0-1-sleep-state { 4108 sda-pins { 4109 pins = "gpio112"; 4110 function = "cci_i2c_sda"; 4111 drive-strength = <2>; 4112 bias-pull-down; 4113 }; 4114 4115 scl-pins { 4116 pins = "gpio113"; 4117 function = "cci_i2c_scl"; 4118 drive-strength = <2>; 4119 bias-pull-down; 4120 }; 4121 }; 4122 4123 cci1_0_default: cci1-0-default-state { 4124 sda-pins { 4125 pins = "gpio114"; 4126 function = "cci_i2c_sda"; 4127 drive-strength = <2>; 4128 bias-pull-up = <2200>; 4129 }; 4130 4131 scl-pins { 4132 pins = "gpio115"; 4133 function = "cci_i2c_scl"; 4134 drive-strength = <2>; 4135 bias-pull-up = <2200>; 4136 }; 4137 }; 4138 4139 cci1_0_sleep: cci1-0-sleep-state { 4140 sda-pins { 4141 pins = "gpio114"; 4142 function = "cci_i2c_sda"; 4143 drive-strength = <2>; 4144 bias-pull-down; 4145 }; 4146 4147 scl-pins { 4148 pins = "gpio115"; 4149 function = "cci_i2c_scl"; 4150 drive-strength = <2>; 4151 bias-pull-down; 4152 }; 4153 }; 4154 4155 cci2_0_default: cci2-0-default-state { 4156 sda-pins { 4157 pins = "gpio74"; 4158 function = "cci_i2c_sda"; 4159 drive-strength = <2>; 4160 bias-pull-up = <2200>; 4161 }; 4162 4163 scl-pins { 4164 pins = "gpio75"; 4165 function = "cci_i2c_scl"; 4166 drive-strength = <2>; 4167 bias-pull-up = <2200>; 4168 }; 4169 }; 4170 4171 cci2_0_sleep: cci2-0-sleep-state { 4172 sda-pins { 4173 pins = "gpio74"; 4174 function = "cci_i2c_sda"; 4175 drive-strength = <2>; 4176 bias-pull-down; 4177 }; 4178 4179 scl-pins { 4180 pins = "gpio75"; 4181 function = "cci_i2c_scl"; 4182 drive-strength = <2>; 4183 bias-pull-down; 4184 }; 4185 }; 4186 4187 cci2_1_default: cci2-1-default-state { 4188 sda-pins { 4189 pins = "gpio0"; 4190 function = "cci_i2c_sda"; 4191 drive-strength = <2>; 4192 bias-pull-up = <2200>; 4193 }; 4194 4195 scl-pins { 4196 pins = "gpio1"; 4197 function = "cci_i2c_scl"; 4198 drive-strength = <2>; 4199 bias-pull-up = <2200>; 4200 }; 4201 }; 4202 4203 cci2_1_sleep: cci2-1-sleep-state { 4204 sda-pins { 4205 pins = "gpio0"; 4206 function = "cci_i2c_sda"; 4207 drive-strength = <2>; 4208 bias-pull-down; 4209 }; 4210 4211 scl-pins { 4212 pins = "gpio1"; 4213 function = "cci_i2c_scl"; 4214 drive-strength = <2>; 4215 bias-pull-down; 4216 }; 4217 }; 4218 4219 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 4220 /* SDA, SCL */ 4221 pins = "gpio16", "gpio17"; 4222 function = "i2chub0_se0"; 4223 drive-strength = <2>; 4224 bias-pull-up; 4225 }; 4226 4227 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 4228 /* SDA, SCL */ 4229 pins = "gpio18", "gpio19"; 4230 function = "i2chub0_se1"; 4231 drive-strength = <2>; 4232 bias-pull-up; 4233 }; 4234 4235 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 4236 /* SDA, SCL */ 4237 pins = "gpio20", "gpio21"; 4238 function = "i2chub0_se2"; 4239 drive-strength = <2>; 4240 bias-pull-up; 4241 }; 4242 4243 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 4244 /* SDA, SCL */ 4245 pins = "gpio22", "gpio23"; 4246 function = "i2chub0_se3"; 4247 drive-strength = <2>; 4248 bias-pull-up; 4249 }; 4250 4251 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 4252 /* SDA, SCL */ 4253 pins = "gpio4", "gpio5"; 4254 function = "i2chub0_se4"; 4255 drive-strength = <2>; 4256 bias-pull-up; 4257 }; 4258 4259 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 4260 /* SDA, SCL */ 4261 pins = "gpio6", "gpio7"; 4262 function = "i2chub0_se5"; 4263 drive-strength = <2>; 4264 bias-pull-up; 4265 }; 4266 4267 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 4268 /* SDA, SCL */ 4269 pins = "gpio8", "gpio9"; 4270 function = "i2chub0_se6"; 4271 drive-strength = <2>; 4272 bias-pull-up; 4273 }; 4274 4275 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 4276 /* SDA, SCL */ 4277 pins = "gpio10", "gpio11"; 4278 function = "i2chub0_se7"; 4279 drive-strength = <2>; 4280 bias-pull-up; 4281 }; 4282 4283 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 4284 /* SDA, SCL */ 4285 pins = "gpio206", "gpio207"; 4286 function = "i2chub0_se8"; 4287 drive-strength = <2>; 4288 bias-pull-up; 4289 }; 4290 4291 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 4292 /* SDA, SCL */ 4293 pins = "gpio84", "gpio85"; 4294 function = "i2chub0_se9"; 4295 drive-strength = <2>; 4296 bias-pull-up; 4297 }; 4298 4299 pcie0_default_state: pcie0-default-state { 4300 perst-pins { 4301 pins = "gpio94"; 4302 function = "gpio"; 4303 drive-strength = <2>; 4304 bias-pull-down; 4305 }; 4306 4307 clkreq-pins { 4308 pins = "gpio95"; 4309 function = "pcie0_clk_req_n"; 4310 drive-strength = <2>; 4311 bias-pull-up; 4312 }; 4313 4314 wake-pins { 4315 pins = "gpio96"; 4316 function = "gpio"; 4317 drive-strength = <2>; 4318 bias-pull-up; 4319 }; 4320 }; 4321 4322 pcie1_default_state: pcie1-default-state { 4323 perst-pins { 4324 pins = "gpio97"; 4325 function = "gpio"; 4326 drive-strength = <2>; 4327 bias-pull-down; 4328 }; 4329 4330 clkreq-pins { 4331 pins = "gpio98"; 4332 function = "pcie1_clk_req_n"; 4333 drive-strength = <2>; 4334 bias-pull-up; 4335 }; 4336 4337 wake-pins { 4338 pins = "gpio99"; 4339 function = "gpio"; 4340 drive-strength = <2>; 4341 bias-pull-up; 4342 }; 4343 }; 4344 4345 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4346 /* SDA, SCL */ 4347 pins = "gpio28", "gpio29"; 4348 function = "qup1_se0"; 4349 drive-strength = <2>; 4350 bias-pull-up = <2200>; 4351 }; 4352 4353 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4354 /* SDA, SCL */ 4355 pins = "gpio32", "gpio33"; 4356 function = "qup1_se1"; 4357 drive-strength = <2>; 4358 bias-pull-up = <2200>; 4359 }; 4360 4361 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4362 /* SDA, SCL */ 4363 pins = "gpio36", "gpio37"; 4364 function = "qup1_se2"; 4365 drive-strength = <2>; 4366 bias-pull-up = <2200>; 4367 }; 4368 4369 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4370 /* SDA, SCL */ 4371 pins = "gpio40", "gpio41"; 4372 function = "qup1_se3"; 4373 drive-strength = <2>; 4374 bias-pull-up = <2200>; 4375 }; 4376 4377 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4378 /* SDA, SCL */ 4379 pins = "gpio44", "gpio45"; 4380 function = "qup1_se4"; 4381 drive-strength = <2>; 4382 bias-pull-up = <2200>; 4383 }; 4384 4385 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4386 /* SDA, SCL */ 4387 pins = "gpio52", "gpio53"; 4388 function = "qup1_se5"; 4389 drive-strength = <2>; 4390 bias-pull-up = <2200>; 4391 }; 4392 4393 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4394 /* SDA, SCL */ 4395 pins = "gpio48", "gpio49"; 4396 function = "qup1_se6"; 4397 drive-strength = <2>; 4398 bias-pull-up = <2200>; 4399 }; 4400 4401 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4402 scl-pins { 4403 pins = "gpio57"; 4404 function = "qup2_se0_l1_mira"; 4405 drive-strength = <2>; 4406 bias-pull-up = <2200>; 4407 }; 4408 4409 sda-pins { 4410 pins = "gpio56"; 4411 function = "qup2_se0_l0_mira"; 4412 drive-strength = <2>; 4413 bias-pull-up = <2200>; 4414 }; 4415 }; 4416 4417 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4418 /* SDA, SCL */ 4419 pins = "gpio60", "gpio61"; 4420 function = "qup2_se1"; 4421 drive-strength = <2>; 4422 bias-pull-up = <2200>; 4423 }; 4424 4425 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4426 /* SDA, SCL */ 4427 pins = "gpio64", "gpio65"; 4428 function = "qup2_se2"; 4429 drive-strength = <2>; 4430 bias-pull-up = <2200>; 4431 }; 4432 4433 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4434 /* SDA, SCL */ 4435 pins = "gpio68", "gpio69"; 4436 function = "qup2_se3"; 4437 drive-strength = <2>; 4438 bias-pull-up = <2200>; 4439 }; 4440 4441 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4442 /* SDA, SCL */ 4443 pins = "gpio2", "gpio3"; 4444 function = "qup2_se4"; 4445 drive-strength = <2>; 4446 bias-pull-up = <2200>; 4447 }; 4448 4449 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4450 /* SDA, SCL */ 4451 pins = "gpio80", "gpio81"; 4452 function = "qup2_se5"; 4453 drive-strength = <2>; 4454 bias-pull-up = <2200>; 4455 }; 4456 4457 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4458 /* SDA, SCL */ 4459 pins = "gpio72", "gpio106"; 4460 function = "qup2_se7"; 4461 drive-strength = <2>; 4462 bias-pull-up = <2200>; 4463 }; 4464 4465 qup_spi0_cs: qup-spi0-cs-state { 4466 pins = "gpio31"; 4467 function = "qup1_se0"; 4468 drive-strength = <6>; 4469 bias-disable; 4470 }; 4471 4472 qup_spi0_data_clk: qup-spi0-data-clk-state { 4473 /* MISO, MOSI, CLK */ 4474 pins = "gpio28", "gpio29", "gpio30"; 4475 function = "qup1_se0"; 4476 drive-strength = <6>; 4477 bias-disable; 4478 }; 4479 4480 qup_spi1_cs: qup-spi1-cs-state { 4481 pins = "gpio35"; 4482 function = "qup1_se1"; 4483 drive-strength = <6>; 4484 bias-disable; 4485 }; 4486 4487 qup_spi1_data_clk: qup-spi1-data-clk-state { 4488 /* MISO, MOSI, CLK */ 4489 pins = "gpio32", "gpio33", "gpio34"; 4490 function = "qup1_se1"; 4491 drive-strength = <6>; 4492 bias-disable; 4493 }; 4494 4495 qup_spi2_cs: qup-spi2-cs-state { 4496 pins = "gpio39"; 4497 function = "qup1_se2"; 4498 drive-strength = <6>; 4499 bias-disable; 4500 }; 4501 4502 qup_spi2_data_clk: qup-spi2-data-clk-state { 4503 /* MISO, MOSI, CLK */ 4504 pins = "gpio36", "gpio37", "gpio38"; 4505 function = "qup1_se2"; 4506 drive-strength = <6>; 4507 bias-disable; 4508 }; 4509 4510 qup_spi3_cs: qup-spi3-cs-state { 4511 pins = "gpio43"; 4512 function = "qup1_se3"; 4513 drive-strength = <6>; 4514 bias-disable; 4515 }; 4516 4517 qup_spi3_data_clk: qup-spi3-data-clk-state { 4518 /* MISO, MOSI, CLK */ 4519 pins = "gpio40", "gpio41", "gpio42"; 4520 function = "qup1_se3"; 4521 drive-strength = <6>; 4522 bias-disable; 4523 }; 4524 4525 qup_spi4_cs: qup-spi4-cs-state { 4526 pins = "gpio47"; 4527 function = "qup1_se4"; 4528 drive-strength = <6>; 4529 bias-disable; 4530 }; 4531 4532 qup_spi4_data_clk: qup-spi4-data-clk-state { 4533 /* MISO, MOSI, CLK */ 4534 pins = "gpio44", "gpio45", "gpio46"; 4535 function = "qup1_se4"; 4536 drive-strength = <6>; 4537 bias-disable; 4538 }; 4539 4540 qup_spi5_cs: qup-spi5-cs-state { 4541 pins = "gpio55"; 4542 function = "qup1_se5"; 4543 drive-strength = <6>; 4544 bias-disable; 4545 }; 4546 4547 qup_spi5_data_clk: qup-spi5-data-clk-state { 4548 /* MISO, MOSI, CLK */ 4549 pins = "gpio52", "gpio53", "gpio54"; 4550 function = "qup1_se5"; 4551 drive-strength = <6>; 4552 bias-disable; 4553 }; 4554 4555 qup_spi6_cs: qup-spi6-cs-state { 4556 pins = "gpio51"; 4557 function = "qup1_se6"; 4558 drive-strength = <6>; 4559 bias-disable; 4560 }; 4561 4562 qup_spi6_data_clk: qup-spi6-data-clk-state { 4563 /* MISO, MOSI, CLK */ 4564 pins = "gpio48", "gpio49", "gpio50"; 4565 function = "qup1_se6"; 4566 drive-strength = <6>; 4567 bias-disable; 4568 }; 4569 4570 qup_spi8_cs: qup-spi8-cs-state { 4571 pins = "gpio59"; 4572 function = "qup2_se0_l3_mira"; 4573 drive-strength = <6>; 4574 bias-disable; 4575 }; 4576 4577 qup_spi8_data_clk: qup-spi8-data-clk-state { 4578 /* MISO, MOSI, CLK */ 4579 pins = "gpio56", "gpio57", "gpio58"; 4580 function = "qup2_se0_l2_mira"; 4581 drive-strength = <6>; 4582 bias-disable; 4583 }; 4584 4585 qup_spi9_cs: qup-spi9-cs-state { 4586 pins = "gpio63"; 4587 function = "qup2_se1"; 4588 drive-strength = <6>; 4589 bias-disable; 4590 }; 4591 4592 qup_spi9_data_clk: qup-spi9-data-clk-state { 4593 /* MISO, MOSI, CLK */ 4594 pins = "gpio60", "gpio61", "gpio62"; 4595 function = "qup2_se1"; 4596 drive-strength = <6>; 4597 bias-disable; 4598 }; 4599 4600 qup_spi10_cs: qup-spi10-cs-state { 4601 pins = "gpio67"; 4602 function = "qup2_se2"; 4603 drive-strength = <6>; 4604 bias-disable; 4605 }; 4606 4607 qup_spi10_data_clk: qup-spi10-data-clk-state { 4608 /* MISO, MOSI, CLK */ 4609 pins = "gpio64", "gpio65", "gpio66"; 4610 function = "qup2_se2"; 4611 drive-strength = <6>; 4612 bias-disable; 4613 }; 4614 4615 qup_spi11_cs: qup-spi11-cs-state { 4616 pins = "gpio71"; 4617 function = "qup2_se3"; 4618 drive-strength = <6>; 4619 bias-disable; 4620 }; 4621 4622 qup_spi11_data_clk: qup-spi11-data-clk-state { 4623 /* MISO, MOSI, CLK */ 4624 pins = "gpio68", "gpio69", "gpio70"; 4625 function = "qup2_se3"; 4626 drive-strength = <6>; 4627 bias-disable; 4628 }; 4629 4630 qup_spi12_cs: qup-spi12-cs-state { 4631 pins = "gpio119"; 4632 function = "qup2_se4"; 4633 drive-strength = <6>; 4634 bias-disable; 4635 }; 4636 4637 qup_spi12_data_clk: qup-spi12-data-clk-state { 4638 /* MISO, MOSI, CLK */ 4639 pins = "gpio2", "gpio3", "gpio118"; 4640 function = "qup2_se4"; 4641 drive-strength = <6>; 4642 bias-disable; 4643 }; 4644 4645 qup_spi13_cs: qup-spi13-cs-state { 4646 pins = "gpio83"; 4647 function = "qup2_se5"; 4648 drive-strength = <6>; 4649 bias-disable; 4650 }; 4651 4652 qup_spi13_data_clk: qup-spi13-data-clk-state { 4653 /* MISO, MOSI, CLK */ 4654 pins = "gpio80", "gpio81", "gpio82"; 4655 function = "qup2_se5"; 4656 drive-strength = <6>; 4657 bias-disable; 4658 }; 4659 4660 qup_spi15_cs: qup-spi15-cs-state { 4661 pins = "gpio75"; 4662 function = "qup2_se7"; 4663 drive-strength = <6>; 4664 bias-disable; 4665 }; 4666 4667 qup_spi15_data_clk: qup-spi15-data-clk-state { 4668 /* MISO, MOSI, CLK */ 4669 pins = "gpio72", "gpio106", "gpio74"; 4670 function = "qup2_se7"; 4671 drive-strength = <6>; 4672 bias-disable; 4673 }; 4674 4675 qup_uart7_default: qup-uart7-default-state { 4676 /* TX, RX */ 4677 pins = "gpio26", "gpio27"; 4678 function = "qup1_se7"; 4679 drive-strength = <2>; 4680 bias-disable; 4681 }; 4682 4683 qup_uart14_default: qup-uart14-default-state { 4684 /* TX, RX */ 4685 pins = "gpio78", "gpio79"; 4686 function = "qup2_se6"; 4687 drive-strength = <2>; 4688 bias-pull-up; 4689 }; 4690 4691 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 4692 /* CTS, RTS */ 4693 pins = "gpio76", "gpio77"; 4694 function = "qup2_se6"; 4695 drive-strength = <2>; 4696 bias-pull-down; 4697 }; 4698 4699 sdc2_sleep: sdc2-sleep-state { 4700 clk-pins { 4701 pins = "sdc2_clk"; 4702 bias-disable; 4703 drive-strength = <2>; 4704 }; 4705 4706 cmd-pins { 4707 pins = "sdc2_cmd"; 4708 bias-pull-up; 4709 drive-strength = <2>; 4710 }; 4711 4712 data-pins { 4713 pins = "sdc2_data"; 4714 bias-pull-up; 4715 drive-strength = <2>; 4716 }; 4717 }; 4718 4719 sdc2_default: sdc2-default-state { 4720 clk-pins { 4721 pins = "sdc2_clk"; 4722 bias-disable; 4723 drive-strength = <16>; 4724 }; 4725 4726 cmd-pins { 4727 pins = "sdc2_cmd"; 4728 bias-pull-up; 4729 drive-strength = <10>; 4730 }; 4731 4732 data-pins { 4733 pins = "sdc2_data"; 4734 bias-pull-up; 4735 drive-strength = <10>; 4736 }; 4737 }; 4738 }; 4739 4740 apps_smmu: iommu@15000000 { 4741 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4742 reg = <0 0x15000000 0 0x100000>; 4743 #iommu-cells = <2>; 4744 #global-interrupts = <1>; 4745 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4746 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4747 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4748 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4749 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4750 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4751 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4752 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4753 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4754 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4755 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4756 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4757 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4758 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4759 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4760 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4761 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4762 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4763 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4764 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4765 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4766 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4767 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4768 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4769 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4770 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4771 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4772 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4773 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4774 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4775 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4776 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4777 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4778 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4779 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4780 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4781 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4782 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4783 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4784 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4785 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4786 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4787 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4788 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4789 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4790 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4791 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4792 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4793 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4794 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4795 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4796 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4797 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4798 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4799 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4800 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4801 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4802 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4803 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4804 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4805 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4806 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4807 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4808 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4809 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4810 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4811 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4812 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4813 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4814 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4815 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4816 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4817 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4818 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4819 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4820 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4821 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4822 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4823 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4824 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4825 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4826 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4827 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4828 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4829 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4830 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4831 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4832 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4833 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4834 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4835 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4836 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4837 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4838 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4839 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4840 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4841 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 4842 dma-coherent; 4843 }; 4844 4845 intc: interrupt-controller@17100000 { 4846 compatible = "arm,gic-v3"; 4847 reg = <0 0x17100000 0 0x10000>, /* GICD */ 4848 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 4849 ranges; 4850 #interrupt-cells = <3>; 4851 interrupt-controller; 4852 #redistributor-regions = <1>; 4853 redistributor-stride = <0 0x40000>; 4854 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4855 #address-cells = <2>; 4856 #size-cells = <2>; 4857 4858 gic_its: msi-controller@17140000 { 4859 compatible = "arm,gic-v3-its"; 4860 reg = <0 0x17140000 0 0x20000>; 4861 msi-controller; 4862 #msi-cells = <1>; 4863 }; 4864 }; 4865 4866 timer@17420000 { 4867 compatible = "arm,armv7-timer-mem"; 4868 reg = <0 0x17420000 0 0x1000>; 4869 ranges = <0 0 0 0x20000000>; 4870 #address-cells = <1>; 4871 #size-cells = <1>; 4872 4873 frame@17421000 { 4874 reg = <0x17421000 0x1000>, 4875 <0x17422000 0x1000>; 4876 frame-number = <0>; 4877 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4878 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4879 }; 4880 4881 frame@17423000 { 4882 reg = <0x17423000 0x1000>; 4883 frame-number = <1>; 4884 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4885 status = "disabled"; 4886 }; 4887 4888 frame@17425000 { 4889 reg = <0x17425000 0x1000>; 4890 frame-number = <2>; 4891 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4892 status = "disabled"; 4893 }; 4894 4895 frame@17427000 { 4896 reg = <0x17427000 0x1000>; 4897 frame-number = <3>; 4898 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4899 status = "disabled"; 4900 }; 4901 4902 frame@17429000 { 4903 reg = <0x17429000 0x1000>; 4904 frame-number = <4>; 4905 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4906 status = "disabled"; 4907 }; 4908 4909 frame@1742b000 { 4910 reg = <0x1742b000 0x1000>; 4911 frame-number = <5>; 4912 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4913 status = "disabled"; 4914 }; 4915 4916 frame@1742d000 { 4917 reg = <0x1742d000 0x1000>; 4918 frame-number = <6>; 4919 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4920 status = "disabled"; 4921 }; 4922 }; 4923 4924 apps_rsc: rsc@17a00000 { 4925 label = "apps_rsc"; 4926 compatible = "qcom,rpmh-rsc"; 4927 reg = <0 0x17a00000 0 0x10000>, 4928 <0 0x17a10000 0 0x10000>, 4929 <0 0x17a20000 0 0x10000>, 4930 <0 0x17a30000 0 0x10000>; 4931 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 4932 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4933 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4934 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4935 qcom,tcs-offset = <0xd00>; 4936 qcom,drv-id = <2>; 4937 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4938 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4939 power-domains = <&cluster_pd>; 4940 4941 apps_bcm_voter: bcm-voter { 4942 compatible = "qcom,bcm-voter"; 4943 }; 4944 4945 rpmhcc: clock-controller { 4946 compatible = "qcom,sm8550-rpmh-clk"; 4947 #clock-cells = <1>; 4948 clock-names = "xo"; 4949 clocks = <&xo_board>; 4950 }; 4951 4952 rpmhpd: power-controller { 4953 compatible = "qcom,sm8550-rpmhpd"; 4954 #power-domain-cells = <1>; 4955 operating-points-v2 = <&rpmhpd_opp_table>; 4956 4957 rpmhpd_opp_table: opp-table { 4958 compatible = "operating-points-v2"; 4959 4960 rpmhpd_opp_ret: opp-16 { 4961 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4962 }; 4963 4964 rpmhpd_opp_min_svs: opp-48 { 4965 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4966 }; 4967 4968 rpmhpd_opp_low_svs_d2: opp-52 { 4969 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 4970 }; 4971 4972 rpmhpd_opp_low_svs_d1: opp-56 { 4973 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4974 }; 4975 4976 rpmhpd_opp_low_svs_d0: opp-60 { 4977 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 4978 }; 4979 4980 rpmhpd_opp_low_svs: opp-64 { 4981 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4982 }; 4983 4984 rpmhpd_opp_low_svs_l1: opp-80 { 4985 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4986 }; 4987 4988 rpmhpd_opp_svs: opp-128 { 4989 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4990 }; 4991 4992 rpmhpd_opp_svs_l0: opp-144 { 4993 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4994 }; 4995 4996 rpmhpd_opp_svs_l1: opp-192 { 4997 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4998 }; 4999 5000 rpmhpd_opp_nom: opp-256 { 5001 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5002 }; 5003 5004 rpmhpd_opp_nom_l1: opp-320 { 5005 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5006 }; 5007 5008 rpmhpd_opp_nom_l2: opp-336 { 5009 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5010 }; 5011 5012 rpmhpd_opp_turbo: opp-384 { 5013 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5014 }; 5015 5016 rpmhpd_opp_turbo_l1: opp-416 { 5017 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5018 }; 5019 }; 5020 }; 5021 }; 5022 5023 cpufreq_hw: cpufreq@17d91000 { 5024 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 5025 reg = <0 0x17d91000 0 0x1000>, 5026 <0 0x17d92000 0 0x1000>, 5027 <0 0x17d93000 0 0x1000>; 5028 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 5029 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 5030 clock-names = "xo", "alternate"; 5031 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5032 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5033 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5034 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5035 #freq-domain-cells = <1>; 5036 #clock-cells = <1>; 5037 }; 5038 5039 pmu@24091000 { 5040 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 5041 reg = <0 0x24091000 0 0x1000>; 5042 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 5043 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 5044 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5045 5046 operating-points-v2 = <&llcc_bwmon_opp_table>; 5047 5048 llcc_bwmon_opp_table: opp-table { 5049 compatible = "operating-points-v2"; 5050 5051 opp-0 { 5052 opp-peak-kBps = <2086000>; 5053 }; 5054 5055 opp-1 { 5056 opp-peak-kBps = <2929000>; 5057 }; 5058 5059 opp-2 { 5060 opp-peak-kBps = <5931000>; 5061 }; 5062 5063 opp-3 { 5064 opp-peak-kBps = <6515000>; 5065 }; 5066 5067 opp-4 { 5068 opp-peak-kBps = <7980000>; 5069 }; 5070 5071 opp-5 { 5072 opp-peak-kBps = <10437000>; 5073 }; 5074 5075 opp-6 { 5076 opp-peak-kBps = <12157000>; 5077 }; 5078 5079 opp-7 { 5080 opp-peak-kBps = <14060000>; 5081 }; 5082 5083 opp-8 { 5084 opp-peak-kBps = <16113000>; 5085 }; 5086 }; 5087 }; 5088 5089 pmu@240b6400 { 5090 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 5091 reg = <0 0x240b6400 0 0x600>; 5092 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5093 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5094 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5095 5096 operating-points-v2 = <&cpu_bwmon_opp_table>; 5097 5098 cpu_bwmon_opp_table: opp-table { 5099 compatible = "operating-points-v2"; 5100 5101 opp-0 { 5102 opp-peak-kBps = <4577000>; 5103 }; 5104 5105 opp-1 { 5106 opp-peak-kBps = <7110000>; 5107 }; 5108 5109 opp-2 { 5110 opp-peak-kBps = <9155000>; 5111 }; 5112 5113 opp-3 { 5114 opp-peak-kBps = <12298000>; 5115 }; 5116 5117 opp-4 { 5118 opp-peak-kBps = <14236000>; 5119 }; 5120 5121 opp-5 { 5122 opp-peak-kBps = <16265000>; 5123 }; 5124 }; 5125 }; 5126 5127 gem_noc: interconnect@24100000 { 5128 compatible = "qcom,sm8550-gem-noc"; 5129 reg = <0 0x24100000 0 0xbb800>; 5130 #interconnect-cells = <2>; 5131 qcom,bcm-voters = <&apps_bcm_voter>; 5132 }; 5133 5134 system-cache-controller@25000000 { 5135 compatible = "qcom,sm8550-llcc"; 5136 reg = <0 0x25000000 0 0x200000>, 5137 <0 0x25200000 0 0x200000>, 5138 <0 0x25400000 0 0x200000>, 5139 <0 0x25600000 0 0x200000>, 5140 <0 0x25800000 0 0x200000>, 5141 <0 0x25a00000 0 0x200000>; 5142 reg-names = "llcc0_base", 5143 "llcc1_base", 5144 "llcc2_base", 5145 "llcc3_base", 5146 "llcc_broadcast_base", 5147 "llcc_broadcast_and_base"; 5148 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 5149 }; 5150 5151 nsp_noc: interconnect@320c0000 { 5152 compatible = "qcom,sm8550-nsp-noc"; 5153 reg = <0 0x320c0000 0 0xe080>; 5154 #interconnect-cells = <2>; 5155 qcom,bcm-voters = <&apps_bcm_voter>; 5156 }; 5157 5158 remoteproc_cdsp: remoteproc@32300000 { 5159 compatible = "qcom,sm8550-cdsp-pas"; 5160 reg = <0x0 0x32300000 0x0 0x10000>; 5161 5162 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5163 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 5164 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 5165 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 5166 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 5167 interrupt-names = "wdog", "fatal", "ready", 5168 "handover", "stop-ack"; 5169 5170 clocks = <&rpmhcc RPMH_CXO_CLK>; 5171 clock-names = "xo"; 5172 5173 power-domains = <&rpmhpd RPMHPD_CX>, 5174 <&rpmhpd RPMHPD_MXC>, 5175 <&rpmhpd RPMHPD_NSP>; 5176 power-domain-names = "cx", "mxc", "nsp"; 5177 5178 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 5179 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5180 5181 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 5182 5183 qcom,qmp = <&aoss_qmp>; 5184 5185 qcom,smem-states = <&smp2p_cdsp_out 0>; 5186 qcom,smem-state-names = "stop"; 5187 5188 status = "disabled"; 5189 5190 glink-edge { 5191 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5192 IPCC_MPROC_SIGNAL_GLINK_QMP 5193 IRQ_TYPE_EDGE_RISING>; 5194 mboxes = <&ipcc IPCC_CLIENT_CDSP 5195 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5196 5197 label = "cdsp"; 5198 qcom,remote-pid = <5>; 5199 5200 fastrpc { 5201 compatible = "qcom,fastrpc"; 5202 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5203 label = "cdsp"; 5204 qcom,non-secure-domain; 5205 #address-cells = <1>; 5206 #size-cells = <0>; 5207 5208 compute-cb@1 { 5209 compatible = "qcom,fastrpc-compute-cb"; 5210 reg = <1>; 5211 iommus = <&apps_smmu 0x1961 0x0>, 5212 <&apps_smmu 0x0c01 0x20>, 5213 <&apps_smmu 0x19c1 0x10>; 5214 dma-coherent; 5215 }; 5216 5217 compute-cb@2 { 5218 compatible = "qcom,fastrpc-compute-cb"; 5219 reg = <2>; 5220 iommus = <&apps_smmu 0x1962 0x0>, 5221 <&apps_smmu 0x0c02 0x20>, 5222 <&apps_smmu 0x19c2 0x10>; 5223 dma-coherent; 5224 }; 5225 5226 compute-cb@3 { 5227 compatible = "qcom,fastrpc-compute-cb"; 5228 reg = <3>; 5229 iommus = <&apps_smmu 0x1963 0x0>, 5230 <&apps_smmu 0x0c03 0x20>, 5231 <&apps_smmu 0x19c3 0x10>; 5232 dma-coherent; 5233 }; 5234 5235 compute-cb@4 { 5236 compatible = "qcom,fastrpc-compute-cb"; 5237 reg = <4>; 5238 iommus = <&apps_smmu 0x1964 0x0>, 5239 <&apps_smmu 0x0c04 0x20>, 5240 <&apps_smmu 0x19c4 0x10>; 5241 dma-coherent; 5242 }; 5243 5244 compute-cb@5 { 5245 compatible = "qcom,fastrpc-compute-cb"; 5246 reg = <5>; 5247 iommus = <&apps_smmu 0x1965 0x0>, 5248 <&apps_smmu 0x0c05 0x20>, 5249 <&apps_smmu 0x19c5 0x10>; 5250 dma-coherent; 5251 }; 5252 5253 compute-cb@6 { 5254 compatible = "qcom,fastrpc-compute-cb"; 5255 reg = <6>; 5256 iommus = <&apps_smmu 0x1966 0x0>, 5257 <&apps_smmu 0x0c06 0x20>, 5258 <&apps_smmu 0x19c6 0x10>; 5259 dma-coherent; 5260 }; 5261 5262 compute-cb@7 { 5263 compatible = "qcom,fastrpc-compute-cb"; 5264 reg = <7>; 5265 iommus = <&apps_smmu 0x1967 0x0>, 5266 <&apps_smmu 0x0c07 0x20>, 5267 <&apps_smmu 0x19c7 0x10>; 5268 dma-coherent; 5269 }; 5270 5271 compute-cb@8 { 5272 compatible = "qcom,fastrpc-compute-cb"; 5273 reg = <8>; 5274 iommus = <&apps_smmu 0x1968 0x0>, 5275 <&apps_smmu 0x0c08 0x20>, 5276 <&apps_smmu 0x19c8 0x10>; 5277 dma-coherent; 5278 }; 5279 5280 /* note: secure cb9 in downstream */ 5281 }; 5282 }; 5283 }; 5284 }; 5285 5286 thermal-zones { 5287 aoss0-thermal { 5288 thermal-sensors = <&tsens0 0>; 5289 5290 trips { 5291 thermal-engine-config { 5292 temperature = <125000>; 5293 hysteresis = <1000>; 5294 type = "passive"; 5295 }; 5296 5297 reset-mon-config { 5298 temperature = <115000>; 5299 hysteresis = <5000>; 5300 type = "passive"; 5301 }; 5302 }; 5303 }; 5304 5305 cpuss0-thermal { 5306 thermal-sensors = <&tsens0 1>; 5307 5308 trips { 5309 thermal-engine-config { 5310 temperature = <125000>; 5311 hysteresis = <1000>; 5312 type = "passive"; 5313 }; 5314 5315 reset-mon-config { 5316 temperature = <115000>; 5317 hysteresis = <5000>; 5318 type = "passive"; 5319 }; 5320 }; 5321 }; 5322 5323 cpuss1-thermal { 5324 thermal-sensors = <&tsens0 2>; 5325 5326 trips { 5327 thermal-engine-config { 5328 temperature = <125000>; 5329 hysteresis = <1000>; 5330 type = "passive"; 5331 }; 5332 5333 reset-mon-config { 5334 temperature = <115000>; 5335 hysteresis = <5000>; 5336 type = "passive"; 5337 }; 5338 }; 5339 }; 5340 5341 cpuss2-thermal { 5342 thermal-sensors = <&tsens0 3>; 5343 5344 trips { 5345 thermal-engine-config { 5346 temperature = <125000>; 5347 hysteresis = <1000>; 5348 type = "passive"; 5349 }; 5350 5351 reset-mon-config { 5352 temperature = <115000>; 5353 hysteresis = <5000>; 5354 type = "passive"; 5355 }; 5356 }; 5357 }; 5358 5359 cpuss3-thermal { 5360 thermal-sensors = <&tsens0 4>; 5361 5362 trips { 5363 thermal-engine-config { 5364 temperature = <125000>; 5365 hysteresis = <1000>; 5366 type = "passive"; 5367 }; 5368 5369 reset-mon-config { 5370 temperature = <115000>; 5371 hysteresis = <5000>; 5372 type = "passive"; 5373 }; 5374 }; 5375 }; 5376 5377 cpu3-top-thermal { 5378 thermal-sensors = <&tsens0 5>; 5379 5380 trips { 5381 cpu3_top_alert0: trip-point0 { 5382 temperature = <90000>; 5383 hysteresis = <2000>; 5384 type = "passive"; 5385 }; 5386 5387 cpu3_top_alert1: trip-point1 { 5388 temperature = <95000>; 5389 hysteresis = <2000>; 5390 type = "passive"; 5391 }; 5392 5393 cpu3_top_crit: cpu-critical { 5394 temperature = <110000>; 5395 hysteresis = <1000>; 5396 type = "critical"; 5397 }; 5398 }; 5399 }; 5400 5401 cpu3-bottom-thermal { 5402 thermal-sensors = <&tsens0 6>; 5403 5404 trips { 5405 cpu3_bottom_alert0: trip-point0 { 5406 temperature = <90000>; 5407 hysteresis = <2000>; 5408 type = "passive"; 5409 }; 5410 5411 cpu3_bottom_alert1: trip-point1 { 5412 temperature = <95000>; 5413 hysteresis = <2000>; 5414 type = "passive"; 5415 }; 5416 5417 cpu3_bottom_crit: cpu-critical { 5418 temperature = <110000>; 5419 hysteresis = <1000>; 5420 type = "critical"; 5421 }; 5422 }; 5423 }; 5424 5425 cpu4-top-thermal { 5426 thermal-sensors = <&tsens0 7>; 5427 5428 trips { 5429 cpu4_top_alert0: trip-point0 { 5430 temperature = <90000>; 5431 hysteresis = <2000>; 5432 type = "passive"; 5433 }; 5434 5435 cpu4_top_alert1: trip-point1 { 5436 temperature = <95000>; 5437 hysteresis = <2000>; 5438 type = "passive"; 5439 }; 5440 5441 cpu4_top_crit: cpu-critical { 5442 temperature = <110000>; 5443 hysteresis = <1000>; 5444 type = "critical"; 5445 }; 5446 }; 5447 }; 5448 5449 cpu4-bottom-thermal { 5450 thermal-sensors = <&tsens0 8>; 5451 5452 trips { 5453 cpu4_bottom_alert0: trip-point0 { 5454 temperature = <90000>; 5455 hysteresis = <2000>; 5456 type = "passive"; 5457 }; 5458 5459 cpu4_bottom_alert1: trip-point1 { 5460 temperature = <95000>; 5461 hysteresis = <2000>; 5462 type = "passive"; 5463 }; 5464 5465 cpu4_bottom_crit: cpu-critical { 5466 temperature = <110000>; 5467 hysteresis = <1000>; 5468 type = "critical"; 5469 }; 5470 }; 5471 }; 5472 5473 cpu5-top-thermal { 5474 thermal-sensors = <&tsens0 9>; 5475 5476 trips { 5477 cpu5_top_alert0: trip-point0 { 5478 temperature = <90000>; 5479 hysteresis = <2000>; 5480 type = "passive"; 5481 }; 5482 5483 cpu5_top_alert1: trip-point1 { 5484 temperature = <95000>; 5485 hysteresis = <2000>; 5486 type = "passive"; 5487 }; 5488 5489 cpu5_top_crit: cpu-critical { 5490 temperature = <110000>; 5491 hysteresis = <1000>; 5492 type = "critical"; 5493 }; 5494 }; 5495 }; 5496 5497 cpu5-bottom-thermal { 5498 thermal-sensors = <&tsens0 10>; 5499 5500 trips { 5501 cpu5_bottom_alert0: trip-point0 { 5502 temperature = <90000>; 5503 hysteresis = <2000>; 5504 type = "passive"; 5505 }; 5506 5507 cpu5_bottom_alert1: trip-point1 { 5508 temperature = <95000>; 5509 hysteresis = <2000>; 5510 type = "passive"; 5511 }; 5512 5513 cpu5_bottom_crit: cpu-critical { 5514 temperature = <110000>; 5515 hysteresis = <1000>; 5516 type = "critical"; 5517 }; 5518 }; 5519 }; 5520 5521 cpu6-top-thermal { 5522 thermal-sensors = <&tsens0 11>; 5523 5524 trips { 5525 cpu6_top_alert0: trip-point0 { 5526 temperature = <90000>; 5527 hysteresis = <2000>; 5528 type = "passive"; 5529 }; 5530 5531 cpu6_top_alert1: trip-point1 { 5532 temperature = <95000>; 5533 hysteresis = <2000>; 5534 type = "passive"; 5535 }; 5536 5537 cpu6_top_crit: cpu-critical { 5538 temperature = <110000>; 5539 hysteresis = <1000>; 5540 type = "critical"; 5541 }; 5542 }; 5543 }; 5544 5545 cpu6-bottom-thermal { 5546 thermal-sensors = <&tsens0 12>; 5547 5548 trips { 5549 cpu6_bottom_alert0: trip-point0 { 5550 temperature = <90000>; 5551 hysteresis = <2000>; 5552 type = "passive"; 5553 }; 5554 5555 cpu6_bottom_alert1: trip-point1 { 5556 temperature = <95000>; 5557 hysteresis = <2000>; 5558 type = "passive"; 5559 }; 5560 5561 cpu6_bottom_crit: cpu-critical { 5562 temperature = <110000>; 5563 hysteresis = <1000>; 5564 type = "critical"; 5565 }; 5566 }; 5567 }; 5568 5569 cpu7-top-thermal { 5570 thermal-sensors = <&tsens0 13>; 5571 5572 trips { 5573 cpu7_top_alert0: trip-point0 { 5574 temperature = <90000>; 5575 hysteresis = <2000>; 5576 type = "passive"; 5577 }; 5578 5579 cpu7_top_alert1: trip-point1 { 5580 temperature = <95000>; 5581 hysteresis = <2000>; 5582 type = "passive"; 5583 }; 5584 5585 cpu7_top_crit: cpu-critical { 5586 temperature = <110000>; 5587 hysteresis = <1000>; 5588 type = "critical"; 5589 }; 5590 }; 5591 }; 5592 5593 cpu7-middle-thermal { 5594 thermal-sensors = <&tsens0 14>; 5595 5596 trips { 5597 cpu7_middle_alert0: trip-point0 { 5598 temperature = <90000>; 5599 hysteresis = <2000>; 5600 type = "passive"; 5601 }; 5602 5603 cpu7_middle_alert1: trip-point1 { 5604 temperature = <95000>; 5605 hysteresis = <2000>; 5606 type = "passive"; 5607 }; 5608 5609 cpu7_middle_crit: cpu-critical { 5610 temperature = <110000>; 5611 hysteresis = <1000>; 5612 type = "critical"; 5613 }; 5614 }; 5615 }; 5616 5617 cpu7-bottom-thermal { 5618 thermal-sensors = <&tsens0 15>; 5619 5620 trips { 5621 cpu7_bottom_alert0: trip-point0 { 5622 temperature = <90000>; 5623 hysteresis = <2000>; 5624 type = "passive"; 5625 }; 5626 5627 cpu7_bottom_alert1: trip-point1 { 5628 temperature = <95000>; 5629 hysteresis = <2000>; 5630 type = "passive"; 5631 }; 5632 5633 cpu7_bottom_crit: cpu-critical { 5634 temperature = <110000>; 5635 hysteresis = <1000>; 5636 type = "critical"; 5637 }; 5638 }; 5639 }; 5640 5641 aoss1-thermal { 5642 thermal-sensors = <&tsens1 0>; 5643 5644 trips { 5645 thermal-engine-config { 5646 temperature = <125000>; 5647 hysteresis = <1000>; 5648 type = "passive"; 5649 }; 5650 5651 reset-mon-config { 5652 temperature = <115000>; 5653 hysteresis = <5000>; 5654 type = "passive"; 5655 }; 5656 }; 5657 }; 5658 5659 cpu0-thermal { 5660 thermal-sensors = <&tsens1 1>; 5661 5662 trips { 5663 cpu0_alert0: trip-point0 { 5664 temperature = <90000>; 5665 hysteresis = <2000>; 5666 type = "passive"; 5667 }; 5668 5669 cpu0_alert1: trip-point1 { 5670 temperature = <95000>; 5671 hysteresis = <2000>; 5672 type = "passive"; 5673 }; 5674 5675 cpu0_crit: cpu-critical { 5676 temperature = <110000>; 5677 hysteresis = <1000>; 5678 type = "critical"; 5679 }; 5680 }; 5681 }; 5682 5683 cpu1-thermal { 5684 thermal-sensors = <&tsens1 2>; 5685 5686 trips { 5687 cpu1_alert0: trip-point0 { 5688 temperature = <90000>; 5689 hysteresis = <2000>; 5690 type = "passive"; 5691 }; 5692 5693 cpu1_alert1: trip-point1 { 5694 temperature = <95000>; 5695 hysteresis = <2000>; 5696 type = "passive"; 5697 }; 5698 5699 cpu1_crit: cpu-critical { 5700 temperature = <110000>; 5701 hysteresis = <1000>; 5702 type = "critical"; 5703 }; 5704 }; 5705 }; 5706 5707 cpu2-thermal { 5708 thermal-sensors = <&tsens1 3>; 5709 5710 trips { 5711 cpu2_alert0: trip-point0 { 5712 temperature = <90000>; 5713 hysteresis = <2000>; 5714 type = "passive"; 5715 }; 5716 5717 cpu2_alert1: trip-point1 { 5718 temperature = <95000>; 5719 hysteresis = <2000>; 5720 type = "passive"; 5721 }; 5722 5723 cpu2_crit: cpu-critical { 5724 temperature = <110000>; 5725 hysteresis = <1000>; 5726 type = "critical"; 5727 }; 5728 }; 5729 }; 5730 5731 cdsp0-thermal { 5732 polling-delay-passive = <10>; 5733 5734 thermal-sensors = <&tsens2 4>; 5735 5736 trips { 5737 thermal-engine-config { 5738 temperature = <125000>; 5739 hysteresis = <1000>; 5740 type = "passive"; 5741 }; 5742 5743 thermal-hal-config { 5744 temperature = <125000>; 5745 hysteresis = <1000>; 5746 type = "passive"; 5747 }; 5748 5749 reset-mon-config { 5750 temperature = <115000>; 5751 hysteresis = <5000>; 5752 type = "passive"; 5753 }; 5754 5755 cdsp0_junction_config: junction-config { 5756 temperature = <95000>; 5757 hysteresis = <5000>; 5758 type = "passive"; 5759 }; 5760 }; 5761 }; 5762 5763 cdsp1-thermal { 5764 polling-delay-passive = <10>; 5765 5766 thermal-sensors = <&tsens2 5>; 5767 5768 trips { 5769 thermal-engine-config { 5770 temperature = <125000>; 5771 hysteresis = <1000>; 5772 type = "passive"; 5773 }; 5774 5775 thermal-hal-config { 5776 temperature = <125000>; 5777 hysteresis = <1000>; 5778 type = "passive"; 5779 }; 5780 5781 reset-mon-config { 5782 temperature = <115000>; 5783 hysteresis = <5000>; 5784 type = "passive"; 5785 }; 5786 5787 cdsp1_junction_config: junction-config { 5788 temperature = <95000>; 5789 hysteresis = <5000>; 5790 type = "passive"; 5791 }; 5792 }; 5793 }; 5794 5795 cdsp2-thermal { 5796 polling-delay-passive = <10>; 5797 5798 thermal-sensors = <&tsens2 6>; 5799 5800 trips { 5801 thermal-engine-config { 5802 temperature = <125000>; 5803 hysteresis = <1000>; 5804 type = "passive"; 5805 }; 5806 5807 thermal-hal-config { 5808 temperature = <125000>; 5809 hysteresis = <1000>; 5810 type = "passive"; 5811 }; 5812 5813 reset-mon-config { 5814 temperature = <115000>; 5815 hysteresis = <5000>; 5816 type = "passive"; 5817 }; 5818 5819 cdsp2_junction_config: junction-config { 5820 temperature = <95000>; 5821 hysteresis = <5000>; 5822 type = "passive"; 5823 }; 5824 }; 5825 }; 5826 5827 cdsp3-thermal { 5828 polling-delay-passive = <10>; 5829 5830 thermal-sensors = <&tsens2 7>; 5831 5832 trips { 5833 thermal-engine-config { 5834 temperature = <125000>; 5835 hysteresis = <1000>; 5836 type = "passive"; 5837 }; 5838 5839 thermal-hal-config { 5840 temperature = <125000>; 5841 hysteresis = <1000>; 5842 type = "passive"; 5843 }; 5844 5845 reset-mon-config { 5846 temperature = <115000>; 5847 hysteresis = <5000>; 5848 type = "passive"; 5849 }; 5850 5851 cdsp3_junction_config: junction-config { 5852 temperature = <95000>; 5853 hysteresis = <5000>; 5854 type = "passive"; 5855 }; 5856 }; 5857 }; 5858 5859 video-thermal { 5860 thermal-sensors = <&tsens1 8>; 5861 5862 trips { 5863 thermal-engine-config { 5864 temperature = <125000>; 5865 hysteresis = <1000>; 5866 type = "passive"; 5867 }; 5868 5869 reset-mon-config { 5870 temperature = <115000>; 5871 hysteresis = <5000>; 5872 type = "passive"; 5873 }; 5874 }; 5875 }; 5876 5877 mem-thermal { 5878 polling-delay-passive = <10>; 5879 5880 thermal-sensors = <&tsens1 9>; 5881 5882 trips { 5883 thermal-engine-config { 5884 temperature = <125000>; 5885 hysteresis = <1000>; 5886 type = "passive"; 5887 }; 5888 5889 ddr_config0: ddr0-config { 5890 temperature = <90000>; 5891 hysteresis = <5000>; 5892 type = "passive"; 5893 }; 5894 5895 reset-mon-config { 5896 temperature = <115000>; 5897 hysteresis = <5000>; 5898 type = "passive"; 5899 }; 5900 }; 5901 }; 5902 5903 modem0-thermal { 5904 thermal-sensors = <&tsens1 10>; 5905 5906 trips { 5907 thermal-engine-config { 5908 temperature = <125000>; 5909 hysteresis = <1000>; 5910 type = "passive"; 5911 }; 5912 5913 mdmss0_config0: mdmss0-config0 { 5914 temperature = <102000>; 5915 hysteresis = <3000>; 5916 type = "passive"; 5917 }; 5918 5919 mdmss0_config1: mdmss0-config1 { 5920 temperature = <105000>; 5921 hysteresis = <3000>; 5922 type = "passive"; 5923 }; 5924 5925 reset-mon-config { 5926 temperature = <115000>; 5927 hysteresis = <5000>; 5928 type = "passive"; 5929 }; 5930 }; 5931 }; 5932 5933 modem1-thermal { 5934 thermal-sensors = <&tsens1 11>; 5935 5936 trips { 5937 thermal-engine-config { 5938 temperature = <125000>; 5939 hysteresis = <1000>; 5940 type = "passive"; 5941 }; 5942 5943 mdmss1_config0: mdmss1-config0 { 5944 temperature = <102000>; 5945 hysteresis = <3000>; 5946 type = "passive"; 5947 }; 5948 5949 mdmss1_config1: mdmss1-config1 { 5950 temperature = <105000>; 5951 hysteresis = <3000>; 5952 type = "passive"; 5953 }; 5954 5955 reset-mon-config { 5956 temperature = <115000>; 5957 hysteresis = <5000>; 5958 type = "passive"; 5959 }; 5960 }; 5961 }; 5962 5963 modem2-thermal { 5964 thermal-sensors = <&tsens1 12>; 5965 5966 trips { 5967 thermal-engine-config { 5968 temperature = <125000>; 5969 hysteresis = <1000>; 5970 type = "passive"; 5971 }; 5972 5973 mdmss2_config0: mdmss2-config0 { 5974 temperature = <102000>; 5975 hysteresis = <3000>; 5976 type = "passive"; 5977 }; 5978 5979 mdmss2_config1: mdmss2-config1 { 5980 temperature = <105000>; 5981 hysteresis = <3000>; 5982 type = "passive"; 5983 }; 5984 5985 reset-mon-config { 5986 temperature = <115000>; 5987 hysteresis = <5000>; 5988 type = "passive"; 5989 }; 5990 }; 5991 }; 5992 5993 modem3-thermal { 5994 thermal-sensors = <&tsens1 13>; 5995 5996 trips { 5997 thermal-engine-config { 5998 temperature = <125000>; 5999 hysteresis = <1000>; 6000 type = "passive"; 6001 }; 6002 6003 mdmss3_config0: mdmss3-config0 { 6004 temperature = <102000>; 6005 hysteresis = <3000>; 6006 type = "passive"; 6007 }; 6008 6009 mdmss3_config1: mdmss3-config1 { 6010 temperature = <105000>; 6011 hysteresis = <3000>; 6012 type = "passive"; 6013 }; 6014 6015 reset-mon-config { 6016 temperature = <115000>; 6017 hysteresis = <5000>; 6018 type = "passive"; 6019 }; 6020 }; 6021 }; 6022 6023 camera0-thermal { 6024 thermal-sensors = <&tsens1 14>; 6025 6026 trips { 6027 thermal-engine-config { 6028 temperature = <125000>; 6029 hysteresis = <1000>; 6030 type = "passive"; 6031 }; 6032 6033 reset-mon-config { 6034 temperature = <115000>; 6035 hysteresis = <5000>; 6036 type = "passive"; 6037 }; 6038 }; 6039 }; 6040 6041 camera1-thermal { 6042 thermal-sensors = <&tsens1 15>; 6043 6044 trips { 6045 thermal-engine-config { 6046 temperature = <125000>; 6047 hysteresis = <1000>; 6048 type = "passive"; 6049 }; 6050 6051 reset-mon-config { 6052 temperature = <115000>; 6053 hysteresis = <5000>; 6054 type = "passive"; 6055 }; 6056 }; 6057 }; 6058 6059 aoss2-thermal { 6060 thermal-sensors = <&tsens2 0>; 6061 6062 trips { 6063 thermal-engine-config { 6064 temperature = <125000>; 6065 hysteresis = <1000>; 6066 type = "passive"; 6067 }; 6068 6069 reset-mon-config { 6070 temperature = <115000>; 6071 hysteresis = <5000>; 6072 type = "passive"; 6073 }; 6074 }; 6075 }; 6076 6077 gpuss-0-thermal { 6078 polling-delay-passive = <10>; 6079 6080 thermal-sensors = <&tsens2 1>; 6081 6082 cooling-maps { 6083 map0 { 6084 trip = <&gpu0_alert0>; 6085 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6086 }; 6087 }; 6088 6089 trips { 6090 gpu0_alert0: trip-point0 { 6091 temperature = <85000>; 6092 hysteresis = <1000>; 6093 type = "passive"; 6094 }; 6095 6096 trip-point1 { 6097 temperature = <90000>; 6098 hysteresis = <1000>; 6099 type = "hot"; 6100 }; 6101 6102 trip-point2 { 6103 temperature = <110000>; 6104 hysteresis = <1000>; 6105 type = "critical"; 6106 }; 6107 }; 6108 }; 6109 6110 gpuss-1-thermal { 6111 polling-delay-passive = <10>; 6112 6113 thermal-sensors = <&tsens2 2>; 6114 6115 cooling-maps { 6116 map0 { 6117 trip = <&gpu1_alert0>; 6118 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6119 }; 6120 }; 6121 6122 trips { 6123 gpu1_alert0: trip-point0 { 6124 temperature = <85000>; 6125 hysteresis = <1000>; 6126 type = "passive"; 6127 }; 6128 6129 trip-point1 { 6130 temperature = <90000>; 6131 hysteresis = <1000>; 6132 type = "hot"; 6133 }; 6134 6135 trip-point2 { 6136 temperature = <110000>; 6137 hysteresis = <1000>; 6138 type = "critical"; 6139 }; 6140 }; 6141 }; 6142 6143 gpuss-2-thermal { 6144 polling-delay-passive = <10>; 6145 6146 thermal-sensors = <&tsens2 3>; 6147 6148 cooling-maps { 6149 map0 { 6150 trip = <&gpu2_alert0>; 6151 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6152 }; 6153 }; 6154 6155 trips { 6156 gpu2_alert0: trip-point0 { 6157 temperature = <85000>; 6158 hysteresis = <1000>; 6159 type = "passive"; 6160 }; 6161 6162 trip-point1 { 6163 temperature = <90000>; 6164 hysteresis = <1000>; 6165 type = "hot"; 6166 }; 6167 6168 trip-point2 { 6169 temperature = <110000>; 6170 hysteresis = <1000>; 6171 type = "critical"; 6172 }; 6173 }; 6174 }; 6175 6176 gpuss-3-thermal { 6177 polling-delay-passive = <10>; 6178 6179 thermal-sensors = <&tsens2 4>; 6180 6181 cooling-maps { 6182 map0 { 6183 trip = <&gpu3_alert0>; 6184 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6185 }; 6186 }; 6187 6188 trips { 6189 gpu3_alert0: trip-point0 { 6190 temperature = <85000>; 6191 hysteresis = <1000>; 6192 type = "passive"; 6193 }; 6194 6195 trip-point1 { 6196 temperature = <90000>; 6197 hysteresis = <1000>; 6198 type = "hot"; 6199 }; 6200 6201 trip-point2 { 6202 temperature = <110000>; 6203 hysteresis = <1000>; 6204 type = "critical"; 6205 }; 6206 }; 6207 }; 6208 6209 gpuss-4-thermal { 6210 polling-delay-passive = <10>; 6211 6212 thermal-sensors = <&tsens2 5>; 6213 6214 cooling-maps { 6215 map0 { 6216 trip = <&gpu4_alert0>; 6217 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6218 }; 6219 }; 6220 6221 trips { 6222 gpu4_alert0: trip-point0 { 6223 temperature = <85000>; 6224 hysteresis = <1000>; 6225 type = "passive"; 6226 }; 6227 6228 trip-point1 { 6229 temperature = <90000>; 6230 hysteresis = <1000>; 6231 type = "hot"; 6232 }; 6233 6234 trip-point2 { 6235 temperature = <110000>; 6236 hysteresis = <1000>; 6237 type = "critical"; 6238 }; 6239 }; 6240 }; 6241 6242 gpuss-5-thermal { 6243 polling-delay-passive = <10>; 6244 6245 thermal-sensors = <&tsens2 6>; 6246 6247 cooling-maps { 6248 map0 { 6249 trip = <&gpu5_alert0>; 6250 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6251 }; 6252 }; 6253 6254 trips { 6255 gpu5_alert0: trip-point0 { 6256 temperature = <85000>; 6257 hysteresis = <1000>; 6258 type = "passive"; 6259 }; 6260 6261 trip-point1 { 6262 temperature = <90000>; 6263 hysteresis = <1000>; 6264 type = "hot"; 6265 }; 6266 6267 trip-point2 { 6268 temperature = <110000>; 6269 hysteresis = <1000>; 6270 type = "critical"; 6271 }; 6272 }; 6273 }; 6274 6275 gpuss-6-thermal { 6276 polling-delay-passive = <10>; 6277 6278 thermal-sensors = <&tsens2 7>; 6279 6280 cooling-maps { 6281 map0 { 6282 trip = <&gpu6_alert0>; 6283 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6284 }; 6285 }; 6286 6287 trips { 6288 gpu6_alert0: trip-point0 { 6289 temperature = <85000>; 6290 hysteresis = <1000>; 6291 type = "passive"; 6292 }; 6293 6294 trip-point1 { 6295 temperature = <90000>; 6296 hysteresis = <1000>; 6297 type = "hot"; 6298 }; 6299 6300 trip-point2 { 6301 temperature = <110000>; 6302 hysteresis = <1000>; 6303 type = "critical"; 6304 }; 6305 }; 6306 }; 6307 6308 gpuss-7-thermal { 6309 polling-delay-passive = <10>; 6310 6311 thermal-sensors = <&tsens2 8>; 6312 6313 cooling-maps { 6314 map0 { 6315 trip = <&gpu7_alert0>; 6316 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6317 }; 6318 }; 6319 6320 trips { 6321 gpu7_alert0: trip-point0 { 6322 temperature = <85000>; 6323 hysteresis = <1000>; 6324 type = "passive"; 6325 }; 6326 6327 trip-point1 { 6328 temperature = <90000>; 6329 hysteresis = <1000>; 6330 type = "hot"; 6331 }; 6332 6333 trip-point2 { 6334 temperature = <110000>; 6335 hysteresis = <1000>; 6336 type = "critical"; 6337 }; 6338 }; 6339 }; 6340 }; 6341 6342 timer { 6343 compatible = "arm,armv8-timer"; 6344 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6345 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6346 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6347 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6348 }; 6349}; 6350