1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sm8450-videocc.h> 9#include <dt-bindings/clock/qcom,sm8550-camcc.h> 10#include <dt-bindings/clock/qcom,sm8550-gcc.h> 11#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 12#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 13#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 14#include <dt-bindings/dma/qcom-gpi.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/interconnect/qcom,icc.h> 19#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/power/qcom,rpmhpd.h> 23#include <dt-bindings/soc/qcom,gpr.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 26#include <dt-bindings/phy/phy-qcom-qmp.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 chosen { }; 36 37 clocks { 38 xo_board: xo-board { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 }; 47 48 bi_tcxo_div2: bi-tcxo-div2-clk { 49 #clock-cells = <0>; 50 compatible = "fixed-factor-clock"; 51 clocks = <&rpmhcc RPMH_CXO_CLK>; 52 clock-mult = <1>; 53 clock-div = <2>; 54 }; 55 56 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 57 #clock-cells = <0>; 58 compatible = "fixed-factor-clock"; 59 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 60 clock-mult = <1>; 61 clock-div = <2>; 62 }; 63 }; 64 65 cpus { 66 #address-cells = <2>; 67 #size-cells = <0>; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a510"; 72 reg = <0 0>; 73 clocks = <&cpufreq_hw 0>; 74 enable-method = "psci"; 75 next-level-cache = <&l2_0>; 76 power-domains = <&cpu_pd0>; 77 power-domain-names = "psci"; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 capacity-dmips-mhz = <1024>; 80 dynamic-power-coefficient = <100>; 81 #cooling-cells = <2>; 82 l2_0: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 cache-unified; 86 next-level-cache = <&l3_0>; 87 l3_0: l3-cache { 88 compatible = "cache"; 89 cache-level = <3>; 90 cache-unified; 91 }; 92 }; 93 }; 94 95 cpu1: cpu@100 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a510"; 98 reg = <0 0x100>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 next-level-cache = <&l2_100>; 102 power-domains = <&cpu_pd1>; 103 power-domain-names = "psci"; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 capacity-dmips-mhz = <1024>; 106 dynamic-power-coefficient = <100>; 107 #cooling-cells = <2>; 108 l2_100: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&l3_0>; 113 }; 114 }; 115 116 cpu2: cpu@200 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a510"; 119 reg = <0 0x200>; 120 clocks = <&cpufreq_hw 0>; 121 enable-method = "psci"; 122 next-level-cache = <&l2_200>; 123 power-domains = <&cpu_pd2>; 124 power-domain-names = "psci"; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 capacity-dmips-mhz = <1024>; 127 dynamic-power-coefficient = <100>; 128 #cooling-cells = <2>; 129 l2_200: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 next-level-cache = <&l3_0>; 134 }; 135 }; 136 137 cpu3: cpu@300 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a715"; 140 reg = <0 0x300>; 141 clocks = <&cpufreq_hw 1>; 142 enable-method = "psci"; 143 next-level-cache = <&l2_300>; 144 power-domains = <&cpu_pd3>; 145 power-domain-names = "psci"; 146 qcom,freq-domain = <&cpufreq_hw 1>; 147 capacity-dmips-mhz = <1792>; 148 dynamic-power-coefficient = <270>; 149 #cooling-cells = <2>; 150 l2_300: l2-cache { 151 compatible = "cache"; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&l3_0>; 155 }; 156 }; 157 158 cpu4: cpu@400 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a715"; 161 reg = <0 0x400>; 162 clocks = <&cpufreq_hw 1>; 163 enable-method = "psci"; 164 next-level-cache = <&l2_400>; 165 power-domains = <&cpu_pd4>; 166 power-domain-names = "psci"; 167 qcom,freq-domain = <&cpufreq_hw 1>; 168 capacity-dmips-mhz = <1792>; 169 dynamic-power-coefficient = <270>; 170 #cooling-cells = <2>; 171 l2_400: l2-cache { 172 compatible = "cache"; 173 cache-level = <2>; 174 cache-unified; 175 next-level-cache = <&l3_0>; 176 }; 177 }; 178 179 cpu5: cpu@500 { 180 device_type = "cpu"; 181 compatible = "arm,cortex-a710"; 182 reg = <0 0x500>; 183 clocks = <&cpufreq_hw 1>; 184 enable-method = "psci"; 185 next-level-cache = <&l2_500>; 186 power-domains = <&cpu_pd5>; 187 power-domain-names = "psci"; 188 qcom,freq-domain = <&cpufreq_hw 1>; 189 capacity-dmips-mhz = <1792>; 190 dynamic-power-coefficient = <270>; 191 #cooling-cells = <2>; 192 l2_500: l2-cache { 193 compatible = "cache"; 194 cache-level = <2>; 195 cache-unified; 196 next-level-cache = <&l3_0>; 197 }; 198 }; 199 200 cpu6: cpu@600 { 201 device_type = "cpu"; 202 compatible = "arm,cortex-a710"; 203 reg = <0 0x600>; 204 clocks = <&cpufreq_hw 1>; 205 enable-method = "psci"; 206 next-level-cache = <&l2_600>; 207 power-domains = <&cpu_pd6>; 208 power-domain-names = "psci"; 209 qcom,freq-domain = <&cpufreq_hw 1>; 210 capacity-dmips-mhz = <1792>; 211 dynamic-power-coefficient = <270>; 212 #cooling-cells = <2>; 213 l2_600: l2-cache { 214 compatible = "cache"; 215 cache-level = <2>; 216 cache-unified; 217 next-level-cache = <&l3_0>; 218 }; 219 }; 220 221 cpu7: cpu@700 { 222 device_type = "cpu"; 223 compatible = "arm,cortex-x3"; 224 reg = <0 0x700>; 225 clocks = <&cpufreq_hw 2>; 226 enable-method = "psci"; 227 next-level-cache = <&l2_700>; 228 power-domains = <&cpu_pd7>; 229 power-domain-names = "psci"; 230 qcom,freq-domain = <&cpufreq_hw 2>; 231 capacity-dmips-mhz = <1894>; 232 dynamic-power-coefficient = <588>; 233 #cooling-cells = <2>; 234 l2_700: l2-cache { 235 compatible = "cache"; 236 cache-level = <2>; 237 cache-unified; 238 next-level-cache = <&l3_0>; 239 }; 240 }; 241 242 cpu-map { 243 cluster0 { 244 core0 { 245 cpu = <&cpu0>; 246 }; 247 248 core1 { 249 cpu = <&cpu1>; 250 }; 251 252 core2 { 253 cpu = <&cpu2>; 254 }; 255 256 core3 { 257 cpu = <&cpu3>; 258 }; 259 260 core4 { 261 cpu = <&cpu4>; 262 }; 263 264 core5 { 265 cpu = <&cpu5>; 266 }; 267 268 core6 { 269 cpu = <&cpu6>; 270 }; 271 272 core7 { 273 cpu = <&cpu7>; 274 }; 275 }; 276 }; 277 278 idle-states { 279 entry-method = "psci"; 280 281 little_cpu_sleep_0: cpu-sleep-0-0 { 282 compatible = "arm,idle-state"; 283 idle-state-name = "silver-rail-power-collapse"; 284 arm,psci-suspend-param = <0x40000004>; 285 entry-latency-us = <550>; 286 exit-latency-us = <750>; 287 min-residency-us = <6700>; 288 local-timer-stop; 289 }; 290 291 big_cpu_sleep_0: cpu-sleep-1-0 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "gold-rail-power-collapse"; 294 arm,psci-suspend-param = <0x40000004>; 295 entry-latency-us = <600>; 296 exit-latency-us = <1300>; 297 min-residency-us = <8136>; 298 local-timer-stop; 299 }; 300 301 prime_cpu_sleep_0: cpu-sleep-2-0 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "goldplus-rail-power-collapse"; 304 arm,psci-suspend-param = <0x40000004>; 305 entry-latency-us = <500>; 306 exit-latency-us = <1350>; 307 min-residency-us = <7480>; 308 local-timer-stop; 309 }; 310 }; 311 312 domain-idle-states { 313 cluster_sleep_0: cluster-sleep-0 { 314 compatible = "domain-idle-state"; 315 arm,psci-suspend-param = <0x41000044>; 316 entry-latency-us = <750>; 317 exit-latency-us = <2350>; 318 min-residency-us = <9144>; 319 }; 320 321 cluster_sleep_1: cluster-sleep-1 { 322 compatible = "domain-idle-state"; 323 arm,psci-suspend-param = <0x4100c344>; 324 entry-latency-us = <2800>; 325 exit-latency-us = <4400>; 326 min-residency-us = <10150>; 327 }; 328 }; 329 }; 330 331 firmware { 332 scm: scm { 333 compatible = "qcom,scm-sm8550", "qcom,scm"; 334 qcom,dload-mode = <&tcsr 0x19000>; 335 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 336 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 337 }; 338 }; 339 340 clk_virt: interconnect-0 { 341 compatible = "qcom,sm8550-clk-virt"; 342 #interconnect-cells = <2>; 343 qcom,bcm-voters = <&apps_bcm_voter>; 344 }; 345 346 mc_virt: interconnect-1 { 347 compatible = "qcom,sm8550-mc-virt"; 348 #interconnect-cells = <2>; 349 qcom,bcm-voters = <&apps_bcm_voter>; 350 }; 351 352 qup_opp_table_100mhz: opp-table-qup100mhz { 353 compatible = "operating-points-v2"; 354 355 opp-75000000 { 356 opp-hz = /bits/ 64 <75000000>; 357 required-opps = <&rpmhpd_opp_low_svs>; 358 }; 359 360 opp-100000000 { 361 opp-hz = /bits/ 64 <100000000>; 362 required-opps = <&rpmhpd_opp_svs>; 363 }; 364 }; 365 366 qup_opp_table_120mhz: opp-table-qup120mhz { 367 compatible = "operating-points-v2"; 368 369 opp-75000000 { 370 opp-hz = /bits/ 64 <75000000>; 371 required-opps = <&rpmhpd_opp_low_svs>; 372 }; 373 374 opp-120000000 { 375 opp-hz = /bits/ 64 <120000000>; 376 required-opps = <&rpmhpd_opp_svs>; 377 }; 378 }; 379 380 qup_opp_table_125mhz: opp-table-qup125mhz { 381 compatible = "operating-points-v2"; 382 383 opp-75000000 { 384 opp-hz = /bits/ 64 <75000000>; 385 required-opps = <&rpmhpd_opp_low_svs>; 386 }; 387 388 opp-125000000 { 389 opp-hz = /bits/ 64 <125000000>; 390 required-opps = <&rpmhpd_opp_svs>; 391 }; 392 }; 393 394 memory@a0000000 { 395 device_type = "memory"; 396 /* We expect the bootloader to fill in the size */ 397 reg = <0 0xa0000000 0 0>; 398 }; 399 400 pmu-a510 { 401 compatible = "arm,cortex-a510-pmu"; 402 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 403 }; 404 405 pmu-a710 { 406 compatible = "arm,cortex-a710-pmu"; 407 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 408 }; 409 410 pmu-a715 { 411 compatible = "arm,cortex-a715-pmu"; 412 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster2>; 413 }; 414 415 pmu-x3 { 416 compatible = "arm,cortex-x3-pmu"; 417 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster3>; 418 }; 419 420 psci { 421 compatible = "arm,psci-1.0"; 422 method = "smc"; 423 424 cpu_pd0: power-domain-cpu0 { 425 #power-domain-cells = <0>; 426 power-domains = <&cluster_pd>; 427 domain-idle-states = <&little_cpu_sleep_0>; 428 }; 429 430 cpu_pd1: power-domain-cpu1 { 431 #power-domain-cells = <0>; 432 power-domains = <&cluster_pd>; 433 domain-idle-states = <&little_cpu_sleep_0>; 434 }; 435 436 cpu_pd2: power-domain-cpu2 { 437 #power-domain-cells = <0>; 438 power-domains = <&cluster_pd>; 439 domain-idle-states = <&little_cpu_sleep_0>; 440 }; 441 442 cpu_pd3: power-domain-cpu3 { 443 #power-domain-cells = <0>; 444 power-domains = <&cluster_pd>; 445 domain-idle-states = <&big_cpu_sleep_0>; 446 }; 447 448 cpu_pd4: power-domain-cpu4 { 449 #power-domain-cells = <0>; 450 power-domains = <&cluster_pd>; 451 domain-idle-states = <&big_cpu_sleep_0>; 452 }; 453 454 cpu_pd5: power-domain-cpu5 { 455 #power-domain-cells = <0>; 456 power-domains = <&cluster_pd>; 457 domain-idle-states = <&big_cpu_sleep_0>; 458 }; 459 460 cpu_pd6: power-domain-cpu6 { 461 #power-domain-cells = <0>; 462 power-domains = <&cluster_pd>; 463 domain-idle-states = <&big_cpu_sleep_0>; 464 }; 465 466 cpu_pd7: power-domain-cpu7 { 467 #power-domain-cells = <0>; 468 power-domains = <&cluster_pd>; 469 domain-idle-states = <&prime_cpu_sleep_0>; 470 }; 471 472 cluster_pd: power-domain-cluster { 473 #power-domain-cells = <0>; 474 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; 475 }; 476 }; 477 478 reserved_memory: reserved-memory { 479 #address-cells = <2>; 480 #size-cells = <2>; 481 ranges; 482 483 hyp_mem: hyp-region@80000000 { 484 reg = <0 0x80000000 0 0xa00000>; 485 no-map; 486 }; 487 488 cpusys_vm_mem: cpusys-vm-region@80a00000 { 489 reg = <0 0x80a00000 0 0x400000>; 490 no-map; 491 }; 492 493 hyp_tags_mem: hyp-tags-region@80e00000 { 494 reg = <0 0x80e00000 0 0x3d0000>; 495 no-map; 496 }; 497 498 xbl_sc_mem: xbl-sc-region@d8100000 { 499 reg = <0 0xd8100000 0 0x40000>; 500 no-map; 501 }; 502 503 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 504 reg = <0 0x811d0000 0 0x30000>; 505 no-map; 506 }; 507 508 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 509 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 510 reg = <0 0x81a00000 0 0x260000>; 511 no-map; 512 }; 513 514 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 515 compatible = "qcom,cmd-db"; 516 reg = <0 0x81c60000 0 0x20000>; 517 no-map; 518 }; 519 520 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 521 aop_config_merged_mem: aop-config-merged-region@81c80000 { 522 reg = <0 0x81c80000 0 0x74000>; 523 no-map; 524 }; 525 526 /* secdata region can be reused by apps */ 527 smem: smem@81d00000 { 528 compatible = "qcom,smem"; 529 reg = <0 0x81d00000 0 0x200000>; 530 hwlocks = <&tcsr_mutex 3>; 531 no-map; 532 }; 533 534 adsp_mhi_mem: adsp-mhi-region@81f00000 { 535 reg = <0 0x81f00000 0 0x20000>; 536 no-map; 537 }; 538 539 global_sync_mem: global-sync-region@82600000 { 540 reg = <0 0x82600000 0 0x100000>; 541 no-map; 542 }; 543 544 tz_stat_mem: tz-stat-region@82700000 { 545 reg = <0 0x82700000 0 0x100000>; 546 no-map; 547 }; 548 549 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 550 reg = <0 0x82800000 0 0x4600000>; 551 no-map; 552 }; 553 554 mpss_mem: mpss-region@8a800000 { 555 reg = <0 0x8a800000 0 0x10800000>; 556 no-map; 557 }; 558 559 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 560 reg = <0 0x9b000000 0 0x80000>; 561 no-map; 562 }; 563 564 ipa_fw_mem: ipa-fw-region@9b080000 { 565 reg = <0 0x9b080000 0 0x10000>; 566 no-map; 567 }; 568 569 ipa_gsi_mem: ipa-gsi-region@9b090000 { 570 reg = <0 0x9b090000 0 0xa000>; 571 no-map; 572 }; 573 574 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 575 reg = <0 0x9b09a000 0 0x2000>; 576 no-map; 577 }; 578 579 spss_region_mem: spss-region@9b100000 { 580 reg = <0 0x9b100000 0 0x180000>; 581 no-map; 582 }; 583 584 /* First part of the "SPU secure shared memory" region */ 585 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 586 reg = <0 0x9b280000 0 0x60000>; 587 no-map; 588 }; 589 590 /* Second part of the "SPU secure shared memory" region */ 591 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 592 reg = <0 0x9b2e0000 0 0x20000>; 593 no-map; 594 }; 595 596 camera_mem: camera-region@9b300000 { 597 reg = <0 0x9b300000 0 0x800000>; 598 no-map; 599 }; 600 601 video_mem: video-region@9bb00000 { 602 reg = <0 0x9bb00000 0 0x700000>; 603 no-map; 604 }; 605 606 cvp_mem: cvp-region@9c200000 { 607 reg = <0 0x9c200000 0 0x700000>; 608 no-map; 609 }; 610 611 cdsp_mem: cdsp-region@9c900000 { 612 reg = <0 0x9c900000 0 0x2000000>; 613 no-map; 614 }; 615 616 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 617 reg = <0 0x9e900000 0 0x80000>; 618 no-map; 619 }; 620 621 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 622 reg = <0 0x9e980000 0 0x80000>; 623 no-map; 624 }; 625 626 adspslpi_mem: adspslpi-region@9ea00000 { 627 reg = <0 0x9ea00000 0 0x4080000>; 628 no-map; 629 }; 630 631 /* uefi region can be reused by apps */ 632 633 /* Linux kernel image is loaded at 0xa8000000 */ 634 635 rmtfs_mem: rmtfs-region@d4a80000 { 636 compatible = "qcom,rmtfs-mem"; 637 reg = <0x0 0xd4a80000 0x0 0x280000>; 638 no-map; 639 640 qcom,client-id = <1>; 641 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 642 }; 643 644 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 645 reg = <0 0xd4d00000 0 0x3300000>; 646 no-map; 647 }; 648 649 tz_reserved_mem: tz-reserved-region@d8000000 { 650 reg = <0 0xd8000000 0 0x100000>; 651 no-map; 652 }; 653 654 cpucp_fw_mem: cpucp-fw-region@d8140000 { 655 reg = <0 0xd8140000 0 0x1c0000>; 656 no-map; 657 }; 658 659 qtee_mem: qtee-region@d8300000 { 660 reg = <0 0xd8300000 0 0x500000>; 661 no-map; 662 }; 663 664 ta_mem: ta-region@d8800000 { 665 reg = <0 0xd8800000 0 0x8a00000>; 666 no-map; 667 }; 668 669 tz_tags_mem: tz-tags-region@e1200000 { 670 reg = <0 0xe1200000 0 0x2740000>; 671 no-map; 672 }; 673 674 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 675 reg = <0 0xe6440000 0 0x279000>; 676 no-map; 677 }; 678 679 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 680 reg = <0 0xf3600000 0 0x4aee000>; 681 no-map; 682 }; 683 684 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 685 reg = <0 0xf80ee000 0 0x1000>; 686 no-map; 687 }; 688 689 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 690 reg = <0 0xf80ef000 0 0x9000>; 691 no-map; 692 }; 693 694 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 695 reg = <0 0xf80f8000 0 0x4000>; 696 no-map; 697 }; 698 699 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 700 reg = <0 0xf80fc000 0 0x4000>; 701 no-map; 702 }; 703 704 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 705 reg = <0 0xf8100000 0 0x100000>; 706 no-map; 707 }; 708 709 oem_vm_mem: oem-vm-region@f8400000 { 710 reg = <0 0xf8400000 0 0x4800000>; 711 no-map; 712 }; 713 714 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 715 reg = <0 0xfcc00000 0 0x4000>; 716 no-map; 717 }; 718 719 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 720 reg = <0 0xfcc04000 0 0x100000>; 721 no-map; 722 }; 723 724 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 725 reg = <0 0xfce00000 0 0x2900000>; 726 no-map; 727 }; 728 729 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 730 reg = <0 0xff700000 0 0x100000>; 731 no-map; 732 }; 733 }; 734 735 smp2p-adsp { 736 compatible = "qcom,smp2p"; 737 qcom,smem = <443>, <429>; 738 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 739 IPCC_MPROC_SIGNAL_SMP2P 740 IRQ_TYPE_EDGE_RISING>; 741 mboxes = <&ipcc IPCC_CLIENT_LPASS 742 IPCC_MPROC_SIGNAL_SMP2P>; 743 744 qcom,local-pid = <0>; 745 qcom,remote-pid = <2>; 746 747 smp2p_adsp_out: master-kernel { 748 qcom,entry-name = "master-kernel"; 749 #qcom,smem-state-cells = <1>; 750 }; 751 752 smp2p_adsp_in: slave-kernel { 753 qcom,entry-name = "slave-kernel"; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 }; 757 }; 758 759 smp2p-cdsp { 760 compatible = "qcom,smp2p"; 761 qcom,smem = <94>, <432>; 762 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 763 IPCC_MPROC_SIGNAL_SMP2P 764 IRQ_TYPE_EDGE_RISING>; 765 mboxes = <&ipcc IPCC_CLIENT_CDSP 766 IPCC_MPROC_SIGNAL_SMP2P>; 767 768 qcom,local-pid = <0>; 769 qcom,remote-pid = <5>; 770 771 smp2p_cdsp_out: master-kernel { 772 qcom,entry-name = "master-kernel"; 773 #qcom,smem-state-cells = <1>; 774 }; 775 776 smp2p_cdsp_in: slave-kernel { 777 qcom,entry-name = "slave-kernel"; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 }; 782 783 smp2p-modem { 784 compatible = "qcom,smp2p"; 785 qcom,smem = <435>, <428>; 786 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 787 IPCC_MPROC_SIGNAL_SMP2P 788 IRQ_TYPE_EDGE_RISING>; 789 mboxes = <&ipcc IPCC_CLIENT_MPSS 790 IPCC_MPROC_SIGNAL_SMP2P>; 791 792 qcom,local-pid = <0>; 793 qcom,remote-pid = <1>; 794 795 smp2p_modem_out: master-kernel { 796 qcom,entry-name = "master-kernel"; 797 #qcom,smem-state-cells = <1>; 798 }; 799 800 smp2p_modem_in: slave-kernel { 801 qcom,entry-name = "slave-kernel"; 802 interrupt-controller; 803 #interrupt-cells = <2>; 804 }; 805 806 ipa_smp2p_out: ipa-ap-to-modem { 807 qcom,entry-name = "ipa"; 808 #qcom,smem-state-cells = <1>; 809 }; 810 811 ipa_smp2p_in: ipa-modem-to-ap { 812 qcom,entry-name = "ipa"; 813 interrupt-controller; 814 #interrupt-cells = <2>; 815 }; 816 }; 817 818 soc: soc@0 { 819 compatible = "simple-bus"; 820 ranges = <0 0 0 0 0x10 0>; 821 dma-ranges = <0 0 0 0 0x10 0>; 822 823 #address-cells = <2>; 824 #size-cells = <2>; 825 826 gcc: clock-controller@100000 { 827 compatible = "qcom,sm8550-gcc"; 828 reg = <0 0x00100000 0 0x1f4200>; 829 #clock-cells = <1>; 830 #reset-cells = <1>; 831 #power-domain-cells = <1>; 832 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 833 <&pcie0_phy>, 834 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 835 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 836 <&ufs_mem_phy 0>, 837 <&ufs_mem_phy 1>, 838 <&ufs_mem_phy 2>, 839 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 840 }; 841 842 ipcc: mailbox@408000 { 843 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 844 reg = <0 0x00408000 0 0x1000>; 845 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>; 846 interrupt-controller; 847 #interrupt-cells = <3>; 848 #mbox-cells = <2>; 849 }; 850 851 gpi_dma2: dma-controller@800000 { 852 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 853 #dma-cells = <3>; 854 reg = <0 0x00800000 0 0x60000>; 855 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>, 856 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>, 857 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, 858 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, 859 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, 860 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, 861 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, 862 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, 863 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, 864 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>, 865 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>, 866 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>; 867 dma-channels = <12>; 868 dma-channel-mask = <0x3e>; 869 iommus = <&apps_smmu 0x436 0>; 870 dma-coherent; 871 status = "disabled"; 872 }; 873 874 qupv3_id_1: geniqup@8c0000 { 875 compatible = "qcom,geni-se-qup"; 876 reg = <0 0x008c0000 0 0x2000>; 877 ranges; 878 clock-names = "m-ahb", "s-ahb"; 879 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 880 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 881 iommus = <&apps_smmu 0x423 0>; 882 dma-coherent; 883 #address-cells = <2>; 884 #size-cells = <2>; 885 status = "disabled"; 886 887 i2c8: i2c@880000 { 888 compatible = "qcom,geni-i2c"; 889 reg = <0 0x00880000 0 0x4000>; 890 clock-names = "se"; 891 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 892 pinctrl-names = "default"; 893 pinctrl-0 = <&qup_i2c8_data_clk>; 894 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 898 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 899 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 900 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 901 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 902 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 903 interconnect-names = "qup-core", "qup-config", "qup-memory"; 904 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 905 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 906 dma-names = "tx", "rx"; 907 power-domains = <&rpmhpd RPMHPD_CX>; 908 operating-points-v2 = <&qup_opp_table_120mhz>; 909 status = "disabled"; 910 }; 911 912 spi8: spi@880000 { 913 compatible = "qcom,geni-spi"; 914 reg = <0 0x00880000 0 0x4000>; 915 clock-names = "se"; 916 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 917 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 918 pinctrl-names = "default"; 919 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 920 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 921 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 922 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 923 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 924 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 925 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 926 interconnect-names = "qup-core", "qup-config", "qup-memory"; 927 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 928 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 929 dma-names = "tx", "rx"; 930 power-domains = <&rpmhpd RPMHPD_CX>; 931 operating-points-v2 = <&qup_opp_table_120mhz>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 status = "disabled"; 935 }; 936 937 i2c9: i2c@884000 { 938 compatible = "qcom,geni-i2c"; 939 reg = <0 0x00884000 0 0x4000>; 940 clock-names = "se"; 941 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&qup_i2c9_data_clk>; 944 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 948 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 949 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 950 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 951 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 952 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 953 interconnect-names = "qup-core", "qup-config", "qup-memory"; 954 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 955 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 956 dma-names = "tx", "rx"; 957 power-domains = <&rpmhpd RPMHPD_CX>; 958 operating-points-v2 = <&qup_opp_table_120mhz>; 959 status = "disabled"; 960 }; 961 962 spi9: spi@884000 { 963 compatible = "qcom,geni-spi"; 964 reg = <0 0x00884000 0 0x4000>; 965 clock-names = "se"; 966 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 967 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 970 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 971 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 972 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 973 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 974 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 975 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 976 interconnect-names = "qup-core", "qup-config", "qup-memory"; 977 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 978 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 979 dma-names = "tx", "rx"; 980 power-domains = <&rpmhpd RPMHPD_CX>; 981 operating-points-v2 = <&qup_opp_table_120mhz>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 i2c10: i2c@888000 { 988 compatible = "qcom,geni-i2c"; 989 reg = <0 0x00888000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&qup_i2c10_data_clk>; 994 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 998 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 999 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1000 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1001 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1002 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1003 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1004 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1005 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1006 dma-names = "tx", "rx"; 1007 power-domains = <&rpmhpd RPMHPD_CX>; 1008 operating-points-v2 = <&qup_opp_table_120mhz>; 1009 status = "disabled"; 1010 }; 1011 1012 spi10: spi@888000 { 1013 compatible = "qcom,geni-spi"; 1014 reg = <0 0x00888000 0 0x4000>; 1015 clock-names = "se"; 1016 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1017 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1020 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1021 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1022 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1023 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1024 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1025 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1026 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1027 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1028 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1029 dma-names = "tx", "rx"; 1030 power-domains = <&rpmhpd RPMHPD_CX>; 1031 operating-points-v2 = <&qup_opp_table_120mhz>; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 i2c11: i2c@88c000 { 1038 compatible = "qcom,geni-i2c"; 1039 reg = <0 0x0088c000 0 0x4000>; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1042 pinctrl-names = "default"; 1043 pinctrl-0 = <&qup_i2c11_data_clk>; 1044 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1048 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1049 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1050 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1051 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1052 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1053 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1054 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1055 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1056 dma-names = "tx", "rx"; 1057 power-domains = <&rpmhpd RPMHPD_CX>; 1058 operating-points-v2 = <&qup_opp_table_120mhz>; 1059 status = "disabled"; 1060 }; 1061 1062 spi11: spi@88c000 { 1063 compatible = "qcom,geni-spi"; 1064 reg = <0 0x0088c000 0 0x4000>; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1067 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1070 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1071 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1072 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1073 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1074 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1075 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1076 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1077 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1078 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1079 dma-names = "tx", "rx"; 1080 power-domains = <&rpmhpd RPMHPD_CX>; 1081 operating-points-v2 = <&qup_opp_table_120mhz>; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 status = "disabled"; 1085 }; 1086 1087 i2c12: i2c@890000 { 1088 compatible = "qcom,geni-i2c"; 1089 reg = <0 0x00890000 0 0x4000>; 1090 clock-names = "se"; 1091 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1092 pinctrl-names = "default"; 1093 pinctrl-0 = <&qup_i2c12_data_clk>; 1094 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1098 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1099 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1100 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1101 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1102 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1103 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1104 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1105 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1106 dma-names = "tx", "rx"; 1107 power-domains = <&rpmhpd RPMHPD_CX>; 1108 operating-points-v2 = <&qup_opp_table_120mhz>; 1109 status = "disabled"; 1110 }; 1111 1112 spi12: spi@890000 { 1113 compatible = "qcom,geni-spi"; 1114 reg = <0 0x00890000 0 0x4000>; 1115 clock-names = "se"; 1116 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1117 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1120 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1121 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1122 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1123 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1124 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1125 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1126 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1127 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1128 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1129 dma-names = "tx", "rx"; 1130 power-domains = <&rpmhpd RPMHPD_CX>; 1131 operating-points-v2 = <&qup_opp_table_120mhz>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 status = "disabled"; 1135 }; 1136 1137 i2c13: i2c@894000 { 1138 compatible = "qcom,geni-i2c"; 1139 reg = <0 0x00894000 0 0x4000>; 1140 clock-names = "se"; 1141 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1142 pinctrl-names = "default"; 1143 pinctrl-0 = <&qup_i2c13_data_clk>; 1144 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1148 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1149 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1150 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1151 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1152 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1153 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1154 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1155 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1156 dma-names = "tx", "rx"; 1157 power-domains = <&rpmhpd RPMHPD_CX>; 1158 operating-points-v2 = <&qup_opp_table_120mhz>; 1159 status = "disabled"; 1160 }; 1161 1162 spi13: spi@894000 { 1163 compatible = "qcom,geni-spi"; 1164 reg = <0 0x00894000 0 0x4000>; 1165 clock-names = "se"; 1166 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1167 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1171 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1172 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1173 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1174 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1176 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1177 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1178 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1179 dma-names = "tx", "rx"; 1180 power-domains = <&rpmhpd RPMHPD_CX>; 1181 operating-points-v2 = <&qup_opp_table_120mhz>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 status = "disabled"; 1185 }; 1186 1187 uart14: serial@898000 { 1188 compatible = "qcom,geni-uart"; 1189 reg = <0 0x898000 0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1194 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH 0>; 1195 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1196 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1197 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1198 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1199 interconnect-names = "qup-core", "qup-config"; 1200 power-domains = <&rpmhpd RPMHPD_CX>; 1201 operating-points-v2 = <&qup_opp_table_125mhz>; 1202 status = "disabled"; 1203 }; 1204 1205 i2c15: i2c@89c000 { 1206 compatible = "qcom,geni-i2c"; 1207 reg = <0 0x0089c000 0 0x4000>; 1208 clock-names = "se"; 1209 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1210 pinctrl-names = "default"; 1211 pinctrl-0 = <&qup_i2c15_data_clk>; 1212 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1216 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1217 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1218 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1219 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1220 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1221 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1222 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1223 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1224 dma-names = "tx", "rx"; 1225 power-domains = <&rpmhpd RPMHPD_CX>; 1226 operating-points-v2 = <&qup_opp_table_100mhz>; 1227 status = "disabled"; 1228 }; 1229 1230 spi15: spi@89c000 { 1231 compatible = "qcom,geni-spi"; 1232 reg = <0 0x0089c000 0 0x4000>; 1233 clock-names = "se"; 1234 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1235 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 1236 pinctrl-names = "default"; 1237 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1238 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1239 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1240 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1241 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1242 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1243 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1244 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1245 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1246 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1247 dma-names = "tx", "rx"; 1248 power-domains = <&rpmhpd RPMHPD_CX>; 1249 operating-points-v2 = <&qup_opp_table_100mhz>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 status = "disabled"; 1253 }; 1254 }; 1255 1256 i2c_master_hub_0: geniqup@9c0000 { 1257 compatible = "qcom,geni-se-i2c-master-hub"; 1258 reg = <0x0 0x009c0000 0x0 0x2000>; 1259 clock-names = "s-ahb"; 1260 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1261 #address-cells = <2>; 1262 #size-cells = <2>; 1263 ranges; 1264 status = "disabled"; 1265 1266 i2c_hub_0: i2c@980000 { 1267 compatible = "qcom,geni-i2c-master-hub"; 1268 reg = <0x0 0x00980000 0x0 0x4000>; 1269 clock-names = "se", "core"; 1270 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1271 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&hub_i2c0_data_clk>; 1274 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1278 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1279 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1280 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1281 interconnect-names = "qup-core", "qup-config"; 1282 power-domains = <&rpmhpd RPMHPD_CX>; 1283 required-opps = <&rpmhpd_opp_low_svs>; 1284 status = "disabled"; 1285 }; 1286 1287 i2c_hub_1: i2c@984000 { 1288 compatible = "qcom,geni-i2c-master-hub"; 1289 reg = <0x0 0x00984000 0x0 0x4000>; 1290 clock-names = "se", "core"; 1291 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1292 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&hub_i2c1_data_clk>; 1295 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH 0>; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1299 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1300 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1301 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1302 interconnect-names = "qup-core", "qup-config"; 1303 power-domains = <&rpmhpd RPMHPD_CX>; 1304 required-opps = <&rpmhpd_opp_low_svs>; 1305 status = "disabled"; 1306 }; 1307 1308 i2c_hub_2: i2c@988000 { 1309 compatible = "qcom,geni-i2c-master-hub"; 1310 reg = <0x0 0x00988000 0x0 0x4000>; 1311 clock-names = "se", "core"; 1312 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1313 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1314 pinctrl-names = "default"; 1315 pinctrl-0 = <&hub_i2c2_data_clk>; 1316 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH 0>; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1320 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1321 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1322 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1323 interconnect-names = "qup-core", "qup-config"; 1324 power-domains = <&rpmhpd RPMHPD_CX>; 1325 required-opps = <&rpmhpd_opp_low_svs>; 1326 status = "disabled"; 1327 }; 1328 1329 i2c_hub_3: i2c@98c000 { 1330 compatible = "qcom,geni-i2c-master-hub"; 1331 reg = <0x0 0x0098c000 0x0 0x4000>; 1332 clock-names = "se", "core"; 1333 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1334 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1335 pinctrl-names = "default"; 1336 pinctrl-0 = <&hub_i2c3_data_clk>; 1337 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1341 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1342 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1343 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1344 interconnect-names = "qup-core", "qup-config"; 1345 power-domains = <&rpmhpd RPMHPD_CX>; 1346 required-opps = <&rpmhpd_opp_low_svs>; 1347 status = "disabled"; 1348 }; 1349 1350 i2c_hub_4: i2c@990000 { 1351 compatible = "qcom,geni-i2c-master-hub"; 1352 reg = <0x0 0x00990000 0x0 0x4000>; 1353 clock-names = "se", "core"; 1354 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1355 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1356 pinctrl-names = "default"; 1357 pinctrl-0 = <&hub_i2c4_data_clk>; 1358 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1362 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1363 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1364 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1365 interconnect-names = "qup-core", "qup-config"; 1366 power-domains = <&rpmhpd RPMHPD_CX>; 1367 required-opps = <&rpmhpd_opp_low_svs>; 1368 status = "disabled"; 1369 }; 1370 1371 i2c_hub_5: i2c@994000 { 1372 compatible = "qcom,geni-i2c-master-hub"; 1373 reg = <0 0x00994000 0 0x4000>; 1374 clock-names = "se", "core"; 1375 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1376 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1377 pinctrl-names = "default"; 1378 pinctrl-0 = <&hub_i2c5_data_clk>; 1379 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH 0>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1383 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1384 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1385 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1386 interconnect-names = "qup-core", "qup-config"; 1387 power-domains = <&rpmhpd RPMHPD_CX>; 1388 required-opps = <&rpmhpd_opp_low_svs>; 1389 status = "disabled"; 1390 }; 1391 1392 i2c_hub_6: i2c@998000 { 1393 compatible = "qcom,geni-i2c-master-hub"; 1394 reg = <0 0x00998000 0 0x4000>; 1395 clock-names = "se", "core"; 1396 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1397 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1398 pinctrl-names = "default"; 1399 pinctrl-0 = <&hub_i2c6_data_clk>; 1400 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH 0>; 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1404 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1405 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1406 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1407 interconnect-names = "qup-core", "qup-config"; 1408 power-domains = <&rpmhpd RPMHPD_CX>; 1409 required-opps = <&rpmhpd_opp_low_svs>; 1410 status = "disabled"; 1411 }; 1412 1413 i2c_hub_7: i2c@99c000 { 1414 compatible = "qcom,geni-i2c-master-hub"; 1415 reg = <0 0x0099c000 0 0x4000>; 1416 clock-names = "se", "core"; 1417 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1418 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1419 pinctrl-names = "default"; 1420 pinctrl-0 = <&hub_i2c7_data_clk>; 1421 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1425 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1426 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1427 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1428 interconnect-names = "qup-core", "qup-config"; 1429 power-domains = <&rpmhpd RPMHPD_CX>; 1430 required-opps = <&rpmhpd_opp_low_svs>; 1431 status = "disabled"; 1432 }; 1433 1434 i2c_hub_8: i2c@9a0000 { 1435 compatible = "qcom,geni-i2c-master-hub"; 1436 reg = <0 0x009a0000 0 0x4000>; 1437 clock-names = "se", "core"; 1438 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1439 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&hub_i2c8_data_clk>; 1442 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH 0>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1446 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1447 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1448 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1449 interconnect-names = "qup-core", "qup-config"; 1450 power-domains = <&rpmhpd RPMHPD_CX>; 1451 required-opps = <&rpmhpd_opp_low_svs>; 1452 status = "disabled"; 1453 }; 1454 1455 i2c_hub_9: i2c@9a4000 { 1456 compatible = "qcom,geni-i2c-master-hub"; 1457 reg = <0 0x009a4000 0 0x4000>; 1458 clock-names = "se", "core"; 1459 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1460 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&hub_i2c9_data_clk>; 1463 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH 0>; 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1467 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1468 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1469 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1470 interconnect-names = "qup-core", "qup-config"; 1471 power-domains = <&rpmhpd RPMHPD_CX>; 1472 required-opps = <&rpmhpd_opp_low_svs>; 1473 status = "disabled"; 1474 }; 1475 }; 1476 1477 gpi_dma1: dma-controller@a00000 { 1478 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1479 #dma-cells = <3>; 1480 reg = <0 0x00a00000 0 0x60000>; 1481 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>, 1482 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>, 1483 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>, 1484 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>, 1485 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>, 1486 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>, 1487 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>, 1488 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>, 1489 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>, 1490 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>, 1491 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>, 1492 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 1493 dma-channels = <12>; 1494 dma-channel-mask = <0x1e>; 1495 iommus = <&apps_smmu 0xb6 0>; 1496 dma-coherent; 1497 status = "disabled"; 1498 }; 1499 1500 qupv3_id_0: geniqup@ac0000 { 1501 compatible = "qcom,geni-se-qup"; 1502 reg = <0 0x00ac0000 0 0x2000>; 1503 ranges; 1504 clock-names = "m-ahb", "s-ahb"; 1505 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1506 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1507 iommus = <&apps_smmu 0xa3 0>; 1508 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1509 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 1510 interconnect-names = "qup-core"; 1511 dma-coherent; 1512 #address-cells = <2>; 1513 #size-cells = <2>; 1514 status = "disabled"; 1515 1516 i2c0: i2c@a80000 { 1517 compatible = "qcom,geni-i2c"; 1518 reg = <0 0x00a80000 0 0x4000>; 1519 clock-names = "se"; 1520 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1521 pinctrl-names = "default"; 1522 pinctrl-0 = <&qup_i2c0_data_clk>; 1523 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1524 #address-cells = <1>; 1525 #size-cells = <0>; 1526 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1527 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1528 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1529 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1530 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1531 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1532 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1533 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1534 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1535 dma-names = "tx", "rx"; 1536 power-domains = <&rpmhpd RPMHPD_CX>; 1537 operating-points-v2 = <&qup_opp_table_120mhz>; 1538 status = "disabled"; 1539 }; 1540 1541 spi0: spi@a80000 { 1542 compatible = "qcom,geni-spi"; 1543 reg = <0 0x00a80000 0 0x4000>; 1544 clock-names = "se"; 1545 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1546 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1547 pinctrl-names = "default"; 1548 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1549 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1550 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1551 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1552 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1553 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1554 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1555 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1556 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1557 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1558 dma-names = "tx", "rx"; 1559 power-domains = <&rpmhpd RPMHPD_CX>; 1560 operating-points-v2 = <&qup_opp_table_120mhz>; 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 status = "disabled"; 1564 }; 1565 1566 i2c1: i2c@a84000 { 1567 compatible = "qcom,geni-i2c"; 1568 reg = <0 0x00a84000 0 0x4000>; 1569 clock-names = "se"; 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1571 pinctrl-names = "default"; 1572 pinctrl-0 = <&qup_i2c1_data_clk>; 1573 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 1574 #address-cells = <1>; 1575 #size-cells = <0>; 1576 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1577 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1578 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1579 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1580 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1581 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1582 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1583 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1584 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1585 dma-names = "tx", "rx"; 1586 power-domains = <&rpmhpd RPMHPD_CX>; 1587 operating-points-v2 = <&qup_opp_table_120mhz>; 1588 status = "disabled"; 1589 }; 1590 1591 spi1: spi@a84000 { 1592 compatible = "qcom,geni-spi"; 1593 reg = <0 0x00a84000 0 0x4000>; 1594 clock-names = "se"; 1595 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1596 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 1597 pinctrl-names = "default"; 1598 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1599 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1600 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1601 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1602 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1603 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1604 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1605 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1606 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1607 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1608 dma-names = "tx", "rx"; 1609 power-domains = <&rpmhpd RPMHPD_CX>; 1610 operating-points-v2 = <&qup_opp_table_120mhz>; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 status = "disabled"; 1614 }; 1615 1616 i2c2: i2c@a88000 { 1617 compatible = "qcom,geni-i2c"; 1618 reg = <0 0x00a88000 0 0x4000>; 1619 clock-names = "se"; 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1621 pinctrl-names = "default"; 1622 pinctrl-0 = <&qup_i2c2_data_clk>; 1623 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1624 #address-cells = <1>; 1625 #size-cells = <0>; 1626 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1627 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1628 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1629 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1630 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1631 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1632 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1633 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1634 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1635 dma-names = "tx", "rx"; 1636 power-domains = <&rpmhpd RPMHPD_CX>; 1637 operating-points-v2 = <&qup_opp_table_100mhz>; 1638 status = "disabled"; 1639 }; 1640 1641 spi2: spi@a88000 { 1642 compatible = "qcom,geni-spi"; 1643 reg = <0 0x00a88000 0 0x4000>; 1644 clock-names = "se"; 1645 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1646 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1647 pinctrl-names = "default"; 1648 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1649 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1650 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1651 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1652 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1653 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1654 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1655 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1656 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1657 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1658 dma-names = "tx", "rx"; 1659 power-domains = <&rpmhpd RPMHPD_CX>; 1660 operating-points-v2 = <&qup_opp_table_100mhz>; 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 status = "disabled"; 1664 }; 1665 1666 i2c3: i2c@a8c000 { 1667 compatible = "qcom,geni-i2c"; 1668 reg = <0 0x00a8c000 0 0x4000>; 1669 clock-names = "se"; 1670 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1671 pinctrl-names = "default"; 1672 pinctrl-0 = <&qup_i2c3_data_clk>; 1673 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1677 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1678 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1679 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1680 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1681 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1682 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1683 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1684 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1685 dma-names = "tx", "rx"; 1686 power-domains = <&rpmhpd RPMHPD_CX>; 1687 operating-points-v2 = <&qup_opp_table_100mhz>; 1688 status = "disabled"; 1689 }; 1690 1691 spi3: spi@a8c000 { 1692 compatible = "qcom,geni-spi"; 1693 reg = <0 0x00a8c000 0 0x4000>; 1694 clock-names = "se"; 1695 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1696 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1697 pinctrl-names = "default"; 1698 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1699 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1700 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1701 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1702 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1703 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1704 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1705 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1706 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1707 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1708 dma-names = "tx", "rx"; 1709 power-domains = <&rpmhpd RPMHPD_CX>; 1710 operating-points-v2 = <&qup_opp_table_100mhz>; 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 status = "disabled"; 1714 }; 1715 1716 i2c4: i2c@a90000 { 1717 compatible = "qcom,geni-i2c"; 1718 reg = <0 0x00a90000 0 0x4000>; 1719 clock-names = "se"; 1720 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1721 pinctrl-names = "default"; 1722 pinctrl-0 = <&qup_i2c4_data_clk>; 1723 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; 1724 #address-cells = <1>; 1725 #size-cells = <0>; 1726 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1727 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1728 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1729 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1730 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1731 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1732 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1733 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1734 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1735 dma-names = "tx", "rx"; 1736 power-domains = <&rpmhpd RPMHPD_CX>; 1737 operating-points-v2 = <&qup_opp_table_100mhz>; 1738 status = "disabled"; 1739 }; 1740 1741 spi4: spi@a90000 { 1742 compatible = "qcom,geni-spi"; 1743 reg = <0 0x00a90000 0 0x4000>; 1744 clock-names = "se"; 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1746 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; 1747 pinctrl-names = "default"; 1748 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1749 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1750 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1751 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1752 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1753 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1754 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1755 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1756 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1757 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1758 dma-names = "tx", "rx"; 1759 power-domains = <&rpmhpd RPMHPD_CX>; 1760 operating-points-v2 = <&qup_opp_table_100mhz>; 1761 #address-cells = <1>; 1762 #size-cells = <0>; 1763 status = "disabled"; 1764 }; 1765 1766 i2c5: i2c@a94000 { 1767 compatible = "qcom,geni-i2c"; 1768 reg = <0 0x00a94000 0 0x4000>; 1769 clock-names = "se"; 1770 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1771 pinctrl-names = "default"; 1772 pinctrl-0 = <&qup_i2c5_data_clk>; 1773 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; 1774 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1775 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1776 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1777 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1778 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1779 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1780 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1781 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1782 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1783 dma-names = "tx", "rx"; 1784 power-domains = <&rpmhpd RPMHPD_CX>; 1785 operating-points-v2 = <&qup_opp_table_100mhz>; 1786 #address-cells = <1>; 1787 #size-cells = <0>; 1788 status = "disabled"; 1789 }; 1790 1791 spi5: spi@a94000 { 1792 compatible = "qcom,geni-spi"; 1793 reg = <0 0x00a94000 0 0x4000>; 1794 clock-names = "se"; 1795 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1796 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; 1797 pinctrl-names = "default"; 1798 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1799 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1800 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1801 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1802 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1803 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1804 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1805 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1806 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1807 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1808 dma-names = "tx", "rx"; 1809 power-domains = <&rpmhpd RPMHPD_CX>; 1810 operating-points-v2 = <&qup_opp_table_100mhz>; 1811 #address-cells = <1>; 1812 #size-cells = <0>; 1813 status = "disabled"; 1814 }; 1815 1816 i2c6: i2c@a98000 { 1817 compatible = "qcom,geni-i2c"; 1818 reg = <0 0x00a98000 0 0x4000>; 1819 clock-names = "se"; 1820 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1821 pinctrl-names = "default"; 1822 pinctrl-0 = <&qup_i2c6_data_clk>; 1823 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 1824 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1825 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1826 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1827 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1828 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1829 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1830 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1831 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1832 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1833 dma-names = "tx", "rx"; 1834 power-domains = <&rpmhpd RPMHPD_CX>; 1835 operating-points-v2 = <&qup_opp_table_100mhz>; 1836 #address-cells = <1>; 1837 #size-cells = <0>; 1838 status = "disabled"; 1839 }; 1840 1841 spi6: spi@a98000 { 1842 compatible = "qcom,geni-spi"; 1843 reg = <0 0x00a98000 0 0x4000>; 1844 clock-names = "se"; 1845 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1846 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 1847 pinctrl-names = "default"; 1848 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1849 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1850 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1851 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1852 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1853 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1854 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1855 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1856 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1857 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1858 dma-names = "tx", "rx"; 1859 power-domains = <&rpmhpd RPMHPD_CX>; 1860 operating-points-v2 = <&qup_opp_table_100mhz>; 1861 #address-cells = <1>; 1862 #size-cells = <0>; 1863 status = "disabled"; 1864 }; 1865 1866 uart7: serial@a9c000 { 1867 compatible = "qcom,geni-debug-uart"; 1868 reg = <0 0x00a9c000 0 0x4000>; 1869 clock-names = "se"; 1870 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1871 pinctrl-names = "default"; 1872 pinctrl-0 = <&qup_uart7_default>; 1873 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>; 1874 interconnect-names = "qup-core", "qup-config"; 1875 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1876 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1877 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1878 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1879 power-domains = <&rpmhpd RPMHPD_CX>; 1880 operating-points-v2 = <&qup_opp_table_100mhz>; 1881 status = "disabled"; 1882 }; 1883 }; 1884 1885 cnoc_main: interconnect@1500000 { 1886 compatible = "qcom,sm8550-cnoc-main"; 1887 reg = <0 0x01500000 0 0x13080>; 1888 #interconnect-cells = <2>; 1889 qcom,bcm-voters = <&apps_bcm_voter>; 1890 }; 1891 1892 config_noc: interconnect@1600000 { 1893 compatible = "qcom,sm8550-config-noc"; 1894 reg = <0 0x01600000 0 0x6200>; 1895 #interconnect-cells = <2>; 1896 qcom,bcm-voters = <&apps_bcm_voter>; 1897 }; 1898 1899 system_noc: interconnect@1680000 { 1900 compatible = "qcom,sm8550-system-noc"; 1901 reg = <0 0x01680000 0 0x1d080>; 1902 #interconnect-cells = <2>; 1903 qcom,bcm-voters = <&apps_bcm_voter>; 1904 }; 1905 1906 pcie_noc: interconnect@16c0000 { 1907 compatible = "qcom,sm8550-pcie-anoc"; 1908 reg = <0 0x016c0000 0 0x12200>; 1909 #interconnect-cells = <2>; 1910 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1911 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1912 qcom,bcm-voters = <&apps_bcm_voter>; 1913 }; 1914 1915 aggre1_noc: interconnect@16e0000 { 1916 compatible = "qcom,sm8550-aggre1-noc"; 1917 reg = <0 0x016e0000 0 0x14400>; 1918 #interconnect-cells = <2>; 1919 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1920 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1921 qcom,bcm-voters = <&apps_bcm_voter>; 1922 }; 1923 1924 aggre2_noc: interconnect@1700000 { 1925 compatible = "qcom,sm8550-aggre2-noc"; 1926 reg = <0 0x01700000 0 0x1e400>; 1927 #interconnect-cells = <2>; 1928 clocks = <&rpmhcc RPMH_IPA_CLK>; 1929 qcom,bcm-voters = <&apps_bcm_voter>; 1930 }; 1931 1932 mmss_noc: interconnect@1780000 { 1933 compatible = "qcom,sm8550-mmss-noc"; 1934 reg = <0 0x01780000 0 0x5b800>; 1935 #interconnect-cells = <2>; 1936 qcom,bcm-voters = <&apps_bcm_voter>; 1937 }; 1938 1939 rng: rng@10c3000 { 1940 compatible = "qcom,sm8550-trng", "qcom,trng"; 1941 reg = <0 0x010c3000 0 0x1000>; 1942 }; 1943 1944 pcie0: pcie@1c00000 { 1945 device_type = "pci"; 1946 compatible = "qcom,pcie-sm8550"; 1947 reg = <0 0x01c00000 0 0x3000>, 1948 <0 0x60000000 0 0xf1d>, 1949 <0 0x60000f20 0 0xa8>, 1950 <0 0x60001000 0 0x1000>, 1951 <0 0x60100000 0 0x100000>; 1952 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1953 #address-cells = <3>; 1954 #size-cells = <2>; 1955 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1956 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1957 bus-range = <0x00 0xff>; 1958 1959 dma-coherent; 1960 1961 linux,pci-domain = <0>; 1962 num-lanes = <2>; 1963 1964 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>, 1965 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>, 1966 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>, 1967 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>, 1968 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>, 1969 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>, 1970 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>, 1971 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>, 1972 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>; 1973 interrupt-names = "msi0", 1974 "msi1", 1975 "msi2", 1976 "msi3", 1977 "msi4", 1978 "msi5", 1979 "msi6", 1980 "msi7", 1981 "global"; 1982 #interrupt-cells = <1>; 1983 interrupt-map-mask = <0 0 0 0x7>; 1984 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */ 1985 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ 1986 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ 1987 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ 1988 1989 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1990 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1991 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1992 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1993 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1994 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1995 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1996 clock-names = "aux", 1997 "cfg", 1998 "bus_master", 1999 "bus_slave", 2000 "slave_q2a", 2001 "ddrss_sf_tbu", 2002 "noc_aggr"; 2003 2004 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2005 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2006 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2007 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2008 interconnect-names = "pcie-mem", "cpu-pcie"; 2009 2010 msi-map = <0x0 &gic_its 0x1400 0x1>, 2011 <0x100 &gic_its 0x1401 0x1>; 2012 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 2013 <0x100 &apps_smmu 0x1401 0x1>; 2014 2015 resets = <&gcc GCC_PCIE_0_BCR>; 2016 reset-names = "pci"; 2017 2018 power-domains = <&gcc PCIE_0_GDSC>; 2019 2020 phys = <&pcie0_phy>; 2021 phy-names = "pciephy"; 2022 2023 operating-points-v2 = <&pcie0_opp_table>; 2024 2025 status = "disabled"; 2026 2027 pcie0_opp_table: opp-table { 2028 compatible = "operating-points-v2"; 2029 2030 /* GEN 1 x1 */ 2031 opp-2500000 { 2032 opp-hz = /bits/ 64 <2500000>; 2033 required-opps = <&rpmhpd_opp_low_svs>; 2034 opp-peak-kBps = <250000 1>; 2035 }; 2036 2037 /* GEN 1 x2 and GEN 2 x1 */ 2038 opp-5000000 { 2039 opp-hz = /bits/ 64 <5000000>; 2040 required-opps = <&rpmhpd_opp_low_svs>; 2041 opp-peak-kBps = <500000 1>; 2042 }; 2043 2044 /* GEN 2 x2 */ 2045 opp-10000000 { 2046 opp-hz = /bits/ 64 <10000000>; 2047 required-opps = <&rpmhpd_opp_low_svs>; 2048 opp-peak-kBps = <1000000 1>; 2049 }; 2050 2051 /* GEN 3 x1 */ 2052 opp-8000000 { 2053 opp-hz = /bits/ 64 <8000000>; 2054 required-opps = <&rpmhpd_opp_nom>; 2055 opp-peak-kBps = <984500 1>; 2056 }; 2057 2058 /* GEN 3 x2 */ 2059 opp-16000000 { 2060 opp-hz = /bits/ 64 <16000000>; 2061 required-opps = <&rpmhpd_opp_nom>; 2062 opp-peak-kBps = <1969000 1>; 2063 }; 2064 }; 2065 2066 pcieport0: pcie@0 { 2067 device_type = "pci"; 2068 reg = <0x0 0x0 0x0 0x0 0x0>; 2069 bus-range = <0x01 0xff>; 2070 2071 #address-cells = <3>; 2072 #size-cells = <2>; 2073 ranges; 2074 }; 2075 }; 2076 2077 pcie0_phy: phy@1c06000 { 2078 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 2079 reg = <0 0x01c06000 0 0x2000>; 2080 2081 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2082 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2083 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 2084 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2085 <&gcc GCC_PCIE_0_PIPE_CLK>; 2086 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2087 "pipe"; 2088 2089 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2090 reset-names = "phy"; 2091 2092 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2093 assigned-clock-rates = <100000000>; 2094 2095 power-domains = <&gcc PCIE_0_PHY_GDSC>; 2096 2097 #clock-cells = <0>; 2098 clock-output-names = "pcie0_pipe_clk"; 2099 2100 #phy-cells = <0>; 2101 2102 status = "disabled"; 2103 }; 2104 2105 pcie1: pcie@1c08000 { 2106 device_type = "pci"; 2107 compatible = "qcom,pcie-sm8550"; 2108 reg = <0x0 0x01c08000 0x0 0x3000>, 2109 <0x0 0x40000000 0x0 0xf1d>, 2110 <0x0 0x40000f20 0x0 0xa8>, 2111 <0x0 0x40001000 0x0 0x1000>, 2112 <0x0 0x40100000 0x0 0x100000>; 2113 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2114 #address-cells = <3>; 2115 #size-cells = <2>; 2116 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2117 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2118 bus-range = <0x00 0xff>; 2119 2120 dma-coherent; 2121 2122 linux,pci-domain = <1>; 2123 num-lanes = <2>; 2124 2125 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>, 2126 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>, 2127 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>, 2128 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 0>, 2129 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>, 2130 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 0>, 2131 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, 2132 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH 0>, 2133 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 2134 interrupt-names = "msi0", 2135 "msi1", 2136 "msi2", 2137 "msi3", 2138 "msi4", 2139 "msi5", 2140 "msi6", 2141 "msi7", 2142 "global"; 2143 #interrupt-cells = <1>; 2144 interrupt-map-mask = <0 0 0 0x7>; 2145 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */ 2146 <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ 2147 <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ 2148 <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ 2149 2150 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2151 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2152 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2153 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2154 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2155 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2156 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2157 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2158 clock-names = "aux", 2159 "cfg", 2160 "bus_master", 2161 "bus_slave", 2162 "slave_q2a", 2163 "ddrss_sf_tbu", 2164 "noc_aggr", 2165 "cnoc_sf_axi"; 2166 2167 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2168 assigned-clock-rates = <19200000>; 2169 2170 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2171 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2172 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2173 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2174 interconnect-names = "pcie-mem", "cpu-pcie"; 2175 2176 msi-map = <0x0 &gic_its 0x1480 0x1>, 2177 <0x100 &gic_its 0x1481 0x1>; 2178 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 2179 <0x100 &apps_smmu 0x1481 0x1>; 2180 2181 resets = <&gcc GCC_PCIE_1_BCR>, 2182 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2183 reset-names = "pci", "link_down"; 2184 2185 power-domains = <&gcc PCIE_1_GDSC>; 2186 2187 phys = <&pcie1_phy>; 2188 phy-names = "pciephy"; 2189 2190 operating-points-v2 = <&pcie1_opp_table>; 2191 2192 status = "disabled"; 2193 2194 pcie1_opp_table: opp-table { 2195 compatible = "operating-points-v2"; 2196 2197 /* GEN 1 x1 */ 2198 opp-2500000 { 2199 opp-hz = /bits/ 64 <2500000>; 2200 required-opps = <&rpmhpd_opp_low_svs>; 2201 opp-peak-kBps = <250000 1>; 2202 }; 2203 2204 /* GEN 1 x2 and GEN 2 x1 */ 2205 opp-5000000 { 2206 opp-hz = /bits/ 64 <5000000>; 2207 required-opps = <&rpmhpd_opp_low_svs>; 2208 opp-peak-kBps = <500000 1>; 2209 }; 2210 2211 /* GEN 2 x2 */ 2212 opp-10000000 { 2213 opp-hz = /bits/ 64 <10000000>; 2214 required-opps = <&rpmhpd_opp_low_svs>; 2215 opp-peak-kBps = <1000000 1>; 2216 }; 2217 2218 /* GEN 3 x1 */ 2219 opp-8000000 { 2220 opp-hz = /bits/ 64 <8000000>; 2221 required-opps = <&rpmhpd_opp_nom>; 2222 opp-peak-kBps = <984500 1>; 2223 }; 2224 2225 /* GEN 3 x2 and GEN 4 x1 */ 2226 opp-16000000 { 2227 opp-hz = /bits/ 64 <16000000>; 2228 required-opps = <&rpmhpd_opp_nom>; 2229 opp-peak-kBps = <1969000 1>; 2230 }; 2231 2232 /* GEN 4 x2 */ 2233 opp-32000000 { 2234 opp-hz = /bits/ 64 <32000000>; 2235 required-opps = <&rpmhpd_opp_nom>; 2236 opp-peak-kBps = <3938000 1>; 2237 }; 2238 }; 2239 2240 pcie@0 { 2241 device_type = "pci"; 2242 reg = <0x0 0x0 0x0 0x0 0x0>; 2243 bus-range = <0x01 0xff>; 2244 2245 #address-cells = <3>; 2246 #size-cells = <2>; 2247 ranges; 2248 }; 2249 }; 2250 2251 pcie1_phy: phy@1c0e000 { 2252 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 2253 reg = <0x0 0x01c0e000 0x0 0x2000>; 2254 2255 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2256 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2257 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 2258 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2259 <&gcc GCC_PCIE_1_PIPE_CLK>; 2260 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2261 "pipe"; 2262 2263 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 2264 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 2265 reset-names = "phy", "phy_nocsr"; 2266 2267 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2268 assigned-clock-rates = <100000000>; 2269 2270 power-domains = <&gcc PCIE_1_PHY_GDSC>; 2271 2272 #clock-cells = <1>; 2273 clock-output-names = "pcie1_pipe_clk"; 2274 2275 #phy-cells = <0>; 2276 2277 status = "disabled"; 2278 }; 2279 2280 cryptobam: dma-controller@1dc4000 { 2281 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2282 reg = <0x0 0x01dc4000 0x0 0x28000>; 2283 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; 2284 #dma-cells = <1>; 2285 qcom,ee = <0>; 2286 qcom,num-ees = <4>; 2287 num-channels = <20>; 2288 qcom,controlled-remotely; 2289 iommus = <&apps_smmu 0x480 0x0>, 2290 <&apps_smmu 0x481 0x0>; 2291 }; 2292 2293 crypto: crypto@1dfa000 { 2294 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 2295 reg = <0x0 0x01dfa000 0x0 0x6000>; 2296 dmas = <&cryptobam 4>, <&cryptobam 5>; 2297 dma-names = "rx", "tx"; 2298 iommus = <&apps_smmu 0x480 0x0>, 2299 <&apps_smmu 0x481 0x0>; 2300 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 2301 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2302 interconnect-names = "memory"; 2303 }; 2304 2305 ufs_mem_phy: phy@1d80000 { 2306 compatible = "qcom,sm8550-qmp-ufs-phy"; 2307 reg = <0x0 0x01d80000 0x0 0x2000>; 2308 clocks = <&rpmhcc RPMH_CXO_CLK>, 2309 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2310 <&tcsr TCSR_UFS_CLKREF_EN>; 2311 clock-names = "ref", 2312 "ref_aux", 2313 "qref"; 2314 2315 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 2316 2317 resets = <&ufs_mem_hc 0>; 2318 reset-names = "ufsphy"; 2319 2320 #clock-cells = <1>; 2321 #phy-cells = <0>; 2322 2323 status = "disabled"; 2324 }; 2325 2326 ufs_mem_hc: ufshc@1d84000 { 2327 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 2328 "jedec,ufs-2.0"; 2329 reg = <0x0 0x01d84000 0x0 0x3000>; 2330 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 2331 phys = <&ufs_mem_phy>; 2332 phy-names = "ufsphy"; 2333 lanes-per-direction = <2>; 2334 #reset-cells = <1>; 2335 resets = <&gcc GCC_UFS_PHY_BCR>; 2336 reset-names = "rst"; 2337 2338 power-domains = <&gcc UFS_PHY_GDSC>; 2339 required-opps = <&rpmhpd_opp_nom>; 2340 2341 iommus = <&apps_smmu 0x60 0x0>; 2342 dma-coherent; 2343 2344 operating-points-v2 = <&ufs_opp_table>; 2345 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2346 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2347 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2348 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2349 2350 interconnect-names = "ufs-ddr", "cpu-ufs"; 2351 clock-names = "core_clk", 2352 "bus_aggr_clk", 2353 "iface_clk", 2354 "core_clk_unipro", 2355 "ref_clk", 2356 "tx_lane0_sync_clk", 2357 "rx_lane0_sync_clk", 2358 "rx_lane1_sync_clk"; 2359 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2360 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2361 <&gcc GCC_UFS_PHY_AHB_CLK>, 2362 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2363 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 2364 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2365 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2366 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2367 qcom,ice = <&ice>; 2368 2369 status = "disabled"; 2370 2371 ufs_opp_table: opp-table { 2372 compatible = "operating-points-v2"; 2373 2374 opp-75000000 { 2375 opp-hz = /bits/ 64 <75000000>, 2376 /bits/ 64 <0>, 2377 /bits/ 64 <0>, 2378 /bits/ 64 <75000000>, 2379 /bits/ 64 <0>, 2380 /bits/ 64 <0>, 2381 /bits/ 64 <0>, 2382 /bits/ 64 <0>; 2383 required-opps = <&rpmhpd_opp_low_svs>; 2384 }; 2385 2386 opp-150000000 { 2387 opp-hz = /bits/ 64 <150000000>, 2388 /bits/ 64 <0>, 2389 /bits/ 64 <0>, 2390 /bits/ 64 <150000000>, 2391 /bits/ 64 <0>, 2392 /bits/ 64 <0>, 2393 /bits/ 64 <0>, 2394 /bits/ 64 <0>; 2395 required-opps = <&rpmhpd_opp_svs>; 2396 }; 2397 2398 opp-300000000 { 2399 opp-hz = /bits/ 64 <300000000>, 2400 /bits/ 64 <0>, 2401 /bits/ 64 <0>, 2402 /bits/ 64 <300000000>, 2403 /bits/ 64 <0>, 2404 /bits/ 64 <0>, 2405 /bits/ 64 <0>, 2406 /bits/ 64 <0>; 2407 required-opps = <&rpmhpd_opp_nom>; 2408 }; 2409 }; 2410 }; 2411 2412 ice: crypto@1d88000 { 2413 compatible = "qcom,sm8550-inline-crypto-engine", 2414 "qcom,inline-crypto-engine"; 2415 reg = <0 0x01d88000 0 0x18000>; 2416 2417 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2418 }; 2419 2420 tcsr_mutex: hwlock@1f40000 { 2421 compatible = "qcom,tcsr-mutex"; 2422 reg = <0 0x01f40000 0 0x20000>; 2423 #hwlock-cells = <1>; 2424 }; 2425 2426 tcsr: clock-controller@1fc0000 { 2427 compatible = "qcom,sm8550-tcsr", "syscon"; 2428 reg = <0 0x01fc0000 0 0x30000>; 2429 clocks = <&rpmhcc RPMH_CXO_CLK>; 2430 #clock-cells = <1>; 2431 #reset-cells = <1>; 2432 }; 2433 2434 gpu: gpu@3d00000 { 2435 compatible = "qcom,adreno-43050a01", "qcom,adreno"; 2436 reg = <0x0 0x03d00000 0x0 0x40000>, 2437 <0x0 0x03d9e000 0x0 0x1000>, 2438 <0x0 0x03d61000 0x0 0x800>; 2439 reg-names = "kgsl_3d0_reg_memory", 2440 "cx_mem", 2441 "cx_dbgc"; 2442 2443 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; 2444 2445 iommus = <&adreno_smmu 0 0x0>, 2446 <&adreno_smmu 1 0x0>; 2447 2448 operating-points-v2 = <&gpu_opp_table>; 2449 2450 qcom,gmu = <&gmu>; 2451 #cooling-cells = <2>; 2452 2453 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 2454 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2455 interconnect-names = "gfx-mem"; 2456 2457 status = "disabled"; 2458 2459 zap-shader { 2460 memory-region = <&gpu_micro_code_mem>; 2461 }; 2462 2463 /* Speedbin needs more work on A740+, keep only lower freqs */ 2464 gpu_opp_table: opp-table { 2465 compatible = "operating-points-v2"; 2466 2467 opp-680000000 { 2468 opp-hz = /bits/ 64 <680000000>; 2469 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2470 opp-peak-kBps = <16500000>; 2471 }; 2472 2473 opp-615000000 { 2474 opp-hz = /bits/ 64 <615000000>; 2475 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2476 opp-peak-kBps = <12449218>; 2477 }; 2478 2479 opp-550000000 { 2480 opp-hz = /bits/ 64 <550000000>; 2481 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2482 opp-peak-kBps = <10687500>; 2483 }; 2484 2485 opp-475000000 { 2486 opp-hz = /bits/ 64 <475000000>; 2487 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2488 opp-peak-kBps = <6074218>; 2489 }; 2490 2491 opp-401000000 { 2492 opp-hz = /bits/ 64 <401000000>; 2493 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2494 opp-peak-kBps = <6074218>; 2495 }; 2496 2497 opp-348000000 { 2498 opp-hz = /bits/ 64 <348000000>; 2499 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 2500 opp-peak-kBps = <6074218>; 2501 }; 2502 2503 opp-295000000 { 2504 opp-hz = /bits/ 64 <295000000>; 2505 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2506 opp-peak-kBps = <6074218>; 2507 }; 2508 2509 opp-220000000 { 2510 opp-hz = /bits/ 64 <220000000>; 2511 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 2512 opp-peak-kBps = <2136718>; 2513 }; 2514 }; 2515 }; 2516 2517 gmu: gmu@3d6a000 { 2518 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu"; 2519 reg = <0x0 0x03d6a000 0x0 0x35000>, 2520 <0x0 0x03d50000 0x0 0x10000>, 2521 <0x0 0x0b280000 0x0 0x10000>; 2522 reg-names = "gmu", "rscc", "gmu_pdc"; 2523 2524 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>, 2525 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 2526 interrupt-names = "hfi", "gmu"; 2527 2528 clocks = <&gpucc GPU_CC_AHB_CLK>, 2529 <&gpucc GPU_CC_CX_GMU_CLK>, 2530 <&gpucc GPU_CC_CXO_CLK>, 2531 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2532 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2533 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2534 <&gpucc GPU_CC_DEMET_CLK>; 2535 clock-names = "ahb", 2536 "gmu", 2537 "cxo", 2538 "axi", 2539 "memnoc", 2540 "hub", 2541 "demet"; 2542 2543 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2544 <&gpucc GPU_CC_GX_GDSC>; 2545 power-domain-names = "cx", 2546 "gx"; 2547 2548 iommus = <&adreno_smmu 5 0x0>; 2549 2550 qcom,qmp = <&aoss_qmp>; 2551 2552 operating-points-v2 = <&gmu_opp_table>; 2553 2554 gmu_opp_table: opp-table { 2555 compatible = "operating-points-v2"; 2556 2557 opp-500000000 { 2558 opp-hz = /bits/ 64 <500000000>; 2559 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2560 }; 2561 2562 opp-200000000 { 2563 opp-hz = /bits/ 64 <200000000>; 2564 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2565 }; 2566 }; 2567 }; 2568 2569 gpucc: clock-controller@3d90000 { 2570 compatible = "qcom,sm8550-gpucc"; 2571 reg = <0 0x03d90000 0 0xa000>; 2572 clocks = <&bi_tcxo_div2>, 2573 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2574 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2575 #clock-cells = <1>; 2576 #reset-cells = <1>; 2577 #power-domain-cells = <1>; 2578 }; 2579 2580 adreno_smmu: iommu@3da0000 { 2581 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", 2582 "qcom,smmu-500", "arm,mmu-500"; 2583 reg = <0x0 0x03da0000 0x0 0x40000>; 2584 #iommu-cells = <2>; 2585 #global-interrupts = <1>; 2586 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>, 2587 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>, 2588 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>, 2589 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>, 2590 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>, 2591 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>, 2592 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>, 2593 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>, 2594 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>, 2595 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>, 2596 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>, 2597 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>, 2598 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>, 2599 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>, 2600 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>, 2601 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>, 2602 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>, 2603 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>, 2604 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>, 2605 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>, 2606 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, 2607 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>, 2608 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>, 2609 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>, 2610 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>, 2611 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>; 2612 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2613 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2614 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2615 <&gpucc GPU_CC_AHB_CLK>; 2616 clock-names = "hlos", 2617 "bus", 2618 "iface", 2619 "ahb"; 2620 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2621 dma-coherent; 2622 }; 2623 2624 ipa: ipa@3f40000 { 2625 compatible = "qcom,sm8550-ipa"; 2626 2627 iommus = <&apps_smmu 0x4a0 0x0>, 2628 <&apps_smmu 0x4a2 0x0>; 2629 reg = <0 0x3f40000 0 0x10000>, 2630 <0 0x3f50000 0 0x5000>, 2631 <0 0x3e04000 0 0xfc000>; 2632 reg-names = "ipa-reg", 2633 "ipa-shared", 2634 "gsi"; 2635 2636 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>, 2637 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>, 2638 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2639 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2640 interrupt-names = "ipa", 2641 "gsi", 2642 "ipa-clock-query", 2643 "ipa-setup-ready"; 2644 2645 clocks = <&rpmhcc RPMH_IPA_CLK>; 2646 clock-names = "core"; 2647 2648 interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS 2649 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2650 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2651 &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2652 interconnect-names = "memory", 2653 "config"; 2654 2655 qcom,qmp = <&aoss_qmp>; 2656 2657 qcom,smem-states = <&ipa_smp2p_out 0>, 2658 <&ipa_smp2p_out 1>; 2659 qcom,smem-state-names = "ipa-clock-enabled-valid", 2660 "ipa-clock-enabled"; 2661 2662 status = "disabled"; 2663 }; 2664 2665 remoteproc_mpss: remoteproc@4080000 { 2666 compatible = "qcom,sm8550-mpss-pas"; 2667 reg = <0x0 0x04080000 0x0 0x10000>; 2668 2669 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, 2670 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2671 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2672 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2673 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2674 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2675 interrupt-names = "wdog", "fatal", "ready", "handover", 2676 "stop-ack", "shutdown-ack"; 2677 2678 clocks = <&rpmhcc RPMH_CXO_CLK>; 2679 clock-names = "xo"; 2680 2681 power-domains = <&rpmhpd RPMHPD_CX>, 2682 <&rpmhpd RPMHPD_MSS>; 2683 power-domain-names = "cx", "mss"; 2684 2685 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 2686 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2687 2688 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 2689 2690 qcom,qmp = <&aoss_qmp>; 2691 2692 qcom,smem-states = <&smp2p_modem_out 0>; 2693 qcom,smem-state-names = "stop"; 2694 2695 status = "disabled"; 2696 2697 glink-edge { 2698 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2699 IPCC_MPROC_SIGNAL_GLINK_QMP 2700 IRQ_TYPE_EDGE_RISING>; 2701 mboxes = <&ipcc IPCC_CLIENT_MPSS 2702 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2703 label = "mpss"; 2704 qcom,remote-pid = <1>; 2705 }; 2706 }; 2707 2708 remoteproc_adsp: remoteproc@6800000 { 2709 compatible = "qcom,sm8550-adsp-pas"; 2710 reg = <0x0 0x06800000 0x0 0x10000>; 2711 2712 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2713 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2714 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2715 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2716 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2717 interrupt-names = "wdog", "fatal", "ready", 2718 "handover", "stop-ack"; 2719 2720 clocks = <&rpmhcc RPMH_CXO_CLK>; 2721 clock-names = "xo"; 2722 2723 power-domains = <&rpmhpd RPMHPD_LCX>, 2724 <&rpmhpd RPMHPD_LMX>; 2725 power-domain-names = "lcx", "lmx"; 2726 2727 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 2728 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2729 2730 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2731 2732 qcom,qmp = <&aoss_qmp>; 2733 2734 qcom,smem-states = <&smp2p_adsp_out 0>; 2735 qcom,smem-state-names = "stop"; 2736 2737 status = "disabled"; 2738 2739 remoteproc_adsp_glink: glink-edge { 2740 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2741 IPCC_MPROC_SIGNAL_GLINK_QMP 2742 IRQ_TYPE_EDGE_RISING>; 2743 mboxes = <&ipcc IPCC_CLIENT_LPASS 2744 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2745 2746 label = "lpass"; 2747 qcom,remote-pid = <2>; 2748 2749 fastrpc { 2750 compatible = "qcom,fastrpc"; 2751 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2752 label = "adsp"; 2753 qcom,non-secure-domain; 2754 #address-cells = <1>; 2755 #size-cells = <0>; 2756 2757 compute-cb@3 { 2758 compatible = "qcom,fastrpc-compute-cb"; 2759 reg = <3>; 2760 iommus = <&apps_smmu 0x1003 0x80>, 2761 <&apps_smmu 0x1063 0x0>; 2762 dma-coherent; 2763 }; 2764 2765 compute-cb@4 { 2766 compatible = "qcom,fastrpc-compute-cb"; 2767 reg = <4>; 2768 iommus = <&apps_smmu 0x1004 0x80>, 2769 <&apps_smmu 0x1064 0x0>; 2770 dma-coherent; 2771 }; 2772 2773 compute-cb@5 { 2774 compatible = "qcom,fastrpc-compute-cb"; 2775 reg = <5>; 2776 iommus = <&apps_smmu 0x1005 0x80>, 2777 <&apps_smmu 0x1065 0x0>; 2778 dma-coherent; 2779 }; 2780 2781 compute-cb@6 { 2782 compatible = "qcom,fastrpc-compute-cb"; 2783 reg = <6>; 2784 iommus = <&apps_smmu 0x1006 0x80>, 2785 <&apps_smmu 0x1066 0x0>; 2786 dma-coherent; 2787 }; 2788 2789 compute-cb@7 { 2790 compatible = "qcom,fastrpc-compute-cb"; 2791 reg = <7>; 2792 iommus = <&apps_smmu 0x1007 0x80>, 2793 <&apps_smmu 0x1067 0x0>; 2794 dma-coherent; 2795 }; 2796 }; 2797 2798 gpr { 2799 compatible = "qcom,gpr"; 2800 qcom,glink-channels = "adsp_apps"; 2801 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2802 qcom,intents = <512 20>; 2803 #address-cells = <1>; 2804 #size-cells = <0>; 2805 2806 q6apm: service@1 { 2807 compatible = "qcom,q6apm"; 2808 reg = <GPR_APM_MODULE_IID>; 2809 #sound-dai-cells = <0>; 2810 qcom,protection-domain = "avs/audio", 2811 "msm/adsp/audio_pd"; 2812 2813 q6apmdai: dais { 2814 compatible = "qcom,q6apm-dais"; 2815 iommus = <&apps_smmu 0x1001 0x80>, 2816 <&apps_smmu 0x1061 0x0>; 2817 }; 2818 2819 q6apmbedai: bedais { 2820 compatible = "qcom,q6apm-lpass-dais"; 2821 #sound-dai-cells = <1>; 2822 }; 2823 }; 2824 2825 q6prm: service@2 { 2826 compatible = "qcom,q6prm"; 2827 reg = <GPR_PRM_MODULE_IID>; 2828 qcom,protection-domain = "avs/audio", 2829 "msm/adsp/audio_pd"; 2830 2831 q6prmcc: clock-controller { 2832 compatible = "qcom,q6prm-lpass-clocks"; 2833 #clock-cells = <2>; 2834 }; 2835 }; 2836 }; 2837 }; 2838 }; 2839 2840 lpass_wsa2macro: codec@6aa0000 { 2841 compatible = "qcom,sm8550-lpass-wsa-macro"; 2842 reg = <0 0x06aa0000 0 0x1000>; 2843 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2844 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2845 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2846 <&lpass_vamacro>; 2847 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2848 2849 #clock-cells = <0>; 2850 clock-output-names = "wsa2-mclk"; 2851 #sound-dai-cells = <1>; 2852 }; 2853 2854 swr3: soundwire@6ab0000 { 2855 compatible = "qcom,soundwire-v2.0.0"; 2856 reg = <0 0x06ab0000 0 0x10000>; 2857 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 2858 clocks = <&lpass_wsa2macro>; 2859 clock-names = "iface"; 2860 label = "WSA2"; 2861 2862 pinctrl-0 = <&wsa2_swr_active>; 2863 pinctrl-names = "default"; 2864 2865 qcom,din-ports = <4>; 2866 qcom,dout-ports = <9>; 2867 2868 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2869 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2870 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2871 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2872 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2873 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2874 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2875 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2876 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2877 2878 #address-cells = <2>; 2879 #size-cells = <0>; 2880 #sound-dai-cells = <1>; 2881 status = "disabled"; 2882 }; 2883 2884 lpass_rxmacro: codec@6ac0000 { 2885 compatible = "qcom,sm8550-lpass-rx-macro"; 2886 reg = <0 0x06ac0000 0 0x1000>; 2887 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2888 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2889 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2890 <&lpass_vamacro>; 2891 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2892 2893 #clock-cells = <0>; 2894 clock-output-names = "mclk"; 2895 #sound-dai-cells = <1>; 2896 }; 2897 2898 swr1: soundwire@6ad0000 { 2899 compatible = "qcom,soundwire-v2.0.0"; 2900 reg = <0 0x06ad0000 0 0x10000>; 2901 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 2902 clocks = <&lpass_rxmacro>; 2903 clock-names = "iface"; 2904 label = "RX"; 2905 2906 pinctrl-0 = <&rx_swr_active>; 2907 pinctrl-names = "default"; 2908 2909 qcom,din-ports = <1>; 2910 qcom,dout-ports = <11>; 2911 2912 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>; 2913 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2914 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2915 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2916 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2917 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>; 2918 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2919 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2920 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2921 2922 #address-cells = <2>; 2923 #size-cells = <0>; 2924 #sound-dai-cells = <1>; 2925 status = "disabled"; 2926 }; 2927 2928 lpass_txmacro: codec@6ae0000 { 2929 compatible = "qcom,sm8550-lpass-tx-macro"; 2930 reg = <0 0x06ae0000 0 0x1000>; 2931 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2932 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2933 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2934 <&lpass_vamacro>; 2935 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2936 2937 #clock-cells = <0>; 2938 clock-output-names = "mclk"; 2939 #sound-dai-cells = <1>; 2940 }; 2941 2942 lpass_wsamacro: codec@6b00000 { 2943 compatible = "qcom,sm8550-lpass-wsa-macro"; 2944 reg = <0 0x06b00000 0 0x1000>; 2945 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2946 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2947 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2948 <&lpass_vamacro>; 2949 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2950 2951 #clock-cells = <0>; 2952 clock-output-names = "mclk"; 2953 #sound-dai-cells = <1>; 2954 }; 2955 2956 swr0: soundwire@6b10000 { 2957 compatible = "qcom,soundwire-v2.0.0"; 2958 reg = <0 0x06b10000 0 0x10000>; 2959 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 2960 clocks = <&lpass_wsamacro>; 2961 clock-names = "iface"; 2962 label = "WSA"; 2963 2964 pinctrl-0 = <&wsa_swr_active>; 2965 pinctrl-names = "default"; 2966 2967 qcom,din-ports = <4>; 2968 qcom,dout-ports = <9>; 2969 2970 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2971 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2972 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2973 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2974 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2975 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2976 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2977 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2978 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2979 2980 #address-cells = <2>; 2981 #size-cells = <0>; 2982 #sound-dai-cells = <1>; 2983 status = "disabled"; 2984 }; 2985 2986 swr2: soundwire@6d30000 { 2987 compatible = "qcom,soundwire-v2.0.0"; 2988 reg = <0 0x06d30000 0 0x10000>; 2989 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>, 2990 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>; 2991 interrupt-names = "core", "wakeup"; 2992 clocks = <&lpass_txmacro>; 2993 clock-names = "iface"; 2994 label = "TX"; 2995 2996 pinctrl-0 = <&tx_swr_active>; 2997 pinctrl-names = "default"; 2998 2999 qcom,din-ports = <4>; 3000 qcom,dout-ports = <0>; 3001 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3002 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 3003 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3004 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3005 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3006 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3007 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3008 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3009 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 3010 3011 #address-cells = <2>; 3012 #size-cells = <0>; 3013 #sound-dai-cells = <1>; 3014 status = "disabled"; 3015 }; 3016 3017 lpass_vamacro: codec@6d44000 { 3018 compatible = "qcom,sm8550-lpass-va-macro"; 3019 reg = <0 0x06d44000 0 0x1000>; 3020 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3021 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3022 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3023 clock-names = "mclk", "macro", "dcodec"; 3024 3025 #clock-cells = <0>; 3026 clock-output-names = "fsgen"; 3027 #sound-dai-cells = <1>; 3028 }; 3029 3030 lpass_tlmm: pinctrl@6e80000 { 3031 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 3032 reg = <0 0x06e80000 0 0x20000>, 3033 <0 0x07250000 0 0x10000>; 3034 gpio-controller; 3035 #gpio-cells = <2>; 3036 gpio-ranges = <&lpass_tlmm 0 0 23>; 3037 3038 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3039 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3040 clock-names = "core", "audio"; 3041 3042 tx_swr_active: tx-swr-active-state { 3043 clk-pins { 3044 pins = "gpio0"; 3045 function = "swr_tx_clk"; 3046 drive-strength = <2>; 3047 slew-rate = <1>; 3048 bias-disable; 3049 }; 3050 3051 data-pins { 3052 pins = "gpio1", "gpio2", "gpio14"; 3053 function = "swr_tx_data"; 3054 drive-strength = <2>; 3055 slew-rate = <1>; 3056 bias-bus-hold; 3057 }; 3058 }; 3059 3060 rx_swr_active: rx-swr-active-state { 3061 clk-pins { 3062 pins = "gpio3"; 3063 function = "swr_rx_clk"; 3064 drive-strength = <2>; 3065 slew-rate = <1>; 3066 bias-disable; 3067 }; 3068 3069 data-pins { 3070 pins = "gpio4", "gpio5"; 3071 function = "swr_rx_data"; 3072 drive-strength = <2>; 3073 slew-rate = <1>; 3074 bias-bus-hold; 3075 }; 3076 }; 3077 3078 dmic01_default: dmic01-default-state { 3079 clk-pins { 3080 pins = "gpio6"; 3081 function = "dmic1_clk"; 3082 drive-strength = <8>; 3083 output-high; 3084 }; 3085 3086 data-pins { 3087 pins = "gpio7"; 3088 function = "dmic1_data"; 3089 drive-strength = <8>; 3090 input-enable; 3091 }; 3092 }; 3093 3094 dmic23_default: dmic23-default-state { 3095 clk-pins { 3096 pins = "gpio8"; 3097 function = "dmic2_clk"; 3098 drive-strength = <8>; 3099 output-high; 3100 }; 3101 3102 data-pins { 3103 pins = "gpio9"; 3104 function = "dmic2_data"; 3105 drive-strength = <8>; 3106 input-enable; 3107 }; 3108 }; 3109 3110 wsa_swr_active: wsa-swr-active-state { 3111 clk-pins { 3112 pins = "gpio10"; 3113 function = "wsa_swr_clk"; 3114 drive-strength = <2>; 3115 slew-rate = <1>; 3116 bias-disable; 3117 }; 3118 3119 data-pins { 3120 pins = "gpio11"; 3121 function = "wsa_swr_data"; 3122 drive-strength = <2>; 3123 slew-rate = <1>; 3124 bias-bus-hold; 3125 }; 3126 }; 3127 3128 wsa2_swr_active: wsa2-swr-active-state { 3129 clk-pins { 3130 pins = "gpio15"; 3131 function = "wsa2_swr_clk"; 3132 drive-strength = <2>; 3133 slew-rate = <1>; 3134 bias-disable; 3135 }; 3136 3137 data-pins { 3138 pins = "gpio16"; 3139 function = "wsa2_swr_data"; 3140 drive-strength = <2>; 3141 slew-rate = <1>; 3142 bias-bus-hold; 3143 }; 3144 }; 3145 }; 3146 3147 lpass_lpiaon_noc: interconnect@7400000 { 3148 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 3149 reg = <0 0x07400000 0 0x19080>; 3150 #interconnect-cells = <2>; 3151 qcom,bcm-voters = <&apps_bcm_voter>; 3152 }; 3153 3154 lpass_lpicx_noc: interconnect@7430000 { 3155 compatible = "qcom,sm8550-lpass-lpicx-noc"; 3156 reg = <0 0x07430000 0 0x3a200>; 3157 #interconnect-cells = <2>; 3158 qcom,bcm-voters = <&apps_bcm_voter>; 3159 }; 3160 3161 lpass_ag_noc: interconnect@7e40000 { 3162 compatible = "qcom,sm8550-lpass-ag-noc"; 3163 reg = <0 0x07e40000 0 0xe080>; 3164 #interconnect-cells = <2>; 3165 qcom,bcm-voters = <&apps_bcm_voter>; 3166 }; 3167 3168 sdhc_2: mmc@8804000 { 3169 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 3170 reg = <0 0x08804000 0 0x1000>; 3171 3172 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>, 3173 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH 0>; 3174 interrupt-names = "hc_irq", "pwr_irq"; 3175 3176 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3177 <&gcc GCC_SDCC2_APPS_CLK>, 3178 <&rpmhcc RPMH_CXO_CLK>; 3179 clock-names = "iface", "core", "xo"; 3180 iommus = <&apps_smmu 0x540 0>; 3181 qcom,dll-config = <0x0007642c>; 3182 qcom,ddr-config = <0x80040868>; 3183 power-domains = <&rpmhpd RPMHPD_CX>; 3184 operating-points-v2 = <&sdhc2_opp_table>; 3185 3186 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3187 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3188 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3189 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 3190 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 3191 bus-width = <4>; 3192 dma-coherent; 3193 3194 /* Forbid SDR104/SDR50 - broken hw! */ 3195 sdhci-caps-mask = <0x3 0>; 3196 3197 status = "disabled"; 3198 3199 sdhc2_opp_table: opp-table { 3200 compatible = "operating-points-v2"; 3201 3202 opp-19200000 { 3203 opp-hz = /bits/ 64 <19200000>; 3204 required-opps = <&rpmhpd_opp_min_svs>; 3205 }; 3206 3207 opp-50000000 { 3208 opp-hz = /bits/ 64 <50000000>; 3209 required-opps = <&rpmhpd_opp_low_svs>; 3210 }; 3211 3212 opp-100000000 { 3213 opp-hz = /bits/ 64 <100000000>; 3214 required-opps = <&rpmhpd_opp_svs>; 3215 }; 3216 3217 opp-202000000 { 3218 opp-hz = /bits/ 64 <202000000>; 3219 required-opps = <&rpmhpd_opp_svs_l1>; 3220 }; 3221 }; 3222 }; 3223 3224 iris: video-codec@aa00000 { 3225 compatible = "qcom,sm8550-iris"; 3226 3227 reg = <0 0x0aa00000 0 0xf0000>; 3228 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; 3229 3230 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 3231 <&videocc VIDEO_CC_MVS0_GDSC>, 3232 <&rpmhpd RPMHPD_MXC>, 3233 <&rpmhpd RPMHPD_MMCX>; 3234 power-domain-names = "venus", 3235 "vcodec0", 3236 "mxc", 3237 "mmcx"; 3238 operating-points-v2 = <&iris_opp_table>; 3239 3240 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3241 <&videocc VIDEO_CC_MVS0C_CLK>, 3242 <&videocc VIDEO_CC_MVS0_CLK>; 3243 clock-names = "iface", 3244 "core", 3245 "vcodec0_core"; 3246 3247 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3248 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 3249 <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS 3250 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3251 interconnect-names = "cpu-cfg", 3252 "video-mem"; 3253 3254 memory-region = <&video_mem>; 3255 3256 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 3257 reset-names = "bus"; 3258 3259 iommus = <&apps_smmu 0x1940 0>, 3260 <&apps_smmu 0x1947 0>; 3261 dma-coherent; 3262 3263 /* 3264 * IRIS firmware is signed by vendors, only 3265 * enable on boards where the proper signed firmware 3266 * is available. 3267 */ 3268 status = "disabled"; 3269 3270 iris_opp_table: opp-table { 3271 compatible = "operating-points-v2"; 3272 3273 opp-240000000 { 3274 opp-hz = /bits/ 64 <240000000>; 3275 required-opps = <&rpmhpd_opp_svs>, 3276 <&rpmhpd_opp_low_svs>; 3277 }; 3278 3279 opp-338000000 { 3280 opp-hz = /bits/ 64 <338000000>; 3281 required-opps = <&rpmhpd_opp_svs>, 3282 <&rpmhpd_opp_svs>; 3283 }; 3284 3285 opp-366000000 { 3286 opp-hz = /bits/ 64 <366000000>; 3287 required-opps = <&rpmhpd_opp_svs_l1>, 3288 <&rpmhpd_opp_svs_l1>; 3289 }; 3290 3291 opp-444000000 { 3292 opp-hz = /bits/ 64 <444000000>; 3293 required-opps = <&rpmhpd_opp_nom>, 3294 <&rpmhpd_opp_nom>; 3295 }; 3296 3297 opp-533333334 { 3298 opp-hz = /bits/ 64 <533333334>; 3299 required-opps = <&rpmhpd_opp_turbo>, 3300 <&rpmhpd_opp_turbo>; 3301 }; 3302 }; 3303 }; 3304 3305 videocc: clock-controller@aaf0000 { 3306 compatible = "qcom,sm8550-videocc"; 3307 reg = <0 0x0aaf0000 0 0x10000>; 3308 clocks = <&bi_tcxo_div2>, 3309 <&gcc GCC_VIDEO_AHB_CLK>; 3310 power-domains = <&rpmhpd RPMHPD_MMCX>, 3311 <&rpmhpd RPMHPD_MXC>; 3312 required-opps = <&rpmhpd_opp_low_svs>, 3313 <&rpmhpd_opp_low_svs>; 3314 #clock-cells = <1>; 3315 #reset-cells = <1>; 3316 #power-domain-cells = <1>; 3317 }; 3318 3319 cci0: cci@ac15000 { 3320 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 3321 reg = <0 0x0ac15000 0 0x1000>; 3322 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>; 3323 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3324 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3325 <&camcc CAM_CC_CPAS_AHB_CLK>, 3326 <&camcc CAM_CC_CCI_0_CLK>; 3327 clock-names = "camnoc_axi", 3328 "cpas_ahb", 3329 "cci"; 3330 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 3331 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 3332 pinctrl-names = "default", "sleep"; 3333 status = "disabled"; 3334 #address-cells = <1>; 3335 #size-cells = <0>; 3336 3337 cci0_i2c0: i2c-bus@0 { 3338 reg = <0>; 3339 clock-frequency = <1000000>; 3340 #address-cells = <1>; 3341 #size-cells = <0>; 3342 }; 3343 3344 cci0_i2c1: i2c-bus@1 { 3345 reg = <1>; 3346 clock-frequency = <1000000>; 3347 #address-cells = <1>; 3348 #size-cells = <0>; 3349 }; 3350 }; 3351 3352 cci1: cci@ac16000 { 3353 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 3354 reg = <0 0x0ac16000 0 0x1000>; 3355 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING 0>; 3356 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3357 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3358 <&camcc CAM_CC_CPAS_AHB_CLK>, 3359 <&camcc CAM_CC_CCI_1_CLK>; 3360 clock-names = "camnoc_axi", 3361 "cpas_ahb", 3362 "cci"; 3363 pinctrl-0 = <&cci1_0_default>; 3364 pinctrl-1 = <&cci1_0_sleep>; 3365 pinctrl-names = "default", "sleep"; 3366 status = "disabled"; 3367 #address-cells = <1>; 3368 #size-cells = <0>; 3369 3370 cci1_i2c0: i2c-bus@0 { 3371 reg = <0>; 3372 clock-frequency = <1000000>; 3373 #address-cells = <1>; 3374 #size-cells = <0>; 3375 }; 3376 }; 3377 3378 cci2: cci@ac17000 { 3379 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 3380 reg = <0 0x0ac17000 0 0x1000>; 3381 interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING 0>; 3382 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3383 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3384 <&camcc CAM_CC_CPAS_AHB_CLK>, 3385 <&camcc CAM_CC_CCI_2_CLK>; 3386 clock-names = "camnoc_axi", 3387 "cpas_ahb", 3388 "cci"; 3389 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 3390 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 3391 pinctrl-names = "default", "sleep"; 3392 status = "disabled"; 3393 #address-cells = <1>; 3394 #size-cells = <0>; 3395 3396 cci2_i2c0: i2c-bus@0 { 3397 reg = <0>; 3398 clock-frequency = <1000000>; 3399 #address-cells = <1>; 3400 #size-cells = <0>; 3401 }; 3402 3403 cci2_i2c1: i2c-bus@1 { 3404 reg = <1>; 3405 clock-frequency = <1000000>; 3406 #address-cells = <1>; 3407 #size-cells = <0>; 3408 }; 3409 }; 3410 3411 camss: isp@acb7000 { 3412 compatible = "qcom,sm8550-camss"; 3413 3414 reg = <0x0 0x0acb7000 0x0 0x0d00>, 3415 <0x0 0x0acb9000 0x0 0x0d00>, 3416 <0x0 0x0acbb000 0x0 0x0d00>, 3417 <0x0 0x0acca000 0x0 0x0a00>, 3418 <0x0 0x0acce000 0x0 0x0a00>, 3419 <0x0 0x0acb6000 0x0 0x1000>, 3420 <0x0 0x0ace4000 0x0 0x2000>, 3421 <0x0 0x0ace6000 0x0 0x2000>, 3422 <0x0 0x0ace8000 0x0 0x2000>, 3423 <0x0 0x0acea000 0x0 0x2000>, 3424 <0x0 0x0acec000 0x0 0x2000>, 3425 <0x0 0x0acee000 0x0 0x2000>, 3426 <0x0 0x0acf0000 0x0 0x2000>, 3427 <0x0 0x0acf2000 0x0 0x2000>, 3428 <0x0 0x0ac62000 0x0 0xf000>, 3429 <0x0 0x0ac71000 0x0 0xf000>, 3430 <0x0 0x0ac80000 0x0 0xf000>, 3431 <0x0 0x0accb000 0x0 0x1800>, 3432 <0x0 0x0accf000 0x0 0x1800>; 3433 reg-names = "csid0", 3434 "csid1", 3435 "csid2", 3436 "csid_lite0", 3437 "csid_lite1", 3438 "csid_wrapper", 3439 "csiphy0", 3440 "csiphy1", 3441 "csiphy2", 3442 "csiphy3", 3443 "csiphy4", 3444 "csiphy5", 3445 "csiphy6", 3446 "csiphy7", 3447 "vfe0", 3448 "vfe1", 3449 "vfe2", 3450 "vfe_lite0", 3451 "vfe_lite1"; 3452 3453 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3454 <&camcc CAM_CC_CPAS_AHB_CLK>, 3455 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 3456 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 3457 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 3458 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 3459 <&camcc CAM_CC_CPAS_IFE_2_CLK>, 3460 <&camcc CAM_CC_CSID_CLK>, 3461 <&camcc CAM_CC_CSIPHY0_CLK>, 3462 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 3463 <&camcc CAM_CC_CSIPHY1_CLK>, 3464 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 3465 <&camcc CAM_CC_CSIPHY2_CLK>, 3466 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 3467 <&camcc CAM_CC_CSIPHY3_CLK>, 3468 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 3469 <&camcc CAM_CC_CSIPHY4_CLK>, 3470 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 3471 <&camcc CAM_CC_CSIPHY5_CLK>, 3472 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 3473 <&camcc CAM_CC_CSIPHY6_CLK>, 3474 <&camcc CAM_CC_CSI6PHYTIMER_CLK>, 3475 <&camcc CAM_CC_CSIPHY7_CLK>, 3476 <&camcc CAM_CC_CSI7PHYTIMER_CLK>, 3477 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 3478 <&gcc GCC_CAMERA_HF_AXI_CLK>, 3479 <&camcc CAM_CC_IFE_0_CLK>, 3480 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 3481 <&camcc CAM_CC_IFE_1_CLK>, 3482 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 3483 <&camcc CAM_CC_IFE_2_CLK>, 3484 <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, 3485 <&camcc CAM_CC_IFE_LITE_CLK>, 3486 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 3487 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 3488 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 3489 clock-names = "camnoc_axi", 3490 "cpas_ahb", 3491 "cpas_fast_ahb_clk", 3492 "cpas_ife_lite", 3493 "cpas_vfe0", 3494 "cpas_vfe1", 3495 "cpas_vfe2", 3496 "csid", 3497 "csiphy0", 3498 "csiphy0_timer", 3499 "csiphy1", 3500 "csiphy1_timer", 3501 "csiphy2", 3502 "csiphy2_timer", 3503 "csiphy3", 3504 "csiphy3_timer", 3505 "csiphy4", 3506 "csiphy4_timer", 3507 "csiphy5", 3508 "csiphy5_timer", 3509 "csiphy6", 3510 "csiphy6_timer", 3511 "csiphy7", 3512 "csiphy7_timer", 3513 "csiphy_rx", 3514 "gcc_axi_hf", 3515 "vfe0", 3516 "vfe0_fast_ahb", 3517 "vfe1", 3518 "vfe1_fast_ahb", 3519 "vfe2", 3520 "vfe2_fast_ahb", 3521 "vfe_lite", 3522 "vfe_lite_ahb", 3523 "vfe_lite_cphy_rx", 3524 "vfe_lite_csid"; 3525 3526 interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING 0>, 3527 <GIC_SPI 603 IRQ_TYPE_EDGE_RISING 0>, 3528 <GIC_SPI 431 IRQ_TYPE_EDGE_RISING 0>, 3529 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING 0>, 3530 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING 0>, 3531 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>, 3532 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>, 3533 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>, 3534 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING 0>, 3535 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING 0>, 3536 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING 0>, 3537 <GIC_SPI 278 IRQ_TYPE_EDGE_RISING 0>, 3538 <GIC_SPI 277 IRQ_TYPE_EDGE_RISING 0>, 3539 <GIC_SPI 602 IRQ_TYPE_EDGE_RISING 0>, 3540 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING 0>, 3541 <GIC_SPI 688 IRQ_TYPE_EDGE_RISING 0>, 3542 <GIC_SPI 606 IRQ_TYPE_EDGE_RISING 0>, 3543 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING 0>; 3544 interrupt-names = "csid0", 3545 "csid1", 3546 "csid2", 3547 "csid_lite0", 3548 "csid_lite1", 3549 "csiphy0", 3550 "csiphy1", 3551 "csiphy2", 3552 "csiphy3", 3553 "csiphy4", 3554 "csiphy5", 3555 "csiphy6", 3556 "csiphy7", 3557 "vfe0", 3558 "vfe1", 3559 "vfe2", 3560 "vfe_lite0", 3561 "vfe_lite1"; 3562 3563 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3564 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 3565 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 3566 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3567 interconnect-names = "ahb", 3568 "hf_0_mnoc"; 3569 3570 iommus = <&apps_smmu 0x800 0x20>; 3571 3572 power-domains = <&camcc CAM_CC_IFE_0_GDSC>, 3573 <&camcc CAM_CC_IFE_1_GDSC>, 3574 <&camcc CAM_CC_IFE_2_GDSC>, 3575 <&camcc CAM_CC_TITAN_TOP_GDSC>; 3576 power-domain-names = "ife0", 3577 "ife1", 3578 "ife2", 3579 "top"; 3580 3581 status = "disabled"; 3582 3583 ports { 3584 #address-cells = <1>; 3585 #size-cells = <0>; 3586 3587 port@0 { 3588 reg = <0>; 3589 }; 3590 3591 port@1 { 3592 reg = <1>; 3593 }; 3594 3595 port@2 { 3596 reg = <2>; 3597 }; 3598 3599 port@3 { 3600 reg = <3>; 3601 }; 3602 3603 port@4 { 3604 reg = <4>; 3605 }; 3606 3607 port@5 { 3608 reg = <5>; 3609 }; 3610 3611 port@6 { 3612 reg = <6>; 3613 }; 3614 3615 port@7 { 3616 reg = <7>; 3617 }; 3618 }; 3619 }; 3620 3621 camcc: clock-controller@ade0000 { 3622 compatible = "qcom,sm8550-camcc"; 3623 reg = <0 0x0ade0000 0 0x20000>; 3624 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3625 <&bi_tcxo_div2>, 3626 <&bi_tcxo_ao_div2>, 3627 <&sleep_clk>; 3628 power-domains = <&rpmhpd RPMHPD_MMCX>, 3629 <&rpmhpd RPMHPD_MXC>; 3630 required-opps = <&rpmhpd_opp_low_svs>, 3631 <&rpmhpd_opp_low_svs>; 3632 #clock-cells = <1>; 3633 #reset-cells = <1>; 3634 #power-domain-cells = <1>; 3635 }; 3636 3637 mdss: display-subsystem@ae00000 { 3638 compatible = "qcom,sm8550-mdss"; 3639 reg = <0 0x0ae00000 0 0x1000>; 3640 reg-names = "mdss"; 3641 3642 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>; 3643 interrupt-controller; 3644 #interrupt-cells = <1>; 3645 3646 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3647 <&gcc GCC_DISP_AHB_CLK>, 3648 <&gcc GCC_DISP_HF_AXI_CLK>, 3649 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3650 3651 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3652 3653 power-domains = <&dispcc MDSS_GDSC>; 3654 3655 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 3656 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3657 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3658 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3659 interconnect-names = "mdp0-mem", "cpu-cfg"; 3660 3661 iommus = <&apps_smmu 0x1c00 0x2>; 3662 3663 #address-cells = <2>; 3664 #size-cells = <2>; 3665 ranges; 3666 3667 status = "disabled"; 3668 3669 mdss_mdp: display-controller@ae01000 { 3670 compatible = "qcom,sm8550-dpu"; 3671 reg = <0 0x0ae01000 0 0x8f000>, 3672 <0 0x0aeb0000 0 0x3000>; 3673 reg-names = "mdp", "vbif"; 3674 3675 interrupt-parent = <&mdss>; 3676 interrupts = <0>; 3677 3678 clocks = <&gcc GCC_DISP_AHB_CLK>, 3679 <&gcc GCC_DISP_HF_AXI_CLK>, 3680 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3681 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3682 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3683 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3684 clock-names = "bus", 3685 "nrt_bus", 3686 "iface", 3687 "lut", 3688 "core", 3689 "vsync"; 3690 3691 power-domains = <&rpmhpd RPMHPD_MMCX>; 3692 3693 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3694 assigned-clock-rates = <19200000>; 3695 3696 operating-points-v2 = <&mdp_opp_table>; 3697 3698 ports { 3699 #address-cells = <1>; 3700 #size-cells = <0>; 3701 3702 port@0 { 3703 reg = <0>; 3704 dpu_intf1_out: endpoint { 3705 remote-endpoint = <&mdss_dsi0_in>; 3706 }; 3707 }; 3708 3709 port@1 { 3710 reg = <1>; 3711 dpu_intf2_out: endpoint { 3712 remote-endpoint = <&mdss_dsi1_in>; 3713 }; 3714 }; 3715 3716 port@2 { 3717 reg = <2>; 3718 dpu_intf0_out: endpoint { 3719 remote-endpoint = <&mdss_dp0_in>; 3720 }; 3721 }; 3722 }; 3723 3724 mdp_opp_table: opp-table { 3725 compatible = "operating-points-v2"; 3726 3727 opp-200000000 { 3728 opp-hz = /bits/ 64 <200000000>; 3729 required-opps = <&rpmhpd_opp_low_svs>; 3730 }; 3731 3732 opp-325000000 { 3733 opp-hz = /bits/ 64 <325000000>; 3734 required-opps = <&rpmhpd_opp_svs>; 3735 }; 3736 3737 opp-375000000 { 3738 opp-hz = /bits/ 64 <375000000>; 3739 required-opps = <&rpmhpd_opp_svs_l1>; 3740 }; 3741 3742 opp-514000000 { 3743 opp-hz = /bits/ 64 <514000000>; 3744 required-opps = <&rpmhpd_opp_nom>; 3745 }; 3746 }; 3747 }; 3748 3749 mdss_dp0: displayport-controller@ae90000 { 3750 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 3751 reg = <0 0xae90000 0 0x200>, 3752 <0 0xae90200 0 0x200>, 3753 <0 0xae90400 0 0xc00>, 3754 <0 0xae91000 0 0x400>, 3755 <0 0xae91400 0 0x400>; 3756 interrupt-parent = <&mdss>; 3757 interrupts = <12>; 3758 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3759 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3760 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3761 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3762 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 3763 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 3764 clock-names = "core_iface", 3765 "core_aux", 3766 "ctrl_link", 3767 "ctrl_link_iface", 3768 "stream_pixel", 3769 "stream_1_pixel"; 3770 3771 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3772 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 3773 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 3774 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3775 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3776 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3777 3778 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 3779 phy-names = "dp"; 3780 3781 #sound-dai-cells = <0>; 3782 3783 operating-points-v2 = <&dp_opp_table>; 3784 power-domains = <&rpmhpd RPMHPD_MMCX>; 3785 3786 status = "disabled"; 3787 3788 ports { 3789 #address-cells = <1>; 3790 #size-cells = <0>; 3791 3792 port@0 { 3793 reg = <0>; 3794 mdss_dp0_in: endpoint { 3795 remote-endpoint = <&dpu_intf0_out>; 3796 }; 3797 }; 3798 3799 port@1 { 3800 reg = <1>; 3801 mdss_dp0_out: endpoint { 3802 data-lanes = <0 1 2 3>; 3803 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 3804 }; 3805 }; 3806 }; 3807 3808 dp_opp_table: opp-table { 3809 compatible = "operating-points-v2"; 3810 3811 opp-162000000 { 3812 opp-hz = /bits/ 64 <162000000>; 3813 required-opps = <&rpmhpd_opp_low_svs_d1>; 3814 }; 3815 3816 opp-270000000 { 3817 opp-hz = /bits/ 64 <270000000>; 3818 required-opps = <&rpmhpd_opp_low_svs>; 3819 }; 3820 3821 opp-540000000 { 3822 opp-hz = /bits/ 64 <540000000>; 3823 required-opps = <&rpmhpd_opp_svs_l1>; 3824 }; 3825 3826 opp-810000000 { 3827 opp-hz = /bits/ 64 <810000000>; 3828 required-opps = <&rpmhpd_opp_nom>; 3829 }; 3830 }; 3831 }; 3832 3833 mdss_dsi0: dsi@ae94000 { 3834 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3835 reg = <0 0x0ae94000 0 0x400>; 3836 reg-names = "dsi_ctrl"; 3837 3838 interrupt-parent = <&mdss>; 3839 interrupts = <4>; 3840 3841 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3842 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3843 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3844 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3845 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3846 <&gcc GCC_DISP_HF_AXI_CLK>; 3847 clock-names = "byte", 3848 "byte_intf", 3849 "pixel", 3850 "core", 3851 "iface", 3852 "bus"; 3853 3854 power-domains = <&rpmhpd RPMHPD_MMCX>; 3855 3856 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3857 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3858 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3859 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 3860 3861 operating-points-v2 = <&mdss_dsi_opp_table>; 3862 3863 phys = <&mdss_dsi0_phy>; 3864 phy-names = "dsi"; 3865 3866 #address-cells = <1>; 3867 #size-cells = <0>; 3868 3869 status = "disabled"; 3870 3871 ports { 3872 #address-cells = <1>; 3873 #size-cells = <0>; 3874 3875 port@0 { 3876 reg = <0>; 3877 mdss_dsi0_in: endpoint { 3878 remote-endpoint = <&dpu_intf1_out>; 3879 }; 3880 }; 3881 3882 port@1 { 3883 reg = <1>; 3884 mdss_dsi0_out: endpoint { 3885 }; 3886 }; 3887 }; 3888 3889 mdss_dsi_opp_table: opp-table { 3890 compatible = "operating-points-v2"; 3891 3892 opp-187500000 { 3893 opp-hz = /bits/ 64 <187500000>; 3894 required-opps = <&rpmhpd_opp_low_svs>; 3895 }; 3896 3897 opp-300000000 { 3898 opp-hz = /bits/ 64 <300000000>; 3899 required-opps = <&rpmhpd_opp_svs>; 3900 }; 3901 3902 opp-358000000 { 3903 opp-hz = /bits/ 64 <358000000>; 3904 required-opps = <&rpmhpd_opp_svs_l1>; 3905 }; 3906 }; 3907 }; 3908 3909 mdss_dsi0_phy: phy@ae95000 { 3910 compatible = "qcom,sm8550-dsi-phy-4nm"; 3911 reg = <0 0x0ae95000 0 0x200>, 3912 <0 0x0ae95200 0 0x280>, 3913 <0 0x0ae95500 0 0x400>; 3914 reg-names = "dsi_phy", 3915 "dsi_phy_lane", 3916 "dsi_pll"; 3917 3918 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3919 <&rpmhcc RPMH_CXO_CLK>; 3920 clock-names = "iface", "ref"; 3921 3922 #clock-cells = <1>; 3923 #phy-cells = <0>; 3924 3925 status = "disabled"; 3926 }; 3927 3928 mdss_dsi1: dsi@ae96000 { 3929 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3930 reg = <0 0x0ae96000 0 0x400>; 3931 reg-names = "dsi_ctrl"; 3932 3933 interrupt-parent = <&mdss>; 3934 interrupts = <5>; 3935 3936 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3937 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3938 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3939 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3940 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3941 <&gcc GCC_DISP_HF_AXI_CLK>; 3942 clock-names = "byte", 3943 "byte_intf", 3944 "pixel", 3945 "core", 3946 "iface", 3947 "bus"; 3948 3949 power-domains = <&rpmhpd RPMHPD_MMCX>; 3950 3951 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3952 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3953 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3954 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 3955 3956 operating-points-v2 = <&mdss_dsi_opp_table>; 3957 3958 phys = <&mdss_dsi1_phy>; 3959 phy-names = "dsi"; 3960 3961 #address-cells = <1>; 3962 #size-cells = <0>; 3963 3964 status = "disabled"; 3965 3966 ports { 3967 #address-cells = <1>; 3968 #size-cells = <0>; 3969 3970 port@0 { 3971 reg = <0>; 3972 mdss_dsi1_in: endpoint { 3973 remote-endpoint = <&dpu_intf2_out>; 3974 }; 3975 }; 3976 3977 port@1 { 3978 reg = <1>; 3979 mdss_dsi1_out: endpoint { 3980 }; 3981 }; 3982 }; 3983 }; 3984 3985 mdss_dsi1_phy: phy@ae97000 { 3986 compatible = "qcom,sm8550-dsi-phy-4nm"; 3987 reg = <0 0x0ae97000 0 0x200>, 3988 <0 0x0ae97200 0 0x280>, 3989 <0 0x0ae97500 0 0x400>; 3990 reg-names = "dsi_phy", 3991 "dsi_phy_lane", 3992 "dsi_pll"; 3993 3994 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3995 <&rpmhcc RPMH_CXO_CLK>; 3996 clock-names = "iface", "ref"; 3997 3998 #clock-cells = <1>; 3999 #phy-cells = <0>; 4000 4001 status = "disabled"; 4002 }; 4003 }; 4004 4005 dispcc: clock-controller@af00000 { 4006 compatible = "qcom,sm8550-dispcc"; 4007 reg = <0 0x0af00000 0 0x20000>; 4008 clocks = <&bi_tcxo_div2>, 4009 <&bi_tcxo_ao_div2>, 4010 <&gcc GCC_DISP_AHB_CLK>, 4011 <&sleep_clk>, 4012 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4013 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 4014 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4015 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 4016 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4017 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4018 <0>, /* dp1 */ 4019 <0>, 4020 <0>, /* dp2 */ 4021 <0>, 4022 <0>, /* dp3 */ 4023 <0>; 4024 power-domains = <&rpmhpd RPMHPD_MMCX>; 4025 required-opps = <&rpmhpd_opp_low_svs>; 4026 #clock-cells = <1>; 4027 #reset-cells = <1>; 4028 #power-domain-cells = <1>; 4029 }; 4030 4031 usb_1_hsphy: phy@88e3000 { 4032 compatible = "qcom,sm8550-snps-eusb2-phy"; 4033 reg = <0x0 0x088e3000 0x0 0x154>; 4034 #phy-cells = <0>; 4035 4036 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 4037 clock-names = "ref"; 4038 4039 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4040 4041 status = "disabled"; 4042 }; 4043 4044 usb_dp_qmpphy: phy@88e8000 { 4045 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 4046 reg = <0x0 0x088e8000 0x0 0x3000>; 4047 4048 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4049 <&rpmhcc RPMH_CXO_CLK>, 4050 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4051 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4052 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 4053 4054 power-domains = <&gcc USB3_PHY_GDSC>; 4055 4056 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4057 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 4058 reset-names = "phy", "common"; 4059 4060 #clock-cells = <1>; 4061 #phy-cells = <1>; 4062 4063 mode-switch; 4064 orientation-switch; 4065 4066 status = "disabled"; 4067 4068 ports { 4069 #address-cells = <1>; 4070 #size-cells = <0>; 4071 4072 port@0 { 4073 reg = <0>; 4074 4075 usb_dp_qmpphy_out: endpoint { 4076 }; 4077 }; 4078 4079 port@1 { 4080 reg = <1>; 4081 4082 usb_dp_qmpphy_usb_ss_in: endpoint { 4083 remote-endpoint = <&usb_1_dwc3_ss>; 4084 }; 4085 }; 4086 4087 port@2 { 4088 reg = <2>; 4089 4090 usb_dp_qmpphy_dp_in: endpoint { 4091 remote-endpoint = <&mdss_dp0_out>; 4092 }; 4093 }; 4094 }; 4095 }; 4096 4097 usb_1: usb@a600000 { 4098 compatible = "qcom,sm8550-dwc3", "qcom,snps-dwc3"; 4099 reg = <0x0 0x0a600000 0x0 0xfc100>; 4100 #address-cells = <1>; 4101 #size-cells = <0>; 4102 4103 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4104 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4105 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4106 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4107 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4108 <&tcsr TCSR_USB3_CLKREF_EN>; 4109 clock-names = "cfg_noc", 4110 "core", 4111 "iface", 4112 "sleep", 4113 "mock_utmi", 4114 "xo"; 4115 4116 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4117 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4118 assigned-clock-rates = <19200000>, <200000000>; 4119 4120 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, 4121 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, 4122 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, 4123 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4124 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4125 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4126 interrupt-names = "dwc_usb3", 4127 "pwr_event", 4128 "hs_phy_irq", 4129 "dp_hs_phy_irq", 4130 "dm_hs_phy_irq", 4131 "ss_phy_irq"; 4132 4133 power-domains = <&gcc USB30_PRIM_GDSC>; 4134 required-opps = <&rpmhpd_opp_nom>; 4135 4136 resets = <&gcc GCC_USB30_PRIM_BCR>; 4137 4138 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 4139 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4140 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4141 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 4142 interconnect-names = "usb-ddr", "apps-usb"; 4143 4144 iommus = <&apps_smmu 0x40 0x0>; 4145 4146 phys = <&usb_1_hsphy>, 4147 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 4148 phy-names = "usb2-phy", "usb3-phy"; 4149 4150 snps,hird-threshold = /bits/ 8 <0x0>; 4151 snps,usb2-gadget-lpm-disable; 4152 snps,dis_u2_susphy_quirk; 4153 snps,dis_enblslpm_quirk; 4154 snps,dis-u1-entry-quirk; 4155 snps,dis-u2-entry-quirk; 4156 snps,is-utmi-l1-suspend; 4157 snps,usb3_lpm_capable; 4158 snps,usb2-lpm-disable; 4159 snps,has-lpm-erratum; 4160 tx-fifo-resize; 4161 4162 dma-coherent; 4163 4164 usb-role-switch; 4165 4166 status = "disabled"; 4167 4168 ports { 4169 #address-cells = <1>; 4170 #size-cells = <0>; 4171 4172 port@0 { 4173 reg = <0>; 4174 4175 usb_1_dwc3_hs: endpoint { 4176 }; 4177 }; 4178 4179 port@1 { 4180 reg = <1>; 4181 4182 usb_1_dwc3_ss: endpoint { 4183 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 4184 }; 4185 }; 4186 }; 4187 }; 4188 4189 pdc: interrupt-controller@b220000 { 4190 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 4191 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 4192 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4193 <125 63 1>, <126 716 12>, 4194 <138 251 5>; 4195 #interrupt-cells = <2>; 4196 interrupt-parent = <&intc>; 4197 interrupt-controller; 4198 }; 4199 4200 tsens0: thermal-sensor@c271000 { 4201 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 4202 reg = <0 0x0c271000 0 0x1000>, /* TM */ 4203 <0 0x0c222000 0 0x1000>; /* SROT */ 4204 #qcom,sensors = <16>; 4205 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>, 4206 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 4207 interrupt-names = "uplow", "critical"; 4208 #thermal-sensor-cells = <1>; 4209 }; 4210 4211 tsens1: thermal-sensor@c272000 { 4212 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 4213 reg = <0 0x0c272000 0 0x1000>, /* TM */ 4214 <0 0x0c223000 0 0x1000>; /* SROT */ 4215 #qcom,sensors = <16>; 4216 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>, 4217 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 4218 interrupt-names = "uplow", "critical"; 4219 #thermal-sensor-cells = <1>; 4220 }; 4221 4222 tsens2: thermal-sensor@c273000 { 4223 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 4224 reg = <0 0x0c273000 0 0x1000>, /* TM */ 4225 <0 0x0c224000 0 0x1000>; /* SROT */ 4226 #qcom,sensors = <16>; 4227 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>, 4228 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 4229 interrupt-names = "uplow", "critical"; 4230 #thermal-sensor-cells = <1>; 4231 }; 4232 4233 aoss_qmp: power-management@c300000 { 4234 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 4235 reg = <0 0x0c300000 0 0x400>; 4236 interrupt-parent = <&ipcc>; 4237 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4238 IRQ_TYPE_EDGE_RISING>; 4239 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4240 4241 #clock-cells = <0>; 4242 }; 4243 4244 sram@c3f0000 { 4245 compatible = "qcom,rpmh-stats"; 4246 reg = <0 0x0c3f0000 0 0x400>; 4247 qcom,qmp = <&aoss_qmp>; 4248 }; 4249 4250 spmi_bus: spmi@c400000 { 4251 compatible = "qcom,spmi-pmic-arb"; 4252 reg = <0 0x0c400000 0 0x3000>, 4253 <0 0x0c500000 0 0x400000>, 4254 <0 0x0c440000 0 0x80000>, 4255 <0 0x0c4c0000 0 0x20000>, 4256 <0 0x0c42d000 0 0x4000>; 4257 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4258 interrupt-names = "periph_irq"; 4259 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4260 qcom,ee = <0>; 4261 qcom,channel = <0>; 4262 qcom,bus-id = <0>; 4263 #address-cells = <2>; 4264 #size-cells = <0>; 4265 interrupt-controller; 4266 #interrupt-cells = <4>; 4267 }; 4268 4269 tlmm: pinctrl@f100000 { 4270 compatible = "qcom,sm8550-tlmm"; 4271 reg = <0 0x0f100000 0 0x300000>; 4272 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; 4273 gpio-controller; 4274 #gpio-cells = <2>; 4275 interrupt-controller; 4276 #interrupt-cells = <2>; 4277 gpio-ranges = <&tlmm 0 0 211>; 4278 wakeup-parent = <&pdc>; 4279 4280 cci0_0_default: cci0-0-default-state { 4281 sda-pins { 4282 pins = "gpio110"; 4283 function = "cci_i2c_sda"; 4284 drive-strength = <2>; 4285 bias-pull-up = <2200>; 4286 }; 4287 4288 scl-pins { 4289 pins = "gpio111"; 4290 function = "cci_i2c_scl"; 4291 drive-strength = <2>; 4292 bias-pull-up = <2200>; 4293 }; 4294 }; 4295 4296 cci0_0_sleep: cci0-0-sleep-state { 4297 sda-pins { 4298 pins = "gpio110"; 4299 function = "cci_i2c_sda"; 4300 drive-strength = <2>; 4301 bias-pull-down; 4302 }; 4303 4304 scl-pins { 4305 pins = "gpio111"; 4306 function = "cci_i2c_scl"; 4307 drive-strength = <2>; 4308 bias-pull-down; 4309 }; 4310 }; 4311 4312 cci0_1_default: cci0-1-default-state { 4313 sda-pins { 4314 pins = "gpio112"; 4315 function = "cci_i2c_sda"; 4316 drive-strength = <2>; 4317 bias-pull-up = <2200>; 4318 }; 4319 4320 scl-pins { 4321 pins = "gpio113"; 4322 function = "cci_i2c_scl"; 4323 drive-strength = <2>; 4324 bias-pull-up = <2200>; 4325 }; 4326 }; 4327 4328 cci0_1_sleep: cci0-1-sleep-state { 4329 sda-pins { 4330 pins = "gpio112"; 4331 function = "cci_i2c_sda"; 4332 drive-strength = <2>; 4333 bias-pull-down; 4334 }; 4335 4336 scl-pins { 4337 pins = "gpio113"; 4338 function = "cci_i2c_scl"; 4339 drive-strength = <2>; 4340 bias-pull-down; 4341 }; 4342 }; 4343 4344 cci1_0_default: cci1-0-default-state { 4345 sda-pins { 4346 pins = "gpio114"; 4347 function = "cci_i2c_sda"; 4348 drive-strength = <2>; 4349 bias-pull-up = <2200>; 4350 }; 4351 4352 scl-pins { 4353 pins = "gpio115"; 4354 function = "cci_i2c_scl"; 4355 drive-strength = <2>; 4356 bias-pull-up = <2200>; 4357 }; 4358 }; 4359 4360 cci1_0_sleep: cci1-0-sleep-state { 4361 sda-pins { 4362 pins = "gpio114"; 4363 function = "cci_i2c_sda"; 4364 drive-strength = <2>; 4365 bias-pull-down; 4366 }; 4367 4368 scl-pins { 4369 pins = "gpio115"; 4370 function = "cci_i2c_scl"; 4371 drive-strength = <2>; 4372 bias-pull-down; 4373 }; 4374 }; 4375 4376 cci2_0_default: cci2-0-default-state { 4377 sda-pins { 4378 pins = "gpio74"; 4379 function = "cci_i2c_sda"; 4380 drive-strength = <2>; 4381 bias-pull-up = <2200>; 4382 }; 4383 4384 scl-pins { 4385 pins = "gpio75"; 4386 function = "cci_i2c_scl"; 4387 drive-strength = <2>; 4388 bias-pull-up = <2200>; 4389 }; 4390 }; 4391 4392 cci2_0_sleep: cci2-0-sleep-state { 4393 sda-pins { 4394 pins = "gpio74"; 4395 function = "cci_i2c_sda"; 4396 drive-strength = <2>; 4397 bias-pull-down; 4398 }; 4399 4400 scl-pins { 4401 pins = "gpio75"; 4402 function = "cci_i2c_scl"; 4403 drive-strength = <2>; 4404 bias-pull-down; 4405 }; 4406 }; 4407 4408 cci2_1_default: cci2-1-default-state { 4409 sda-pins { 4410 pins = "gpio0"; 4411 function = "cci_i2c_sda"; 4412 drive-strength = <2>; 4413 bias-pull-up = <2200>; 4414 }; 4415 4416 scl-pins { 4417 pins = "gpio1"; 4418 function = "cci_i2c_scl"; 4419 drive-strength = <2>; 4420 bias-pull-up = <2200>; 4421 }; 4422 }; 4423 4424 cci2_1_sleep: cci2-1-sleep-state { 4425 sda-pins { 4426 pins = "gpio0"; 4427 function = "cci_i2c_sda"; 4428 drive-strength = <2>; 4429 bias-pull-down; 4430 }; 4431 4432 scl-pins { 4433 pins = "gpio1"; 4434 function = "cci_i2c_scl"; 4435 drive-strength = <2>; 4436 bias-pull-down; 4437 }; 4438 }; 4439 4440 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 4441 /* SDA, SCL */ 4442 pins = "gpio16", "gpio17"; 4443 function = "i2chub0_se0"; 4444 drive-strength = <2>; 4445 bias-pull-up; 4446 }; 4447 4448 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 4449 /* SDA, SCL */ 4450 pins = "gpio18", "gpio19"; 4451 function = "i2chub0_se1"; 4452 drive-strength = <2>; 4453 bias-pull-up; 4454 }; 4455 4456 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 4457 /* SDA, SCL */ 4458 pins = "gpio20", "gpio21"; 4459 function = "i2chub0_se2"; 4460 drive-strength = <2>; 4461 bias-pull-up; 4462 }; 4463 4464 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 4465 /* SDA, SCL */ 4466 pins = "gpio22", "gpio23"; 4467 function = "i2chub0_se3"; 4468 drive-strength = <2>; 4469 bias-pull-up; 4470 }; 4471 4472 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 4473 /* SDA, SCL */ 4474 pins = "gpio4", "gpio5"; 4475 function = "i2chub0_se4"; 4476 drive-strength = <2>; 4477 bias-pull-up; 4478 }; 4479 4480 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 4481 /* SDA, SCL */ 4482 pins = "gpio6", "gpio7"; 4483 function = "i2chub0_se5"; 4484 drive-strength = <2>; 4485 bias-pull-up; 4486 }; 4487 4488 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 4489 /* SDA, SCL */ 4490 pins = "gpio8", "gpio9"; 4491 function = "i2chub0_se6"; 4492 drive-strength = <2>; 4493 bias-pull-up; 4494 }; 4495 4496 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 4497 /* SDA, SCL */ 4498 pins = "gpio10", "gpio11"; 4499 function = "i2chub0_se7"; 4500 drive-strength = <2>; 4501 bias-pull-up; 4502 }; 4503 4504 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 4505 /* SDA, SCL */ 4506 pins = "gpio206", "gpio207"; 4507 function = "i2chub0_se8"; 4508 drive-strength = <2>; 4509 bias-pull-up; 4510 }; 4511 4512 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 4513 /* SDA, SCL */ 4514 pins = "gpio84", "gpio85"; 4515 function = "i2chub0_se9"; 4516 drive-strength = <2>; 4517 bias-pull-up; 4518 }; 4519 4520 pcie0_default_state: pcie0-default-state { 4521 perst-pins { 4522 pins = "gpio94"; 4523 function = "gpio"; 4524 drive-strength = <2>; 4525 bias-pull-down; 4526 }; 4527 4528 clkreq-pins { 4529 pins = "gpio95"; 4530 function = "pcie0_clk_req_n"; 4531 drive-strength = <2>; 4532 bias-pull-up; 4533 }; 4534 4535 wake-pins { 4536 pins = "gpio96"; 4537 function = "gpio"; 4538 drive-strength = <2>; 4539 bias-pull-up; 4540 }; 4541 }; 4542 4543 pcie1_default_state: pcie1-default-state { 4544 perst-pins { 4545 pins = "gpio97"; 4546 function = "gpio"; 4547 drive-strength = <2>; 4548 bias-pull-down; 4549 }; 4550 4551 clkreq-pins { 4552 pins = "gpio98"; 4553 function = "pcie1_clk_req_n"; 4554 drive-strength = <2>; 4555 bias-pull-up; 4556 }; 4557 4558 wake-pins { 4559 pins = "gpio99"; 4560 function = "gpio"; 4561 drive-strength = <2>; 4562 bias-pull-up; 4563 }; 4564 }; 4565 4566 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4567 /* SDA, SCL */ 4568 pins = "gpio28", "gpio29"; 4569 function = "qup1_se0"; 4570 drive-strength = <2>; 4571 bias-pull-up = <2200>; 4572 }; 4573 4574 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4575 /* SDA, SCL */ 4576 pins = "gpio32", "gpio33"; 4577 function = "qup1_se1"; 4578 drive-strength = <2>; 4579 bias-pull-up = <2200>; 4580 }; 4581 4582 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4583 /* SDA, SCL */ 4584 pins = "gpio36", "gpio37"; 4585 function = "qup1_se2"; 4586 drive-strength = <2>; 4587 bias-pull-up = <2200>; 4588 }; 4589 4590 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4591 /* SDA, SCL */ 4592 pins = "gpio40", "gpio41"; 4593 function = "qup1_se3"; 4594 drive-strength = <2>; 4595 bias-pull-up = <2200>; 4596 }; 4597 4598 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4599 /* SDA, SCL */ 4600 pins = "gpio44", "gpio45"; 4601 function = "qup1_se4"; 4602 drive-strength = <2>; 4603 bias-pull-up = <2200>; 4604 }; 4605 4606 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4607 /* SDA, SCL */ 4608 pins = "gpio52", "gpio53"; 4609 function = "qup1_se5"; 4610 drive-strength = <2>; 4611 bias-pull-up = <2200>; 4612 }; 4613 4614 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4615 /* SDA, SCL */ 4616 pins = "gpio48", "gpio49"; 4617 function = "qup1_se6"; 4618 drive-strength = <2>; 4619 bias-pull-up = <2200>; 4620 }; 4621 4622 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4623 scl-pins { 4624 pins = "gpio57"; 4625 function = "qup2_se0_l1_mira"; 4626 drive-strength = <2>; 4627 bias-pull-up = <2200>; 4628 }; 4629 4630 sda-pins { 4631 pins = "gpio56"; 4632 function = "qup2_se0_l0_mira"; 4633 drive-strength = <2>; 4634 bias-pull-up = <2200>; 4635 }; 4636 }; 4637 4638 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4639 /* SDA, SCL */ 4640 pins = "gpio60", "gpio61"; 4641 function = "qup2_se1"; 4642 drive-strength = <2>; 4643 bias-pull-up = <2200>; 4644 }; 4645 4646 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4647 /* SDA, SCL */ 4648 pins = "gpio64", "gpio65"; 4649 function = "qup2_se2"; 4650 drive-strength = <2>; 4651 bias-pull-up = <2200>; 4652 }; 4653 4654 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4655 /* SDA, SCL */ 4656 pins = "gpio68", "gpio69"; 4657 function = "qup2_se3"; 4658 drive-strength = <2>; 4659 bias-pull-up = <2200>; 4660 }; 4661 4662 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4663 /* SDA, SCL */ 4664 pins = "gpio2", "gpio3"; 4665 function = "qup2_se4"; 4666 drive-strength = <2>; 4667 bias-pull-up = <2200>; 4668 }; 4669 4670 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4671 /* SDA, SCL */ 4672 pins = "gpio80", "gpio81"; 4673 function = "qup2_se5"; 4674 drive-strength = <2>; 4675 bias-pull-up = <2200>; 4676 }; 4677 4678 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4679 /* SDA, SCL */ 4680 pins = "gpio72", "gpio106"; 4681 function = "qup2_se7"; 4682 drive-strength = <2>; 4683 bias-pull-up = <2200>; 4684 }; 4685 4686 qup_spi0_cs: qup-spi0-cs-state { 4687 pins = "gpio31"; 4688 function = "qup1_se0"; 4689 drive-strength = <6>; 4690 bias-disable; 4691 }; 4692 4693 qup_spi0_data_clk: qup-spi0-data-clk-state { 4694 /* MISO, MOSI, CLK */ 4695 pins = "gpio28", "gpio29", "gpio30"; 4696 function = "qup1_se0"; 4697 drive-strength = <6>; 4698 bias-disable; 4699 }; 4700 4701 qup_spi1_cs: qup-spi1-cs-state { 4702 pins = "gpio35"; 4703 function = "qup1_se1"; 4704 drive-strength = <6>; 4705 bias-disable; 4706 }; 4707 4708 qup_spi1_data_clk: qup-spi1-data-clk-state { 4709 /* MISO, MOSI, CLK */ 4710 pins = "gpio32", "gpio33", "gpio34"; 4711 function = "qup1_se1"; 4712 drive-strength = <6>; 4713 bias-disable; 4714 }; 4715 4716 qup_spi2_cs: qup-spi2-cs-state { 4717 pins = "gpio39"; 4718 function = "qup1_se2"; 4719 drive-strength = <6>; 4720 bias-disable; 4721 }; 4722 4723 qup_spi2_data_clk: qup-spi2-data-clk-state { 4724 /* MISO, MOSI, CLK */ 4725 pins = "gpio36", "gpio37", "gpio38"; 4726 function = "qup1_se2"; 4727 drive-strength = <6>; 4728 bias-disable; 4729 }; 4730 4731 qup_spi3_cs: qup-spi3-cs-state { 4732 pins = "gpio43"; 4733 function = "qup1_se3"; 4734 drive-strength = <6>; 4735 bias-disable; 4736 }; 4737 4738 qup_spi3_data_clk: qup-spi3-data-clk-state { 4739 /* MISO, MOSI, CLK */ 4740 pins = "gpio40", "gpio41", "gpio42"; 4741 function = "qup1_se3"; 4742 drive-strength = <6>; 4743 bias-disable; 4744 }; 4745 4746 qup_spi4_cs: qup-spi4-cs-state { 4747 pins = "gpio47"; 4748 function = "qup1_se4"; 4749 drive-strength = <6>; 4750 bias-disable; 4751 }; 4752 4753 qup_spi4_data_clk: qup-spi4-data-clk-state { 4754 /* MISO, MOSI, CLK */ 4755 pins = "gpio44", "gpio45", "gpio46"; 4756 function = "qup1_se4"; 4757 drive-strength = <6>; 4758 bias-disable; 4759 }; 4760 4761 qup_spi5_cs: qup-spi5-cs-state { 4762 pins = "gpio55"; 4763 function = "qup1_se5"; 4764 drive-strength = <6>; 4765 bias-disable; 4766 }; 4767 4768 qup_spi5_data_clk: qup-spi5-data-clk-state { 4769 /* MISO, MOSI, CLK */ 4770 pins = "gpio52", "gpio53", "gpio54"; 4771 function = "qup1_se5"; 4772 drive-strength = <6>; 4773 bias-disable; 4774 }; 4775 4776 qup_spi6_cs: qup-spi6-cs-state { 4777 pins = "gpio51"; 4778 function = "qup1_se6"; 4779 drive-strength = <6>; 4780 bias-disable; 4781 }; 4782 4783 qup_spi6_data_clk: qup-spi6-data-clk-state { 4784 /* MISO, MOSI, CLK */ 4785 pins = "gpio48", "gpio49", "gpio50"; 4786 function = "qup1_se6"; 4787 drive-strength = <6>; 4788 bias-disable; 4789 }; 4790 4791 qup_spi8_cs: qup-spi8-cs-state { 4792 pins = "gpio59"; 4793 function = "qup2_se0_l3_mira"; 4794 drive-strength = <6>; 4795 bias-disable; 4796 }; 4797 4798 qup_spi8_data_clk: qup-spi8-data-clk-state { 4799 /* MISO, MOSI, CLK */ 4800 pins = "gpio56", "gpio57", "gpio58"; 4801 function = "qup2_se0_l2_mira"; 4802 drive-strength = <6>; 4803 bias-disable; 4804 }; 4805 4806 qup_spi9_cs: qup-spi9-cs-state { 4807 pins = "gpio63"; 4808 function = "qup2_se1"; 4809 drive-strength = <6>; 4810 bias-disable; 4811 }; 4812 4813 qup_spi9_data_clk: qup-spi9-data-clk-state { 4814 /* MISO, MOSI, CLK */ 4815 pins = "gpio60", "gpio61", "gpio62"; 4816 function = "qup2_se1"; 4817 drive-strength = <6>; 4818 bias-disable; 4819 }; 4820 4821 qup_spi10_cs: qup-spi10-cs-state { 4822 pins = "gpio67"; 4823 function = "qup2_se2"; 4824 drive-strength = <6>; 4825 bias-disable; 4826 }; 4827 4828 qup_spi10_data_clk: qup-spi10-data-clk-state { 4829 /* MISO, MOSI, CLK */ 4830 pins = "gpio64", "gpio65", "gpio66"; 4831 function = "qup2_se2"; 4832 drive-strength = <6>; 4833 bias-disable; 4834 }; 4835 4836 qup_spi11_cs: qup-spi11-cs-state { 4837 pins = "gpio71"; 4838 function = "qup2_se3"; 4839 drive-strength = <6>; 4840 bias-disable; 4841 }; 4842 4843 qup_spi11_data_clk: qup-spi11-data-clk-state { 4844 /* MISO, MOSI, CLK */ 4845 pins = "gpio68", "gpio69", "gpio70"; 4846 function = "qup2_se3"; 4847 drive-strength = <6>; 4848 bias-disable; 4849 }; 4850 4851 qup_spi12_cs: qup-spi12-cs-state { 4852 pins = "gpio119"; 4853 function = "qup2_se4"; 4854 drive-strength = <6>; 4855 bias-disable; 4856 }; 4857 4858 qup_spi12_data_clk: qup-spi12-data-clk-state { 4859 /* MISO, MOSI, CLK */ 4860 pins = "gpio2", "gpio3", "gpio118"; 4861 function = "qup2_se4"; 4862 drive-strength = <6>; 4863 bias-disable; 4864 }; 4865 4866 qup_spi13_cs: qup-spi13-cs-state { 4867 pins = "gpio83"; 4868 function = "qup2_se5"; 4869 drive-strength = <6>; 4870 bias-disable; 4871 }; 4872 4873 qup_spi13_data_clk: qup-spi13-data-clk-state { 4874 /* MISO, MOSI, CLK */ 4875 pins = "gpio80", "gpio81", "gpio82"; 4876 function = "qup2_se5"; 4877 drive-strength = <6>; 4878 bias-disable; 4879 }; 4880 4881 qup_spi15_cs: qup-spi15-cs-state { 4882 pins = "gpio75"; 4883 function = "qup2_se7"; 4884 drive-strength = <6>; 4885 bias-disable; 4886 }; 4887 4888 qup_spi15_data_clk: qup-spi15-data-clk-state { 4889 /* MISO, MOSI, CLK */ 4890 pins = "gpio72", "gpio106", "gpio74"; 4891 function = "qup2_se7"; 4892 drive-strength = <6>; 4893 bias-disable; 4894 }; 4895 4896 qup_uart7_default: qup-uart7-default-state { 4897 /* TX, RX */ 4898 pins = "gpio26", "gpio27"; 4899 function = "qup1_se7"; 4900 drive-strength = <2>; 4901 bias-disable; 4902 }; 4903 4904 qup_uart14_default: qup-uart14-default-state { 4905 /* TX, RX */ 4906 pins = "gpio78", "gpio79"; 4907 function = "qup2_se6"; 4908 drive-strength = <2>; 4909 bias-pull-up; 4910 }; 4911 4912 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 4913 /* CTS, RTS */ 4914 pins = "gpio76", "gpio77"; 4915 function = "qup2_se6"; 4916 drive-strength = <2>; 4917 bias-pull-down; 4918 }; 4919 4920 sdc2_sleep: sdc2-sleep-state { 4921 clk-pins { 4922 pins = "sdc2_clk"; 4923 bias-disable; 4924 drive-strength = <2>; 4925 }; 4926 4927 cmd-pins { 4928 pins = "sdc2_cmd"; 4929 bias-pull-up; 4930 drive-strength = <2>; 4931 }; 4932 4933 data-pins { 4934 pins = "sdc2_data"; 4935 bias-pull-up; 4936 drive-strength = <2>; 4937 }; 4938 }; 4939 4940 sdc2_default: sdc2-default-state { 4941 clk-pins { 4942 pins = "sdc2_clk"; 4943 bias-disable; 4944 drive-strength = <16>; 4945 }; 4946 4947 cmd-pins { 4948 pins = "sdc2_cmd"; 4949 bias-pull-up; 4950 drive-strength = <10>; 4951 }; 4952 4953 data-pins { 4954 pins = "sdc2_data"; 4955 bias-pull-up; 4956 drive-strength = <10>; 4957 }; 4958 }; 4959 }; 4960 4961 apps_smmu: iommu@15000000 { 4962 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4963 reg = <0 0x15000000 0 0x100000>; 4964 #iommu-cells = <2>; 4965 #global-interrupts = <1>; 4966 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, 4967 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, 4968 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, 4969 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, 4970 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, 4971 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 4972 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, 4973 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 4974 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 4975 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, 4976 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, 4977 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 4978 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 4979 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 4980 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, 4981 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, 4982 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, 4983 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, 4984 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 4985 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, 4986 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, 4987 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, 4988 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, 4989 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, 4990 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, 4991 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, 4992 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, 4993 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, 4994 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, 4995 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, 4996 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, 4997 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, 4998 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, 4999 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, 5000 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, 5001 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, 5002 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, 5003 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, 5004 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, 5005 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, 5006 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, 5007 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, 5008 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, 5009 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, 5010 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, 5011 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, 5012 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, 5013 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, 5014 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, 5015 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, 5016 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, 5017 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, 5018 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, 5019 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, 5020 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, 5021 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, 5022 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, 5023 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, 5024 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, 5025 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, 5026 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, 5027 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>, 5028 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>, 5029 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>, 5030 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>, 5031 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>, 5032 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>, 5033 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 5034 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 5035 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>, 5036 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>, 5037 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>, 5038 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>, 5039 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>, 5040 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>, 5041 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>, 5042 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>, 5043 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>, 5044 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, 5045 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, 5046 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, 5047 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, 5048 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, 5049 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>, 5050 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>, 5051 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>, 5052 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>, 5053 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>, 5054 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>, 5055 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>, 5056 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>, 5057 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>, 5058 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>, 5059 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>, 5060 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>, 5061 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>, 5062 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>; 5063 dma-coherent; 5064 }; 5065 5066 intc: interrupt-controller@17100000 { 5067 compatible = "arm,gic-v3"; 5068 reg = <0 0x17100000 0 0x10000>, /* GICD */ 5069 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 5070 ranges; 5071 #interrupt-cells = <4>; 5072 interrupt-controller; 5073 #redistributor-regions = <1>; 5074 redistributor-stride = <0 0x40000>; 5075 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>; 5076 #address-cells = <2>; 5077 #size-cells = <2>; 5078 5079 ppi-partitions { 5080 ppi_cluster0: interrupt-partition-0 { 5081 affinity = <&cpu0 &cpu1 &cpu2>; 5082 }; 5083 5084 ppi_cluster1: interrupt-partition-1 { 5085 affinity = <&cpu3 &cpu4>; 5086 }; 5087 5088 ppi_cluster2: interrupt-partition-2 { 5089 affinity = <&cpu5 &cpu6>; 5090 }; 5091 5092 ppi_cluster3: interrupt-partition-3 { 5093 affinity = <&cpu7>; 5094 }; 5095 }; 5096 5097 gic_its: msi-controller@17140000 { 5098 compatible = "arm,gic-v3-its"; 5099 reg = <0 0x17140000 0 0x20000>; 5100 msi-controller; 5101 #msi-cells = <1>; 5102 }; 5103 }; 5104 5105 timer@17420000 { 5106 compatible = "arm,armv7-timer-mem"; 5107 reg = <0 0x17420000 0 0x1000>; 5108 ranges = <0 0 0 0x20000000>; 5109 #address-cells = <1>; 5110 #size-cells = <1>; 5111 5112 frame@17421000 { 5113 reg = <0x17421000 0x1000>, 5114 <0x17422000 0x1000>; 5115 frame-number = <0>; 5116 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, 5117 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 5118 }; 5119 5120 frame@17423000 { 5121 reg = <0x17423000 0x1000>; 5122 frame-number = <1>; 5123 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 5124 status = "disabled"; 5125 }; 5126 5127 frame@17425000 { 5128 reg = <0x17425000 0x1000>; 5129 frame-number = <2>; 5130 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 5131 status = "disabled"; 5132 }; 5133 5134 frame@17427000 { 5135 reg = <0x17427000 0x1000>; 5136 frame-number = <3>; 5137 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 5138 status = "disabled"; 5139 }; 5140 5141 frame@17429000 { 5142 reg = <0x17429000 0x1000>; 5143 frame-number = <4>; 5144 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 5145 status = "disabled"; 5146 }; 5147 5148 frame@1742b000 { 5149 reg = <0x1742b000 0x1000>; 5150 frame-number = <5>; 5151 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; 5152 status = "disabled"; 5153 }; 5154 5155 frame@1742d000 { 5156 reg = <0x1742d000 0x1000>; 5157 frame-number = <6>; 5158 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 5159 status = "disabled"; 5160 }; 5161 }; 5162 5163 apps_rsc: rsc@17a00000 { 5164 label = "apps_rsc"; 5165 compatible = "qcom,rpmh-rsc"; 5166 reg = <0 0x17a00000 0 0x10000>, 5167 <0 0x17a10000 0 0x10000>, 5168 <0 0x17a20000 0 0x10000>, 5169 <0 0x17a30000 0 0x10000>; 5170 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 5171 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, 5172 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, 5173 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; 5174 qcom,tcs-offset = <0xd00>; 5175 qcom,drv-id = <2>; 5176 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 5177 <WAKE_TCS 2>, <CONTROL_TCS 0>; 5178 power-domains = <&cluster_pd>; 5179 5180 apps_bcm_voter: bcm-voter { 5181 compatible = "qcom,bcm-voter"; 5182 }; 5183 5184 rpmhcc: clock-controller { 5185 compatible = "qcom,sm8550-rpmh-clk"; 5186 #clock-cells = <1>; 5187 clock-names = "xo"; 5188 clocks = <&xo_board>; 5189 }; 5190 5191 rpmhpd: power-controller { 5192 compatible = "qcom,sm8550-rpmhpd"; 5193 #power-domain-cells = <1>; 5194 operating-points-v2 = <&rpmhpd_opp_table>; 5195 5196 rpmhpd_opp_table: opp-table { 5197 compatible = "operating-points-v2"; 5198 5199 rpmhpd_opp_ret: opp-16 { 5200 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5201 }; 5202 5203 rpmhpd_opp_min_svs: opp-48 { 5204 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5205 }; 5206 5207 rpmhpd_opp_low_svs_d2: opp-52 { 5208 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5209 }; 5210 5211 rpmhpd_opp_low_svs_d1: opp-56 { 5212 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5213 }; 5214 5215 rpmhpd_opp_low_svs_d0: opp-60 { 5216 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5217 }; 5218 5219 rpmhpd_opp_low_svs: opp-64 { 5220 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5221 }; 5222 5223 rpmhpd_opp_low_svs_l1: opp-80 { 5224 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5225 }; 5226 5227 rpmhpd_opp_svs: opp-128 { 5228 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5229 }; 5230 5231 rpmhpd_opp_svs_l0: opp-144 { 5232 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5233 }; 5234 5235 rpmhpd_opp_svs_l1: opp-192 { 5236 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5237 }; 5238 5239 rpmhpd_opp_nom: opp-256 { 5240 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5241 }; 5242 5243 rpmhpd_opp_nom_l1: opp-320 { 5244 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5245 }; 5246 5247 rpmhpd_opp_nom_l2: opp-336 { 5248 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5249 }; 5250 5251 rpmhpd_opp_turbo: opp-384 { 5252 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5253 }; 5254 5255 rpmhpd_opp_turbo_l1: opp-416 { 5256 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5257 }; 5258 }; 5259 }; 5260 }; 5261 5262 cpufreq_hw: cpufreq@17d91000 { 5263 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 5264 reg = <0 0x17d91000 0 0x1000>, 5265 <0 0x17d92000 0 0x1000>, 5266 <0 0x17d93000 0 0x1000>; 5267 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 5268 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 5269 clock-names = "xo", "alternate"; 5270 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, 5271 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>, 5272 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 5273 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5274 #freq-domain-cells = <1>; 5275 #clock-cells = <1>; 5276 }; 5277 5278 pmu@24091000 { 5279 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 5280 reg = <0 0x24091000 0 0x1000>; 5281 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 5282 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 5283 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5284 5285 operating-points-v2 = <&llcc_bwmon_opp_table>; 5286 5287 llcc_bwmon_opp_table: opp-table { 5288 compatible = "operating-points-v2"; 5289 5290 opp-0 { 5291 opp-peak-kBps = <2086000>; 5292 }; 5293 5294 opp-1 { 5295 opp-peak-kBps = <2929000>; 5296 }; 5297 5298 opp-2 { 5299 opp-peak-kBps = <5931000>; 5300 }; 5301 5302 opp-3 { 5303 opp-peak-kBps = <6515000>; 5304 }; 5305 5306 opp-4 { 5307 opp-peak-kBps = <7980000>; 5308 }; 5309 5310 opp-5 { 5311 opp-peak-kBps = <10437000>; 5312 }; 5313 5314 opp-6 { 5315 opp-peak-kBps = <12157000>; 5316 }; 5317 5318 opp-7 { 5319 opp-peak-kBps = <14060000>; 5320 }; 5321 5322 opp-8 { 5323 opp-peak-kBps = <16113000>; 5324 }; 5325 }; 5326 }; 5327 5328 pmu@240b6400 { 5329 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 5330 reg = <0 0x240b6400 0 0x600>; 5331 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>; 5332 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5333 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5334 5335 operating-points-v2 = <&cpu_bwmon_opp_table>; 5336 5337 cpu_bwmon_opp_table: opp-table { 5338 compatible = "operating-points-v2"; 5339 5340 opp-0 { 5341 opp-peak-kBps = <4577000>; 5342 }; 5343 5344 opp-1 { 5345 opp-peak-kBps = <7110000>; 5346 }; 5347 5348 opp-2 { 5349 opp-peak-kBps = <9155000>; 5350 }; 5351 5352 opp-3 { 5353 opp-peak-kBps = <12298000>; 5354 }; 5355 5356 opp-4 { 5357 opp-peak-kBps = <14236000>; 5358 }; 5359 5360 opp-5 { 5361 opp-peak-kBps = <16265000>; 5362 }; 5363 }; 5364 }; 5365 5366 gem_noc: interconnect@24100000 { 5367 compatible = "qcom,sm8550-gem-noc"; 5368 reg = <0 0x24100000 0 0xbb800>; 5369 #interconnect-cells = <2>; 5370 qcom,bcm-voters = <&apps_bcm_voter>; 5371 }; 5372 5373 system-cache-controller@25000000 { 5374 compatible = "qcom,sm8550-llcc"; 5375 reg = <0 0x25000000 0 0x200000>, 5376 <0 0x25200000 0 0x200000>, 5377 <0 0x25400000 0 0x200000>, 5378 <0 0x25600000 0 0x200000>, 5379 <0 0x25800000 0 0x200000>, 5380 <0 0x25a00000 0 0x200000>; 5381 reg-names = "llcc0_base", 5382 "llcc1_base", 5383 "llcc2_base", 5384 "llcc3_base", 5385 "llcc_broadcast_base", 5386 "llcc_broadcast_and_base"; 5387 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH 0>; 5388 }; 5389 5390 nsp_noc: interconnect@320c0000 { 5391 compatible = "qcom,sm8550-nsp-noc"; 5392 reg = <0 0x320c0000 0 0xe080>; 5393 #interconnect-cells = <2>; 5394 qcom,bcm-voters = <&apps_bcm_voter>; 5395 }; 5396 5397 remoteproc_cdsp: remoteproc@32300000 { 5398 compatible = "qcom,sm8550-cdsp-pas"; 5399 reg = <0x0 0x32300000 0x0 0x10000>; 5400 5401 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, 5402 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 5403 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 5404 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 5405 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 5406 interrupt-names = "wdog", "fatal", "ready", 5407 "handover", "stop-ack"; 5408 5409 clocks = <&rpmhcc RPMH_CXO_CLK>; 5410 clock-names = "xo"; 5411 5412 power-domains = <&rpmhpd RPMHPD_CX>, 5413 <&rpmhpd RPMHPD_MXC>, 5414 <&rpmhpd RPMHPD_NSP>; 5415 power-domain-names = "cx", "mxc", "nsp"; 5416 5417 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 5418 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5419 5420 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 5421 5422 qcom,qmp = <&aoss_qmp>; 5423 5424 qcom,smem-states = <&smp2p_cdsp_out 0>; 5425 qcom,smem-state-names = "stop"; 5426 5427 status = "disabled"; 5428 5429 glink-edge { 5430 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5431 IPCC_MPROC_SIGNAL_GLINK_QMP 5432 IRQ_TYPE_EDGE_RISING>; 5433 mboxes = <&ipcc IPCC_CLIENT_CDSP 5434 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5435 5436 label = "cdsp"; 5437 qcom,remote-pid = <5>; 5438 5439 fastrpc { 5440 compatible = "qcom,fastrpc"; 5441 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5442 label = "cdsp"; 5443 qcom,non-secure-domain; 5444 #address-cells = <1>; 5445 #size-cells = <0>; 5446 5447 compute-cb@1 { 5448 compatible = "qcom,fastrpc-compute-cb"; 5449 reg = <1>; 5450 iommus = <&apps_smmu 0x1961 0x0>, 5451 <&apps_smmu 0x0c01 0x20>, 5452 <&apps_smmu 0x19c1 0x10>; 5453 dma-coherent; 5454 }; 5455 5456 compute-cb@2 { 5457 compatible = "qcom,fastrpc-compute-cb"; 5458 reg = <2>; 5459 iommus = <&apps_smmu 0x1962 0x0>, 5460 <&apps_smmu 0x0c02 0x20>, 5461 <&apps_smmu 0x19c2 0x10>; 5462 dma-coherent; 5463 }; 5464 5465 compute-cb@3 { 5466 compatible = "qcom,fastrpc-compute-cb"; 5467 reg = <3>; 5468 iommus = <&apps_smmu 0x1963 0x0>, 5469 <&apps_smmu 0x0c03 0x20>, 5470 <&apps_smmu 0x19c3 0x10>; 5471 dma-coherent; 5472 }; 5473 5474 compute-cb@4 { 5475 compatible = "qcom,fastrpc-compute-cb"; 5476 reg = <4>; 5477 iommus = <&apps_smmu 0x1964 0x0>, 5478 <&apps_smmu 0x0c04 0x20>, 5479 <&apps_smmu 0x19c4 0x10>; 5480 dma-coherent; 5481 }; 5482 5483 compute-cb@5 { 5484 compatible = "qcom,fastrpc-compute-cb"; 5485 reg = <5>; 5486 iommus = <&apps_smmu 0x1965 0x0>, 5487 <&apps_smmu 0x0c05 0x20>, 5488 <&apps_smmu 0x19c5 0x10>; 5489 dma-coherent; 5490 }; 5491 5492 compute-cb@6 { 5493 compatible = "qcom,fastrpc-compute-cb"; 5494 reg = <6>; 5495 iommus = <&apps_smmu 0x1966 0x0>, 5496 <&apps_smmu 0x0c06 0x20>, 5497 <&apps_smmu 0x19c6 0x10>; 5498 dma-coherent; 5499 }; 5500 5501 compute-cb@7 { 5502 compatible = "qcom,fastrpc-compute-cb"; 5503 reg = <7>; 5504 iommus = <&apps_smmu 0x1967 0x0>, 5505 <&apps_smmu 0x0c07 0x20>, 5506 <&apps_smmu 0x19c7 0x10>; 5507 dma-coherent; 5508 }; 5509 5510 compute-cb@8 { 5511 compatible = "qcom,fastrpc-compute-cb"; 5512 reg = <8>; 5513 iommus = <&apps_smmu 0x1968 0x0>, 5514 <&apps_smmu 0x0c08 0x20>, 5515 <&apps_smmu 0x19c8 0x10>; 5516 dma-coherent; 5517 }; 5518 5519 /* note: secure cb9 in downstream */ 5520 }; 5521 }; 5522 }; 5523 }; 5524 5525 thermal-zones { 5526 aoss0-thermal { 5527 thermal-sensors = <&tsens0 0>; 5528 5529 trips { 5530 thermal-engine-config { 5531 temperature = <125000>; 5532 hysteresis = <1000>; 5533 type = "passive"; 5534 }; 5535 5536 reset-mon-config { 5537 temperature = <115000>; 5538 hysteresis = <5000>; 5539 type = "passive"; 5540 }; 5541 }; 5542 }; 5543 5544 cpuss0-thermal { 5545 thermal-sensors = <&tsens0 1>; 5546 5547 trips { 5548 thermal-engine-config { 5549 temperature = <125000>; 5550 hysteresis = <1000>; 5551 type = "passive"; 5552 }; 5553 5554 reset-mon-config { 5555 temperature = <115000>; 5556 hysteresis = <5000>; 5557 type = "passive"; 5558 }; 5559 }; 5560 }; 5561 5562 cpuss1-thermal { 5563 thermal-sensors = <&tsens0 2>; 5564 5565 trips { 5566 thermal-engine-config { 5567 temperature = <125000>; 5568 hysteresis = <1000>; 5569 type = "passive"; 5570 }; 5571 5572 reset-mon-config { 5573 temperature = <115000>; 5574 hysteresis = <5000>; 5575 type = "passive"; 5576 }; 5577 }; 5578 }; 5579 5580 cpuss2-thermal { 5581 thermal-sensors = <&tsens0 3>; 5582 5583 trips { 5584 thermal-engine-config { 5585 temperature = <125000>; 5586 hysteresis = <1000>; 5587 type = "passive"; 5588 }; 5589 5590 reset-mon-config { 5591 temperature = <115000>; 5592 hysteresis = <5000>; 5593 type = "passive"; 5594 }; 5595 }; 5596 }; 5597 5598 cpuss3-thermal { 5599 thermal-sensors = <&tsens0 4>; 5600 5601 trips { 5602 thermal-engine-config { 5603 temperature = <125000>; 5604 hysteresis = <1000>; 5605 type = "passive"; 5606 }; 5607 5608 reset-mon-config { 5609 temperature = <115000>; 5610 hysteresis = <5000>; 5611 type = "passive"; 5612 }; 5613 }; 5614 }; 5615 5616 cpu3-top-thermal { 5617 thermal-sensors = <&tsens0 5>; 5618 5619 trips { 5620 cpu3_top_alert0: trip-point0 { 5621 temperature = <90000>; 5622 hysteresis = <2000>; 5623 type = "passive"; 5624 }; 5625 5626 cpu3_top_alert1: trip-point1 { 5627 temperature = <95000>; 5628 hysteresis = <2000>; 5629 type = "passive"; 5630 }; 5631 5632 cpu3_top_crit: cpu-critical { 5633 temperature = <110000>; 5634 hysteresis = <1000>; 5635 type = "critical"; 5636 }; 5637 }; 5638 }; 5639 5640 cpu3-bottom-thermal { 5641 thermal-sensors = <&tsens0 6>; 5642 5643 trips { 5644 cpu3_bottom_alert0: trip-point0 { 5645 temperature = <90000>; 5646 hysteresis = <2000>; 5647 type = "passive"; 5648 }; 5649 5650 cpu3_bottom_alert1: trip-point1 { 5651 temperature = <95000>; 5652 hysteresis = <2000>; 5653 type = "passive"; 5654 }; 5655 5656 cpu3_bottom_crit: cpu-critical { 5657 temperature = <110000>; 5658 hysteresis = <1000>; 5659 type = "critical"; 5660 }; 5661 }; 5662 }; 5663 5664 cpu4-top-thermal { 5665 thermal-sensors = <&tsens0 7>; 5666 5667 trips { 5668 cpu4_top_alert0: trip-point0 { 5669 temperature = <90000>; 5670 hysteresis = <2000>; 5671 type = "passive"; 5672 }; 5673 5674 cpu4_top_alert1: trip-point1 { 5675 temperature = <95000>; 5676 hysteresis = <2000>; 5677 type = "passive"; 5678 }; 5679 5680 cpu4_top_crit: cpu-critical { 5681 temperature = <110000>; 5682 hysteresis = <1000>; 5683 type = "critical"; 5684 }; 5685 }; 5686 }; 5687 5688 cpu4-bottom-thermal { 5689 thermal-sensors = <&tsens0 8>; 5690 5691 trips { 5692 cpu4_bottom_alert0: trip-point0 { 5693 temperature = <90000>; 5694 hysteresis = <2000>; 5695 type = "passive"; 5696 }; 5697 5698 cpu4_bottom_alert1: trip-point1 { 5699 temperature = <95000>; 5700 hysteresis = <2000>; 5701 type = "passive"; 5702 }; 5703 5704 cpu4_bottom_crit: cpu-critical { 5705 temperature = <110000>; 5706 hysteresis = <1000>; 5707 type = "critical"; 5708 }; 5709 }; 5710 }; 5711 5712 cpu5-top-thermal { 5713 thermal-sensors = <&tsens0 9>; 5714 5715 trips { 5716 cpu5_top_alert0: trip-point0 { 5717 temperature = <90000>; 5718 hysteresis = <2000>; 5719 type = "passive"; 5720 }; 5721 5722 cpu5_top_alert1: trip-point1 { 5723 temperature = <95000>; 5724 hysteresis = <2000>; 5725 type = "passive"; 5726 }; 5727 5728 cpu5_top_crit: cpu-critical { 5729 temperature = <110000>; 5730 hysteresis = <1000>; 5731 type = "critical"; 5732 }; 5733 }; 5734 }; 5735 5736 cpu5-bottom-thermal { 5737 thermal-sensors = <&tsens0 10>; 5738 5739 trips { 5740 cpu5_bottom_alert0: trip-point0 { 5741 temperature = <90000>; 5742 hysteresis = <2000>; 5743 type = "passive"; 5744 }; 5745 5746 cpu5_bottom_alert1: trip-point1 { 5747 temperature = <95000>; 5748 hysteresis = <2000>; 5749 type = "passive"; 5750 }; 5751 5752 cpu5_bottom_crit: cpu-critical { 5753 temperature = <110000>; 5754 hysteresis = <1000>; 5755 type = "critical"; 5756 }; 5757 }; 5758 }; 5759 5760 cpu6-top-thermal { 5761 thermal-sensors = <&tsens0 11>; 5762 5763 trips { 5764 cpu6_top_alert0: trip-point0 { 5765 temperature = <90000>; 5766 hysteresis = <2000>; 5767 type = "passive"; 5768 }; 5769 5770 cpu6_top_alert1: trip-point1 { 5771 temperature = <95000>; 5772 hysteresis = <2000>; 5773 type = "passive"; 5774 }; 5775 5776 cpu6_top_crit: cpu-critical { 5777 temperature = <110000>; 5778 hysteresis = <1000>; 5779 type = "critical"; 5780 }; 5781 }; 5782 }; 5783 5784 cpu6-bottom-thermal { 5785 thermal-sensors = <&tsens0 12>; 5786 5787 trips { 5788 cpu6_bottom_alert0: trip-point0 { 5789 temperature = <90000>; 5790 hysteresis = <2000>; 5791 type = "passive"; 5792 }; 5793 5794 cpu6_bottom_alert1: trip-point1 { 5795 temperature = <95000>; 5796 hysteresis = <2000>; 5797 type = "passive"; 5798 }; 5799 5800 cpu6_bottom_crit: cpu-critical { 5801 temperature = <110000>; 5802 hysteresis = <1000>; 5803 type = "critical"; 5804 }; 5805 }; 5806 }; 5807 5808 cpu7-top-thermal { 5809 thermal-sensors = <&tsens0 13>; 5810 5811 trips { 5812 cpu7_top_alert0: trip-point0 { 5813 temperature = <90000>; 5814 hysteresis = <2000>; 5815 type = "passive"; 5816 }; 5817 5818 cpu7_top_alert1: trip-point1 { 5819 temperature = <95000>; 5820 hysteresis = <2000>; 5821 type = "passive"; 5822 }; 5823 5824 cpu7_top_crit: cpu-critical { 5825 temperature = <110000>; 5826 hysteresis = <1000>; 5827 type = "critical"; 5828 }; 5829 }; 5830 }; 5831 5832 cpu7-middle-thermal { 5833 thermal-sensors = <&tsens0 14>; 5834 5835 trips { 5836 cpu7_middle_alert0: trip-point0 { 5837 temperature = <90000>; 5838 hysteresis = <2000>; 5839 type = "passive"; 5840 }; 5841 5842 cpu7_middle_alert1: trip-point1 { 5843 temperature = <95000>; 5844 hysteresis = <2000>; 5845 type = "passive"; 5846 }; 5847 5848 cpu7_middle_crit: cpu-critical { 5849 temperature = <110000>; 5850 hysteresis = <1000>; 5851 type = "critical"; 5852 }; 5853 }; 5854 }; 5855 5856 cpu7-bottom-thermal { 5857 thermal-sensors = <&tsens0 15>; 5858 5859 trips { 5860 cpu7_bottom_alert0: trip-point0 { 5861 temperature = <90000>; 5862 hysteresis = <2000>; 5863 type = "passive"; 5864 }; 5865 5866 cpu7_bottom_alert1: trip-point1 { 5867 temperature = <95000>; 5868 hysteresis = <2000>; 5869 type = "passive"; 5870 }; 5871 5872 cpu7_bottom_crit: cpu-critical { 5873 temperature = <110000>; 5874 hysteresis = <1000>; 5875 type = "critical"; 5876 }; 5877 }; 5878 }; 5879 5880 aoss1-thermal { 5881 thermal-sensors = <&tsens1 0>; 5882 5883 trips { 5884 thermal-engine-config { 5885 temperature = <125000>; 5886 hysteresis = <1000>; 5887 type = "passive"; 5888 }; 5889 5890 reset-mon-config { 5891 temperature = <115000>; 5892 hysteresis = <5000>; 5893 type = "passive"; 5894 }; 5895 }; 5896 }; 5897 5898 cpu0-thermal { 5899 thermal-sensors = <&tsens1 1>; 5900 5901 trips { 5902 cpu0_alert0: trip-point0 { 5903 temperature = <90000>; 5904 hysteresis = <2000>; 5905 type = "passive"; 5906 }; 5907 5908 cpu0_alert1: trip-point1 { 5909 temperature = <95000>; 5910 hysteresis = <2000>; 5911 type = "passive"; 5912 }; 5913 5914 cpu0_crit: cpu-critical { 5915 temperature = <110000>; 5916 hysteresis = <1000>; 5917 type = "critical"; 5918 }; 5919 }; 5920 }; 5921 5922 cpu1-thermal { 5923 thermal-sensors = <&tsens1 2>; 5924 5925 trips { 5926 cpu1_alert0: trip-point0 { 5927 temperature = <90000>; 5928 hysteresis = <2000>; 5929 type = "passive"; 5930 }; 5931 5932 cpu1_alert1: trip-point1 { 5933 temperature = <95000>; 5934 hysteresis = <2000>; 5935 type = "passive"; 5936 }; 5937 5938 cpu1_crit: cpu-critical { 5939 temperature = <110000>; 5940 hysteresis = <1000>; 5941 type = "critical"; 5942 }; 5943 }; 5944 }; 5945 5946 cpu2-thermal { 5947 thermal-sensors = <&tsens1 3>; 5948 5949 trips { 5950 cpu2_alert0: trip-point0 { 5951 temperature = <90000>; 5952 hysteresis = <2000>; 5953 type = "passive"; 5954 }; 5955 5956 cpu2_alert1: trip-point1 { 5957 temperature = <95000>; 5958 hysteresis = <2000>; 5959 type = "passive"; 5960 }; 5961 5962 cpu2_crit: cpu-critical { 5963 temperature = <110000>; 5964 hysteresis = <1000>; 5965 type = "critical"; 5966 }; 5967 }; 5968 }; 5969 5970 cdsp0-thermal { 5971 polling-delay-passive = <10>; 5972 5973 thermal-sensors = <&tsens2 4>; 5974 5975 trips { 5976 thermal-engine-config { 5977 temperature = <125000>; 5978 hysteresis = <1000>; 5979 type = "passive"; 5980 }; 5981 5982 thermal-hal-config { 5983 temperature = <125000>; 5984 hysteresis = <1000>; 5985 type = "passive"; 5986 }; 5987 5988 reset-mon-config { 5989 temperature = <115000>; 5990 hysteresis = <5000>; 5991 type = "passive"; 5992 }; 5993 5994 cdsp0_junction_config: junction-config { 5995 temperature = <95000>; 5996 hysteresis = <5000>; 5997 type = "passive"; 5998 }; 5999 }; 6000 }; 6001 6002 cdsp1-thermal { 6003 polling-delay-passive = <10>; 6004 6005 thermal-sensors = <&tsens2 5>; 6006 6007 trips { 6008 thermal-engine-config { 6009 temperature = <125000>; 6010 hysteresis = <1000>; 6011 type = "passive"; 6012 }; 6013 6014 thermal-hal-config { 6015 temperature = <125000>; 6016 hysteresis = <1000>; 6017 type = "passive"; 6018 }; 6019 6020 reset-mon-config { 6021 temperature = <115000>; 6022 hysteresis = <5000>; 6023 type = "passive"; 6024 }; 6025 6026 cdsp1_junction_config: junction-config { 6027 temperature = <95000>; 6028 hysteresis = <5000>; 6029 type = "passive"; 6030 }; 6031 }; 6032 }; 6033 6034 cdsp2-thermal { 6035 polling-delay-passive = <10>; 6036 6037 thermal-sensors = <&tsens2 6>; 6038 6039 trips { 6040 thermal-engine-config { 6041 temperature = <125000>; 6042 hysteresis = <1000>; 6043 type = "passive"; 6044 }; 6045 6046 thermal-hal-config { 6047 temperature = <125000>; 6048 hysteresis = <1000>; 6049 type = "passive"; 6050 }; 6051 6052 reset-mon-config { 6053 temperature = <115000>; 6054 hysteresis = <5000>; 6055 type = "passive"; 6056 }; 6057 6058 cdsp2_junction_config: junction-config { 6059 temperature = <95000>; 6060 hysteresis = <5000>; 6061 type = "passive"; 6062 }; 6063 }; 6064 }; 6065 6066 cdsp3-thermal { 6067 polling-delay-passive = <10>; 6068 6069 thermal-sensors = <&tsens2 7>; 6070 6071 trips { 6072 thermal-engine-config { 6073 temperature = <125000>; 6074 hysteresis = <1000>; 6075 type = "passive"; 6076 }; 6077 6078 thermal-hal-config { 6079 temperature = <125000>; 6080 hysteresis = <1000>; 6081 type = "passive"; 6082 }; 6083 6084 reset-mon-config { 6085 temperature = <115000>; 6086 hysteresis = <5000>; 6087 type = "passive"; 6088 }; 6089 6090 cdsp3_junction_config: junction-config { 6091 temperature = <95000>; 6092 hysteresis = <5000>; 6093 type = "passive"; 6094 }; 6095 }; 6096 }; 6097 6098 video-thermal { 6099 thermal-sensors = <&tsens1 8>; 6100 6101 trips { 6102 thermal-engine-config { 6103 temperature = <125000>; 6104 hysteresis = <1000>; 6105 type = "passive"; 6106 }; 6107 6108 reset-mon-config { 6109 temperature = <115000>; 6110 hysteresis = <5000>; 6111 type = "passive"; 6112 }; 6113 }; 6114 }; 6115 6116 mem-thermal { 6117 polling-delay-passive = <10>; 6118 6119 thermal-sensors = <&tsens1 9>; 6120 6121 trips { 6122 thermal-engine-config { 6123 temperature = <125000>; 6124 hysteresis = <1000>; 6125 type = "passive"; 6126 }; 6127 6128 ddr_config0: ddr0-config { 6129 temperature = <90000>; 6130 hysteresis = <5000>; 6131 type = "passive"; 6132 }; 6133 6134 reset-mon-config { 6135 temperature = <115000>; 6136 hysteresis = <5000>; 6137 type = "passive"; 6138 }; 6139 }; 6140 }; 6141 6142 modem0-thermal { 6143 thermal-sensors = <&tsens1 10>; 6144 6145 trips { 6146 thermal-engine-config { 6147 temperature = <125000>; 6148 hysteresis = <1000>; 6149 type = "passive"; 6150 }; 6151 6152 mdmss0_config0: mdmss0-config0 { 6153 temperature = <102000>; 6154 hysteresis = <3000>; 6155 type = "passive"; 6156 }; 6157 6158 mdmss0_config1: mdmss0-config1 { 6159 temperature = <105000>; 6160 hysteresis = <3000>; 6161 type = "passive"; 6162 }; 6163 6164 reset-mon-config { 6165 temperature = <115000>; 6166 hysteresis = <5000>; 6167 type = "passive"; 6168 }; 6169 }; 6170 }; 6171 6172 modem1-thermal { 6173 thermal-sensors = <&tsens1 11>; 6174 6175 trips { 6176 thermal-engine-config { 6177 temperature = <125000>; 6178 hysteresis = <1000>; 6179 type = "passive"; 6180 }; 6181 6182 mdmss1_config0: mdmss1-config0 { 6183 temperature = <102000>; 6184 hysteresis = <3000>; 6185 type = "passive"; 6186 }; 6187 6188 mdmss1_config1: mdmss1-config1 { 6189 temperature = <105000>; 6190 hysteresis = <3000>; 6191 type = "passive"; 6192 }; 6193 6194 reset-mon-config { 6195 temperature = <115000>; 6196 hysteresis = <5000>; 6197 type = "passive"; 6198 }; 6199 }; 6200 }; 6201 6202 modem2-thermal { 6203 thermal-sensors = <&tsens1 12>; 6204 6205 trips { 6206 thermal-engine-config { 6207 temperature = <125000>; 6208 hysteresis = <1000>; 6209 type = "passive"; 6210 }; 6211 6212 mdmss2_config0: mdmss2-config0 { 6213 temperature = <102000>; 6214 hysteresis = <3000>; 6215 type = "passive"; 6216 }; 6217 6218 mdmss2_config1: mdmss2-config1 { 6219 temperature = <105000>; 6220 hysteresis = <3000>; 6221 type = "passive"; 6222 }; 6223 6224 reset-mon-config { 6225 temperature = <115000>; 6226 hysteresis = <5000>; 6227 type = "passive"; 6228 }; 6229 }; 6230 }; 6231 6232 modem3-thermal { 6233 thermal-sensors = <&tsens1 13>; 6234 6235 trips { 6236 thermal-engine-config { 6237 temperature = <125000>; 6238 hysteresis = <1000>; 6239 type = "passive"; 6240 }; 6241 6242 mdmss3_config0: mdmss3-config0 { 6243 temperature = <102000>; 6244 hysteresis = <3000>; 6245 type = "passive"; 6246 }; 6247 6248 mdmss3_config1: mdmss3-config1 { 6249 temperature = <105000>; 6250 hysteresis = <3000>; 6251 type = "passive"; 6252 }; 6253 6254 reset-mon-config { 6255 temperature = <115000>; 6256 hysteresis = <5000>; 6257 type = "passive"; 6258 }; 6259 }; 6260 }; 6261 6262 camera0-thermal { 6263 thermal-sensors = <&tsens1 14>; 6264 6265 trips { 6266 thermal-engine-config { 6267 temperature = <125000>; 6268 hysteresis = <1000>; 6269 type = "passive"; 6270 }; 6271 6272 reset-mon-config { 6273 temperature = <115000>; 6274 hysteresis = <5000>; 6275 type = "passive"; 6276 }; 6277 }; 6278 }; 6279 6280 camera1-thermal { 6281 thermal-sensors = <&tsens1 15>; 6282 6283 trips { 6284 thermal-engine-config { 6285 temperature = <125000>; 6286 hysteresis = <1000>; 6287 type = "passive"; 6288 }; 6289 6290 reset-mon-config { 6291 temperature = <115000>; 6292 hysteresis = <5000>; 6293 type = "passive"; 6294 }; 6295 }; 6296 }; 6297 6298 aoss2-thermal { 6299 thermal-sensors = <&tsens2 0>; 6300 6301 trips { 6302 thermal-engine-config { 6303 temperature = <125000>; 6304 hysteresis = <1000>; 6305 type = "passive"; 6306 }; 6307 6308 reset-mon-config { 6309 temperature = <115000>; 6310 hysteresis = <5000>; 6311 type = "passive"; 6312 }; 6313 }; 6314 }; 6315 6316 gpuss-0-thermal { 6317 polling-delay-passive = <10>; 6318 6319 thermal-sensors = <&tsens2 1>; 6320 6321 cooling-maps { 6322 map0 { 6323 trip = <&gpu0_alert0>; 6324 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6325 }; 6326 }; 6327 6328 trips { 6329 gpu0_alert0: trip-point0 { 6330 temperature = <85000>; 6331 hysteresis = <1000>; 6332 type = "passive"; 6333 }; 6334 6335 trip-point1 { 6336 temperature = <90000>; 6337 hysteresis = <1000>; 6338 type = "hot"; 6339 }; 6340 6341 trip-point2 { 6342 temperature = <110000>; 6343 hysteresis = <1000>; 6344 type = "critical"; 6345 }; 6346 }; 6347 }; 6348 6349 gpuss-1-thermal { 6350 polling-delay-passive = <10>; 6351 6352 thermal-sensors = <&tsens2 2>; 6353 6354 cooling-maps { 6355 map0 { 6356 trip = <&gpu1_alert0>; 6357 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6358 }; 6359 }; 6360 6361 trips { 6362 gpu1_alert0: trip-point0 { 6363 temperature = <85000>; 6364 hysteresis = <1000>; 6365 type = "passive"; 6366 }; 6367 6368 trip-point1 { 6369 temperature = <90000>; 6370 hysteresis = <1000>; 6371 type = "hot"; 6372 }; 6373 6374 trip-point2 { 6375 temperature = <110000>; 6376 hysteresis = <1000>; 6377 type = "critical"; 6378 }; 6379 }; 6380 }; 6381 6382 gpuss-2-thermal { 6383 polling-delay-passive = <10>; 6384 6385 thermal-sensors = <&tsens2 3>; 6386 6387 cooling-maps { 6388 map0 { 6389 trip = <&gpu2_alert0>; 6390 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6391 }; 6392 }; 6393 6394 trips { 6395 gpu2_alert0: trip-point0 { 6396 temperature = <85000>; 6397 hysteresis = <1000>; 6398 type = "passive"; 6399 }; 6400 6401 trip-point1 { 6402 temperature = <90000>; 6403 hysteresis = <1000>; 6404 type = "hot"; 6405 }; 6406 6407 trip-point2 { 6408 temperature = <110000>; 6409 hysteresis = <1000>; 6410 type = "critical"; 6411 }; 6412 }; 6413 }; 6414 6415 gpuss-3-thermal { 6416 polling-delay-passive = <10>; 6417 6418 thermal-sensors = <&tsens2 4>; 6419 6420 cooling-maps { 6421 map0 { 6422 trip = <&gpu3_alert0>; 6423 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6424 }; 6425 }; 6426 6427 trips { 6428 gpu3_alert0: trip-point0 { 6429 temperature = <85000>; 6430 hysteresis = <1000>; 6431 type = "passive"; 6432 }; 6433 6434 trip-point1 { 6435 temperature = <90000>; 6436 hysteresis = <1000>; 6437 type = "hot"; 6438 }; 6439 6440 trip-point2 { 6441 temperature = <110000>; 6442 hysteresis = <1000>; 6443 type = "critical"; 6444 }; 6445 }; 6446 }; 6447 6448 gpuss-4-thermal { 6449 polling-delay-passive = <10>; 6450 6451 thermal-sensors = <&tsens2 5>; 6452 6453 cooling-maps { 6454 map0 { 6455 trip = <&gpu4_alert0>; 6456 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6457 }; 6458 }; 6459 6460 trips { 6461 gpu4_alert0: trip-point0 { 6462 temperature = <85000>; 6463 hysteresis = <1000>; 6464 type = "passive"; 6465 }; 6466 6467 trip-point1 { 6468 temperature = <90000>; 6469 hysteresis = <1000>; 6470 type = "hot"; 6471 }; 6472 6473 trip-point2 { 6474 temperature = <110000>; 6475 hysteresis = <1000>; 6476 type = "critical"; 6477 }; 6478 }; 6479 }; 6480 6481 gpuss-5-thermal { 6482 polling-delay-passive = <10>; 6483 6484 thermal-sensors = <&tsens2 6>; 6485 6486 cooling-maps { 6487 map0 { 6488 trip = <&gpu5_alert0>; 6489 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6490 }; 6491 }; 6492 6493 trips { 6494 gpu5_alert0: trip-point0 { 6495 temperature = <85000>; 6496 hysteresis = <1000>; 6497 type = "passive"; 6498 }; 6499 6500 trip-point1 { 6501 temperature = <90000>; 6502 hysteresis = <1000>; 6503 type = "hot"; 6504 }; 6505 6506 trip-point2 { 6507 temperature = <110000>; 6508 hysteresis = <1000>; 6509 type = "critical"; 6510 }; 6511 }; 6512 }; 6513 6514 gpuss-6-thermal { 6515 polling-delay-passive = <10>; 6516 6517 thermal-sensors = <&tsens2 7>; 6518 6519 cooling-maps { 6520 map0 { 6521 trip = <&gpu6_alert0>; 6522 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6523 }; 6524 }; 6525 6526 trips { 6527 gpu6_alert0: trip-point0 { 6528 temperature = <85000>; 6529 hysteresis = <1000>; 6530 type = "passive"; 6531 }; 6532 6533 trip-point1 { 6534 temperature = <90000>; 6535 hysteresis = <1000>; 6536 type = "hot"; 6537 }; 6538 6539 trip-point2 { 6540 temperature = <110000>; 6541 hysteresis = <1000>; 6542 type = "critical"; 6543 }; 6544 }; 6545 }; 6546 6547 gpuss-7-thermal { 6548 polling-delay-passive = <10>; 6549 6550 thermal-sensors = <&tsens2 8>; 6551 6552 cooling-maps { 6553 map0 { 6554 trip = <&gpu7_alert0>; 6555 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6556 }; 6557 }; 6558 6559 trips { 6560 gpu7_alert0: trip-point0 { 6561 temperature = <85000>; 6562 hysteresis = <1000>; 6563 type = "passive"; 6564 }; 6565 6566 trip-point1 { 6567 temperature = <90000>; 6568 hysteresis = <1000>; 6569 type = "hot"; 6570 }; 6571 6572 trip-point2 { 6573 temperature = <110000>; 6574 hysteresis = <1000>; 6575 type = "critical"; 6576 }; 6577 }; 6578 }; 6579 }; 6580 6581 timer { 6582 compatible = "arm,armv8-timer"; 6583 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 6584 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 6585 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 6586 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; 6587 }; 6588}; 6589