1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sm8450-videocc.h> 9#include <dt-bindings/clock/qcom,sm8550-camcc.h> 10#include <dt-bindings/clock/qcom,sm8550-gcc.h> 11#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 12#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 13#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 14#include <dt-bindings/dma/qcom-gpi.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/interconnect/qcom,icc.h> 19#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/power/qcom,rpmhpd.h> 23#include <dt-bindings/soc/qcom,gpr.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 26#include <dt-bindings/phy/phy-qcom-qmp.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 chosen { }; 36 37 clocks { 38 xo_board: xo-board { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 }; 47 48 bi_tcxo_div2: bi-tcxo-div2-clk { 49 #clock-cells = <0>; 50 compatible = "fixed-factor-clock"; 51 clocks = <&rpmhcc RPMH_CXO_CLK>; 52 clock-mult = <1>; 53 clock-div = <2>; 54 }; 55 56 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 57 #clock-cells = <0>; 58 compatible = "fixed-factor-clock"; 59 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 60 clock-mult = <1>; 61 clock-div = <2>; 62 }; 63 }; 64 65 cpus { 66 #address-cells = <2>; 67 #size-cells = <0>; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a510"; 72 reg = <0 0>; 73 clocks = <&cpufreq_hw 0>; 74 enable-method = "psci"; 75 next-level-cache = <&l2_0>; 76 power-domains = <&cpu_pd0>; 77 power-domain-names = "psci"; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 capacity-dmips-mhz = <1024>; 80 dynamic-power-coefficient = <100>; 81 #cooling-cells = <2>; 82 l2_0: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 cache-unified; 86 next-level-cache = <&l3_0>; 87 l3_0: l3-cache { 88 compatible = "cache"; 89 cache-level = <3>; 90 cache-unified; 91 }; 92 }; 93 }; 94 95 cpu1: cpu@100 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a510"; 98 reg = <0 0x100>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 next-level-cache = <&l2_100>; 102 power-domains = <&cpu_pd1>; 103 power-domain-names = "psci"; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 capacity-dmips-mhz = <1024>; 106 dynamic-power-coefficient = <100>; 107 #cooling-cells = <2>; 108 l2_100: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&l3_0>; 113 }; 114 }; 115 116 cpu2: cpu@200 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a510"; 119 reg = <0 0x200>; 120 clocks = <&cpufreq_hw 0>; 121 enable-method = "psci"; 122 next-level-cache = <&l2_200>; 123 power-domains = <&cpu_pd2>; 124 power-domain-names = "psci"; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 capacity-dmips-mhz = <1024>; 127 dynamic-power-coefficient = <100>; 128 #cooling-cells = <2>; 129 l2_200: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 next-level-cache = <&l3_0>; 134 }; 135 }; 136 137 cpu3: cpu@300 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a715"; 140 reg = <0 0x300>; 141 clocks = <&cpufreq_hw 1>; 142 enable-method = "psci"; 143 next-level-cache = <&l2_300>; 144 power-domains = <&cpu_pd3>; 145 power-domain-names = "psci"; 146 qcom,freq-domain = <&cpufreq_hw 1>; 147 capacity-dmips-mhz = <1792>; 148 dynamic-power-coefficient = <270>; 149 #cooling-cells = <2>; 150 l2_300: l2-cache { 151 compatible = "cache"; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&l3_0>; 155 }; 156 }; 157 158 cpu4: cpu@400 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a715"; 161 reg = <0 0x400>; 162 clocks = <&cpufreq_hw 1>; 163 enable-method = "psci"; 164 next-level-cache = <&l2_400>; 165 power-domains = <&cpu_pd4>; 166 power-domain-names = "psci"; 167 qcom,freq-domain = <&cpufreq_hw 1>; 168 capacity-dmips-mhz = <1792>; 169 dynamic-power-coefficient = <270>; 170 #cooling-cells = <2>; 171 l2_400: l2-cache { 172 compatible = "cache"; 173 cache-level = <2>; 174 cache-unified; 175 next-level-cache = <&l3_0>; 176 }; 177 }; 178 179 cpu5: cpu@500 { 180 device_type = "cpu"; 181 compatible = "arm,cortex-a710"; 182 reg = <0 0x500>; 183 clocks = <&cpufreq_hw 1>; 184 enable-method = "psci"; 185 next-level-cache = <&l2_500>; 186 power-domains = <&cpu_pd5>; 187 power-domain-names = "psci"; 188 qcom,freq-domain = <&cpufreq_hw 1>; 189 capacity-dmips-mhz = <1792>; 190 dynamic-power-coefficient = <270>; 191 #cooling-cells = <2>; 192 l2_500: l2-cache { 193 compatible = "cache"; 194 cache-level = <2>; 195 cache-unified; 196 next-level-cache = <&l3_0>; 197 }; 198 }; 199 200 cpu6: cpu@600 { 201 device_type = "cpu"; 202 compatible = "arm,cortex-a710"; 203 reg = <0 0x600>; 204 clocks = <&cpufreq_hw 1>; 205 enable-method = "psci"; 206 next-level-cache = <&l2_600>; 207 power-domains = <&cpu_pd6>; 208 power-domain-names = "psci"; 209 qcom,freq-domain = <&cpufreq_hw 1>; 210 capacity-dmips-mhz = <1792>; 211 dynamic-power-coefficient = <270>; 212 #cooling-cells = <2>; 213 l2_600: l2-cache { 214 compatible = "cache"; 215 cache-level = <2>; 216 cache-unified; 217 next-level-cache = <&l3_0>; 218 }; 219 }; 220 221 cpu7: cpu@700 { 222 device_type = "cpu"; 223 compatible = "arm,cortex-x3"; 224 reg = <0 0x700>; 225 clocks = <&cpufreq_hw 2>; 226 enable-method = "psci"; 227 next-level-cache = <&l2_700>; 228 power-domains = <&cpu_pd7>; 229 power-domain-names = "psci"; 230 qcom,freq-domain = <&cpufreq_hw 2>; 231 capacity-dmips-mhz = <1894>; 232 dynamic-power-coefficient = <588>; 233 #cooling-cells = <2>; 234 l2_700: l2-cache { 235 compatible = "cache"; 236 cache-level = <2>; 237 cache-unified; 238 next-level-cache = <&l3_0>; 239 }; 240 }; 241 242 cpu-map { 243 cluster0 { 244 core0 { 245 cpu = <&cpu0>; 246 }; 247 248 core1 { 249 cpu = <&cpu1>; 250 }; 251 252 core2 { 253 cpu = <&cpu2>; 254 }; 255 256 core3 { 257 cpu = <&cpu3>; 258 }; 259 260 core4 { 261 cpu = <&cpu4>; 262 }; 263 264 core5 { 265 cpu = <&cpu5>; 266 }; 267 268 core6 { 269 cpu = <&cpu6>; 270 }; 271 272 core7 { 273 cpu = <&cpu7>; 274 }; 275 }; 276 }; 277 278 idle-states { 279 entry-method = "psci"; 280 281 little_cpu_sleep_0: cpu-sleep-0-0 { 282 compatible = "arm,idle-state"; 283 idle-state-name = "silver-rail-power-collapse"; 284 arm,psci-suspend-param = <0x40000004>; 285 entry-latency-us = <550>; 286 exit-latency-us = <750>; 287 min-residency-us = <6700>; 288 local-timer-stop; 289 }; 290 291 big_cpu_sleep_0: cpu-sleep-1-0 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "gold-rail-power-collapse"; 294 arm,psci-suspend-param = <0x40000004>; 295 entry-latency-us = <600>; 296 exit-latency-us = <1300>; 297 min-residency-us = <8136>; 298 local-timer-stop; 299 }; 300 301 prime_cpu_sleep_0: cpu-sleep-2-0 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "goldplus-rail-power-collapse"; 304 arm,psci-suspend-param = <0x40000004>; 305 entry-latency-us = <500>; 306 exit-latency-us = <1350>; 307 min-residency-us = <7480>; 308 local-timer-stop; 309 }; 310 }; 311 312 domain-idle-states { 313 cluster_sleep_0: cluster-sleep-0 { 314 compatible = "domain-idle-state"; 315 arm,psci-suspend-param = <0x41000044>; 316 entry-latency-us = <750>; 317 exit-latency-us = <2350>; 318 min-residency-us = <9144>; 319 }; 320 321 cluster_sleep_1: cluster-sleep-1 { 322 compatible = "domain-idle-state"; 323 arm,psci-suspend-param = <0x4100c344>; 324 entry-latency-us = <2800>; 325 exit-latency-us = <4400>; 326 min-residency-us = <10150>; 327 }; 328 }; 329 }; 330 331 firmware { 332 scm: scm { 333 compatible = "qcom,scm-sm8550", "qcom,scm"; 334 qcom,dload-mode = <&tcsr 0x19000>; 335 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 336 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 337 }; 338 }; 339 340 clk_virt: interconnect-0 { 341 compatible = "qcom,sm8550-clk-virt"; 342 #interconnect-cells = <2>; 343 qcom,bcm-voters = <&apps_bcm_voter>; 344 }; 345 346 mc_virt: interconnect-1 { 347 compatible = "qcom,sm8550-mc-virt"; 348 #interconnect-cells = <2>; 349 qcom,bcm-voters = <&apps_bcm_voter>; 350 }; 351 352 qup_opp_table_100mhz: opp-table-qup100mhz { 353 compatible = "operating-points-v2"; 354 355 opp-75000000 { 356 opp-hz = /bits/ 64 <75000000>; 357 required-opps = <&rpmhpd_opp_low_svs>; 358 }; 359 360 opp-100000000 { 361 opp-hz = /bits/ 64 <100000000>; 362 required-opps = <&rpmhpd_opp_svs>; 363 }; 364 }; 365 366 qup_opp_table_120mhz: opp-table-qup120mhz { 367 compatible = "operating-points-v2"; 368 369 opp-75000000 { 370 opp-hz = /bits/ 64 <75000000>; 371 required-opps = <&rpmhpd_opp_low_svs>; 372 }; 373 374 opp-120000000 { 375 opp-hz = /bits/ 64 <120000000>; 376 required-opps = <&rpmhpd_opp_svs>; 377 }; 378 }; 379 380 qup_opp_table_125mhz: opp-table-qup125mhz { 381 compatible = "operating-points-v2"; 382 383 opp-75000000 { 384 opp-hz = /bits/ 64 <75000000>; 385 required-opps = <&rpmhpd_opp_low_svs>; 386 }; 387 388 opp-125000000 { 389 opp-hz = /bits/ 64 <125000000>; 390 required-opps = <&rpmhpd_opp_svs>; 391 }; 392 }; 393 394 memory@a0000000 { 395 device_type = "memory"; 396 /* We expect the bootloader to fill in the size */ 397 reg = <0 0xa0000000 0 0>; 398 }; 399 400 pmu-a510 { 401 compatible = "arm,cortex-a510-pmu"; 402 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 403 }; 404 405 pmu-a710 { 406 compatible = "arm,cortex-a710-pmu"; 407 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 408 }; 409 410 pmu-a715 { 411 compatible = "arm,cortex-a715-pmu"; 412 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster2>; 413 }; 414 415 pmu-x3 { 416 compatible = "arm,cortex-x3-pmu"; 417 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster3>; 418 }; 419 420 psci { 421 compatible = "arm,psci-1.0"; 422 method = "smc"; 423 424 cpu_pd0: power-domain-cpu0 { 425 #power-domain-cells = <0>; 426 power-domains = <&cluster_pd>; 427 domain-idle-states = <&little_cpu_sleep_0>; 428 }; 429 430 cpu_pd1: power-domain-cpu1 { 431 #power-domain-cells = <0>; 432 power-domains = <&cluster_pd>; 433 domain-idle-states = <&little_cpu_sleep_0>; 434 }; 435 436 cpu_pd2: power-domain-cpu2 { 437 #power-domain-cells = <0>; 438 power-domains = <&cluster_pd>; 439 domain-idle-states = <&little_cpu_sleep_0>; 440 }; 441 442 cpu_pd3: power-domain-cpu3 { 443 #power-domain-cells = <0>; 444 power-domains = <&cluster_pd>; 445 domain-idle-states = <&big_cpu_sleep_0>; 446 }; 447 448 cpu_pd4: power-domain-cpu4 { 449 #power-domain-cells = <0>; 450 power-domains = <&cluster_pd>; 451 domain-idle-states = <&big_cpu_sleep_0>; 452 }; 453 454 cpu_pd5: power-domain-cpu5 { 455 #power-domain-cells = <0>; 456 power-domains = <&cluster_pd>; 457 domain-idle-states = <&big_cpu_sleep_0>; 458 }; 459 460 cpu_pd6: power-domain-cpu6 { 461 #power-domain-cells = <0>; 462 power-domains = <&cluster_pd>; 463 domain-idle-states = <&big_cpu_sleep_0>; 464 }; 465 466 cpu_pd7: power-domain-cpu7 { 467 #power-domain-cells = <0>; 468 power-domains = <&cluster_pd>; 469 domain-idle-states = <&prime_cpu_sleep_0>; 470 }; 471 472 cluster_pd: power-domain-cluster { 473 #power-domain-cells = <0>; 474 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; 475 }; 476 }; 477 478 reserved_memory: reserved-memory { 479 #address-cells = <2>; 480 #size-cells = <2>; 481 ranges; 482 483 hyp_mem: hyp-region@80000000 { 484 reg = <0 0x80000000 0 0xa00000>; 485 no-map; 486 }; 487 488 cpusys_vm_mem: cpusys-vm-region@80a00000 { 489 reg = <0 0x80a00000 0 0x400000>; 490 no-map; 491 }; 492 493 hyp_tags_mem: hyp-tags-region@80e00000 { 494 reg = <0 0x80e00000 0 0x3d0000>; 495 no-map; 496 }; 497 498 xbl_sc_mem: xbl-sc-region@d8100000 { 499 reg = <0 0xd8100000 0 0x40000>; 500 no-map; 501 }; 502 503 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 504 reg = <0 0x811d0000 0 0x30000>; 505 no-map; 506 }; 507 508 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 509 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 510 reg = <0 0x81a00000 0 0x260000>; 511 no-map; 512 }; 513 514 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 515 compatible = "qcom,cmd-db"; 516 reg = <0 0x81c60000 0 0x20000>; 517 no-map; 518 }; 519 520 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 521 aop_config_merged_mem: aop-config-merged-region@81c80000 { 522 reg = <0 0x81c80000 0 0x74000>; 523 no-map; 524 }; 525 526 /* secdata region can be reused by apps */ 527 smem: smem@81d00000 { 528 compatible = "qcom,smem"; 529 reg = <0 0x81d00000 0 0x200000>; 530 hwlocks = <&tcsr_mutex 3>; 531 no-map; 532 }; 533 534 adsp_mhi_mem: adsp-mhi-region@81f00000 { 535 reg = <0 0x81f00000 0 0x20000>; 536 no-map; 537 }; 538 539 global_sync_mem: global-sync-region@82600000 { 540 reg = <0 0x82600000 0 0x100000>; 541 no-map; 542 }; 543 544 tz_stat_mem: tz-stat-region@82700000 { 545 reg = <0 0x82700000 0 0x100000>; 546 no-map; 547 }; 548 549 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 550 reg = <0 0x82800000 0 0x4600000>; 551 no-map; 552 }; 553 554 mpss_mem: mpss-region@8a800000 { 555 reg = <0 0x8a800000 0 0x10800000>; 556 no-map; 557 }; 558 559 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 560 reg = <0 0x9b000000 0 0x80000>; 561 no-map; 562 }; 563 564 ipa_fw_mem: ipa-fw-region@9b080000 { 565 reg = <0 0x9b080000 0 0x10000>; 566 no-map; 567 }; 568 569 ipa_gsi_mem: ipa-gsi-region@9b090000 { 570 reg = <0 0x9b090000 0 0xa000>; 571 no-map; 572 }; 573 574 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 575 reg = <0 0x9b09a000 0 0x2000>; 576 no-map; 577 }; 578 579 spss_region_mem: spss-region@9b100000 { 580 reg = <0 0x9b100000 0 0x180000>; 581 no-map; 582 }; 583 584 /* First part of the "SPU secure shared memory" region */ 585 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 586 reg = <0 0x9b280000 0 0x60000>; 587 no-map; 588 }; 589 590 /* Second part of the "SPU secure shared memory" region */ 591 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 592 reg = <0 0x9b2e0000 0 0x20000>; 593 no-map; 594 }; 595 596 camera_mem: camera-region@9b300000 { 597 reg = <0 0x9b300000 0 0x800000>; 598 no-map; 599 }; 600 601 video_mem: video-region@9bb00000 { 602 reg = <0 0x9bb00000 0 0x700000>; 603 no-map; 604 }; 605 606 cvp_mem: cvp-region@9c200000 { 607 reg = <0 0x9c200000 0 0x700000>; 608 no-map; 609 }; 610 611 cdsp_mem: cdsp-region@9c900000 { 612 reg = <0 0x9c900000 0 0x2000000>; 613 no-map; 614 }; 615 616 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 617 reg = <0 0x9e900000 0 0x80000>; 618 no-map; 619 }; 620 621 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 622 reg = <0 0x9e980000 0 0x80000>; 623 no-map; 624 }; 625 626 adspslpi_mem: adspslpi-region@9ea00000 { 627 reg = <0 0x9ea00000 0 0x4080000>; 628 no-map; 629 }; 630 631 /* uefi region can be reused by apps */ 632 633 /* Linux kernel image is loaded at 0xa8000000 */ 634 635 rmtfs_mem: rmtfs-region@d4a80000 { 636 compatible = "qcom,rmtfs-mem"; 637 reg = <0x0 0xd4a80000 0x0 0x280000>; 638 no-map; 639 640 qcom,client-id = <1>; 641 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 642 }; 643 644 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 645 reg = <0 0xd4d00000 0 0x3300000>; 646 no-map; 647 }; 648 649 tz_reserved_mem: tz-reserved-region@d8000000 { 650 reg = <0 0xd8000000 0 0x100000>; 651 no-map; 652 }; 653 654 cpucp_fw_mem: cpucp-fw-region@d8140000 { 655 reg = <0 0xd8140000 0 0x1c0000>; 656 no-map; 657 }; 658 659 qtee_mem: qtee-region@d8300000 { 660 reg = <0 0xd8300000 0 0x500000>; 661 no-map; 662 }; 663 664 ta_mem: ta-region@d8800000 { 665 reg = <0 0xd8800000 0 0x8a00000>; 666 no-map; 667 }; 668 669 tz_tags_mem: tz-tags-region@e1200000 { 670 reg = <0 0xe1200000 0 0x2740000>; 671 no-map; 672 }; 673 674 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 675 reg = <0 0xe6440000 0 0x279000>; 676 no-map; 677 }; 678 679 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 680 reg = <0 0xf3600000 0 0x4aee000>; 681 no-map; 682 }; 683 684 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 685 reg = <0 0xf80ee000 0 0x1000>; 686 no-map; 687 }; 688 689 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 690 reg = <0 0xf80ef000 0 0x9000>; 691 no-map; 692 }; 693 694 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 695 reg = <0 0xf80f8000 0 0x4000>; 696 no-map; 697 }; 698 699 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 700 reg = <0 0xf80fc000 0 0x4000>; 701 no-map; 702 }; 703 704 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 705 reg = <0 0xf8100000 0 0x100000>; 706 no-map; 707 }; 708 709 oem_vm_mem: oem-vm-region@f8400000 { 710 reg = <0 0xf8400000 0 0x4800000>; 711 no-map; 712 }; 713 714 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 715 reg = <0 0xfcc00000 0 0x4000>; 716 no-map; 717 }; 718 719 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 720 reg = <0 0xfcc04000 0 0x100000>; 721 no-map; 722 }; 723 724 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 725 reg = <0 0xfce00000 0 0x2900000>; 726 no-map; 727 }; 728 729 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 730 reg = <0 0xff700000 0 0x100000>; 731 no-map; 732 }; 733 }; 734 735 smp2p-adsp { 736 compatible = "qcom,smp2p"; 737 qcom,smem = <443>, <429>; 738 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 739 IPCC_MPROC_SIGNAL_SMP2P 740 IRQ_TYPE_EDGE_RISING>; 741 mboxes = <&ipcc IPCC_CLIENT_LPASS 742 IPCC_MPROC_SIGNAL_SMP2P>; 743 744 qcom,local-pid = <0>; 745 qcom,remote-pid = <2>; 746 747 smp2p_adsp_out: master-kernel { 748 qcom,entry-name = "master-kernel"; 749 #qcom,smem-state-cells = <1>; 750 }; 751 752 smp2p_adsp_in: slave-kernel { 753 qcom,entry-name = "slave-kernel"; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 }; 757 }; 758 759 smp2p-cdsp { 760 compatible = "qcom,smp2p"; 761 qcom,smem = <94>, <432>; 762 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 763 IPCC_MPROC_SIGNAL_SMP2P 764 IRQ_TYPE_EDGE_RISING>; 765 mboxes = <&ipcc IPCC_CLIENT_CDSP 766 IPCC_MPROC_SIGNAL_SMP2P>; 767 768 qcom,local-pid = <0>; 769 qcom,remote-pid = <5>; 770 771 smp2p_cdsp_out: master-kernel { 772 qcom,entry-name = "master-kernel"; 773 #qcom,smem-state-cells = <1>; 774 }; 775 776 smp2p_cdsp_in: slave-kernel { 777 qcom,entry-name = "slave-kernel"; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 }; 782 783 smp2p-modem { 784 compatible = "qcom,smp2p"; 785 qcom,smem = <435>, <428>; 786 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 787 IPCC_MPROC_SIGNAL_SMP2P 788 IRQ_TYPE_EDGE_RISING>; 789 mboxes = <&ipcc IPCC_CLIENT_MPSS 790 IPCC_MPROC_SIGNAL_SMP2P>; 791 792 qcom,local-pid = <0>; 793 qcom,remote-pid = <1>; 794 795 smp2p_modem_out: master-kernel { 796 qcom,entry-name = "master-kernel"; 797 #qcom,smem-state-cells = <1>; 798 }; 799 800 smp2p_modem_in: slave-kernel { 801 qcom,entry-name = "slave-kernel"; 802 interrupt-controller; 803 #interrupt-cells = <2>; 804 }; 805 806 ipa_smp2p_out: ipa-ap-to-modem { 807 qcom,entry-name = "ipa"; 808 #qcom,smem-state-cells = <1>; 809 }; 810 811 ipa_smp2p_in: ipa-modem-to-ap { 812 qcom,entry-name = "ipa"; 813 interrupt-controller; 814 #interrupt-cells = <2>; 815 }; 816 }; 817 818 soc: soc@0 { 819 compatible = "simple-bus"; 820 ranges = <0 0 0 0 0x10 0>; 821 dma-ranges = <0 0 0 0 0x10 0>; 822 823 #address-cells = <2>; 824 #size-cells = <2>; 825 826 gcc: clock-controller@100000 { 827 compatible = "qcom,sm8550-gcc"; 828 reg = <0 0x00100000 0 0x1f4200>; 829 #clock-cells = <1>; 830 #reset-cells = <1>; 831 #power-domain-cells = <1>; 832 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 833 <&pcie0_phy>, 834 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 835 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 836 <&ufs_mem_phy 0>, 837 <&ufs_mem_phy 1>, 838 <&ufs_mem_phy 2>, 839 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 840 }; 841 842 ipcc: mailbox@408000 { 843 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 844 reg = <0 0x00408000 0 0x1000>; 845 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>; 846 interrupt-controller; 847 #interrupt-cells = <3>; 848 #mbox-cells = <2>; 849 }; 850 851 gpi_dma2: dma-controller@800000 { 852 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 853 #dma-cells = <3>; 854 reg = <0 0x00800000 0 0x60000>; 855 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>, 856 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>, 857 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, 858 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, 859 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, 860 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, 861 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, 862 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, 863 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, 864 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>, 865 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>, 866 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>; 867 dma-channels = <12>; 868 dma-channel-mask = <0x3e>; 869 iommus = <&apps_smmu 0x436 0>; 870 dma-coherent; 871 status = "disabled"; 872 }; 873 874 qupv3_id_1: geniqup@8c0000 { 875 compatible = "qcom,geni-se-qup"; 876 reg = <0 0x008c0000 0 0x2000>; 877 ranges; 878 clock-names = "m-ahb", "s-ahb"; 879 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 880 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 881 iommus = <&apps_smmu 0x423 0>; 882 dma-coherent; 883 #address-cells = <2>; 884 #size-cells = <2>; 885 status = "disabled"; 886 887 i2c8: i2c@880000 { 888 compatible = "qcom,geni-i2c"; 889 reg = <0 0x00880000 0 0x4000>; 890 clock-names = "se"; 891 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 892 pinctrl-names = "default"; 893 pinctrl-0 = <&qup_i2c8_data_clk>; 894 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 898 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 899 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 900 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 901 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 902 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 903 interconnect-names = "qup-core", "qup-config", "qup-memory"; 904 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 905 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 906 dma-names = "tx", "rx"; 907 power-domains = <&rpmhpd RPMHPD_CX>; 908 operating-points-v2 = <&qup_opp_table_120mhz>; 909 status = "disabled"; 910 }; 911 912 spi8: spi@880000 { 913 compatible = "qcom,geni-spi"; 914 reg = <0 0x00880000 0 0x4000>; 915 clock-names = "se"; 916 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 917 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 918 pinctrl-names = "default"; 919 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 920 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 921 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 922 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 923 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 924 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 925 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 926 interconnect-names = "qup-core", "qup-config", "qup-memory"; 927 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 928 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 929 dma-names = "tx", "rx"; 930 power-domains = <&rpmhpd RPMHPD_CX>; 931 operating-points-v2 = <&qup_opp_table_120mhz>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 status = "disabled"; 935 }; 936 937 i2c9: i2c@884000 { 938 compatible = "qcom,geni-i2c"; 939 reg = <0 0x00884000 0 0x4000>; 940 clock-names = "se"; 941 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 942 pinctrl-names = "default"; 943 pinctrl-0 = <&qup_i2c9_data_clk>; 944 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 948 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 949 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 950 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 951 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 952 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 953 interconnect-names = "qup-core", "qup-config", "qup-memory"; 954 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 955 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 956 dma-names = "tx", "rx"; 957 power-domains = <&rpmhpd RPMHPD_CX>; 958 operating-points-v2 = <&qup_opp_table_120mhz>; 959 status = "disabled"; 960 }; 961 962 spi9: spi@884000 { 963 compatible = "qcom,geni-spi"; 964 reg = <0 0x00884000 0 0x4000>; 965 clock-names = "se"; 966 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 967 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 970 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 971 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 972 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 973 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 974 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 975 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 976 interconnect-names = "qup-core", "qup-config", "qup-memory"; 977 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 978 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 979 dma-names = "tx", "rx"; 980 power-domains = <&rpmhpd RPMHPD_CX>; 981 operating-points-v2 = <&qup_opp_table_120mhz>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 i2c10: i2c@888000 { 988 compatible = "qcom,geni-i2c"; 989 reg = <0 0x00888000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&qup_i2c10_data_clk>; 994 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 998 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 999 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1000 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1001 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1002 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1003 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1004 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1005 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1006 dma-names = "tx", "rx"; 1007 power-domains = <&rpmhpd RPMHPD_CX>; 1008 operating-points-v2 = <&qup_opp_table_120mhz>; 1009 status = "disabled"; 1010 }; 1011 1012 spi10: spi@888000 { 1013 compatible = "qcom,geni-spi"; 1014 reg = <0 0x00888000 0 0x4000>; 1015 clock-names = "se"; 1016 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1017 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1020 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1021 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1022 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1023 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1024 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1025 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1026 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1027 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1028 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1029 dma-names = "tx", "rx"; 1030 power-domains = <&rpmhpd RPMHPD_CX>; 1031 operating-points-v2 = <&qup_opp_table_120mhz>; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 i2c11: i2c@88c000 { 1038 compatible = "qcom,geni-i2c"; 1039 reg = <0 0x0088c000 0 0x4000>; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1042 pinctrl-names = "default"; 1043 pinctrl-0 = <&qup_i2c11_data_clk>; 1044 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1048 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1049 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1050 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1051 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1052 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1053 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1054 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1055 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1056 dma-names = "tx", "rx"; 1057 power-domains = <&rpmhpd RPMHPD_CX>; 1058 operating-points-v2 = <&qup_opp_table_120mhz>; 1059 status = "disabled"; 1060 }; 1061 1062 spi11: spi@88c000 { 1063 compatible = "qcom,geni-spi"; 1064 reg = <0 0x0088c000 0 0x4000>; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1067 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1070 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1071 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1072 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1073 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1074 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1075 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1076 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1077 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1078 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1079 dma-names = "tx", "rx"; 1080 power-domains = <&rpmhpd RPMHPD_CX>; 1081 operating-points-v2 = <&qup_opp_table_120mhz>; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 status = "disabled"; 1085 }; 1086 1087 i2c12: i2c@890000 { 1088 compatible = "qcom,geni-i2c"; 1089 reg = <0 0x00890000 0 0x4000>; 1090 clock-names = "se"; 1091 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1092 pinctrl-names = "default"; 1093 pinctrl-0 = <&qup_i2c12_data_clk>; 1094 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1098 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1099 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1100 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1101 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1102 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1103 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1104 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1105 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1106 dma-names = "tx", "rx"; 1107 power-domains = <&rpmhpd RPMHPD_CX>; 1108 operating-points-v2 = <&qup_opp_table_120mhz>; 1109 status = "disabled"; 1110 }; 1111 1112 spi12: spi@890000 { 1113 compatible = "qcom,geni-spi"; 1114 reg = <0 0x00890000 0 0x4000>; 1115 clock-names = "se"; 1116 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1117 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1120 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1121 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1122 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1123 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1124 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1125 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1126 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1127 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1128 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1129 dma-names = "tx", "rx"; 1130 power-domains = <&rpmhpd RPMHPD_CX>; 1131 operating-points-v2 = <&qup_opp_table_120mhz>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 status = "disabled"; 1135 }; 1136 1137 i2c13: i2c@894000 { 1138 compatible = "qcom,geni-i2c"; 1139 reg = <0 0x00894000 0 0x4000>; 1140 clock-names = "se"; 1141 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1142 pinctrl-names = "default"; 1143 pinctrl-0 = <&qup_i2c13_data_clk>; 1144 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1148 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1149 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1150 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1151 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1152 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1153 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1154 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1155 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1156 dma-names = "tx", "rx"; 1157 power-domains = <&rpmhpd RPMHPD_CX>; 1158 operating-points-v2 = <&qup_opp_table_120mhz>; 1159 status = "disabled"; 1160 }; 1161 1162 spi13: spi@894000 { 1163 compatible = "qcom,geni-spi"; 1164 reg = <0 0x00894000 0 0x4000>; 1165 clock-names = "se"; 1166 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1167 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH 0>; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1171 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1172 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1173 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1174 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1176 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1177 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1178 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1179 dma-names = "tx", "rx"; 1180 power-domains = <&rpmhpd RPMHPD_CX>; 1181 operating-points-v2 = <&qup_opp_table_120mhz>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 status = "disabled"; 1185 }; 1186 1187 uart14: serial@898000 { 1188 compatible = "qcom,geni-uart"; 1189 reg = <0 0x898000 0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1194 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH 0>; 1195 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1196 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1197 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1198 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1199 interconnect-names = "qup-core", "qup-config"; 1200 power-domains = <&rpmhpd RPMHPD_CX>; 1201 operating-points-v2 = <&qup_opp_table_125mhz>; 1202 status = "disabled"; 1203 }; 1204 1205 i2c15: i2c@89c000 { 1206 compatible = "qcom,geni-i2c"; 1207 reg = <0 0x0089c000 0 0x4000>; 1208 clock-names = "se"; 1209 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1210 pinctrl-names = "default"; 1211 pinctrl-0 = <&qup_i2c15_data_clk>; 1212 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1216 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1217 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1218 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1219 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1220 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1221 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1222 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1223 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1224 dma-names = "tx", "rx"; 1225 power-domains = <&rpmhpd RPMHPD_CX>; 1226 operating-points-v2 = <&qup_opp_table_100mhz>; 1227 status = "disabled"; 1228 }; 1229 1230 spi15: spi@89c000 { 1231 compatible = "qcom,geni-spi"; 1232 reg = <0 0x0089c000 0 0x4000>; 1233 clock-names = "se"; 1234 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1235 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 1236 pinctrl-names = "default"; 1237 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1238 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1239 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1240 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1241 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 1242 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1243 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1244 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1245 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1246 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1247 dma-names = "tx", "rx"; 1248 power-domains = <&rpmhpd RPMHPD_CX>; 1249 operating-points-v2 = <&qup_opp_table_100mhz>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 status = "disabled"; 1253 }; 1254 }; 1255 1256 i2c_master_hub_0: geniqup@9c0000 { 1257 compatible = "qcom,geni-se-i2c-master-hub"; 1258 reg = <0x0 0x009c0000 0x0 0x2000>; 1259 clock-names = "s-ahb"; 1260 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1261 #address-cells = <2>; 1262 #size-cells = <2>; 1263 ranges; 1264 status = "disabled"; 1265 1266 i2c_hub_0: i2c@980000 { 1267 compatible = "qcom,geni-i2c-master-hub"; 1268 reg = <0x0 0x00980000 0x0 0x4000>; 1269 clock-names = "se", "core"; 1270 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1271 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&hub_i2c0_data_clk>; 1274 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1278 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1279 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1280 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1281 interconnect-names = "qup-core", "qup-config"; 1282 power-domains = <&rpmhpd RPMHPD_CX>; 1283 required-opps = <&rpmhpd_opp_low_svs>; 1284 status = "disabled"; 1285 }; 1286 1287 i2c_hub_1: i2c@984000 { 1288 compatible = "qcom,geni-i2c-master-hub"; 1289 reg = <0x0 0x00984000 0x0 0x4000>; 1290 clock-names = "se", "core"; 1291 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1292 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&hub_i2c1_data_clk>; 1295 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH 0>; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1299 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1300 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1301 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1302 interconnect-names = "qup-core", "qup-config"; 1303 power-domains = <&rpmhpd RPMHPD_CX>; 1304 required-opps = <&rpmhpd_opp_low_svs>; 1305 status = "disabled"; 1306 }; 1307 1308 i2c_hub_2: i2c@988000 { 1309 compatible = "qcom,geni-i2c-master-hub"; 1310 reg = <0x0 0x00988000 0x0 0x4000>; 1311 clock-names = "se", "core"; 1312 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1313 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1314 pinctrl-names = "default"; 1315 pinctrl-0 = <&hub_i2c2_data_clk>; 1316 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH 0>; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1320 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1321 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1322 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1323 interconnect-names = "qup-core", "qup-config"; 1324 power-domains = <&rpmhpd RPMHPD_CX>; 1325 required-opps = <&rpmhpd_opp_low_svs>; 1326 status = "disabled"; 1327 }; 1328 1329 i2c_hub_3: i2c@98c000 { 1330 compatible = "qcom,geni-i2c-master-hub"; 1331 reg = <0x0 0x0098c000 0x0 0x4000>; 1332 clock-names = "se", "core"; 1333 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1334 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1335 pinctrl-names = "default"; 1336 pinctrl-0 = <&hub_i2c3_data_clk>; 1337 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1341 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1342 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1343 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1344 interconnect-names = "qup-core", "qup-config"; 1345 power-domains = <&rpmhpd RPMHPD_CX>; 1346 required-opps = <&rpmhpd_opp_low_svs>; 1347 status = "disabled"; 1348 }; 1349 1350 i2c_hub_4: i2c@990000 { 1351 compatible = "qcom,geni-i2c-master-hub"; 1352 reg = <0x0 0x00990000 0x0 0x4000>; 1353 clock-names = "se", "core"; 1354 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1355 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1356 pinctrl-names = "default"; 1357 pinctrl-0 = <&hub_i2c4_data_clk>; 1358 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1362 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1363 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1364 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1365 interconnect-names = "qup-core", "qup-config"; 1366 power-domains = <&rpmhpd RPMHPD_CX>; 1367 required-opps = <&rpmhpd_opp_low_svs>; 1368 status = "disabled"; 1369 }; 1370 1371 i2c_hub_5: i2c@994000 { 1372 compatible = "qcom,geni-i2c-master-hub"; 1373 reg = <0 0x00994000 0 0x4000>; 1374 clock-names = "se", "core"; 1375 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1376 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1377 pinctrl-names = "default"; 1378 pinctrl-0 = <&hub_i2c5_data_clk>; 1379 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH 0>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1383 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1384 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1385 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1386 interconnect-names = "qup-core", "qup-config"; 1387 power-domains = <&rpmhpd RPMHPD_CX>; 1388 required-opps = <&rpmhpd_opp_low_svs>; 1389 status = "disabled"; 1390 }; 1391 1392 i2c_hub_6: i2c@998000 { 1393 compatible = "qcom,geni-i2c-master-hub"; 1394 reg = <0 0x00998000 0 0x4000>; 1395 clock-names = "se", "core"; 1396 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1397 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1398 pinctrl-names = "default"; 1399 pinctrl-0 = <&hub_i2c6_data_clk>; 1400 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH 0>; 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1404 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1405 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1406 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1407 interconnect-names = "qup-core", "qup-config"; 1408 power-domains = <&rpmhpd RPMHPD_CX>; 1409 required-opps = <&rpmhpd_opp_low_svs>; 1410 status = "disabled"; 1411 }; 1412 1413 i2c_hub_7: i2c@99c000 { 1414 compatible = "qcom,geni-i2c-master-hub"; 1415 reg = <0 0x0099c000 0 0x4000>; 1416 clock-names = "se", "core"; 1417 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1418 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1419 pinctrl-names = "default"; 1420 pinctrl-0 = <&hub_i2c7_data_clk>; 1421 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1425 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1426 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1427 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1428 interconnect-names = "qup-core", "qup-config"; 1429 power-domains = <&rpmhpd RPMHPD_CX>; 1430 required-opps = <&rpmhpd_opp_low_svs>; 1431 status = "disabled"; 1432 }; 1433 1434 i2c_hub_8: i2c@9a0000 { 1435 compatible = "qcom,geni-i2c-master-hub"; 1436 reg = <0 0x009a0000 0 0x4000>; 1437 clock-names = "se", "core"; 1438 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1439 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&hub_i2c8_data_clk>; 1442 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH 0>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1446 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1447 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1448 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1449 interconnect-names = "qup-core", "qup-config"; 1450 power-domains = <&rpmhpd RPMHPD_CX>; 1451 required-opps = <&rpmhpd_opp_low_svs>; 1452 status = "disabled"; 1453 }; 1454 1455 i2c_hub_9: i2c@9a4000 { 1456 compatible = "qcom,geni-i2c-master-hub"; 1457 reg = <0 0x009a4000 0 0x4000>; 1458 clock-names = "se", "core"; 1459 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1460 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&hub_i2c9_data_clk>; 1463 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH 0>; 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1467 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1468 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1469 &config_noc SLAVE_I2C QCOM_ICC_TAG_ACTIVE_ONLY>; 1470 interconnect-names = "qup-core", "qup-config"; 1471 power-domains = <&rpmhpd RPMHPD_CX>; 1472 required-opps = <&rpmhpd_opp_low_svs>; 1473 status = "disabled"; 1474 }; 1475 }; 1476 1477 gpi_dma1: dma-controller@a00000 { 1478 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1479 #dma-cells = <3>; 1480 reg = <0 0x00a00000 0 0x60000>; 1481 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>, 1482 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>, 1483 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>, 1484 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>, 1485 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>, 1486 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH 0>, 1487 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>, 1488 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>, 1489 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>, 1490 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>, 1491 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>, 1492 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 1493 dma-channels = <12>; 1494 dma-channel-mask = <0x1e>; 1495 iommus = <&apps_smmu 0xb6 0>; 1496 dma-coherent; 1497 status = "disabled"; 1498 }; 1499 1500 qupv3_id_0: geniqup@ac0000 { 1501 compatible = "qcom,geni-se-qup"; 1502 reg = <0 0x00ac0000 0 0x2000>; 1503 ranges; 1504 clock-names = "m-ahb", "s-ahb"; 1505 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1506 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1507 iommus = <&apps_smmu 0xa3 0>; 1508 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1509 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 1510 interconnect-names = "qup-core"; 1511 dma-coherent; 1512 #address-cells = <2>; 1513 #size-cells = <2>; 1514 status = "disabled"; 1515 1516 i2c0: i2c@a80000 { 1517 compatible = "qcom,geni-i2c"; 1518 reg = <0 0x00a80000 0 0x4000>; 1519 clock-names = "se"; 1520 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1521 pinctrl-names = "default"; 1522 pinctrl-0 = <&qup_i2c0_data_clk>; 1523 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1524 #address-cells = <1>; 1525 #size-cells = <0>; 1526 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1527 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1528 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1529 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1530 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1531 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1532 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1533 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1534 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1535 dma-names = "tx", "rx"; 1536 power-domains = <&rpmhpd RPMHPD_CX>; 1537 operating-points-v2 = <&qup_opp_table_120mhz>; 1538 status = "disabled"; 1539 }; 1540 1541 spi0: spi@a80000 { 1542 compatible = "qcom,geni-spi"; 1543 reg = <0 0x00a80000 0 0x4000>; 1544 clock-names = "se"; 1545 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1546 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; 1547 pinctrl-names = "default"; 1548 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1549 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1550 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1551 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1552 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1553 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1554 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1555 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1556 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1557 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1558 dma-names = "tx", "rx"; 1559 power-domains = <&rpmhpd RPMHPD_CX>; 1560 operating-points-v2 = <&qup_opp_table_120mhz>; 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 status = "disabled"; 1564 }; 1565 1566 i2c1: i2c@a84000 { 1567 compatible = "qcom,geni-i2c"; 1568 reg = <0 0x00a84000 0 0x4000>; 1569 clock-names = "se"; 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1571 pinctrl-names = "default"; 1572 pinctrl-0 = <&qup_i2c1_data_clk>; 1573 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 1574 #address-cells = <1>; 1575 #size-cells = <0>; 1576 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1577 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1578 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1579 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1580 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1581 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1582 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1583 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1584 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1585 dma-names = "tx", "rx"; 1586 power-domains = <&rpmhpd RPMHPD_CX>; 1587 operating-points-v2 = <&qup_opp_table_120mhz>; 1588 status = "disabled"; 1589 }; 1590 1591 spi1: spi@a84000 { 1592 compatible = "qcom,geni-spi"; 1593 reg = <0 0x00a84000 0 0x4000>; 1594 clock-names = "se"; 1595 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1596 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 1597 pinctrl-names = "default"; 1598 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1599 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1600 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1601 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1602 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1603 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1604 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1605 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1606 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1607 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1608 dma-names = "tx", "rx"; 1609 power-domains = <&rpmhpd RPMHPD_CX>; 1610 operating-points-v2 = <&qup_opp_table_120mhz>; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 status = "disabled"; 1614 }; 1615 1616 i2c2: i2c@a88000 { 1617 compatible = "qcom,geni-i2c"; 1618 reg = <0 0x00a88000 0 0x4000>; 1619 clock-names = "se"; 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1621 pinctrl-names = "default"; 1622 pinctrl-0 = <&qup_i2c2_data_clk>; 1623 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1624 #address-cells = <1>; 1625 #size-cells = <0>; 1626 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1627 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1628 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1629 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1630 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1631 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1632 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1633 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1634 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1635 dma-names = "tx", "rx"; 1636 power-domains = <&rpmhpd RPMHPD_CX>; 1637 operating-points-v2 = <&qup_opp_table_100mhz>; 1638 status = "disabled"; 1639 }; 1640 1641 spi2: spi@a88000 { 1642 compatible = "qcom,geni-spi"; 1643 reg = <0 0x00a88000 0 0x4000>; 1644 clock-names = "se"; 1645 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1646 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1647 pinctrl-names = "default"; 1648 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1649 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1650 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1651 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1652 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1653 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1654 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1655 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1656 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1657 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1658 dma-names = "tx", "rx"; 1659 power-domains = <&rpmhpd RPMHPD_CX>; 1660 operating-points-v2 = <&qup_opp_table_100mhz>; 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 status = "disabled"; 1664 }; 1665 1666 i2c3: i2c@a8c000 { 1667 compatible = "qcom,geni-i2c"; 1668 reg = <0 0x00a8c000 0 0x4000>; 1669 clock-names = "se"; 1670 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1671 pinctrl-names = "default"; 1672 pinctrl-0 = <&qup_i2c3_data_clk>; 1673 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1677 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1678 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1679 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1680 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1681 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1682 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1683 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1684 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1685 dma-names = "tx", "rx"; 1686 power-domains = <&rpmhpd RPMHPD_CX>; 1687 operating-points-v2 = <&qup_opp_table_100mhz>; 1688 status = "disabled"; 1689 }; 1690 1691 spi3: spi@a8c000 { 1692 compatible = "qcom,geni-spi"; 1693 reg = <0 0x00a8c000 0 0x4000>; 1694 clock-names = "se"; 1695 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1696 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1697 pinctrl-names = "default"; 1698 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1699 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1700 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1701 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1702 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1703 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1704 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1705 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1706 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1707 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1708 dma-names = "tx", "rx"; 1709 power-domains = <&rpmhpd RPMHPD_CX>; 1710 operating-points-v2 = <&qup_opp_table_100mhz>; 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 status = "disabled"; 1714 }; 1715 1716 i2c4: i2c@a90000 { 1717 compatible = "qcom,geni-i2c"; 1718 reg = <0 0x00a90000 0 0x4000>; 1719 clock-names = "se"; 1720 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1721 pinctrl-names = "default"; 1722 pinctrl-0 = <&qup_i2c4_data_clk>; 1723 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; 1724 #address-cells = <1>; 1725 #size-cells = <0>; 1726 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1727 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1728 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1729 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1730 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1731 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1732 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1733 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1734 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1735 dma-names = "tx", "rx"; 1736 power-domains = <&rpmhpd RPMHPD_CX>; 1737 operating-points-v2 = <&qup_opp_table_100mhz>; 1738 status = "disabled"; 1739 }; 1740 1741 spi4: spi@a90000 { 1742 compatible = "qcom,geni-spi"; 1743 reg = <0 0x00a90000 0 0x4000>; 1744 clock-names = "se"; 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1746 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH 0>; 1747 pinctrl-names = "default"; 1748 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1749 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1750 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1751 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1752 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1753 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1754 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1755 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1756 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1757 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1758 dma-names = "tx", "rx"; 1759 power-domains = <&rpmhpd RPMHPD_CX>; 1760 operating-points-v2 = <&qup_opp_table_100mhz>; 1761 #address-cells = <1>; 1762 #size-cells = <0>; 1763 status = "disabled"; 1764 }; 1765 1766 i2c5: i2c@a94000 { 1767 compatible = "qcom,geni-i2c"; 1768 reg = <0 0x00a94000 0 0x4000>; 1769 clock-names = "se"; 1770 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1771 pinctrl-names = "default"; 1772 pinctrl-0 = <&qup_i2c5_data_clk>; 1773 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; 1774 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1775 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1776 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1777 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1778 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1779 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1780 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1781 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1782 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1783 dma-names = "tx", "rx"; 1784 power-domains = <&rpmhpd RPMHPD_CX>; 1785 operating-points-v2 = <&qup_opp_table_100mhz>; 1786 #address-cells = <1>; 1787 #size-cells = <0>; 1788 status = "disabled"; 1789 }; 1790 1791 spi5: spi@a94000 { 1792 compatible = "qcom,geni-spi"; 1793 reg = <0 0x00a94000 0 0x4000>; 1794 clock-names = "se"; 1795 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1796 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>; 1797 pinctrl-names = "default"; 1798 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1799 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1800 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1801 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1802 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1803 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1804 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1805 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1806 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1807 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1808 dma-names = "tx", "rx"; 1809 power-domains = <&rpmhpd RPMHPD_CX>; 1810 operating-points-v2 = <&qup_opp_table_100mhz>; 1811 #address-cells = <1>; 1812 #size-cells = <0>; 1813 status = "disabled"; 1814 }; 1815 1816 i2c6: i2c@a98000 { 1817 compatible = "qcom,geni-i2c"; 1818 reg = <0 0x00a98000 0 0x4000>; 1819 clock-names = "se"; 1820 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1821 pinctrl-names = "default"; 1822 pinctrl-0 = <&qup_i2c6_data_clk>; 1823 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 1824 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1825 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1826 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1827 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1828 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1829 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1830 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1831 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1832 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1833 dma-names = "tx", "rx"; 1834 power-domains = <&rpmhpd RPMHPD_CX>; 1835 operating-points-v2 = <&qup_opp_table_100mhz>; 1836 #address-cells = <1>; 1837 #size-cells = <0>; 1838 status = "disabled"; 1839 }; 1840 1841 spi6: spi@a98000 { 1842 compatible = "qcom,geni-spi"; 1843 reg = <0 0x00a98000 0 0x4000>; 1844 clock-names = "se"; 1845 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1846 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 1847 pinctrl-names = "default"; 1848 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1849 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1850 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1851 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1852 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1853 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1854 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1855 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1856 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1857 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1858 dma-names = "tx", "rx"; 1859 power-domains = <&rpmhpd RPMHPD_CX>; 1860 operating-points-v2 = <&qup_opp_table_100mhz>; 1861 #address-cells = <1>; 1862 #size-cells = <0>; 1863 status = "disabled"; 1864 }; 1865 1866 uart7: serial@a9c000 { 1867 compatible = "qcom,geni-debug-uart"; 1868 reg = <0 0x00a9c000 0 0x4000>; 1869 clock-names = "se"; 1870 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1871 pinctrl-names = "default"; 1872 pinctrl-0 = <&qup_uart7_default>; 1873 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>; 1874 interconnect-names = "qup-core", "qup-config"; 1875 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1876 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1877 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1878 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1879 power-domains = <&rpmhpd RPMHPD_CX>; 1880 operating-points-v2 = <&qup_opp_table_100mhz>; 1881 status = "disabled"; 1882 }; 1883 }; 1884 1885 cnoc_main: interconnect@1500000 { 1886 compatible = "qcom,sm8550-cnoc-main"; 1887 reg = <0 0x01500000 0 0x13080>; 1888 #interconnect-cells = <2>; 1889 qcom,bcm-voters = <&apps_bcm_voter>; 1890 }; 1891 1892 config_noc: interconnect@1600000 { 1893 compatible = "qcom,sm8550-config-noc"; 1894 reg = <0 0x01600000 0 0x6200>; 1895 #interconnect-cells = <2>; 1896 qcom,bcm-voters = <&apps_bcm_voter>; 1897 }; 1898 1899 system_noc: interconnect@1680000 { 1900 compatible = "qcom,sm8550-system-noc"; 1901 reg = <0 0x01680000 0 0x1d080>; 1902 #interconnect-cells = <2>; 1903 qcom,bcm-voters = <&apps_bcm_voter>; 1904 }; 1905 1906 pcie_noc: interconnect@16c0000 { 1907 compatible = "qcom,sm8550-pcie-anoc"; 1908 reg = <0 0x016c0000 0 0x12200>; 1909 #interconnect-cells = <2>; 1910 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1911 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1912 qcom,bcm-voters = <&apps_bcm_voter>; 1913 }; 1914 1915 aggre1_noc: interconnect@16e0000 { 1916 compatible = "qcom,sm8550-aggre1-noc"; 1917 reg = <0 0x016e0000 0 0x14400>; 1918 #interconnect-cells = <2>; 1919 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1920 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1921 qcom,bcm-voters = <&apps_bcm_voter>; 1922 }; 1923 1924 aggre2_noc: interconnect@1700000 { 1925 compatible = "qcom,sm8550-aggre2-noc"; 1926 reg = <0 0x01700000 0 0x1e400>; 1927 #interconnect-cells = <2>; 1928 clocks = <&rpmhcc RPMH_IPA_CLK>; 1929 qcom,bcm-voters = <&apps_bcm_voter>; 1930 }; 1931 1932 mmss_noc: interconnect@1780000 { 1933 compatible = "qcom,sm8550-mmss-noc"; 1934 reg = <0 0x01780000 0 0x5b800>; 1935 #interconnect-cells = <2>; 1936 qcom,bcm-voters = <&apps_bcm_voter>; 1937 }; 1938 1939 rng: rng@10c3000 { 1940 compatible = "qcom,sm8550-trng", "qcom,trng"; 1941 reg = <0 0x010c3000 0 0x1000>; 1942 }; 1943 1944 pcie0: pcie@1c00000 { 1945 device_type = "pci"; 1946 compatible = "qcom,pcie-sm8550"; 1947 reg = <0 0x01c00000 0 0x3000>, 1948 <0 0x60000000 0 0xf1d>, 1949 <0 0x60000f20 0 0xa8>, 1950 <0 0x60001000 0 0x1000>, 1951 <0 0x60100000 0 0x100000>; 1952 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1953 #address-cells = <3>; 1954 #size-cells = <2>; 1955 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1956 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1957 bus-range = <0x00 0xff>; 1958 1959 dma-coherent; 1960 1961 linux,pci-domain = <0>; 1962 num-lanes = <2>; 1963 1964 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>, 1965 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>, 1966 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>, 1967 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>, 1968 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>, 1969 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>, 1970 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>, 1971 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>, 1972 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH 0>; 1973 interrupt-names = "msi0", 1974 "msi1", 1975 "msi2", 1976 "msi3", 1977 "msi4", 1978 "msi5", 1979 "msi6", 1980 "msi7", 1981 "global"; 1982 #interrupt-cells = <1>; 1983 interrupt-map-mask = <0 0 0 0x7>; 1984 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */ 1985 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ 1986 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ 1987 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ 1988 1989 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1990 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1991 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1992 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1993 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1994 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1995 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1996 clock-names = "aux", 1997 "cfg", 1998 "bus_master", 1999 "bus_slave", 2000 "slave_q2a", 2001 "ddrss_sf_tbu", 2002 "noc_aggr"; 2003 2004 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2005 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2006 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2007 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2008 interconnect-names = "pcie-mem", "cpu-pcie"; 2009 2010 msi-map = <0x0 &gic_its 0x1400 0x1>, 2011 <0x100 &gic_its 0x1401 0x1>; 2012 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 2013 <0x100 &apps_smmu 0x1401 0x1>; 2014 2015 resets = <&gcc GCC_PCIE_0_BCR>; 2016 reset-names = "pci"; 2017 2018 power-domains = <&gcc PCIE_0_GDSC>; 2019 2020 phys = <&pcie0_phy>; 2021 phy-names = "pciephy"; 2022 2023 operating-points-v2 = <&pcie0_opp_table>; 2024 2025 status = "disabled"; 2026 2027 pcie0_opp_table: opp-table { 2028 compatible = "operating-points-v2"; 2029 2030 /* 2.5 GT/s x1 */ 2031 opp-2500000-1 { 2032 opp-hz = /bits/ 64 <2500000>; 2033 required-opps = <&rpmhpd_opp_low_svs>; 2034 opp-peak-kBps = <250000 1>; 2035 opp-level = <1>; 2036 }; 2037 2038 /* 2.5 GT/s x2 */ 2039 opp-5000000-1 { 2040 opp-hz = /bits/ 64 <5000000>; 2041 required-opps = <&rpmhpd_opp_low_svs>; 2042 opp-peak-kBps = <500000 1>; 2043 opp-level = <1>; 2044 }; 2045 2046 /* 5 GT/s x1 */ 2047 opp-5000000-2 { 2048 opp-hz = /bits/ 64 <5000000>; 2049 required-opps = <&rpmhpd_opp_low_svs>; 2050 opp-peak-kBps = <500000 1>; 2051 opp-level = <2>; 2052 }; 2053 2054 /* 5 GT/s x2 */ 2055 opp-10000000-2 { 2056 opp-hz = /bits/ 64 <10000000>; 2057 required-opps = <&rpmhpd_opp_low_svs>; 2058 opp-peak-kBps = <1000000 1>; 2059 opp-level = <2>; 2060 }; 2061 2062 /* 8 GT/s x1 */ 2063 opp-8000000-3 { 2064 opp-hz = /bits/ 64 <8000000>; 2065 required-opps = <&rpmhpd_opp_nom>; 2066 opp-peak-kBps = <984500 1>; 2067 opp-level = <3>; 2068 }; 2069 2070 /* 8 GT/s x2 */ 2071 opp-16000000-3 { 2072 opp-hz = /bits/ 64 <16000000>; 2073 required-opps = <&rpmhpd_opp_nom>; 2074 opp-peak-kBps = <1969000 1>; 2075 opp-level = <3>; 2076 }; 2077 }; 2078 2079 pcieport0: pcie@0 { 2080 device_type = "pci"; 2081 reg = <0x0 0x0 0x0 0x0 0x0>; 2082 bus-range = <0x01 0xff>; 2083 2084 #address-cells = <3>; 2085 #size-cells = <2>; 2086 ranges; 2087 }; 2088 }; 2089 2090 pcie0_phy: phy@1c06000 { 2091 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 2092 reg = <0 0x01c06000 0 0x2000>; 2093 2094 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2095 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2096 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 2097 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2098 <&gcc GCC_PCIE_0_PIPE_CLK>; 2099 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2100 "pipe"; 2101 2102 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2103 reset-names = "phy"; 2104 2105 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2106 assigned-clock-rates = <100000000>; 2107 2108 power-domains = <&gcc PCIE_0_PHY_GDSC>; 2109 2110 #clock-cells = <0>; 2111 clock-output-names = "pcie0_pipe_clk"; 2112 2113 #phy-cells = <0>; 2114 2115 status = "disabled"; 2116 }; 2117 2118 pcie1: pcie@1c08000 { 2119 device_type = "pci"; 2120 compatible = "qcom,pcie-sm8550"; 2121 reg = <0x0 0x01c08000 0x0 0x3000>, 2122 <0x0 0x40000000 0x0 0xf1d>, 2123 <0x0 0x40000f20 0x0 0xa8>, 2124 <0x0 0x40001000 0x0 0x1000>, 2125 <0x0 0x40100000 0x0 0x100000>; 2126 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2127 #address-cells = <3>; 2128 #size-cells = <2>; 2129 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2130 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2131 bus-range = <0x00 0xff>; 2132 2133 dma-coherent; 2134 2135 linux,pci-domain = <1>; 2136 num-lanes = <2>; 2137 2138 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>, 2139 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>, 2140 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>, 2141 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 0>, 2142 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>, 2143 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 0>, 2144 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, 2145 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH 0>, 2146 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 2147 interrupt-names = "msi0", 2148 "msi1", 2149 "msi2", 2150 "msi3", 2151 "msi4", 2152 "msi5", 2153 "msi6", 2154 "msi7", 2155 "global"; 2156 #interrupt-cells = <1>; 2157 interrupt-map-mask = <0 0 0 0x7>; 2158 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */ 2159 <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ 2160 <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ 2161 <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ 2162 2163 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2164 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2165 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2166 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2167 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2168 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2169 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2170 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2171 clock-names = "aux", 2172 "cfg", 2173 "bus_master", 2174 "bus_slave", 2175 "slave_q2a", 2176 "ddrss_sf_tbu", 2177 "noc_aggr", 2178 "cnoc_sf_axi"; 2179 2180 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2181 assigned-clock-rates = <19200000>; 2182 2183 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2184 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2185 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2186 &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2187 interconnect-names = "pcie-mem", "cpu-pcie"; 2188 2189 msi-map = <0x0 &gic_its 0x1480 0x1>, 2190 <0x100 &gic_its 0x1481 0x1>; 2191 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 2192 <0x100 &apps_smmu 0x1481 0x1>; 2193 2194 resets = <&gcc GCC_PCIE_1_BCR>, 2195 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2196 reset-names = "pci", "link_down"; 2197 2198 power-domains = <&gcc PCIE_1_GDSC>; 2199 2200 phys = <&pcie1_phy>; 2201 phy-names = "pciephy"; 2202 2203 operating-points-v2 = <&pcie1_opp_table>; 2204 2205 status = "disabled"; 2206 2207 pcie1_opp_table: opp-table { 2208 compatible = "operating-points-v2"; 2209 2210 /* 2.5 GT/s x1 */ 2211 opp-2500000-1 { 2212 opp-hz = /bits/ 64 <2500000>; 2213 required-opps = <&rpmhpd_opp_low_svs>; 2214 opp-peak-kBps = <250000 1>; 2215 opp-level = <1>; 2216 }; 2217 2218 /* 2.5 GT/s x2 */ 2219 opp-5000000-1 { 2220 opp-hz = /bits/ 64 <5000000>; 2221 required-opps = <&rpmhpd_opp_low_svs>; 2222 opp-peak-kBps = <500000 1>; 2223 opp-level = <1>; 2224 }; 2225 2226 /* 5 GT/s x1 */ 2227 opp-5000000-2 { 2228 opp-hz = /bits/ 64 <5000000>; 2229 required-opps = <&rpmhpd_opp_low_svs>; 2230 opp-peak-kBps = <500000 1>; 2231 opp-level = <2>; 2232 }; 2233 2234 /* 5 GT/s x2 */ 2235 opp-10000000-2 { 2236 opp-hz = /bits/ 64 <10000000>; 2237 required-opps = <&rpmhpd_opp_low_svs>; 2238 opp-peak-kBps = <1000000 1>; 2239 opp-level = <2>; 2240 }; 2241 2242 /* 8 GT/s x1 */ 2243 opp-8000000-3 { 2244 opp-hz = /bits/ 64 <8000000>; 2245 required-opps = <&rpmhpd_opp_nom>; 2246 opp-peak-kBps = <984500 1>; 2247 opp-level = <3>; 2248 }; 2249 2250 /* 8 GT/s x2 */ 2251 opp-16000000-3 { 2252 opp-hz = /bits/ 64 <16000000>; 2253 required-opps = <&rpmhpd_opp_nom>; 2254 opp-peak-kBps = <1969000 1>; 2255 opp-level = <3>; 2256 }; 2257 2258 /* 16 GT/s x1 */ 2259 opp-16000000-4 { 2260 opp-hz = /bits/ 64 <16000000>; 2261 required-opps = <&rpmhpd_opp_nom>; 2262 opp-peak-kBps = <1969000 1>; 2263 opp-level = <4>; 2264 }; 2265 2266 /* 16 GT/s x2 */ 2267 opp-32000000-4 { 2268 opp-hz = /bits/ 64 <32000000>; 2269 required-opps = <&rpmhpd_opp_nom>; 2270 opp-peak-kBps = <3938000 1>; 2271 opp-level = <4>; 2272 }; 2273 }; 2274 2275 pcie@0 { 2276 device_type = "pci"; 2277 reg = <0x0 0x0 0x0 0x0 0x0>; 2278 bus-range = <0x01 0xff>; 2279 2280 #address-cells = <3>; 2281 #size-cells = <2>; 2282 ranges; 2283 }; 2284 }; 2285 2286 pcie1_phy: phy@1c0e000 { 2287 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 2288 reg = <0x0 0x01c0e000 0x0 0x2000>; 2289 2290 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2291 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2292 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 2293 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2294 <&gcc GCC_PCIE_1_PIPE_CLK>; 2295 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2296 "pipe"; 2297 2298 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 2299 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 2300 reset-names = "phy", "phy_nocsr"; 2301 2302 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2303 assigned-clock-rates = <100000000>; 2304 2305 power-domains = <&gcc PCIE_1_PHY_GDSC>; 2306 2307 #clock-cells = <1>; 2308 clock-output-names = "pcie1_pipe_clk"; 2309 2310 #phy-cells = <0>; 2311 2312 status = "disabled"; 2313 }; 2314 2315 cryptobam: dma-controller@1dc4000 { 2316 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2317 reg = <0x0 0x01dc4000 0x0 0x28000>; 2318 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>; 2319 #dma-cells = <1>; 2320 qcom,ee = <0>; 2321 qcom,num-ees = <4>; 2322 num-channels = <20>; 2323 qcom,controlled-remotely; 2324 iommus = <&apps_smmu 0x480 0x0>, 2325 <&apps_smmu 0x481 0x0>; 2326 }; 2327 2328 crypto: crypto@1dfa000 { 2329 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 2330 reg = <0x0 0x01dfa000 0x0 0x6000>; 2331 dmas = <&cryptobam 4>, <&cryptobam 5>; 2332 dma-names = "rx", "tx"; 2333 iommus = <&apps_smmu 0x480 0x0>, 2334 <&apps_smmu 0x481 0x0>; 2335 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 2336 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2337 interconnect-names = "memory"; 2338 }; 2339 2340 ufs_mem_phy: phy@1d80000 { 2341 compatible = "qcom,sm8550-qmp-ufs-phy"; 2342 reg = <0x0 0x01d80000 0x0 0x2000>; 2343 clocks = <&rpmhcc RPMH_CXO_CLK>, 2344 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2345 <&tcsr TCSR_UFS_CLKREF_EN>; 2346 clock-names = "ref", 2347 "ref_aux", 2348 "qref"; 2349 2350 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 2351 2352 resets = <&ufs_mem_hc 0>; 2353 reset-names = "ufsphy"; 2354 2355 #clock-cells = <1>; 2356 #phy-cells = <0>; 2357 2358 status = "disabled"; 2359 }; 2360 2361 ufs_mem_hc: ufshc@1d84000 { 2362 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 2363 "jedec,ufs-2.0"; 2364 reg = <0x0 0x01d84000 0x0 0x3000>; 2365 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 2366 phys = <&ufs_mem_phy>; 2367 phy-names = "ufsphy"; 2368 lanes-per-direction = <2>; 2369 #reset-cells = <1>; 2370 resets = <&gcc GCC_UFS_PHY_BCR>; 2371 reset-names = "rst"; 2372 2373 power-domains = <&gcc UFS_PHY_GDSC>; 2374 required-opps = <&rpmhpd_opp_nom>; 2375 2376 iommus = <&apps_smmu 0x60 0x0>; 2377 dma-coherent; 2378 2379 operating-points-v2 = <&ufs_opp_table>; 2380 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2381 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2382 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2383 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2384 2385 interconnect-names = "ufs-ddr", "cpu-ufs"; 2386 clock-names = "core_clk", 2387 "bus_aggr_clk", 2388 "iface_clk", 2389 "core_clk_unipro", 2390 "ref_clk", 2391 "tx_lane0_sync_clk", 2392 "rx_lane0_sync_clk", 2393 "rx_lane1_sync_clk"; 2394 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2395 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2396 <&gcc GCC_UFS_PHY_AHB_CLK>, 2397 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2398 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 2399 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2400 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2401 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2402 qcom,ice = <&ice>; 2403 2404 status = "disabled"; 2405 2406 ufs_opp_table: opp-table { 2407 compatible = "operating-points-v2"; 2408 2409 opp-75000000 { 2410 opp-hz = /bits/ 64 <75000000>, 2411 /bits/ 64 <0>, 2412 /bits/ 64 <0>, 2413 /bits/ 64 <75000000>, 2414 /bits/ 64 <0>, 2415 /bits/ 64 <0>, 2416 /bits/ 64 <0>, 2417 /bits/ 64 <0>; 2418 required-opps = <&rpmhpd_opp_low_svs>; 2419 }; 2420 2421 opp-150000000 { 2422 opp-hz = /bits/ 64 <150000000>, 2423 /bits/ 64 <0>, 2424 /bits/ 64 <0>, 2425 /bits/ 64 <150000000>, 2426 /bits/ 64 <0>, 2427 /bits/ 64 <0>, 2428 /bits/ 64 <0>, 2429 /bits/ 64 <0>; 2430 required-opps = <&rpmhpd_opp_svs>; 2431 }; 2432 2433 opp-300000000 { 2434 opp-hz = /bits/ 64 <300000000>, 2435 /bits/ 64 <0>, 2436 /bits/ 64 <0>, 2437 /bits/ 64 <300000000>, 2438 /bits/ 64 <0>, 2439 /bits/ 64 <0>, 2440 /bits/ 64 <0>, 2441 /bits/ 64 <0>; 2442 required-opps = <&rpmhpd_opp_nom>; 2443 }; 2444 }; 2445 }; 2446 2447 ice: crypto@1d88000 { 2448 compatible = "qcom,sm8550-inline-crypto-engine", 2449 "qcom,inline-crypto-engine"; 2450 reg = <0 0x01d88000 0 0x18000>; 2451 2452 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2453 }; 2454 2455 tcsr_mutex: hwlock@1f40000 { 2456 compatible = "qcom,tcsr-mutex"; 2457 reg = <0 0x01f40000 0 0x20000>; 2458 #hwlock-cells = <1>; 2459 }; 2460 2461 tcsr: clock-controller@1fc0000 { 2462 compatible = "qcom,sm8550-tcsr", "syscon"; 2463 reg = <0 0x01fc0000 0 0x30000>; 2464 clocks = <&rpmhcc RPMH_CXO_CLK>; 2465 #clock-cells = <1>; 2466 #reset-cells = <1>; 2467 }; 2468 2469 gpu: gpu@3d00000 { 2470 compatible = "qcom,adreno-43050a01", "qcom,adreno"; 2471 reg = <0x0 0x03d00000 0x0 0x40000>, 2472 <0x0 0x03d9e000 0x0 0x1000>, 2473 <0x0 0x03d61000 0x0 0x800>; 2474 reg-names = "kgsl_3d0_reg_memory", 2475 "cx_mem", 2476 "cx_dbgc"; 2477 2478 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; 2479 2480 iommus = <&adreno_smmu 0 0x0>, 2481 <&adreno_smmu 1 0x0>; 2482 2483 operating-points-v2 = <&gpu_opp_table>; 2484 2485 qcom,gmu = <&gmu>; 2486 #cooling-cells = <2>; 2487 2488 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 2489 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2490 interconnect-names = "gfx-mem"; 2491 2492 status = "disabled"; 2493 2494 gpu_zap_shader: zap-shader { 2495 memory-region = <&gpu_micro_code_mem>; 2496 }; 2497 2498 /* Speedbin needs more work on A740+, keep only lower freqs */ 2499 gpu_opp_table: opp-table { 2500 compatible = "operating-points-v2"; 2501 2502 opp-680000000 { 2503 opp-hz = /bits/ 64 <680000000>; 2504 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2505 opp-peak-kBps = <16500000>; 2506 }; 2507 2508 opp-615000000 { 2509 opp-hz = /bits/ 64 <615000000>; 2510 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2511 opp-peak-kBps = <12449218>; 2512 }; 2513 2514 opp-550000000 { 2515 opp-hz = /bits/ 64 <550000000>; 2516 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2517 opp-peak-kBps = <10687500>; 2518 }; 2519 2520 opp-475000000 { 2521 opp-hz = /bits/ 64 <475000000>; 2522 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2523 opp-peak-kBps = <6074218>; 2524 }; 2525 2526 opp-401000000 { 2527 opp-hz = /bits/ 64 <401000000>; 2528 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2529 opp-peak-kBps = <6074218>; 2530 }; 2531 2532 opp-348000000 { 2533 opp-hz = /bits/ 64 <348000000>; 2534 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 2535 opp-peak-kBps = <6074218>; 2536 }; 2537 2538 opp-295000000 { 2539 opp-hz = /bits/ 64 <295000000>; 2540 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2541 opp-peak-kBps = <6074218>; 2542 }; 2543 2544 opp-220000000 { 2545 opp-hz = /bits/ 64 <220000000>; 2546 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 2547 opp-peak-kBps = <2136718>; 2548 }; 2549 }; 2550 }; 2551 2552 gmu: gmu@3d6a000 { 2553 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu"; 2554 reg = <0x0 0x03d6a000 0x0 0x35000>, 2555 <0x0 0x03d50000 0x0 0x10000>, 2556 <0x0 0x0b280000 0x0 0x10000>; 2557 reg-names = "gmu", "rscc", "gmu_pdc"; 2558 2559 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>, 2560 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 2561 interrupt-names = "hfi", "gmu"; 2562 2563 clocks = <&gpucc GPU_CC_AHB_CLK>, 2564 <&gpucc GPU_CC_CX_GMU_CLK>, 2565 <&gpucc GPU_CC_CXO_CLK>, 2566 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2567 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2568 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2569 <&gpucc GPU_CC_DEMET_CLK>; 2570 clock-names = "ahb", 2571 "gmu", 2572 "cxo", 2573 "axi", 2574 "memnoc", 2575 "hub", 2576 "demet"; 2577 2578 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2579 <&gpucc GPU_CC_GX_GDSC>; 2580 power-domain-names = "cx", 2581 "gx"; 2582 2583 iommus = <&adreno_smmu 5 0x0>; 2584 2585 qcom,qmp = <&aoss_qmp>; 2586 2587 operating-points-v2 = <&gmu_opp_table>; 2588 2589 gmu_opp_table: opp-table { 2590 compatible = "operating-points-v2"; 2591 2592 opp-500000000 { 2593 opp-hz = /bits/ 64 <500000000>; 2594 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2595 }; 2596 2597 opp-200000000 { 2598 opp-hz = /bits/ 64 <200000000>; 2599 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2600 }; 2601 }; 2602 }; 2603 2604 gpucc: clock-controller@3d90000 { 2605 compatible = "qcom,sm8550-gpucc"; 2606 reg = <0 0x03d90000 0 0xa000>; 2607 clocks = <&bi_tcxo_div2>, 2608 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2609 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2610 #clock-cells = <1>; 2611 #reset-cells = <1>; 2612 #power-domain-cells = <1>; 2613 }; 2614 2615 adreno_smmu: iommu@3da0000 { 2616 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", 2617 "qcom,smmu-500", "arm,mmu-500"; 2618 reg = <0x0 0x03da0000 0x0 0x40000>; 2619 #iommu-cells = <2>; 2620 #global-interrupts = <1>; 2621 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>, 2622 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>, 2623 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>, 2624 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>, 2625 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>, 2626 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>, 2627 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>, 2628 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>, 2629 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>, 2630 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>, 2631 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>, 2632 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>, 2633 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>, 2634 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>, 2635 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>, 2636 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>, 2637 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>, 2638 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>, 2639 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>, 2640 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>, 2641 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, 2642 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>, 2643 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>, 2644 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>, 2645 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>, 2646 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>; 2647 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2648 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2649 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2650 <&gpucc GPU_CC_AHB_CLK>; 2651 clock-names = "hlos", 2652 "bus", 2653 "iface", 2654 "ahb"; 2655 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2656 dma-coherent; 2657 }; 2658 2659 ipa: ipa@3f40000 { 2660 compatible = "qcom,sm8550-ipa"; 2661 2662 iommus = <&apps_smmu 0x4a0 0x0>, 2663 <&apps_smmu 0x4a2 0x0>; 2664 reg = <0 0x3f40000 0 0x10000>, 2665 <0 0x3f50000 0 0x5000>, 2666 <0 0x3e04000 0 0xfc000>; 2667 reg-names = "ipa-reg", 2668 "ipa-shared", 2669 "gsi"; 2670 2671 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>, 2672 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>, 2673 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2674 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2675 interrupt-names = "ipa", 2676 "gsi", 2677 "ipa-clock-query", 2678 "ipa-setup-ready"; 2679 2680 clocks = <&rpmhcc RPMH_IPA_CLK>; 2681 clock-names = "core"; 2682 2683 interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS 2684 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2685 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2686 &config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2687 interconnect-names = "memory", 2688 "config"; 2689 2690 qcom,qmp = <&aoss_qmp>; 2691 2692 qcom,smem-states = <&ipa_smp2p_out 0>, 2693 <&ipa_smp2p_out 1>; 2694 qcom,smem-state-names = "ipa-clock-enabled-valid", 2695 "ipa-clock-enabled"; 2696 2697 status = "disabled"; 2698 }; 2699 2700 remoteproc_mpss: remoteproc@4080000 { 2701 compatible = "qcom,sm8550-mpss-pas"; 2702 reg = <0x0 0x04080000 0x0 0x10000>; 2703 2704 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, 2705 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2706 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2707 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2708 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2709 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2710 interrupt-names = "wdog", "fatal", "ready", "handover", 2711 "stop-ack", "shutdown-ack"; 2712 2713 clocks = <&rpmhcc RPMH_CXO_CLK>; 2714 clock-names = "xo"; 2715 2716 power-domains = <&rpmhpd RPMHPD_CX>, 2717 <&rpmhpd RPMHPD_MSS>; 2718 power-domain-names = "cx", "mss"; 2719 2720 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 2721 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2722 2723 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 2724 2725 qcom,qmp = <&aoss_qmp>; 2726 2727 qcom,smem-states = <&smp2p_modem_out 0>; 2728 qcom,smem-state-names = "stop"; 2729 2730 status = "disabled"; 2731 2732 glink-edge { 2733 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2734 IPCC_MPROC_SIGNAL_GLINK_QMP 2735 IRQ_TYPE_EDGE_RISING>; 2736 mboxes = <&ipcc IPCC_CLIENT_MPSS 2737 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2738 label = "mpss"; 2739 qcom,remote-pid = <1>; 2740 }; 2741 }; 2742 2743 remoteproc_adsp: remoteproc@6800000 { 2744 compatible = "qcom,sm8550-adsp-pas"; 2745 reg = <0x0 0x06800000 0x0 0x10000>; 2746 2747 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2748 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2749 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2750 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2751 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2752 interrupt-names = "wdog", "fatal", "ready", 2753 "handover", "stop-ack"; 2754 2755 clocks = <&rpmhcc RPMH_CXO_CLK>; 2756 clock-names = "xo"; 2757 2758 power-domains = <&rpmhpd RPMHPD_LCX>, 2759 <&rpmhpd RPMHPD_LMX>; 2760 power-domain-names = "lcx", "lmx"; 2761 2762 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 2763 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2764 2765 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2766 2767 qcom,qmp = <&aoss_qmp>; 2768 2769 qcom,smem-states = <&smp2p_adsp_out 0>; 2770 qcom,smem-state-names = "stop"; 2771 2772 status = "disabled"; 2773 2774 remoteproc_adsp_glink: glink-edge { 2775 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2776 IPCC_MPROC_SIGNAL_GLINK_QMP 2777 IRQ_TYPE_EDGE_RISING>; 2778 mboxes = <&ipcc IPCC_CLIENT_LPASS 2779 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2780 2781 label = "lpass"; 2782 qcom,remote-pid = <2>; 2783 2784 fastrpc { 2785 compatible = "qcom,fastrpc"; 2786 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2787 label = "adsp"; 2788 qcom,non-secure-domain; 2789 #address-cells = <1>; 2790 #size-cells = <0>; 2791 2792 compute-cb@3 { 2793 compatible = "qcom,fastrpc-compute-cb"; 2794 reg = <3>; 2795 iommus = <&apps_smmu 0x1003 0x80>, 2796 <&apps_smmu 0x1063 0x0>; 2797 dma-coherent; 2798 }; 2799 2800 compute-cb@4 { 2801 compatible = "qcom,fastrpc-compute-cb"; 2802 reg = <4>; 2803 iommus = <&apps_smmu 0x1004 0x80>, 2804 <&apps_smmu 0x1064 0x0>; 2805 dma-coherent; 2806 }; 2807 2808 compute-cb@5 { 2809 compatible = "qcom,fastrpc-compute-cb"; 2810 reg = <5>; 2811 iommus = <&apps_smmu 0x1005 0x80>, 2812 <&apps_smmu 0x1065 0x0>; 2813 dma-coherent; 2814 }; 2815 2816 compute-cb@6 { 2817 compatible = "qcom,fastrpc-compute-cb"; 2818 reg = <6>; 2819 iommus = <&apps_smmu 0x1006 0x80>, 2820 <&apps_smmu 0x1066 0x0>; 2821 dma-coherent; 2822 }; 2823 2824 compute-cb@7 { 2825 compatible = "qcom,fastrpc-compute-cb"; 2826 reg = <7>; 2827 iommus = <&apps_smmu 0x1007 0x80>, 2828 <&apps_smmu 0x1067 0x0>; 2829 dma-coherent; 2830 }; 2831 }; 2832 2833 gpr { 2834 compatible = "qcom,gpr"; 2835 qcom,glink-channels = "adsp_apps"; 2836 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2837 qcom,intents = <512 20>; 2838 #address-cells = <1>; 2839 #size-cells = <0>; 2840 2841 q6apm: service@1 { 2842 compatible = "qcom,q6apm"; 2843 reg = <GPR_APM_MODULE_IID>; 2844 #sound-dai-cells = <0>; 2845 qcom,protection-domain = "avs/audio", 2846 "msm/adsp/audio_pd"; 2847 2848 q6apmdai: dais { 2849 compatible = "qcom,q6apm-dais"; 2850 iommus = <&apps_smmu 0x1001 0x80>, 2851 <&apps_smmu 0x1061 0x0>; 2852 }; 2853 2854 q6apmbedai: bedais { 2855 compatible = "qcom,q6apm-lpass-dais"; 2856 #sound-dai-cells = <1>; 2857 }; 2858 }; 2859 2860 q6prm: service@2 { 2861 compatible = "qcom,q6prm"; 2862 reg = <GPR_PRM_MODULE_IID>; 2863 qcom,protection-domain = "avs/audio", 2864 "msm/adsp/audio_pd"; 2865 2866 q6prmcc: clock-controller { 2867 compatible = "qcom,q6prm-lpass-clocks"; 2868 #clock-cells = <2>; 2869 }; 2870 }; 2871 }; 2872 }; 2873 }; 2874 2875 lpass_wsa2macro: codec@6aa0000 { 2876 compatible = "qcom,sm8550-lpass-wsa-macro"; 2877 reg = <0 0x06aa0000 0 0x1000>; 2878 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2879 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2880 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2881 <&lpass_vamacro>; 2882 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2883 2884 #clock-cells = <0>; 2885 clock-output-names = "wsa2-mclk"; 2886 #sound-dai-cells = <1>; 2887 }; 2888 2889 swr3: soundwire@6ab0000 { 2890 compatible = "qcom,soundwire-v2.0.0"; 2891 reg = <0 0x06ab0000 0 0x10000>; 2892 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; 2893 clocks = <&lpass_wsa2macro>; 2894 clock-names = "iface"; 2895 label = "WSA2"; 2896 2897 pinctrl-0 = <&wsa2_swr_active>; 2898 pinctrl-names = "default"; 2899 2900 qcom,din-ports = <4>; 2901 qcom,dout-ports = <9>; 2902 2903 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2904 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2905 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2906 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2907 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2908 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2909 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2910 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2911 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2912 2913 #address-cells = <2>; 2914 #size-cells = <0>; 2915 #sound-dai-cells = <1>; 2916 status = "disabled"; 2917 }; 2918 2919 lpass_rxmacro: codec@6ac0000 { 2920 compatible = "qcom,sm8550-lpass-rx-macro"; 2921 reg = <0 0x06ac0000 0 0x1000>; 2922 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2923 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2924 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2925 <&lpass_vamacro>; 2926 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2927 2928 #clock-cells = <0>; 2929 clock-output-names = "mclk"; 2930 #sound-dai-cells = <1>; 2931 }; 2932 2933 swr1: soundwire@6ad0000 { 2934 compatible = "qcom,soundwire-v2.0.0"; 2935 reg = <0 0x06ad0000 0 0x10000>; 2936 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 2937 clocks = <&lpass_rxmacro>; 2938 clock-names = "iface"; 2939 label = "RX"; 2940 2941 pinctrl-0 = <&rx_swr_active>; 2942 pinctrl-names = "default"; 2943 2944 qcom,din-ports = <1>; 2945 qcom,dout-ports = <11>; 2946 2947 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>; 2948 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2949 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2950 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2951 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2952 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>; 2953 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2954 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2955 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2956 2957 #address-cells = <2>; 2958 #size-cells = <0>; 2959 #sound-dai-cells = <1>; 2960 status = "disabled"; 2961 }; 2962 2963 lpass_txmacro: codec@6ae0000 { 2964 compatible = "qcom,sm8550-lpass-tx-macro"; 2965 reg = <0 0x06ae0000 0 0x1000>; 2966 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2967 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2968 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2969 <&lpass_vamacro>; 2970 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2971 2972 #clock-cells = <0>; 2973 clock-output-names = "mclk"; 2974 #sound-dai-cells = <1>; 2975 }; 2976 2977 lpass_wsamacro: codec@6b00000 { 2978 compatible = "qcom,sm8550-lpass-wsa-macro"; 2979 reg = <0 0x06b00000 0 0x1000>; 2980 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2981 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2982 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2983 <&lpass_vamacro>; 2984 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2985 2986 #clock-cells = <0>; 2987 clock-output-names = "mclk"; 2988 #sound-dai-cells = <1>; 2989 }; 2990 2991 swr0: soundwire@6b10000 { 2992 compatible = "qcom,soundwire-v2.0.0"; 2993 reg = <0 0x06b10000 0 0x10000>; 2994 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 2995 clocks = <&lpass_wsamacro>; 2996 clock-names = "iface"; 2997 label = "WSA"; 2998 2999 pinctrl-0 = <&wsa_swr_active>; 3000 pinctrl-names = "default"; 3001 3002 qcom,din-ports = <4>; 3003 qcom,dout-ports = <9>; 3004 3005 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 3006 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 3007 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3008 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3009 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 3010 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 3011 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 3012 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3013 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3014 3015 #address-cells = <2>; 3016 #size-cells = <0>; 3017 #sound-dai-cells = <1>; 3018 status = "disabled"; 3019 }; 3020 3021 swr2: soundwire@6d30000 { 3022 compatible = "qcom,soundwire-v2.0.0"; 3023 reg = <0 0x06d30000 0 0x10000>; 3024 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>, 3025 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>; 3026 interrupt-names = "core", "wakeup"; 3027 clocks = <&lpass_txmacro>; 3028 clock-names = "iface"; 3029 label = "TX"; 3030 3031 pinctrl-0 = <&tx_swr_active>; 3032 pinctrl-names = "default"; 3033 3034 qcom,din-ports = <4>; 3035 qcom,dout-ports = <0>; 3036 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3037 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 3038 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3039 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3040 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3041 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3042 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3043 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3044 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 3045 3046 #address-cells = <2>; 3047 #size-cells = <0>; 3048 #sound-dai-cells = <1>; 3049 status = "disabled"; 3050 }; 3051 3052 lpass_vamacro: codec@6d44000 { 3053 compatible = "qcom,sm8550-lpass-va-macro"; 3054 reg = <0 0x06d44000 0 0x1000>; 3055 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3056 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3057 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3058 clock-names = "mclk", "macro", "dcodec"; 3059 3060 #clock-cells = <0>; 3061 clock-output-names = "fsgen"; 3062 #sound-dai-cells = <1>; 3063 }; 3064 3065 lpass_tlmm: pinctrl@6e80000 { 3066 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 3067 reg = <0 0x06e80000 0 0x20000>, 3068 <0 0x07250000 0 0x10000>; 3069 gpio-controller; 3070 #gpio-cells = <2>; 3071 gpio-ranges = <&lpass_tlmm 0 0 23>; 3072 3073 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3074 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3075 clock-names = "core", "audio"; 3076 3077 tx_swr_active: tx-swr-active-state { 3078 clk-pins { 3079 pins = "gpio0"; 3080 function = "swr_tx_clk"; 3081 drive-strength = <2>; 3082 slew-rate = <1>; 3083 bias-disable; 3084 }; 3085 3086 data-pins { 3087 pins = "gpio1", "gpio2", "gpio14"; 3088 function = "swr_tx_data"; 3089 drive-strength = <2>; 3090 slew-rate = <1>; 3091 bias-bus-hold; 3092 }; 3093 }; 3094 3095 rx_swr_active: rx-swr-active-state { 3096 clk-pins { 3097 pins = "gpio3"; 3098 function = "swr_rx_clk"; 3099 drive-strength = <2>; 3100 slew-rate = <1>; 3101 bias-disable; 3102 }; 3103 3104 data-pins { 3105 pins = "gpio4", "gpio5"; 3106 function = "swr_rx_data"; 3107 drive-strength = <2>; 3108 slew-rate = <1>; 3109 bias-bus-hold; 3110 }; 3111 }; 3112 3113 dmic01_default: dmic01-default-state { 3114 clk-pins { 3115 pins = "gpio6"; 3116 function = "dmic1_clk"; 3117 drive-strength = <8>; 3118 output-high; 3119 }; 3120 3121 data-pins { 3122 pins = "gpio7"; 3123 function = "dmic1_data"; 3124 drive-strength = <8>; 3125 input-enable; 3126 }; 3127 }; 3128 3129 dmic23_default: dmic23-default-state { 3130 clk-pins { 3131 pins = "gpio8"; 3132 function = "dmic2_clk"; 3133 drive-strength = <8>; 3134 output-high; 3135 }; 3136 3137 data-pins { 3138 pins = "gpio9"; 3139 function = "dmic2_data"; 3140 drive-strength = <8>; 3141 input-enable; 3142 }; 3143 }; 3144 3145 wsa_swr_active: wsa-swr-active-state { 3146 clk-pins { 3147 pins = "gpio10"; 3148 function = "wsa_swr_clk"; 3149 drive-strength = <2>; 3150 slew-rate = <1>; 3151 bias-disable; 3152 }; 3153 3154 data-pins { 3155 pins = "gpio11"; 3156 function = "wsa_swr_data"; 3157 drive-strength = <2>; 3158 slew-rate = <1>; 3159 bias-bus-hold; 3160 }; 3161 }; 3162 3163 wsa2_swr_active: wsa2-swr-active-state { 3164 clk-pins { 3165 pins = "gpio15"; 3166 function = "wsa2_swr_clk"; 3167 drive-strength = <2>; 3168 slew-rate = <1>; 3169 bias-disable; 3170 }; 3171 3172 data-pins { 3173 pins = "gpio16"; 3174 function = "wsa2_swr_data"; 3175 drive-strength = <2>; 3176 slew-rate = <1>; 3177 bias-bus-hold; 3178 }; 3179 }; 3180 }; 3181 3182 lpass_lpiaon_noc: interconnect@7400000 { 3183 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 3184 reg = <0 0x07400000 0 0x19080>; 3185 #interconnect-cells = <2>; 3186 qcom,bcm-voters = <&apps_bcm_voter>; 3187 }; 3188 3189 lpass_lpicx_noc: interconnect@7430000 { 3190 compatible = "qcom,sm8550-lpass-lpicx-noc"; 3191 reg = <0 0x07430000 0 0x3a200>; 3192 #interconnect-cells = <2>; 3193 qcom,bcm-voters = <&apps_bcm_voter>; 3194 }; 3195 3196 lpass_ag_noc: interconnect@7e40000 { 3197 compatible = "qcom,sm8550-lpass-ag-noc"; 3198 reg = <0 0x07e40000 0 0xe080>; 3199 #interconnect-cells = <2>; 3200 qcom,bcm-voters = <&apps_bcm_voter>; 3201 }; 3202 3203 sdhc_2: mmc@8804000 { 3204 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 3205 reg = <0 0x08804000 0 0x1000>; 3206 3207 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>, 3208 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH 0>; 3209 interrupt-names = "hc_irq", "pwr_irq"; 3210 3211 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3212 <&gcc GCC_SDCC2_APPS_CLK>, 3213 <&rpmhcc RPMH_CXO_CLK>; 3214 clock-names = "iface", "core", "xo"; 3215 iommus = <&apps_smmu 0x540 0>; 3216 qcom,dll-config = <0x0007642c>; 3217 qcom,ddr-config = <0x80040868>; 3218 power-domains = <&rpmhpd RPMHPD_CX>; 3219 operating-points-v2 = <&sdhc2_opp_table>; 3220 3221 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3222 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3223 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3224 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 3225 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 3226 bus-width = <4>; 3227 max-sd-hs-hz = <37500000>; 3228 dma-coherent; 3229 3230 /* Forbid SDR104/SDR50 - broken hw! */ 3231 sdhci-caps-mask = <0x3 0>; 3232 3233 status = "disabled"; 3234 3235 sdhc2_opp_table: opp-table { 3236 compatible = "operating-points-v2"; 3237 3238 opp-19200000 { 3239 opp-hz = /bits/ 64 <19200000>; 3240 required-opps = <&rpmhpd_opp_min_svs>; 3241 }; 3242 3243 opp-50000000 { 3244 opp-hz = /bits/ 64 <50000000>; 3245 required-opps = <&rpmhpd_opp_low_svs>; 3246 }; 3247 3248 opp-100000000 { 3249 opp-hz = /bits/ 64 <100000000>; 3250 required-opps = <&rpmhpd_opp_svs>; 3251 }; 3252 3253 opp-202000000 { 3254 opp-hz = /bits/ 64 <202000000>; 3255 required-opps = <&rpmhpd_opp_svs_l1>; 3256 }; 3257 }; 3258 }; 3259 3260 iris: video-codec@aa00000 { 3261 compatible = "qcom,sm8550-iris"; 3262 3263 reg = <0 0x0aa00000 0 0xf0000>; 3264 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; 3265 3266 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 3267 <&videocc VIDEO_CC_MVS0_GDSC>, 3268 <&rpmhpd RPMHPD_MXC>, 3269 <&rpmhpd RPMHPD_MMCX>; 3270 power-domain-names = "venus", 3271 "vcodec0", 3272 "mxc", 3273 "mmcx"; 3274 operating-points-v2 = <&iris_opp_table>; 3275 3276 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3277 <&videocc VIDEO_CC_MVS0C_CLK>, 3278 <&videocc VIDEO_CC_MVS0_CLK>; 3279 clock-names = "iface", 3280 "core", 3281 "vcodec0_core"; 3282 3283 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3284 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 3285 <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS 3286 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3287 interconnect-names = "cpu-cfg", 3288 "video-mem"; 3289 3290 memory-region = <&video_mem>; 3291 3292 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 3293 reset-names = "bus"; 3294 3295 iommus = <&apps_smmu 0x1940 0>, 3296 <&apps_smmu 0x1947 0>; 3297 dma-coherent; 3298 3299 /* 3300 * IRIS firmware is signed by vendors, only 3301 * enable on boards where the proper signed firmware 3302 * is available. 3303 */ 3304 status = "disabled"; 3305 3306 iris_opp_table: opp-table { 3307 compatible = "operating-points-v2"; 3308 3309 opp-240000000 { 3310 opp-hz = /bits/ 64 <240000000>; 3311 required-opps = <&rpmhpd_opp_svs>, 3312 <&rpmhpd_opp_low_svs>; 3313 }; 3314 3315 opp-338000000 { 3316 opp-hz = /bits/ 64 <338000000>; 3317 required-opps = <&rpmhpd_opp_svs>, 3318 <&rpmhpd_opp_svs>; 3319 }; 3320 3321 opp-366000000 { 3322 opp-hz = /bits/ 64 <366000000>; 3323 required-opps = <&rpmhpd_opp_svs_l1>, 3324 <&rpmhpd_opp_svs_l1>; 3325 }; 3326 3327 opp-444000000 { 3328 opp-hz = /bits/ 64 <444000000>; 3329 required-opps = <&rpmhpd_opp_nom>, 3330 <&rpmhpd_opp_nom>; 3331 }; 3332 3333 opp-533333334 { 3334 opp-hz = /bits/ 64 <533333334>; 3335 required-opps = <&rpmhpd_opp_turbo>, 3336 <&rpmhpd_opp_turbo>; 3337 }; 3338 }; 3339 }; 3340 3341 videocc: clock-controller@aaf0000 { 3342 compatible = "qcom,sm8550-videocc"; 3343 reg = <0 0x0aaf0000 0 0x10000>; 3344 clocks = <&bi_tcxo_div2>, 3345 <&gcc GCC_VIDEO_AHB_CLK>; 3346 power-domains = <&rpmhpd RPMHPD_MMCX>, 3347 <&rpmhpd RPMHPD_MXC>; 3348 required-opps = <&rpmhpd_opp_low_svs>, 3349 <&rpmhpd_opp_low_svs>; 3350 #clock-cells = <1>; 3351 #reset-cells = <1>; 3352 #power-domain-cells = <1>; 3353 }; 3354 3355 cci0: cci@ac15000 { 3356 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 3357 reg = <0 0x0ac15000 0 0x1000>; 3358 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>; 3359 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3360 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3361 <&camcc CAM_CC_CPAS_AHB_CLK>, 3362 <&camcc CAM_CC_CCI_0_CLK>; 3363 clock-names = "camnoc_axi", 3364 "cpas_ahb", 3365 "cci"; 3366 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 3367 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 3368 pinctrl-names = "default", "sleep"; 3369 status = "disabled"; 3370 #address-cells = <1>; 3371 #size-cells = <0>; 3372 3373 cci0_i2c0: i2c-bus@0 { 3374 reg = <0>; 3375 clock-frequency = <1000000>; 3376 #address-cells = <1>; 3377 #size-cells = <0>; 3378 }; 3379 3380 cci0_i2c1: i2c-bus@1 { 3381 reg = <1>; 3382 clock-frequency = <1000000>; 3383 #address-cells = <1>; 3384 #size-cells = <0>; 3385 }; 3386 }; 3387 3388 cci1: cci@ac16000 { 3389 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 3390 reg = <0 0x0ac16000 0 0x1000>; 3391 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING 0>; 3392 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3393 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3394 <&camcc CAM_CC_CPAS_AHB_CLK>, 3395 <&camcc CAM_CC_CCI_1_CLK>; 3396 clock-names = "camnoc_axi", 3397 "cpas_ahb", 3398 "cci"; 3399 pinctrl-0 = <&cci1_0_default>; 3400 pinctrl-1 = <&cci1_0_sleep>; 3401 pinctrl-names = "default", "sleep"; 3402 status = "disabled"; 3403 #address-cells = <1>; 3404 #size-cells = <0>; 3405 3406 cci1_i2c0: i2c-bus@0 { 3407 reg = <0>; 3408 clock-frequency = <1000000>; 3409 #address-cells = <1>; 3410 #size-cells = <0>; 3411 }; 3412 }; 3413 3414 cci2: cci@ac17000 { 3415 compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; 3416 reg = <0 0x0ac17000 0 0x1000>; 3417 interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING 0>; 3418 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 3419 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3420 <&camcc CAM_CC_CPAS_AHB_CLK>, 3421 <&camcc CAM_CC_CCI_2_CLK>; 3422 clock-names = "camnoc_axi", 3423 "cpas_ahb", 3424 "cci"; 3425 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 3426 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 3427 pinctrl-names = "default", "sleep"; 3428 status = "disabled"; 3429 #address-cells = <1>; 3430 #size-cells = <0>; 3431 3432 cci2_i2c0: i2c-bus@0 { 3433 reg = <0>; 3434 clock-frequency = <1000000>; 3435 #address-cells = <1>; 3436 #size-cells = <0>; 3437 }; 3438 3439 cci2_i2c1: i2c-bus@1 { 3440 reg = <1>; 3441 clock-frequency = <1000000>; 3442 #address-cells = <1>; 3443 #size-cells = <0>; 3444 }; 3445 }; 3446 3447 camss: isp@acb7000 { 3448 compatible = "qcom,sm8550-camss"; 3449 3450 reg = <0x0 0x0acb7000 0x0 0x0d00>, 3451 <0x0 0x0acb9000 0x0 0x0d00>, 3452 <0x0 0x0acbb000 0x0 0x0d00>, 3453 <0x0 0x0acca000 0x0 0x0a00>, 3454 <0x0 0x0acce000 0x0 0x0a00>, 3455 <0x0 0x0acb6000 0x0 0x1000>, 3456 <0x0 0x0ace4000 0x0 0x2000>, 3457 <0x0 0x0ace6000 0x0 0x2000>, 3458 <0x0 0x0ace8000 0x0 0x2000>, 3459 <0x0 0x0acea000 0x0 0x2000>, 3460 <0x0 0x0acec000 0x0 0x2000>, 3461 <0x0 0x0acee000 0x0 0x2000>, 3462 <0x0 0x0acf0000 0x0 0x2000>, 3463 <0x0 0x0acf2000 0x0 0x2000>, 3464 <0x0 0x0ac62000 0x0 0xf000>, 3465 <0x0 0x0ac71000 0x0 0xf000>, 3466 <0x0 0x0ac80000 0x0 0xf000>, 3467 <0x0 0x0accb000 0x0 0x1800>, 3468 <0x0 0x0accf000 0x0 0x1800>; 3469 reg-names = "csid0", 3470 "csid1", 3471 "csid2", 3472 "csid_lite0", 3473 "csid_lite1", 3474 "csid_wrapper", 3475 "csiphy0", 3476 "csiphy1", 3477 "csiphy2", 3478 "csiphy3", 3479 "csiphy4", 3480 "csiphy5", 3481 "csiphy6", 3482 "csiphy7", 3483 "vfe0", 3484 "vfe1", 3485 "vfe2", 3486 "vfe_lite0", 3487 "vfe_lite1"; 3488 3489 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3490 <&camcc CAM_CC_CPAS_AHB_CLK>, 3491 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 3492 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 3493 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 3494 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 3495 <&camcc CAM_CC_CPAS_IFE_2_CLK>, 3496 <&camcc CAM_CC_CSID_CLK>, 3497 <&camcc CAM_CC_CSIPHY0_CLK>, 3498 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 3499 <&camcc CAM_CC_CSIPHY1_CLK>, 3500 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 3501 <&camcc CAM_CC_CSIPHY2_CLK>, 3502 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 3503 <&camcc CAM_CC_CSIPHY3_CLK>, 3504 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 3505 <&camcc CAM_CC_CSIPHY4_CLK>, 3506 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 3507 <&camcc CAM_CC_CSIPHY5_CLK>, 3508 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 3509 <&camcc CAM_CC_CSIPHY6_CLK>, 3510 <&camcc CAM_CC_CSI6PHYTIMER_CLK>, 3511 <&camcc CAM_CC_CSIPHY7_CLK>, 3512 <&camcc CAM_CC_CSI7PHYTIMER_CLK>, 3513 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 3514 <&gcc GCC_CAMERA_HF_AXI_CLK>, 3515 <&camcc CAM_CC_IFE_0_CLK>, 3516 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 3517 <&camcc CAM_CC_IFE_1_CLK>, 3518 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 3519 <&camcc CAM_CC_IFE_2_CLK>, 3520 <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, 3521 <&camcc CAM_CC_IFE_LITE_CLK>, 3522 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 3523 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 3524 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 3525 clock-names = "camnoc_axi", 3526 "cpas_ahb", 3527 "cpas_fast_ahb_clk", 3528 "cpas_ife_lite", 3529 "cpas_vfe0", 3530 "cpas_vfe1", 3531 "cpas_vfe2", 3532 "csid", 3533 "csiphy0", 3534 "csiphy0_timer", 3535 "csiphy1", 3536 "csiphy1_timer", 3537 "csiphy2", 3538 "csiphy2_timer", 3539 "csiphy3", 3540 "csiphy3_timer", 3541 "csiphy4", 3542 "csiphy4_timer", 3543 "csiphy5", 3544 "csiphy5_timer", 3545 "csiphy6", 3546 "csiphy6_timer", 3547 "csiphy7", 3548 "csiphy7_timer", 3549 "csiphy_rx", 3550 "gcc_axi_hf", 3551 "vfe0", 3552 "vfe0_fast_ahb", 3553 "vfe1", 3554 "vfe1_fast_ahb", 3555 "vfe2", 3556 "vfe2_fast_ahb", 3557 "vfe_lite", 3558 "vfe_lite_ahb", 3559 "vfe_lite_cphy_rx", 3560 "vfe_lite_csid"; 3561 3562 interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING 0>, 3563 <GIC_SPI 603 IRQ_TYPE_EDGE_RISING 0>, 3564 <GIC_SPI 431 IRQ_TYPE_EDGE_RISING 0>, 3565 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING 0>, 3566 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING 0>, 3567 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>, 3568 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>, 3569 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>, 3570 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING 0>, 3571 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING 0>, 3572 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING 0>, 3573 <GIC_SPI 278 IRQ_TYPE_EDGE_RISING 0>, 3574 <GIC_SPI 277 IRQ_TYPE_EDGE_RISING 0>, 3575 <GIC_SPI 602 IRQ_TYPE_EDGE_RISING 0>, 3576 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING 0>, 3577 <GIC_SPI 688 IRQ_TYPE_EDGE_RISING 0>, 3578 <GIC_SPI 606 IRQ_TYPE_EDGE_RISING 0>, 3579 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING 0>; 3580 interrupt-names = "csid0", 3581 "csid1", 3582 "csid2", 3583 "csid_lite0", 3584 "csid_lite1", 3585 "csiphy0", 3586 "csiphy1", 3587 "csiphy2", 3588 "csiphy3", 3589 "csiphy4", 3590 "csiphy5", 3591 "csiphy6", 3592 "csiphy7", 3593 "vfe0", 3594 "vfe1", 3595 "vfe2", 3596 "vfe_lite0", 3597 "vfe_lite1"; 3598 3599 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3600 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 3601 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 3602 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3603 interconnect-names = "ahb", 3604 "hf_0_mnoc"; 3605 3606 iommus = <&apps_smmu 0x800 0x20>; 3607 3608 power-domains = <&camcc CAM_CC_IFE_0_GDSC>, 3609 <&camcc CAM_CC_IFE_1_GDSC>, 3610 <&camcc CAM_CC_IFE_2_GDSC>, 3611 <&camcc CAM_CC_TITAN_TOP_GDSC>; 3612 power-domain-names = "ife0", 3613 "ife1", 3614 "ife2", 3615 "top"; 3616 3617 status = "disabled"; 3618 3619 ports { 3620 #address-cells = <1>; 3621 #size-cells = <0>; 3622 3623 port@0 { 3624 reg = <0>; 3625 }; 3626 3627 port@1 { 3628 reg = <1>; 3629 }; 3630 3631 port@2 { 3632 reg = <2>; 3633 }; 3634 3635 port@3 { 3636 reg = <3>; 3637 }; 3638 3639 port@4 { 3640 reg = <4>; 3641 }; 3642 3643 port@5 { 3644 reg = <5>; 3645 }; 3646 3647 port@6 { 3648 reg = <6>; 3649 }; 3650 3651 port@7 { 3652 reg = <7>; 3653 }; 3654 }; 3655 }; 3656 3657 camcc: clock-controller@ade0000 { 3658 compatible = "qcom,sm8550-camcc"; 3659 reg = <0 0x0ade0000 0 0x20000>; 3660 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3661 <&bi_tcxo_div2>, 3662 <&bi_tcxo_ao_div2>, 3663 <&sleep_clk>; 3664 power-domains = <&rpmhpd RPMHPD_MMCX>, 3665 <&rpmhpd RPMHPD_MXC>; 3666 required-opps = <&rpmhpd_opp_low_svs>, 3667 <&rpmhpd_opp_low_svs>; 3668 #clock-cells = <1>; 3669 #reset-cells = <1>; 3670 #power-domain-cells = <1>; 3671 }; 3672 3673 mdss: display-subsystem@ae00000 { 3674 compatible = "qcom,sm8550-mdss"; 3675 reg = <0 0x0ae00000 0 0x1000>; 3676 reg-names = "mdss"; 3677 3678 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>; 3679 interrupt-controller; 3680 #interrupt-cells = <1>; 3681 3682 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3683 <&gcc GCC_DISP_AHB_CLK>, 3684 <&gcc GCC_DISP_HF_AXI_CLK>, 3685 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3686 3687 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3688 3689 power-domains = <&dispcc MDSS_GDSC>; 3690 3691 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 3692 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3693 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3694 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3695 interconnect-names = "mdp0-mem", "cpu-cfg"; 3696 3697 iommus = <&apps_smmu 0x1c00 0x2>; 3698 3699 #address-cells = <2>; 3700 #size-cells = <2>; 3701 ranges; 3702 3703 status = "disabled"; 3704 3705 mdss_mdp: display-controller@ae01000 { 3706 compatible = "qcom,sm8550-dpu"; 3707 reg = <0 0x0ae01000 0 0x8f000>, 3708 <0 0x0aeb0000 0 0x3000>; 3709 reg-names = "mdp", "vbif"; 3710 3711 interrupt-parent = <&mdss>; 3712 interrupts = <0>; 3713 3714 clocks = <&gcc GCC_DISP_AHB_CLK>, 3715 <&gcc GCC_DISP_HF_AXI_CLK>, 3716 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3717 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3718 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3719 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3720 clock-names = "bus", 3721 "nrt_bus", 3722 "iface", 3723 "lut", 3724 "core", 3725 "vsync"; 3726 3727 power-domains = <&rpmhpd RPMHPD_MMCX>; 3728 3729 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3730 assigned-clock-rates = <19200000>; 3731 3732 operating-points-v2 = <&mdp_opp_table>; 3733 3734 ports { 3735 #address-cells = <1>; 3736 #size-cells = <0>; 3737 3738 port@0 { 3739 reg = <0>; 3740 dpu_intf1_out: endpoint { 3741 remote-endpoint = <&mdss_dsi0_in>; 3742 }; 3743 }; 3744 3745 port@1 { 3746 reg = <1>; 3747 dpu_intf2_out: endpoint { 3748 remote-endpoint = <&mdss_dsi1_in>; 3749 }; 3750 }; 3751 3752 port@2 { 3753 reg = <2>; 3754 dpu_intf0_out: endpoint { 3755 remote-endpoint = <&mdss_dp0_in>; 3756 }; 3757 }; 3758 }; 3759 3760 mdp_opp_table: opp-table { 3761 compatible = "operating-points-v2"; 3762 3763 opp-200000000 { 3764 opp-hz = /bits/ 64 <200000000>; 3765 required-opps = <&rpmhpd_opp_low_svs>; 3766 }; 3767 3768 opp-325000000 { 3769 opp-hz = /bits/ 64 <325000000>; 3770 required-opps = <&rpmhpd_opp_svs>; 3771 }; 3772 3773 opp-375000000 { 3774 opp-hz = /bits/ 64 <375000000>; 3775 required-opps = <&rpmhpd_opp_svs_l1>; 3776 }; 3777 3778 opp-514000000 { 3779 opp-hz = /bits/ 64 <514000000>; 3780 required-opps = <&rpmhpd_opp_nom>; 3781 }; 3782 }; 3783 }; 3784 3785 mdss_dp0: displayport-controller@ae90000 { 3786 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 3787 reg = <0 0xae90000 0 0x200>, 3788 <0 0xae90200 0 0x200>, 3789 <0 0xae90400 0 0xc00>, 3790 <0 0xae91000 0 0x400>, 3791 <0 0xae91400 0 0x400>; 3792 interrupt-parent = <&mdss>; 3793 interrupts = <12>; 3794 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3795 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3796 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3797 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3798 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 3799 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 3800 clock-names = "core_iface", 3801 "core_aux", 3802 "ctrl_link", 3803 "ctrl_link_iface", 3804 "stream_pixel", 3805 "stream_1_pixel"; 3806 3807 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3808 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 3809 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 3810 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3811 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3812 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3813 3814 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 3815 phy-names = "dp"; 3816 3817 #sound-dai-cells = <0>; 3818 3819 operating-points-v2 = <&dp_opp_table>; 3820 power-domains = <&rpmhpd RPMHPD_MMCX>; 3821 3822 status = "disabled"; 3823 3824 ports { 3825 #address-cells = <1>; 3826 #size-cells = <0>; 3827 3828 port@0 { 3829 reg = <0>; 3830 mdss_dp0_in: endpoint { 3831 remote-endpoint = <&dpu_intf0_out>; 3832 }; 3833 }; 3834 3835 port@1 { 3836 reg = <1>; 3837 mdss_dp0_out: endpoint { 3838 data-lanes = <0 1 2 3>; 3839 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 3840 }; 3841 }; 3842 }; 3843 3844 dp_opp_table: opp-table { 3845 compatible = "operating-points-v2"; 3846 3847 opp-162000000 { 3848 opp-hz = /bits/ 64 <162000000>; 3849 required-opps = <&rpmhpd_opp_low_svs_d1>; 3850 }; 3851 3852 opp-270000000 { 3853 opp-hz = /bits/ 64 <270000000>; 3854 required-opps = <&rpmhpd_opp_low_svs>; 3855 }; 3856 3857 opp-540000000 { 3858 opp-hz = /bits/ 64 <540000000>; 3859 required-opps = <&rpmhpd_opp_svs_l1>; 3860 }; 3861 3862 opp-810000000 { 3863 opp-hz = /bits/ 64 <810000000>; 3864 required-opps = <&rpmhpd_opp_nom>; 3865 }; 3866 }; 3867 }; 3868 3869 mdss_dsi0: dsi@ae94000 { 3870 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3871 reg = <0 0x0ae94000 0 0x400>; 3872 reg-names = "dsi_ctrl"; 3873 3874 interrupt-parent = <&mdss>; 3875 interrupts = <4>; 3876 3877 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3878 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3879 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3880 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3881 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3882 <&gcc GCC_DISP_HF_AXI_CLK>; 3883 clock-names = "byte", 3884 "byte_intf", 3885 "pixel", 3886 "core", 3887 "iface", 3888 "bus"; 3889 3890 power-domains = <&rpmhpd RPMHPD_MMCX>; 3891 3892 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3893 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3894 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3895 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 3896 3897 operating-points-v2 = <&mdss_dsi_opp_table>; 3898 3899 phys = <&mdss_dsi0_phy>; 3900 phy-names = "dsi"; 3901 3902 #address-cells = <1>; 3903 #size-cells = <0>; 3904 3905 status = "disabled"; 3906 3907 ports { 3908 #address-cells = <1>; 3909 #size-cells = <0>; 3910 3911 port@0 { 3912 reg = <0>; 3913 mdss_dsi0_in: endpoint { 3914 remote-endpoint = <&dpu_intf1_out>; 3915 }; 3916 }; 3917 3918 port@1 { 3919 reg = <1>; 3920 mdss_dsi0_out: endpoint { 3921 }; 3922 }; 3923 }; 3924 3925 mdss_dsi_opp_table: opp-table { 3926 compatible = "operating-points-v2"; 3927 3928 opp-187500000 { 3929 opp-hz = /bits/ 64 <187500000>; 3930 required-opps = <&rpmhpd_opp_low_svs>; 3931 }; 3932 3933 opp-300000000 { 3934 opp-hz = /bits/ 64 <300000000>; 3935 required-opps = <&rpmhpd_opp_svs>; 3936 }; 3937 3938 opp-358000000 { 3939 opp-hz = /bits/ 64 <358000000>; 3940 required-opps = <&rpmhpd_opp_svs_l1>; 3941 }; 3942 }; 3943 }; 3944 3945 mdss_dsi0_phy: phy@ae95000 { 3946 compatible = "qcom,sm8550-dsi-phy-4nm"; 3947 reg = <0 0x0ae95000 0 0x200>, 3948 <0 0x0ae95200 0 0x280>, 3949 <0 0x0ae95500 0 0x400>; 3950 reg-names = "dsi_phy", 3951 "dsi_phy_lane", 3952 "dsi_pll"; 3953 3954 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3955 <&rpmhcc RPMH_CXO_CLK>; 3956 clock-names = "iface", "ref"; 3957 3958 #clock-cells = <1>; 3959 #phy-cells = <0>; 3960 3961 status = "disabled"; 3962 }; 3963 3964 mdss_dsi1: dsi@ae96000 { 3965 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3966 reg = <0 0x0ae96000 0 0x400>; 3967 reg-names = "dsi_ctrl"; 3968 3969 interrupt-parent = <&mdss>; 3970 interrupts = <5>; 3971 3972 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3973 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3974 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3975 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3976 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3977 <&gcc GCC_DISP_HF_AXI_CLK>; 3978 clock-names = "byte", 3979 "byte_intf", 3980 "pixel", 3981 "core", 3982 "iface", 3983 "bus"; 3984 3985 power-domains = <&rpmhpd RPMHPD_MMCX>; 3986 3987 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3988 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3989 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3990 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 3991 3992 operating-points-v2 = <&mdss_dsi_opp_table>; 3993 3994 phys = <&mdss_dsi1_phy>; 3995 phy-names = "dsi"; 3996 3997 #address-cells = <1>; 3998 #size-cells = <0>; 3999 4000 status = "disabled"; 4001 4002 ports { 4003 #address-cells = <1>; 4004 #size-cells = <0>; 4005 4006 port@0 { 4007 reg = <0>; 4008 mdss_dsi1_in: endpoint { 4009 remote-endpoint = <&dpu_intf2_out>; 4010 }; 4011 }; 4012 4013 port@1 { 4014 reg = <1>; 4015 mdss_dsi1_out: endpoint { 4016 }; 4017 }; 4018 }; 4019 }; 4020 4021 mdss_dsi1_phy: phy@ae97000 { 4022 compatible = "qcom,sm8550-dsi-phy-4nm"; 4023 reg = <0 0x0ae97000 0 0x200>, 4024 <0 0x0ae97200 0 0x280>, 4025 <0 0x0ae97500 0 0x400>; 4026 reg-names = "dsi_phy", 4027 "dsi_phy_lane", 4028 "dsi_pll"; 4029 4030 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4031 <&rpmhcc RPMH_CXO_CLK>; 4032 clock-names = "iface", "ref"; 4033 4034 #clock-cells = <1>; 4035 #phy-cells = <0>; 4036 4037 status = "disabled"; 4038 }; 4039 }; 4040 4041 dispcc: clock-controller@af00000 { 4042 compatible = "qcom,sm8550-dispcc"; 4043 reg = <0 0x0af00000 0 0x20000>; 4044 clocks = <&bi_tcxo_div2>, 4045 <&bi_tcxo_ao_div2>, 4046 <&gcc GCC_DISP_AHB_CLK>, 4047 <&sleep_clk>, 4048 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4049 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 4050 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4051 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 4052 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4053 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4054 <0>, /* dp1 */ 4055 <0>, 4056 <0>, /* dp2 */ 4057 <0>, 4058 <0>, /* dp3 */ 4059 <0>; 4060 power-domains = <&rpmhpd RPMHPD_MMCX>; 4061 required-opps = <&rpmhpd_opp_low_svs>; 4062 #clock-cells = <1>; 4063 #reset-cells = <1>; 4064 #power-domain-cells = <1>; 4065 }; 4066 4067 usb_1_hsphy: phy@88e3000 { 4068 compatible = "qcom,sm8550-snps-eusb2-phy"; 4069 reg = <0x0 0x088e3000 0x0 0x154>; 4070 #phy-cells = <0>; 4071 4072 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 4073 clock-names = "ref"; 4074 4075 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4076 4077 status = "disabled"; 4078 }; 4079 4080 usb_dp_qmpphy: phy@88e8000 { 4081 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 4082 reg = <0x0 0x088e8000 0x0 0x3000>; 4083 4084 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4085 <&rpmhcc RPMH_CXO_CLK>, 4086 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4087 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4088 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 4089 4090 power-domains = <&gcc USB3_PHY_GDSC>; 4091 4092 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4093 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 4094 reset-names = "phy", "common"; 4095 4096 #clock-cells = <1>; 4097 #phy-cells = <1>; 4098 4099 mode-switch; 4100 orientation-switch; 4101 4102 status = "disabled"; 4103 4104 ports { 4105 #address-cells = <1>; 4106 #size-cells = <0>; 4107 4108 port@0 { 4109 reg = <0>; 4110 4111 usb_dp_qmpphy_out: endpoint { 4112 }; 4113 }; 4114 4115 port@1 { 4116 reg = <1>; 4117 4118 usb_dp_qmpphy_usb_ss_in: endpoint { 4119 remote-endpoint = <&usb_1_dwc3_ss>; 4120 }; 4121 }; 4122 4123 port@2 { 4124 reg = <2>; 4125 4126 usb_dp_qmpphy_dp_in: endpoint { 4127 remote-endpoint = <&mdss_dp0_out>; 4128 }; 4129 }; 4130 }; 4131 }; 4132 4133 usb_1: usb@a600000 { 4134 compatible = "qcom,sm8550-dwc3", "qcom,snps-dwc3"; 4135 reg = <0x0 0x0a600000 0x0 0xfc100>; 4136 4137 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4138 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4139 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4140 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4141 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4142 <&tcsr TCSR_USB3_CLKREF_EN>; 4143 clock-names = "cfg_noc", 4144 "core", 4145 "iface", 4146 "sleep", 4147 "mock_utmi", 4148 "xo"; 4149 4150 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4151 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4152 assigned-clock-rates = <19200000>, <200000000>; 4153 4154 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, 4155 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, 4156 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, 4157 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4158 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4159 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4160 interrupt-names = "dwc_usb3", 4161 "pwr_event", 4162 "hs_phy_irq", 4163 "dp_hs_phy_irq", 4164 "dm_hs_phy_irq", 4165 "ss_phy_irq"; 4166 4167 power-domains = <&gcc USB30_PRIM_GDSC>; 4168 required-opps = <&rpmhpd_opp_nom>; 4169 4170 resets = <&gcc GCC_USB30_PRIM_BCR>; 4171 4172 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 4173 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4174 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4175 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 4176 interconnect-names = "usb-ddr", "apps-usb"; 4177 4178 iommus = <&apps_smmu 0x40 0x0>; 4179 4180 phys = <&usb_1_hsphy>, 4181 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 4182 phy-names = "usb2-phy", "usb3-phy"; 4183 4184 snps,hird-threshold = /bits/ 8 <0x0>; 4185 snps,usb2-gadget-lpm-disable; 4186 snps,dis_u2_susphy_quirk; 4187 snps,dis_enblslpm_quirk; 4188 snps,dis-u1-entry-quirk; 4189 snps,dis-u2-entry-quirk; 4190 snps,is-utmi-l1-suspend; 4191 snps,usb3_lpm_capable; 4192 snps,usb2-lpm-disable; 4193 snps,has-lpm-erratum; 4194 tx-fifo-resize; 4195 4196 dma-coherent; 4197 4198 usb-role-switch; 4199 4200 status = "disabled"; 4201 4202 ports { 4203 #address-cells = <1>; 4204 #size-cells = <0>; 4205 4206 port@0 { 4207 reg = <0>; 4208 4209 usb_1_dwc3_hs: endpoint { 4210 }; 4211 }; 4212 4213 port@1 { 4214 reg = <1>; 4215 4216 usb_1_dwc3_ss: endpoint { 4217 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 4218 }; 4219 }; 4220 }; 4221 }; 4222 4223 pdc: interrupt-controller@b220000 { 4224 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 4225 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 4226 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4227 <125 63 1>, <126 716 12>, 4228 <138 251 5>; 4229 #interrupt-cells = <2>; 4230 interrupt-parent = <&intc>; 4231 interrupt-controller; 4232 }; 4233 4234 tsens0: thermal-sensor@c271000 { 4235 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 4236 reg = <0 0x0c271000 0 0x1000>, /* TM */ 4237 <0 0x0c222000 0 0x1000>; /* SROT */ 4238 #qcom,sensors = <16>; 4239 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>, 4240 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 4241 interrupt-names = "uplow", "critical"; 4242 #thermal-sensor-cells = <1>; 4243 }; 4244 4245 tsens1: thermal-sensor@c272000 { 4246 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 4247 reg = <0 0x0c272000 0 0x1000>, /* TM */ 4248 <0 0x0c223000 0 0x1000>; /* SROT */ 4249 #qcom,sensors = <16>; 4250 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>, 4251 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 4252 interrupt-names = "uplow", "critical"; 4253 #thermal-sensor-cells = <1>; 4254 }; 4255 4256 tsens2: thermal-sensor@c273000 { 4257 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 4258 reg = <0 0x0c273000 0 0x1000>, /* TM */ 4259 <0 0x0c224000 0 0x1000>; /* SROT */ 4260 #qcom,sensors = <16>; 4261 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>, 4262 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 4263 interrupt-names = "uplow", "critical"; 4264 #thermal-sensor-cells = <1>; 4265 }; 4266 4267 aoss_qmp: power-management@c300000 { 4268 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 4269 reg = <0 0x0c300000 0 0x400>; 4270 interrupt-parent = <&ipcc>; 4271 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4272 IRQ_TYPE_EDGE_RISING>; 4273 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4274 4275 #clock-cells = <0>; 4276 }; 4277 4278 sram@c3f0000 { 4279 compatible = "qcom,rpmh-stats"; 4280 reg = <0 0x0c3f0000 0 0x400>; 4281 qcom,qmp = <&aoss_qmp>; 4282 }; 4283 4284 spmi_bus: spmi@c400000 { 4285 compatible = "qcom,spmi-pmic-arb"; 4286 reg = <0 0x0c400000 0 0x3000>, 4287 <0 0x0c500000 0 0x400000>, 4288 <0 0x0c440000 0 0x80000>, 4289 <0 0x0c4c0000 0 0x20000>, 4290 <0 0x0c42d000 0 0x4000>; 4291 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4292 interrupt-names = "periph_irq"; 4293 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4294 qcom,ee = <0>; 4295 qcom,channel = <0>; 4296 qcom,bus-id = <0>; 4297 #address-cells = <2>; 4298 #size-cells = <0>; 4299 interrupt-controller; 4300 #interrupt-cells = <4>; 4301 }; 4302 4303 tlmm: pinctrl@f100000 { 4304 compatible = "qcom,sm8550-tlmm"; 4305 reg = <0 0x0f100000 0 0x300000>; 4306 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; 4307 gpio-controller; 4308 #gpio-cells = <2>; 4309 interrupt-controller; 4310 #interrupt-cells = <2>; 4311 gpio-ranges = <&tlmm 0 0 211>; 4312 wakeup-parent = <&pdc>; 4313 4314 cam0_default: cam0-default-state { 4315 mclk-pins { 4316 pins = "gpio100"; 4317 function = "cam_mclk"; 4318 drive-strength = <2>; 4319 bias-disable; 4320 }; 4321 }; 4322 4323 cam0_sleep: cam0-sleep-state { 4324 mclk-pins { 4325 pins = "gpio100"; 4326 function = "cam_mclk"; 4327 drive-strength = <2>; 4328 bias-pull-down; 4329 }; 4330 }; 4331 4332 cam1_default: cam1-default-state { 4333 mclk-pins { 4334 pins = "gpio101"; 4335 function = "cam_mclk"; 4336 drive-strength = <2>; 4337 bias-disable; 4338 }; 4339 }; 4340 4341 cam1_sleep: cam1-sleep-state { 4342 mclk-pins { 4343 pins = "gpio101"; 4344 function = "cam_mclk"; 4345 drive-strength = <2>; 4346 bias-pull-down; 4347 }; 4348 }; 4349 4350 cam2_default: cam2-default-state { 4351 mclk-pins { 4352 pins = "gpio102"; 4353 function = "cam_mclk"; 4354 drive-strength = <2>; 4355 bias-disable; 4356 }; 4357 }; 4358 4359 cam2_sleep: cam2-sleep-state { 4360 mclk-pins { 4361 pins = "gpio102"; 4362 function = "cam_mclk"; 4363 drive-strength = <2>; 4364 bias-pull-down; 4365 }; 4366 }; 4367 4368 cam3_default: cam3-default-state { 4369 mclk-pins { 4370 pins = "gpio103"; 4371 function = "cam_mclk"; 4372 drive-strength = <2>; 4373 bias-disable; 4374 }; 4375 }; 4376 4377 cam3_sleep: cam3-sleep-state { 4378 mclk-pins { 4379 pins = "gpio103"; 4380 function = "cam_mclk"; 4381 drive-strength = <2>; 4382 bias-pull-down; 4383 }; 4384 }; 4385 4386 cam4_default: cam4-default-state { 4387 mclk-pins { 4388 pins = "gpio104"; 4389 function = "cam_aon_mclk4"; 4390 drive-strength = <2>; 4391 bias-disable; 4392 }; 4393 }; 4394 4395 cam4_sleep: cam4-sleep-state { 4396 mclk-pins { 4397 pins = "gpio104"; 4398 function = "cam_aon_mclk4"; 4399 drive-strength = <2>; 4400 bias-pull-down; 4401 }; 4402 }; 4403 4404 cam5_default: cam5-default-state { 4405 mclk-pins { 4406 pins = "gpio105"; 4407 function = "cam_mclk"; 4408 drive-strength = <2>; 4409 bias-disable; 4410 }; 4411 }; 4412 4413 cam5_sleep: cam5-sleep-state { 4414 mclk-pins { 4415 pins = "gpio105"; 4416 function = "cam_mclk"; 4417 drive-strength = <2>; 4418 bias-pull-down; 4419 }; 4420 }; 4421 4422 cam6_default: cam6-default-state { 4423 mclk-pins { 4424 pins = "gpio106"; 4425 function = "cam_mclk"; 4426 drive-strength = <2>; 4427 bias-disable; 4428 }; 4429 }; 4430 4431 cam6_sleep: cam6-sleep-state { 4432 mclk-pins { 4433 pins = "gpio106"; 4434 function = "cam_mclk"; 4435 drive-strength = <2>; 4436 bias-pull-down; 4437 }; 4438 }; 4439 4440 cam7_default: cam7-default-state { 4441 mclk-pins { 4442 pins = "gpio107"; 4443 function = "cam_mclk"; 4444 drive-strength = <2>; 4445 bias-disable; 4446 }; 4447 }; 4448 4449 cam7_sleep: cam7-sleep-state { 4450 mclk-pins { 4451 pins = "gpio107"; 4452 function = "cam_mclk"; 4453 drive-strength = <2>; 4454 bias-pull-down; 4455 }; 4456 }; 4457 4458 cci0_0_default: cci0-0-default-state { 4459 sda-pins { 4460 pins = "gpio110"; 4461 function = "cci_i2c_sda"; 4462 drive-strength = <2>; 4463 bias-pull-up = <2200>; 4464 }; 4465 4466 scl-pins { 4467 pins = "gpio111"; 4468 function = "cci_i2c_scl"; 4469 drive-strength = <2>; 4470 bias-pull-up = <2200>; 4471 }; 4472 }; 4473 4474 cci0_0_sleep: cci0-0-sleep-state { 4475 sda-pins { 4476 pins = "gpio110"; 4477 function = "cci_i2c_sda"; 4478 drive-strength = <2>; 4479 bias-pull-down; 4480 }; 4481 4482 scl-pins { 4483 pins = "gpio111"; 4484 function = "cci_i2c_scl"; 4485 drive-strength = <2>; 4486 bias-pull-down; 4487 }; 4488 }; 4489 4490 cci0_1_default: cci0-1-default-state { 4491 sda-pins { 4492 pins = "gpio112"; 4493 function = "cci_i2c_sda"; 4494 drive-strength = <2>; 4495 bias-pull-up = <2200>; 4496 }; 4497 4498 scl-pins { 4499 pins = "gpio113"; 4500 function = "cci_i2c_scl"; 4501 drive-strength = <2>; 4502 bias-pull-up = <2200>; 4503 }; 4504 }; 4505 4506 cci0_1_sleep: cci0-1-sleep-state { 4507 sda-pins { 4508 pins = "gpio112"; 4509 function = "cci_i2c_sda"; 4510 drive-strength = <2>; 4511 bias-pull-down; 4512 }; 4513 4514 scl-pins { 4515 pins = "gpio113"; 4516 function = "cci_i2c_scl"; 4517 drive-strength = <2>; 4518 bias-pull-down; 4519 }; 4520 }; 4521 4522 cci1_0_default: cci1-0-default-state { 4523 sda-pins { 4524 pins = "gpio114"; 4525 function = "cci_i2c_sda"; 4526 drive-strength = <2>; 4527 bias-pull-up = <2200>; 4528 }; 4529 4530 scl-pins { 4531 pins = "gpio115"; 4532 function = "cci_i2c_scl"; 4533 drive-strength = <2>; 4534 bias-pull-up = <2200>; 4535 }; 4536 }; 4537 4538 cci1_0_sleep: cci1-0-sleep-state { 4539 sda-pins { 4540 pins = "gpio114"; 4541 function = "cci_i2c_sda"; 4542 drive-strength = <2>; 4543 bias-pull-down; 4544 }; 4545 4546 scl-pins { 4547 pins = "gpio115"; 4548 function = "cci_i2c_scl"; 4549 drive-strength = <2>; 4550 bias-pull-down; 4551 }; 4552 }; 4553 4554 cci2_0_default: cci2-0-default-state { 4555 sda-pins { 4556 pins = "gpio74"; 4557 function = "cci_i2c_sda"; 4558 drive-strength = <2>; 4559 bias-pull-up = <2200>; 4560 }; 4561 4562 scl-pins { 4563 pins = "gpio75"; 4564 function = "cci_i2c_scl"; 4565 drive-strength = <2>; 4566 bias-pull-up = <2200>; 4567 }; 4568 }; 4569 4570 cci2_0_sleep: cci2-0-sleep-state { 4571 sda-pins { 4572 pins = "gpio74"; 4573 function = "cci_i2c_sda"; 4574 drive-strength = <2>; 4575 bias-pull-down; 4576 }; 4577 4578 scl-pins { 4579 pins = "gpio75"; 4580 function = "cci_i2c_scl"; 4581 drive-strength = <2>; 4582 bias-pull-down; 4583 }; 4584 }; 4585 4586 cci2_1_default: cci2-1-default-state { 4587 sda-pins { 4588 pins = "gpio0"; 4589 function = "cci_i2c_sda"; 4590 drive-strength = <2>; 4591 bias-pull-up = <2200>; 4592 }; 4593 4594 scl-pins { 4595 pins = "gpio1"; 4596 function = "cci_i2c_scl"; 4597 drive-strength = <2>; 4598 bias-pull-up = <2200>; 4599 }; 4600 }; 4601 4602 cci2_1_sleep: cci2-1-sleep-state { 4603 sda-pins { 4604 pins = "gpio0"; 4605 function = "cci_i2c_sda"; 4606 drive-strength = <2>; 4607 bias-pull-down; 4608 }; 4609 4610 scl-pins { 4611 pins = "gpio1"; 4612 function = "cci_i2c_scl"; 4613 drive-strength = <2>; 4614 bias-pull-down; 4615 }; 4616 }; 4617 4618 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 4619 /* SDA, SCL */ 4620 pins = "gpio16", "gpio17"; 4621 function = "i2chub0_se0"; 4622 drive-strength = <2>; 4623 bias-pull-up; 4624 }; 4625 4626 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 4627 /* SDA, SCL */ 4628 pins = "gpio18", "gpio19"; 4629 function = "i2chub0_se1"; 4630 drive-strength = <2>; 4631 bias-pull-up; 4632 }; 4633 4634 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 4635 /* SDA, SCL */ 4636 pins = "gpio20", "gpio21"; 4637 function = "i2chub0_se2"; 4638 drive-strength = <2>; 4639 bias-pull-up; 4640 }; 4641 4642 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 4643 /* SDA, SCL */ 4644 pins = "gpio22", "gpio23"; 4645 function = "i2chub0_se3"; 4646 drive-strength = <2>; 4647 bias-pull-up; 4648 }; 4649 4650 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 4651 /* SDA, SCL */ 4652 pins = "gpio4", "gpio5"; 4653 function = "i2chub0_se4"; 4654 drive-strength = <2>; 4655 bias-pull-up; 4656 }; 4657 4658 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 4659 /* SDA, SCL */ 4660 pins = "gpio6", "gpio7"; 4661 function = "i2chub0_se5"; 4662 drive-strength = <2>; 4663 bias-pull-up; 4664 }; 4665 4666 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 4667 /* SDA, SCL */ 4668 pins = "gpio8", "gpio9"; 4669 function = "i2chub0_se6"; 4670 drive-strength = <2>; 4671 bias-pull-up; 4672 }; 4673 4674 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 4675 /* SDA, SCL */ 4676 pins = "gpio10", "gpio11"; 4677 function = "i2chub0_se7"; 4678 drive-strength = <2>; 4679 bias-pull-up; 4680 }; 4681 4682 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 4683 /* SDA, SCL */ 4684 pins = "gpio206", "gpio207"; 4685 function = "i2chub0_se8"; 4686 drive-strength = <2>; 4687 bias-pull-up; 4688 }; 4689 4690 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 4691 /* SDA, SCL */ 4692 pins = "gpio84", "gpio85"; 4693 function = "i2chub0_se9"; 4694 drive-strength = <2>; 4695 bias-pull-up; 4696 }; 4697 4698 pcie0_default_state: pcie0-default-state { 4699 perst-pins { 4700 pins = "gpio94"; 4701 function = "gpio"; 4702 drive-strength = <2>; 4703 bias-pull-down; 4704 }; 4705 4706 clkreq-pins { 4707 pins = "gpio95"; 4708 function = "pcie0_clk_req_n"; 4709 drive-strength = <2>; 4710 bias-pull-up; 4711 }; 4712 4713 wake-pins { 4714 pins = "gpio96"; 4715 function = "gpio"; 4716 drive-strength = <2>; 4717 bias-pull-up; 4718 }; 4719 }; 4720 4721 pcie1_default_state: pcie1-default-state { 4722 perst-pins { 4723 pins = "gpio97"; 4724 function = "gpio"; 4725 drive-strength = <2>; 4726 bias-pull-down; 4727 }; 4728 4729 clkreq-pins { 4730 pins = "gpio98"; 4731 function = "pcie1_clk_req_n"; 4732 drive-strength = <2>; 4733 bias-pull-up; 4734 }; 4735 4736 wake-pins { 4737 pins = "gpio99"; 4738 function = "gpio"; 4739 drive-strength = <2>; 4740 bias-pull-up; 4741 }; 4742 }; 4743 4744 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4745 /* SDA, SCL */ 4746 pins = "gpio28", "gpio29"; 4747 function = "qup1_se0"; 4748 drive-strength = <2>; 4749 bias-pull-up = <2200>; 4750 }; 4751 4752 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4753 /* SDA, SCL */ 4754 pins = "gpio32", "gpio33"; 4755 function = "qup1_se1"; 4756 drive-strength = <2>; 4757 bias-pull-up = <2200>; 4758 }; 4759 4760 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4761 /* SDA, SCL */ 4762 pins = "gpio36", "gpio37"; 4763 function = "qup1_se2"; 4764 drive-strength = <2>; 4765 bias-pull-up = <2200>; 4766 }; 4767 4768 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4769 /* SDA, SCL */ 4770 pins = "gpio40", "gpio41"; 4771 function = "qup1_se3"; 4772 drive-strength = <2>; 4773 bias-pull-up = <2200>; 4774 }; 4775 4776 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4777 /* SDA, SCL */ 4778 pins = "gpio44", "gpio45"; 4779 function = "qup1_se4"; 4780 drive-strength = <2>; 4781 bias-pull-up = <2200>; 4782 }; 4783 4784 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4785 /* SDA, SCL */ 4786 pins = "gpio52", "gpio53"; 4787 function = "qup1_se5"; 4788 drive-strength = <2>; 4789 bias-pull-up = <2200>; 4790 }; 4791 4792 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4793 /* SDA, SCL */ 4794 pins = "gpio48", "gpio49"; 4795 function = "qup1_se6"; 4796 drive-strength = <2>; 4797 bias-pull-up = <2200>; 4798 }; 4799 4800 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4801 scl-pins { 4802 pins = "gpio57"; 4803 function = "qup2_se0_l1_mira"; 4804 drive-strength = <2>; 4805 bias-pull-up = <2200>; 4806 }; 4807 4808 sda-pins { 4809 pins = "gpio56"; 4810 function = "qup2_se0_l0_mira"; 4811 drive-strength = <2>; 4812 bias-pull-up = <2200>; 4813 }; 4814 }; 4815 4816 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4817 /* SDA, SCL */ 4818 pins = "gpio60", "gpio61"; 4819 function = "qup2_se1"; 4820 drive-strength = <2>; 4821 bias-pull-up = <2200>; 4822 }; 4823 4824 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4825 /* SDA, SCL */ 4826 pins = "gpio64", "gpio65"; 4827 function = "qup2_se2"; 4828 drive-strength = <2>; 4829 bias-pull-up = <2200>; 4830 }; 4831 4832 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4833 /* SDA, SCL */ 4834 pins = "gpio68", "gpio69"; 4835 function = "qup2_se3"; 4836 drive-strength = <2>; 4837 bias-pull-up = <2200>; 4838 }; 4839 4840 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4841 /* SDA, SCL */ 4842 pins = "gpio2", "gpio3"; 4843 function = "qup2_se4"; 4844 drive-strength = <2>; 4845 bias-pull-up = <2200>; 4846 }; 4847 4848 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4849 /* SDA, SCL */ 4850 pins = "gpio80", "gpio81"; 4851 function = "qup2_se5"; 4852 drive-strength = <2>; 4853 bias-pull-up = <2200>; 4854 }; 4855 4856 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4857 /* SDA, SCL */ 4858 pins = "gpio72", "gpio106"; 4859 function = "qup2_se7"; 4860 drive-strength = <2>; 4861 bias-pull-up = <2200>; 4862 }; 4863 4864 qup_spi0_cs: qup-spi0-cs-state { 4865 pins = "gpio31"; 4866 function = "qup1_se0"; 4867 drive-strength = <6>; 4868 bias-disable; 4869 }; 4870 4871 qup_spi0_data_clk: qup-spi0-data-clk-state { 4872 /* MISO, MOSI, CLK */ 4873 pins = "gpio28", "gpio29", "gpio30"; 4874 function = "qup1_se0"; 4875 drive-strength = <6>; 4876 bias-disable; 4877 }; 4878 4879 qup_spi1_cs: qup-spi1-cs-state { 4880 pins = "gpio35"; 4881 function = "qup1_se1"; 4882 drive-strength = <6>; 4883 bias-disable; 4884 }; 4885 4886 qup_spi1_data_clk: qup-spi1-data-clk-state { 4887 /* MISO, MOSI, CLK */ 4888 pins = "gpio32", "gpio33", "gpio34"; 4889 function = "qup1_se1"; 4890 drive-strength = <6>; 4891 bias-disable; 4892 }; 4893 4894 qup_spi2_cs: qup-spi2-cs-state { 4895 pins = "gpio39"; 4896 function = "qup1_se2"; 4897 drive-strength = <6>; 4898 bias-disable; 4899 }; 4900 4901 qup_spi2_data_clk: qup-spi2-data-clk-state { 4902 /* MISO, MOSI, CLK */ 4903 pins = "gpio36", "gpio37", "gpio38"; 4904 function = "qup1_se2"; 4905 drive-strength = <6>; 4906 bias-disable; 4907 }; 4908 4909 qup_spi3_cs: qup-spi3-cs-state { 4910 pins = "gpio43"; 4911 function = "qup1_se3"; 4912 drive-strength = <6>; 4913 bias-disable; 4914 }; 4915 4916 qup_spi3_data_clk: qup-spi3-data-clk-state { 4917 /* MISO, MOSI, CLK */ 4918 pins = "gpio40", "gpio41", "gpio42"; 4919 function = "qup1_se3"; 4920 drive-strength = <6>; 4921 bias-disable; 4922 }; 4923 4924 qup_spi4_cs: qup-spi4-cs-state { 4925 pins = "gpio47"; 4926 function = "qup1_se4"; 4927 drive-strength = <6>; 4928 bias-disable; 4929 }; 4930 4931 qup_spi4_data_clk: qup-spi4-data-clk-state { 4932 /* MISO, MOSI, CLK */ 4933 pins = "gpio44", "gpio45", "gpio46"; 4934 function = "qup1_se4"; 4935 drive-strength = <6>; 4936 bias-disable; 4937 }; 4938 4939 qup_spi5_cs: qup-spi5-cs-state { 4940 pins = "gpio55"; 4941 function = "qup1_se5"; 4942 drive-strength = <6>; 4943 bias-disable; 4944 }; 4945 4946 qup_spi5_data_clk: qup-spi5-data-clk-state { 4947 /* MISO, MOSI, CLK */ 4948 pins = "gpio52", "gpio53", "gpio54"; 4949 function = "qup1_se5"; 4950 drive-strength = <6>; 4951 bias-disable; 4952 }; 4953 4954 qup_spi6_cs: qup-spi6-cs-state { 4955 pins = "gpio51"; 4956 function = "qup1_se6"; 4957 drive-strength = <6>; 4958 bias-disable; 4959 }; 4960 4961 qup_spi6_data_clk: qup-spi6-data-clk-state { 4962 /* MISO, MOSI, CLK */ 4963 pins = "gpio48", "gpio49", "gpio50"; 4964 function = "qup1_se6"; 4965 drive-strength = <6>; 4966 bias-disable; 4967 }; 4968 4969 qup_spi8_cs: qup-spi8-cs-state { 4970 pins = "gpio59"; 4971 function = "qup2_se0_l3_mira"; 4972 drive-strength = <6>; 4973 bias-disable; 4974 }; 4975 4976 qup_spi8_data_clk: qup-spi8-data-clk-state { 4977 /* MISO, MOSI, CLK */ 4978 pins = "gpio56", "gpio57", "gpio58"; 4979 function = "qup2_se0_l2_mira"; 4980 drive-strength = <6>; 4981 bias-disable; 4982 }; 4983 4984 qup_spi9_cs: qup-spi9-cs-state { 4985 pins = "gpio63"; 4986 function = "qup2_se1"; 4987 drive-strength = <6>; 4988 bias-disable; 4989 }; 4990 4991 qup_spi9_data_clk: qup-spi9-data-clk-state { 4992 /* MISO, MOSI, CLK */ 4993 pins = "gpio60", "gpio61", "gpio62"; 4994 function = "qup2_se1"; 4995 drive-strength = <6>; 4996 bias-disable; 4997 }; 4998 4999 qup_spi10_cs: qup-spi10-cs-state { 5000 pins = "gpio67"; 5001 function = "qup2_se2"; 5002 drive-strength = <6>; 5003 bias-disable; 5004 }; 5005 5006 qup_spi10_data_clk: qup-spi10-data-clk-state { 5007 /* MISO, MOSI, CLK */ 5008 pins = "gpio64", "gpio65", "gpio66"; 5009 function = "qup2_se2"; 5010 drive-strength = <6>; 5011 bias-disable; 5012 }; 5013 5014 qup_spi11_cs: qup-spi11-cs-state { 5015 pins = "gpio71"; 5016 function = "qup2_se3"; 5017 drive-strength = <6>; 5018 bias-disable; 5019 }; 5020 5021 qup_spi11_data_clk: qup-spi11-data-clk-state { 5022 /* MISO, MOSI, CLK */ 5023 pins = "gpio68", "gpio69", "gpio70"; 5024 function = "qup2_se3"; 5025 drive-strength = <6>; 5026 bias-disable; 5027 }; 5028 5029 qup_spi12_cs: qup-spi12-cs-state { 5030 pins = "gpio119"; 5031 function = "qup2_se4"; 5032 drive-strength = <6>; 5033 bias-disable; 5034 }; 5035 5036 qup_spi12_data_clk: qup-spi12-data-clk-state { 5037 /* MISO, MOSI, CLK */ 5038 pins = "gpio2", "gpio3", "gpio118"; 5039 function = "qup2_se4"; 5040 drive-strength = <6>; 5041 bias-disable; 5042 }; 5043 5044 qup_spi13_cs: qup-spi13-cs-state { 5045 pins = "gpio83"; 5046 function = "qup2_se5"; 5047 drive-strength = <6>; 5048 bias-disable; 5049 }; 5050 5051 qup_spi13_data_clk: qup-spi13-data-clk-state { 5052 /* MISO, MOSI, CLK */ 5053 pins = "gpio80", "gpio81", "gpio82"; 5054 function = "qup2_se5"; 5055 drive-strength = <6>; 5056 bias-disable; 5057 }; 5058 5059 qup_spi15_cs: qup-spi15-cs-state { 5060 pins = "gpio75"; 5061 function = "qup2_se7"; 5062 drive-strength = <6>; 5063 bias-disable; 5064 }; 5065 5066 qup_spi15_data_clk: qup-spi15-data-clk-state { 5067 /* MISO, MOSI, CLK */ 5068 pins = "gpio72", "gpio106", "gpio74"; 5069 function = "qup2_se7"; 5070 drive-strength = <6>; 5071 bias-disable; 5072 }; 5073 5074 qup_uart7_default: qup-uart7-default-state { 5075 /* TX, RX */ 5076 pins = "gpio26", "gpio27"; 5077 function = "qup1_se7"; 5078 drive-strength = <2>; 5079 bias-disable; 5080 }; 5081 5082 qup_uart14_default: qup-uart14-default-state { 5083 /* TX, RX */ 5084 pins = "gpio78", "gpio79"; 5085 function = "qup2_se6"; 5086 drive-strength = <2>; 5087 bias-pull-up; 5088 }; 5089 5090 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 5091 /* CTS, RTS */ 5092 pins = "gpio76", "gpio77"; 5093 function = "qup2_se6"; 5094 drive-strength = <2>; 5095 bias-pull-down; 5096 }; 5097 5098 sdc2_sleep: sdc2-sleep-state { 5099 clk-pins { 5100 pins = "sdc2_clk"; 5101 bias-disable; 5102 drive-strength = <2>; 5103 }; 5104 5105 cmd-pins { 5106 pins = "sdc2_cmd"; 5107 bias-pull-up; 5108 drive-strength = <2>; 5109 }; 5110 5111 data-pins { 5112 pins = "sdc2_data"; 5113 bias-pull-up; 5114 drive-strength = <2>; 5115 }; 5116 }; 5117 5118 sdc2_default: sdc2-default-state { 5119 clk-pins { 5120 pins = "sdc2_clk"; 5121 bias-disable; 5122 drive-strength = <16>; 5123 }; 5124 5125 cmd-pins { 5126 pins = "sdc2_cmd"; 5127 bias-pull-up; 5128 drive-strength = <10>; 5129 }; 5130 5131 data-pins { 5132 pins = "sdc2_data"; 5133 bias-pull-up; 5134 drive-strength = <10>; 5135 }; 5136 }; 5137 }; 5138 5139 apps_smmu: iommu@15000000 { 5140 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5141 reg = <0 0x15000000 0 0x100000>; 5142 #iommu-cells = <2>; 5143 #global-interrupts = <1>; 5144 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, 5145 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, 5146 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, 5147 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, 5148 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, 5149 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 5150 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, 5151 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 5152 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 5153 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, 5154 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, 5155 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 5156 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 5157 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 5158 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, 5159 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, 5160 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, 5161 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, 5162 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 5163 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, 5164 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, 5165 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, 5166 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, 5167 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, 5168 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, 5169 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, 5170 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, 5171 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, 5172 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, 5173 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, 5174 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, 5175 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, 5176 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, 5177 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, 5178 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, 5179 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, 5180 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, 5181 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, 5182 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, 5183 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, 5184 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, 5185 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, 5186 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, 5187 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, 5188 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, 5189 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, 5190 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, 5191 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, 5192 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, 5193 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, 5194 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, 5195 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, 5196 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, 5197 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, 5198 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, 5199 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, 5200 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, 5201 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, 5202 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, 5203 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, 5204 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, 5205 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>, 5206 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>, 5207 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>, 5208 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>, 5209 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>, 5210 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>, 5211 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 5212 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 5213 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>, 5214 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>, 5215 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>, 5216 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>, 5217 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>, 5218 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>, 5219 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>, 5220 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>, 5221 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>, 5222 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, 5223 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, 5224 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, 5225 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, 5226 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, 5227 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>, 5228 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>, 5229 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>, 5230 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>, 5231 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>, 5232 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>, 5233 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>, 5234 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>, 5235 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>, 5236 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>, 5237 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>, 5238 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>, 5239 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>, 5240 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>; 5241 dma-coherent; 5242 }; 5243 5244 intc: interrupt-controller@17100000 { 5245 compatible = "arm,gic-v3"; 5246 reg = <0 0x17100000 0 0x10000>, /* GICD */ 5247 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 5248 ranges; 5249 #interrupt-cells = <4>; 5250 interrupt-controller; 5251 #redistributor-regions = <1>; 5252 redistributor-stride = <0 0x40000>; 5253 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>; 5254 #address-cells = <2>; 5255 #size-cells = <2>; 5256 5257 ppi-partitions { 5258 ppi_cluster0: interrupt-partition-0 { 5259 affinity = <&cpu0 &cpu1 &cpu2>; 5260 }; 5261 5262 ppi_cluster1: interrupt-partition-1 { 5263 affinity = <&cpu3 &cpu4>; 5264 }; 5265 5266 ppi_cluster2: interrupt-partition-2 { 5267 affinity = <&cpu5 &cpu6>; 5268 }; 5269 5270 ppi_cluster3: interrupt-partition-3 { 5271 affinity = <&cpu7>; 5272 }; 5273 }; 5274 5275 gic_its: msi-controller@17140000 { 5276 compatible = "arm,gic-v3-its"; 5277 reg = <0 0x17140000 0 0x20000>; 5278 msi-controller; 5279 #msi-cells = <1>; 5280 }; 5281 }; 5282 5283 timer@17420000 { 5284 compatible = "arm,armv7-timer-mem"; 5285 reg = <0 0x17420000 0 0x1000>; 5286 ranges = <0 0 0 0x20000000>; 5287 #address-cells = <1>; 5288 #size-cells = <1>; 5289 5290 frame@17421000 { 5291 reg = <0x17421000 0x1000>, 5292 <0x17422000 0x1000>; 5293 frame-number = <0>; 5294 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, 5295 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 5296 }; 5297 5298 frame@17423000 { 5299 reg = <0x17423000 0x1000>; 5300 frame-number = <1>; 5301 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 5302 status = "disabled"; 5303 }; 5304 5305 frame@17425000 { 5306 reg = <0x17425000 0x1000>; 5307 frame-number = <2>; 5308 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 5309 status = "disabled"; 5310 }; 5311 5312 frame@17427000 { 5313 reg = <0x17427000 0x1000>; 5314 frame-number = <3>; 5315 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 5316 status = "disabled"; 5317 }; 5318 5319 frame@17429000 { 5320 reg = <0x17429000 0x1000>; 5321 frame-number = <4>; 5322 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 5323 status = "disabled"; 5324 }; 5325 5326 frame@1742b000 { 5327 reg = <0x1742b000 0x1000>; 5328 frame-number = <5>; 5329 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; 5330 status = "disabled"; 5331 }; 5332 5333 frame@1742d000 { 5334 reg = <0x1742d000 0x1000>; 5335 frame-number = <6>; 5336 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 5337 status = "disabled"; 5338 }; 5339 }; 5340 5341 apps_rsc: rsc@17a00000 { 5342 label = "apps_rsc"; 5343 compatible = "qcom,rpmh-rsc"; 5344 reg = <0 0x17a00000 0 0x10000>, 5345 <0 0x17a10000 0 0x10000>, 5346 <0 0x17a20000 0 0x10000>, 5347 <0 0x17a30000 0 0x10000>; 5348 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 5349 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, 5350 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, 5351 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; 5352 qcom,tcs-offset = <0xd00>; 5353 qcom,drv-id = <2>; 5354 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 5355 <WAKE_TCS 2>, <CONTROL_TCS 0>; 5356 power-domains = <&cluster_pd>; 5357 5358 apps_bcm_voter: bcm-voter { 5359 compatible = "qcom,bcm-voter"; 5360 }; 5361 5362 rpmhcc: clock-controller { 5363 compatible = "qcom,sm8550-rpmh-clk"; 5364 #clock-cells = <1>; 5365 clock-names = "xo"; 5366 clocks = <&xo_board>; 5367 }; 5368 5369 rpmhpd: power-controller { 5370 compatible = "qcom,sm8550-rpmhpd"; 5371 #power-domain-cells = <1>; 5372 operating-points-v2 = <&rpmhpd_opp_table>; 5373 5374 rpmhpd_opp_table: opp-table { 5375 compatible = "operating-points-v2"; 5376 5377 rpmhpd_opp_ret: opp-16 { 5378 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5379 }; 5380 5381 rpmhpd_opp_min_svs: opp-48 { 5382 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5383 }; 5384 5385 rpmhpd_opp_low_svs_d2: opp-52 { 5386 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5387 }; 5388 5389 rpmhpd_opp_low_svs_d1: opp-56 { 5390 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5391 }; 5392 5393 rpmhpd_opp_low_svs_d0: opp-60 { 5394 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5395 }; 5396 5397 rpmhpd_opp_low_svs: opp-64 { 5398 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5399 }; 5400 5401 rpmhpd_opp_low_svs_l1: opp-80 { 5402 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5403 }; 5404 5405 rpmhpd_opp_svs: opp-128 { 5406 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5407 }; 5408 5409 rpmhpd_opp_svs_l0: opp-144 { 5410 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5411 }; 5412 5413 rpmhpd_opp_svs_l1: opp-192 { 5414 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5415 }; 5416 5417 rpmhpd_opp_nom: opp-256 { 5418 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5419 }; 5420 5421 rpmhpd_opp_nom_l1: opp-320 { 5422 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5423 }; 5424 5425 rpmhpd_opp_nom_l2: opp-336 { 5426 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5427 }; 5428 5429 rpmhpd_opp_turbo: opp-384 { 5430 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5431 }; 5432 5433 rpmhpd_opp_turbo_l1: opp-416 { 5434 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5435 }; 5436 }; 5437 }; 5438 }; 5439 5440 cpufreq_hw: cpufreq@17d91000 { 5441 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 5442 reg = <0 0x17d91000 0 0x1000>, 5443 <0 0x17d92000 0 0x1000>, 5444 <0 0x17d93000 0 0x1000>; 5445 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 5446 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 5447 clock-names = "xo", "alternate"; 5448 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, 5449 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>, 5450 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 5451 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5452 #freq-domain-cells = <1>; 5453 #clock-cells = <1>; 5454 }; 5455 5456 pmu@24091000 { 5457 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 5458 reg = <0 0x24091000 0 0x1000>; 5459 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 5460 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 5461 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5462 5463 operating-points-v2 = <&llcc_bwmon_opp_table>; 5464 5465 llcc_bwmon_opp_table: opp-table { 5466 compatible = "operating-points-v2"; 5467 5468 opp-0 { 5469 opp-peak-kBps = <2086000>; 5470 }; 5471 5472 opp-1 { 5473 opp-peak-kBps = <2929000>; 5474 }; 5475 5476 opp-2 { 5477 opp-peak-kBps = <5931000>; 5478 }; 5479 5480 opp-3 { 5481 opp-peak-kBps = <6515000>; 5482 }; 5483 5484 opp-4 { 5485 opp-peak-kBps = <7980000>; 5486 }; 5487 5488 opp-5 { 5489 opp-peak-kBps = <10437000>; 5490 }; 5491 5492 opp-6 { 5493 opp-peak-kBps = <12157000>; 5494 }; 5495 5496 opp-7 { 5497 opp-peak-kBps = <14060000>; 5498 }; 5499 5500 opp-8 { 5501 opp-peak-kBps = <16113000>; 5502 }; 5503 }; 5504 }; 5505 5506 pmu@240b6400 { 5507 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 5508 reg = <0 0x240b6400 0 0x600>; 5509 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>; 5510 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5511 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5512 5513 operating-points-v2 = <&cpu_bwmon_opp_table>; 5514 5515 cpu_bwmon_opp_table: opp-table { 5516 compatible = "operating-points-v2"; 5517 5518 opp-0 { 5519 opp-peak-kBps = <4577000>; 5520 }; 5521 5522 opp-1 { 5523 opp-peak-kBps = <7110000>; 5524 }; 5525 5526 opp-2 { 5527 opp-peak-kBps = <9155000>; 5528 }; 5529 5530 opp-3 { 5531 opp-peak-kBps = <12298000>; 5532 }; 5533 5534 opp-4 { 5535 opp-peak-kBps = <14236000>; 5536 }; 5537 5538 opp-5 { 5539 opp-peak-kBps = <16265000>; 5540 }; 5541 }; 5542 }; 5543 5544 gem_noc: interconnect@24100000 { 5545 compatible = "qcom,sm8550-gem-noc"; 5546 reg = <0 0x24100000 0 0xbb800>; 5547 #interconnect-cells = <2>; 5548 qcom,bcm-voters = <&apps_bcm_voter>; 5549 }; 5550 5551 system-cache-controller@25000000 { 5552 compatible = "qcom,sm8550-llcc"; 5553 reg = <0 0x25000000 0 0x200000>, 5554 <0 0x25200000 0 0x200000>, 5555 <0 0x25400000 0 0x200000>, 5556 <0 0x25600000 0 0x200000>, 5557 <0 0x25800000 0 0x200000>, 5558 <0 0x25a00000 0 0x200000>; 5559 reg-names = "llcc0_base", 5560 "llcc1_base", 5561 "llcc2_base", 5562 "llcc3_base", 5563 "llcc_broadcast_base", 5564 "llcc_broadcast_and_base"; 5565 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH 0>; 5566 }; 5567 5568 nsp_noc: interconnect@320c0000 { 5569 compatible = "qcom,sm8550-nsp-noc"; 5570 reg = <0 0x320c0000 0 0xe080>; 5571 #interconnect-cells = <2>; 5572 qcom,bcm-voters = <&apps_bcm_voter>; 5573 }; 5574 5575 remoteproc_cdsp: remoteproc@32300000 { 5576 compatible = "qcom,sm8550-cdsp-pas"; 5577 reg = <0x0 0x32300000 0x0 0x10000>; 5578 5579 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, 5580 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 5581 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 5582 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 5583 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 5584 interrupt-names = "wdog", "fatal", "ready", 5585 "handover", "stop-ack"; 5586 5587 clocks = <&rpmhcc RPMH_CXO_CLK>; 5588 clock-names = "xo"; 5589 5590 power-domains = <&rpmhpd RPMHPD_CX>, 5591 <&rpmhpd RPMHPD_MXC>, 5592 <&rpmhpd RPMHPD_NSP>; 5593 power-domain-names = "cx", "mxc", "nsp"; 5594 5595 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 5596 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5597 5598 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 5599 5600 qcom,qmp = <&aoss_qmp>; 5601 5602 qcom,smem-states = <&smp2p_cdsp_out 0>; 5603 qcom,smem-state-names = "stop"; 5604 5605 status = "disabled"; 5606 5607 glink-edge { 5608 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5609 IPCC_MPROC_SIGNAL_GLINK_QMP 5610 IRQ_TYPE_EDGE_RISING>; 5611 mboxes = <&ipcc IPCC_CLIENT_CDSP 5612 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5613 5614 label = "cdsp"; 5615 qcom,remote-pid = <5>; 5616 5617 fastrpc { 5618 compatible = "qcom,fastrpc"; 5619 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5620 label = "cdsp"; 5621 qcom,non-secure-domain; 5622 #address-cells = <1>; 5623 #size-cells = <0>; 5624 5625 compute-cb@1 { 5626 compatible = "qcom,fastrpc-compute-cb"; 5627 reg = <1>; 5628 iommus = <&apps_smmu 0x1961 0x0>, 5629 <&apps_smmu 0x0c01 0x20>, 5630 <&apps_smmu 0x19c1 0x10>; 5631 dma-coherent; 5632 }; 5633 5634 compute-cb@2 { 5635 compatible = "qcom,fastrpc-compute-cb"; 5636 reg = <2>; 5637 iommus = <&apps_smmu 0x1962 0x0>, 5638 <&apps_smmu 0x0c02 0x20>, 5639 <&apps_smmu 0x19c2 0x10>; 5640 dma-coherent; 5641 }; 5642 5643 compute-cb@3 { 5644 compatible = "qcom,fastrpc-compute-cb"; 5645 reg = <3>; 5646 iommus = <&apps_smmu 0x1963 0x0>, 5647 <&apps_smmu 0x0c03 0x20>, 5648 <&apps_smmu 0x19c3 0x10>; 5649 dma-coherent; 5650 }; 5651 5652 compute-cb@4 { 5653 compatible = "qcom,fastrpc-compute-cb"; 5654 reg = <4>; 5655 iommus = <&apps_smmu 0x1964 0x0>, 5656 <&apps_smmu 0x0c04 0x20>, 5657 <&apps_smmu 0x19c4 0x10>; 5658 dma-coherent; 5659 }; 5660 5661 compute-cb@5 { 5662 compatible = "qcom,fastrpc-compute-cb"; 5663 reg = <5>; 5664 iommus = <&apps_smmu 0x1965 0x0>, 5665 <&apps_smmu 0x0c05 0x20>, 5666 <&apps_smmu 0x19c5 0x10>; 5667 dma-coherent; 5668 }; 5669 5670 compute-cb@6 { 5671 compatible = "qcom,fastrpc-compute-cb"; 5672 reg = <6>; 5673 iommus = <&apps_smmu 0x1966 0x0>, 5674 <&apps_smmu 0x0c06 0x20>, 5675 <&apps_smmu 0x19c6 0x10>; 5676 dma-coherent; 5677 }; 5678 5679 compute-cb@7 { 5680 compatible = "qcom,fastrpc-compute-cb"; 5681 reg = <7>; 5682 iommus = <&apps_smmu 0x1967 0x0>, 5683 <&apps_smmu 0x0c07 0x20>, 5684 <&apps_smmu 0x19c7 0x10>; 5685 dma-coherent; 5686 }; 5687 5688 compute-cb@8 { 5689 compatible = "qcom,fastrpc-compute-cb"; 5690 reg = <8>; 5691 iommus = <&apps_smmu 0x1968 0x0>, 5692 <&apps_smmu 0x0c08 0x20>, 5693 <&apps_smmu 0x19c8 0x10>; 5694 dma-coherent; 5695 }; 5696 5697 /* note: secure cb9 in downstream */ 5698 }; 5699 }; 5700 }; 5701 }; 5702 5703 thermal-zones { 5704 aoss0-thermal { 5705 thermal-sensors = <&tsens0 0>; 5706 5707 trips { 5708 thermal-engine-config { 5709 temperature = <125000>; 5710 hysteresis = <1000>; 5711 type = "passive"; 5712 }; 5713 5714 reset-mon-config { 5715 temperature = <115000>; 5716 hysteresis = <5000>; 5717 type = "passive"; 5718 }; 5719 }; 5720 }; 5721 5722 cpuss0-thermal { 5723 thermal-sensors = <&tsens0 1>; 5724 5725 trips { 5726 thermal-engine-config { 5727 temperature = <125000>; 5728 hysteresis = <1000>; 5729 type = "passive"; 5730 }; 5731 5732 reset-mon-config { 5733 temperature = <115000>; 5734 hysteresis = <5000>; 5735 type = "passive"; 5736 }; 5737 }; 5738 }; 5739 5740 cpuss1-thermal { 5741 thermal-sensors = <&tsens0 2>; 5742 5743 trips { 5744 thermal-engine-config { 5745 temperature = <125000>; 5746 hysteresis = <1000>; 5747 type = "passive"; 5748 }; 5749 5750 reset-mon-config { 5751 temperature = <115000>; 5752 hysteresis = <5000>; 5753 type = "passive"; 5754 }; 5755 }; 5756 }; 5757 5758 cpuss2-thermal { 5759 thermal-sensors = <&tsens0 3>; 5760 5761 trips { 5762 thermal-engine-config { 5763 temperature = <125000>; 5764 hysteresis = <1000>; 5765 type = "passive"; 5766 }; 5767 5768 reset-mon-config { 5769 temperature = <115000>; 5770 hysteresis = <5000>; 5771 type = "passive"; 5772 }; 5773 }; 5774 }; 5775 5776 cpuss3-thermal { 5777 thermal-sensors = <&tsens0 4>; 5778 5779 trips { 5780 thermal-engine-config { 5781 temperature = <125000>; 5782 hysteresis = <1000>; 5783 type = "passive"; 5784 }; 5785 5786 reset-mon-config { 5787 temperature = <115000>; 5788 hysteresis = <5000>; 5789 type = "passive"; 5790 }; 5791 }; 5792 }; 5793 5794 cpu3-top-thermal { 5795 thermal-sensors = <&tsens0 5>; 5796 5797 trips { 5798 cpu3_top_alert0: trip-point0 { 5799 temperature = <90000>; 5800 hysteresis = <2000>; 5801 type = "passive"; 5802 }; 5803 5804 cpu3_top_alert1: trip-point1 { 5805 temperature = <95000>; 5806 hysteresis = <2000>; 5807 type = "passive"; 5808 }; 5809 5810 cpu3_top_crit: cpu-critical { 5811 temperature = <110000>; 5812 hysteresis = <1000>; 5813 type = "critical"; 5814 }; 5815 }; 5816 }; 5817 5818 cpu3-bottom-thermal { 5819 thermal-sensors = <&tsens0 6>; 5820 5821 trips { 5822 cpu3_bottom_alert0: trip-point0 { 5823 temperature = <90000>; 5824 hysteresis = <2000>; 5825 type = "passive"; 5826 }; 5827 5828 cpu3_bottom_alert1: trip-point1 { 5829 temperature = <95000>; 5830 hysteresis = <2000>; 5831 type = "passive"; 5832 }; 5833 5834 cpu3_bottom_crit: cpu-critical { 5835 temperature = <110000>; 5836 hysteresis = <1000>; 5837 type = "critical"; 5838 }; 5839 }; 5840 }; 5841 5842 cpu4-top-thermal { 5843 thermal-sensors = <&tsens0 7>; 5844 5845 trips { 5846 cpu4_top_alert0: trip-point0 { 5847 temperature = <90000>; 5848 hysteresis = <2000>; 5849 type = "passive"; 5850 }; 5851 5852 cpu4_top_alert1: trip-point1 { 5853 temperature = <95000>; 5854 hysteresis = <2000>; 5855 type = "passive"; 5856 }; 5857 5858 cpu4_top_crit: cpu-critical { 5859 temperature = <110000>; 5860 hysteresis = <1000>; 5861 type = "critical"; 5862 }; 5863 }; 5864 }; 5865 5866 cpu4-bottom-thermal { 5867 thermal-sensors = <&tsens0 8>; 5868 5869 trips { 5870 cpu4_bottom_alert0: trip-point0 { 5871 temperature = <90000>; 5872 hysteresis = <2000>; 5873 type = "passive"; 5874 }; 5875 5876 cpu4_bottom_alert1: trip-point1 { 5877 temperature = <95000>; 5878 hysteresis = <2000>; 5879 type = "passive"; 5880 }; 5881 5882 cpu4_bottom_crit: cpu-critical { 5883 temperature = <110000>; 5884 hysteresis = <1000>; 5885 type = "critical"; 5886 }; 5887 }; 5888 }; 5889 5890 cpu5-top-thermal { 5891 thermal-sensors = <&tsens0 9>; 5892 5893 trips { 5894 cpu5_top_alert0: trip-point0 { 5895 temperature = <90000>; 5896 hysteresis = <2000>; 5897 type = "passive"; 5898 }; 5899 5900 cpu5_top_alert1: trip-point1 { 5901 temperature = <95000>; 5902 hysteresis = <2000>; 5903 type = "passive"; 5904 }; 5905 5906 cpu5_top_crit: cpu-critical { 5907 temperature = <110000>; 5908 hysteresis = <1000>; 5909 type = "critical"; 5910 }; 5911 }; 5912 }; 5913 5914 cpu5-bottom-thermal { 5915 thermal-sensors = <&tsens0 10>; 5916 5917 trips { 5918 cpu5_bottom_alert0: trip-point0 { 5919 temperature = <90000>; 5920 hysteresis = <2000>; 5921 type = "passive"; 5922 }; 5923 5924 cpu5_bottom_alert1: trip-point1 { 5925 temperature = <95000>; 5926 hysteresis = <2000>; 5927 type = "passive"; 5928 }; 5929 5930 cpu5_bottom_crit: cpu-critical { 5931 temperature = <110000>; 5932 hysteresis = <1000>; 5933 type = "critical"; 5934 }; 5935 }; 5936 }; 5937 5938 cpu6-top-thermal { 5939 thermal-sensors = <&tsens0 11>; 5940 5941 trips { 5942 cpu6_top_alert0: trip-point0 { 5943 temperature = <90000>; 5944 hysteresis = <2000>; 5945 type = "passive"; 5946 }; 5947 5948 cpu6_top_alert1: trip-point1 { 5949 temperature = <95000>; 5950 hysteresis = <2000>; 5951 type = "passive"; 5952 }; 5953 5954 cpu6_top_crit: cpu-critical { 5955 temperature = <110000>; 5956 hysteresis = <1000>; 5957 type = "critical"; 5958 }; 5959 }; 5960 }; 5961 5962 cpu6-bottom-thermal { 5963 thermal-sensors = <&tsens0 12>; 5964 5965 trips { 5966 cpu6_bottom_alert0: trip-point0 { 5967 temperature = <90000>; 5968 hysteresis = <2000>; 5969 type = "passive"; 5970 }; 5971 5972 cpu6_bottom_alert1: trip-point1 { 5973 temperature = <95000>; 5974 hysteresis = <2000>; 5975 type = "passive"; 5976 }; 5977 5978 cpu6_bottom_crit: cpu-critical { 5979 temperature = <110000>; 5980 hysteresis = <1000>; 5981 type = "critical"; 5982 }; 5983 }; 5984 }; 5985 5986 cpu7-top-thermal { 5987 thermal-sensors = <&tsens0 13>; 5988 5989 trips { 5990 cpu7_top_alert0: trip-point0 { 5991 temperature = <90000>; 5992 hysteresis = <2000>; 5993 type = "passive"; 5994 }; 5995 5996 cpu7_top_alert1: trip-point1 { 5997 temperature = <95000>; 5998 hysteresis = <2000>; 5999 type = "passive"; 6000 }; 6001 6002 cpu7_top_crit: cpu-critical { 6003 temperature = <110000>; 6004 hysteresis = <1000>; 6005 type = "critical"; 6006 }; 6007 }; 6008 }; 6009 6010 cpu7-middle-thermal { 6011 thermal-sensors = <&tsens0 14>; 6012 6013 trips { 6014 cpu7_middle_alert0: trip-point0 { 6015 temperature = <90000>; 6016 hysteresis = <2000>; 6017 type = "passive"; 6018 }; 6019 6020 cpu7_middle_alert1: trip-point1 { 6021 temperature = <95000>; 6022 hysteresis = <2000>; 6023 type = "passive"; 6024 }; 6025 6026 cpu7_middle_crit: cpu-critical { 6027 temperature = <110000>; 6028 hysteresis = <1000>; 6029 type = "critical"; 6030 }; 6031 }; 6032 }; 6033 6034 cpu7-bottom-thermal { 6035 thermal-sensors = <&tsens0 15>; 6036 6037 trips { 6038 cpu7_bottom_alert0: trip-point0 { 6039 temperature = <90000>; 6040 hysteresis = <2000>; 6041 type = "passive"; 6042 }; 6043 6044 cpu7_bottom_alert1: trip-point1 { 6045 temperature = <95000>; 6046 hysteresis = <2000>; 6047 type = "passive"; 6048 }; 6049 6050 cpu7_bottom_crit: cpu-critical { 6051 temperature = <110000>; 6052 hysteresis = <1000>; 6053 type = "critical"; 6054 }; 6055 }; 6056 }; 6057 6058 aoss1-thermal { 6059 thermal-sensors = <&tsens1 0>; 6060 6061 trips { 6062 thermal-engine-config { 6063 temperature = <125000>; 6064 hysteresis = <1000>; 6065 type = "passive"; 6066 }; 6067 6068 reset-mon-config { 6069 temperature = <115000>; 6070 hysteresis = <5000>; 6071 type = "passive"; 6072 }; 6073 }; 6074 }; 6075 6076 cpu0-thermal { 6077 thermal-sensors = <&tsens1 1>; 6078 6079 trips { 6080 cpu0_alert0: trip-point0 { 6081 temperature = <90000>; 6082 hysteresis = <2000>; 6083 type = "passive"; 6084 }; 6085 6086 cpu0_alert1: trip-point1 { 6087 temperature = <95000>; 6088 hysteresis = <2000>; 6089 type = "passive"; 6090 }; 6091 6092 cpu0_crit: cpu-critical { 6093 temperature = <110000>; 6094 hysteresis = <1000>; 6095 type = "critical"; 6096 }; 6097 }; 6098 }; 6099 6100 cpu1-thermal { 6101 thermal-sensors = <&tsens1 2>; 6102 6103 trips { 6104 cpu1_alert0: trip-point0 { 6105 temperature = <90000>; 6106 hysteresis = <2000>; 6107 type = "passive"; 6108 }; 6109 6110 cpu1_alert1: trip-point1 { 6111 temperature = <95000>; 6112 hysteresis = <2000>; 6113 type = "passive"; 6114 }; 6115 6116 cpu1_crit: cpu-critical { 6117 temperature = <110000>; 6118 hysteresis = <1000>; 6119 type = "critical"; 6120 }; 6121 }; 6122 }; 6123 6124 cpu2-thermal { 6125 thermal-sensors = <&tsens1 3>; 6126 6127 trips { 6128 cpu2_alert0: trip-point0 { 6129 temperature = <90000>; 6130 hysteresis = <2000>; 6131 type = "passive"; 6132 }; 6133 6134 cpu2_alert1: trip-point1 { 6135 temperature = <95000>; 6136 hysteresis = <2000>; 6137 type = "passive"; 6138 }; 6139 6140 cpu2_crit: cpu-critical { 6141 temperature = <110000>; 6142 hysteresis = <1000>; 6143 type = "critical"; 6144 }; 6145 }; 6146 }; 6147 6148 cdsp0-thermal { 6149 polling-delay-passive = <10>; 6150 6151 thermal-sensors = <&tsens2 4>; 6152 6153 trips { 6154 thermal-engine-config { 6155 temperature = <125000>; 6156 hysteresis = <1000>; 6157 type = "passive"; 6158 }; 6159 6160 thermal-hal-config { 6161 temperature = <125000>; 6162 hysteresis = <1000>; 6163 type = "passive"; 6164 }; 6165 6166 reset-mon-config { 6167 temperature = <115000>; 6168 hysteresis = <5000>; 6169 type = "passive"; 6170 }; 6171 6172 cdsp0_junction_config: junction-config { 6173 temperature = <95000>; 6174 hysteresis = <5000>; 6175 type = "passive"; 6176 }; 6177 }; 6178 }; 6179 6180 cdsp1-thermal { 6181 polling-delay-passive = <10>; 6182 6183 thermal-sensors = <&tsens2 5>; 6184 6185 trips { 6186 thermal-engine-config { 6187 temperature = <125000>; 6188 hysteresis = <1000>; 6189 type = "passive"; 6190 }; 6191 6192 thermal-hal-config { 6193 temperature = <125000>; 6194 hysteresis = <1000>; 6195 type = "passive"; 6196 }; 6197 6198 reset-mon-config { 6199 temperature = <115000>; 6200 hysteresis = <5000>; 6201 type = "passive"; 6202 }; 6203 6204 cdsp1_junction_config: junction-config { 6205 temperature = <95000>; 6206 hysteresis = <5000>; 6207 type = "passive"; 6208 }; 6209 }; 6210 }; 6211 6212 cdsp2-thermal { 6213 polling-delay-passive = <10>; 6214 6215 thermal-sensors = <&tsens2 6>; 6216 6217 trips { 6218 thermal-engine-config { 6219 temperature = <125000>; 6220 hysteresis = <1000>; 6221 type = "passive"; 6222 }; 6223 6224 thermal-hal-config { 6225 temperature = <125000>; 6226 hysteresis = <1000>; 6227 type = "passive"; 6228 }; 6229 6230 reset-mon-config { 6231 temperature = <115000>; 6232 hysteresis = <5000>; 6233 type = "passive"; 6234 }; 6235 6236 cdsp2_junction_config: junction-config { 6237 temperature = <95000>; 6238 hysteresis = <5000>; 6239 type = "passive"; 6240 }; 6241 }; 6242 }; 6243 6244 cdsp3-thermal { 6245 polling-delay-passive = <10>; 6246 6247 thermal-sensors = <&tsens2 7>; 6248 6249 trips { 6250 thermal-engine-config { 6251 temperature = <125000>; 6252 hysteresis = <1000>; 6253 type = "passive"; 6254 }; 6255 6256 thermal-hal-config { 6257 temperature = <125000>; 6258 hysteresis = <1000>; 6259 type = "passive"; 6260 }; 6261 6262 reset-mon-config { 6263 temperature = <115000>; 6264 hysteresis = <5000>; 6265 type = "passive"; 6266 }; 6267 6268 cdsp3_junction_config: junction-config { 6269 temperature = <95000>; 6270 hysteresis = <5000>; 6271 type = "passive"; 6272 }; 6273 }; 6274 }; 6275 6276 video-thermal { 6277 thermal-sensors = <&tsens1 8>; 6278 6279 trips { 6280 thermal-engine-config { 6281 temperature = <125000>; 6282 hysteresis = <1000>; 6283 type = "passive"; 6284 }; 6285 6286 reset-mon-config { 6287 temperature = <115000>; 6288 hysteresis = <5000>; 6289 type = "passive"; 6290 }; 6291 }; 6292 }; 6293 6294 mem-thermal { 6295 polling-delay-passive = <10>; 6296 6297 thermal-sensors = <&tsens1 9>; 6298 6299 trips { 6300 thermal-engine-config { 6301 temperature = <125000>; 6302 hysteresis = <1000>; 6303 type = "passive"; 6304 }; 6305 6306 ddr_config0: ddr0-config { 6307 temperature = <90000>; 6308 hysteresis = <5000>; 6309 type = "passive"; 6310 }; 6311 6312 reset-mon-config { 6313 temperature = <115000>; 6314 hysteresis = <5000>; 6315 type = "passive"; 6316 }; 6317 }; 6318 }; 6319 6320 modem0-thermal { 6321 thermal-sensors = <&tsens1 10>; 6322 6323 trips { 6324 thermal-engine-config { 6325 temperature = <125000>; 6326 hysteresis = <1000>; 6327 type = "passive"; 6328 }; 6329 6330 mdmss0_config0: mdmss0-config0 { 6331 temperature = <102000>; 6332 hysteresis = <3000>; 6333 type = "passive"; 6334 }; 6335 6336 mdmss0_config1: mdmss0-config1 { 6337 temperature = <105000>; 6338 hysteresis = <3000>; 6339 type = "passive"; 6340 }; 6341 6342 reset-mon-config { 6343 temperature = <115000>; 6344 hysteresis = <5000>; 6345 type = "passive"; 6346 }; 6347 }; 6348 }; 6349 6350 modem1-thermal { 6351 thermal-sensors = <&tsens1 11>; 6352 6353 trips { 6354 thermal-engine-config { 6355 temperature = <125000>; 6356 hysteresis = <1000>; 6357 type = "passive"; 6358 }; 6359 6360 mdmss1_config0: mdmss1-config0 { 6361 temperature = <102000>; 6362 hysteresis = <3000>; 6363 type = "passive"; 6364 }; 6365 6366 mdmss1_config1: mdmss1-config1 { 6367 temperature = <105000>; 6368 hysteresis = <3000>; 6369 type = "passive"; 6370 }; 6371 6372 reset-mon-config { 6373 temperature = <115000>; 6374 hysteresis = <5000>; 6375 type = "passive"; 6376 }; 6377 }; 6378 }; 6379 6380 modem2-thermal { 6381 thermal-sensors = <&tsens1 12>; 6382 6383 trips { 6384 thermal-engine-config { 6385 temperature = <125000>; 6386 hysteresis = <1000>; 6387 type = "passive"; 6388 }; 6389 6390 mdmss2_config0: mdmss2-config0 { 6391 temperature = <102000>; 6392 hysteresis = <3000>; 6393 type = "passive"; 6394 }; 6395 6396 mdmss2_config1: mdmss2-config1 { 6397 temperature = <105000>; 6398 hysteresis = <3000>; 6399 type = "passive"; 6400 }; 6401 6402 reset-mon-config { 6403 temperature = <115000>; 6404 hysteresis = <5000>; 6405 type = "passive"; 6406 }; 6407 }; 6408 }; 6409 6410 modem3-thermal { 6411 thermal-sensors = <&tsens1 13>; 6412 6413 trips { 6414 thermal-engine-config { 6415 temperature = <125000>; 6416 hysteresis = <1000>; 6417 type = "passive"; 6418 }; 6419 6420 mdmss3_config0: mdmss3-config0 { 6421 temperature = <102000>; 6422 hysteresis = <3000>; 6423 type = "passive"; 6424 }; 6425 6426 mdmss3_config1: mdmss3-config1 { 6427 temperature = <105000>; 6428 hysteresis = <3000>; 6429 type = "passive"; 6430 }; 6431 6432 reset-mon-config { 6433 temperature = <115000>; 6434 hysteresis = <5000>; 6435 type = "passive"; 6436 }; 6437 }; 6438 }; 6439 6440 camera0-thermal { 6441 thermal-sensors = <&tsens1 14>; 6442 6443 trips { 6444 thermal-engine-config { 6445 temperature = <125000>; 6446 hysteresis = <1000>; 6447 type = "passive"; 6448 }; 6449 6450 reset-mon-config { 6451 temperature = <115000>; 6452 hysteresis = <5000>; 6453 type = "passive"; 6454 }; 6455 }; 6456 }; 6457 6458 camera1-thermal { 6459 thermal-sensors = <&tsens1 15>; 6460 6461 trips { 6462 thermal-engine-config { 6463 temperature = <125000>; 6464 hysteresis = <1000>; 6465 type = "passive"; 6466 }; 6467 6468 reset-mon-config { 6469 temperature = <115000>; 6470 hysteresis = <5000>; 6471 type = "passive"; 6472 }; 6473 }; 6474 }; 6475 6476 aoss2-thermal { 6477 thermal-sensors = <&tsens2 0>; 6478 6479 trips { 6480 thermal-engine-config { 6481 temperature = <125000>; 6482 hysteresis = <1000>; 6483 type = "passive"; 6484 }; 6485 6486 reset-mon-config { 6487 temperature = <115000>; 6488 hysteresis = <5000>; 6489 type = "passive"; 6490 }; 6491 }; 6492 }; 6493 6494 gpuss-0-thermal { 6495 polling-delay-passive = <10>; 6496 6497 thermal-sensors = <&tsens2 1>; 6498 6499 cooling-maps { 6500 map0 { 6501 trip = <&gpu0_alert0>; 6502 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6503 }; 6504 }; 6505 6506 trips { 6507 gpu0_alert0: trip-point0 { 6508 temperature = <85000>; 6509 hysteresis = <1000>; 6510 type = "passive"; 6511 }; 6512 6513 trip-point1 { 6514 temperature = <90000>; 6515 hysteresis = <1000>; 6516 type = "hot"; 6517 }; 6518 6519 trip-point2 { 6520 temperature = <110000>; 6521 hysteresis = <1000>; 6522 type = "critical"; 6523 }; 6524 }; 6525 }; 6526 6527 gpuss-1-thermal { 6528 polling-delay-passive = <10>; 6529 6530 thermal-sensors = <&tsens2 2>; 6531 6532 cooling-maps { 6533 map0 { 6534 trip = <&gpu1_alert0>; 6535 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6536 }; 6537 }; 6538 6539 trips { 6540 gpu1_alert0: trip-point0 { 6541 temperature = <85000>; 6542 hysteresis = <1000>; 6543 type = "passive"; 6544 }; 6545 6546 trip-point1 { 6547 temperature = <90000>; 6548 hysteresis = <1000>; 6549 type = "hot"; 6550 }; 6551 6552 trip-point2 { 6553 temperature = <110000>; 6554 hysteresis = <1000>; 6555 type = "critical"; 6556 }; 6557 }; 6558 }; 6559 6560 gpuss-2-thermal { 6561 polling-delay-passive = <10>; 6562 6563 thermal-sensors = <&tsens2 3>; 6564 6565 cooling-maps { 6566 map0 { 6567 trip = <&gpu2_alert0>; 6568 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6569 }; 6570 }; 6571 6572 trips { 6573 gpu2_alert0: trip-point0 { 6574 temperature = <85000>; 6575 hysteresis = <1000>; 6576 type = "passive"; 6577 }; 6578 6579 trip-point1 { 6580 temperature = <90000>; 6581 hysteresis = <1000>; 6582 type = "hot"; 6583 }; 6584 6585 trip-point2 { 6586 temperature = <110000>; 6587 hysteresis = <1000>; 6588 type = "critical"; 6589 }; 6590 }; 6591 }; 6592 6593 gpuss-3-thermal { 6594 polling-delay-passive = <10>; 6595 6596 thermal-sensors = <&tsens2 4>; 6597 6598 cooling-maps { 6599 map0 { 6600 trip = <&gpu3_alert0>; 6601 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6602 }; 6603 }; 6604 6605 trips { 6606 gpu3_alert0: trip-point0 { 6607 temperature = <85000>; 6608 hysteresis = <1000>; 6609 type = "passive"; 6610 }; 6611 6612 trip-point1 { 6613 temperature = <90000>; 6614 hysteresis = <1000>; 6615 type = "hot"; 6616 }; 6617 6618 trip-point2 { 6619 temperature = <110000>; 6620 hysteresis = <1000>; 6621 type = "critical"; 6622 }; 6623 }; 6624 }; 6625 6626 gpuss-4-thermal { 6627 polling-delay-passive = <10>; 6628 6629 thermal-sensors = <&tsens2 5>; 6630 6631 cooling-maps { 6632 map0 { 6633 trip = <&gpu4_alert0>; 6634 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6635 }; 6636 }; 6637 6638 trips { 6639 gpu4_alert0: trip-point0 { 6640 temperature = <85000>; 6641 hysteresis = <1000>; 6642 type = "passive"; 6643 }; 6644 6645 trip-point1 { 6646 temperature = <90000>; 6647 hysteresis = <1000>; 6648 type = "hot"; 6649 }; 6650 6651 trip-point2 { 6652 temperature = <110000>; 6653 hysteresis = <1000>; 6654 type = "critical"; 6655 }; 6656 }; 6657 }; 6658 6659 gpuss-5-thermal { 6660 polling-delay-passive = <10>; 6661 6662 thermal-sensors = <&tsens2 6>; 6663 6664 cooling-maps { 6665 map0 { 6666 trip = <&gpu5_alert0>; 6667 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6668 }; 6669 }; 6670 6671 trips { 6672 gpu5_alert0: trip-point0 { 6673 temperature = <85000>; 6674 hysteresis = <1000>; 6675 type = "passive"; 6676 }; 6677 6678 trip-point1 { 6679 temperature = <90000>; 6680 hysteresis = <1000>; 6681 type = "hot"; 6682 }; 6683 6684 trip-point2 { 6685 temperature = <110000>; 6686 hysteresis = <1000>; 6687 type = "critical"; 6688 }; 6689 }; 6690 }; 6691 6692 gpuss-6-thermal { 6693 polling-delay-passive = <10>; 6694 6695 thermal-sensors = <&tsens2 7>; 6696 6697 cooling-maps { 6698 map0 { 6699 trip = <&gpu6_alert0>; 6700 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6701 }; 6702 }; 6703 6704 trips { 6705 gpu6_alert0: trip-point0 { 6706 temperature = <85000>; 6707 hysteresis = <1000>; 6708 type = "passive"; 6709 }; 6710 6711 trip-point1 { 6712 temperature = <90000>; 6713 hysteresis = <1000>; 6714 type = "hot"; 6715 }; 6716 6717 trip-point2 { 6718 temperature = <110000>; 6719 hysteresis = <1000>; 6720 type = "critical"; 6721 }; 6722 }; 6723 }; 6724 6725 gpuss-7-thermal { 6726 polling-delay-passive = <10>; 6727 6728 thermal-sensors = <&tsens2 8>; 6729 6730 cooling-maps { 6731 map0 { 6732 trip = <&gpu7_alert0>; 6733 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6734 }; 6735 }; 6736 6737 trips { 6738 gpu7_alert0: trip-point0 { 6739 temperature = <85000>; 6740 hysteresis = <1000>; 6741 type = "passive"; 6742 }; 6743 6744 trip-point1 { 6745 temperature = <90000>; 6746 hysteresis = <1000>; 6747 type = "hot"; 6748 }; 6749 6750 trip-point2 { 6751 temperature = <110000>; 6752 hysteresis = <1000>; 6753 type = "critical"; 6754 }; 6755 }; 6756 }; 6757 }; 6758 6759 timer { 6760 compatible = "arm,armv8-timer"; 6761 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 6762 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 6763 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 6764 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; 6765 }; 6766}; 6767