1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8450-videocc.h> 8#include <dt-bindings/clock/qcom,sm8550-camcc.h> 9#include <dt-bindings/clock/qcom,sm8550-gcc.h> 10#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 11#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 12#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 24#include <dt-bindings/phy/phy-qcom-qmp.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 chosen { }; 34 35 clocks { 36 xo_board: xo-board { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 }; 45 46 bi_tcxo_div2: bi-tcxo-div2-clk { 47 #clock-cells = <0>; 48 compatible = "fixed-factor-clock"; 49 clocks = <&rpmhcc RPMH_CXO_CLK>; 50 clock-mult = <1>; 51 clock-div = <2>; 52 }; 53 54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 55 #clock-cells = <0>; 56 compatible = "fixed-factor-clock"; 57 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 58 clock-mult = <1>; 59 clock-div = <2>; 60 }; 61 62 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 }; 66 }; 67 68 cpus { 69 #address-cells = <2>; 70 #size-cells = <0>; 71 72 CPU0: cpu@0 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a510"; 75 reg = <0 0>; 76 clocks = <&cpufreq_hw 0>; 77 enable-method = "psci"; 78 next-level-cache = <&L2_0>; 79 power-domains = <&CPU_PD0>; 80 power-domain-names = "psci"; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 capacity-dmips-mhz = <1024>; 83 dynamic-power-coefficient = <100>; 84 #cooling-cells = <2>; 85 L2_0: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 cache-unified; 89 next-level-cache = <&L3_0>; 90 L3_0: l3-cache { 91 compatible = "cache"; 92 cache-level = <3>; 93 cache-unified; 94 }; 95 }; 96 }; 97 98 CPU1: cpu@100 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a510"; 101 reg = <0 0x100>; 102 clocks = <&cpufreq_hw 0>; 103 enable-method = "psci"; 104 next-level-cache = <&L2_100>; 105 power-domains = <&CPU_PD1>; 106 power-domain-names = "psci"; 107 qcom,freq-domain = <&cpufreq_hw 0>; 108 capacity-dmips-mhz = <1024>; 109 dynamic-power-coefficient = <100>; 110 #cooling-cells = <2>; 111 L2_100: l2-cache { 112 compatible = "cache"; 113 cache-level = <2>; 114 cache-unified; 115 next-level-cache = <&L3_0>; 116 }; 117 }; 118 119 CPU2: cpu@200 { 120 device_type = "cpu"; 121 compatible = "arm,cortex-a510"; 122 reg = <0 0x200>; 123 clocks = <&cpufreq_hw 0>; 124 enable-method = "psci"; 125 next-level-cache = <&L2_200>; 126 power-domains = <&CPU_PD2>; 127 power-domain-names = "psci"; 128 qcom,freq-domain = <&cpufreq_hw 0>; 129 capacity-dmips-mhz = <1024>; 130 dynamic-power-coefficient = <100>; 131 #cooling-cells = <2>; 132 L2_200: l2-cache { 133 compatible = "cache"; 134 cache-level = <2>; 135 cache-unified; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU3: cpu@300 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-a715"; 143 reg = <0 0x300>; 144 clocks = <&cpufreq_hw 1>; 145 enable-method = "psci"; 146 next-level-cache = <&L2_300>; 147 power-domains = <&CPU_PD3>; 148 power-domain-names = "psci"; 149 qcom,freq-domain = <&cpufreq_hw 1>; 150 capacity-dmips-mhz = <1792>; 151 dynamic-power-coefficient = <270>; 152 #cooling-cells = <2>; 153 L2_300: l2-cache { 154 compatible = "cache"; 155 cache-level = <2>; 156 cache-unified; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 161 CPU4: cpu@400 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-a715"; 164 reg = <0 0x400>; 165 clocks = <&cpufreq_hw 1>; 166 enable-method = "psci"; 167 next-level-cache = <&L2_400>; 168 power-domains = <&CPU_PD4>; 169 power-domain-names = "psci"; 170 qcom,freq-domain = <&cpufreq_hw 1>; 171 capacity-dmips-mhz = <1792>; 172 dynamic-power-coefficient = <270>; 173 #cooling-cells = <2>; 174 L2_400: l2-cache { 175 compatible = "cache"; 176 cache-level = <2>; 177 cache-unified; 178 next-level-cache = <&L3_0>; 179 }; 180 }; 181 182 CPU5: cpu@500 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a710"; 185 reg = <0 0x500>; 186 clocks = <&cpufreq_hw 1>; 187 enable-method = "psci"; 188 next-level-cache = <&L2_500>; 189 power-domains = <&CPU_PD5>; 190 power-domain-names = "psci"; 191 qcom,freq-domain = <&cpufreq_hw 1>; 192 capacity-dmips-mhz = <1792>; 193 dynamic-power-coefficient = <270>; 194 #cooling-cells = <2>; 195 L2_500: l2-cache { 196 compatible = "cache"; 197 cache-level = <2>; 198 cache-unified; 199 next-level-cache = <&L3_0>; 200 }; 201 }; 202 203 CPU6: cpu@600 { 204 device_type = "cpu"; 205 compatible = "arm,cortex-a710"; 206 reg = <0 0x600>; 207 clocks = <&cpufreq_hw 1>; 208 enable-method = "psci"; 209 next-level-cache = <&L2_600>; 210 power-domains = <&CPU_PD6>; 211 power-domain-names = "psci"; 212 qcom,freq-domain = <&cpufreq_hw 1>; 213 capacity-dmips-mhz = <1792>; 214 dynamic-power-coefficient = <270>; 215 #cooling-cells = <2>; 216 L2_600: l2-cache { 217 compatible = "cache"; 218 cache-level = <2>; 219 cache-unified; 220 next-level-cache = <&L3_0>; 221 }; 222 }; 223 224 CPU7: cpu@700 { 225 device_type = "cpu"; 226 compatible = "arm,cortex-x3"; 227 reg = <0 0x700>; 228 clocks = <&cpufreq_hw 2>; 229 enable-method = "psci"; 230 next-level-cache = <&L2_700>; 231 power-domains = <&CPU_PD7>; 232 power-domain-names = "psci"; 233 qcom,freq-domain = <&cpufreq_hw 2>; 234 capacity-dmips-mhz = <1894>; 235 dynamic-power-coefficient = <588>; 236 #cooling-cells = <2>; 237 L2_700: l2-cache { 238 compatible = "cache"; 239 cache-level = <2>; 240 cache-unified; 241 next-level-cache = <&L3_0>; 242 }; 243 }; 244 245 cpu-map { 246 cluster0 { 247 core0 { 248 cpu = <&CPU0>; 249 }; 250 251 core1 { 252 cpu = <&CPU1>; 253 }; 254 255 core2 { 256 cpu = <&CPU2>; 257 }; 258 259 core3 { 260 cpu = <&CPU3>; 261 }; 262 263 core4 { 264 cpu = <&CPU4>; 265 }; 266 267 core5 { 268 cpu = <&CPU5>; 269 }; 270 271 core6 { 272 cpu = <&CPU6>; 273 }; 274 275 core7 { 276 cpu = <&CPU7>; 277 }; 278 }; 279 }; 280 281 idle-states { 282 entry-method = "psci"; 283 284 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 285 compatible = "arm,idle-state"; 286 idle-state-name = "silver-rail-power-collapse"; 287 arm,psci-suspend-param = <0x40000004>; 288 entry-latency-us = <550>; 289 exit-latency-us = <750>; 290 min-residency-us = <6700>; 291 local-timer-stop; 292 }; 293 294 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 295 compatible = "arm,idle-state"; 296 idle-state-name = "gold-rail-power-collapse"; 297 arm,psci-suspend-param = <0x40000004>; 298 entry-latency-us = <600>; 299 exit-latency-us = <1300>; 300 min-residency-us = <8136>; 301 local-timer-stop; 302 }; 303 304 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 { 305 compatible = "arm,idle-state"; 306 idle-state-name = "goldplus-rail-power-collapse"; 307 arm,psci-suspend-param = <0x40000004>; 308 entry-latency-us = <500>; 309 exit-latency-us = <1350>; 310 min-residency-us = <7480>; 311 local-timer-stop; 312 }; 313 }; 314 315 domain-idle-states { 316 CLUSTER_SLEEP_0: cluster-sleep-0 { 317 compatible = "domain-idle-state"; 318 arm,psci-suspend-param = <0x41000044>; 319 entry-latency-us = <750>; 320 exit-latency-us = <2350>; 321 min-residency-us = <9144>; 322 }; 323 324 CLUSTER_SLEEP_1: cluster-sleep-1 { 325 compatible = "domain-idle-state"; 326 arm,psci-suspend-param = <0x4100c344>; 327 entry-latency-us = <2800>; 328 exit-latency-us = <4400>; 329 min-residency-us = <10150>; 330 }; 331 }; 332 }; 333 334 firmware { 335 scm: scm { 336 compatible = "qcom,scm-sm8550", "qcom,scm"; 337 qcom,dload-mode = <&tcsr 0x19000>; 338 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 339 }; 340 }; 341 342 clk_virt: interconnect-0 { 343 compatible = "qcom,sm8550-clk-virt"; 344 #interconnect-cells = <2>; 345 qcom,bcm-voters = <&apps_bcm_voter>; 346 }; 347 348 mc_virt: interconnect-1 { 349 compatible = "qcom,sm8550-mc-virt"; 350 #interconnect-cells = <2>; 351 qcom,bcm-voters = <&apps_bcm_voter>; 352 }; 353 354 memory@a0000000 { 355 device_type = "memory"; 356 /* We expect the bootloader to fill in the size */ 357 reg = <0 0xa0000000 0 0>; 358 }; 359 360 pmu { 361 compatible = "arm,armv8-pmuv3"; 362 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 363 }; 364 365 psci { 366 compatible = "arm,psci-1.0"; 367 method = "smc"; 368 369 CPU_PD0: power-domain-cpu0 { 370 #power-domain-cells = <0>; 371 power-domains = <&CLUSTER_PD>; 372 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 373 }; 374 375 CPU_PD1: power-domain-cpu1 { 376 #power-domain-cells = <0>; 377 power-domains = <&CLUSTER_PD>; 378 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 379 }; 380 381 CPU_PD2: power-domain-cpu2 { 382 #power-domain-cells = <0>; 383 power-domains = <&CLUSTER_PD>; 384 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 385 }; 386 387 CPU_PD3: power-domain-cpu3 { 388 #power-domain-cells = <0>; 389 power-domains = <&CLUSTER_PD>; 390 domain-idle-states = <&BIG_CPU_SLEEP_0>; 391 }; 392 393 CPU_PD4: power-domain-cpu4 { 394 #power-domain-cells = <0>; 395 power-domains = <&CLUSTER_PD>; 396 domain-idle-states = <&BIG_CPU_SLEEP_0>; 397 }; 398 399 CPU_PD5: power-domain-cpu5 { 400 #power-domain-cells = <0>; 401 power-domains = <&CLUSTER_PD>; 402 domain-idle-states = <&BIG_CPU_SLEEP_0>; 403 }; 404 405 CPU_PD6: power-domain-cpu6 { 406 #power-domain-cells = <0>; 407 power-domains = <&CLUSTER_PD>; 408 domain-idle-states = <&BIG_CPU_SLEEP_0>; 409 }; 410 411 CPU_PD7: power-domain-cpu7 { 412 #power-domain-cells = <0>; 413 power-domains = <&CLUSTER_PD>; 414 domain-idle-states = <&PRIME_CPU_SLEEP_0>; 415 }; 416 417 CLUSTER_PD: power-domain-cluster { 418 #power-domain-cells = <0>; 419 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 420 }; 421 }; 422 423 reserved_memory: reserved-memory { 424 #address-cells = <2>; 425 #size-cells = <2>; 426 ranges; 427 428 hyp_mem: hyp-region@80000000 { 429 reg = <0 0x80000000 0 0xa00000>; 430 no-map; 431 }; 432 433 cpusys_vm_mem: cpusys-vm-region@80a00000 { 434 reg = <0 0x80a00000 0 0x400000>; 435 no-map; 436 }; 437 438 hyp_tags_mem: hyp-tags-region@80e00000 { 439 reg = <0 0x80e00000 0 0x3d0000>; 440 no-map; 441 }; 442 443 xbl_sc_mem: xbl-sc-region@d8100000 { 444 reg = <0 0xd8100000 0 0x40000>; 445 no-map; 446 }; 447 448 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 449 reg = <0 0x811d0000 0 0x30000>; 450 no-map; 451 }; 452 453 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 454 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 455 reg = <0 0x81a00000 0 0x260000>; 456 no-map; 457 }; 458 459 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 460 compatible = "qcom,cmd-db"; 461 reg = <0 0x81c60000 0 0x20000>; 462 no-map; 463 }; 464 465 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 466 aop_config_merged_mem: aop-config-merged-region@81c80000 { 467 reg = <0 0x81c80000 0 0x74000>; 468 no-map; 469 }; 470 471 /* secdata region can be reused by apps */ 472 smem: smem@81d00000 { 473 compatible = "qcom,smem"; 474 reg = <0 0x81d00000 0 0x200000>; 475 hwlocks = <&tcsr_mutex 3>; 476 no-map; 477 }; 478 479 adsp_mhi_mem: adsp-mhi-region@81f00000 { 480 reg = <0 0x81f00000 0 0x20000>; 481 no-map; 482 }; 483 484 global_sync_mem: global-sync-region@82600000 { 485 reg = <0 0x82600000 0 0x100000>; 486 no-map; 487 }; 488 489 tz_stat_mem: tz-stat-region@82700000 { 490 reg = <0 0x82700000 0 0x100000>; 491 no-map; 492 }; 493 494 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 495 reg = <0 0x82800000 0 0x4600000>; 496 no-map; 497 }; 498 499 mpss_mem: mpss-region@8a800000 { 500 reg = <0 0x8a800000 0 0x10800000>; 501 no-map; 502 }; 503 504 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 505 reg = <0 0x9b000000 0 0x80000>; 506 no-map; 507 }; 508 509 ipa_fw_mem: ipa-fw-region@9b080000 { 510 reg = <0 0x9b080000 0 0x10000>; 511 no-map; 512 }; 513 514 ipa_gsi_mem: ipa-gsi-region@9b090000 { 515 reg = <0 0x9b090000 0 0xa000>; 516 no-map; 517 }; 518 519 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 520 reg = <0 0x9b09a000 0 0x2000>; 521 no-map; 522 }; 523 524 spss_region_mem: spss-region@9b100000 { 525 reg = <0 0x9b100000 0 0x180000>; 526 no-map; 527 }; 528 529 /* First part of the "SPU secure shared memory" region */ 530 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 531 reg = <0 0x9b280000 0 0x60000>; 532 no-map; 533 }; 534 535 /* Second part of the "SPU secure shared memory" region */ 536 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 537 reg = <0 0x9b2e0000 0 0x20000>; 538 no-map; 539 }; 540 541 camera_mem: camera-region@9b300000 { 542 reg = <0 0x9b300000 0 0x800000>; 543 no-map; 544 }; 545 546 video_mem: video-region@9bb00000 { 547 reg = <0 0x9bb00000 0 0x700000>; 548 no-map; 549 }; 550 551 cvp_mem: cvp-region@9c200000 { 552 reg = <0 0x9c200000 0 0x700000>; 553 no-map; 554 }; 555 556 cdsp_mem: cdsp-region@9c900000 { 557 reg = <0 0x9c900000 0 0x2000000>; 558 no-map; 559 }; 560 561 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 562 reg = <0 0x9e900000 0 0x80000>; 563 no-map; 564 }; 565 566 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 567 reg = <0 0x9e980000 0 0x80000>; 568 no-map; 569 }; 570 571 adspslpi_mem: adspslpi-region@9ea00000 { 572 reg = <0 0x9ea00000 0 0x4080000>; 573 no-map; 574 }; 575 576 /* uefi region can be reused by apps */ 577 578 /* Linux kernel image is loaded at 0xa8000000 */ 579 580 rmtfs_mem: rmtfs-region@d4a80000 { 581 compatible = "qcom,rmtfs-mem"; 582 reg = <0x0 0xd4a80000 0x0 0x280000>; 583 no-map; 584 585 qcom,client-id = <1>; 586 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 587 }; 588 589 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 590 reg = <0 0xd4d00000 0 0x3300000>; 591 no-map; 592 }; 593 594 tz_reserved_mem: tz-reserved-region@d8000000 { 595 reg = <0 0xd8000000 0 0x100000>; 596 no-map; 597 }; 598 599 cpucp_fw_mem: cpucp-fw-region@d8140000 { 600 reg = <0 0xd8140000 0 0x1c0000>; 601 no-map; 602 }; 603 604 qtee_mem: qtee-region@d8300000 { 605 reg = <0 0xd8300000 0 0x500000>; 606 no-map; 607 }; 608 609 ta_mem: ta-region@d8800000 { 610 reg = <0 0xd8800000 0 0x8a00000>; 611 no-map; 612 }; 613 614 tz_tags_mem: tz-tags-region@e1200000 { 615 reg = <0 0xe1200000 0 0x2740000>; 616 no-map; 617 }; 618 619 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 620 reg = <0 0xe6440000 0 0x279000>; 621 no-map; 622 }; 623 624 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 625 reg = <0 0xf3600000 0 0x4aee000>; 626 no-map; 627 }; 628 629 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 630 reg = <0 0xf80ee000 0 0x1000>; 631 no-map; 632 }; 633 634 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 635 reg = <0 0xf80ef000 0 0x9000>; 636 no-map; 637 }; 638 639 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 640 reg = <0 0xf80f8000 0 0x4000>; 641 no-map; 642 }; 643 644 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 645 reg = <0 0xf80fc000 0 0x4000>; 646 no-map; 647 }; 648 649 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 650 reg = <0 0xf8100000 0 0x100000>; 651 no-map; 652 }; 653 654 oem_vm_mem: oem-vm-region@f8400000 { 655 reg = <0 0xf8400000 0 0x4800000>; 656 no-map; 657 }; 658 659 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 660 reg = <0 0xfcc00000 0 0x4000>; 661 no-map; 662 }; 663 664 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 665 reg = <0 0xfcc04000 0 0x100000>; 666 no-map; 667 }; 668 669 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 670 reg = <0 0xfce00000 0 0x2900000>; 671 no-map; 672 }; 673 674 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 675 reg = <0 0xff700000 0 0x100000>; 676 no-map; 677 }; 678 }; 679 680 smp2p-adsp { 681 compatible = "qcom,smp2p"; 682 qcom,smem = <443>, <429>; 683 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 684 IPCC_MPROC_SIGNAL_SMP2P 685 IRQ_TYPE_EDGE_RISING>; 686 mboxes = <&ipcc IPCC_CLIENT_LPASS 687 IPCC_MPROC_SIGNAL_SMP2P>; 688 689 qcom,local-pid = <0>; 690 qcom,remote-pid = <2>; 691 692 smp2p_adsp_out: master-kernel { 693 qcom,entry-name = "master-kernel"; 694 #qcom,smem-state-cells = <1>; 695 }; 696 697 smp2p_adsp_in: slave-kernel { 698 qcom,entry-name = "slave-kernel"; 699 interrupt-controller; 700 #interrupt-cells = <2>; 701 }; 702 }; 703 704 smp2p-cdsp { 705 compatible = "qcom,smp2p"; 706 qcom,smem = <94>, <432>; 707 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 708 IPCC_MPROC_SIGNAL_SMP2P 709 IRQ_TYPE_EDGE_RISING>; 710 mboxes = <&ipcc IPCC_CLIENT_CDSP 711 IPCC_MPROC_SIGNAL_SMP2P>; 712 713 qcom,local-pid = <0>; 714 qcom,remote-pid = <5>; 715 716 smp2p_cdsp_out: master-kernel { 717 qcom,entry-name = "master-kernel"; 718 #qcom,smem-state-cells = <1>; 719 }; 720 721 smp2p_cdsp_in: slave-kernel { 722 qcom,entry-name = "slave-kernel"; 723 interrupt-controller; 724 #interrupt-cells = <2>; 725 }; 726 }; 727 728 smp2p-modem { 729 compatible = "qcom,smp2p"; 730 qcom,smem = <435>, <428>; 731 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 732 IPCC_MPROC_SIGNAL_SMP2P 733 IRQ_TYPE_EDGE_RISING>; 734 mboxes = <&ipcc IPCC_CLIENT_MPSS 735 IPCC_MPROC_SIGNAL_SMP2P>; 736 737 qcom,local-pid = <0>; 738 qcom,remote-pid = <1>; 739 740 smp2p_modem_out: master-kernel { 741 qcom,entry-name = "master-kernel"; 742 #qcom,smem-state-cells = <1>; 743 }; 744 745 smp2p_modem_in: slave-kernel { 746 qcom,entry-name = "slave-kernel"; 747 interrupt-controller; 748 #interrupt-cells = <2>; 749 }; 750 751 ipa_smp2p_out: ipa-ap-to-modem { 752 qcom,entry-name = "ipa"; 753 #qcom,smem-state-cells = <1>; 754 }; 755 756 ipa_smp2p_in: ipa-modem-to-ap { 757 qcom,entry-name = "ipa"; 758 interrupt-controller; 759 #interrupt-cells = <2>; 760 }; 761 }; 762 763 soc: soc@0 { 764 compatible = "simple-bus"; 765 ranges = <0 0 0 0 0x10 0>; 766 dma-ranges = <0 0 0 0 0x10 0>; 767 768 #address-cells = <2>; 769 #size-cells = <2>; 770 771 gcc: clock-controller@100000 { 772 compatible = "qcom,sm8550-gcc"; 773 reg = <0 0x00100000 0 0x1f4200>; 774 #clock-cells = <1>; 775 #reset-cells = <1>; 776 #power-domain-cells = <1>; 777 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 778 <&pcie0_phy>, 779 <&pcie1_phy>, 780 <&pcie_1_phy_aux_clk>, 781 <&ufs_mem_phy 0>, 782 <&ufs_mem_phy 1>, 783 <&ufs_mem_phy 2>, 784 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 785 }; 786 787 ipcc: mailbox@408000 { 788 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 789 reg = <0 0x00408000 0 0x1000>; 790 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 791 interrupt-controller; 792 #interrupt-cells = <3>; 793 #mbox-cells = <2>; 794 }; 795 796 gpi_dma2: dma-controller@800000 { 797 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 798 #dma-cells = <3>; 799 reg = <0 0x00800000 0 0x60000>; 800 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 812 dma-channels = <12>; 813 dma-channel-mask = <0x3e>; 814 iommus = <&apps_smmu 0x436 0>; 815 status = "disabled"; 816 }; 817 818 qupv3_id_1: geniqup@8c0000 { 819 compatible = "qcom,geni-se-qup"; 820 reg = <0 0x008c0000 0 0x2000>; 821 ranges; 822 clock-names = "m-ahb", "s-ahb"; 823 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 824 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 825 iommus = <&apps_smmu 0x423 0>; 826 #address-cells = <2>; 827 #size-cells = <2>; 828 status = "disabled"; 829 830 i2c8: i2c@880000 { 831 compatible = "qcom,geni-i2c"; 832 reg = <0 0x00880000 0 0x4000>; 833 clock-names = "se"; 834 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 835 pinctrl-names = "default"; 836 pinctrl-0 = <&qup_i2c8_data_clk>; 837 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 841 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 842 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 843 interconnect-names = "qup-core", "qup-config", "qup-memory"; 844 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 845 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 846 dma-names = "tx", "rx"; 847 status = "disabled"; 848 }; 849 850 spi8: spi@880000 { 851 compatible = "qcom,geni-spi"; 852 reg = <0 0x00880000 0 0x4000>; 853 clock-names = "se"; 854 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 855 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 856 pinctrl-names = "default"; 857 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 858 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 859 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 860 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 861 interconnect-names = "qup-core", "qup-config", "qup-memory"; 862 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 863 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 864 dma-names = "tx", "rx"; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 status = "disabled"; 868 }; 869 870 i2c9: i2c@884000 { 871 compatible = "qcom,geni-i2c"; 872 reg = <0 0x00884000 0 0x4000>; 873 clock-names = "se"; 874 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 875 pinctrl-names = "default"; 876 pinctrl-0 = <&qup_i2c9_data_clk>; 877 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 881 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 882 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 883 interconnect-names = "qup-core", "qup-config", "qup-memory"; 884 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 885 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 886 dma-names = "tx", "rx"; 887 status = "disabled"; 888 }; 889 890 spi9: spi@884000 { 891 compatible = "qcom,geni-spi"; 892 reg = <0 0x00884000 0 0x4000>; 893 clock-names = "se"; 894 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 895 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 896 pinctrl-names = "default"; 897 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 898 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 899 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 900 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 901 interconnect-names = "qup-core", "qup-config", "qup-memory"; 902 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 903 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 904 dma-names = "tx", "rx"; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 status = "disabled"; 908 }; 909 910 i2c10: i2c@888000 { 911 compatible = "qcom,geni-i2c"; 912 reg = <0 0x00888000 0 0x4000>; 913 clock-names = "se"; 914 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 915 pinctrl-names = "default"; 916 pinctrl-0 = <&qup_i2c10_data_clk>; 917 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 921 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 922 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 923 interconnect-names = "qup-core", "qup-config", "qup-memory"; 924 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 925 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 926 dma-names = "tx", "rx"; 927 status = "disabled"; 928 }; 929 930 spi10: spi@888000 { 931 compatible = "qcom,geni-spi"; 932 reg = <0 0x00888000 0 0x4000>; 933 clock-names = "se"; 934 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 935 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 938 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 939 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 940 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 941 interconnect-names = "qup-core", "qup-config", "qup-memory"; 942 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 943 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 944 dma-names = "tx", "rx"; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 status = "disabled"; 948 }; 949 950 i2c11: i2c@88c000 { 951 compatible = "qcom,geni-i2c"; 952 reg = <0 0x0088c000 0 0x4000>; 953 clock-names = "se"; 954 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 955 pinctrl-names = "default"; 956 pinctrl-0 = <&qup_i2c11_data_clk>; 957 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 961 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 962 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 963 interconnect-names = "qup-core", "qup-config", "qup-memory"; 964 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 965 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 966 dma-names = "tx", "rx"; 967 status = "disabled"; 968 }; 969 970 spi11: spi@88c000 { 971 compatible = "qcom,geni-spi"; 972 reg = <0 0x0088c000 0 0x4000>; 973 clock-names = "se"; 974 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 975 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 976 pinctrl-names = "default"; 977 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 978 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 979 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 980 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 981 interconnect-names = "qup-core", "qup-config", "qup-memory"; 982 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 983 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 984 dma-names = "tx", "rx"; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 status = "disabled"; 988 }; 989 990 i2c12: i2c@890000 { 991 compatible = "qcom,geni-i2c"; 992 reg = <0 0x00890000 0 0x4000>; 993 clock-names = "se"; 994 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 995 pinctrl-names = "default"; 996 pinctrl-0 = <&qup_i2c12_data_clk>; 997 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1001 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1002 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1003 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1004 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1005 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1006 dma-names = "tx", "rx"; 1007 status = "disabled"; 1008 }; 1009 1010 spi12: spi@890000 { 1011 compatible = "qcom,geni-spi"; 1012 reg = <0 0x00890000 0 0x4000>; 1013 clock-names = "se"; 1014 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1015 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1018 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1019 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1020 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1021 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1022 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1023 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1024 dma-names = "tx", "rx"; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 status = "disabled"; 1028 }; 1029 1030 i2c13: i2c@894000 { 1031 compatible = "qcom,geni-i2c"; 1032 reg = <0 0x00894000 0 0x4000>; 1033 clock-names = "se"; 1034 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1035 pinctrl-names = "default"; 1036 pinctrl-0 = <&qup_i2c13_data_clk>; 1037 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1041 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1042 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1043 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1044 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1045 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1046 dma-names = "tx", "rx"; 1047 status = "disabled"; 1048 }; 1049 1050 spi13: spi@894000 { 1051 compatible = "qcom,geni-spi"; 1052 reg = <0 0x00894000 0 0x4000>; 1053 clock-names = "se"; 1054 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1055 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1056 pinctrl-names = "default"; 1057 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1058 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1059 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1060 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1061 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1062 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1063 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1064 dma-names = "tx", "rx"; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 status = "disabled"; 1068 }; 1069 1070 uart14: serial@898000 { 1071 compatible = "qcom,geni-uart"; 1072 reg = <0 0x898000 0 0x4000>; 1073 clock-names = "se"; 1074 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1077 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1078 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1079 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1080 interconnect-names = "qup-core", "qup-config"; 1081 status = "disabled"; 1082 }; 1083 1084 i2c15: i2c@89c000 { 1085 compatible = "qcom,geni-i2c"; 1086 reg = <0 0x0089c000 0 0x4000>; 1087 clock-names = "se"; 1088 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&qup_i2c15_data_clk>; 1091 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1095 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1096 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1097 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1098 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1099 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1100 dma-names = "tx", "rx"; 1101 status = "disabled"; 1102 }; 1103 1104 spi15: spi@89c000 { 1105 compatible = "qcom,geni-spi"; 1106 reg = <0 0x0089c000 0 0x4000>; 1107 clock-names = "se"; 1108 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1109 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1110 pinctrl-names = "default"; 1111 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1112 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1113 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1114 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1115 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1116 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1117 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1118 dma-names = "tx", "rx"; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 status = "disabled"; 1122 }; 1123 }; 1124 1125 i2c_master_hub_0: geniqup@9c0000 { 1126 compatible = "qcom,geni-se-i2c-master-hub"; 1127 reg = <0x0 0x009c0000 0x0 0x2000>; 1128 clock-names = "s-ahb"; 1129 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1130 #address-cells = <2>; 1131 #size-cells = <2>; 1132 ranges; 1133 status = "disabled"; 1134 1135 i2c_hub_0: i2c@980000 { 1136 compatible = "qcom,geni-i2c-master-hub"; 1137 reg = <0x0 0x00980000 0x0 0x4000>; 1138 clock-names = "se", "core"; 1139 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1140 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&hub_i2c0_data_clk>; 1143 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1147 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1148 interconnect-names = "qup-core", "qup-config"; 1149 status = "disabled"; 1150 }; 1151 1152 i2c_hub_1: i2c@984000 { 1153 compatible = "qcom,geni-i2c-master-hub"; 1154 reg = <0x0 0x00984000 0x0 0x4000>; 1155 clock-names = "se", "core"; 1156 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1157 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1158 pinctrl-names = "default"; 1159 pinctrl-0 = <&hub_i2c1_data_clk>; 1160 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1164 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1165 interconnect-names = "qup-core", "qup-config"; 1166 status = "disabled"; 1167 }; 1168 1169 i2c_hub_2: i2c@988000 { 1170 compatible = "qcom,geni-i2c-master-hub"; 1171 reg = <0x0 0x00988000 0x0 0x4000>; 1172 clock-names = "se", "core"; 1173 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1174 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&hub_i2c2_data_clk>; 1177 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1181 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1182 interconnect-names = "qup-core", "qup-config"; 1183 status = "disabled"; 1184 }; 1185 1186 i2c_hub_3: i2c@98c000 { 1187 compatible = "qcom,geni-i2c-master-hub"; 1188 reg = <0x0 0x0098c000 0x0 0x4000>; 1189 clock-names = "se", "core"; 1190 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1191 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&hub_i2c3_data_clk>; 1194 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1198 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1199 interconnect-names = "qup-core", "qup-config"; 1200 status = "disabled"; 1201 }; 1202 1203 i2c_hub_4: i2c@990000 { 1204 compatible = "qcom,geni-i2c-master-hub"; 1205 reg = <0x0 0x00990000 0x0 0x4000>; 1206 clock-names = "se", "core"; 1207 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1208 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&hub_i2c4_data_clk>; 1211 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1215 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1216 interconnect-names = "qup-core", "qup-config"; 1217 status = "disabled"; 1218 }; 1219 1220 i2c_hub_5: i2c@994000 { 1221 compatible = "qcom,geni-i2c-master-hub"; 1222 reg = <0 0x00994000 0 0x4000>; 1223 clock-names = "se", "core"; 1224 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1225 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1226 pinctrl-names = "default"; 1227 pinctrl-0 = <&hub_i2c5_data_clk>; 1228 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1232 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1233 interconnect-names = "qup-core", "qup-config"; 1234 status = "disabled"; 1235 }; 1236 1237 i2c_hub_6: i2c@998000 { 1238 compatible = "qcom,geni-i2c-master-hub"; 1239 reg = <0 0x00998000 0 0x4000>; 1240 clock-names = "se", "core"; 1241 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1242 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&hub_i2c6_data_clk>; 1245 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1249 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1250 interconnect-names = "qup-core", "qup-config"; 1251 status = "disabled"; 1252 }; 1253 1254 i2c_hub_7: i2c@99c000 { 1255 compatible = "qcom,geni-i2c-master-hub"; 1256 reg = <0 0x0099c000 0 0x4000>; 1257 clock-names = "se", "core"; 1258 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1259 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&hub_i2c7_data_clk>; 1262 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1266 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1267 interconnect-names = "qup-core", "qup-config"; 1268 status = "disabled"; 1269 }; 1270 1271 i2c_hub_8: i2c@9a0000 { 1272 compatible = "qcom,geni-i2c-master-hub"; 1273 reg = <0 0x009a0000 0 0x4000>; 1274 clock-names = "se", "core"; 1275 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1276 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1277 pinctrl-names = "default"; 1278 pinctrl-0 = <&hub_i2c8_data_clk>; 1279 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1283 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1284 interconnect-names = "qup-core", "qup-config"; 1285 status = "disabled"; 1286 }; 1287 1288 i2c_hub_9: i2c@9a4000 { 1289 compatible = "qcom,geni-i2c-master-hub"; 1290 reg = <0 0x009a4000 0 0x4000>; 1291 clock-names = "se", "core"; 1292 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1293 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&hub_i2c9_data_clk>; 1296 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1300 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1301 interconnect-names = "qup-core", "qup-config"; 1302 status = "disabled"; 1303 }; 1304 }; 1305 1306 gpi_dma1: dma-controller@a00000 { 1307 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1308 #dma-cells = <3>; 1309 reg = <0 0x00a00000 0 0x60000>; 1310 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1311 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1313 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1319 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1320 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1322 dma-channels = <12>; 1323 dma-channel-mask = <0x1e>; 1324 iommus = <&apps_smmu 0xb6 0>; 1325 status = "disabled"; 1326 }; 1327 1328 qupv3_id_0: geniqup@ac0000 { 1329 compatible = "qcom,geni-se-qup"; 1330 reg = <0 0x00ac0000 0 0x2000>; 1331 ranges; 1332 clock-names = "m-ahb", "s-ahb"; 1333 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1334 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1335 iommus = <&apps_smmu 0xa3 0>; 1336 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1337 interconnect-names = "qup-core"; 1338 #address-cells = <2>; 1339 #size-cells = <2>; 1340 status = "disabled"; 1341 1342 i2c0: i2c@a80000 { 1343 compatible = "qcom,geni-i2c"; 1344 reg = <0 0x00a80000 0 0x4000>; 1345 clock-names = "se"; 1346 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1347 pinctrl-names = "default"; 1348 pinctrl-0 = <&qup_i2c0_data_clk>; 1349 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1353 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1354 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1355 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1356 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1357 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1358 dma-names = "tx", "rx"; 1359 status = "disabled"; 1360 }; 1361 1362 spi0: spi@a80000 { 1363 compatible = "qcom,geni-spi"; 1364 reg = <0 0x00a80000 0 0x4000>; 1365 clock-names = "se"; 1366 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1367 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1368 pinctrl-names = "default"; 1369 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1370 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1371 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1372 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1373 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1374 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1375 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1376 dma-names = "tx", "rx"; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 status = "disabled"; 1380 }; 1381 1382 i2c1: i2c@a84000 { 1383 compatible = "qcom,geni-i2c"; 1384 reg = <0 0x00a84000 0 0x4000>; 1385 clock-names = "se"; 1386 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1387 pinctrl-names = "default"; 1388 pinctrl-0 = <&qup_i2c1_data_clk>; 1389 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1393 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1394 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1395 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1396 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1397 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1398 dma-names = "tx", "rx"; 1399 status = "disabled"; 1400 }; 1401 1402 spi1: spi@a84000 { 1403 compatible = "qcom,geni-spi"; 1404 reg = <0 0x00a84000 0 0x4000>; 1405 clock-names = "se"; 1406 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1407 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1408 pinctrl-names = "default"; 1409 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1410 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1411 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1412 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1413 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1414 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1415 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1416 dma-names = "tx", "rx"; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 status = "disabled"; 1420 }; 1421 1422 i2c2: i2c@a88000 { 1423 compatible = "qcom,geni-i2c"; 1424 reg = <0 0x00a88000 0 0x4000>; 1425 clock-names = "se"; 1426 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1427 pinctrl-names = "default"; 1428 pinctrl-0 = <&qup_i2c2_data_clk>; 1429 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1433 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1434 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1435 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1436 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1437 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1438 dma-names = "tx", "rx"; 1439 status = "disabled"; 1440 }; 1441 1442 spi2: spi@a88000 { 1443 compatible = "qcom,geni-spi"; 1444 reg = <0 0x00a88000 0 0x4000>; 1445 clock-names = "se"; 1446 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1447 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1448 pinctrl-names = "default"; 1449 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1450 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1451 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1452 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1453 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1454 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1455 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1456 dma-names = "tx", "rx"; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 status = "disabled"; 1460 }; 1461 1462 i2c3: i2c@a8c000 { 1463 compatible = "qcom,geni-i2c"; 1464 reg = <0 0x00a8c000 0 0x4000>; 1465 clock-names = "se"; 1466 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1467 pinctrl-names = "default"; 1468 pinctrl-0 = <&qup_i2c3_data_clk>; 1469 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1470 #address-cells = <1>; 1471 #size-cells = <0>; 1472 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1473 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1474 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1475 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1476 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1477 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1478 dma-names = "tx", "rx"; 1479 status = "disabled"; 1480 }; 1481 1482 spi3: spi@a8c000 { 1483 compatible = "qcom,geni-spi"; 1484 reg = <0 0x00a8c000 0 0x4000>; 1485 clock-names = "se"; 1486 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1487 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1488 pinctrl-names = "default"; 1489 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1490 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1491 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1492 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1493 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1494 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1495 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1496 dma-names = "tx", "rx"; 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 status = "disabled"; 1500 }; 1501 1502 i2c4: i2c@a90000 { 1503 compatible = "qcom,geni-i2c"; 1504 reg = <0 0x00a90000 0 0x4000>; 1505 clock-names = "se"; 1506 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1507 pinctrl-names = "default"; 1508 pinctrl-0 = <&qup_i2c4_data_clk>; 1509 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1510 #address-cells = <1>; 1511 #size-cells = <0>; 1512 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1513 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1514 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1515 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1516 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1517 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1518 dma-names = "tx", "rx"; 1519 status = "disabled"; 1520 }; 1521 1522 spi4: spi@a90000 { 1523 compatible = "qcom,geni-spi"; 1524 reg = <0 0x00a90000 0 0x4000>; 1525 clock-names = "se"; 1526 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1527 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1528 pinctrl-names = "default"; 1529 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1530 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1531 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1532 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1533 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1534 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1535 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1536 dma-names = "tx", "rx"; 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 status = "disabled"; 1540 }; 1541 1542 i2c5: i2c@a94000 { 1543 compatible = "qcom,geni-i2c"; 1544 reg = <0 0x00a94000 0 0x4000>; 1545 clock-names = "se"; 1546 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1547 pinctrl-names = "default"; 1548 pinctrl-0 = <&qup_i2c5_data_clk>; 1549 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1550 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1551 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1552 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1553 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1554 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1555 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1556 dma-names = "tx", "rx"; 1557 #address-cells = <1>; 1558 #size-cells = <0>; 1559 status = "disabled"; 1560 }; 1561 1562 spi5: spi@a94000 { 1563 compatible = "qcom,geni-spi"; 1564 reg = <0 0x00a94000 0 0x4000>; 1565 clock-names = "se"; 1566 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1567 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1568 pinctrl-names = "default"; 1569 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1570 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1571 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1572 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1573 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1574 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1575 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1576 dma-names = "tx", "rx"; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 status = "disabled"; 1580 }; 1581 1582 i2c6: i2c@a98000 { 1583 compatible = "qcom,geni-i2c"; 1584 reg = <0 0x00a98000 0 0x4000>; 1585 clock-names = "se"; 1586 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1587 pinctrl-names = "default"; 1588 pinctrl-0 = <&qup_i2c6_data_clk>; 1589 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1590 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1591 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1592 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1593 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1594 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1595 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1596 dma-names = "tx", "rx"; 1597 #address-cells = <1>; 1598 #size-cells = <0>; 1599 status = "disabled"; 1600 }; 1601 1602 spi6: spi@a98000 { 1603 compatible = "qcom,geni-spi"; 1604 reg = <0 0x00a98000 0 0x4000>; 1605 clock-names = "se"; 1606 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1607 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1608 pinctrl-names = "default"; 1609 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1610 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1611 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1612 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1613 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1614 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1615 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1616 dma-names = "tx", "rx"; 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 status = "disabled"; 1620 }; 1621 1622 uart7: serial@a9c000 { 1623 compatible = "qcom,geni-debug-uart"; 1624 reg = <0 0x00a9c000 0 0x4000>; 1625 clock-names = "se"; 1626 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1627 pinctrl-names = "default"; 1628 pinctrl-0 = <&qup_uart7_default>; 1629 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1630 interconnect-names = "qup-core", "qup-config"; 1631 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1632 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1633 status = "disabled"; 1634 }; 1635 }; 1636 1637 cnoc_main: interconnect@1500000 { 1638 compatible = "qcom,sm8550-cnoc-main"; 1639 reg = <0 0x01500000 0 0x13080>; 1640 #interconnect-cells = <2>; 1641 qcom,bcm-voters = <&apps_bcm_voter>; 1642 }; 1643 1644 config_noc: interconnect@1600000 { 1645 compatible = "qcom,sm8550-config-noc"; 1646 reg = <0 0x01600000 0 0x6200>; 1647 #interconnect-cells = <2>; 1648 qcom,bcm-voters = <&apps_bcm_voter>; 1649 }; 1650 1651 system_noc: interconnect@1680000 { 1652 compatible = "qcom,sm8550-system-noc"; 1653 reg = <0 0x01680000 0 0x1d080>; 1654 #interconnect-cells = <2>; 1655 qcom,bcm-voters = <&apps_bcm_voter>; 1656 }; 1657 1658 pcie_noc: interconnect@16c0000 { 1659 compatible = "qcom,sm8550-pcie-anoc"; 1660 reg = <0 0x016c0000 0 0x12200>; 1661 #interconnect-cells = <2>; 1662 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1663 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1664 qcom,bcm-voters = <&apps_bcm_voter>; 1665 }; 1666 1667 aggre1_noc: interconnect@16e0000 { 1668 compatible = "qcom,sm8550-aggre1-noc"; 1669 reg = <0 0x016e0000 0 0x14400>; 1670 #interconnect-cells = <2>; 1671 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1672 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1673 qcom,bcm-voters = <&apps_bcm_voter>; 1674 }; 1675 1676 aggre2_noc: interconnect@1700000 { 1677 compatible = "qcom,sm8550-aggre2-noc"; 1678 reg = <0 0x01700000 0 0x1e400>; 1679 #interconnect-cells = <2>; 1680 clocks = <&rpmhcc RPMH_IPA_CLK>; 1681 qcom,bcm-voters = <&apps_bcm_voter>; 1682 }; 1683 1684 mmss_noc: interconnect@1780000 { 1685 compatible = "qcom,sm8550-mmss-noc"; 1686 reg = <0 0x01780000 0 0x5b800>; 1687 #interconnect-cells = <2>; 1688 qcom,bcm-voters = <&apps_bcm_voter>; 1689 }; 1690 1691 rng: rng@10c3000 { 1692 compatible = "qcom,sm8550-trng", "qcom,trng"; 1693 reg = <0 0x010c3000 0 0x1000>; 1694 }; 1695 1696 pcie0: pcie@1c00000 { 1697 device_type = "pci"; 1698 compatible = "qcom,pcie-sm8550"; 1699 reg = <0 0x01c00000 0 0x3000>, 1700 <0 0x60000000 0 0xf1d>, 1701 <0 0x60000f20 0 0xa8>, 1702 <0 0x60001000 0 0x1000>, 1703 <0 0x60100000 0 0x100000>; 1704 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1705 #address-cells = <3>; 1706 #size-cells = <2>; 1707 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1708 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1709 bus-range = <0x00 0xff>; 1710 1711 dma-coherent; 1712 1713 linux,pci-domain = <0>; 1714 num-lanes = <2>; 1715 1716 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1718 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1719 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1720 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1724 interrupt-names = "msi0", 1725 "msi1", 1726 "msi2", 1727 "msi3", 1728 "msi4", 1729 "msi5", 1730 "msi6", 1731 "msi7"; 1732 #interrupt-cells = <1>; 1733 interrupt-map-mask = <0 0 0 0x7>; 1734 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1735 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1736 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1737 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1738 1739 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1740 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1741 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1742 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1743 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1744 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1745 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1746 clock-names = "aux", 1747 "cfg", 1748 "bus_master", 1749 "bus_slave", 1750 "slave_q2a", 1751 "ddrss_sf_tbu", 1752 "noc_aggr"; 1753 1754 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 1755 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; 1756 interconnect-names = "pcie-mem", "cpu-pcie"; 1757 1758 msi-map = <0x0 &gic_its 0x1400 0x1>, 1759 <0x100 &gic_its 0x1401 0x1>; 1760 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 1761 <0x100 &apps_smmu 0x1401 0x1>; 1762 1763 resets = <&gcc GCC_PCIE_0_BCR>; 1764 reset-names = "pci"; 1765 1766 power-domains = <&gcc PCIE_0_GDSC>; 1767 1768 phys = <&pcie0_phy>; 1769 phy-names = "pciephy"; 1770 1771 status = "disabled"; 1772 }; 1773 1774 pcie0_phy: phy@1c06000 { 1775 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 1776 reg = <0 0x01c06000 0 0x2000>; 1777 1778 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1779 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1780 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1781 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1782 <&gcc GCC_PCIE_0_PIPE_CLK>; 1783 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1784 "pipe"; 1785 1786 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1787 reset-names = "phy"; 1788 1789 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1790 assigned-clock-rates = <100000000>; 1791 1792 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1793 1794 #clock-cells = <0>; 1795 clock-output-names = "pcie0_pipe_clk"; 1796 1797 #phy-cells = <0>; 1798 1799 status = "disabled"; 1800 }; 1801 1802 pcie1: pcie@1c08000 { 1803 device_type = "pci"; 1804 compatible = "qcom,pcie-sm8550"; 1805 reg = <0x0 0x01c08000 0x0 0x3000>, 1806 <0x0 0x40000000 0x0 0xf1d>, 1807 <0x0 0x40000f20 0x0 0xa8>, 1808 <0x0 0x40001000 0x0 0x1000>, 1809 <0x0 0x40100000 0x0 0x100000>; 1810 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1811 #address-cells = <3>; 1812 #size-cells = <2>; 1813 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1814 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1815 bus-range = <0x00 0xff>; 1816 1817 dma-coherent; 1818 1819 linux,pci-domain = <1>; 1820 num-lanes = <2>; 1821 1822 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1830 interrupt-names = "msi0", 1831 "msi1", 1832 "msi2", 1833 "msi3", 1834 "msi4", 1835 "msi5", 1836 "msi6", 1837 "msi7"; 1838 #interrupt-cells = <1>; 1839 interrupt-map-mask = <0 0 0 0x7>; 1840 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1841 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1842 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1843 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1844 1845 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1846 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1847 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1848 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1849 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1850 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1851 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1852 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 1853 clock-names = "aux", 1854 "cfg", 1855 "bus_master", 1856 "bus_slave", 1857 "slave_q2a", 1858 "ddrss_sf_tbu", 1859 "noc_aggr", 1860 "cnoc_sf_axi"; 1861 1862 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1863 assigned-clock-rates = <19200000>; 1864 1865 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 1866 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; 1867 interconnect-names = "pcie-mem", "cpu-pcie"; 1868 1869 msi-map = <0x0 &gic_its 0x1480 0x1>, 1870 <0x100 &gic_its 0x1481 0x1>; 1871 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 1872 <0x100 &apps_smmu 0x1481 0x1>; 1873 1874 resets = <&gcc GCC_PCIE_1_BCR>, 1875 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1876 reset-names = "pci", "link_down"; 1877 1878 power-domains = <&gcc PCIE_1_GDSC>; 1879 1880 phys = <&pcie1_phy>; 1881 phy-names = "pciephy"; 1882 1883 status = "disabled"; 1884 }; 1885 1886 pcie1_phy: phy@1c0e000 { 1887 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 1888 reg = <0x0 0x01c0e000 0x0 0x2000>; 1889 1890 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1891 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1892 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1893 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1894 <&gcc GCC_PCIE_1_PIPE_CLK>; 1895 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1896 "pipe"; 1897 1898 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 1899 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 1900 reset-names = "phy", "phy_nocsr"; 1901 1902 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1903 assigned-clock-rates = <100000000>; 1904 1905 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1906 1907 #clock-cells = <0>; 1908 clock-output-names = "pcie1_pipe_clk"; 1909 1910 #phy-cells = <0>; 1911 1912 status = "disabled"; 1913 }; 1914 1915 cryptobam: dma-controller@1dc4000 { 1916 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1917 reg = <0x0 0x01dc4000 0x0 0x28000>; 1918 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1919 #dma-cells = <1>; 1920 qcom,ee = <0>; 1921 qcom,controlled-remotely; 1922 iommus = <&apps_smmu 0x480 0x0>, 1923 <&apps_smmu 0x481 0x0>; 1924 }; 1925 1926 crypto: crypto@1dfa000 { 1927 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 1928 reg = <0x0 0x01dfa000 0x0 0x6000>; 1929 dmas = <&cryptobam 4>, <&cryptobam 5>; 1930 dma-names = "rx", "tx"; 1931 iommus = <&apps_smmu 0x480 0x0>, 1932 <&apps_smmu 0x481 0x0>; 1933 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1934 interconnect-names = "memory"; 1935 }; 1936 1937 ufs_mem_phy: phy@1d80000 { 1938 compatible = "qcom,sm8550-qmp-ufs-phy"; 1939 reg = <0x0 0x01d80000 0x0 0x2000>; 1940 clocks = <&rpmhcc RPMH_CXO_CLK>, 1941 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1942 <&tcsr TCSR_UFS_CLKREF_EN>; 1943 clock-names = "ref", 1944 "ref_aux", 1945 "qref"; 1946 1947 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1948 1949 resets = <&ufs_mem_hc 0>; 1950 reset-names = "ufsphy"; 1951 1952 #clock-cells = <1>; 1953 #phy-cells = <0>; 1954 1955 status = "disabled"; 1956 }; 1957 1958 ufs_mem_hc: ufs@1d84000 { 1959 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 1960 "jedec,ufs-2.0"; 1961 reg = <0x0 0x01d84000 0x0 0x3000>; 1962 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1963 phys = <&ufs_mem_phy>; 1964 phy-names = "ufsphy"; 1965 lanes-per-direction = <2>; 1966 #reset-cells = <1>; 1967 resets = <&gcc GCC_UFS_PHY_BCR>; 1968 reset-names = "rst"; 1969 1970 power-domains = <&gcc UFS_PHY_GDSC>; 1971 required-opps = <&rpmhpd_opp_nom>; 1972 1973 iommus = <&apps_smmu 0x60 0x0>; 1974 dma-coherent; 1975 1976 operating-points-v2 = <&ufs_opp_table>; 1977 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 1978 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 1979 1980 interconnect-names = "ufs-ddr", "cpu-ufs"; 1981 clock-names = "core_clk", 1982 "bus_aggr_clk", 1983 "iface_clk", 1984 "core_clk_unipro", 1985 "ref_clk", 1986 "tx_lane0_sync_clk", 1987 "rx_lane0_sync_clk", 1988 "rx_lane1_sync_clk"; 1989 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1990 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1991 <&gcc GCC_UFS_PHY_AHB_CLK>, 1992 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1993 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 1994 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1995 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1996 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1997 qcom,ice = <&ice>; 1998 1999 status = "disabled"; 2000 2001 ufs_opp_table: opp-table { 2002 compatible = "operating-points-v2"; 2003 2004 opp-75000000 { 2005 opp-hz = /bits/ 64 <75000000>, 2006 /bits/ 64 <0>, 2007 /bits/ 64 <0>, 2008 /bits/ 64 <75000000>, 2009 /bits/ 64 <0>, 2010 /bits/ 64 <0>, 2011 /bits/ 64 <0>, 2012 /bits/ 64 <0>; 2013 required-opps = <&rpmhpd_opp_low_svs>; 2014 }; 2015 2016 opp-150000000 { 2017 opp-hz = /bits/ 64 <150000000>, 2018 /bits/ 64 <0>, 2019 /bits/ 64 <0>, 2020 /bits/ 64 <150000000>, 2021 /bits/ 64 <0>, 2022 /bits/ 64 <0>, 2023 /bits/ 64 <0>, 2024 /bits/ 64 <0>; 2025 required-opps = <&rpmhpd_opp_svs>; 2026 }; 2027 2028 opp-300000000 { 2029 opp-hz = /bits/ 64 <300000000>, 2030 /bits/ 64 <0>, 2031 /bits/ 64 <0>, 2032 /bits/ 64 <300000000>, 2033 /bits/ 64 <0>, 2034 /bits/ 64 <0>, 2035 /bits/ 64 <0>, 2036 /bits/ 64 <0>; 2037 required-opps = <&rpmhpd_opp_nom>; 2038 }; 2039 }; 2040 }; 2041 2042 ice: crypto@1d88000 { 2043 compatible = "qcom,sm8550-inline-crypto-engine", 2044 "qcom,inline-crypto-engine"; 2045 reg = <0 0x01d88000 0 0x8000>; 2046 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2047 }; 2048 2049 tcsr_mutex: hwlock@1f40000 { 2050 compatible = "qcom,tcsr-mutex"; 2051 reg = <0 0x01f40000 0 0x20000>; 2052 #hwlock-cells = <1>; 2053 }; 2054 2055 tcsr: clock-controller@1fc0000 { 2056 compatible = "qcom,sm8550-tcsr", "syscon"; 2057 reg = <0 0x01fc0000 0 0x30000>; 2058 clocks = <&rpmhcc RPMH_CXO_CLK>; 2059 #clock-cells = <1>; 2060 #reset-cells = <1>; 2061 }; 2062 2063 gpu: gpu@3d00000 { 2064 compatible = "qcom,adreno-43050a01", "qcom,adreno"; 2065 reg = <0x0 0x03d00000 0x0 0x40000>, 2066 <0x0 0x03d9e000 0x0 0x1000>, 2067 <0x0 0x03d61000 0x0 0x800>; 2068 reg-names = "kgsl_3d0_reg_memory", 2069 "cx_mem", 2070 "cx_dbgc"; 2071 2072 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2073 2074 iommus = <&adreno_smmu 0 0x0>, 2075 <&adreno_smmu 1 0x0>; 2076 2077 operating-points-v2 = <&gpu_opp_table>; 2078 2079 qcom,gmu = <&gmu>; 2080 #cooling-cells = <2>; 2081 2082 status = "disabled"; 2083 2084 zap-shader { 2085 memory-region = <&gpu_micro_code_mem>; 2086 }; 2087 2088 /* Speedbin needs more work on A740+, keep only lower freqs */ 2089 gpu_opp_table: opp-table { 2090 compatible = "operating-points-v2"; 2091 2092 opp-680000000 { 2093 opp-hz = /bits/ 64 <680000000>; 2094 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2095 }; 2096 2097 opp-615000000 { 2098 opp-hz = /bits/ 64 <615000000>; 2099 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2100 }; 2101 2102 opp-550000000 { 2103 opp-hz = /bits/ 64 <550000000>; 2104 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2105 }; 2106 2107 opp-475000000 { 2108 opp-hz = /bits/ 64 <475000000>; 2109 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2110 }; 2111 2112 opp-401000000 { 2113 opp-hz = /bits/ 64 <401000000>; 2114 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2115 }; 2116 2117 opp-348000000 { 2118 opp-hz = /bits/ 64 <348000000>; 2119 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 2120 }; 2121 2122 opp-295000000 { 2123 opp-hz = /bits/ 64 <295000000>; 2124 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2125 }; 2126 2127 opp-220000000 { 2128 opp-hz = /bits/ 64 <220000000>; 2129 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 2130 }; 2131 }; 2132 }; 2133 2134 gmu: gmu@3d6a000 { 2135 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu"; 2136 reg = <0x0 0x03d6a000 0x0 0x35000>, 2137 <0x0 0x03d50000 0x0 0x10000>, 2138 <0x0 0x0b280000 0x0 0x10000>; 2139 reg-names = "gmu", "rscc", "gmu_pdc"; 2140 2141 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2143 interrupt-names = "hfi", "gmu"; 2144 2145 clocks = <&gpucc GPU_CC_AHB_CLK>, 2146 <&gpucc GPU_CC_CX_GMU_CLK>, 2147 <&gpucc GPU_CC_CXO_CLK>, 2148 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2149 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2150 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2151 <&gpucc GPU_CC_DEMET_CLK>; 2152 clock-names = "ahb", 2153 "gmu", 2154 "cxo", 2155 "axi", 2156 "memnoc", 2157 "hub", 2158 "demet"; 2159 2160 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2161 <&gpucc GPU_CC_GX_GDSC>; 2162 power-domain-names = "cx", 2163 "gx"; 2164 2165 iommus = <&adreno_smmu 5 0x0>; 2166 2167 qcom,qmp = <&aoss_qmp>; 2168 2169 operating-points-v2 = <&gmu_opp_table>; 2170 2171 gmu_opp_table: opp-table { 2172 compatible = "operating-points-v2"; 2173 2174 opp-500000000 { 2175 opp-hz = /bits/ 64 <500000000>; 2176 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2177 }; 2178 2179 opp-200000000 { 2180 opp-hz = /bits/ 64 <200000000>; 2181 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2182 }; 2183 }; 2184 }; 2185 2186 gpucc: clock-controller@3d90000 { 2187 compatible = "qcom,sm8550-gpucc"; 2188 reg = <0 0x03d90000 0 0xa000>; 2189 clocks = <&bi_tcxo_div2>, 2190 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2191 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2192 #clock-cells = <1>; 2193 #reset-cells = <1>; 2194 #power-domain-cells = <1>; 2195 }; 2196 2197 adreno_smmu: iommu@3da0000 { 2198 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", 2199 "qcom,smmu-500", "arm,mmu-500"; 2200 reg = <0x0 0x03da0000 0x0 0x40000>; 2201 #iommu-cells = <2>; 2202 #global-interrupts = <1>; 2203 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>, 2205 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2206 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2207 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2208 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2209 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2210 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2211 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2212 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2214 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2215 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2219 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2221 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2223 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2228 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 2229 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2230 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2231 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2232 <&gpucc GPU_CC_AHB_CLK>; 2233 clock-names = "hlos", 2234 "bus", 2235 "iface", 2236 "ahb"; 2237 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2238 dma-coherent; 2239 }; 2240 2241 ipa: ipa@3f40000 { 2242 compatible = "qcom,sm8550-ipa"; 2243 2244 iommus = <&apps_smmu 0x4a0 0x0>, 2245 <&apps_smmu 0x4a2 0x0>; 2246 reg = <0 0x3f40000 0 0x10000>, 2247 <0 0x3f50000 0 0x5000>, 2248 <0 0x3e04000 0 0xfc000>; 2249 reg-names = "ipa-reg", 2250 "ipa-shared", 2251 "gsi"; 2252 2253 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2254 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2255 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2256 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2257 interrupt-names = "ipa", 2258 "gsi", 2259 "ipa-clock-query", 2260 "ipa-setup-ready"; 2261 2262 clocks = <&rpmhcc RPMH_IPA_CLK>; 2263 clock-names = "core"; 2264 2265 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2266 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2267 interconnect-names = "memory", 2268 "config"; 2269 2270 qcom,qmp = <&aoss_qmp>; 2271 2272 qcom,smem-states = <&ipa_smp2p_out 0>, 2273 <&ipa_smp2p_out 1>; 2274 qcom,smem-state-names = "ipa-clock-enabled-valid", 2275 "ipa-clock-enabled"; 2276 2277 status = "disabled"; 2278 }; 2279 2280 remoteproc_mpss: remoteproc@4080000 { 2281 compatible = "qcom,sm8550-mpss-pas"; 2282 reg = <0x0 0x04080000 0x0 0x4040>; 2283 2284 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2285 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2286 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2287 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2288 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2289 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2290 interrupt-names = "wdog", "fatal", "ready", "handover", 2291 "stop-ack", "shutdown-ack"; 2292 2293 clocks = <&rpmhcc RPMH_CXO_CLK>; 2294 clock-names = "xo"; 2295 2296 power-domains = <&rpmhpd RPMHPD_CX>, 2297 <&rpmhpd RPMHPD_MSS>; 2298 power-domain-names = "cx", "mss"; 2299 2300 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2301 2302 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 2303 2304 qcom,qmp = <&aoss_qmp>; 2305 2306 qcom,smem-states = <&smp2p_modem_out 0>; 2307 qcom,smem-state-names = "stop"; 2308 2309 status = "disabled"; 2310 2311 glink-edge { 2312 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2313 IPCC_MPROC_SIGNAL_GLINK_QMP 2314 IRQ_TYPE_EDGE_RISING>; 2315 mboxes = <&ipcc IPCC_CLIENT_MPSS 2316 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2317 label = "mpss"; 2318 qcom,remote-pid = <1>; 2319 }; 2320 }; 2321 2322 lpass_wsa2macro: codec@6aa0000 { 2323 compatible = "qcom,sm8550-lpass-wsa-macro"; 2324 reg = <0 0x06aa0000 0 0x1000>; 2325 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2326 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2327 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2328 <&lpass_vamacro>; 2329 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2330 2331 #clock-cells = <0>; 2332 clock-output-names = "wsa2-mclk"; 2333 #sound-dai-cells = <1>; 2334 }; 2335 2336 swr3: soundwire@6ab0000 { 2337 compatible = "qcom,soundwire-v2.0.0"; 2338 reg = <0 0x06ab0000 0 0x10000>; 2339 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2340 clocks = <&lpass_wsa2macro>; 2341 clock-names = "iface"; 2342 label = "WSA2"; 2343 2344 pinctrl-0 = <&wsa2_swr_active>; 2345 pinctrl-names = "default"; 2346 2347 qcom,din-ports = <4>; 2348 qcom,dout-ports = <9>; 2349 2350 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2351 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2352 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2353 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2354 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2355 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2356 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2357 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2358 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2359 2360 #address-cells = <2>; 2361 #size-cells = <0>; 2362 #sound-dai-cells = <1>; 2363 status = "disabled"; 2364 }; 2365 2366 lpass_rxmacro: codec@6ac0000 { 2367 compatible = "qcom,sm8550-lpass-rx-macro"; 2368 reg = <0 0x06ac0000 0 0x1000>; 2369 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2370 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2371 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2372 <&lpass_vamacro>; 2373 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2374 2375 #clock-cells = <0>; 2376 clock-output-names = "mclk"; 2377 #sound-dai-cells = <1>; 2378 }; 2379 2380 swr1: soundwire@6ad0000 { 2381 compatible = "qcom,soundwire-v2.0.0"; 2382 reg = <0 0x06ad0000 0 0x10000>; 2383 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2384 clocks = <&lpass_rxmacro>; 2385 clock-names = "iface"; 2386 label = "RX"; 2387 2388 pinctrl-0 = <&rx_swr_active>; 2389 pinctrl-names = "default"; 2390 2391 qcom,din-ports = <1>; 2392 qcom,dout-ports = <11>; 2393 2394 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>; 2395 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2396 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2397 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2398 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2399 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>; 2400 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2401 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2402 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2403 2404 #address-cells = <2>; 2405 #size-cells = <0>; 2406 #sound-dai-cells = <1>; 2407 status = "disabled"; 2408 }; 2409 2410 lpass_txmacro: codec@6ae0000 { 2411 compatible = "qcom,sm8550-lpass-tx-macro"; 2412 reg = <0 0x06ae0000 0 0x1000>; 2413 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2414 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2415 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2416 <&lpass_vamacro>; 2417 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2418 2419 #clock-cells = <0>; 2420 clock-output-names = "mclk"; 2421 #sound-dai-cells = <1>; 2422 }; 2423 2424 lpass_wsamacro: codec@6b00000 { 2425 compatible = "qcom,sm8550-lpass-wsa-macro"; 2426 reg = <0 0x06b00000 0 0x1000>; 2427 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2428 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2429 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2430 <&lpass_vamacro>; 2431 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2432 2433 #clock-cells = <0>; 2434 clock-output-names = "mclk"; 2435 #sound-dai-cells = <1>; 2436 }; 2437 2438 swr0: soundwire@6b10000 { 2439 compatible = "qcom,soundwire-v2.0.0"; 2440 reg = <0 0x06b10000 0 0x10000>; 2441 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2442 clocks = <&lpass_wsamacro>; 2443 clock-names = "iface"; 2444 label = "WSA"; 2445 2446 pinctrl-0 = <&wsa_swr_active>; 2447 pinctrl-names = "default"; 2448 2449 qcom,din-ports = <4>; 2450 qcom,dout-ports = <9>; 2451 2452 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2453 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2454 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2455 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2456 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2457 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2458 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2459 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2460 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2461 2462 #address-cells = <2>; 2463 #size-cells = <0>; 2464 #sound-dai-cells = <1>; 2465 status = "disabled"; 2466 }; 2467 2468 swr2: soundwire@6d30000 { 2469 compatible = "qcom,soundwire-v2.0.0"; 2470 reg = <0 0x06d30000 0 0x10000>; 2471 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2473 interrupt-names = "core", "wakeup"; 2474 clocks = <&lpass_txmacro>; 2475 clock-names = "iface"; 2476 label = "TX"; 2477 2478 pinctrl-0 = <&tx_swr_active>; 2479 pinctrl-names = "default"; 2480 2481 qcom,din-ports = <4>; 2482 qcom,dout-ports = <0>; 2483 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2484 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2485 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2486 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2487 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2488 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2489 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2490 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2491 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2492 2493 #address-cells = <2>; 2494 #size-cells = <0>; 2495 #sound-dai-cells = <1>; 2496 status = "disabled"; 2497 }; 2498 2499 lpass_vamacro: codec@6d44000 { 2500 compatible = "qcom,sm8550-lpass-va-macro"; 2501 reg = <0 0x06d44000 0 0x1000>; 2502 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2503 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2504 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2505 clock-names = "mclk", "macro", "dcodec"; 2506 2507 #clock-cells = <0>; 2508 clock-output-names = "fsgen"; 2509 #sound-dai-cells = <1>; 2510 }; 2511 2512 lpass_tlmm: pinctrl@6e80000 { 2513 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 2514 reg = <0 0x06e80000 0 0x20000>, 2515 <0 0x07250000 0 0x10000>; 2516 gpio-controller; 2517 #gpio-cells = <2>; 2518 gpio-ranges = <&lpass_tlmm 0 0 23>; 2519 2520 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2521 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2522 clock-names = "core", "audio"; 2523 2524 tx_swr_active: tx-swr-active-state { 2525 clk-pins { 2526 pins = "gpio0"; 2527 function = "swr_tx_clk"; 2528 drive-strength = <2>; 2529 slew-rate = <1>; 2530 bias-disable; 2531 }; 2532 2533 data-pins { 2534 pins = "gpio1", "gpio2", "gpio14"; 2535 function = "swr_tx_data"; 2536 drive-strength = <2>; 2537 slew-rate = <1>; 2538 bias-bus-hold; 2539 }; 2540 }; 2541 2542 rx_swr_active: rx-swr-active-state { 2543 clk-pins { 2544 pins = "gpio3"; 2545 function = "swr_rx_clk"; 2546 drive-strength = <2>; 2547 slew-rate = <1>; 2548 bias-disable; 2549 }; 2550 2551 data-pins { 2552 pins = "gpio4", "gpio5"; 2553 function = "swr_rx_data"; 2554 drive-strength = <2>; 2555 slew-rate = <1>; 2556 bias-bus-hold; 2557 }; 2558 }; 2559 2560 dmic01_default: dmic01-default-state { 2561 clk-pins { 2562 pins = "gpio6"; 2563 function = "dmic1_clk"; 2564 drive-strength = <8>; 2565 output-high; 2566 }; 2567 2568 data-pins { 2569 pins = "gpio7"; 2570 function = "dmic1_data"; 2571 drive-strength = <8>; 2572 input-enable; 2573 }; 2574 }; 2575 2576 dmic23_default: dmic23-default-state { 2577 clk-pins { 2578 pins = "gpio8"; 2579 function = "dmic2_clk"; 2580 drive-strength = <8>; 2581 output-high; 2582 }; 2583 2584 data-pins { 2585 pins = "gpio9"; 2586 function = "dmic2_data"; 2587 drive-strength = <8>; 2588 input-enable; 2589 }; 2590 }; 2591 2592 wsa_swr_active: wsa-swr-active-state { 2593 clk-pins { 2594 pins = "gpio10"; 2595 function = "wsa_swr_clk"; 2596 drive-strength = <2>; 2597 slew-rate = <1>; 2598 bias-disable; 2599 }; 2600 2601 data-pins { 2602 pins = "gpio11"; 2603 function = "wsa_swr_data"; 2604 drive-strength = <2>; 2605 slew-rate = <1>; 2606 bias-bus-hold; 2607 }; 2608 }; 2609 2610 wsa2_swr_active: wsa2-swr-active-state { 2611 clk-pins { 2612 pins = "gpio15"; 2613 function = "wsa2_swr_clk"; 2614 drive-strength = <2>; 2615 slew-rate = <1>; 2616 bias-disable; 2617 }; 2618 2619 data-pins { 2620 pins = "gpio16"; 2621 function = "wsa2_swr_data"; 2622 drive-strength = <2>; 2623 slew-rate = <1>; 2624 bias-bus-hold; 2625 }; 2626 }; 2627 }; 2628 2629 lpass_lpiaon_noc: interconnect@7400000 { 2630 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 2631 reg = <0 0x07400000 0 0x19080>; 2632 #interconnect-cells = <2>; 2633 qcom,bcm-voters = <&apps_bcm_voter>; 2634 }; 2635 2636 lpass_lpicx_noc: interconnect@7430000 { 2637 compatible = "qcom,sm8550-lpass-lpicx-noc"; 2638 reg = <0 0x07430000 0 0x3a200>; 2639 #interconnect-cells = <2>; 2640 qcom,bcm-voters = <&apps_bcm_voter>; 2641 }; 2642 2643 lpass_ag_noc: interconnect@7e40000 { 2644 compatible = "qcom,sm8550-lpass-ag-noc"; 2645 reg = <0 0x07e40000 0 0xe080>; 2646 #interconnect-cells = <2>; 2647 qcom,bcm-voters = <&apps_bcm_voter>; 2648 }; 2649 2650 sdhc_2: mmc@8804000 { 2651 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 2652 reg = <0 0x08804000 0 0x1000>; 2653 2654 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2655 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2656 interrupt-names = "hc_irq", "pwr_irq"; 2657 2658 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2659 <&gcc GCC_SDCC2_APPS_CLK>, 2660 <&rpmhcc RPMH_CXO_CLK>; 2661 clock-names = "iface", "core", "xo"; 2662 iommus = <&apps_smmu 0x540 0>; 2663 qcom,dll-config = <0x0007642c>; 2664 qcom,ddr-config = <0x80040868>; 2665 power-domains = <&rpmhpd RPMHPD_CX>; 2666 operating-points-v2 = <&sdhc2_opp_table>; 2667 2668 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2669 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2670 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 2671 bus-width = <4>; 2672 dma-coherent; 2673 2674 /* Forbid SDR104/SDR50 - broken hw! */ 2675 sdhci-caps-mask = <0x3 0>; 2676 2677 status = "disabled"; 2678 2679 sdhc2_opp_table: opp-table { 2680 compatible = "operating-points-v2"; 2681 2682 opp-19200000 { 2683 opp-hz = /bits/ 64 <19200000>; 2684 required-opps = <&rpmhpd_opp_min_svs>; 2685 }; 2686 2687 opp-50000000 { 2688 opp-hz = /bits/ 64 <50000000>; 2689 required-opps = <&rpmhpd_opp_low_svs>; 2690 }; 2691 2692 opp-100000000 { 2693 opp-hz = /bits/ 64 <100000000>; 2694 required-opps = <&rpmhpd_opp_svs>; 2695 }; 2696 2697 opp-202000000 { 2698 opp-hz = /bits/ 64 <202000000>; 2699 required-opps = <&rpmhpd_opp_svs_l1>; 2700 }; 2701 }; 2702 }; 2703 2704 videocc: clock-controller@aaf0000 { 2705 compatible = "qcom,sm8550-videocc"; 2706 reg = <0 0x0aaf0000 0 0x10000>; 2707 clocks = <&bi_tcxo_div2>, 2708 <&gcc GCC_VIDEO_AHB_CLK>; 2709 power-domains = <&rpmhpd RPMHPD_MMCX>; 2710 required-opps = <&rpmhpd_opp_low_svs>; 2711 #clock-cells = <1>; 2712 #reset-cells = <1>; 2713 #power-domain-cells = <1>; 2714 }; 2715 2716 camcc: clock-controller@ade0000 { 2717 compatible = "qcom,sm8550-camcc"; 2718 reg = <0 0x0ade0000 0 0x20000>; 2719 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2720 <&bi_tcxo_div2>, 2721 <&bi_tcxo_ao_div2>, 2722 <&sleep_clk>; 2723 power-domains = <&rpmhpd SM8550_MMCX>; 2724 required-opps = <&rpmhpd_opp_low_svs>; 2725 #clock-cells = <1>; 2726 #reset-cells = <1>; 2727 #power-domain-cells = <1>; 2728 }; 2729 2730 mdss: display-subsystem@ae00000 { 2731 compatible = "qcom,sm8550-mdss"; 2732 reg = <0 0x0ae00000 0 0x1000>; 2733 reg-names = "mdss"; 2734 2735 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2736 interrupt-controller; 2737 #interrupt-cells = <1>; 2738 2739 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2740 <&gcc GCC_DISP_AHB_CLK>, 2741 <&gcc GCC_DISP_HF_AXI_CLK>, 2742 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2743 2744 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2745 2746 power-domains = <&dispcc MDSS_GDSC>; 2747 2748 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, 2749 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2750 interconnect-names = "mdp0-mem", "mdp1-mem"; 2751 2752 iommus = <&apps_smmu 0x1c00 0x2>; 2753 2754 #address-cells = <2>; 2755 #size-cells = <2>; 2756 ranges; 2757 2758 status = "disabled"; 2759 2760 mdss_mdp: display-controller@ae01000 { 2761 compatible = "qcom,sm8550-dpu"; 2762 reg = <0 0x0ae01000 0 0x8f000>, 2763 <0 0x0aeb0000 0 0x2008>; 2764 reg-names = "mdp", "vbif"; 2765 2766 interrupt-parent = <&mdss>; 2767 interrupts = <0>; 2768 2769 clocks = <&gcc GCC_DISP_AHB_CLK>, 2770 <&gcc GCC_DISP_HF_AXI_CLK>, 2771 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2772 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2773 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2774 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2775 clock-names = "bus", 2776 "nrt_bus", 2777 "iface", 2778 "lut", 2779 "core", 2780 "vsync"; 2781 2782 power-domains = <&rpmhpd RPMHPD_MMCX>; 2783 2784 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2785 assigned-clock-rates = <19200000>; 2786 2787 operating-points-v2 = <&mdp_opp_table>; 2788 2789 ports { 2790 #address-cells = <1>; 2791 #size-cells = <0>; 2792 2793 port@0 { 2794 reg = <0>; 2795 dpu_intf1_out: endpoint { 2796 remote-endpoint = <&mdss_dsi0_in>; 2797 }; 2798 }; 2799 2800 port@1 { 2801 reg = <1>; 2802 dpu_intf2_out: endpoint { 2803 remote-endpoint = <&mdss_dsi1_in>; 2804 }; 2805 }; 2806 2807 port@2 { 2808 reg = <2>; 2809 dpu_intf0_out: endpoint { 2810 remote-endpoint = <&mdss_dp0_in>; 2811 }; 2812 }; 2813 }; 2814 2815 mdp_opp_table: opp-table { 2816 compatible = "operating-points-v2"; 2817 2818 opp-200000000 { 2819 opp-hz = /bits/ 64 <200000000>; 2820 required-opps = <&rpmhpd_opp_low_svs>; 2821 }; 2822 2823 opp-325000000 { 2824 opp-hz = /bits/ 64 <325000000>; 2825 required-opps = <&rpmhpd_opp_svs>; 2826 }; 2827 2828 opp-375000000 { 2829 opp-hz = /bits/ 64 <375000000>; 2830 required-opps = <&rpmhpd_opp_svs_l1>; 2831 }; 2832 2833 opp-514000000 { 2834 opp-hz = /bits/ 64 <514000000>; 2835 required-opps = <&rpmhpd_opp_nom>; 2836 }; 2837 }; 2838 }; 2839 2840 mdss_dp0: displayport-controller@ae90000 { 2841 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 2842 reg = <0 0xae90000 0 0x200>, 2843 <0 0xae90200 0 0x200>, 2844 <0 0xae90400 0 0xc00>, 2845 <0 0xae91000 0 0x400>, 2846 <0 0xae91400 0 0x400>; 2847 interrupt-parent = <&mdss>; 2848 interrupts = <12>; 2849 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2850 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2851 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2852 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2853 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2854 clock-names = "core_iface", 2855 "core_aux", 2856 "ctrl_link", 2857 "ctrl_link_iface", 2858 "stream_pixel"; 2859 2860 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2861 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2862 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2863 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2864 2865 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 2866 phy-names = "dp"; 2867 2868 #sound-dai-cells = <0>; 2869 2870 operating-points-v2 = <&dp_opp_table>; 2871 power-domains = <&rpmhpd RPMHPD_MMCX>; 2872 2873 status = "disabled"; 2874 2875 ports { 2876 #address-cells = <1>; 2877 #size-cells = <0>; 2878 2879 port@0 { 2880 reg = <0>; 2881 mdss_dp0_in: endpoint { 2882 remote-endpoint = <&dpu_intf0_out>; 2883 }; 2884 }; 2885 2886 port@1 { 2887 reg = <1>; 2888 mdss_dp0_out: endpoint { 2889 }; 2890 }; 2891 }; 2892 2893 dp_opp_table: opp-table { 2894 compatible = "operating-points-v2"; 2895 2896 opp-162000000 { 2897 opp-hz = /bits/ 64 <162000000>; 2898 required-opps = <&rpmhpd_opp_low_svs_d1>; 2899 }; 2900 2901 opp-270000000 { 2902 opp-hz = /bits/ 64 <270000000>; 2903 required-opps = <&rpmhpd_opp_low_svs>; 2904 }; 2905 2906 opp-540000000 { 2907 opp-hz = /bits/ 64 <540000000>; 2908 required-opps = <&rpmhpd_opp_svs_l1>; 2909 }; 2910 2911 opp-810000000 { 2912 opp-hz = /bits/ 64 <810000000>; 2913 required-opps = <&rpmhpd_opp_nom>; 2914 }; 2915 }; 2916 }; 2917 2918 mdss_dsi0: dsi@ae94000 { 2919 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2920 reg = <0 0x0ae94000 0 0x400>; 2921 reg-names = "dsi_ctrl"; 2922 2923 interrupt-parent = <&mdss>; 2924 interrupts = <4>; 2925 2926 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2927 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2928 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2929 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2930 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2931 <&gcc GCC_DISP_HF_AXI_CLK>; 2932 clock-names = "byte", 2933 "byte_intf", 2934 "pixel", 2935 "core", 2936 "iface", 2937 "bus"; 2938 2939 power-domains = <&rpmhpd RPMHPD_MMCX>; 2940 2941 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2942 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2943 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2944 <&mdss_dsi0_phy 1>; 2945 2946 operating-points-v2 = <&mdss_dsi_opp_table>; 2947 2948 phys = <&mdss_dsi0_phy>; 2949 phy-names = "dsi"; 2950 2951 #address-cells = <1>; 2952 #size-cells = <0>; 2953 2954 status = "disabled"; 2955 2956 ports { 2957 #address-cells = <1>; 2958 #size-cells = <0>; 2959 2960 port@0 { 2961 reg = <0>; 2962 mdss_dsi0_in: endpoint { 2963 remote-endpoint = <&dpu_intf1_out>; 2964 }; 2965 }; 2966 2967 port@1 { 2968 reg = <1>; 2969 mdss_dsi0_out: endpoint { 2970 }; 2971 }; 2972 }; 2973 2974 mdss_dsi_opp_table: opp-table { 2975 compatible = "operating-points-v2"; 2976 2977 opp-187500000 { 2978 opp-hz = /bits/ 64 <187500000>; 2979 required-opps = <&rpmhpd_opp_low_svs>; 2980 }; 2981 2982 opp-300000000 { 2983 opp-hz = /bits/ 64 <300000000>; 2984 required-opps = <&rpmhpd_opp_svs>; 2985 }; 2986 2987 opp-358000000 { 2988 opp-hz = /bits/ 64 <358000000>; 2989 required-opps = <&rpmhpd_opp_svs_l1>; 2990 }; 2991 }; 2992 }; 2993 2994 mdss_dsi0_phy: phy@ae95000 { 2995 compatible = "qcom,sm8550-dsi-phy-4nm"; 2996 reg = <0 0x0ae95000 0 0x200>, 2997 <0 0x0ae95200 0 0x280>, 2998 <0 0x0ae95500 0 0x400>; 2999 reg-names = "dsi_phy", 3000 "dsi_phy_lane", 3001 "dsi_pll"; 3002 3003 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3004 <&rpmhcc RPMH_CXO_CLK>; 3005 clock-names = "iface", "ref"; 3006 3007 #clock-cells = <1>; 3008 #phy-cells = <0>; 3009 3010 status = "disabled"; 3011 }; 3012 3013 mdss_dsi1: dsi@ae96000 { 3014 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3015 reg = <0 0x0ae96000 0 0x400>; 3016 reg-names = "dsi_ctrl"; 3017 3018 interrupt-parent = <&mdss>; 3019 interrupts = <5>; 3020 3021 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3022 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3023 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3024 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3025 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3026 <&gcc GCC_DISP_HF_AXI_CLK>; 3027 clock-names = "byte", 3028 "byte_intf", 3029 "pixel", 3030 "core", 3031 "iface", 3032 "bus"; 3033 3034 power-domains = <&rpmhpd RPMHPD_MMCX>; 3035 3036 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3037 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3038 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3039 <&mdss_dsi1_phy 1>; 3040 3041 operating-points-v2 = <&mdss_dsi_opp_table>; 3042 3043 phys = <&mdss_dsi1_phy>; 3044 phy-names = "dsi"; 3045 3046 #address-cells = <1>; 3047 #size-cells = <0>; 3048 3049 status = "disabled"; 3050 3051 ports { 3052 #address-cells = <1>; 3053 #size-cells = <0>; 3054 3055 port@0 { 3056 reg = <0>; 3057 mdss_dsi1_in: endpoint { 3058 remote-endpoint = <&dpu_intf2_out>; 3059 }; 3060 }; 3061 3062 port@1 { 3063 reg = <1>; 3064 mdss_dsi1_out: endpoint { 3065 }; 3066 }; 3067 }; 3068 }; 3069 3070 mdss_dsi1_phy: phy@ae97000 { 3071 compatible = "qcom,sm8550-dsi-phy-4nm"; 3072 reg = <0 0x0ae97000 0 0x200>, 3073 <0 0x0ae97200 0 0x280>, 3074 <0 0x0ae97500 0 0x400>; 3075 reg-names = "dsi_phy", 3076 "dsi_phy_lane", 3077 "dsi_pll"; 3078 3079 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3080 <&rpmhcc RPMH_CXO_CLK>; 3081 clock-names = "iface", "ref"; 3082 3083 #clock-cells = <1>; 3084 #phy-cells = <0>; 3085 3086 status = "disabled"; 3087 }; 3088 }; 3089 3090 dispcc: clock-controller@af00000 { 3091 compatible = "qcom,sm8550-dispcc"; 3092 reg = <0 0x0af00000 0 0x20000>; 3093 clocks = <&bi_tcxo_div2>, 3094 <&bi_tcxo_ao_div2>, 3095 <&gcc GCC_DISP_AHB_CLK>, 3096 <&sleep_clk>, 3097 <&mdss_dsi0_phy 0>, 3098 <&mdss_dsi0_phy 1>, 3099 <&mdss_dsi1_phy 0>, 3100 <&mdss_dsi1_phy 1>, 3101 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3102 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3103 <0>, /* dp1 */ 3104 <0>, 3105 <0>, /* dp2 */ 3106 <0>, 3107 <0>, /* dp3 */ 3108 <0>; 3109 power-domains = <&rpmhpd RPMHPD_MMCX>; 3110 required-opps = <&rpmhpd_opp_low_svs>; 3111 #clock-cells = <1>; 3112 #reset-cells = <1>; 3113 #power-domain-cells = <1>; 3114 }; 3115 3116 usb_1_hsphy: phy@88e3000 { 3117 compatible = "qcom,sm8550-snps-eusb2-phy"; 3118 reg = <0x0 0x088e3000 0x0 0x154>; 3119 #phy-cells = <0>; 3120 3121 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 3122 clock-names = "ref"; 3123 3124 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3125 3126 status = "disabled"; 3127 }; 3128 3129 usb_dp_qmpphy: phy@88e8000 { 3130 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 3131 reg = <0x0 0x088e8000 0x0 0x3000>; 3132 3133 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3134 <&rpmhcc RPMH_CXO_CLK>, 3135 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3136 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3137 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3138 3139 power-domains = <&gcc USB3_PHY_GDSC>; 3140 3141 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3142 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 3143 reset-names = "phy", "common"; 3144 3145 #clock-cells = <1>; 3146 #phy-cells = <1>; 3147 3148 status = "disabled"; 3149 3150 ports { 3151 #address-cells = <1>; 3152 #size-cells = <0>; 3153 3154 port@0 { 3155 reg = <0>; 3156 3157 usb_dp_qmpphy_out: endpoint { 3158 }; 3159 }; 3160 3161 port@1 { 3162 reg = <1>; 3163 3164 usb_dp_qmpphy_usb_ss_in: endpoint { 3165 }; 3166 }; 3167 3168 port@2 { 3169 reg = <2>; 3170 3171 usb_dp_qmpphy_dp_in: endpoint { 3172 }; 3173 }; 3174 }; 3175 }; 3176 3177 usb_1: usb@a6f8800 { 3178 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 3179 reg = <0x0 0x0a6f8800 0x0 0x400>; 3180 #address-cells = <2>; 3181 #size-cells = <2>; 3182 ranges; 3183 3184 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3185 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3186 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3187 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3188 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3189 <&tcsr TCSR_USB3_CLKREF_EN>; 3190 clock-names = "cfg_noc", 3191 "core", 3192 "iface", 3193 "sleep", 3194 "mock_utmi", 3195 "xo"; 3196 3197 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3198 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3199 assigned-clock-rates = <19200000>, <200000000>; 3200 3201 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3202 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3203 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3204 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3205 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3206 interrupt-names = "pwr_event", 3207 "hs_phy_irq", 3208 "dp_hs_phy_irq", 3209 "dm_hs_phy_irq", 3210 "ss_phy_irq"; 3211 3212 power-domains = <&gcc USB30_PRIM_GDSC>; 3213 required-opps = <&rpmhpd_opp_nom>; 3214 3215 resets = <&gcc GCC_USB30_PRIM_BCR>; 3216 3217 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3218 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3219 interconnect-names = "usb-ddr", "apps-usb"; 3220 3221 status = "disabled"; 3222 3223 usb_1_dwc3: usb@a600000 { 3224 compatible = "snps,dwc3"; 3225 reg = <0x0 0x0a600000 0x0 0xcd00>; 3226 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3227 iommus = <&apps_smmu 0x40 0x0>; 3228 snps,dis_u2_susphy_quirk; 3229 snps,dis_enblslpm_quirk; 3230 snps,usb3_lpm_capable; 3231 phys = <&usb_1_hsphy>, 3232 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 3233 phy-names = "usb2-phy", "usb3-phy"; 3234 3235 ports { 3236 #address-cells = <1>; 3237 #size-cells = <0>; 3238 3239 port@0 { 3240 reg = <0>; 3241 3242 usb_1_dwc3_hs: endpoint { 3243 }; 3244 }; 3245 3246 port@1 { 3247 reg = <1>; 3248 3249 usb_1_dwc3_ss: endpoint { 3250 }; 3251 }; 3252 }; 3253 }; 3254 }; 3255 3256 pdc: interrupt-controller@b220000 { 3257 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 3258 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3259 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3260 <125 63 1>, <126 716 12>, 3261 <138 251 5>; 3262 #interrupt-cells = <2>; 3263 interrupt-parent = <&intc>; 3264 interrupt-controller; 3265 }; 3266 3267 tsens0: thermal-sensor@c271000 { 3268 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3269 reg = <0 0x0c271000 0 0x1000>, /* TM */ 3270 <0 0x0c222000 0 0x1000>; /* SROT */ 3271 #qcom,sensors = <16>; 3272 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 3274 interrupt-names = "uplow", "critical"; 3275 #thermal-sensor-cells = <1>; 3276 }; 3277 3278 tsens1: thermal-sensor@c272000 { 3279 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3280 reg = <0 0x0c272000 0 0x1000>, /* TM */ 3281 <0 0x0c223000 0 0x1000>; /* SROT */ 3282 #qcom,sensors = <16>; 3283 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 3285 interrupt-names = "uplow", "critical"; 3286 #thermal-sensor-cells = <1>; 3287 }; 3288 3289 tsens2: thermal-sensor@c273000 { 3290 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3291 reg = <0 0x0c273000 0 0x1000>, /* TM */ 3292 <0 0x0c224000 0 0x1000>; /* SROT */ 3293 #qcom,sensors = <16>; 3294 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 3296 interrupt-names = "uplow", "critical"; 3297 #thermal-sensor-cells = <1>; 3298 }; 3299 3300 aoss_qmp: power-management@c300000 { 3301 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 3302 reg = <0 0x0c300000 0 0x400>; 3303 interrupt-parent = <&ipcc>; 3304 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3305 IRQ_TYPE_EDGE_RISING>; 3306 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3307 3308 #clock-cells = <0>; 3309 }; 3310 3311 sram@c3f0000 { 3312 compatible = "qcom,rpmh-stats"; 3313 reg = <0 0x0c3f0000 0 0x400>; 3314 }; 3315 3316 spmi_bus: spmi@c400000 { 3317 compatible = "qcom,spmi-pmic-arb"; 3318 reg = <0 0x0c400000 0 0x3000>, 3319 <0 0x0c500000 0 0x400000>, 3320 <0 0x0c440000 0 0x80000>, 3321 <0 0x0c4c0000 0 0x20000>, 3322 <0 0x0c42d000 0 0x4000>; 3323 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3324 interrupt-names = "periph_irq"; 3325 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3326 qcom,ee = <0>; 3327 qcom,channel = <0>; 3328 qcom,bus-id = <0>; 3329 #address-cells = <2>; 3330 #size-cells = <0>; 3331 interrupt-controller; 3332 #interrupt-cells = <4>; 3333 }; 3334 3335 tlmm: pinctrl@f100000 { 3336 compatible = "qcom,sm8550-tlmm"; 3337 reg = <0 0x0f100000 0 0x300000>; 3338 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3339 gpio-controller; 3340 #gpio-cells = <2>; 3341 interrupt-controller; 3342 #interrupt-cells = <2>; 3343 gpio-ranges = <&tlmm 0 0 211>; 3344 wakeup-parent = <&pdc>; 3345 3346 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3347 /* SDA, SCL */ 3348 pins = "gpio16", "gpio17"; 3349 function = "i2chub0_se0"; 3350 drive-strength = <2>; 3351 bias-pull-up; 3352 }; 3353 3354 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 3355 /* SDA, SCL */ 3356 pins = "gpio18", "gpio19"; 3357 function = "i2chub0_se1"; 3358 drive-strength = <2>; 3359 bias-pull-up; 3360 }; 3361 3362 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 3363 /* SDA, SCL */ 3364 pins = "gpio20", "gpio21"; 3365 function = "i2chub0_se2"; 3366 drive-strength = <2>; 3367 bias-pull-up; 3368 }; 3369 3370 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 3371 /* SDA, SCL */ 3372 pins = "gpio22", "gpio23"; 3373 function = "i2chub0_se3"; 3374 drive-strength = <2>; 3375 bias-pull-up; 3376 }; 3377 3378 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 3379 /* SDA, SCL */ 3380 pins = "gpio4", "gpio5"; 3381 function = "i2chub0_se4"; 3382 drive-strength = <2>; 3383 bias-pull-up; 3384 }; 3385 3386 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 3387 /* SDA, SCL */ 3388 pins = "gpio6", "gpio7"; 3389 function = "i2chub0_se5"; 3390 drive-strength = <2>; 3391 bias-pull-up; 3392 }; 3393 3394 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 3395 /* SDA, SCL */ 3396 pins = "gpio8", "gpio9"; 3397 function = "i2chub0_se6"; 3398 drive-strength = <2>; 3399 bias-pull-up; 3400 }; 3401 3402 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 3403 /* SDA, SCL */ 3404 pins = "gpio10", "gpio11"; 3405 function = "i2chub0_se7"; 3406 drive-strength = <2>; 3407 bias-pull-up; 3408 }; 3409 3410 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 3411 /* SDA, SCL */ 3412 pins = "gpio206", "gpio207"; 3413 function = "i2chub0_se8"; 3414 drive-strength = <2>; 3415 bias-pull-up; 3416 }; 3417 3418 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 3419 /* SDA, SCL */ 3420 pins = "gpio84", "gpio85"; 3421 function = "i2chub0_se9"; 3422 drive-strength = <2>; 3423 bias-pull-up; 3424 }; 3425 3426 pcie0_default_state: pcie0-default-state { 3427 perst-pins { 3428 pins = "gpio94"; 3429 function = "gpio"; 3430 drive-strength = <2>; 3431 bias-pull-down; 3432 }; 3433 3434 clkreq-pins { 3435 pins = "gpio95"; 3436 function = "pcie0_clk_req_n"; 3437 drive-strength = <2>; 3438 bias-pull-up; 3439 }; 3440 3441 wake-pins { 3442 pins = "gpio96"; 3443 function = "gpio"; 3444 drive-strength = <2>; 3445 bias-pull-up; 3446 }; 3447 }; 3448 3449 pcie1_default_state: pcie1-default-state { 3450 perst-pins { 3451 pins = "gpio97"; 3452 function = "gpio"; 3453 drive-strength = <2>; 3454 bias-pull-down; 3455 }; 3456 3457 clkreq-pins { 3458 pins = "gpio98"; 3459 function = "pcie1_clk_req_n"; 3460 drive-strength = <2>; 3461 bias-pull-up; 3462 }; 3463 3464 wake-pins { 3465 pins = "gpio99"; 3466 function = "gpio"; 3467 drive-strength = <2>; 3468 bias-pull-up; 3469 }; 3470 }; 3471 3472 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3473 /* SDA, SCL */ 3474 pins = "gpio28", "gpio29"; 3475 function = "qup1_se0"; 3476 drive-strength = <2>; 3477 bias-pull-up = <2200>; 3478 }; 3479 3480 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3481 /* SDA, SCL */ 3482 pins = "gpio32", "gpio33"; 3483 function = "qup1_se1"; 3484 drive-strength = <2>; 3485 bias-pull-up = <2200>; 3486 }; 3487 3488 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3489 /* SDA, SCL */ 3490 pins = "gpio36", "gpio37"; 3491 function = "qup1_se2"; 3492 drive-strength = <2>; 3493 bias-pull-up = <2200>; 3494 }; 3495 3496 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3497 /* SDA, SCL */ 3498 pins = "gpio40", "gpio41"; 3499 function = "qup1_se3"; 3500 drive-strength = <2>; 3501 bias-pull-up = <2200>; 3502 }; 3503 3504 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3505 /* SDA, SCL */ 3506 pins = "gpio44", "gpio45"; 3507 function = "qup1_se4"; 3508 drive-strength = <2>; 3509 bias-pull-up = <2200>; 3510 }; 3511 3512 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3513 /* SDA, SCL */ 3514 pins = "gpio52", "gpio53"; 3515 function = "qup1_se5"; 3516 drive-strength = <2>; 3517 bias-pull-up = <2200>; 3518 }; 3519 3520 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3521 /* SDA, SCL */ 3522 pins = "gpio48", "gpio49"; 3523 function = "qup1_se6"; 3524 drive-strength = <2>; 3525 bias-pull-up = <2200>; 3526 }; 3527 3528 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3529 scl-pins { 3530 pins = "gpio57"; 3531 function = "qup2_se0_l1_mira"; 3532 drive-strength = <2>; 3533 bias-pull-up = <2200>; 3534 }; 3535 3536 sda-pins { 3537 pins = "gpio56"; 3538 function = "qup2_se0_l0_mira"; 3539 drive-strength = <2>; 3540 bias-pull-up = <2200>; 3541 }; 3542 }; 3543 3544 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3545 /* SDA, SCL */ 3546 pins = "gpio60", "gpio61"; 3547 function = "qup2_se1"; 3548 drive-strength = <2>; 3549 bias-pull-up = <2200>; 3550 }; 3551 3552 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3553 /* SDA, SCL */ 3554 pins = "gpio64", "gpio65"; 3555 function = "qup2_se2"; 3556 drive-strength = <2>; 3557 bias-pull-up = <2200>; 3558 }; 3559 3560 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3561 /* SDA, SCL */ 3562 pins = "gpio68", "gpio69"; 3563 function = "qup2_se3"; 3564 drive-strength = <2>; 3565 bias-pull-up = <2200>; 3566 }; 3567 3568 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3569 /* SDA, SCL */ 3570 pins = "gpio2", "gpio3"; 3571 function = "qup2_se4"; 3572 drive-strength = <2>; 3573 bias-pull-up = <2200>; 3574 }; 3575 3576 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3577 /* SDA, SCL */ 3578 pins = "gpio80", "gpio81"; 3579 function = "qup2_se5"; 3580 drive-strength = <2>; 3581 bias-pull-up = <2200>; 3582 }; 3583 3584 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3585 /* SDA, SCL */ 3586 pins = "gpio72", "gpio106"; 3587 function = "qup2_se7"; 3588 drive-strength = <2>; 3589 bias-pull-up = <2200>; 3590 }; 3591 3592 qup_spi0_cs: qup-spi0-cs-state { 3593 pins = "gpio31"; 3594 function = "qup1_se0"; 3595 drive-strength = <6>; 3596 bias-disable; 3597 }; 3598 3599 qup_spi0_data_clk: qup-spi0-data-clk-state { 3600 /* MISO, MOSI, CLK */ 3601 pins = "gpio28", "gpio29", "gpio30"; 3602 function = "qup1_se0"; 3603 drive-strength = <6>; 3604 bias-disable; 3605 }; 3606 3607 qup_spi1_cs: qup-spi1-cs-state { 3608 pins = "gpio35"; 3609 function = "qup1_se1"; 3610 drive-strength = <6>; 3611 bias-disable; 3612 }; 3613 3614 qup_spi1_data_clk: qup-spi1-data-clk-state { 3615 /* MISO, MOSI, CLK */ 3616 pins = "gpio32", "gpio33", "gpio34"; 3617 function = "qup1_se1"; 3618 drive-strength = <6>; 3619 bias-disable; 3620 }; 3621 3622 qup_spi2_cs: qup-spi2-cs-state { 3623 pins = "gpio39"; 3624 function = "qup1_se2"; 3625 drive-strength = <6>; 3626 bias-disable; 3627 }; 3628 3629 qup_spi2_data_clk: qup-spi2-data-clk-state { 3630 /* MISO, MOSI, CLK */ 3631 pins = "gpio36", "gpio37", "gpio38"; 3632 function = "qup1_se2"; 3633 drive-strength = <6>; 3634 bias-disable; 3635 }; 3636 3637 qup_spi3_cs: qup-spi3-cs-state { 3638 pins = "gpio43"; 3639 function = "qup1_se3"; 3640 drive-strength = <6>; 3641 bias-disable; 3642 }; 3643 3644 qup_spi3_data_clk: qup-spi3-data-clk-state { 3645 /* MISO, MOSI, CLK */ 3646 pins = "gpio40", "gpio41", "gpio42"; 3647 function = "qup1_se3"; 3648 drive-strength = <6>; 3649 bias-disable; 3650 }; 3651 3652 qup_spi4_cs: qup-spi4-cs-state { 3653 pins = "gpio47"; 3654 function = "qup1_se4"; 3655 drive-strength = <6>; 3656 bias-disable; 3657 }; 3658 3659 qup_spi4_data_clk: qup-spi4-data-clk-state { 3660 /* MISO, MOSI, CLK */ 3661 pins = "gpio44", "gpio45", "gpio46"; 3662 function = "qup1_se4"; 3663 drive-strength = <6>; 3664 bias-disable; 3665 }; 3666 3667 qup_spi5_cs: qup-spi5-cs-state { 3668 pins = "gpio55"; 3669 function = "qup1_se5"; 3670 drive-strength = <6>; 3671 bias-disable; 3672 }; 3673 3674 qup_spi5_data_clk: qup-spi5-data-clk-state { 3675 /* MISO, MOSI, CLK */ 3676 pins = "gpio52", "gpio53", "gpio54"; 3677 function = "qup1_se5"; 3678 drive-strength = <6>; 3679 bias-disable; 3680 }; 3681 3682 qup_spi6_cs: qup-spi6-cs-state { 3683 pins = "gpio51"; 3684 function = "qup1_se6"; 3685 drive-strength = <6>; 3686 bias-disable; 3687 }; 3688 3689 qup_spi6_data_clk: qup-spi6-data-clk-state { 3690 /* MISO, MOSI, CLK */ 3691 pins = "gpio48", "gpio49", "gpio50"; 3692 function = "qup1_se6"; 3693 drive-strength = <6>; 3694 bias-disable; 3695 }; 3696 3697 qup_spi8_cs: qup-spi8-cs-state { 3698 pins = "gpio59"; 3699 function = "qup2_se0_l3_mira"; 3700 drive-strength = <6>; 3701 bias-disable; 3702 }; 3703 3704 qup_spi8_data_clk: qup-spi8-data-clk-state { 3705 /* MISO, MOSI, CLK */ 3706 pins = "gpio56", "gpio57", "gpio58"; 3707 function = "qup2_se0_l2_mira"; 3708 drive-strength = <6>; 3709 bias-disable; 3710 }; 3711 3712 qup_spi9_cs: qup-spi9-cs-state { 3713 pins = "gpio63"; 3714 function = "qup2_se1"; 3715 drive-strength = <6>; 3716 bias-disable; 3717 }; 3718 3719 qup_spi9_data_clk: qup-spi9-data-clk-state { 3720 /* MISO, MOSI, CLK */ 3721 pins = "gpio60", "gpio61", "gpio62"; 3722 function = "qup2_se1"; 3723 drive-strength = <6>; 3724 bias-disable; 3725 }; 3726 3727 qup_spi10_cs: qup-spi10-cs-state { 3728 pins = "gpio67"; 3729 function = "qup2_se2"; 3730 drive-strength = <6>; 3731 bias-disable; 3732 }; 3733 3734 qup_spi10_data_clk: qup-spi10-data-clk-state { 3735 /* MISO, MOSI, CLK */ 3736 pins = "gpio64", "gpio65", "gpio66"; 3737 function = "qup2_se2"; 3738 drive-strength = <6>; 3739 bias-disable; 3740 }; 3741 3742 qup_spi11_cs: qup-spi11-cs-state { 3743 pins = "gpio71"; 3744 function = "qup2_se3"; 3745 drive-strength = <6>; 3746 bias-disable; 3747 }; 3748 3749 qup_spi11_data_clk: qup-spi11-data-clk-state { 3750 /* MISO, MOSI, CLK */ 3751 pins = "gpio68", "gpio69", "gpio70"; 3752 function = "qup2_se3"; 3753 drive-strength = <6>; 3754 bias-disable; 3755 }; 3756 3757 qup_spi12_cs: qup-spi12-cs-state { 3758 pins = "gpio119"; 3759 function = "qup2_se4"; 3760 drive-strength = <6>; 3761 bias-disable; 3762 }; 3763 3764 qup_spi12_data_clk: qup-spi12-data-clk-state { 3765 /* MISO, MOSI, CLK */ 3766 pins = "gpio2", "gpio3", "gpio118"; 3767 function = "qup2_se4"; 3768 drive-strength = <6>; 3769 bias-disable; 3770 }; 3771 3772 qup_spi13_cs: qup-spi13-cs-state { 3773 pins = "gpio83"; 3774 function = "qup2_se5"; 3775 drive-strength = <6>; 3776 bias-disable; 3777 }; 3778 3779 qup_spi13_data_clk: qup-spi13-data-clk-state { 3780 /* MISO, MOSI, CLK */ 3781 pins = "gpio80", "gpio81", "gpio82"; 3782 function = "qup2_se5"; 3783 drive-strength = <6>; 3784 bias-disable; 3785 }; 3786 3787 qup_spi15_cs: qup-spi15-cs-state { 3788 pins = "gpio75"; 3789 function = "qup2_se7"; 3790 drive-strength = <6>; 3791 bias-disable; 3792 }; 3793 3794 qup_spi15_data_clk: qup-spi15-data-clk-state { 3795 /* MISO, MOSI, CLK */ 3796 pins = "gpio72", "gpio106", "gpio74"; 3797 function = "qup2_se7"; 3798 drive-strength = <6>; 3799 bias-disable; 3800 }; 3801 3802 qup_uart7_default: qup-uart7-default-state { 3803 /* TX, RX */ 3804 pins = "gpio26", "gpio27"; 3805 function = "qup1_se7"; 3806 drive-strength = <2>; 3807 bias-disable; 3808 }; 3809 3810 qup_uart14_default: qup-uart14-default-state { 3811 /* TX, RX */ 3812 pins = "gpio78", "gpio79"; 3813 function = "qup2_se6"; 3814 drive-strength = <2>; 3815 bias-pull-up; 3816 }; 3817 3818 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 3819 /* CTS, RTS */ 3820 pins = "gpio76", "gpio77"; 3821 function = "qup2_se6"; 3822 drive-strength = <2>; 3823 bias-pull-down; 3824 }; 3825 3826 sdc2_sleep: sdc2-sleep-state { 3827 clk-pins { 3828 pins = "sdc2_clk"; 3829 bias-disable; 3830 drive-strength = <2>; 3831 }; 3832 3833 cmd-pins { 3834 pins = "sdc2_cmd"; 3835 bias-pull-up; 3836 drive-strength = <2>; 3837 }; 3838 3839 data-pins { 3840 pins = "sdc2_data"; 3841 bias-pull-up; 3842 drive-strength = <2>; 3843 }; 3844 }; 3845 3846 sdc2_default: sdc2-default-state { 3847 clk-pins { 3848 pins = "sdc2_clk"; 3849 bias-disable; 3850 drive-strength = <16>; 3851 }; 3852 3853 cmd-pins { 3854 pins = "sdc2_cmd"; 3855 bias-pull-up; 3856 drive-strength = <10>; 3857 }; 3858 3859 data-pins { 3860 pins = "sdc2_data"; 3861 bias-pull-up; 3862 drive-strength = <10>; 3863 }; 3864 }; 3865 }; 3866 3867 apps_smmu: iommu@15000000 { 3868 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3869 reg = <0 0x15000000 0 0x100000>; 3870 #iommu-cells = <2>; 3871 #global-interrupts = <1>; 3872 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3873 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3874 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3875 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3876 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3877 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3878 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3879 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3880 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3881 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3882 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3883 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3884 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3885 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3886 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3887 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3888 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3889 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3890 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3891 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3892 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3893 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3894 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3895 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3896 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3897 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3898 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3899 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3900 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3901 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3902 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3903 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3904 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3905 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3906 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3907 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3908 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3909 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3910 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3911 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3912 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3913 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3914 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3915 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3916 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3917 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3918 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3919 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3920 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3921 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3922 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3923 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3924 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3925 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3926 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3927 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3928 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3929 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3930 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3931 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3932 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3933 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3934 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3935 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3936 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3937 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3938 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3939 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3940 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3941 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3942 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3943 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3944 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3945 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3946 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3947 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3948 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3949 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3950 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3951 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3952 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3953 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3954 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3955 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3956 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3957 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3958 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3959 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3960 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3961 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3962 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3963 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3964 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3965 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3966 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3967 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3968 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 3969 }; 3970 3971 intc: interrupt-controller@17100000 { 3972 compatible = "arm,gic-v3"; 3973 reg = <0 0x17100000 0 0x10000>, /* GICD */ 3974 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 3975 ranges; 3976 #interrupt-cells = <3>; 3977 interrupt-controller; 3978 #redistributor-regions = <1>; 3979 redistributor-stride = <0 0x40000>; 3980 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3981 #address-cells = <2>; 3982 #size-cells = <2>; 3983 3984 gic_its: msi-controller@17140000 { 3985 compatible = "arm,gic-v3-its"; 3986 reg = <0 0x17140000 0 0x20000>; 3987 msi-controller; 3988 #msi-cells = <1>; 3989 }; 3990 }; 3991 3992 timer@17420000 { 3993 compatible = "arm,armv7-timer-mem"; 3994 reg = <0 0x17420000 0 0x1000>; 3995 ranges = <0 0 0 0x20000000>; 3996 #address-cells = <1>; 3997 #size-cells = <1>; 3998 3999 frame@17421000 { 4000 reg = <0x17421000 0x1000>, 4001 <0x17422000 0x1000>; 4002 frame-number = <0>; 4003 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4004 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4005 }; 4006 4007 frame@17423000 { 4008 reg = <0x17423000 0x1000>; 4009 frame-number = <1>; 4010 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4011 status = "disabled"; 4012 }; 4013 4014 frame@17425000 { 4015 reg = <0x17425000 0x1000>; 4016 frame-number = <2>; 4017 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4018 status = "disabled"; 4019 }; 4020 4021 frame@17427000 { 4022 reg = <0x17427000 0x1000>; 4023 frame-number = <3>; 4024 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4025 status = "disabled"; 4026 }; 4027 4028 frame@17429000 { 4029 reg = <0x17429000 0x1000>; 4030 frame-number = <4>; 4031 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4032 status = "disabled"; 4033 }; 4034 4035 frame@1742b000 { 4036 reg = <0x1742b000 0x1000>; 4037 frame-number = <5>; 4038 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4039 status = "disabled"; 4040 }; 4041 4042 frame@1742d000 { 4043 reg = <0x1742d000 0x1000>; 4044 frame-number = <6>; 4045 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4046 status = "disabled"; 4047 }; 4048 }; 4049 4050 apps_rsc: rsc@17a00000 { 4051 label = "apps_rsc"; 4052 compatible = "qcom,rpmh-rsc"; 4053 reg = <0 0x17a00000 0 0x10000>, 4054 <0 0x17a10000 0 0x10000>, 4055 <0 0x17a20000 0 0x10000>, 4056 <0 0x17a30000 0 0x10000>; 4057 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 4058 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4061 qcom,tcs-offset = <0xd00>; 4062 qcom,drv-id = <2>; 4063 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4064 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4065 power-domains = <&CLUSTER_PD>; 4066 4067 apps_bcm_voter: bcm-voter { 4068 compatible = "qcom,bcm-voter"; 4069 }; 4070 4071 rpmhcc: clock-controller { 4072 compatible = "qcom,sm8550-rpmh-clk"; 4073 #clock-cells = <1>; 4074 clock-names = "xo"; 4075 clocks = <&xo_board>; 4076 }; 4077 4078 rpmhpd: power-controller { 4079 compatible = "qcom,sm8550-rpmhpd"; 4080 #power-domain-cells = <1>; 4081 operating-points-v2 = <&rpmhpd_opp_table>; 4082 4083 rpmhpd_opp_table: opp-table { 4084 compatible = "operating-points-v2"; 4085 4086 rpmhpd_opp_ret: opp-16 { 4087 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4088 }; 4089 4090 rpmhpd_opp_min_svs: opp-48 { 4091 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4092 }; 4093 4094 rpmhpd_opp_low_svs_d2: opp-52 { 4095 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 4096 }; 4097 4098 rpmhpd_opp_low_svs_d1: opp-56 { 4099 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4100 }; 4101 4102 rpmhpd_opp_low_svs_d0: opp-60 { 4103 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 4104 }; 4105 4106 rpmhpd_opp_low_svs: opp-64 { 4107 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4108 }; 4109 4110 rpmhpd_opp_low_svs_l1: opp-80 { 4111 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4112 }; 4113 4114 rpmhpd_opp_svs: opp-128 { 4115 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4116 }; 4117 4118 rpmhpd_opp_svs_l0: opp-144 { 4119 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4120 }; 4121 4122 rpmhpd_opp_svs_l1: opp-192 { 4123 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4124 }; 4125 4126 rpmhpd_opp_nom: opp-256 { 4127 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4128 }; 4129 4130 rpmhpd_opp_nom_l1: opp-320 { 4131 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4132 }; 4133 4134 rpmhpd_opp_nom_l2: opp-336 { 4135 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4136 }; 4137 4138 rpmhpd_opp_turbo: opp-384 { 4139 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4140 }; 4141 4142 rpmhpd_opp_turbo_l1: opp-416 { 4143 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4144 }; 4145 }; 4146 }; 4147 }; 4148 4149 cpufreq_hw: cpufreq@17d91000 { 4150 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 4151 reg = <0 0x17d91000 0 0x1000>, 4152 <0 0x17d92000 0 0x1000>, 4153 <0 0x17d93000 0 0x1000>; 4154 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4155 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 4156 clock-names = "xo", "alternate"; 4157 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4158 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4159 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4160 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4161 #freq-domain-cells = <1>; 4162 #clock-cells = <1>; 4163 }; 4164 4165 pmu@24091000 { 4166 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4167 reg = <0 0x24091000 0 0x1000>; 4168 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4169 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 4170 4171 operating-points-v2 = <&llcc_bwmon_opp_table>; 4172 4173 llcc_bwmon_opp_table: opp-table { 4174 compatible = "operating-points-v2"; 4175 4176 opp-0 { 4177 opp-peak-kBps = <2086000>; 4178 }; 4179 4180 opp-1 { 4181 opp-peak-kBps = <2929000>; 4182 }; 4183 4184 opp-2 { 4185 opp-peak-kBps = <5931000>; 4186 }; 4187 4188 opp-3 { 4189 opp-peak-kBps = <6515000>; 4190 }; 4191 4192 opp-4 { 4193 opp-peak-kBps = <7980000>; 4194 }; 4195 4196 opp-5 { 4197 opp-peak-kBps = <10437000>; 4198 }; 4199 4200 opp-6 { 4201 opp-peak-kBps = <12157000>; 4202 }; 4203 4204 opp-7 { 4205 opp-peak-kBps = <14060000>; 4206 }; 4207 4208 opp-8 { 4209 opp-peak-kBps = <16113000>; 4210 }; 4211 }; 4212 }; 4213 4214 pmu@240b6400 { 4215 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 4216 reg = <0 0x240b6400 0 0x600>; 4217 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4218 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 4219 4220 operating-points-v2 = <&cpu_bwmon_opp_table>; 4221 4222 cpu_bwmon_opp_table: opp-table { 4223 compatible = "operating-points-v2"; 4224 4225 opp-0 { 4226 opp-peak-kBps = <4577000>; 4227 }; 4228 4229 opp-1 { 4230 opp-peak-kBps = <7110000>; 4231 }; 4232 4233 opp-2 { 4234 opp-peak-kBps = <9155000>; 4235 }; 4236 4237 opp-3 { 4238 opp-peak-kBps = <12298000>; 4239 }; 4240 4241 opp-4 { 4242 opp-peak-kBps = <14236000>; 4243 }; 4244 4245 opp-5 { 4246 opp-peak-kBps = <16265000>; 4247 }; 4248 }; 4249 }; 4250 4251 gem_noc: interconnect@24100000 { 4252 compatible = "qcom,sm8550-gem-noc"; 4253 reg = <0 0x24100000 0 0xbb800>; 4254 #interconnect-cells = <2>; 4255 qcom,bcm-voters = <&apps_bcm_voter>; 4256 }; 4257 4258 system-cache-controller@25000000 { 4259 compatible = "qcom,sm8550-llcc"; 4260 reg = <0 0x25000000 0 0x200000>, 4261 <0 0x25200000 0 0x200000>, 4262 <0 0x25400000 0 0x200000>, 4263 <0 0x25600000 0 0x200000>, 4264 <0 0x25800000 0 0x200000>; 4265 reg-names = "llcc0_base", 4266 "llcc1_base", 4267 "llcc2_base", 4268 "llcc3_base", 4269 "llcc_broadcast_base"; 4270 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4271 }; 4272 4273 remoteproc_adsp: remoteproc@30000000 { 4274 compatible = "qcom,sm8550-adsp-pas"; 4275 reg = <0x0 0x30000000 0x0 0x100>; 4276 4277 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4278 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4279 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4280 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4281 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4282 interrupt-names = "wdog", "fatal", "ready", 4283 "handover", "stop-ack"; 4284 4285 clocks = <&rpmhcc RPMH_CXO_CLK>; 4286 clock-names = "xo"; 4287 4288 power-domains = <&rpmhpd RPMHPD_LCX>, 4289 <&rpmhpd RPMHPD_LMX>; 4290 power-domain-names = "lcx", "lmx"; 4291 4292 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 4293 4294 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 4295 4296 qcom,qmp = <&aoss_qmp>; 4297 4298 qcom,smem-states = <&smp2p_adsp_out 0>; 4299 qcom,smem-state-names = "stop"; 4300 4301 status = "disabled"; 4302 4303 remoteproc_adsp_glink: glink-edge { 4304 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4305 IPCC_MPROC_SIGNAL_GLINK_QMP 4306 IRQ_TYPE_EDGE_RISING>; 4307 mboxes = <&ipcc IPCC_CLIENT_LPASS 4308 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4309 4310 label = "lpass"; 4311 qcom,remote-pid = <2>; 4312 4313 fastrpc { 4314 compatible = "qcom,fastrpc"; 4315 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4316 label = "adsp"; 4317 #address-cells = <1>; 4318 #size-cells = <0>; 4319 4320 compute-cb@3 { 4321 compatible = "qcom,fastrpc-compute-cb"; 4322 reg = <3>; 4323 iommus = <&apps_smmu 0x1003 0x80>, 4324 <&apps_smmu 0x1063 0x0>; 4325 dma-coherent; 4326 }; 4327 4328 compute-cb@4 { 4329 compatible = "qcom,fastrpc-compute-cb"; 4330 reg = <4>; 4331 iommus = <&apps_smmu 0x1004 0x80>, 4332 <&apps_smmu 0x1064 0x0>; 4333 dma-coherent; 4334 }; 4335 4336 compute-cb@5 { 4337 compatible = "qcom,fastrpc-compute-cb"; 4338 reg = <5>; 4339 iommus = <&apps_smmu 0x1005 0x80>, 4340 <&apps_smmu 0x1065 0x0>; 4341 dma-coherent; 4342 }; 4343 4344 compute-cb@6 { 4345 compatible = "qcom,fastrpc-compute-cb"; 4346 reg = <6>; 4347 iommus = <&apps_smmu 0x1006 0x80>, 4348 <&apps_smmu 0x1066 0x0>; 4349 dma-coherent; 4350 }; 4351 4352 compute-cb@7 { 4353 compatible = "qcom,fastrpc-compute-cb"; 4354 reg = <7>; 4355 iommus = <&apps_smmu 0x1007 0x80>, 4356 <&apps_smmu 0x1067 0x0>; 4357 dma-coherent; 4358 }; 4359 }; 4360 4361 gpr { 4362 compatible = "qcom,gpr"; 4363 qcom,glink-channels = "adsp_apps"; 4364 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4365 qcom,intents = <512 20>; 4366 #address-cells = <1>; 4367 #size-cells = <0>; 4368 4369 q6apm: service@1 { 4370 compatible = "qcom,q6apm"; 4371 reg = <GPR_APM_MODULE_IID>; 4372 #sound-dai-cells = <0>; 4373 qcom,protection-domain = "avs/audio", 4374 "msm/adsp/audio_pd"; 4375 4376 q6apmdai: dais { 4377 compatible = "qcom,q6apm-dais"; 4378 iommus = <&apps_smmu 0x1001 0x80>, 4379 <&apps_smmu 0x1061 0x0>; 4380 }; 4381 4382 q6apmbedai: bedais { 4383 compatible = "qcom,q6apm-lpass-dais"; 4384 #sound-dai-cells = <1>; 4385 }; 4386 }; 4387 4388 q6prm: service@2 { 4389 compatible = "qcom,q6prm"; 4390 reg = <GPR_PRM_MODULE_IID>; 4391 qcom,protection-domain = "avs/audio", 4392 "msm/adsp/audio_pd"; 4393 4394 q6prmcc: clock-controller { 4395 compatible = "qcom,q6prm-lpass-clocks"; 4396 #clock-cells = <2>; 4397 }; 4398 }; 4399 }; 4400 }; 4401 }; 4402 4403 nsp_noc: interconnect@320c0000 { 4404 compatible = "qcom,sm8550-nsp-noc"; 4405 reg = <0 0x320c0000 0 0xe080>; 4406 #interconnect-cells = <2>; 4407 qcom,bcm-voters = <&apps_bcm_voter>; 4408 }; 4409 4410 remoteproc_cdsp: remoteproc@32300000 { 4411 compatible = "qcom,sm8550-cdsp-pas"; 4412 reg = <0x0 0x32300000 0x0 0x1400000>; 4413 4414 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4415 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 4416 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 4417 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 4418 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 4419 interrupt-names = "wdog", "fatal", "ready", 4420 "handover", "stop-ack"; 4421 4422 clocks = <&rpmhcc RPMH_CXO_CLK>; 4423 clock-names = "xo"; 4424 4425 power-domains = <&rpmhpd RPMHPD_CX>, 4426 <&rpmhpd RPMHPD_MXC>, 4427 <&rpmhpd RPMHPD_NSP>; 4428 power-domain-names = "cx", "mxc", "nsp"; 4429 4430 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4431 4432 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 4433 4434 qcom,qmp = <&aoss_qmp>; 4435 4436 qcom,smem-states = <&smp2p_cdsp_out 0>; 4437 qcom,smem-state-names = "stop"; 4438 4439 status = "disabled"; 4440 4441 glink-edge { 4442 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4443 IPCC_MPROC_SIGNAL_GLINK_QMP 4444 IRQ_TYPE_EDGE_RISING>; 4445 mboxes = <&ipcc IPCC_CLIENT_CDSP 4446 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4447 4448 label = "cdsp"; 4449 qcom,remote-pid = <5>; 4450 4451 fastrpc { 4452 compatible = "qcom,fastrpc"; 4453 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4454 label = "cdsp"; 4455 #address-cells = <1>; 4456 #size-cells = <0>; 4457 4458 compute-cb@1 { 4459 compatible = "qcom,fastrpc-compute-cb"; 4460 reg = <1>; 4461 iommus = <&apps_smmu 0x1961 0x0>, 4462 <&apps_smmu 0x0c01 0x20>, 4463 <&apps_smmu 0x19c1 0x10>; 4464 dma-coherent; 4465 }; 4466 4467 compute-cb@2 { 4468 compatible = "qcom,fastrpc-compute-cb"; 4469 reg = <2>; 4470 iommus = <&apps_smmu 0x1962 0x0>, 4471 <&apps_smmu 0x0c02 0x20>, 4472 <&apps_smmu 0x19c2 0x10>; 4473 dma-coherent; 4474 }; 4475 4476 compute-cb@3 { 4477 compatible = "qcom,fastrpc-compute-cb"; 4478 reg = <3>; 4479 iommus = <&apps_smmu 0x1963 0x0>, 4480 <&apps_smmu 0x0c03 0x20>, 4481 <&apps_smmu 0x19c3 0x10>; 4482 dma-coherent; 4483 }; 4484 4485 compute-cb@4 { 4486 compatible = "qcom,fastrpc-compute-cb"; 4487 reg = <4>; 4488 iommus = <&apps_smmu 0x1964 0x0>, 4489 <&apps_smmu 0x0c04 0x20>, 4490 <&apps_smmu 0x19c4 0x10>; 4491 dma-coherent; 4492 }; 4493 4494 compute-cb@5 { 4495 compatible = "qcom,fastrpc-compute-cb"; 4496 reg = <5>; 4497 iommus = <&apps_smmu 0x1965 0x0>, 4498 <&apps_smmu 0x0c05 0x20>, 4499 <&apps_smmu 0x19c5 0x10>; 4500 dma-coherent; 4501 }; 4502 4503 compute-cb@6 { 4504 compatible = "qcom,fastrpc-compute-cb"; 4505 reg = <6>; 4506 iommus = <&apps_smmu 0x1966 0x0>, 4507 <&apps_smmu 0x0c06 0x20>, 4508 <&apps_smmu 0x19c6 0x10>; 4509 dma-coherent; 4510 }; 4511 4512 compute-cb@7 { 4513 compatible = "qcom,fastrpc-compute-cb"; 4514 reg = <7>; 4515 iommus = <&apps_smmu 0x1967 0x0>, 4516 <&apps_smmu 0x0c07 0x20>, 4517 <&apps_smmu 0x19c7 0x10>; 4518 dma-coherent; 4519 }; 4520 4521 compute-cb@8 { 4522 compatible = "qcom,fastrpc-compute-cb"; 4523 reg = <8>; 4524 iommus = <&apps_smmu 0x1968 0x0>, 4525 <&apps_smmu 0x0c08 0x20>, 4526 <&apps_smmu 0x19c8 0x10>; 4527 dma-coherent; 4528 }; 4529 4530 /* note: secure cb9 in downstream */ 4531 }; 4532 }; 4533 }; 4534 }; 4535 4536 thermal-zones { 4537 aoss0-thermal { 4538 polling-delay-passive = <0>; 4539 polling-delay = <0>; 4540 thermal-sensors = <&tsens0 0>; 4541 4542 trips { 4543 thermal-engine-config { 4544 temperature = <125000>; 4545 hysteresis = <1000>; 4546 type = "passive"; 4547 }; 4548 4549 reset-mon-config { 4550 temperature = <115000>; 4551 hysteresis = <5000>; 4552 type = "passive"; 4553 }; 4554 }; 4555 }; 4556 4557 cpuss0-thermal { 4558 polling-delay-passive = <0>; 4559 polling-delay = <0>; 4560 thermal-sensors = <&tsens0 1>; 4561 4562 trips { 4563 thermal-engine-config { 4564 temperature = <125000>; 4565 hysteresis = <1000>; 4566 type = "passive"; 4567 }; 4568 4569 reset-mon-config { 4570 temperature = <115000>; 4571 hysteresis = <5000>; 4572 type = "passive"; 4573 }; 4574 }; 4575 }; 4576 4577 cpuss1-thermal { 4578 polling-delay-passive = <0>; 4579 polling-delay = <0>; 4580 thermal-sensors = <&tsens0 2>; 4581 4582 trips { 4583 thermal-engine-config { 4584 temperature = <125000>; 4585 hysteresis = <1000>; 4586 type = "passive"; 4587 }; 4588 4589 reset-mon-config { 4590 temperature = <115000>; 4591 hysteresis = <5000>; 4592 type = "passive"; 4593 }; 4594 }; 4595 }; 4596 4597 cpuss2-thermal { 4598 polling-delay-passive = <0>; 4599 polling-delay = <0>; 4600 thermal-sensors = <&tsens0 3>; 4601 4602 trips { 4603 thermal-engine-config { 4604 temperature = <125000>; 4605 hysteresis = <1000>; 4606 type = "passive"; 4607 }; 4608 4609 reset-mon-config { 4610 temperature = <115000>; 4611 hysteresis = <5000>; 4612 type = "passive"; 4613 }; 4614 }; 4615 }; 4616 4617 cpuss3-thermal { 4618 polling-delay-passive = <0>; 4619 polling-delay = <0>; 4620 thermal-sensors = <&tsens0 4>; 4621 4622 trips { 4623 thermal-engine-config { 4624 temperature = <125000>; 4625 hysteresis = <1000>; 4626 type = "passive"; 4627 }; 4628 4629 reset-mon-config { 4630 temperature = <115000>; 4631 hysteresis = <5000>; 4632 type = "passive"; 4633 }; 4634 }; 4635 }; 4636 4637 cpu3-top-thermal { 4638 polling-delay-passive = <0>; 4639 polling-delay = <0>; 4640 thermal-sensors = <&tsens0 5>; 4641 4642 trips { 4643 cpu3_top_alert0: trip-point0 { 4644 temperature = <90000>; 4645 hysteresis = <2000>; 4646 type = "passive"; 4647 }; 4648 4649 cpu3_top_alert1: trip-point1 { 4650 temperature = <95000>; 4651 hysteresis = <2000>; 4652 type = "passive"; 4653 }; 4654 4655 cpu3_top_crit: cpu-critical { 4656 temperature = <110000>; 4657 hysteresis = <1000>; 4658 type = "critical"; 4659 }; 4660 }; 4661 }; 4662 4663 cpu3-bottom-thermal { 4664 polling-delay-passive = <0>; 4665 polling-delay = <0>; 4666 thermal-sensors = <&tsens0 6>; 4667 4668 trips { 4669 cpu3_bottom_alert0: trip-point0 { 4670 temperature = <90000>; 4671 hysteresis = <2000>; 4672 type = "passive"; 4673 }; 4674 4675 cpu3_bottom_alert1: trip-point1 { 4676 temperature = <95000>; 4677 hysteresis = <2000>; 4678 type = "passive"; 4679 }; 4680 4681 cpu3_bottom_crit: cpu-critical { 4682 temperature = <110000>; 4683 hysteresis = <1000>; 4684 type = "critical"; 4685 }; 4686 }; 4687 }; 4688 4689 cpu4-top-thermal { 4690 polling-delay-passive = <0>; 4691 polling-delay = <0>; 4692 thermal-sensors = <&tsens0 7>; 4693 4694 trips { 4695 cpu4_top_alert0: trip-point0 { 4696 temperature = <90000>; 4697 hysteresis = <2000>; 4698 type = "passive"; 4699 }; 4700 4701 cpu4_top_alert1: trip-point1 { 4702 temperature = <95000>; 4703 hysteresis = <2000>; 4704 type = "passive"; 4705 }; 4706 4707 cpu4_top_crit: cpu-critical { 4708 temperature = <110000>; 4709 hysteresis = <1000>; 4710 type = "critical"; 4711 }; 4712 }; 4713 }; 4714 4715 cpu4-bottom-thermal { 4716 polling-delay-passive = <0>; 4717 polling-delay = <0>; 4718 thermal-sensors = <&tsens0 8>; 4719 4720 trips { 4721 cpu4_bottom_alert0: trip-point0 { 4722 temperature = <90000>; 4723 hysteresis = <2000>; 4724 type = "passive"; 4725 }; 4726 4727 cpu4_bottom_alert1: trip-point1 { 4728 temperature = <95000>; 4729 hysteresis = <2000>; 4730 type = "passive"; 4731 }; 4732 4733 cpu4_bottom_crit: cpu-critical { 4734 temperature = <110000>; 4735 hysteresis = <1000>; 4736 type = "critical"; 4737 }; 4738 }; 4739 }; 4740 4741 cpu5-top-thermal { 4742 polling-delay-passive = <0>; 4743 polling-delay = <0>; 4744 thermal-sensors = <&tsens0 9>; 4745 4746 trips { 4747 cpu5_top_alert0: trip-point0 { 4748 temperature = <90000>; 4749 hysteresis = <2000>; 4750 type = "passive"; 4751 }; 4752 4753 cpu5_top_alert1: trip-point1 { 4754 temperature = <95000>; 4755 hysteresis = <2000>; 4756 type = "passive"; 4757 }; 4758 4759 cpu5_top_crit: cpu-critical { 4760 temperature = <110000>; 4761 hysteresis = <1000>; 4762 type = "critical"; 4763 }; 4764 }; 4765 }; 4766 4767 cpu5-bottom-thermal { 4768 polling-delay-passive = <0>; 4769 polling-delay = <0>; 4770 thermal-sensors = <&tsens0 10>; 4771 4772 trips { 4773 cpu5_bottom_alert0: trip-point0 { 4774 temperature = <90000>; 4775 hysteresis = <2000>; 4776 type = "passive"; 4777 }; 4778 4779 cpu5_bottom_alert1: trip-point1 { 4780 temperature = <95000>; 4781 hysteresis = <2000>; 4782 type = "passive"; 4783 }; 4784 4785 cpu5_bottom_crit: cpu-critical { 4786 temperature = <110000>; 4787 hysteresis = <1000>; 4788 type = "critical"; 4789 }; 4790 }; 4791 }; 4792 4793 cpu6-top-thermal { 4794 polling-delay-passive = <0>; 4795 polling-delay = <0>; 4796 thermal-sensors = <&tsens0 11>; 4797 4798 trips { 4799 cpu6_top_alert0: trip-point0 { 4800 temperature = <90000>; 4801 hysteresis = <2000>; 4802 type = "passive"; 4803 }; 4804 4805 cpu6_top_alert1: trip-point1 { 4806 temperature = <95000>; 4807 hysteresis = <2000>; 4808 type = "passive"; 4809 }; 4810 4811 cpu6_top_crit: cpu-critical { 4812 temperature = <110000>; 4813 hysteresis = <1000>; 4814 type = "critical"; 4815 }; 4816 }; 4817 }; 4818 4819 cpu6-bottom-thermal { 4820 polling-delay-passive = <0>; 4821 polling-delay = <0>; 4822 thermal-sensors = <&tsens0 12>; 4823 4824 trips { 4825 cpu6_bottom_alert0: trip-point0 { 4826 temperature = <90000>; 4827 hysteresis = <2000>; 4828 type = "passive"; 4829 }; 4830 4831 cpu6_bottom_alert1: trip-point1 { 4832 temperature = <95000>; 4833 hysteresis = <2000>; 4834 type = "passive"; 4835 }; 4836 4837 cpu6_bottom_crit: cpu-critical { 4838 temperature = <110000>; 4839 hysteresis = <1000>; 4840 type = "critical"; 4841 }; 4842 }; 4843 }; 4844 4845 cpu7-top-thermal { 4846 polling-delay-passive = <0>; 4847 polling-delay = <0>; 4848 thermal-sensors = <&tsens0 13>; 4849 4850 trips { 4851 cpu7_top_alert0: trip-point0 { 4852 temperature = <90000>; 4853 hysteresis = <2000>; 4854 type = "passive"; 4855 }; 4856 4857 cpu7_top_alert1: trip-point1 { 4858 temperature = <95000>; 4859 hysteresis = <2000>; 4860 type = "passive"; 4861 }; 4862 4863 cpu7_top_crit: cpu-critical { 4864 temperature = <110000>; 4865 hysteresis = <1000>; 4866 type = "critical"; 4867 }; 4868 }; 4869 }; 4870 4871 cpu7-middle-thermal { 4872 polling-delay-passive = <0>; 4873 polling-delay = <0>; 4874 thermal-sensors = <&tsens0 14>; 4875 4876 trips { 4877 cpu7_middle_alert0: trip-point0 { 4878 temperature = <90000>; 4879 hysteresis = <2000>; 4880 type = "passive"; 4881 }; 4882 4883 cpu7_middle_alert1: trip-point1 { 4884 temperature = <95000>; 4885 hysteresis = <2000>; 4886 type = "passive"; 4887 }; 4888 4889 cpu7_middle_crit: cpu-critical { 4890 temperature = <110000>; 4891 hysteresis = <1000>; 4892 type = "critical"; 4893 }; 4894 }; 4895 }; 4896 4897 cpu7-bottom-thermal { 4898 polling-delay-passive = <0>; 4899 polling-delay = <0>; 4900 thermal-sensors = <&tsens0 15>; 4901 4902 trips { 4903 cpu7_bottom_alert0: trip-point0 { 4904 temperature = <90000>; 4905 hysteresis = <2000>; 4906 type = "passive"; 4907 }; 4908 4909 cpu7_bottom_alert1: trip-point1 { 4910 temperature = <95000>; 4911 hysteresis = <2000>; 4912 type = "passive"; 4913 }; 4914 4915 cpu7_bottom_crit: cpu-critical { 4916 temperature = <110000>; 4917 hysteresis = <1000>; 4918 type = "critical"; 4919 }; 4920 }; 4921 }; 4922 4923 aoss1-thermal { 4924 polling-delay-passive = <0>; 4925 polling-delay = <0>; 4926 thermal-sensors = <&tsens1 0>; 4927 4928 trips { 4929 thermal-engine-config { 4930 temperature = <125000>; 4931 hysteresis = <1000>; 4932 type = "passive"; 4933 }; 4934 4935 reset-mon-config { 4936 temperature = <115000>; 4937 hysteresis = <5000>; 4938 type = "passive"; 4939 }; 4940 }; 4941 }; 4942 4943 cpu0-thermal { 4944 polling-delay-passive = <0>; 4945 polling-delay = <0>; 4946 thermal-sensors = <&tsens1 1>; 4947 4948 trips { 4949 cpu0_alert0: trip-point0 { 4950 temperature = <90000>; 4951 hysteresis = <2000>; 4952 type = "passive"; 4953 }; 4954 4955 cpu0_alert1: trip-point1 { 4956 temperature = <95000>; 4957 hysteresis = <2000>; 4958 type = "passive"; 4959 }; 4960 4961 cpu0_crit: cpu-critical { 4962 temperature = <110000>; 4963 hysteresis = <1000>; 4964 type = "critical"; 4965 }; 4966 }; 4967 }; 4968 4969 cpu1-thermal { 4970 polling-delay-passive = <0>; 4971 polling-delay = <0>; 4972 thermal-sensors = <&tsens1 2>; 4973 4974 trips { 4975 cpu1_alert0: trip-point0 { 4976 temperature = <90000>; 4977 hysteresis = <2000>; 4978 type = "passive"; 4979 }; 4980 4981 cpu1_alert1: trip-point1 { 4982 temperature = <95000>; 4983 hysteresis = <2000>; 4984 type = "passive"; 4985 }; 4986 4987 cpu1_crit: cpu-critical { 4988 temperature = <110000>; 4989 hysteresis = <1000>; 4990 type = "critical"; 4991 }; 4992 }; 4993 }; 4994 4995 cpu2-thermal { 4996 polling-delay-passive = <0>; 4997 polling-delay = <0>; 4998 thermal-sensors = <&tsens1 3>; 4999 5000 trips { 5001 cpu2_alert0: trip-point0 { 5002 temperature = <90000>; 5003 hysteresis = <2000>; 5004 type = "passive"; 5005 }; 5006 5007 cpu2_alert1: trip-point1 { 5008 temperature = <95000>; 5009 hysteresis = <2000>; 5010 type = "passive"; 5011 }; 5012 5013 cpu2_crit: cpu-critical { 5014 temperature = <110000>; 5015 hysteresis = <1000>; 5016 type = "critical"; 5017 }; 5018 }; 5019 }; 5020 5021 cdsp0-thermal { 5022 polling-delay-passive = <10>; 5023 polling-delay = <0>; 5024 thermal-sensors = <&tsens2 4>; 5025 5026 trips { 5027 thermal-engine-config { 5028 temperature = <125000>; 5029 hysteresis = <1000>; 5030 type = "passive"; 5031 }; 5032 5033 thermal-hal-config { 5034 temperature = <125000>; 5035 hysteresis = <1000>; 5036 type = "passive"; 5037 }; 5038 5039 reset-mon-config { 5040 temperature = <115000>; 5041 hysteresis = <5000>; 5042 type = "passive"; 5043 }; 5044 5045 cdsp0_junction_config: junction-config { 5046 temperature = <95000>; 5047 hysteresis = <5000>; 5048 type = "passive"; 5049 }; 5050 }; 5051 }; 5052 5053 cdsp1-thermal { 5054 polling-delay-passive = <10>; 5055 polling-delay = <0>; 5056 thermal-sensors = <&tsens2 5>; 5057 5058 trips { 5059 thermal-engine-config { 5060 temperature = <125000>; 5061 hysteresis = <1000>; 5062 type = "passive"; 5063 }; 5064 5065 thermal-hal-config { 5066 temperature = <125000>; 5067 hysteresis = <1000>; 5068 type = "passive"; 5069 }; 5070 5071 reset-mon-config { 5072 temperature = <115000>; 5073 hysteresis = <5000>; 5074 type = "passive"; 5075 }; 5076 5077 cdsp1_junction_config: junction-config { 5078 temperature = <95000>; 5079 hysteresis = <5000>; 5080 type = "passive"; 5081 }; 5082 }; 5083 }; 5084 5085 cdsp2-thermal { 5086 polling-delay-passive = <10>; 5087 polling-delay = <0>; 5088 thermal-sensors = <&tsens2 6>; 5089 5090 trips { 5091 thermal-engine-config { 5092 temperature = <125000>; 5093 hysteresis = <1000>; 5094 type = "passive"; 5095 }; 5096 5097 thermal-hal-config { 5098 temperature = <125000>; 5099 hysteresis = <1000>; 5100 type = "passive"; 5101 }; 5102 5103 reset-mon-config { 5104 temperature = <115000>; 5105 hysteresis = <5000>; 5106 type = "passive"; 5107 }; 5108 5109 cdsp2_junction_config: junction-config { 5110 temperature = <95000>; 5111 hysteresis = <5000>; 5112 type = "passive"; 5113 }; 5114 }; 5115 }; 5116 5117 cdsp3-thermal { 5118 polling-delay-passive = <10>; 5119 polling-delay = <0>; 5120 thermal-sensors = <&tsens2 7>; 5121 5122 trips { 5123 thermal-engine-config { 5124 temperature = <125000>; 5125 hysteresis = <1000>; 5126 type = "passive"; 5127 }; 5128 5129 thermal-hal-config { 5130 temperature = <125000>; 5131 hysteresis = <1000>; 5132 type = "passive"; 5133 }; 5134 5135 reset-mon-config { 5136 temperature = <115000>; 5137 hysteresis = <5000>; 5138 type = "passive"; 5139 }; 5140 5141 cdsp3_junction_config: junction-config { 5142 temperature = <95000>; 5143 hysteresis = <5000>; 5144 type = "passive"; 5145 }; 5146 }; 5147 }; 5148 5149 video-thermal { 5150 polling-delay-passive = <0>; 5151 polling-delay = <0>; 5152 thermal-sensors = <&tsens1 8>; 5153 5154 trips { 5155 thermal-engine-config { 5156 temperature = <125000>; 5157 hysteresis = <1000>; 5158 type = "passive"; 5159 }; 5160 5161 reset-mon-config { 5162 temperature = <115000>; 5163 hysteresis = <5000>; 5164 type = "passive"; 5165 }; 5166 }; 5167 }; 5168 5169 mem-thermal { 5170 polling-delay-passive = <10>; 5171 polling-delay = <0>; 5172 thermal-sensors = <&tsens1 9>; 5173 5174 trips { 5175 thermal-engine-config { 5176 temperature = <125000>; 5177 hysteresis = <1000>; 5178 type = "passive"; 5179 }; 5180 5181 ddr_config0: ddr0-config { 5182 temperature = <90000>; 5183 hysteresis = <5000>; 5184 type = "passive"; 5185 }; 5186 5187 reset-mon-config { 5188 temperature = <115000>; 5189 hysteresis = <5000>; 5190 type = "passive"; 5191 }; 5192 }; 5193 }; 5194 5195 modem0-thermal { 5196 polling-delay-passive = <0>; 5197 polling-delay = <0>; 5198 thermal-sensors = <&tsens1 10>; 5199 5200 trips { 5201 thermal-engine-config { 5202 temperature = <125000>; 5203 hysteresis = <1000>; 5204 type = "passive"; 5205 }; 5206 5207 mdmss0_config0: mdmss0-config0 { 5208 temperature = <102000>; 5209 hysteresis = <3000>; 5210 type = "passive"; 5211 }; 5212 5213 mdmss0_config1: mdmss0-config1 { 5214 temperature = <105000>; 5215 hysteresis = <3000>; 5216 type = "passive"; 5217 }; 5218 5219 reset-mon-config { 5220 temperature = <115000>; 5221 hysteresis = <5000>; 5222 type = "passive"; 5223 }; 5224 }; 5225 }; 5226 5227 modem1-thermal { 5228 polling-delay-passive = <0>; 5229 polling-delay = <0>; 5230 thermal-sensors = <&tsens1 11>; 5231 5232 trips { 5233 thermal-engine-config { 5234 temperature = <125000>; 5235 hysteresis = <1000>; 5236 type = "passive"; 5237 }; 5238 5239 mdmss1_config0: mdmss1-config0 { 5240 temperature = <102000>; 5241 hysteresis = <3000>; 5242 type = "passive"; 5243 }; 5244 5245 mdmss1_config1: mdmss1-config1 { 5246 temperature = <105000>; 5247 hysteresis = <3000>; 5248 type = "passive"; 5249 }; 5250 5251 reset-mon-config { 5252 temperature = <115000>; 5253 hysteresis = <5000>; 5254 type = "passive"; 5255 }; 5256 }; 5257 }; 5258 5259 modem2-thermal { 5260 polling-delay-passive = <0>; 5261 polling-delay = <0>; 5262 thermal-sensors = <&tsens1 12>; 5263 5264 trips { 5265 thermal-engine-config { 5266 temperature = <125000>; 5267 hysteresis = <1000>; 5268 type = "passive"; 5269 }; 5270 5271 mdmss2_config0: mdmss2-config0 { 5272 temperature = <102000>; 5273 hysteresis = <3000>; 5274 type = "passive"; 5275 }; 5276 5277 mdmss2_config1: mdmss2-config1 { 5278 temperature = <105000>; 5279 hysteresis = <3000>; 5280 type = "passive"; 5281 }; 5282 5283 reset-mon-config { 5284 temperature = <115000>; 5285 hysteresis = <5000>; 5286 type = "passive"; 5287 }; 5288 }; 5289 }; 5290 5291 modem3-thermal { 5292 polling-delay-passive = <0>; 5293 polling-delay = <0>; 5294 thermal-sensors = <&tsens1 13>; 5295 5296 trips { 5297 thermal-engine-config { 5298 temperature = <125000>; 5299 hysteresis = <1000>; 5300 type = "passive"; 5301 }; 5302 5303 mdmss3_config0: mdmss3-config0 { 5304 temperature = <102000>; 5305 hysteresis = <3000>; 5306 type = "passive"; 5307 }; 5308 5309 mdmss3_config1: mdmss3-config1 { 5310 temperature = <105000>; 5311 hysteresis = <3000>; 5312 type = "passive"; 5313 }; 5314 5315 reset-mon-config { 5316 temperature = <115000>; 5317 hysteresis = <5000>; 5318 type = "passive"; 5319 }; 5320 }; 5321 }; 5322 5323 camera0-thermal { 5324 polling-delay-passive = <0>; 5325 polling-delay = <0>; 5326 thermal-sensors = <&tsens1 14>; 5327 5328 trips { 5329 thermal-engine-config { 5330 temperature = <125000>; 5331 hysteresis = <1000>; 5332 type = "passive"; 5333 }; 5334 5335 reset-mon-config { 5336 temperature = <115000>; 5337 hysteresis = <5000>; 5338 type = "passive"; 5339 }; 5340 }; 5341 }; 5342 5343 camera1-thermal { 5344 polling-delay-passive = <0>; 5345 polling-delay = <0>; 5346 thermal-sensors = <&tsens1 15>; 5347 5348 trips { 5349 thermal-engine-config { 5350 temperature = <125000>; 5351 hysteresis = <1000>; 5352 type = "passive"; 5353 }; 5354 5355 reset-mon-config { 5356 temperature = <115000>; 5357 hysteresis = <5000>; 5358 type = "passive"; 5359 }; 5360 }; 5361 }; 5362 5363 aoss2-thermal { 5364 polling-delay-passive = <0>; 5365 polling-delay = <0>; 5366 thermal-sensors = <&tsens2 0>; 5367 5368 trips { 5369 thermal-engine-config { 5370 temperature = <125000>; 5371 hysteresis = <1000>; 5372 type = "passive"; 5373 }; 5374 5375 reset-mon-config { 5376 temperature = <115000>; 5377 hysteresis = <5000>; 5378 type = "passive"; 5379 }; 5380 }; 5381 }; 5382 5383 gpuss-0-thermal { 5384 polling-delay-passive = <10>; 5385 polling-delay = <0>; 5386 thermal-sensors = <&tsens2 1>; 5387 5388 cooling-maps { 5389 map0 { 5390 trip = <&gpu0_junction_config>; 5391 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5392 }; 5393 }; 5394 5395 trips { 5396 thermal-engine-config { 5397 temperature = <125000>; 5398 hysteresis = <1000>; 5399 type = "passive"; 5400 }; 5401 5402 thermal-hal-config { 5403 temperature = <125000>; 5404 hysteresis = <1000>; 5405 type = "passive"; 5406 }; 5407 5408 reset-mon-config { 5409 temperature = <115000>; 5410 hysteresis = <5000>; 5411 type = "passive"; 5412 }; 5413 5414 gpu0_junction_config: junction-config { 5415 temperature = <95000>; 5416 hysteresis = <5000>; 5417 type = "passive"; 5418 }; 5419 }; 5420 }; 5421 5422 gpuss-1-thermal { 5423 polling-delay-passive = <10>; 5424 polling-delay = <0>; 5425 thermal-sensors = <&tsens2 2>; 5426 5427 cooling-maps { 5428 map0 { 5429 trip = <&gpu1_junction_config>; 5430 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5431 }; 5432 }; 5433 5434 trips { 5435 thermal-engine-config { 5436 temperature = <125000>; 5437 hysteresis = <1000>; 5438 type = "passive"; 5439 }; 5440 5441 thermal-hal-config { 5442 temperature = <125000>; 5443 hysteresis = <1000>; 5444 type = "passive"; 5445 }; 5446 5447 reset-mon-config { 5448 temperature = <115000>; 5449 hysteresis = <5000>; 5450 type = "passive"; 5451 }; 5452 5453 gpu1_junction_config: junction-config { 5454 temperature = <95000>; 5455 hysteresis = <5000>; 5456 type = "passive"; 5457 }; 5458 }; 5459 }; 5460 5461 gpuss-2-thermal { 5462 polling-delay-passive = <10>; 5463 polling-delay = <0>; 5464 thermal-sensors = <&tsens2 3>; 5465 5466 cooling-maps { 5467 map0 { 5468 trip = <&gpu2_junction_config>; 5469 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5470 }; 5471 }; 5472 5473 trips { 5474 thermal-engine-config { 5475 temperature = <125000>; 5476 hysteresis = <1000>; 5477 type = "passive"; 5478 }; 5479 5480 thermal-hal-config { 5481 temperature = <125000>; 5482 hysteresis = <1000>; 5483 type = "passive"; 5484 }; 5485 5486 reset-mon-config { 5487 temperature = <115000>; 5488 hysteresis = <5000>; 5489 type = "passive"; 5490 }; 5491 5492 gpu2_junction_config: junction-config { 5493 temperature = <95000>; 5494 hysteresis = <5000>; 5495 type = "passive"; 5496 }; 5497 }; 5498 }; 5499 5500 gpuss-3-thermal { 5501 polling-delay-passive = <10>; 5502 polling-delay = <0>; 5503 thermal-sensors = <&tsens2 4>; 5504 5505 cooling-maps { 5506 map0 { 5507 trip = <&gpu3_junction_config>; 5508 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5509 }; 5510 }; 5511 5512 trips { 5513 thermal-engine-config { 5514 temperature = <125000>; 5515 hysteresis = <1000>; 5516 type = "passive"; 5517 }; 5518 5519 thermal-hal-config { 5520 temperature = <125000>; 5521 hysteresis = <1000>; 5522 type = "passive"; 5523 }; 5524 5525 reset-mon-config { 5526 temperature = <115000>; 5527 hysteresis = <5000>; 5528 type = "passive"; 5529 }; 5530 5531 gpu3_junction_config: junction-config { 5532 temperature = <95000>; 5533 hysteresis = <5000>; 5534 type = "passive"; 5535 }; 5536 }; 5537 }; 5538 5539 gpuss-4-thermal { 5540 polling-delay-passive = <10>; 5541 polling-delay = <0>; 5542 thermal-sensors = <&tsens2 5>; 5543 5544 cooling-maps { 5545 map0 { 5546 trip = <&gpu4_junction_config>; 5547 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5548 }; 5549 }; 5550 5551 trips { 5552 thermal-engine-config { 5553 temperature = <125000>; 5554 hysteresis = <1000>; 5555 type = "passive"; 5556 }; 5557 5558 thermal-hal-config { 5559 temperature = <125000>; 5560 hysteresis = <1000>; 5561 type = "passive"; 5562 }; 5563 5564 reset-mon-config { 5565 temperature = <115000>; 5566 hysteresis = <5000>; 5567 type = "passive"; 5568 }; 5569 5570 gpu4_junction_config: junction-config { 5571 temperature = <95000>; 5572 hysteresis = <5000>; 5573 type = "passive"; 5574 }; 5575 }; 5576 }; 5577 5578 gpuss-5-thermal { 5579 polling-delay-passive = <10>; 5580 polling-delay = <0>; 5581 thermal-sensors = <&tsens2 6>; 5582 5583 cooling-maps { 5584 map0 { 5585 trip = <&gpu5_junction_config>; 5586 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5587 }; 5588 }; 5589 5590 trips { 5591 thermal-engine-config { 5592 temperature = <125000>; 5593 hysteresis = <1000>; 5594 type = "passive"; 5595 }; 5596 5597 thermal-hal-config { 5598 temperature = <125000>; 5599 hysteresis = <1000>; 5600 type = "passive"; 5601 }; 5602 5603 reset-mon-config { 5604 temperature = <115000>; 5605 hysteresis = <5000>; 5606 type = "passive"; 5607 }; 5608 5609 gpu5_junction_config: junction-config { 5610 temperature = <95000>; 5611 hysteresis = <5000>; 5612 type = "passive"; 5613 }; 5614 }; 5615 }; 5616 5617 gpuss-6-thermal { 5618 polling-delay-passive = <10>; 5619 polling-delay = <0>; 5620 thermal-sensors = <&tsens2 7>; 5621 5622 cooling-maps { 5623 map0 { 5624 trip = <&gpu6_junction_config>; 5625 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5626 }; 5627 }; 5628 5629 trips { 5630 thermal-engine-config { 5631 temperature = <125000>; 5632 hysteresis = <1000>; 5633 type = "passive"; 5634 }; 5635 5636 thermal-hal-config { 5637 temperature = <125000>; 5638 hysteresis = <1000>; 5639 type = "passive"; 5640 }; 5641 5642 reset-mon-config { 5643 temperature = <115000>; 5644 hysteresis = <5000>; 5645 type = "passive"; 5646 }; 5647 5648 gpu6_junction_config: junction-config { 5649 temperature = <95000>; 5650 hysteresis = <5000>; 5651 type = "passive"; 5652 }; 5653 }; 5654 }; 5655 5656 gpuss-7-thermal { 5657 polling-delay-passive = <10>; 5658 polling-delay = <0>; 5659 thermal-sensors = <&tsens2 8>; 5660 5661 cooling-maps { 5662 map0 { 5663 trip = <&gpu7_junction_config>; 5664 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5665 }; 5666 }; 5667 5668 trips { 5669 thermal-engine-config { 5670 temperature = <125000>; 5671 hysteresis = <1000>; 5672 type = "passive"; 5673 }; 5674 5675 thermal-hal-config { 5676 temperature = <125000>; 5677 hysteresis = <1000>; 5678 type = "passive"; 5679 }; 5680 5681 reset-mon-config { 5682 temperature = <115000>; 5683 hysteresis = <5000>; 5684 type = "passive"; 5685 }; 5686 5687 gpu7_junction_config: junction-config { 5688 temperature = <95000>; 5689 hysteresis = <5000>; 5690 type = "passive"; 5691 }; 5692 }; 5693 }; 5694 }; 5695 5696 timer { 5697 compatible = "arm,armv8-timer"; 5698 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5699 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5700 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5701 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5702 }; 5703}; 5704