1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8450-videocc.h> 8#include <dt-bindings/clock/qcom,sm8550-camcc.h> 9#include <dt-bindings/clock/qcom,sm8550-gcc.h> 10#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 11#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 12#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 24#include <dt-bindings/phy/phy-qcom-qmp.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 chosen { }; 34 35 clocks { 36 xo_board: xo-board { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 }; 45 46 bi_tcxo_div2: bi-tcxo-div2-clk { 47 #clock-cells = <0>; 48 compatible = "fixed-factor-clock"; 49 clocks = <&rpmhcc RPMH_CXO_CLK>; 50 clock-mult = <1>; 51 clock-div = <2>; 52 }; 53 54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 55 #clock-cells = <0>; 56 compatible = "fixed-factor-clock"; 57 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 58 clock-mult = <1>; 59 clock-div = <2>; 60 }; 61 62 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 }; 66 }; 67 68 cpus { 69 #address-cells = <2>; 70 #size-cells = <0>; 71 72 CPU0: cpu@0 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a510"; 75 reg = <0 0>; 76 clocks = <&cpufreq_hw 0>; 77 enable-method = "psci"; 78 next-level-cache = <&L2_0>; 79 power-domains = <&CPU_PD0>; 80 power-domain-names = "psci"; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 capacity-dmips-mhz = <1024>; 83 dynamic-power-coefficient = <100>; 84 #cooling-cells = <2>; 85 L2_0: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 cache-unified; 89 next-level-cache = <&L3_0>; 90 L3_0: l3-cache { 91 compatible = "cache"; 92 cache-level = <3>; 93 cache-unified; 94 }; 95 }; 96 }; 97 98 CPU1: cpu@100 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a510"; 101 reg = <0 0x100>; 102 clocks = <&cpufreq_hw 0>; 103 enable-method = "psci"; 104 next-level-cache = <&L2_100>; 105 power-domains = <&CPU_PD1>; 106 power-domain-names = "psci"; 107 qcom,freq-domain = <&cpufreq_hw 0>; 108 capacity-dmips-mhz = <1024>; 109 dynamic-power-coefficient = <100>; 110 #cooling-cells = <2>; 111 L2_100: l2-cache { 112 compatible = "cache"; 113 cache-level = <2>; 114 cache-unified; 115 next-level-cache = <&L3_0>; 116 }; 117 }; 118 119 CPU2: cpu@200 { 120 device_type = "cpu"; 121 compatible = "arm,cortex-a510"; 122 reg = <0 0x200>; 123 clocks = <&cpufreq_hw 0>; 124 enable-method = "psci"; 125 next-level-cache = <&L2_200>; 126 power-domains = <&CPU_PD2>; 127 power-domain-names = "psci"; 128 qcom,freq-domain = <&cpufreq_hw 0>; 129 capacity-dmips-mhz = <1024>; 130 dynamic-power-coefficient = <100>; 131 #cooling-cells = <2>; 132 L2_200: l2-cache { 133 compatible = "cache"; 134 cache-level = <2>; 135 cache-unified; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU3: cpu@300 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-a715"; 143 reg = <0 0x300>; 144 clocks = <&cpufreq_hw 1>; 145 enable-method = "psci"; 146 next-level-cache = <&L2_300>; 147 power-domains = <&CPU_PD3>; 148 power-domain-names = "psci"; 149 qcom,freq-domain = <&cpufreq_hw 1>; 150 capacity-dmips-mhz = <1792>; 151 dynamic-power-coefficient = <270>; 152 #cooling-cells = <2>; 153 L2_300: l2-cache { 154 compatible = "cache"; 155 cache-level = <2>; 156 cache-unified; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 161 CPU4: cpu@400 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-a715"; 164 reg = <0 0x400>; 165 clocks = <&cpufreq_hw 1>; 166 enable-method = "psci"; 167 next-level-cache = <&L2_400>; 168 power-domains = <&CPU_PD4>; 169 power-domain-names = "psci"; 170 qcom,freq-domain = <&cpufreq_hw 1>; 171 capacity-dmips-mhz = <1792>; 172 dynamic-power-coefficient = <270>; 173 #cooling-cells = <2>; 174 L2_400: l2-cache { 175 compatible = "cache"; 176 cache-level = <2>; 177 cache-unified; 178 next-level-cache = <&L3_0>; 179 }; 180 }; 181 182 CPU5: cpu@500 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a710"; 185 reg = <0 0x500>; 186 clocks = <&cpufreq_hw 1>; 187 enable-method = "psci"; 188 next-level-cache = <&L2_500>; 189 power-domains = <&CPU_PD5>; 190 power-domain-names = "psci"; 191 qcom,freq-domain = <&cpufreq_hw 1>; 192 capacity-dmips-mhz = <1792>; 193 dynamic-power-coefficient = <270>; 194 #cooling-cells = <2>; 195 L2_500: l2-cache { 196 compatible = "cache"; 197 cache-level = <2>; 198 cache-unified; 199 next-level-cache = <&L3_0>; 200 }; 201 }; 202 203 CPU6: cpu@600 { 204 device_type = "cpu"; 205 compatible = "arm,cortex-a710"; 206 reg = <0 0x600>; 207 clocks = <&cpufreq_hw 1>; 208 enable-method = "psci"; 209 next-level-cache = <&L2_600>; 210 power-domains = <&CPU_PD6>; 211 power-domain-names = "psci"; 212 qcom,freq-domain = <&cpufreq_hw 1>; 213 capacity-dmips-mhz = <1792>; 214 dynamic-power-coefficient = <270>; 215 #cooling-cells = <2>; 216 L2_600: l2-cache { 217 compatible = "cache"; 218 cache-level = <2>; 219 cache-unified; 220 next-level-cache = <&L3_0>; 221 }; 222 }; 223 224 CPU7: cpu@700 { 225 device_type = "cpu"; 226 compatible = "arm,cortex-x3"; 227 reg = <0 0x700>; 228 clocks = <&cpufreq_hw 2>; 229 enable-method = "psci"; 230 next-level-cache = <&L2_700>; 231 power-domains = <&CPU_PD7>; 232 power-domain-names = "psci"; 233 qcom,freq-domain = <&cpufreq_hw 2>; 234 capacity-dmips-mhz = <1894>; 235 dynamic-power-coefficient = <588>; 236 #cooling-cells = <2>; 237 L2_700: l2-cache { 238 compatible = "cache"; 239 cache-level = <2>; 240 cache-unified; 241 next-level-cache = <&L3_0>; 242 }; 243 }; 244 245 cpu-map { 246 cluster0 { 247 core0 { 248 cpu = <&CPU0>; 249 }; 250 251 core1 { 252 cpu = <&CPU1>; 253 }; 254 255 core2 { 256 cpu = <&CPU2>; 257 }; 258 259 core3 { 260 cpu = <&CPU3>; 261 }; 262 263 core4 { 264 cpu = <&CPU4>; 265 }; 266 267 core5 { 268 cpu = <&CPU5>; 269 }; 270 271 core6 { 272 cpu = <&CPU6>; 273 }; 274 275 core7 { 276 cpu = <&CPU7>; 277 }; 278 }; 279 }; 280 281 idle-states { 282 entry-method = "psci"; 283 284 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 285 compatible = "arm,idle-state"; 286 idle-state-name = "silver-rail-power-collapse"; 287 arm,psci-suspend-param = <0x40000004>; 288 entry-latency-us = <550>; 289 exit-latency-us = <750>; 290 min-residency-us = <6700>; 291 local-timer-stop; 292 }; 293 294 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 295 compatible = "arm,idle-state"; 296 idle-state-name = "gold-rail-power-collapse"; 297 arm,psci-suspend-param = <0x40000004>; 298 entry-latency-us = <600>; 299 exit-latency-us = <1300>; 300 min-residency-us = <8136>; 301 local-timer-stop; 302 }; 303 304 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 { 305 compatible = "arm,idle-state"; 306 idle-state-name = "goldplus-rail-power-collapse"; 307 arm,psci-suspend-param = <0x40000004>; 308 entry-latency-us = <500>; 309 exit-latency-us = <1350>; 310 min-residency-us = <7480>; 311 local-timer-stop; 312 }; 313 }; 314 315 domain-idle-states { 316 CLUSTER_SLEEP_0: cluster-sleep-0 { 317 compatible = "domain-idle-state"; 318 arm,psci-suspend-param = <0x41000044>; 319 entry-latency-us = <750>; 320 exit-latency-us = <2350>; 321 min-residency-us = <9144>; 322 }; 323 324 CLUSTER_SLEEP_1: cluster-sleep-1 { 325 compatible = "domain-idle-state"; 326 arm,psci-suspend-param = <0x4100c344>; 327 entry-latency-us = <2800>; 328 exit-latency-us = <4400>; 329 min-residency-us = <10150>; 330 }; 331 }; 332 }; 333 334 firmware { 335 scm: scm { 336 compatible = "qcom,scm-sm8550", "qcom,scm"; 337 qcom,dload-mode = <&tcsr 0x19000>; 338 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 339 }; 340 }; 341 342 clk_virt: interconnect-0 { 343 compatible = "qcom,sm8550-clk-virt"; 344 #interconnect-cells = <2>; 345 qcom,bcm-voters = <&apps_bcm_voter>; 346 }; 347 348 mc_virt: interconnect-1 { 349 compatible = "qcom,sm8550-mc-virt"; 350 #interconnect-cells = <2>; 351 qcom,bcm-voters = <&apps_bcm_voter>; 352 }; 353 354 memory@a0000000 { 355 device_type = "memory"; 356 /* We expect the bootloader to fill in the size */ 357 reg = <0 0xa0000000 0 0>; 358 }; 359 360 pmu { 361 compatible = "arm,armv8-pmuv3"; 362 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 363 }; 364 365 psci { 366 compatible = "arm,psci-1.0"; 367 method = "smc"; 368 369 CPU_PD0: power-domain-cpu0 { 370 #power-domain-cells = <0>; 371 power-domains = <&CLUSTER_PD>; 372 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 373 }; 374 375 CPU_PD1: power-domain-cpu1 { 376 #power-domain-cells = <0>; 377 power-domains = <&CLUSTER_PD>; 378 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 379 }; 380 381 CPU_PD2: power-domain-cpu2 { 382 #power-domain-cells = <0>; 383 power-domains = <&CLUSTER_PD>; 384 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 385 }; 386 387 CPU_PD3: power-domain-cpu3 { 388 #power-domain-cells = <0>; 389 power-domains = <&CLUSTER_PD>; 390 domain-idle-states = <&BIG_CPU_SLEEP_0>; 391 }; 392 393 CPU_PD4: power-domain-cpu4 { 394 #power-domain-cells = <0>; 395 power-domains = <&CLUSTER_PD>; 396 domain-idle-states = <&BIG_CPU_SLEEP_0>; 397 }; 398 399 CPU_PD5: power-domain-cpu5 { 400 #power-domain-cells = <0>; 401 power-domains = <&CLUSTER_PD>; 402 domain-idle-states = <&BIG_CPU_SLEEP_0>; 403 }; 404 405 CPU_PD6: power-domain-cpu6 { 406 #power-domain-cells = <0>; 407 power-domains = <&CLUSTER_PD>; 408 domain-idle-states = <&BIG_CPU_SLEEP_0>; 409 }; 410 411 CPU_PD7: power-domain-cpu7 { 412 #power-domain-cells = <0>; 413 power-domains = <&CLUSTER_PD>; 414 domain-idle-states = <&PRIME_CPU_SLEEP_0>; 415 }; 416 417 CLUSTER_PD: power-domain-cluster { 418 #power-domain-cells = <0>; 419 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 420 }; 421 }; 422 423 reserved_memory: reserved-memory { 424 #address-cells = <2>; 425 #size-cells = <2>; 426 ranges; 427 428 hyp_mem: hyp-region@80000000 { 429 reg = <0 0x80000000 0 0xa00000>; 430 no-map; 431 }; 432 433 cpusys_vm_mem: cpusys-vm-region@80a00000 { 434 reg = <0 0x80a00000 0 0x400000>; 435 no-map; 436 }; 437 438 hyp_tags_mem: hyp-tags-region@80e00000 { 439 reg = <0 0x80e00000 0 0x3d0000>; 440 no-map; 441 }; 442 443 xbl_sc_mem: xbl-sc-region@d8100000 { 444 reg = <0 0xd8100000 0 0x40000>; 445 no-map; 446 }; 447 448 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 449 reg = <0 0x811d0000 0 0x30000>; 450 no-map; 451 }; 452 453 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 454 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 455 reg = <0 0x81a00000 0 0x260000>; 456 no-map; 457 }; 458 459 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 460 compatible = "qcom,cmd-db"; 461 reg = <0 0x81c60000 0 0x20000>; 462 no-map; 463 }; 464 465 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 466 aop_config_merged_mem: aop-config-merged-region@81c80000 { 467 reg = <0 0x81c80000 0 0x74000>; 468 no-map; 469 }; 470 471 /* secdata region can be reused by apps */ 472 smem: smem@81d00000 { 473 compatible = "qcom,smem"; 474 reg = <0 0x81d00000 0 0x200000>; 475 hwlocks = <&tcsr_mutex 3>; 476 no-map; 477 }; 478 479 adsp_mhi_mem: adsp-mhi-region@81f00000 { 480 reg = <0 0x81f00000 0 0x20000>; 481 no-map; 482 }; 483 484 global_sync_mem: global-sync-region@82600000 { 485 reg = <0 0x82600000 0 0x100000>; 486 no-map; 487 }; 488 489 tz_stat_mem: tz-stat-region@82700000 { 490 reg = <0 0x82700000 0 0x100000>; 491 no-map; 492 }; 493 494 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 495 reg = <0 0x82800000 0 0x4600000>; 496 no-map; 497 }; 498 499 mpss_mem: mpss-region@8a800000 { 500 reg = <0 0x8a800000 0 0x10800000>; 501 no-map; 502 }; 503 504 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 505 reg = <0 0x9b000000 0 0x80000>; 506 no-map; 507 }; 508 509 ipa_fw_mem: ipa-fw-region@9b080000 { 510 reg = <0 0x9b080000 0 0x10000>; 511 no-map; 512 }; 513 514 ipa_gsi_mem: ipa-gsi-region@9b090000 { 515 reg = <0 0x9b090000 0 0xa000>; 516 no-map; 517 }; 518 519 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 520 reg = <0 0x9b09a000 0 0x2000>; 521 no-map; 522 }; 523 524 spss_region_mem: spss-region@9b100000 { 525 reg = <0 0x9b100000 0 0x180000>; 526 no-map; 527 }; 528 529 /* First part of the "SPU secure shared memory" region */ 530 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 531 reg = <0 0x9b280000 0 0x60000>; 532 no-map; 533 }; 534 535 /* Second part of the "SPU secure shared memory" region */ 536 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 537 reg = <0 0x9b2e0000 0 0x20000>; 538 no-map; 539 }; 540 541 camera_mem: camera-region@9b300000 { 542 reg = <0 0x9b300000 0 0x800000>; 543 no-map; 544 }; 545 546 video_mem: video-region@9bb00000 { 547 reg = <0 0x9bb00000 0 0x700000>; 548 no-map; 549 }; 550 551 cvp_mem: cvp-region@9c200000 { 552 reg = <0 0x9c200000 0 0x700000>; 553 no-map; 554 }; 555 556 cdsp_mem: cdsp-region@9c900000 { 557 reg = <0 0x9c900000 0 0x2000000>; 558 no-map; 559 }; 560 561 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 562 reg = <0 0x9e900000 0 0x80000>; 563 no-map; 564 }; 565 566 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 567 reg = <0 0x9e980000 0 0x80000>; 568 no-map; 569 }; 570 571 adspslpi_mem: adspslpi-region@9ea00000 { 572 reg = <0 0x9ea00000 0 0x4080000>; 573 no-map; 574 }; 575 576 /* uefi region can be reused by apps */ 577 578 /* Linux kernel image is loaded at 0xa8000000 */ 579 580 rmtfs_mem: rmtfs-region@d4a80000 { 581 compatible = "qcom,rmtfs-mem"; 582 reg = <0x0 0xd4a80000 0x0 0x280000>; 583 no-map; 584 585 qcom,client-id = <1>; 586 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 587 }; 588 589 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 590 reg = <0 0xd4d00000 0 0x3300000>; 591 no-map; 592 }; 593 594 tz_reserved_mem: tz-reserved-region@d8000000 { 595 reg = <0 0xd8000000 0 0x100000>; 596 no-map; 597 }; 598 599 cpucp_fw_mem: cpucp-fw-region@d8140000 { 600 reg = <0 0xd8140000 0 0x1c0000>; 601 no-map; 602 }; 603 604 qtee_mem: qtee-region@d8300000 { 605 reg = <0 0xd8300000 0 0x500000>; 606 no-map; 607 }; 608 609 ta_mem: ta-region@d8800000 { 610 reg = <0 0xd8800000 0 0x8a00000>; 611 no-map; 612 }; 613 614 tz_tags_mem: tz-tags-region@e1200000 { 615 reg = <0 0xe1200000 0 0x2740000>; 616 no-map; 617 }; 618 619 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 620 reg = <0 0xe6440000 0 0x279000>; 621 no-map; 622 }; 623 624 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 625 reg = <0 0xf3600000 0 0x4aee000>; 626 no-map; 627 }; 628 629 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 630 reg = <0 0xf80ee000 0 0x1000>; 631 no-map; 632 }; 633 634 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 635 reg = <0 0xf80ef000 0 0x9000>; 636 no-map; 637 }; 638 639 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 640 reg = <0 0xf80f8000 0 0x4000>; 641 no-map; 642 }; 643 644 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 645 reg = <0 0xf80fc000 0 0x4000>; 646 no-map; 647 }; 648 649 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 650 reg = <0 0xf8100000 0 0x100000>; 651 no-map; 652 }; 653 654 oem_vm_mem: oem-vm-region@f8400000 { 655 reg = <0 0xf8400000 0 0x4800000>; 656 no-map; 657 }; 658 659 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 660 reg = <0 0xfcc00000 0 0x4000>; 661 no-map; 662 }; 663 664 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 665 reg = <0 0xfcc04000 0 0x100000>; 666 no-map; 667 }; 668 669 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 670 reg = <0 0xfce00000 0 0x2900000>; 671 no-map; 672 }; 673 674 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 675 reg = <0 0xff700000 0 0x100000>; 676 no-map; 677 }; 678 }; 679 680 smp2p-adsp { 681 compatible = "qcom,smp2p"; 682 qcom,smem = <443>, <429>; 683 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 684 IPCC_MPROC_SIGNAL_SMP2P 685 IRQ_TYPE_EDGE_RISING>; 686 mboxes = <&ipcc IPCC_CLIENT_LPASS 687 IPCC_MPROC_SIGNAL_SMP2P>; 688 689 qcom,local-pid = <0>; 690 qcom,remote-pid = <2>; 691 692 smp2p_adsp_out: master-kernel { 693 qcom,entry-name = "master-kernel"; 694 #qcom,smem-state-cells = <1>; 695 }; 696 697 smp2p_adsp_in: slave-kernel { 698 qcom,entry-name = "slave-kernel"; 699 interrupt-controller; 700 #interrupt-cells = <2>; 701 }; 702 }; 703 704 smp2p-cdsp { 705 compatible = "qcom,smp2p"; 706 qcom,smem = <94>, <432>; 707 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 708 IPCC_MPROC_SIGNAL_SMP2P 709 IRQ_TYPE_EDGE_RISING>; 710 mboxes = <&ipcc IPCC_CLIENT_CDSP 711 IPCC_MPROC_SIGNAL_SMP2P>; 712 713 qcom,local-pid = <0>; 714 qcom,remote-pid = <5>; 715 716 smp2p_cdsp_out: master-kernel { 717 qcom,entry-name = "master-kernel"; 718 #qcom,smem-state-cells = <1>; 719 }; 720 721 smp2p_cdsp_in: slave-kernel { 722 qcom,entry-name = "slave-kernel"; 723 interrupt-controller; 724 #interrupt-cells = <2>; 725 }; 726 }; 727 728 smp2p-modem { 729 compatible = "qcom,smp2p"; 730 qcom,smem = <435>, <428>; 731 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 732 IPCC_MPROC_SIGNAL_SMP2P 733 IRQ_TYPE_EDGE_RISING>; 734 mboxes = <&ipcc IPCC_CLIENT_MPSS 735 IPCC_MPROC_SIGNAL_SMP2P>; 736 737 qcom,local-pid = <0>; 738 qcom,remote-pid = <1>; 739 740 smp2p_modem_out: master-kernel { 741 qcom,entry-name = "master-kernel"; 742 #qcom,smem-state-cells = <1>; 743 }; 744 745 smp2p_modem_in: slave-kernel { 746 qcom,entry-name = "slave-kernel"; 747 interrupt-controller; 748 #interrupt-cells = <2>; 749 }; 750 751 ipa_smp2p_out: ipa-ap-to-modem { 752 qcom,entry-name = "ipa"; 753 #qcom,smem-state-cells = <1>; 754 }; 755 756 ipa_smp2p_in: ipa-modem-to-ap { 757 qcom,entry-name = "ipa"; 758 interrupt-controller; 759 #interrupt-cells = <2>; 760 }; 761 }; 762 763 soc: soc@0 { 764 compatible = "simple-bus"; 765 ranges = <0 0 0 0 0x10 0>; 766 dma-ranges = <0 0 0 0 0x10 0>; 767 768 #address-cells = <2>; 769 #size-cells = <2>; 770 771 gcc: clock-controller@100000 { 772 compatible = "qcom,sm8550-gcc"; 773 reg = <0 0x00100000 0 0x1f4200>; 774 #clock-cells = <1>; 775 #reset-cells = <1>; 776 #power-domain-cells = <1>; 777 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 778 <&pcie0_phy>, 779 <&pcie1_phy>, 780 <&pcie_1_phy_aux_clk>, 781 <&ufs_mem_phy 0>, 782 <&ufs_mem_phy 1>, 783 <&ufs_mem_phy 2>, 784 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 785 }; 786 787 ipcc: mailbox@408000 { 788 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 789 reg = <0 0x00408000 0 0x1000>; 790 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 791 interrupt-controller; 792 #interrupt-cells = <3>; 793 #mbox-cells = <2>; 794 }; 795 796 gpi_dma2: dma-controller@800000 { 797 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 798 #dma-cells = <3>; 799 reg = <0 0x00800000 0 0x60000>; 800 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 812 dma-channels = <12>; 813 dma-channel-mask = <0x3e>; 814 iommus = <&apps_smmu 0x436 0>; 815 dma-coherent; 816 status = "disabled"; 817 }; 818 819 qupv3_id_1: geniqup@8c0000 { 820 compatible = "qcom,geni-se-qup"; 821 reg = <0 0x008c0000 0 0x2000>; 822 ranges; 823 clock-names = "m-ahb", "s-ahb"; 824 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 825 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 826 iommus = <&apps_smmu 0x423 0>; 827 dma-coherent; 828 #address-cells = <2>; 829 #size-cells = <2>; 830 status = "disabled"; 831 832 i2c8: i2c@880000 { 833 compatible = "qcom,geni-i2c"; 834 reg = <0 0x00880000 0 0x4000>; 835 clock-names = "se"; 836 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&qup_i2c8_data_clk>; 839 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 843 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 844 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 845 interconnect-names = "qup-core", "qup-config", "qup-memory"; 846 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 847 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 848 dma-names = "tx", "rx"; 849 status = "disabled"; 850 }; 851 852 spi8: spi@880000 { 853 compatible = "qcom,geni-spi"; 854 reg = <0 0x00880000 0 0x4000>; 855 clock-names = "se"; 856 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 857 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 858 pinctrl-names = "default"; 859 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 860 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 861 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 862 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 863 interconnect-names = "qup-core", "qup-config", "qup-memory"; 864 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 865 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 866 dma-names = "tx", "rx"; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 status = "disabled"; 870 }; 871 872 i2c9: i2c@884000 { 873 compatible = "qcom,geni-i2c"; 874 reg = <0 0x00884000 0 0x4000>; 875 clock-names = "se"; 876 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 877 pinctrl-names = "default"; 878 pinctrl-0 = <&qup_i2c9_data_clk>; 879 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 883 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 884 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 885 interconnect-names = "qup-core", "qup-config", "qup-memory"; 886 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 887 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 888 dma-names = "tx", "rx"; 889 status = "disabled"; 890 }; 891 892 spi9: spi@884000 { 893 compatible = "qcom,geni-spi"; 894 reg = <0 0x00884000 0 0x4000>; 895 clock-names = "se"; 896 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 897 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 898 pinctrl-names = "default"; 899 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 900 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 901 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 902 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 903 interconnect-names = "qup-core", "qup-config", "qup-memory"; 904 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 905 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 906 dma-names = "tx", "rx"; 907 #address-cells = <1>; 908 #size-cells = <0>; 909 status = "disabled"; 910 }; 911 912 i2c10: i2c@888000 { 913 compatible = "qcom,geni-i2c"; 914 reg = <0 0x00888000 0 0x4000>; 915 clock-names = "se"; 916 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 917 pinctrl-names = "default"; 918 pinctrl-0 = <&qup_i2c10_data_clk>; 919 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 923 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 924 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 925 interconnect-names = "qup-core", "qup-config", "qup-memory"; 926 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 927 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 928 dma-names = "tx", "rx"; 929 status = "disabled"; 930 }; 931 932 spi10: spi@888000 { 933 compatible = "qcom,geni-spi"; 934 reg = <0 0x00888000 0 0x4000>; 935 clock-names = "se"; 936 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 937 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 938 pinctrl-names = "default"; 939 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 940 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 941 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 942 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 943 interconnect-names = "qup-core", "qup-config", "qup-memory"; 944 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 945 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 946 dma-names = "tx", "rx"; 947 #address-cells = <1>; 948 #size-cells = <0>; 949 status = "disabled"; 950 }; 951 952 i2c11: i2c@88c000 { 953 compatible = "qcom,geni-i2c"; 954 reg = <0 0x0088c000 0 0x4000>; 955 clock-names = "se"; 956 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 957 pinctrl-names = "default"; 958 pinctrl-0 = <&qup_i2c11_data_clk>; 959 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 963 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 964 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 965 interconnect-names = "qup-core", "qup-config", "qup-memory"; 966 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 967 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 968 dma-names = "tx", "rx"; 969 status = "disabled"; 970 }; 971 972 spi11: spi@88c000 { 973 compatible = "qcom,geni-spi"; 974 reg = <0 0x0088c000 0 0x4000>; 975 clock-names = "se"; 976 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 977 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 978 pinctrl-names = "default"; 979 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 980 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 981 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 982 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 983 interconnect-names = "qup-core", "qup-config", "qup-memory"; 984 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 985 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 986 dma-names = "tx", "rx"; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 status = "disabled"; 990 }; 991 992 i2c12: i2c@890000 { 993 compatible = "qcom,geni-i2c"; 994 reg = <0 0x00890000 0 0x4000>; 995 clock-names = "se"; 996 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&qup_i2c12_data_clk>; 999 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1003 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1004 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1005 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1006 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1007 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1008 dma-names = "tx", "rx"; 1009 status = "disabled"; 1010 }; 1011 1012 spi12: spi@890000 { 1013 compatible = "qcom,geni-spi"; 1014 reg = <0 0x00890000 0 0x4000>; 1015 clock-names = "se"; 1016 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1017 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1020 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1021 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1022 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1023 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1024 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1025 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1026 dma-names = "tx", "rx"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 status = "disabled"; 1030 }; 1031 1032 i2c13: i2c@894000 { 1033 compatible = "qcom,geni-i2c"; 1034 reg = <0 0x00894000 0 0x4000>; 1035 clock-names = "se"; 1036 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&qup_i2c13_data_clk>; 1039 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1043 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1044 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1045 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1046 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1047 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1048 dma-names = "tx", "rx"; 1049 status = "disabled"; 1050 }; 1051 1052 spi13: spi@894000 { 1053 compatible = "qcom,geni-spi"; 1054 reg = <0 0x00894000 0 0x4000>; 1055 clock-names = "se"; 1056 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1057 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1060 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1061 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1062 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1063 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1064 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1065 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1066 dma-names = "tx", "rx"; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 uart14: serial@898000 { 1073 compatible = "qcom,geni-uart"; 1074 reg = <0 0x898000 0 0x4000>; 1075 clock-names = "se"; 1076 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1077 pinctrl-names = "default"; 1078 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1079 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1080 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1081 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1082 interconnect-names = "qup-core", "qup-config"; 1083 status = "disabled"; 1084 }; 1085 1086 i2c15: i2c@89c000 { 1087 compatible = "qcom,geni-i2c"; 1088 reg = <0 0x0089c000 0 0x4000>; 1089 clock-names = "se"; 1090 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1091 pinctrl-names = "default"; 1092 pinctrl-0 = <&qup_i2c15_data_clk>; 1093 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1097 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1098 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1099 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1100 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1101 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1102 dma-names = "tx", "rx"; 1103 status = "disabled"; 1104 }; 1105 1106 spi15: spi@89c000 { 1107 compatible = "qcom,geni-spi"; 1108 reg = <0 0x0089c000 0 0x4000>; 1109 clock-names = "se"; 1110 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1111 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1114 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1115 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1116 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1117 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1118 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1119 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1120 dma-names = "tx", "rx"; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 }; 1126 1127 i2c_master_hub_0: geniqup@9c0000 { 1128 compatible = "qcom,geni-se-i2c-master-hub"; 1129 reg = <0x0 0x009c0000 0x0 0x2000>; 1130 clock-names = "s-ahb"; 1131 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1132 #address-cells = <2>; 1133 #size-cells = <2>; 1134 ranges; 1135 status = "disabled"; 1136 1137 i2c_hub_0: i2c@980000 { 1138 compatible = "qcom,geni-i2c-master-hub"; 1139 reg = <0x0 0x00980000 0x0 0x4000>; 1140 clock-names = "se", "core"; 1141 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1142 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1143 pinctrl-names = "default"; 1144 pinctrl-0 = <&hub_i2c0_data_clk>; 1145 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1149 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1150 interconnect-names = "qup-core", "qup-config"; 1151 status = "disabled"; 1152 }; 1153 1154 i2c_hub_1: i2c@984000 { 1155 compatible = "qcom,geni-i2c-master-hub"; 1156 reg = <0x0 0x00984000 0x0 0x4000>; 1157 clock-names = "se", "core"; 1158 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1159 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1160 pinctrl-names = "default"; 1161 pinctrl-0 = <&hub_i2c1_data_clk>; 1162 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1166 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1167 interconnect-names = "qup-core", "qup-config"; 1168 status = "disabled"; 1169 }; 1170 1171 i2c_hub_2: i2c@988000 { 1172 compatible = "qcom,geni-i2c-master-hub"; 1173 reg = <0x0 0x00988000 0x0 0x4000>; 1174 clock-names = "se", "core"; 1175 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1176 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1177 pinctrl-names = "default"; 1178 pinctrl-0 = <&hub_i2c2_data_clk>; 1179 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1183 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1184 interconnect-names = "qup-core", "qup-config"; 1185 status = "disabled"; 1186 }; 1187 1188 i2c_hub_3: i2c@98c000 { 1189 compatible = "qcom,geni-i2c-master-hub"; 1190 reg = <0x0 0x0098c000 0x0 0x4000>; 1191 clock-names = "se", "core"; 1192 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1193 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&hub_i2c3_data_clk>; 1196 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1200 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1201 interconnect-names = "qup-core", "qup-config"; 1202 status = "disabled"; 1203 }; 1204 1205 i2c_hub_4: i2c@990000 { 1206 compatible = "qcom,geni-i2c-master-hub"; 1207 reg = <0x0 0x00990000 0x0 0x4000>; 1208 clock-names = "se", "core"; 1209 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1210 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&hub_i2c4_data_clk>; 1213 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1217 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1218 interconnect-names = "qup-core", "qup-config"; 1219 status = "disabled"; 1220 }; 1221 1222 i2c_hub_5: i2c@994000 { 1223 compatible = "qcom,geni-i2c-master-hub"; 1224 reg = <0 0x00994000 0 0x4000>; 1225 clock-names = "se", "core"; 1226 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1227 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1228 pinctrl-names = "default"; 1229 pinctrl-0 = <&hub_i2c5_data_clk>; 1230 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1234 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1235 interconnect-names = "qup-core", "qup-config"; 1236 status = "disabled"; 1237 }; 1238 1239 i2c_hub_6: i2c@998000 { 1240 compatible = "qcom,geni-i2c-master-hub"; 1241 reg = <0 0x00998000 0 0x4000>; 1242 clock-names = "se", "core"; 1243 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1244 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1245 pinctrl-names = "default"; 1246 pinctrl-0 = <&hub_i2c6_data_clk>; 1247 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1251 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1252 interconnect-names = "qup-core", "qup-config"; 1253 status = "disabled"; 1254 }; 1255 1256 i2c_hub_7: i2c@99c000 { 1257 compatible = "qcom,geni-i2c-master-hub"; 1258 reg = <0 0x0099c000 0 0x4000>; 1259 clock-names = "se", "core"; 1260 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1261 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1262 pinctrl-names = "default"; 1263 pinctrl-0 = <&hub_i2c7_data_clk>; 1264 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1268 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1269 interconnect-names = "qup-core", "qup-config"; 1270 status = "disabled"; 1271 }; 1272 1273 i2c_hub_8: i2c@9a0000 { 1274 compatible = "qcom,geni-i2c-master-hub"; 1275 reg = <0 0x009a0000 0 0x4000>; 1276 clock-names = "se", "core"; 1277 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1278 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&hub_i2c8_data_clk>; 1281 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1285 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1286 interconnect-names = "qup-core", "qup-config"; 1287 status = "disabled"; 1288 }; 1289 1290 i2c_hub_9: i2c@9a4000 { 1291 compatible = "qcom,geni-i2c-master-hub"; 1292 reg = <0 0x009a4000 0 0x4000>; 1293 clock-names = "se", "core"; 1294 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1295 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1296 pinctrl-names = "default"; 1297 pinctrl-0 = <&hub_i2c9_data_clk>; 1298 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1302 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1303 interconnect-names = "qup-core", "qup-config"; 1304 status = "disabled"; 1305 }; 1306 }; 1307 1308 gpi_dma1: dma-controller@a00000 { 1309 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1310 #dma-cells = <3>; 1311 reg = <0 0x00a00000 0 0x60000>; 1312 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1313 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1319 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1320 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1324 dma-channels = <12>; 1325 dma-channel-mask = <0x1e>; 1326 iommus = <&apps_smmu 0xb6 0>; 1327 dma-coherent; 1328 status = "disabled"; 1329 }; 1330 1331 qupv3_id_0: geniqup@ac0000 { 1332 compatible = "qcom,geni-se-qup"; 1333 reg = <0 0x00ac0000 0 0x2000>; 1334 ranges; 1335 clock-names = "m-ahb", "s-ahb"; 1336 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1337 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1338 iommus = <&apps_smmu 0xa3 0>; 1339 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1340 interconnect-names = "qup-core"; 1341 dma-coherent; 1342 #address-cells = <2>; 1343 #size-cells = <2>; 1344 status = "disabled"; 1345 1346 i2c0: i2c@a80000 { 1347 compatible = "qcom,geni-i2c"; 1348 reg = <0 0x00a80000 0 0x4000>; 1349 clock-names = "se"; 1350 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1351 pinctrl-names = "default"; 1352 pinctrl-0 = <&qup_i2c0_data_clk>; 1353 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1357 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1358 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1359 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1360 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1361 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1362 dma-names = "tx", "rx"; 1363 status = "disabled"; 1364 }; 1365 1366 spi0: spi@a80000 { 1367 compatible = "qcom,geni-spi"; 1368 reg = <0 0x00a80000 0 0x4000>; 1369 clock-names = "se"; 1370 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1371 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1372 pinctrl-names = "default"; 1373 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1374 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1375 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1376 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1377 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1378 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1379 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1380 dma-names = "tx", "rx"; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 status = "disabled"; 1384 }; 1385 1386 i2c1: i2c@a84000 { 1387 compatible = "qcom,geni-i2c"; 1388 reg = <0 0x00a84000 0 0x4000>; 1389 clock-names = "se"; 1390 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_i2c1_data_clk>; 1393 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1397 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1398 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1399 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1400 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1401 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1402 dma-names = "tx", "rx"; 1403 status = "disabled"; 1404 }; 1405 1406 spi1: spi@a84000 { 1407 compatible = "qcom,geni-spi"; 1408 reg = <0 0x00a84000 0 0x4000>; 1409 clock-names = "se"; 1410 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1411 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1412 pinctrl-names = "default"; 1413 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1414 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1415 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1416 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1417 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1418 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1419 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1420 dma-names = "tx", "rx"; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 status = "disabled"; 1424 }; 1425 1426 i2c2: i2c@a88000 { 1427 compatible = "qcom,geni-i2c"; 1428 reg = <0 0x00a88000 0 0x4000>; 1429 clock-names = "se"; 1430 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1431 pinctrl-names = "default"; 1432 pinctrl-0 = <&qup_i2c2_data_clk>; 1433 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1437 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1438 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1439 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1440 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1441 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1442 dma-names = "tx", "rx"; 1443 status = "disabled"; 1444 }; 1445 1446 spi2: spi@a88000 { 1447 compatible = "qcom,geni-spi"; 1448 reg = <0 0x00a88000 0 0x4000>; 1449 clock-names = "se"; 1450 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1451 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1452 pinctrl-names = "default"; 1453 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1454 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1455 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1456 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1457 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1458 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1459 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1460 dma-names = "tx", "rx"; 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 status = "disabled"; 1464 }; 1465 1466 i2c3: i2c@a8c000 { 1467 compatible = "qcom,geni-i2c"; 1468 reg = <0 0x00a8c000 0 0x4000>; 1469 clock-names = "se"; 1470 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1471 pinctrl-names = "default"; 1472 pinctrl-0 = <&qup_i2c3_data_clk>; 1473 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1477 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1478 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1479 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1480 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1481 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1482 dma-names = "tx", "rx"; 1483 status = "disabled"; 1484 }; 1485 1486 spi3: spi@a8c000 { 1487 compatible = "qcom,geni-spi"; 1488 reg = <0 0x00a8c000 0 0x4000>; 1489 clock-names = "se"; 1490 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1491 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1492 pinctrl-names = "default"; 1493 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1494 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1495 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1496 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1497 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1498 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1499 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1500 dma-names = "tx", "rx"; 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 status = "disabled"; 1504 }; 1505 1506 i2c4: i2c@a90000 { 1507 compatible = "qcom,geni-i2c"; 1508 reg = <0 0x00a90000 0 0x4000>; 1509 clock-names = "se"; 1510 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&qup_i2c4_data_clk>; 1513 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1514 #address-cells = <1>; 1515 #size-cells = <0>; 1516 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1517 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1518 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1519 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1520 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1521 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1522 dma-names = "tx", "rx"; 1523 status = "disabled"; 1524 }; 1525 1526 spi4: spi@a90000 { 1527 compatible = "qcom,geni-spi"; 1528 reg = <0 0x00a90000 0 0x4000>; 1529 clock-names = "se"; 1530 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1531 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1532 pinctrl-names = "default"; 1533 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1534 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1535 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1536 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1537 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1538 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1539 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1540 dma-names = "tx", "rx"; 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 status = "disabled"; 1544 }; 1545 1546 i2c5: i2c@a94000 { 1547 compatible = "qcom,geni-i2c"; 1548 reg = <0 0x00a94000 0 0x4000>; 1549 clock-names = "se"; 1550 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1551 pinctrl-names = "default"; 1552 pinctrl-0 = <&qup_i2c5_data_clk>; 1553 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1554 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1555 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1556 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1557 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1558 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1559 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1560 dma-names = "tx", "rx"; 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 status = "disabled"; 1564 }; 1565 1566 spi5: spi@a94000 { 1567 compatible = "qcom,geni-spi"; 1568 reg = <0 0x00a94000 0 0x4000>; 1569 clock-names = "se"; 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1571 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1572 pinctrl-names = "default"; 1573 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1574 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1575 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1576 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1577 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1578 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1579 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1580 dma-names = "tx", "rx"; 1581 #address-cells = <1>; 1582 #size-cells = <0>; 1583 status = "disabled"; 1584 }; 1585 1586 i2c6: i2c@a98000 { 1587 compatible = "qcom,geni-i2c"; 1588 reg = <0 0x00a98000 0 0x4000>; 1589 clock-names = "se"; 1590 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1591 pinctrl-names = "default"; 1592 pinctrl-0 = <&qup_i2c6_data_clk>; 1593 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1594 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1595 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1596 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1597 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1598 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1599 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1600 dma-names = "tx", "rx"; 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 status = "disabled"; 1604 }; 1605 1606 spi6: spi@a98000 { 1607 compatible = "qcom,geni-spi"; 1608 reg = <0 0x00a98000 0 0x4000>; 1609 clock-names = "se"; 1610 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1611 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1612 pinctrl-names = "default"; 1613 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1614 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1615 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1616 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1617 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1618 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1619 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1620 dma-names = "tx", "rx"; 1621 #address-cells = <1>; 1622 #size-cells = <0>; 1623 status = "disabled"; 1624 }; 1625 1626 uart7: serial@a9c000 { 1627 compatible = "qcom,geni-debug-uart"; 1628 reg = <0 0x00a9c000 0 0x4000>; 1629 clock-names = "se"; 1630 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1631 pinctrl-names = "default"; 1632 pinctrl-0 = <&qup_uart7_default>; 1633 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1634 interconnect-names = "qup-core", "qup-config"; 1635 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1636 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1637 status = "disabled"; 1638 }; 1639 }; 1640 1641 cnoc_main: interconnect@1500000 { 1642 compatible = "qcom,sm8550-cnoc-main"; 1643 reg = <0 0x01500000 0 0x13080>; 1644 #interconnect-cells = <2>; 1645 qcom,bcm-voters = <&apps_bcm_voter>; 1646 }; 1647 1648 config_noc: interconnect@1600000 { 1649 compatible = "qcom,sm8550-config-noc"; 1650 reg = <0 0x01600000 0 0x6200>; 1651 #interconnect-cells = <2>; 1652 qcom,bcm-voters = <&apps_bcm_voter>; 1653 }; 1654 1655 system_noc: interconnect@1680000 { 1656 compatible = "qcom,sm8550-system-noc"; 1657 reg = <0 0x01680000 0 0x1d080>; 1658 #interconnect-cells = <2>; 1659 qcom,bcm-voters = <&apps_bcm_voter>; 1660 }; 1661 1662 pcie_noc: interconnect@16c0000 { 1663 compatible = "qcom,sm8550-pcie-anoc"; 1664 reg = <0 0x016c0000 0 0x12200>; 1665 #interconnect-cells = <2>; 1666 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1667 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1668 qcom,bcm-voters = <&apps_bcm_voter>; 1669 }; 1670 1671 aggre1_noc: interconnect@16e0000 { 1672 compatible = "qcom,sm8550-aggre1-noc"; 1673 reg = <0 0x016e0000 0 0x14400>; 1674 #interconnect-cells = <2>; 1675 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1676 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1677 qcom,bcm-voters = <&apps_bcm_voter>; 1678 }; 1679 1680 aggre2_noc: interconnect@1700000 { 1681 compatible = "qcom,sm8550-aggre2-noc"; 1682 reg = <0 0x01700000 0 0x1e400>; 1683 #interconnect-cells = <2>; 1684 clocks = <&rpmhcc RPMH_IPA_CLK>; 1685 qcom,bcm-voters = <&apps_bcm_voter>; 1686 }; 1687 1688 mmss_noc: interconnect@1780000 { 1689 compatible = "qcom,sm8550-mmss-noc"; 1690 reg = <0 0x01780000 0 0x5b800>; 1691 #interconnect-cells = <2>; 1692 qcom,bcm-voters = <&apps_bcm_voter>; 1693 }; 1694 1695 rng: rng@10c3000 { 1696 compatible = "qcom,sm8550-trng", "qcom,trng"; 1697 reg = <0 0x010c3000 0 0x1000>; 1698 }; 1699 1700 pcie0: pcie@1c00000 { 1701 device_type = "pci"; 1702 compatible = "qcom,pcie-sm8550"; 1703 reg = <0 0x01c00000 0 0x3000>, 1704 <0 0x60000000 0 0xf1d>, 1705 <0 0x60000f20 0 0xa8>, 1706 <0 0x60001000 0 0x1000>, 1707 <0 0x60100000 0 0x100000>; 1708 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1709 #address-cells = <3>; 1710 #size-cells = <2>; 1711 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1712 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1713 bus-range = <0x00 0xff>; 1714 1715 dma-coherent; 1716 1717 linux,pci-domain = <0>; 1718 num-lanes = <2>; 1719 1720 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1728 interrupt-names = "msi0", 1729 "msi1", 1730 "msi2", 1731 "msi3", 1732 "msi4", 1733 "msi5", 1734 "msi6", 1735 "msi7"; 1736 #interrupt-cells = <1>; 1737 interrupt-map-mask = <0 0 0 0x7>; 1738 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1739 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1740 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1741 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1742 1743 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1744 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1745 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1746 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1747 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1748 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1749 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1750 clock-names = "aux", 1751 "cfg", 1752 "bus_master", 1753 "bus_slave", 1754 "slave_q2a", 1755 "ddrss_sf_tbu", 1756 "noc_aggr"; 1757 1758 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 1759 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; 1760 interconnect-names = "pcie-mem", "cpu-pcie"; 1761 1762 /* Entries are reversed due to the unusual ITS DeviceID encoding */ 1763 msi-map = <0x0 &gic_its 0x1401 0x1>, 1764 <0x100 &gic_its 0x1400 0x1>; 1765 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 1766 <0x100 &apps_smmu 0x1401 0x1>; 1767 1768 resets = <&gcc GCC_PCIE_0_BCR>; 1769 reset-names = "pci"; 1770 1771 power-domains = <&gcc PCIE_0_GDSC>; 1772 1773 phys = <&pcie0_phy>; 1774 phy-names = "pciephy"; 1775 1776 status = "disabled"; 1777 1778 pcie@0 { 1779 device_type = "pci"; 1780 reg = <0x0 0x0 0x0 0x0 0x0>; 1781 bus-range = <0x01 0xff>; 1782 1783 #address-cells = <3>; 1784 #size-cells = <2>; 1785 ranges; 1786 }; 1787 }; 1788 1789 pcie0_phy: phy@1c06000 { 1790 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 1791 reg = <0 0x01c06000 0 0x2000>; 1792 1793 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1794 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1795 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1796 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1797 <&gcc GCC_PCIE_0_PIPE_CLK>; 1798 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1799 "pipe"; 1800 1801 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1802 reset-names = "phy"; 1803 1804 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1805 assigned-clock-rates = <100000000>; 1806 1807 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1808 1809 #clock-cells = <0>; 1810 clock-output-names = "pcie0_pipe_clk"; 1811 1812 #phy-cells = <0>; 1813 1814 status = "disabled"; 1815 }; 1816 1817 pcie1: pcie@1c08000 { 1818 device_type = "pci"; 1819 compatible = "qcom,pcie-sm8550"; 1820 reg = <0x0 0x01c08000 0x0 0x3000>, 1821 <0x0 0x40000000 0x0 0xf1d>, 1822 <0x0 0x40000f20 0x0 0xa8>, 1823 <0x0 0x40001000 0x0 0x1000>, 1824 <0x0 0x40100000 0x0 0x100000>; 1825 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1826 #address-cells = <3>; 1827 #size-cells = <2>; 1828 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1829 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1830 bus-range = <0x00 0xff>; 1831 1832 dma-coherent; 1833 1834 linux,pci-domain = <1>; 1835 num-lanes = <2>; 1836 1837 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1845 interrupt-names = "msi0", 1846 "msi1", 1847 "msi2", 1848 "msi3", 1849 "msi4", 1850 "msi5", 1851 "msi6", 1852 "msi7"; 1853 #interrupt-cells = <1>; 1854 interrupt-map-mask = <0 0 0 0x7>; 1855 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1856 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1857 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1858 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1859 1860 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1861 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1862 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1863 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1864 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1865 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1866 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1867 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 1868 clock-names = "aux", 1869 "cfg", 1870 "bus_master", 1871 "bus_slave", 1872 "slave_q2a", 1873 "ddrss_sf_tbu", 1874 "noc_aggr", 1875 "cnoc_sf_axi"; 1876 1877 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1878 assigned-clock-rates = <19200000>; 1879 1880 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 1881 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; 1882 interconnect-names = "pcie-mem", "cpu-pcie"; 1883 1884 /* Entries are reversed due to the unusual ITS DeviceID encoding */ 1885 msi-map = <0x0 &gic_its 0x1481 0x1>, 1886 <0x100 &gic_its 0x1480 0x1>; 1887 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 1888 <0x100 &apps_smmu 0x1481 0x1>; 1889 1890 resets = <&gcc GCC_PCIE_1_BCR>, 1891 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1892 reset-names = "pci", "link_down"; 1893 1894 power-domains = <&gcc PCIE_1_GDSC>; 1895 1896 phys = <&pcie1_phy>; 1897 phy-names = "pciephy"; 1898 1899 status = "disabled"; 1900 1901 pcie@0 { 1902 device_type = "pci"; 1903 reg = <0x0 0x0 0x0 0x0 0x0>; 1904 bus-range = <0x01 0xff>; 1905 1906 #address-cells = <3>; 1907 #size-cells = <2>; 1908 ranges; 1909 }; 1910 }; 1911 1912 pcie1_phy: phy@1c0e000 { 1913 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 1914 reg = <0x0 0x01c0e000 0x0 0x2000>; 1915 1916 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1917 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1918 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1919 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1920 <&gcc GCC_PCIE_1_PIPE_CLK>; 1921 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1922 "pipe"; 1923 1924 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 1925 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 1926 reset-names = "phy", "phy_nocsr"; 1927 1928 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1929 assigned-clock-rates = <100000000>; 1930 1931 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1932 1933 #clock-cells = <0>; 1934 clock-output-names = "pcie1_pipe_clk"; 1935 1936 #phy-cells = <0>; 1937 1938 status = "disabled"; 1939 }; 1940 1941 cryptobam: dma-controller@1dc4000 { 1942 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1943 reg = <0x0 0x01dc4000 0x0 0x28000>; 1944 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1945 #dma-cells = <1>; 1946 qcom,ee = <0>; 1947 qcom,controlled-remotely; 1948 iommus = <&apps_smmu 0x480 0x0>, 1949 <&apps_smmu 0x481 0x0>; 1950 }; 1951 1952 crypto: crypto@1dfa000 { 1953 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 1954 reg = <0x0 0x01dfa000 0x0 0x6000>; 1955 dmas = <&cryptobam 4>, <&cryptobam 5>; 1956 dma-names = "rx", "tx"; 1957 iommus = <&apps_smmu 0x480 0x0>, 1958 <&apps_smmu 0x481 0x0>; 1959 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1960 interconnect-names = "memory"; 1961 }; 1962 1963 ufs_mem_phy: phy@1d80000 { 1964 compatible = "qcom,sm8550-qmp-ufs-phy"; 1965 reg = <0x0 0x01d80000 0x0 0x2000>; 1966 clocks = <&rpmhcc RPMH_CXO_CLK>, 1967 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1968 <&tcsr TCSR_UFS_CLKREF_EN>; 1969 clock-names = "ref", 1970 "ref_aux", 1971 "qref"; 1972 1973 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1974 1975 resets = <&ufs_mem_hc 0>; 1976 reset-names = "ufsphy"; 1977 1978 #clock-cells = <1>; 1979 #phy-cells = <0>; 1980 1981 status = "disabled"; 1982 }; 1983 1984 ufs_mem_hc: ufs@1d84000 { 1985 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 1986 "jedec,ufs-2.0"; 1987 reg = <0x0 0x01d84000 0x0 0x3000>; 1988 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1989 phys = <&ufs_mem_phy>; 1990 phy-names = "ufsphy"; 1991 lanes-per-direction = <2>; 1992 #reset-cells = <1>; 1993 resets = <&gcc GCC_UFS_PHY_BCR>; 1994 reset-names = "rst"; 1995 1996 power-domains = <&gcc UFS_PHY_GDSC>; 1997 required-opps = <&rpmhpd_opp_nom>; 1998 1999 iommus = <&apps_smmu 0x60 0x0>; 2000 dma-coherent; 2001 2002 operating-points-v2 = <&ufs_opp_table>; 2003 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 2004 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2005 2006 interconnect-names = "ufs-ddr", "cpu-ufs"; 2007 clock-names = "core_clk", 2008 "bus_aggr_clk", 2009 "iface_clk", 2010 "core_clk_unipro", 2011 "ref_clk", 2012 "tx_lane0_sync_clk", 2013 "rx_lane0_sync_clk", 2014 "rx_lane1_sync_clk"; 2015 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2016 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2017 <&gcc GCC_UFS_PHY_AHB_CLK>, 2018 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2019 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 2020 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2021 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2022 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2023 qcom,ice = <&ice>; 2024 2025 status = "disabled"; 2026 2027 ufs_opp_table: opp-table { 2028 compatible = "operating-points-v2"; 2029 2030 opp-75000000 { 2031 opp-hz = /bits/ 64 <75000000>, 2032 /bits/ 64 <0>, 2033 /bits/ 64 <0>, 2034 /bits/ 64 <75000000>, 2035 /bits/ 64 <0>, 2036 /bits/ 64 <0>, 2037 /bits/ 64 <0>, 2038 /bits/ 64 <0>; 2039 required-opps = <&rpmhpd_opp_low_svs>; 2040 }; 2041 2042 opp-150000000 { 2043 opp-hz = /bits/ 64 <150000000>, 2044 /bits/ 64 <0>, 2045 /bits/ 64 <0>, 2046 /bits/ 64 <150000000>, 2047 /bits/ 64 <0>, 2048 /bits/ 64 <0>, 2049 /bits/ 64 <0>, 2050 /bits/ 64 <0>; 2051 required-opps = <&rpmhpd_opp_svs>; 2052 }; 2053 2054 opp-300000000 { 2055 opp-hz = /bits/ 64 <300000000>, 2056 /bits/ 64 <0>, 2057 /bits/ 64 <0>, 2058 /bits/ 64 <300000000>, 2059 /bits/ 64 <0>, 2060 /bits/ 64 <0>, 2061 /bits/ 64 <0>, 2062 /bits/ 64 <0>; 2063 required-opps = <&rpmhpd_opp_nom>; 2064 }; 2065 }; 2066 }; 2067 2068 ice: crypto@1d88000 { 2069 compatible = "qcom,sm8550-inline-crypto-engine", 2070 "qcom,inline-crypto-engine"; 2071 reg = <0 0x01d88000 0 0x8000>; 2072 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2073 }; 2074 2075 tcsr_mutex: hwlock@1f40000 { 2076 compatible = "qcom,tcsr-mutex"; 2077 reg = <0 0x01f40000 0 0x20000>; 2078 #hwlock-cells = <1>; 2079 }; 2080 2081 tcsr: clock-controller@1fc0000 { 2082 compatible = "qcom,sm8550-tcsr", "syscon"; 2083 reg = <0 0x01fc0000 0 0x30000>; 2084 clocks = <&rpmhcc RPMH_CXO_CLK>; 2085 #clock-cells = <1>; 2086 #reset-cells = <1>; 2087 }; 2088 2089 gpu: gpu@3d00000 { 2090 compatible = "qcom,adreno-43050a01", "qcom,adreno"; 2091 reg = <0x0 0x03d00000 0x0 0x40000>, 2092 <0x0 0x03d9e000 0x0 0x1000>, 2093 <0x0 0x03d61000 0x0 0x800>; 2094 reg-names = "kgsl_3d0_reg_memory", 2095 "cx_mem", 2096 "cx_dbgc"; 2097 2098 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2099 2100 iommus = <&adreno_smmu 0 0x0>, 2101 <&adreno_smmu 1 0x0>; 2102 2103 operating-points-v2 = <&gpu_opp_table>; 2104 2105 qcom,gmu = <&gmu>; 2106 #cooling-cells = <2>; 2107 2108 status = "disabled"; 2109 2110 zap-shader { 2111 memory-region = <&gpu_micro_code_mem>; 2112 }; 2113 2114 /* Speedbin needs more work on A740+, keep only lower freqs */ 2115 gpu_opp_table: opp-table { 2116 compatible = "operating-points-v2"; 2117 2118 opp-680000000 { 2119 opp-hz = /bits/ 64 <680000000>; 2120 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2121 }; 2122 2123 opp-615000000 { 2124 opp-hz = /bits/ 64 <615000000>; 2125 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2126 }; 2127 2128 opp-550000000 { 2129 opp-hz = /bits/ 64 <550000000>; 2130 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2131 }; 2132 2133 opp-475000000 { 2134 opp-hz = /bits/ 64 <475000000>; 2135 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2136 }; 2137 2138 opp-401000000 { 2139 opp-hz = /bits/ 64 <401000000>; 2140 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2141 }; 2142 2143 opp-348000000 { 2144 opp-hz = /bits/ 64 <348000000>; 2145 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 2146 }; 2147 2148 opp-295000000 { 2149 opp-hz = /bits/ 64 <295000000>; 2150 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2151 }; 2152 2153 opp-220000000 { 2154 opp-hz = /bits/ 64 <220000000>; 2155 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 2156 }; 2157 }; 2158 }; 2159 2160 gmu: gmu@3d6a000 { 2161 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu"; 2162 reg = <0x0 0x03d6a000 0x0 0x35000>, 2163 <0x0 0x03d50000 0x0 0x10000>, 2164 <0x0 0x0b280000 0x0 0x10000>; 2165 reg-names = "gmu", "rscc", "gmu_pdc"; 2166 2167 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2169 interrupt-names = "hfi", "gmu"; 2170 2171 clocks = <&gpucc GPU_CC_AHB_CLK>, 2172 <&gpucc GPU_CC_CX_GMU_CLK>, 2173 <&gpucc GPU_CC_CXO_CLK>, 2174 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2175 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2176 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2177 <&gpucc GPU_CC_DEMET_CLK>; 2178 clock-names = "ahb", 2179 "gmu", 2180 "cxo", 2181 "axi", 2182 "memnoc", 2183 "hub", 2184 "demet"; 2185 2186 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2187 <&gpucc GPU_CC_GX_GDSC>; 2188 power-domain-names = "cx", 2189 "gx"; 2190 2191 iommus = <&adreno_smmu 5 0x0>; 2192 2193 qcom,qmp = <&aoss_qmp>; 2194 2195 operating-points-v2 = <&gmu_opp_table>; 2196 2197 gmu_opp_table: opp-table { 2198 compatible = "operating-points-v2"; 2199 2200 opp-500000000 { 2201 opp-hz = /bits/ 64 <500000000>; 2202 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2203 }; 2204 2205 opp-200000000 { 2206 opp-hz = /bits/ 64 <200000000>; 2207 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2208 }; 2209 }; 2210 }; 2211 2212 gpucc: clock-controller@3d90000 { 2213 compatible = "qcom,sm8550-gpucc"; 2214 reg = <0 0x03d90000 0 0xa000>; 2215 clocks = <&bi_tcxo_div2>, 2216 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2217 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2218 #clock-cells = <1>; 2219 #reset-cells = <1>; 2220 #power-domain-cells = <1>; 2221 }; 2222 2223 adreno_smmu: iommu@3da0000 { 2224 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", 2225 "qcom,smmu-500", "arm,mmu-500"; 2226 reg = <0x0 0x03da0000 0x0 0x40000>; 2227 #iommu-cells = <2>; 2228 #global-interrupts = <1>; 2229 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>, 2231 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2236 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2237 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2238 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2239 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2240 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2241 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2242 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2243 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2244 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2245 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2246 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2247 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2248 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2249 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2250 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2251 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2252 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2253 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2254 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 2255 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2256 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2257 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2258 <&gpucc GPU_CC_AHB_CLK>; 2259 clock-names = "hlos", 2260 "bus", 2261 "iface", 2262 "ahb"; 2263 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2264 dma-coherent; 2265 }; 2266 2267 ipa: ipa@3f40000 { 2268 compatible = "qcom,sm8550-ipa"; 2269 2270 iommus = <&apps_smmu 0x4a0 0x0>, 2271 <&apps_smmu 0x4a2 0x0>; 2272 reg = <0 0x3f40000 0 0x10000>, 2273 <0 0x3f50000 0 0x5000>, 2274 <0 0x3e04000 0 0xfc000>; 2275 reg-names = "ipa-reg", 2276 "ipa-shared", 2277 "gsi"; 2278 2279 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2280 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2281 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2282 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2283 interrupt-names = "ipa", 2284 "gsi", 2285 "ipa-clock-query", 2286 "ipa-setup-ready"; 2287 2288 clocks = <&rpmhcc RPMH_IPA_CLK>; 2289 clock-names = "core"; 2290 2291 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2292 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2293 interconnect-names = "memory", 2294 "config"; 2295 2296 qcom,qmp = <&aoss_qmp>; 2297 2298 qcom,smem-states = <&ipa_smp2p_out 0>, 2299 <&ipa_smp2p_out 1>; 2300 qcom,smem-state-names = "ipa-clock-enabled-valid", 2301 "ipa-clock-enabled"; 2302 2303 status = "disabled"; 2304 }; 2305 2306 remoteproc_mpss: remoteproc@4080000 { 2307 compatible = "qcom,sm8550-mpss-pas"; 2308 reg = <0x0 0x04080000 0x0 0x4040>; 2309 2310 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2311 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2312 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2313 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2314 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2315 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2316 interrupt-names = "wdog", "fatal", "ready", "handover", 2317 "stop-ack", "shutdown-ack"; 2318 2319 clocks = <&rpmhcc RPMH_CXO_CLK>; 2320 clock-names = "xo"; 2321 2322 power-domains = <&rpmhpd RPMHPD_CX>, 2323 <&rpmhpd RPMHPD_MSS>; 2324 power-domain-names = "cx", "mss"; 2325 2326 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2327 2328 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 2329 2330 qcom,qmp = <&aoss_qmp>; 2331 2332 qcom,smem-states = <&smp2p_modem_out 0>; 2333 qcom,smem-state-names = "stop"; 2334 2335 status = "disabled"; 2336 2337 glink-edge { 2338 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2339 IPCC_MPROC_SIGNAL_GLINK_QMP 2340 IRQ_TYPE_EDGE_RISING>; 2341 mboxes = <&ipcc IPCC_CLIENT_MPSS 2342 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2343 label = "mpss"; 2344 qcom,remote-pid = <1>; 2345 }; 2346 }; 2347 2348 lpass_wsa2macro: codec@6aa0000 { 2349 compatible = "qcom,sm8550-lpass-wsa-macro"; 2350 reg = <0 0x06aa0000 0 0x1000>; 2351 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2352 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2353 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2354 <&lpass_vamacro>; 2355 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2356 2357 #clock-cells = <0>; 2358 clock-output-names = "wsa2-mclk"; 2359 #sound-dai-cells = <1>; 2360 }; 2361 2362 swr3: soundwire@6ab0000 { 2363 compatible = "qcom,soundwire-v2.0.0"; 2364 reg = <0 0x06ab0000 0 0x10000>; 2365 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2366 clocks = <&lpass_wsa2macro>; 2367 clock-names = "iface"; 2368 label = "WSA2"; 2369 2370 pinctrl-0 = <&wsa2_swr_active>; 2371 pinctrl-names = "default"; 2372 2373 qcom,din-ports = <4>; 2374 qcom,dout-ports = <9>; 2375 2376 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2377 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2378 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2379 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2380 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2381 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2382 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2383 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2384 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2385 2386 #address-cells = <2>; 2387 #size-cells = <0>; 2388 #sound-dai-cells = <1>; 2389 status = "disabled"; 2390 }; 2391 2392 lpass_rxmacro: codec@6ac0000 { 2393 compatible = "qcom,sm8550-lpass-rx-macro"; 2394 reg = <0 0x06ac0000 0 0x1000>; 2395 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2396 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2397 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2398 <&lpass_vamacro>; 2399 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2400 2401 #clock-cells = <0>; 2402 clock-output-names = "mclk"; 2403 #sound-dai-cells = <1>; 2404 }; 2405 2406 swr1: soundwire@6ad0000 { 2407 compatible = "qcom,soundwire-v2.0.0"; 2408 reg = <0 0x06ad0000 0 0x10000>; 2409 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2410 clocks = <&lpass_rxmacro>; 2411 clock-names = "iface"; 2412 label = "RX"; 2413 2414 pinctrl-0 = <&rx_swr_active>; 2415 pinctrl-names = "default"; 2416 2417 qcom,din-ports = <1>; 2418 qcom,dout-ports = <11>; 2419 2420 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>; 2421 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2422 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2423 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2424 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2425 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>; 2426 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2427 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2428 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2429 2430 #address-cells = <2>; 2431 #size-cells = <0>; 2432 #sound-dai-cells = <1>; 2433 status = "disabled"; 2434 }; 2435 2436 lpass_txmacro: codec@6ae0000 { 2437 compatible = "qcom,sm8550-lpass-tx-macro"; 2438 reg = <0 0x06ae0000 0 0x1000>; 2439 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2440 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2441 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2442 <&lpass_vamacro>; 2443 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2444 2445 #clock-cells = <0>; 2446 clock-output-names = "mclk"; 2447 #sound-dai-cells = <1>; 2448 }; 2449 2450 lpass_wsamacro: codec@6b00000 { 2451 compatible = "qcom,sm8550-lpass-wsa-macro"; 2452 reg = <0 0x06b00000 0 0x1000>; 2453 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2454 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2455 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2456 <&lpass_vamacro>; 2457 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2458 2459 #clock-cells = <0>; 2460 clock-output-names = "mclk"; 2461 #sound-dai-cells = <1>; 2462 }; 2463 2464 swr0: soundwire@6b10000 { 2465 compatible = "qcom,soundwire-v2.0.0"; 2466 reg = <0 0x06b10000 0 0x10000>; 2467 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2468 clocks = <&lpass_wsamacro>; 2469 clock-names = "iface"; 2470 label = "WSA"; 2471 2472 pinctrl-0 = <&wsa_swr_active>; 2473 pinctrl-names = "default"; 2474 2475 qcom,din-ports = <4>; 2476 qcom,dout-ports = <9>; 2477 2478 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2479 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2480 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2481 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2482 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2483 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2484 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2485 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2486 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2487 2488 #address-cells = <2>; 2489 #size-cells = <0>; 2490 #sound-dai-cells = <1>; 2491 status = "disabled"; 2492 }; 2493 2494 swr2: soundwire@6d30000 { 2495 compatible = "qcom,soundwire-v2.0.0"; 2496 reg = <0 0x06d30000 0 0x10000>; 2497 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2499 interrupt-names = "core", "wakeup"; 2500 clocks = <&lpass_txmacro>; 2501 clock-names = "iface"; 2502 label = "TX"; 2503 2504 pinctrl-0 = <&tx_swr_active>; 2505 pinctrl-names = "default"; 2506 2507 qcom,din-ports = <4>; 2508 qcom,dout-ports = <0>; 2509 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2510 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2511 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2512 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2513 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2514 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2515 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2516 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2517 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2518 2519 #address-cells = <2>; 2520 #size-cells = <0>; 2521 #sound-dai-cells = <1>; 2522 status = "disabled"; 2523 }; 2524 2525 lpass_vamacro: codec@6d44000 { 2526 compatible = "qcom,sm8550-lpass-va-macro"; 2527 reg = <0 0x06d44000 0 0x1000>; 2528 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2529 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2530 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2531 clock-names = "mclk", "macro", "dcodec"; 2532 2533 #clock-cells = <0>; 2534 clock-output-names = "fsgen"; 2535 #sound-dai-cells = <1>; 2536 }; 2537 2538 lpass_tlmm: pinctrl@6e80000 { 2539 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 2540 reg = <0 0x06e80000 0 0x20000>, 2541 <0 0x07250000 0 0x10000>; 2542 gpio-controller; 2543 #gpio-cells = <2>; 2544 gpio-ranges = <&lpass_tlmm 0 0 23>; 2545 2546 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2547 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2548 clock-names = "core", "audio"; 2549 2550 tx_swr_active: tx-swr-active-state { 2551 clk-pins { 2552 pins = "gpio0"; 2553 function = "swr_tx_clk"; 2554 drive-strength = <2>; 2555 slew-rate = <1>; 2556 bias-disable; 2557 }; 2558 2559 data-pins { 2560 pins = "gpio1", "gpio2", "gpio14"; 2561 function = "swr_tx_data"; 2562 drive-strength = <2>; 2563 slew-rate = <1>; 2564 bias-bus-hold; 2565 }; 2566 }; 2567 2568 rx_swr_active: rx-swr-active-state { 2569 clk-pins { 2570 pins = "gpio3"; 2571 function = "swr_rx_clk"; 2572 drive-strength = <2>; 2573 slew-rate = <1>; 2574 bias-disable; 2575 }; 2576 2577 data-pins { 2578 pins = "gpio4", "gpio5"; 2579 function = "swr_rx_data"; 2580 drive-strength = <2>; 2581 slew-rate = <1>; 2582 bias-bus-hold; 2583 }; 2584 }; 2585 2586 dmic01_default: dmic01-default-state { 2587 clk-pins { 2588 pins = "gpio6"; 2589 function = "dmic1_clk"; 2590 drive-strength = <8>; 2591 output-high; 2592 }; 2593 2594 data-pins { 2595 pins = "gpio7"; 2596 function = "dmic1_data"; 2597 drive-strength = <8>; 2598 input-enable; 2599 }; 2600 }; 2601 2602 dmic23_default: dmic23-default-state { 2603 clk-pins { 2604 pins = "gpio8"; 2605 function = "dmic2_clk"; 2606 drive-strength = <8>; 2607 output-high; 2608 }; 2609 2610 data-pins { 2611 pins = "gpio9"; 2612 function = "dmic2_data"; 2613 drive-strength = <8>; 2614 input-enable; 2615 }; 2616 }; 2617 2618 wsa_swr_active: wsa-swr-active-state { 2619 clk-pins { 2620 pins = "gpio10"; 2621 function = "wsa_swr_clk"; 2622 drive-strength = <2>; 2623 slew-rate = <1>; 2624 bias-disable; 2625 }; 2626 2627 data-pins { 2628 pins = "gpio11"; 2629 function = "wsa_swr_data"; 2630 drive-strength = <2>; 2631 slew-rate = <1>; 2632 bias-bus-hold; 2633 }; 2634 }; 2635 2636 wsa2_swr_active: wsa2-swr-active-state { 2637 clk-pins { 2638 pins = "gpio15"; 2639 function = "wsa2_swr_clk"; 2640 drive-strength = <2>; 2641 slew-rate = <1>; 2642 bias-disable; 2643 }; 2644 2645 data-pins { 2646 pins = "gpio16"; 2647 function = "wsa2_swr_data"; 2648 drive-strength = <2>; 2649 slew-rate = <1>; 2650 bias-bus-hold; 2651 }; 2652 }; 2653 }; 2654 2655 lpass_lpiaon_noc: interconnect@7400000 { 2656 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 2657 reg = <0 0x07400000 0 0x19080>; 2658 #interconnect-cells = <2>; 2659 qcom,bcm-voters = <&apps_bcm_voter>; 2660 }; 2661 2662 lpass_lpicx_noc: interconnect@7430000 { 2663 compatible = "qcom,sm8550-lpass-lpicx-noc"; 2664 reg = <0 0x07430000 0 0x3a200>; 2665 #interconnect-cells = <2>; 2666 qcom,bcm-voters = <&apps_bcm_voter>; 2667 }; 2668 2669 lpass_ag_noc: interconnect@7e40000 { 2670 compatible = "qcom,sm8550-lpass-ag-noc"; 2671 reg = <0 0x07e40000 0 0xe080>; 2672 #interconnect-cells = <2>; 2673 qcom,bcm-voters = <&apps_bcm_voter>; 2674 }; 2675 2676 sdhc_2: mmc@8804000 { 2677 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 2678 reg = <0 0x08804000 0 0x1000>; 2679 2680 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2681 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2682 interrupt-names = "hc_irq", "pwr_irq"; 2683 2684 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2685 <&gcc GCC_SDCC2_APPS_CLK>, 2686 <&rpmhcc RPMH_CXO_CLK>; 2687 clock-names = "iface", "core", "xo"; 2688 iommus = <&apps_smmu 0x540 0>; 2689 qcom,dll-config = <0x0007642c>; 2690 qcom,ddr-config = <0x80040868>; 2691 power-domains = <&rpmhpd RPMHPD_CX>; 2692 operating-points-v2 = <&sdhc2_opp_table>; 2693 2694 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2695 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2696 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 2697 bus-width = <4>; 2698 dma-coherent; 2699 2700 /* Forbid SDR104/SDR50 - broken hw! */ 2701 sdhci-caps-mask = <0x3 0>; 2702 2703 status = "disabled"; 2704 2705 sdhc2_opp_table: opp-table { 2706 compatible = "operating-points-v2"; 2707 2708 opp-19200000 { 2709 opp-hz = /bits/ 64 <19200000>; 2710 required-opps = <&rpmhpd_opp_min_svs>; 2711 }; 2712 2713 opp-50000000 { 2714 opp-hz = /bits/ 64 <50000000>; 2715 required-opps = <&rpmhpd_opp_low_svs>; 2716 }; 2717 2718 opp-100000000 { 2719 opp-hz = /bits/ 64 <100000000>; 2720 required-opps = <&rpmhpd_opp_svs>; 2721 }; 2722 2723 opp-202000000 { 2724 opp-hz = /bits/ 64 <202000000>; 2725 required-opps = <&rpmhpd_opp_svs_l1>; 2726 }; 2727 }; 2728 }; 2729 2730 videocc: clock-controller@aaf0000 { 2731 compatible = "qcom,sm8550-videocc"; 2732 reg = <0 0x0aaf0000 0 0x10000>; 2733 clocks = <&bi_tcxo_div2>, 2734 <&gcc GCC_VIDEO_AHB_CLK>; 2735 power-domains = <&rpmhpd RPMHPD_MMCX>; 2736 required-opps = <&rpmhpd_opp_low_svs>; 2737 #clock-cells = <1>; 2738 #reset-cells = <1>; 2739 #power-domain-cells = <1>; 2740 }; 2741 2742 camcc: clock-controller@ade0000 { 2743 compatible = "qcom,sm8550-camcc"; 2744 reg = <0 0x0ade0000 0 0x20000>; 2745 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2746 <&bi_tcxo_div2>, 2747 <&bi_tcxo_ao_div2>, 2748 <&sleep_clk>; 2749 power-domains = <&rpmhpd SM8550_MMCX>; 2750 required-opps = <&rpmhpd_opp_low_svs>; 2751 #clock-cells = <1>; 2752 #reset-cells = <1>; 2753 #power-domain-cells = <1>; 2754 }; 2755 2756 mdss: display-subsystem@ae00000 { 2757 compatible = "qcom,sm8550-mdss"; 2758 reg = <0 0x0ae00000 0 0x1000>; 2759 reg-names = "mdss"; 2760 2761 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2762 interrupt-controller; 2763 #interrupt-cells = <1>; 2764 2765 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2766 <&gcc GCC_DISP_AHB_CLK>, 2767 <&gcc GCC_DISP_HF_AXI_CLK>, 2768 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2769 2770 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2771 2772 power-domains = <&dispcc MDSS_GDSC>; 2773 2774 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, 2775 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2776 interconnect-names = "mdp0-mem", "mdp1-mem"; 2777 2778 iommus = <&apps_smmu 0x1c00 0x2>; 2779 2780 #address-cells = <2>; 2781 #size-cells = <2>; 2782 ranges; 2783 2784 status = "disabled"; 2785 2786 mdss_mdp: display-controller@ae01000 { 2787 compatible = "qcom,sm8550-dpu"; 2788 reg = <0 0x0ae01000 0 0x8f000>, 2789 <0 0x0aeb0000 0 0x2008>; 2790 reg-names = "mdp", "vbif"; 2791 2792 interrupt-parent = <&mdss>; 2793 interrupts = <0>; 2794 2795 clocks = <&gcc GCC_DISP_AHB_CLK>, 2796 <&gcc GCC_DISP_HF_AXI_CLK>, 2797 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2798 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2799 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2800 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2801 clock-names = "bus", 2802 "nrt_bus", 2803 "iface", 2804 "lut", 2805 "core", 2806 "vsync"; 2807 2808 power-domains = <&rpmhpd RPMHPD_MMCX>; 2809 2810 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2811 assigned-clock-rates = <19200000>; 2812 2813 operating-points-v2 = <&mdp_opp_table>; 2814 2815 ports { 2816 #address-cells = <1>; 2817 #size-cells = <0>; 2818 2819 port@0 { 2820 reg = <0>; 2821 dpu_intf1_out: endpoint { 2822 remote-endpoint = <&mdss_dsi0_in>; 2823 }; 2824 }; 2825 2826 port@1 { 2827 reg = <1>; 2828 dpu_intf2_out: endpoint { 2829 remote-endpoint = <&mdss_dsi1_in>; 2830 }; 2831 }; 2832 2833 port@2 { 2834 reg = <2>; 2835 dpu_intf0_out: endpoint { 2836 remote-endpoint = <&mdss_dp0_in>; 2837 }; 2838 }; 2839 }; 2840 2841 mdp_opp_table: opp-table { 2842 compatible = "operating-points-v2"; 2843 2844 opp-200000000 { 2845 opp-hz = /bits/ 64 <200000000>; 2846 required-opps = <&rpmhpd_opp_low_svs>; 2847 }; 2848 2849 opp-325000000 { 2850 opp-hz = /bits/ 64 <325000000>; 2851 required-opps = <&rpmhpd_opp_svs>; 2852 }; 2853 2854 opp-375000000 { 2855 opp-hz = /bits/ 64 <375000000>; 2856 required-opps = <&rpmhpd_opp_svs_l1>; 2857 }; 2858 2859 opp-514000000 { 2860 opp-hz = /bits/ 64 <514000000>; 2861 required-opps = <&rpmhpd_opp_nom>; 2862 }; 2863 }; 2864 }; 2865 2866 mdss_dp0: displayport-controller@ae90000 { 2867 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 2868 reg = <0 0xae90000 0 0x200>, 2869 <0 0xae90200 0 0x200>, 2870 <0 0xae90400 0 0xc00>, 2871 <0 0xae91000 0 0x400>, 2872 <0 0xae91400 0 0x400>; 2873 interrupt-parent = <&mdss>; 2874 interrupts = <12>; 2875 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2876 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2877 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2878 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2879 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2880 clock-names = "core_iface", 2881 "core_aux", 2882 "ctrl_link", 2883 "ctrl_link_iface", 2884 "stream_pixel"; 2885 2886 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2887 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2888 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2889 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2890 2891 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 2892 phy-names = "dp"; 2893 2894 #sound-dai-cells = <0>; 2895 2896 operating-points-v2 = <&dp_opp_table>; 2897 power-domains = <&rpmhpd RPMHPD_MMCX>; 2898 2899 status = "disabled"; 2900 2901 ports { 2902 #address-cells = <1>; 2903 #size-cells = <0>; 2904 2905 port@0 { 2906 reg = <0>; 2907 mdss_dp0_in: endpoint { 2908 remote-endpoint = <&dpu_intf0_out>; 2909 }; 2910 }; 2911 2912 port@1 { 2913 reg = <1>; 2914 mdss_dp0_out: endpoint { 2915 }; 2916 }; 2917 }; 2918 2919 dp_opp_table: opp-table { 2920 compatible = "operating-points-v2"; 2921 2922 opp-162000000 { 2923 opp-hz = /bits/ 64 <162000000>; 2924 required-opps = <&rpmhpd_opp_low_svs_d1>; 2925 }; 2926 2927 opp-270000000 { 2928 opp-hz = /bits/ 64 <270000000>; 2929 required-opps = <&rpmhpd_opp_low_svs>; 2930 }; 2931 2932 opp-540000000 { 2933 opp-hz = /bits/ 64 <540000000>; 2934 required-opps = <&rpmhpd_opp_svs_l1>; 2935 }; 2936 2937 opp-810000000 { 2938 opp-hz = /bits/ 64 <810000000>; 2939 required-opps = <&rpmhpd_opp_nom>; 2940 }; 2941 }; 2942 }; 2943 2944 mdss_dsi0: dsi@ae94000 { 2945 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2946 reg = <0 0x0ae94000 0 0x400>; 2947 reg-names = "dsi_ctrl"; 2948 2949 interrupt-parent = <&mdss>; 2950 interrupts = <4>; 2951 2952 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2953 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2954 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2955 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2956 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2957 <&gcc GCC_DISP_HF_AXI_CLK>; 2958 clock-names = "byte", 2959 "byte_intf", 2960 "pixel", 2961 "core", 2962 "iface", 2963 "bus"; 2964 2965 power-domains = <&rpmhpd RPMHPD_MMCX>; 2966 2967 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2968 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2969 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2970 <&mdss_dsi0_phy 1>; 2971 2972 operating-points-v2 = <&mdss_dsi_opp_table>; 2973 2974 phys = <&mdss_dsi0_phy>; 2975 phy-names = "dsi"; 2976 2977 #address-cells = <1>; 2978 #size-cells = <0>; 2979 2980 status = "disabled"; 2981 2982 ports { 2983 #address-cells = <1>; 2984 #size-cells = <0>; 2985 2986 port@0 { 2987 reg = <0>; 2988 mdss_dsi0_in: endpoint { 2989 remote-endpoint = <&dpu_intf1_out>; 2990 }; 2991 }; 2992 2993 port@1 { 2994 reg = <1>; 2995 mdss_dsi0_out: endpoint { 2996 }; 2997 }; 2998 }; 2999 3000 mdss_dsi_opp_table: opp-table { 3001 compatible = "operating-points-v2"; 3002 3003 opp-187500000 { 3004 opp-hz = /bits/ 64 <187500000>; 3005 required-opps = <&rpmhpd_opp_low_svs>; 3006 }; 3007 3008 opp-300000000 { 3009 opp-hz = /bits/ 64 <300000000>; 3010 required-opps = <&rpmhpd_opp_svs>; 3011 }; 3012 3013 opp-358000000 { 3014 opp-hz = /bits/ 64 <358000000>; 3015 required-opps = <&rpmhpd_opp_svs_l1>; 3016 }; 3017 }; 3018 }; 3019 3020 mdss_dsi0_phy: phy@ae95000 { 3021 compatible = "qcom,sm8550-dsi-phy-4nm"; 3022 reg = <0 0x0ae95000 0 0x200>, 3023 <0 0x0ae95200 0 0x280>, 3024 <0 0x0ae95500 0 0x400>; 3025 reg-names = "dsi_phy", 3026 "dsi_phy_lane", 3027 "dsi_pll"; 3028 3029 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3030 <&rpmhcc RPMH_CXO_CLK>; 3031 clock-names = "iface", "ref"; 3032 3033 #clock-cells = <1>; 3034 #phy-cells = <0>; 3035 3036 status = "disabled"; 3037 }; 3038 3039 mdss_dsi1: dsi@ae96000 { 3040 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3041 reg = <0 0x0ae96000 0 0x400>; 3042 reg-names = "dsi_ctrl"; 3043 3044 interrupt-parent = <&mdss>; 3045 interrupts = <5>; 3046 3047 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3048 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3049 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3050 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3051 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3052 <&gcc GCC_DISP_HF_AXI_CLK>; 3053 clock-names = "byte", 3054 "byte_intf", 3055 "pixel", 3056 "core", 3057 "iface", 3058 "bus"; 3059 3060 power-domains = <&rpmhpd RPMHPD_MMCX>; 3061 3062 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3063 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3064 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3065 <&mdss_dsi1_phy 1>; 3066 3067 operating-points-v2 = <&mdss_dsi_opp_table>; 3068 3069 phys = <&mdss_dsi1_phy>; 3070 phy-names = "dsi"; 3071 3072 #address-cells = <1>; 3073 #size-cells = <0>; 3074 3075 status = "disabled"; 3076 3077 ports { 3078 #address-cells = <1>; 3079 #size-cells = <0>; 3080 3081 port@0 { 3082 reg = <0>; 3083 mdss_dsi1_in: endpoint { 3084 remote-endpoint = <&dpu_intf2_out>; 3085 }; 3086 }; 3087 3088 port@1 { 3089 reg = <1>; 3090 mdss_dsi1_out: endpoint { 3091 }; 3092 }; 3093 }; 3094 }; 3095 3096 mdss_dsi1_phy: phy@ae97000 { 3097 compatible = "qcom,sm8550-dsi-phy-4nm"; 3098 reg = <0 0x0ae97000 0 0x200>, 3099 <0 0x0ae97200 0 0x280>, 3100 <0 0x0ae97500 0 0x400>; 3101 reg-names = "dsi_phy", 3102 "dsi_phy_lane", 3103 "dsi_pll"; 3104 3105 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3106 <&rpmhcc RPMH_CXO_CLK>; 3107 clock-names = "iface", "ref"; 3108 3109 #clock-cells = <1>; 3110 #phy-cells = <0>; 3111 3112 status = "disabled"; 3113 }; 3114 }; 3115 3116 dispcc: clock-controller@af00000 { 3117 compatible = "qcom,sm8550-dispcc"; 3118 reg = <0 0x0af00000 0 0x20000>; 3119 clocks = <&bi_tcxo_div2>, 3120 <&bi_tcxo_ao_div2>, 3121 <&gcc GCC_DISP_AHB_CLK>, 3122 <&sleep_clk>, 3123 <&mdss_dsi0_phy 0>, 3124 <&mdss_dsi0_phy 1>, 3125 <&mdss_dsi1_phy 0>, 3126 <&mdss_dsi1_phy 1>, 3127 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3128 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3129 <0>, /* dp1 */ 3130 <0>, 3131 <0>, /* dp2 */ 3132 <0>, 3133 <0>, /* dp3 */ 3134 <0>; 3135 power-domains = <&rpmhpd RPMHPD_MMCX>; 3136 required-opps = <&rpmhpd_opp_low_svs>; 3137 #clock-cells = <1>; 3138 #reset-cells = <1>; 3139 #power-domain-cells = <1>; 3140 }; 3141 3142 usb_1_hsphy: phy@88e3000 { 3143 compatible = "qcom,sm8550-snps-eusb2-phy"; 3144 reg = <0x0 0x088e3000 0x0 0x154>; 3145 #phy-cells = <0>; 3146 3147 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 3148 clock-names = "ref"; 3149 3150 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3151 3152 status = "disabled"; 3153 }; 3154 3155 usb_dp_qmpphy: phy@88e8000 { 3156 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 3157 reg = <0x0 0x088e8000 0x0 0x3000>; 3158 3159 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3160 <&rpmhcc RPMH_CXO_CLK>, 3161 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3162 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3163 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3164 3165 power-domains = <&gcc USB3_PHY_GDSC>; 3166 3167 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3168 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 3169 reset-names = "phy", "common"; 3170 3171 #clock-cells = <1>; 3172 #phy-cells = <1>; 3173 3174 status = "disabled"; 3175 3176 ports { 3177 #address-cells = <1>; 3178 #size-cells = <0>; 3179 3180 port@0 { 3181 reg = <0>; 3182 3183 usb_dp_qmpphy_out: endpoint { 3184 }; 3185 }; 3186 3187 port@1 { 3188 reg = <1>; 3189 3190 usb_dp_qmpphy_usb_ss_in: endpoint { 3191 }; 3192 }; 3193 3194 port@2 { 3195 reg = <2>; 3196 3197 usb_dp_qmpphy_dp_in: endpoint { 3198 }; 3199 }; 3200 }; 3201 }; 3202 3203 usb_1: usb@a6f8800 { 3204 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 3205 reg = <0x0 0x0a6f8800 0x0 0x400>; 3206 #address-cells = <2>; 3207 #size-cells = <2>; 3208 ranges; 3209 3210 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3211 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3212 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3213 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3214 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3215 <&tcsr TCSR_USB3_CLKREF_EN>; 3216 clock-names = "cfg_noc", 3217 "core", 3218 "iface", 3219 "sleep", 3220 "mock_utmi", 3221 "xo"; 3222 3223 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3224 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3225 assigned-clock-rates = <19200000>, <200000000>; 3226 3227 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3228 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3229 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3230 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3231 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3232 interrupt-names = "pwr_event", 3233 "hs_phy_irq", 3234 "dp_hs_phy_irq", 3235 "dm_hs_phy_irq", 3236 "ss_phy_irq"; 3237 3238 power-domains = <&gcc USB30_PRIM_GDSC>; 3239 required-opps = <&rpmhpd_opp_nom>; 3240 3241 resets = <&gcc GCC_USB30_PRIM_BCR>; 3242 3243 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3244 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3245 interconnect-names = "usb-ddr", "apps-usb"; 3246 3247 status = "disabled"; 3248 3249 usb_1_dwc3: usb@a600000 { 3250 compatible = "snps,dwc3"; 3251 reg = <0x0 0x0a600000 0x0 0xcd00>; 3252 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3253 iommus = <&apps_smmu 0x40 0x0>; 3254 phys = <&usb_1_hsphy>, 3255 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 3256 phy-names = "usb2-phy", "usb3-phy"; 3257 snps,hird-threshold = /bits/ 8 <0x0>; 3258 snps,usb2-gadget-lpm-disable; 3259 snps,dis_u2_susphy_quirk; 3260 snps,dis_enblslpm_quirk; 3261 snps,dis-u1-entry-quirk; 3262 snps,dis-u2-entry-quirk; 3263 snps,is-utmi-l1-suspend; 3264 snps,usb3_lpm_capable; 3265 snps,usb2-lpm-disable; 3266 snps,has-lpm-erratum; 3267 tx-fifo-resize; 3268 dma-coherent; 3269 3270 ports { 3271 #address-cells = <1>; 3272 #size-cells = <0>; 3273 3274 port@0 { 3275 reg = <0>; 3276 3277 usb_1_dwc3_hs: endpoint { 3278 }; 3279 }; 3280 3281 port@1 { 3282 reg = <1>; 3283 3284 usb_1_dwc3_ss: endpoint { 3285 }; 3286 }; 3287 }; 3288 }; 3289 }; 3290 3291 pdc: interrupt-controller@b220000 { 3292 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 3293 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3294 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3295 <125 63 1>, <126 716 12>, 3296 <138 251 5>; 3297 #interrupt-cells = <2>; 3298 interrupt-parent = <&intc>; 3299 interrupt-controller; 3300 }; 3301 3302 tsens0: thermal-sensor@c271000 { 3303 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3304 reg = <0 0x0c271000 0 0x1000>, /* TM */ 3305 <0 0x0c222000 0 0x1000>; /* SROT */ 3306 #qcom,sensors = <16>; 3307 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 3309 interrupt-names = "uplow", "critical"; 3310 #thermal-sensor-cells = <1>; 3311 }; 3312 3313 tsens1: thermal-sensor@c272000 { 3314 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3315 reg = <0 0x0c272000 0 0x1000>, /* TM */ 3316 <0 0x0c223000 0 0x1000>; /* SROT */ 3317 #qcom,sensors = <16>; 3318 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 3320 interrupt-names = "uplow", "critical"; 3321 #thermal-sensor-cells = <1>; 3322 }; 3323 3324 tsens2: thermal-sensor@c273000 { 3325 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3326 reg = <0 0x0c273000 0 0x1000>, /* TM */ 3327 <0 0x0c224000 0 0x1000>; /* SROT */ 3328 #qcom,sensors = <16>; 3329 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 3331 interrupt-names = "uplow", "critical"; 3332 #thermal-sensor-cells = <1>; 3333 }; 3334 3335 aoss_qmp: power-management@c300000 { 3336 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 3337 reg = <0 0x0c300000 0 0x400>; 3338 interrupt-parent = <&ipcc>; 3339 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3340 IRQ_TYPE_EDGE_RISING>; 3341 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3342 3343 #clock-cells = <0>; 3344 }; 3345 3346 sram@c3f0000 { 3347 compatible = "qcom,rpmh-stats"; 3348 reg = <0 0x0c3f0000 0 0x400>; 3349 }; 3350 3351 spmi_bus: spmi@c400000 { 3352 compatible = "qcom,spmi-pmic-arb"; 3353 reg = <0 0x0c400000 0 0x3000>, 3354 <0 0x0c500000 0 0x400000>, 3355 <0 0x0c440000 0 0x80000>, 3356 <0 0x0c4c0000 0 0x20000>, 3357 <0 0x0c42d000 0 0x4000>; 3358 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3359 interrupt-names = "periph_irq"; 3360 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3361 qcom,ee = <0>; 3362 qcom,channel = <0>; 3363 qcom,bus-id = <0>; 3364 #address-cells = <2>; 3365 #size-cells = <0>; 3366 interrupt-controller; 3367 #interrupt-cells = <4>; 3368 }; 3369 3370 tlmm: pinctrl@f100000 { 3371 compatible = "qcom,sm8550-tlmm"; 3372 reg = <0 0x0f100000 0 0x300000>; 3373 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3374 gpio-controller; 3375 #gpio-cells = <2>; 3376 interrupt-controller; 3377 #interrupt-cells = <2>; 3378 gpio-ranges = <&tlmm 0 0 211>; 3379 wakeup-parent = <&pdc>; 3380 3381 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3382 /* SDA, SCL */ 3383 pins = "gpio16", "gpio17"; 3384 function = "i2chub0_se0"; 3385 drive-strength = <2>; 3386 bias-pull-up; 3387 }; 3388 3389 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 3390 /* SDA, SCL */ 3391 pins = "gpio18", "gpio19"; 3392 function = "i2chub0_se1"; 3393 drive-strength = <2>; 3394 bias-pull-up; 3395 }; 3396 3397 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 3398 /* SDA, SCL */ 3399 pins = "gpio20", "gpio21"; 3400 function = "i2chub0_se2"; 3401 drive-strength = <2>; 3402 bias-pull-up; 3403 }; 3404 3405 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 3406 /* SDA, SCL */ 3407 pins = "gpio22", "gpio23"; 3408 function = "i2chub0_se3"; 3409 drive-strength = <2>; 3410 bias-pull-up; 3411 }; 3412 3413 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 3414 /* SDA, SCL */ 3415 pins = "gpio4", "gpio5"; 3416 function = "i2chub0_se4"; 3417 drive-strength = <2>; 3418 bias-pull-up; 3419 }; 3420 3421 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 3422 /* SDA, SCL */ 3423 pins = "gpio6", "gpio7"; 3424 function = "i2chub0_se5"; 3425 drive-strength = <2>; 3426 bias-pull-up; 3427 }; 3428 3429 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 3430 /* SDA, SCL */ 3431 pins = "gpio8", "gpio9"; 3432 function = "i2chub0_se6"; 3433 drive-strength = <2>; 3434 bias-pull-up; 3435 }; 3436 3437 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 3438 /* SDA, SCL */ 3439 pins = "gpio10", "gpio11"; 3440 function = "i2chub0_se7"; 3441 drive-strength = <2>; 3442 bias-pull-up; 3443 }; 3444 3445 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 3446 /* SDA, SCL */ 3447 pins = "gpio206", "gpio207"; 3448 function = "i2chub0_se8"; 3449 drive-strength = <2>; 3450 bias-pull-up; 3451 }; 3452 3453 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 3454 /* SDA, SCL */ 3455 pins = "gpio84", "gpio85"; 3456 function = "i2chub0_se9"; 3457 drive-strength = <2>; 3458 bias-pull-up; 3459 }; 3460 3461 pcie0_default_state: pcie0-default-state { 3462 perst-pins { 3463 pins = "gpio94"; 3464 function = "gpio"; 3465 drive-strength = <2>; 3466 bias-pull-down; 3467 }; 3468 3469 clkreq-pins { 3470 pins = "gpio95"; 3471 function = "pcie0_clk_req_n"; 3472 drive-strength = <2>; 3473 bias-pull-up; 3474 }; 3475 3476 wake-pins { 3477 pins = "gpio96"; 3478 function = "gpio"; 3479 drive-strength = <2>; 3480 bias-pull-up; 3481 }; 3482 }; 3483 3484 pcie1_default_state: pcie1-default-state { 3485 perst-pins { 3486 pins = "gpio97"; 3487 function = "gpio"; 3488 drive-strength = <2>; 3489 bias-pull-down; 3490 }; 3491 3492 clkreq-pins { 3493 pins = "gpio98"; 3494 function = "pcie1_clk_req_n"; 3495 drive-strength = <2>; 3496 bias-pull-up; 3497 }; 3498 3499 wake-pins { 3500 pins = "gpio99"; 3501 function = "gpio"; 3502 drive-strength = <2>; 3503 bias-pull-up; 3504 }; 3505 }; 3506 3507 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3508 /* SDA, SCL */ 3509 pins = "gpio28", "gpio29"; 3510 function = "qup1_se0"; 3511 drive-strength = <2>; 3512 bias-pull-up = <2200>; 3513 }; 3514 3515 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3516 /* SDA, SCL */ 3517 pins = "gpio32", "gpio33"; 3518 function = "qup1_se1"; 3519 drive-strength = <2>; 3520 bias-pull-up = <2200>; 3521 }; 3522 3523 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3524 /* SDA, SCL */ 3525 pins = "gpio36", "gpio37"; 3526 function = "qup1_se2"; 3527 drive-strength = <2>; 3528 bias-pull-up = <2200>; 3529 }; 3530 3531 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3532 /* SDA, SCL */ 3533 pins = "gpio40", "gpio41"; 3534 function = "qup1_se3"; 3535 drive-strength = <2>; 3536 bias-pull-up = <2200>; 3537 }; 3538 3539 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3540 /* SDA, SCL */ 3541 pins = "gpio44", "gpio45"; 3542 function = "qup1_se4"; 3543 drive-strength = <2>; 3544 bias-pull-up = <2200>; 3545 }; 3546 3547 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3548 /* SDA, SCL */ 3549 pins = "gpio52", "gpio53"; 3550 function = "qup1_se5"; 3551 drive-strength = <2>; 3552 bias-pull-up = <2200>; 3553 }; 3554 3555 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3556 /* SDA, SCL */ 3557 pins = "gpio48", "gpio49"; 3558 function = "qup1_se6"; 3559 drive-strength = <2>; 3560 bias-pull-up = <2200>; 3561 }; 3562 3563 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3564 scl-pins { 3565 pins = "gpio57"; 3566 function = "qup2_se0_l1_mira"; 3567 drive-strength = <2>; 3568 bias-pull-up = <2200>; 3569 }; 3570 3571 sda-pins { 3572 pins = "gpio56"; 3573 function = "qup2_se0_l0_mira"; 3574 drive-strength = <2>; 3575 bias-pull-up = <2200>; 3576 }; 3577 }; 3578 3579 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3580 /* SDA, SCL */ 3581 pins = "gpio60", "gpio61"; 3582 function = "qup2_se1"; 3583 drive-strength = <2>; 3584 bias-pull-up = <2200>; 3585 }; 3586 3587 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3588 /* SDA, SCL */ 3589 pins = "gpio64", "gpio65"; 3590 function = "qup2_se2"; 3591 drive-strength = <2>; 3592 bias-pull-up = <2200>; 3593 }; 3594 3595 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3596 /* SDA, SCL */ 3597 pins = "gpio68", "gpio69"; 3598 function = "qup2_se3"; 3599 drive-strength = <2>; 3600 bias-pull-up = <2200>; 3601 }; 3602 3603 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3604 /* SDA, SCL */ 3605 pins = "gpio2", "gpio3"; 3606 function = "qup2_se4"; 3607 drive-strength = <2>; 3608 bias-pull-up = <2200>; 3609 }; 3610 3611 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3612 /* SDA, SCL */ 3613 pins = "gpio80", "gpio81"; 3614 function = "qup2_se5"; 3615 drive-strength = <2>; 3616 bias-pull-up = <2200>; 3617 }; 3618 3619 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3620 /* SDA, SCL */ 3621 pins = "gpio72", "gpio106"; 3622 function = "qup2_se7"; 3623 drive-strength = <2>; 3624 bias-pull-up = <2200>; 3625 }; 3626 3627 qup_spi0_cs: qup-spi0-cs-state { 3628 pins = "gpio31"; 3629 function = "qup1_se0"; 3630 drive-strength = <6>; 3631 bias-disable; 3632 }; 3633 3634 qup_spi0_data_clk: qup-spi0-data-clk-state { 3635 /* MISO, MOSI, CLK */ 3636 pins = "gpio28", "gpio29", "gpio30"; 3637 function = "qup1_se0"; 3638 drive-strength = <6>; 3639 bias-disable; 3640 }; 3641 3642 qup_spi1_cs: qup-spi1-cs-state { 3643 pins = "gpio35"; 3644 function = "qup1_se1"; 3645 drive-strength = <6>; 3646 bias-disable; 3647 }; 3648 3649 qup_spi1_data_clk: qup-spi1-data-clk-state { 3650 /* MISO, MOSI, CLK */ 3651 pins = "gpio32", "gpio33", "gpio34"; 3652 function = "qup1_se1"; 3653 drive-strength = <6>; 3654 bias-disable; 3655 }; 3656 3657 qup_spi2_cs: qup-spi2-cs-state { 3658 pins = "gpio39"; 3659 function = "qup1_se2"; 3660 drive-strength = <6>; 3661 bias-disable; 3662 }; 3663 3664 qup_spi2_data_clk: qup-spi2-data-clk-state { 3665 /* MISO, MOSI, CLK */ 3666 pins = "gpio36", "gpio37", "gpio38"; 3667 function = "qup1_se2"; 3668 drive-strength = <6>; 3669 bias-disable; 3670 }; 3671 3672 qup_spi3_cs: qup-spi3-cs-state { 3673 pins = "gpio43"; 3674 function = "qup1_se3"; 3675 drive-strength = <6>; 3676 bias-disable; 3677 }; 3678 3679 qup_spi3_data_clk: qup-spi3-data-clk-state { 3680 /* MISO, MOSI, CLK */ 3681 pins = "gpio40", "gpio41", "gpio42"; 3682 function = "qup1_se3"; 3683 drive-strength = <6>; 3684 bias-disable; 3685 }; 3686 3687 qup_spi4_cs: qup-spi4-cs-state { 3688 pins = "gpio47"; 3689 function = "qup1_se4"; 3690 drive-strength = <6>; 3691 bias-disable; 3692 }; 3693 3694 qup_spi4_data_clk: qup-spi4-data-clk-state { 3695 /* MISO, MOSI, CLK */ 3696 pins = "gpio44", "gpio45", "gpio46"; 3697 function = "qup1_se4"; 3698 drive-strength = <6>; 3699 bias-disable; 3700 }; 3701 3702 qup_spi5_cs: qup-spi5-cs-state { 3703 pins = "gpio55"; 3704 function = "qup1_se5"; 3705 drive-strength = <6>; 3706 bias-disable; 3707 }; 3708 3709 qup_spi5_data_clk: qup-spi5-data-clk-state { 3710 /* MISO, MOSI, CLK */ 3711 pins = "gpio52", "gpio53", "gpio54"; 3712 function = "qup1_se5"; 3713 drive-strength = <6>; 3714 bias-disable; 3715 }; 3716 3717 qup_spi6_cs: qup-spi6-cs-state { 3718 pins = "gpio51"; 3719 function = "qup1_se6"; 3720 drive-strength = <6>; 3721 bias-disable; 3722 }; 3723 3724 qup_spi6_data_clk: qup-spi6-data-clk-state { 3725 /* MISO, MOSI, CLK */ 3726 pins = "gpio48", "gpio49", "gpio50"; 3727 function = "qup1_se6"; 3728 drive-strength = <6>; 3729 bias-disable; 3730 }; 3731 3732 qup_spi8_cs: qup-spi8-cs-state { 3733 pins = "gpio59"; 3734 function = "qup2_se0_l3_mira"; 3735 drive-strength = <6>; 3736 bias-disable; 3737 }; 3738 3739 qup_spi8_data_clk: qup-spi8-data-clk-state { 3740 /* MISO, MOSI, CLK */ 3741 pins = "gpio56", "gpio57", "gpio58"; 3742 function = "qup2_se0_l2_mira"; 3743 drive-strength = <6>; 3744 bias-disable; 3745 }; 3746 3747 qup_spi9_cs: qup-spi9-cs-state { 3748 pins = "gpio63"; 3749 function = "qup2_se1"; 3750 drive-strength = <6>; 3751 bias-disable; 3752 }; 3753 3754 qup_spi9_data_clk: qup-spi9-data-clk-state { 3755 /* MISO, MOSI, CLK */ 3756 pins = "gpio60", "gpio61", "gpio62"; 3757 function = "qup2_se1"; 3758 drive-strength = <6>; 3759 bias-disable; 3760 }; 3761 3762 qup_spi10_cs: qup-spi10-cs-state { 3763 pins = "gpio67"; 3764 function = "qup2_se2"; 3765 drive-strength = <6>; 3766 bias-disable; 3767 }; 3768 3769 qup_spi10_data_clk: qup-spi10-data-clk-state { 3770 /* MISO, MOSI, CLK */ 3771 pins = "gpio64", "gpio65", "gpio66"; 3772 function = "qup2_se2"; 3773 drive-strength = <6>; 3774 bias-disable; 3775 }; 3776 3777 qup_spi11_cs: qup-spi11-cs-state { 3778 pins = "gpio71"; 3779 function = "qup2_se3"; 3780 drive-strength = <6>; 3781 bias-disable; 3782 }; 3783 3784 qup_spi11_data_clk: qup-spi11-data-clk-state { 3785 /* MISO, MOSI, CLK */ 3786 pins = "gpio68", "gpio69", "gpio70"; 3787 function = "qup2_se3"; 3788 drive-strength = <6>; 3789 bias-disable; 3790 }; 3791 3792 qup_spi12_cs: qup-spi12-cs-state { 3793 pins = "gpio119"; 3794 function = "qup2_se4"; 3795 drive-strength = <6>; 3796 bias-disable; 3797 }; 3798 3799 qup_spi12_data_clk: qup-spi12-data-clk-state { 3800 /* MISO, MOSI, CLK */ 3801 pins = "gpio2", "gpio3", "gpio118"; 3802 function = "qup2_se4"; 3803 drive-strength = <6>; 3804 bias-disable; 3805 }; 3806 3807 qup_spi13_cs: qup-spi13-cs-state { 3808 pins = "gpio83"; 3809 function = "qup2_se5"; 3810 drive-strength = <6>; 3811 bias-disable; 3812 }; 3813 3814 qup_spi13_data_clk: qup-spi13-data-clk-state { 3815 /* MISO, MOSI, CLK */ 3816 pins = "gpio80", "gpio81", "gpio82"; 3817 function = "qup2_se5"; 3818 drive-strength = <6>; 3819 bias-disable; 3820 }; 3821 3822 qup_spi15_cs: qup-spi15-cs-state { 3823 pins = "gpio75"; 3824 function = "qup2_se7"; 3825 drive-strength = <6>; 3826 bias-disable; 3827 }; 3828 3829 qup_spi15_data_clk: qup-spi15-data-clk-state { 3830 /* MISO, MOSI, CLK */ 3831 pins = "gpio72", "gpio106", "gpio74"; 3832 function = "qup2_se7"; 3833 drive-strength = <6>; 3834 bias-disable; 3835 }; 3836 3837 qup_uart7_default: qup-uart7-default-state { 3838 /* TX, RX */ 3839 pins = "gpio26", "gpio27"; 3840 function = "qup1_se7"; 3841 drive-strength = <2>; 3842 bias-disable; 3843 }; 3844 3845 qup_uart14_default: qup-uart14-default-state { 3846 /* TX, RX */ 3847 pins = "gpio78", "gpio79"; 3848 function = "qup2_se6"; 3849 drive-strength = <2>; 3850 bias-pull-up; 3851 }; 3852 3853 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 3854 /* CTS, RTS */ 3855 pins = "gpio76", "gpio77"; 3856 function = "qup2_se6"; 3857 drive-strength = <2>; 3858 bias-pull-down; 3859 }; 3860 3861 sdc2_sleep: sdc2-sleep-state { 3862 clk-pins { 3863 pins = "sdc2_clk"; 3864 bias-disable; 3865 drive-strength = <2>; 3866 }; 3867 3868 cmd-pins { 3869 pins = "sdc2_cmd"; 3870 bias-pull-up; 3871 drive-strength = <2>; 3872 }; 3873 3874 data-pins { 3875 pins = "sdc2_data"; 3876 bias-pull-up; 3877 drive-strength = <2>; 3878 }; 3879 }; 3880 3881 sdc2_default: sdc2-default-state { 3882 clk-pins { 3883 pins = "sdc2_clk"; 3884 bias-disable; 3885 drive-strength = <16>; 3886 }; 3887 3888 cmd-pins { 3889 pins = "sdc2_cmd"; 3890 bias-pull-up; 3891 drive-strength = <10>; 3892 }; 3893 3894 data-pins { 3895 pins = "sdc2_data"; 3896 bias-pull-up; 3897 drive-strength = <10>; 3898 }; 3899 }; 3900 }; 3901 3902 apps_smmu: iommu@15000000 { 3903 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3904 reg = <0 0x15000000 0 0x100000>; 3905 #iommu-cells = <2>; 3906 #global-interrupts = <1>; 3907 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3908 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3909 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3910 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3911 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3912 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3913 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3914 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3915 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3916 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3917 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3918 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3919 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3920 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3921 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3922 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3923 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3924 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3925 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3926 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3927 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3928 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3929 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3930 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3931 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3932 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3933 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3934 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3935 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3936 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3937 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3938 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3939 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3940 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3941 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3942 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3943 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3944 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3945 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3946 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3947 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3948 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3949 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3950 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3951 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3952 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3953 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3954 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3955 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3956 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3957 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3958 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3959 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3960 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3961 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3962 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3963 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3964 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3965 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3966 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3967 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3968 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3969 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3970 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3971 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3972 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3973 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3974 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3975 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3976 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3977 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3978 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3979 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3980 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3981 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3982 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3983 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3984 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3985 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3986 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3987 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3988 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3989 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3990 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3991 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3992 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3993 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3994 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3995 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3996 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3997 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3998 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3999 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4000 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4001 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4002 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4003 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 4004 dma-coherent; 4005 }; 4006 4007 intc: interrupt-controller@17100000 { 4008 compatible = "arm,gic-v3"; 4009 reg = <0 0x17100000 0 0x10000>, /* GICD */ 4010 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 4011 ranges; 4012 #interrupt-cells = <3>; 4013 interrupt-controller; 4014 #redistributor-regions = <1>; 4015 redistributor-stride = <0 0x40000>; 4016 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4017 #address-cells = <2>; 4018 #size-cells = <2>; 4019 4020 gic_its: msi-controller@17140000 { 4021 compatible = "arm,gic-v3-its"; 4022 reg = <0 0x17140000 0 0x20000>; 4023 msi-controller; 4024 #msi-cells = <1>; 4025 }; 4026 }; 4027 4028 timer@17420000 { 4029 compatible = "arm,armv7-timer-mem"; 4030 reg = <0 0x17420000 0 0x1000>; 4031 ranges = <0 0 0 0x20000000>; 4032 #address-cells = <1>; 4033 #size-cells = <1>; 4034 4035 frame@17421000 { 4036 reg = <0x17421000 0x1000>, 4037 <0x17422000 0x1000>; 4038 frame-number = <0>; 4039 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4040 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4041 }; 4042 4043 frame@17423000 { 4044 reg = <0x17423000 0x1000>; 4045 frame-number = <1>; 4046 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4047 status = "disabled"; 4048 }; 4049 4050 frame@17425000 { 4051 reg = <0x17425000 0x1000>; 4052 frame-number = <2>; 4053 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4054 status = "disabled"; 4055 }; 4056 4057 frame@17427000 { 4058 reg = <0x17427000 0x1000>; 4059 frame-number = <3>; 4060 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4061 status = "disabled"; 4062 }; 4063 4064 frame@17429000 { 4065 reg = <0x17429000 0x1000>; 4066 frame-number = <4>; 4067 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4068 status = "disabled"; 4069 }; 4070 4071 frame@1742b000 { 4072 reg = <0x1742b000 0x1000>; 4073 frame-number = <5>; 4074 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4075 status = "disabled"; 4076 }; 4077 4078 frame@1742d000 { 4079 reg = <0x1742d000 0x1000>; 4080 frame-number = <6>; 4081 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4082 status = "disabled"; 4083 }; 4084 }; 4085 4086 apps_rsc: rsc@17a00000 { 4087 label = "apps_rsc"; 4088 compatible = "qcom,rpmh-rsc"; 4089 reg = <0 0x17a00000 0 0x10000>, 4090 <0 0x17a10000 0 0x10000>, 4091 <0 0x17a20000 0 0x10000>, 4092 <0 0x17a30000 0 0x10000>; 4093 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 4094 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4097 qcom,tcs-offset = <0xd00>; 4098 qcom,drv-id = <2>; 4099 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4100 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4101 power-domains = <&CLUSTER_PD>; 4102 4103 apps_bcm_voter: bcm-voter { 4104 compatible = "qcom,bcm-voter"; 4105 }; 4106 4107 rpmhcc: clock-controller { 4108 compatible = "qcom,sm8550-rpmh-clk"; 4109 #clock-cells = <1>; 4110 clock-names = "xo"; 4111 clocks = <&xo_board>; 4112 }; 4113 4114 rpmhpd: power-controller { 4115 compatible = "qcom,sm8550-rpmhpd"; 4116 #power-domain-cells = <1>; 4117 operating-points-v2 = <&rpmhpd_opp_table>; 4118 4119 rpmhpd_opp_table: opp-table { 4120 compatible = "operating-points-v2"; 4121 4122 rpmhpd_opp_ret: opp-16 { 4123 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4124 }; 4125 4126 rpmhpd_opp_min_svs: opp-48 { 4127 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4128 }; 4129 4130 rpmhpd_opp_low_svs_d2: opp-52 { 4131 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 4132 }; 4133 4134 rpmhpd_opp_low_svs_d1: opp-56 { 4135 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4136 }; 4137 4138 rpmhpd_opp_low_svs_d0: opp-60 { 4139 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 4140 }; 4141 4142 rpmhpd_opp_low_svs: opp-64 { 4143 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4144 }; 4145 4146 rpmhpd_opp_low_svs_l1: opp-80 { 4147 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4148 }; 4149 4150 rpmhpd_opp_svs: opp-128 { 4151 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4152 }; 4153 4154 rpmhpd_opp_svs_l0: opp-144 { 4155 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4156 }; 4157 4158 rpmhpd_opp_svs_l1: opp-192 { 4159 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4160 }; 4161 4162 rpmhpd_opp_nom: opp-256 { 4163 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4164 }; 4165 4166 rpmhpd_opp_nom_l1: opp-320 { 4167 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4168 }; 4169 4170 rpmhpd_opp_nom_l2: opp-336 { 4171 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4172 }; 4173 4174 rpmhpd_opp_turbo: opp-384 { 4175 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4176 }; 4177 4178 rpmhpd_opp_turbo_l1: opp-416 { 4179 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4180 }; 4181 }; 4182 }; 4183 }; 4184 4185 cpufreq_hw: cpufreq@17d91000 { 4186 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 4187 reg = <0 0x17d91000 0 0x1000>, 4188 <0 0x17d92000 0 0x1000>, 4189 <0 0x17d93000 0 0x1000>; 4190 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4191 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 4192 clock-names = "xo", "alternate"; 4193 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4194 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4195 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4196 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4197 #freq-domain-cells = <1>; 4198 #clock-cells = <1>; 4199 }; 4200 4201 pmu@24091000 { 4202 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4203 reg = <0 0x24091000 0 0x1000>; 4204 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4205 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 4206 4207 operating-points-v2 = <&llcc_bwmon_opp_table>; 4208 4209 llcc_bwmon_opp_table: opp-table { 4210 compatible = "operating-points-v2"; 4211 4212 opp-0 { 4213 opp-peak-kBps = <2086000>; 4214 }; 4215 4216 opp-1 { 4217 opp-peak-kBps = <2929000>; 4218 }; 4219 4220 opp-2 { 4221 opp-peak-kBps = <5931000>; 4222 }; 4223 4224 opp-3 { 4225 opp-peak-kBps = <6515000>; 4226 }; 4227 4228 opp-4 { 4229 opp-peak-kBps = <7980000>; 4230 }; 4231 4232 opp-5 { 4233 opp-peak-kBps = <10437000>; 4234 }; 4235 4236 opp-6 { 4237 opp-peak-kBps = <12157000>; 4238 }; 4239 4240 opp-7 { 4241 opp-peak-kBps = <14060000>; 4242 }; 4243 4244 opp-8 { 4245 opp-peak-kBps = <16113000>; 4246 }; 4247 }; 4248 }; 4249 4250 pmu@240b6400 { 4251 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 4252 reg = <0 0x240b6400 0 0x600>; 4253 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4254 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 4255 4256 operating-points-v2 = <&cpu_bwmon_opp_table>; 4257 4258 cpu_bwmon_opp_table: opp-table { 4259 compatible = "operating-points-v2"; 4260 4261 opp-0 { 4262 opp-peak-kBps = <4577000>; 4263 }; 4264 4265 opp-1 { 4266 opp-peak-kBps = <7110000>; 4267 }; 4268 4269 opp-2 { 4270 opp-peak-kBps = <9155000>; 4271 }; 4272 4273 opp-3 { 4274 opp-peak-kBps = <12298000>; 4275 }; 4276 4277 opp-4 { 4278 opp-peak-kBps = <14236000>; 4279 }; 4280 4281 opp-5 { 4282 opp-peak-kBps = <16265000>; 4283 }; 4284 }; 4285 }; 4286 4287 gem_noc: interconnect@24100000 { 4288 compatible = "qcom,sm8550-gem-noc"; 4289 reg = <0 0x24100000 0 0xbb800>; 4290 #interconnect-cells = <2>; 4291 qcom,bcm-voters = <&apps_bcm_voter>; 4292 }; 4293 4294 system-cache-controller@25000000 { 4295 compatible = "qcom,sm8550-llcc"; 4296 reg = <0 0x25000000 0 0x200000>, 4297 <0 0x25200000 0 0x200000>, 4298 <0 0x25400000 0 0x200000>, 4299 <0 0x25600000 0 0x200000>, 4300 <0 0x25800000 0 0x200000>; 4301 reg-names = "llcc0_base", 4302 "llcc1_base", 4303 "llcc2_base", 4304 "llcc3_base", 4305 "llcc_broadcast_base"; 4306 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4307 }; 4308 4309 remoteproc_adsp: remoteproc@30000000 { 4310 compatible = "qcom,sm8550-adsp-pas"; 4311 reg = <0x0 0x30000000 0x0 0x100>; 4312 4313 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4314 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4315 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4316 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4317 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4318 interrupt-names = "wdog", "fatal", "ready", 4319 "handover", "stop-ack"; 4320 4321 clocks = <&rpmhcc RPMH_CXO_CLK>; 4322 clock-names = "xo"; 4323 4324 power-domains = <&rpmhpd RPMHPD_LCX>, 4325 <&rpmhpd RPMHPD_LMX>; 4326 power-domain-names = "lcx", "lmx"; 4327 4328 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 4329 4330 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 4331 4332 qcom,qmp = <&aoss_qmp>; 4333 4334 qcom,smem-states = <&smp2p_adsp_out 0>; 4335 qcom,smem-state-names = "stop"; 4336 4337 status = "disabled"; 4338 4339 remoteproc_adsp_glink: glink-edge { 4340 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4341 IPCC_MPROC_SIGNAL_GLINK_QMP 4342 IRQ_TYPE_EDGE_RISING>; 4343 mboxes = <&ipcc IPCC_CLIENT_LPASS 4344 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4345 4346 label = "lpass"; 4347 qcom,remote-pid = <2>; 4348 4349 fastrpc { 4350 compatible = "qcom,fastrpc"; 4351 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4352 label = "adsp"; 4353 qcom,non-secure-domain; 4354 #address-cells = <1>; 4355 #size-cells = <0>; 4356 4357 compute-cb@3 { 4358 compatible = "qcom,fastrpc-compute-cb"; 4359 reg = <3>; 4360 iommus = <&apps_smmu 0x1003 0x80>, 4361 <&apps_smmu 0x1063 0x0>; 4362 dma-coherent; 4363 }; 4364 4365 compute-cb@4 { 4366 compatible = "qcom,fastrpc-compute-cb"; 4367 reg = <4>; 4368 iommus = <&apps_smmu 0x1004 0x80>, 4369 <&apps_smmu 0x1064 0x0>; 4370 dma-coherent; 4371 }; 4372 4373 compute-cb@5 { 4374 compatible = "qcom,fastrpc-compute-cb"; 4375 reg = <5>; 4376 iommus = <&apps_smmu 0x1005 0x80>, 4377 <&apps_smmu 0x1065 0x0>; 4378 dma-coherent; 4379 }; 4380 4381 compute-cb@6 { 4382 compatible = "qcom,fastrpc-compute-cb"; 4383 reg = <6>; 4384 iommus = <&apps_smmu 0x1006 0x80>, 4385 <&apps_smmu 0x1066 0x0>; 4386 dma-coherent; 4387 }; 4388 4389 compute-cb@7 { 4390 compatible = "qcom,fastrpc-compute-cb"; 4391 reg = <7>; 4392 iommus = <&apps_smmu 0x1007 0x80>, 4393 <&apps_smmu 0x1067 0x0>; 4394 dma-coherent; 4395 }; 4396 }; 4397 4398 gpr { 4399 compatible = "qcom,gpr"; 4400 qcom,glink-channels = "adsp_apps"; 4401 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4402 qcom,intents = <512 20>; 4403 #address-cells = <1>; 4404 #size-cells = <0>; 4405 4406 q6apm: service@1 { 4407 compatible = "qcom,q6apm"; 4408 reg = <GPR_APM_MODULE_IID>; 4409 #sound-dai-cells = <0>; 4410 qcom,protection-domain = "avs/audio", 4411 "msm/adsp/audio_pd"; 4412 4413 q6apmdai: dais { 4414 compatible = "qcom,q6apm-dais"; 4415 iommus = <&apps_smmu 0x1001 0x80>, 4416 <&apps_smmu 0x1061 0x0>; 4417 }; 4418 4419 q6apmbedai: bedais { 4420 compatible = "qcom,q6apm-lpass-dais"; 4421 #sound-dai-cells = <1>; 4422 }; 4423 }; 4424 4425 q6prm: service@2 { 4426 compatible = "qcom,q6prm"; 4427 reg = <GPR_PRM_MODULE_IID>; 4428 qcom,protection-domain = "avs/audio", 4429 "msm/adsp/audio_pd"; 4430 4431 q6prmcc: clock-controller { 4432 compatible = "qcom,q6prm-lpass-clocks"; 4433 #clock-cells = <2>; 4434 }; 4435 }; 4436 }; 4437 }; 4438 }; 4439 4440 nsp_noc: interconnect@320c0000 { 4441 compatible = "qcom,sm8550-nsp-noc"; 4442 reg = <0 0x320c0000 0 0xe080>; 4443 #interconnect-cells = <2>; 4444 qcom,bcm-voters = <&apps_bcm_voter>; 4445 }; 4446 4447 remoteproc_cdsp: remoteproc@32300000 { 4448 compatible = "qcom,sm8550-cdsp-pas"; 4449 reg = <0x0 0x32300000 0x0 0x1400000>; 4450 4451 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4452 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 4453 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 4454 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 4455 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 4456 interrupt-names = "wdog", "fatal", "ready", 4457 "handover", "stop-ack"; 4458 4459 clocks = <&rpmhcc RPMH_CXO_CLK>; 4460 clock-names = "xo"; 4461 4462 power-domains = <&rpmhpd RPMHPD_CX>, 4463 <&rpmhpd RPMHPD_MXC>, 4464 <&rpmhpd RPMHPD_NSP>; 4465 power-domain-names = "cx", "mxc", "nsp"; 4466 4467 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4468 4469 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 4470 4471 qcom,qmp = <&aoss_qmp>; 4472 4473 qcom,smem-states = <&smp2p_cdsp_out 0>; 4474 qcom,smem-state-names = "stop"; 4475 4476 status = "disabled"; 4477 4478 glink-edge { 4479 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4480 IPCC_MPROC_SIGNAL_GLINK_QMP 4481 IRQ_TYPE_EDGE_RISING>; 4482 mboxes = <&ipcc IPCC_CLIENT_CDSP 4483 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4484 4485 label = "cdsp"; 4486 qcom,remote-pid = <5>; 4487 4488 fastrpc { 4489 compatible = "qcom,fastrpc"; 4490 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4491 label = "cdsp"; 4492 qcom,non-secure-domain; 4493 #address-cells = <1>; 4494 #size-cells = <0>; 4495 4496 compute-cb@1 { 4497 compatible = "qcom,fastrpc-compute-cb"; 4498 reg = <1>; 4499 iommus = <&apps_smmu 0x1961 0x0>, 4500 <&apps_smmu 0x0c01 0x20>, 4501 <&apps_smmu 0x19c1 0x10>; 4502 dma-coherent; 4503 }; 4504 4505 compute-cb@2 { 4506 compatible = "qcom,fastrpc-compute-cb"; 4507 reg = <2>; 4508 iommus = <&apps_smmu 0x1962 0x0>, 4509 <&apps_smmu 0x0c02 0x20>, 4510 <&apps_smmu 0x19c2 0x10>; 4511 dma-coherent; 4512 }; 4513 4514 compute-cb@3 { 4515 compatible = "qcom,fastrpc-compute-cb"; 4516 reg = <3>; 4517 iommus = <&apps_smmu 0x1963 0x0>, 4518 <&apps_smmu 0x0c03 0x20>, 4519 <&apps_smmu 0x19c3 0x10>; 4520 dma-coherent; 4521 }; 4522 4523 compute-cb@4 { 4524 compatible = "qcom,fastrpc-compute-cb"; 4525 reg = <4>; 4526 iommus = <&apps_smmu 0x1964 0x0>, 4527 <&apps_smmu 0x0c04 0x20>, 4528 <&apps_smmu 0x19c4 0x10>; 4529 dma-coherent; 4530 }; 4531 4532 compute-cb@5 { 4533 compatible = "qcom,fastrpc-compute-cb"; 4534 reg = <5>; 4535 iommus = <&apps_smmu 0x1965 0x0>, 4536 <&apps_smmu 0x0c05 0x20>, 4537 <&apps_smmu 0x19c5 0x10>; 4538 dma-coherent; 4539 }; 4540 4541 compute-cb@6 { 4542 compatible = "qcom,fastrpc-compute-cb"; 4543 reg = <6>; 4544 iommus = <&apps_smmu 0x1966 0x0>, 4545 <&apps_smmu 0x0c06 0x20>, 4546 <&apps_smmu 0x19c6 0x10>; 4547 dma-coherent; 4548 }; 4549 4550 compute-cb@7 { 4551 compatible = "qcom,fastrpc-compute-cb"; 4552 reg = <7>; 4553 iommus = <&apps_smmu 0x1967 0x0>, 4554 <&apps_smmu 0x0c07 0x20>, 4555 <&apps_smmu 0x19c7 0x10>; 4556 dma-coherent; 4557 }; 4558 4559 compute-cb@8 { 4560 compatible = "qcom,fastrpc-compute-cb"; 4561 reg = <8>; 4562 iommus = <&apps_smmu 0x1968 0x0>, 4563 <&apps_smmu 0x0c08 0x20>, 4564 <&apps_smmu 0x19c8 0x10>; 4565 dma-coherent; 4566 }; 4567 4568 /* note: secure cb9 in downstream */ 4569 }; 4570 }; 4571 }; 4572 }; 4573 4574 thermal-zones { 4575 aoss0-thermal { 4576 polling-delay-passive = <0>; 4577 polling-delay = <0>; 4578 thermal-sensors = <&tsens0 0>; 4579 4580 trips { 4581 thermal-engine-config { 4582 temperature = <125000>; 4583 hysteresis = <1000>; 4584 type = "passive"; 4585 }; 4586 4587 reset-mon-config { 4588 temperature = <115000>; 4589 hysteresis = <5000>; 4590 type = "passive"; 4591 }; 4592 }; 4593 }; 4594 4595 cpuss0-thermal { 4596 polling-delay-passive = <0>; 4597 polling-delay = <0>; 4598 thermal-sensors = <&tsens0 1>; 4599 4600 trips { 4601 thermal-engine-config { 4602 temperature = <125000>; 4603 hysteresis = <1000>; 4604 type = "passive"; 4605 }; 4606 4607 reset-mon-config { 4608 temperature = <115000>; 4609 hysteresis = <5000>; 4610 type = "passive"; 4611 }; 4612 }; 4613 }; 4614 4615 cpuss1-thermal { 4616 polling-delay-passive = <0>; 4617 polling-delay = <0>; 4618 thermal-sensors = <&tsens0 2>; 4619 4620 trips { 4621 thermal-engine-config { 4622 temperature = <125000>; 4623 hysteresis = <1000>; 4624 type = "passive"; 4625 }; 4626 4627 reset-mon-config { 4628 temperature = <115000>; 4629 hysteresis = <5000>; 4630 type = "passive"; 4631 }; 4632 }; 4633 }; 4634 4635 cpuss2-thermal { 4636 polling-delay-passive = <0>; 4637 polling-delay = <0>; 4638 thermal-sensors = <&tsens0 3>; 4639 4640 trips { 4641 thermal-engine-config { 4642 temperature = <125000>; 4643 hysteresis = <1000>; 4644 type = "passive"; 4645 }; 4646 4647 reset-mon-config { 4648 temperature = <115000>; 4649 hysteresis = <5000>; 4650 type = "passive"; 4651 }; 4652 }; 4653 }; 4654 4655 cpuss3-thermal { 4656 polling-delay-passive = <0>; 4657 polling-delay = <0>; 4658 thermal-sensors = <&tsens0 4>; 4659 4660 trips { 4661 thermal-engine-config { 4662 temperature = <125000>; 4663 hysteresis = <1000>; 4664 type = "passive"; 4665 }; 4666 4667 reset-mon-config { 4668 temperature = <115000>; 4669 hysteresis = <5000>; 4670 type = "passive"; 4671 }; 4672 }; 4673 }; 4674 4675 cpu3-top-thermal { 4676 polling-delay-passive = <0>; 4677 polling-delay = <0>; 4678 thermal-sensors = <&tsens0 5>; 4679 4680 trips { 4681 cpu3_top_alert0: trip-point0 { 4682 temperature = <90000>; 4683 hysteresis = <2000>; 4684 type = "passive"; 4685 }; 4686 4687 cpu3_top_alert1: trip-point1 { 4688 temperature = <95000>; 4689 hysteresis = <2000>; 4690 type = "passive"; 4691 }; 4692 4693 cpu3_top_crit: cpu-critical { 4694 temperature = <110000>; 4695 hysteresis = <1000>; 4696 type = "critical"; 4697 }; 4698 }; 4699 }; 4700 4701 cpu3-bottom-thermal { 4702 polling-delay-passive = <0>; 4703 polling-delay = <0>; 4704 thermal-sensors = <&tsens0 6>; 4705 4706 trips { 4707 cpu3_bottom_alert0: trip-point0 { 4708 temperature = <90000>; 4709 hysteresis = <2000>; 4710 type = "passive"; 4711 }; 4712 4713 cpu3_bottom_alert1: trip-point1 { 4714 temperature = <95000>; 4715 hysteresis = <2000>; 4716 type = "passive"; 4717 }; 4718 4719 cpu3_bottom_crit: cpu-critical { 4720 temperature = <110000>; 4721 hysteresis = <1000>; 4722 type = "critical"; 4723 }; 4724 }; 4725 }; 4726 4727 cpu4-top-thermal { 4728 polling-delay-passive = <0>; 4729 polling-delay = <0>; 4730 thermal-sensors = <&tsens0 7>; 4731 4732 trips { 4733 cpu4_top_alert0: trip-point0 { 4734 temperature = <90000>; 4735 hysteresis = <2000>; 4736 type = "passive"; 4737 }; 4738 4739 cpu4_top_alert1: trip-point1 { 4740 temperature = <95000>; 4741 hysteresis = <2000>; 4742 type = "passive"; 4743 }; 4744 4745 cpu4_top_crit: cpu-critical { 4746 temperature = <110000>; 4747 hysteresis = <1000>; 4748 type = "critical"; 4749 }; 4750 }; 4751 }; 4752 4753 cpu4-bottom-thermal { 4754 polling-delay-passive = <0>; 4755 polling-delay = <0>; 4756 thermal-sensors = <&tsens0 8>; 4757 4758 trips { 4759 cpu4_bottom_alert0: trip-point0 { 4760 temperature = <90000>; 4761 hysteresis = <2000>; 4762 type = "passive"; 4763 }; 4764 4765 cpu4_bottom_alert1: trip-point1 { 4766 temperature = <95000>; 4767 hysteresis = <2000>; 4768 type = "passive"; 4769 }; 4770 4771 cpu4_bottom_crit: cpu-critical { 4772 temperature = <110000>; 4773 hysteresis = <1000>; 4774 type = "critical"; 4775 }; 4776 }; 4777 }; 4778 4779 cpu5-top-thermal { 4780 polling-delay-passive = <0>; 4781 polling-delay = <0>; 4782 thermal-sensors = <&tsens0 9>; 4783 4784 trips { 4785 cpu5_top_alert0: trip-point0 { 4786 temperature = <90000>; 4787 hysteresis = <2000>; 4788 type = "passive"; 4789 }; 4790 4791 cpu5_top_alert1: trip-point1 { 4792 temperature = <95000>; 4793 hysteresis = <2000>; 4794 type = "passive"; 4795 }; 4796 4797 cpu5_top_crit: cpu-critical { 4798 temperature = <110000>; 4799 hysteresis = <1000>; 4800 type = "critical"; 4801 }; 4802 }; 4803 }; 4804 4805 cpu5-bottom-thermal { 4806 polling-delay-passive = <0>; 4807 polling-delay = <0>; 4808 thermal-sensors = <&tsens0 10>; 4809 4810 trips { 4811 cpu5_bottom_alert0: trip-point0 { 4812 temperature = <90000>; 4813 hysteresis = <2000>; 4814 type = "passive"; 4815 }; 4816 4817 cpu5_bottom_alert1: trip-point1 { 4818 temperature = <95000>; 4819 hysteresis = <2000>; 4820 type = "passive"; 4821 }; 4822 4823 cpu5_bottom_crit: cpu-critical { 4824 temperature = <110000>; 4825 hysteresis = <1000>; 4826 type = "critical"; 4827 }; 4828 }; 4829 }; 4830 4831 cpu6-top-thermal { 4832 polling-delay-passive = <0>; 4833 polling-delay = <0>; 4834 thermal-sensors = <&tsens0 11>; 4835 4836 trips { 4837 cpu6_top_alert0: trip-point0 { 4838 temperature = <90000>; 4839 hysteresis = <2000>; 4840 type = "passive"; 4841 }; 4842 4843 cpu6_top_alert1: trip-point1 { 4844 temperature = <95000>; 4845 hysteresis = <2000>; 4846 type = "passive"; 4847 }; 4848 4849 cpu6_top_crit: cpu-critical { 4850 temperature = <110000>; 4851 hysteresis = <1000>; 4852 type = "critical"; 4853 }; 4854 }; 4855 }; 4856 4857 cpu6-bottom-thermal { 4858 polling-delay-passive = <0>; 4859 polling-delay = <0>; 4860 thermal-sensors = <&tsens0 12>; 4861 4862 trips { 4863 cpu6_bottom_alert0: trip-point0 { 4864 temperature = <90000>; 4865 hysteresis = <2000>; 4866 type = "passive"; 4867 }; 4868 4869 cpu6_bottom_alert1: trip-point1 { 4870 temperature = <95000>; 4871 hysteresis = <2000>; 4872 type = "passive"; 4873 }; 4874 4875 cpu6_bottom_crit: cpu-critical { 4876 temperature = <110000>; 4877 hysteresis = <1000>; 4878 type = "critical"; 4879 }; 4880 }; 4881 }; 4882 4883 cpu7-top-thermal { 4884 polling-delay-passive = <0>; 4885 polling-delay = <0>; 4886 thermal-sensors = <&tsens0 13>; 4887 4888 trips { 4889 cpu7_top_alert0: trip-point0 { 4890 temperature = <90000>; 4891 hysteresis = <2000>; 4892 type = "passive"; 4893 }; 4894 4895 cpu7_top_alert1: trip-point1 { 4896 temperature = <95000>; 4897 hysteresis = <2000>; 4898 type = "passive"; 4899 }; 4900 4901 cpu7_top_crit: cpu-critical { 4902 temperature = <110000>; 4903 hysteresis = <1000>; 4904 type = "critical"; 4905 }; 4906 }; 4907 }; 4908 4909 cpu7-middle-thermal { 4910 polling-delay-passive = <0>; 4911 polling-delay = <0>; 4912 thermal-sensors = <&tsens0 14>; 4913 4914 trips { 4915 cpu7_middle_alert0: trip-point0 { 4916 temperature = <90000>; 4917 hysteresis = <2000>; 4918 type = "passive"; 4919 }; 4920 4921 cpu7_middle_alert1: trip-point1 { 4922 temperature = <95000>; 4923 hysteresis = <2000>; 4924 type = "passive"; 4925 }; 4926 4927 cpu7_middle_crit: cpu-critical { 4928 temperature = <110000>; 4929 hysteresis = <1000>; 4930 type = "critical"; 4931 }; 4932 }; 4933 }; 4934 4935 cpu7-bottom-thermal { 4936 polling-delay-passive = <0>; 4937 polling-delay = <0>; 4938 thermal-sensors = <&tsens0 15>; 4939 4940 trips { 4941 cpu7_bottom_alert0: trip-point0 { 4942 temperature = <90000>; 4943 hysteresis = <2000>; 4944 type = "passive"; 4945 }; 4946 4947 cpu7_bottom_alert1: trip-point1 { 4948 temperature = <95000>; 4949 hysteresis = <2000>; 4950 type = "passive"; 4951 }; 4952 4953 cpu7_bottom_crit: cpu-critical { 4954 temperature = <110000>; 4955 hysteresis = <1000>; 4956 type = "critical"; 4957 }; 4958 }; 4959 }; 4960 4961 aoss1-thermal { 4962 polling-delay-passive = <0>; 4963 polling-delay = <0>; 4964 thermal-sensors = <&tsens1 0>; 4965 4966 trips { 4967 thermal-engine-config { 4968 temperature = <125000>; 4969 hysteresis = <1000>; 4970 type = "passive"; 4971 }; 4972 4973 reset-mon-config { 4974 temperature = <115000>; 4975 hysteresis = <5000>; 4976 type = "passive"; 4977 }; 4978 }; 4979 }; 4980 4981 cpu0-thermal { 4982 polling-delay-passive = <0>; 4983 polling-delay = <0>; 4984 thermal-sensors = <&tsens1 1>; 4985 4986 trips { 4987 cpu0_alert0: trip-point0 { 4988 temperature = <90000>; 4989 hysteresis = <2000>; 4990 type = "passive"; 4991 }; 4992 4993 cpu0_alert1: trip-point1 { 4994 temperature = <95000>; 4995 hysteresis = <2000>; 4996 type = "passive"; 4997 }; 4998 4999 cpu0_crit: cpu-critical { 5000 temperature = <110000>; 5001 hysteresis = <1000>; 5002 type = "critical"; 5003 }; 5004 }; 5005 }; 5006 5007 cpu1-thermal { 5008 polling-delay-passive = <0>; 5009 polling-delay = <0>; 5010 thermal-sensors = <&tsens1 2>; 5011 5012 trips { 5013 cpu1_alert0: trip-point0 { 5014 temperature = <90000>; 5015 hysteresis = <2000>; 5016 type = "passive"; 5017 }; 5018 5019 cpu1_alert1: trip-point1 { 5020 temperature = <95000>; 5021 hysteresis = <2000>; 5022 type = "passive"; 5023 }; 5024 5025 cpu1_crit: cpu-critical { 5026 temperature = <110000>; 5027 hysteresis = <1000>; 5028 type = "critical"; 5029 }; 5030 }; 5031 }; 5032 5033 cpu2-thermal { 5034 polling-delay-passive = <0>; 5035 polling-delay = <0>; 5036 thermal-sensors = <&tsens1 3>; 5037 5038 trips { 5039 cpu2_alert0: trip-point0 { 5040 temperature = <90000>; 5041 hysteresis = <2000>; 5042 type = "passive"; 5043 }; 5044 5045 cpu2_alert1: trip-point1 { 5046 temperature = <95000>; 5047 hysteresis = <2000>; 5048 type = "passive"; 5049 }; 5050 5051 cpu2_crit: cpu-critical { 5052 temperature = <110000>; 5053 hysteresis = <1000>; 5054 type = "critical"; 5055 }; 5056 }; 5057 }; 5058 5059 cdsp0-thermal { 5060 polling-delay-passive = <10>; 5061 polling-delay = <0>; 5062 thermal-sensors = <&tsens2 4>; 5063 5064 trips { 5065 thermal-engine-config { 5066 temperature = <125000>; 5067 hysteresis = <1000>; 5068 type = "passive"; 5069 }; 5070 5071 thermal-hal-config { 5072 temperature = <125000>; 5073 hysteresis = <1000>; 5074 type = "passive"; 5075 }; 5076 5077 reset-mon-config { 5078 temperature = <115000>; 5079 hysteresis = <5000>; 5080 type = "passive"; 5081 }; 5082 5083 cdsp0_junction_config: junction-config { 5084 temperature = <95000>; 5085 hysteresis = <5000>; 5086 type = "passive"; 5087 }; 5088 }; 5089 }; 5090 5091 cdsp1-thermal { 5092 polling-delay-passive = <10>; 5093 polling-delay = <0>; 5094 thermal-sensors = <&tsens2 5>; 5095 5096 trips { 5097 thermal-engine-config { 5098 temperature = <125000>; 5099 hysteresis = <1000>; 5100 type = "passive"; 5101 }; 5102 5103 thermal-hal-config { 5104 temperature = <125000>; 5105 hysteresis = <1000>; 5106 type = "passive"; 5107 }; 5108 5109 reset-mon-config { 5110 temperature = <115000>; 5111 hysteresis = <5000>; 5112 type = "passive"; 5113 }; 5114 5115 cdsp1_junction_config: junction-config { 5116 temperature = <95000>; 5117 hysteresis = <5000>; 5118 type = "passive"; 5119 }; 5120 }; 5121 }; 5122 5123 cdsp2-thermal { 5124 polling-delay-passive = <10>; 5125 polling-delay = <0>; 5126 thermal-sensors = <&tsens2 6>; 5127 5128 trips { 5129 thermal-engine-config { 5130 temperature = <125000>; 5131 hysteresis = <1000>; 5132 type = "passive"; 5133 }; 5134 5135 thermal-hal-config { 5136 temperature = <125000>; 5137 hysteresis = <1000>; 5138 type = "passive"; 5139 }; 5140 5141 reset-mon-config { 5142 temperature = <115000>; 5143 hysteresis = <5000>; 5144 type = "passive"; 5145 }; 5146 5147 cdsp2_junction_config: junction-config { 5148 temperature = <95000>; 5149 hysteresis = <5000>; 5150 type = "passive"; 5151 }; 5152 }; 5153 }; 5154 5155 cdsp3-thermal { 5156 polling-delay-passive = <10>; 5157 polling-delay = <0>; 5158 thermal-sensors = <&tsens2 7>; 5159 5160 trips { 5161 thermal-engine-config { 5162 temperature = <125000>; 5163 hysteresis = <1000>; 5164 type = "passive"; 5165 }; 5166 5167 thermal-hal-config { 5168 temperature = <125000>; 5169 hysteresis = <1000>; 5170 type = "passive"; 5171 }; 5172 5173 reset-mon-config { 5174 temperature = <115000>; 5175 hysteresis = <5000>; 5176 type = "passive"; 5177 }; 5178 5179 cdsp3_junction_config: junction-config { 5180 temperature = <95000>; 5181 hysteresis = <5000>; 5182 type = "passive"; 5183 }; 5184 }; 5185 }; 5186 5187 video-thermal { 5188 polling-delay-passive = <0>; 5189 polling-delay = <0>; 5190 thermal-sensors = <&tsens1 8>; 5191 5192 trips { 5193 thermal-engine-config { 5194 temperature = <125000>; 5195 hysteresis = <1000>; 5196 type = "passive"; 5197 }; 5198 5199 reset-mon-config { 5200 temperature = <115000>; 5201 hysteresis = <5000>; 5202 type = "passive"; 5203 }; 5204 }; 5205 }; 5206 5207 mem-thermal { 5208 polling-delay-passive = <10>; 5209 polling-delay = <0>; 5210 thermal-sensors = <&tsens1 9>; 5211 5212 trips { 5213 thermal-engine-config { 5214 temperature = <125000>; 5215 hysteresis = <1000>; 5216 type = "passive"; 5217 }; 5218 5219 ddr_config0: ddr0-config { 5220 temperature = <90000>; 5221 hysteresis = <5000>; 5222 type = "passive"; 5223 }; 5224 5225 reset-mon-config { 5226 temperature = <115000>; 5227 hysteresis = <5000>; 5228 type = "passive"; 5229 }; 5230 }; 5231 }; 5232 5233 modem0-thermal { 5234 polling-delay-passive = <0>; 5235 polling-delay = <0>; 5236 thermal-sensors = <&tsens1 10>; 5237 5238 trips { 5239 thermal-engine-config { 5240 temperature = <125000>; 5241 hysteresis = <1000>; 5242 type = "passive"; 5243 }; 5244 5245 mdmss0_config0: mdmss0-config0 { 5246 temperature = <102000>; 5247 hysteresis = <3000>; 5248 type = "passive"; 5249 }; 5250 5251 mdmss0_config1: mdmss0-config1 { 5252 temperature = <105000>; 5253 hysteresis = <3000>; 5254 type = "passive"; 5255 }; 5256 5257 reset-mon-config { 5258 temperature = <115000>; 5259 hysteresis = <5000>; 5260 type = "passive"; 5261 }; 5262 }; 5263 }; 5264 5265 modem1-thermal { 5266 polling-delay-passive = <0>; 5267 polling-delay = <0>; 5268 thermal-sensors = <&tsens1 11>; 5269 5270 trips { 5271 thermal-engine-config { 5272 temperature = <125000>; 5273 hysteresis = <1000>; 5274 type = "passive"; 5275 }; 5276 5277 mdmss1_config0: mdmss1-config0 { 5278 temperature = <102000>; 5279 hysteresis = <3000>; 5280 type = "passive"; 5281 }; 5282 5283 mdmss1_config1: mdmss1-config1 { 5284 temperature = <105000>; 5285 hysteresis = <3000>; 5286 type = "passive"; 5287 }; 5288 5289 reset-mon-config { 5290 temperature = <115000>; 5291 hysteresis = <5000>; 5292 type = "passive"; 5293 }; 5294 }; 5295 }; 5296 5297 modem2-thermal { 5298 polling-delay-passive = <0>; 5299 polling-delay = <0>; 5300 thermal-sensors = <&tsens1 12>; 5301 5302 trips { 5303 thermal-engine-config { 5304 temperature = <125000>; 5305 hysteresis = <1000>; 5306 type = "passive"; 5307 }; 5308 5309 mdmss2_config0: mdmss2-config0 { 5310 temperature = <102000>; 5311 hysteresis = <3000>; 5312 type = "passive"; 5313 }; 5314 5315 mdmss2_config1: mdmss2-config1 { 5316 temperature = <105000>; 5317 hysteresis = <3000>; 5318 type = "passive"; 5319 }; 5320 5321 reset-mon-config { 5322 temperature = <115000>; 5323 hysteresis = <5000>; 5324 type = "passive"; 5325 }; 5326 }; 5327 }; 5328 5329 modem3-thermal { 5330 polling-delay-passive = <0>; 5331 polling-delay = <0>; 5332 thermal-sensors = <&tsens1 13>; 5333 5334 trips { 5335 thermal-engine-config { 5336 temperature = <125000>; 5337 hysteresis = <1000>; 5338 type = "passive"; 5339 }; 5340 5341 mdmss3_config0: mdmss3-config0 { 5342 temperature = <102000>; 5343 hysteresis = <3000>; 5344 type = "passive"; 5345 }; 5346 5347 mdmss3_config1: mdmss3-config1 { 5348 temperature = <105000>; 5349 hysteresis = <3000>; 5350 type = "passive"; 5351 }; 5352 5353 reset-mon-config { 5354 temperature = <115000>; 5355 hysteresis = <5000>; 5356 type = "passive"; 5357 }; 5358 }; 5359 }; 5360 5361 camera0-thermal { 5362 polling-delay-passive = <0>; 5363 polling-delay = <0>; 5364 thermal-sensors = <&tsens1 14>; 5365 5366 trips { 5367 thermal-engine-config { 5368 temperature = <125000>; 5369 hysteresis = <1000>; 5370 type = "passive"; 5371 }; 5372 5373 reset-mon-config { 5374 temperature = <115000>; 5375 hysteresis = <5000>; 5376 type = "passive"; 5377 }; 5378 }; 5379 }; 5380 5381 camera1-thermal { 5382 polling-delay-passive = <0>; 5383 polling-delay = <0>; 5384 thermal-sensors = <&tsens1 15>; 5385 5386 trips { 5387 thermal-engine-config { 5388 temperature = <125000>; 5389 hysteresis = <1000>; 5390 type = "passive"; 5391 }; 5392 5393 reset-mon-config { 5394 temperature = <115000>; 5395 hysteresis = <5000>; 5396 type = "passive"; 5397 }; 5398 }; 5399 }; 5400 5401 aoss2-thermal { 5402 polling-delay-passive = <0>; 5403 polling-delay = <0>; 5404 thermal-sensors = <&tsens2 0>; 5405 5406 trips { 5407 thermal-engine-config { 5408 temperature = <125000>; 5409 hysteresis = <1000>; 5410 type = "passive"; 5411 }; 5412 5413 reset-mon-config { 5414 temperature = <115000>; 5415 hysteresis = <5000>; 5416 type = "passive"; 5417 }; 5418 }; 5419 }; 5420 5421 gpuss-0-thermal { 5422 polling-delay-passive = <10>; 5423 polling-delay = <0>; 5424 thermal-sensors = <&tsens2 1>; 5425 5426 cooling-maps { 5427 map0 { 5428 trip = <&gpu0_junction_config>; 5429 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5430 }; 5431 }; 5432 5433 trips { 5434 thermal-engine-config { 5435 temperature = <125000>; 5436 hysteresis = <1000>; 5437 type = "passive"; 5438 }; 5439 5440 thermal-hal-config { 5441 temperature = <125000>; 5442 hysteresis = <1000>; 5443 type = "passive"; 5444 }; 5445 5446 reset-mon-config { 5447 temperature = <115000>; 5448 hysteresis = <5000>; 5449 type = "passive"; 5450 }; 5451 5452 gpu0_junction_config: junction-config { 5453 temperature = <95000>; 5454 hysteresis = <5000>; 5455 type = "passive"; 5456 }; 5457 }; 5458 }; 5459 5460 gpuss-1-thermal { 5461 polling-delay-passive = <10>; 5462 polling-delay = <0>; 5463 thermal-sensors = <&tsens2 2>; 5464 5465 cooling-maps { 5466 map0 { 5467 trip = <&gpu1_junction_config>; 5468 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5469 }; 5470 }; 5471 5472 trips { 5473 thermal-engine-config { 5474 temperature = <125000>; 5475 hysteresis = <1000>; 5476 type = "passive"; 5477 }; 5478 5479 thermal-hal-config { 5480 temperature = <125000>; 5481 hysteresis = <1000>; 5482 type = "passive"; 5483 }; 5484 5485 reset-mon-config { 5486 temperature = <115000>; 5487 hysteresis = <5000>; 5488 type = "passive"; 5489 }; 5490 5491 gpu1_junction_config: junction-config { 5492 temperature = <95000>; 5493 hysteresis = <5000>; 5494 type = "passive"; 5495 }; 5496 }; 5497 }; 5498 5499 gpuss-2-thermal { 5500 polling-delay-passive = <10>; 5501 polling-delay = <0>; 5502 thermal-sensors = <&tsens2 3>; 5503 5504 cooling-maps { 5505 map0 { 5506 trip = <&gpu2_junction_config>; 5507 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5508 }; 5509 }; 5510 5511 trips { 5512 thermal-engine-config { 5513 temperature = <125000>; 5514 hysteresis = <1000>; 5515 type = "passive"; 5516 }; 5517 5518 thermal-hal-config { 5519 temperature = <125000>; 5520 hysteresis = <1000>; 5521 type = "passive"; 5522 }; 5523 5524 reset-mon-config { 5525 temperature = <115000>; 5526 hysteresis = <5000>; 5527 type = "passive"; 5528 }; 5529 5530 gpu2_junction_config: junction-config { 5531 temperature = <95000>; 5532 hysteresis = <5000>; 5533 type = "passive"; 5534 }; 5535 }; 5536 }; 5537 5538 gpuss-3-thermal { 5539 polling-delay-passive = <10>; 5540 polling-delay = <0>; 5541 thermal-sensors = <&tsens2 4>; 5542 5543 cooling-maps { 5544 map0 { 5545 trip = <&gpu3_junction_config>; 5546 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5547 }; 5548 }; 5549 5550 trips { 5551 thermal-engine-config { 5552 temperature = <125000>; 5553 hysteresis = <1000>; 5554 type = "passive"; 5555 }; 5556 5557 thermal-hal-config { 5558 temperature = <125000>; 5559 hysteresis = <1000>; 5560 type = "passive"; 5561 }; 5562 5563 reset-mon-config { 5564 temperature = <115000>; 5565 hysteresis = <5000>; 5566 type = "passive"; 5567 }; 5568 5569 gpu3_junction_config: junction-config { 5570 temperature = <95000>; 5571 hysteresis = <5000>; 5572 type = "passive"; 5573 }; 5574 }; 5575 }; 5576 5577 gpuss-4-thermal { 5578 polling-delay-passive = <10>; 5579 polling-delay = <0>; 5580 thermal-sensors = <&tsens2 5>; 5581 5582 cooling-maps { 5583 map0 { 5584 trip = <&gpu4_junction_config>; 5585 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5586 }; 5587 }; 5588 5589 trips { 5590 thermal-engine-config { 5591 temperature = <125000>; 5592 hysteresis = <1000>; 5593 type = "passive"; 5594 }; 5595 5596 thermal-hal-config { 5597 temperature = <125000>; 5598 hysteresis = <1000>; 5599 type = "passive"; 5600 }; 5601 5602 reset-mon-config { 5603 temperature = <115000>; 5604 hysteresis = <5000>; 5605 type = "passive"; 5606 }; 5607 5608 gpu4_junction_config: junction-config { 5609 temperature = <95000>; 5610 hysteresis = <5000>; 5611 type = "passive"; 5612 }; 5613 }; 5614 }; 5615 5616 gpuss-5-thermal { 5617 polling-delay-passive = <10>; 5618 polling-delay = <0>; 5619 thermal-sensors = <&tsens2 6>; 5620 5621 cooling-maps { 5622 map0 { 5623 trip = <&gpu5_junction_config>; 5624 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5625 }; 5626 }; 5627 5628 trips { 5629 thermal-engine-config { 5630 temperature = <125000>; 5631 hysteresis = <1000>; 5632 type = "passive"; 5633 }; 5634 5635 thermal-hal-config { 5636 temperature = <125000>; 5637 hysteresis = <1000>; 5638 type = "passive"; 5639 }; 5640 5641 reset-mon-config { 5642 temperature = <115000>; 5643 hysteresis = <5000>; 5644 type = "passive"; 5645 }; 5646 5647 gpu5_junction_config: junction-config { 5648 temperature = <95000>; 5649 hysteresis = <5000>; 5650 type = "passive"; 5651 }; 5652 }; 5653 }; 5654 5655 gpuss-6-thermal { 5656 polling-delay-passive = <10>; 5657 polling-delay = <0>; 5658 thermal-sensors = <&tsens2 7>; 5659 5660 cooling-maps { 5661 map0 { 5662 trip = <&gpu6_junction_config>; 5663 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5664 }; 5665 }; 5666 5667 trips { 5668 thermal-engine-config { 5669 temperature = <125000>; 5670 hysteresis = <1000>; 5671 type = "passive"; 5672 }; 5673 5674 thermal-hal-config { 5675 temperature = <125000>; 5676 hysteresis = <1000>; 5677 type = "passive"; 5678 }; 5679 5680 reset-mon-config { 5681 temperature = <115000>; 5682 hysteresis = <5000>; 5683 type = "passive"; 5684 }; 5685 5686 gpu6_junction_config: junction-config { 5687 temperature = <95000>; 5688 hysteresis = <5000>; 5689 type = "passive"; 5690 }; 5691 }; 5692 }; 5693 5694 gpuss-7-thermal { 5695 polling-delay-passive = <10>; 5696 polling-delay = <0>; 5697 thermal-sensors = <&tsens2 8>; 5698 5699 cooling-maps { 5700 map0 { 5701 trip = <&gpu7_junction_config>; 5702 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5703 }; 5704 }; 5705 5706 trips { 5707 thermal-engine-config { 5708 temperature = <125000>; 5709 hysteresis = <1000>; 5710 type = "passive"; 5711 }; 5712 5713 thermal-hal-config { 5714 temperature = <125000>; 5715 hysteresis = <1000>; 5716 type = "passive"; 5717 }; 5718 5719 reset-mon-config { 5720 temperature = <115000>; 5721 hysteresis = <5000>; 5722 type = "passive"; 5723 }; 5724 5725 gpu7_junction_config: junction-config { 5726 temperature = <95000>; 5727 hysteresis = <5000>; 5728 type = "passive"; 5729 }; 5730 }; 5731 }; 5732 }; 5733 5734 timer { 5735 compatible = "arm,armv8-timer"; 5736 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5737 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5738 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5739 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5740 }; 5741}; 5742