1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8450-videocc.h> 8#include <dt-bindings/clock/qcom,sm8550-camcc.h> 9#include <dt-bindings/clock/qcom,sm8550-gcc.h> 10#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 11#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 12#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 24#include <dt-bindings/phy/phy-qcom-qmp.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 chosen { }; 34 35 clocks { 36 xo_board: xo-board { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 }; 45 46 bi_tcxo_div2: bi-tcxo-div2-clk { 47 #clock-cells = <0>; 48 compatible = "fixed-factor-clock"; 49 clocks = <&rpmhcc RPMH_CXO_CLK>; 50 clock-mult = <1>; 51 clock-div = <2>; 52 }; 53 54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 55 #clock-cells = <0>; 56 compatible = "fixed-factor-clock"; 57 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 58 clock-mult = <1>; 59 clock-div = <2>; 60 }; 61 62 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 }; 66 }; 67 68 cpus { 69 #address-cells = <2>; 70 #size-cells = <0>; 71 72 CPU0: cpu@0 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a510"; 75 reg = <0 0>; 76 clocks = <&cpufreq_hw 0>; 77 enable-method = "psci"; 78 next-level-cache = <&L2_0>; 79 power-domains = <&CPU_PD0>; 80 power-domain-names = "psci"; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 capacity-dmips-mhz = <1024>; 83 dynamic-power-coefficient = <100>; 84 #cooling-cells = <2>; 85 L2_0: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 cache-unified; 89 next-level-cache = <&L3_0>; 90 L3_0: l3-cache { 91 compatible = "cache"; 92 cache-level = <3>; 93 cache-unified; 94 }; 95 }; 96 }; 97 98 CPU1: cpu@100 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a510"; 101 reg = <0 0x100>; 102 clocks = <&cpufreq_hw 0>; 103 enable-method = "psci"; 104 next-level-cache = <&L2_100>; 105 power-domains = <&CPU_PD1>; 106 power-domain-names = "psci"; 107 qcom,freq-domain = <&cpufreq_hw 0>; 108 capacity-dmips-mhz = <1024>; 109 dynamic-power-coefficient = <100>; 110 #cooling-cells = <2>; 111 L2_100: l2-cache { 112 compatible = "cache"; 113 cache-level = <2>; 114 cache-unified; 115 next-level-cache = <&L3_0>; 116 }; 117 }; 118 119 CPU2: cpu@200 { 120 device_type = "cpu"; 121 compatible = "arm,cortex-a510"; 122 reg = <0 0x200>; 123 clocks = <&cpufreq_hw 0>; 124 enable-method = "psci"; 125 next-level-cache = <&L2_200>; 126 power-domains = <&CPU_PD2>; 127 power-domain-names = "psci"; 128 qcom,freq-domain = <&cpufreq_hw 0>; 129 capacity-dmips-mhz = <1024>; 130 dynamic-power-coefficient = <100>; 131 #cooling-cells = <2>; 132 L2_200: l2-cache { 133 compatible = "cache"; 134 cache-level = <2>; 135 cache-unified; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU3: cpu@300 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-a715"; 143 reg = <0 0x300>; 144 clocks = <&cpufreq_hw 1>; 145 enable-method = "psci"; 146 next-level-cache = <&L2_300>; 147 power-domains = <&CPU_PD3>; 148 power-domain-names = "psci"; 149 qcom,freq-domain = <&cpufreq_hw 1>; 150 capacity-dmips-mhz = <1792>; 151 dynamic-power-coefficient = <270>; 152 #cooling-cells = <2>; 153 L2_300: l2-cache { 154 compatible = "cache"; 155 cache-level = <2>; 156 cache-unified; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 161 CPU4: cpu@400 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-a715"; 164 reg = <0 0x400>; 165 clocks = <&cpufreq_hw 1>; 166 enable-method = "psci"; 167 next-level-cache = <&L2_400>; 168 power-domains = <&CPU_PD4>; 169 power-domain-names = "psci"; 170 qcom,freq-domain = <&cpufreq_hw 1>; 171 capacity-dmips-mhz = <1792>; 172 dynamic-power-coefficient = <270>; 173 #cooling-cells = <2>; 174 L2_400: l2-cache { 175 compatible = "cache"; 176 cache-level = <2>; 177 cache-unified; 178 next-level-cache = <&L3_0>; 179 }; 180 }; 181 182 CPU5: cpu@500 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a710"; 185 reg = <0 0x500>; 186 clocks = <&cpufreq_hw 1>; 187 enable-method = "psci"; 188 next-level-cache = <&L2_500>; 189 power-domains = <&CPU_PD5>; 190 power-domain-names = "psci"; 191 qcom,freq-domain = <&cpufreq_hw 1>; 192 capacity-dmips-mhz = <1792>; 193 dynamic-power-coefficient = <270>; 194 #cooling-cells = <2>; 195 L2_500: l2-cache { 196 compatible = "cache"; 197 cache-level = <2>; 198 cache-unified; 199 next-level-cache = <&L3_0>; 200 }; 201 }; 202 203 CPU6: cpu@600 { 204 device_type = "cpu"; 205 compatible = "arm,cortex-a710"; 206 reg = <0 0x600>; 207 clocks = <&cpufreq_hw 1>; 208 enable-method = "psci"; 209 next-level-cache = <&L2_600>; 210 power-domains = <&CPU_PD6>; 211 power-domain-names = "psci"; 212 qcom,freq-domain = <&cpufreq_hw 1>; 213 capacity-dmips-mhz = <1792>; 214 dynamic-power-coefficient = <270>; 215 #cooling-cells = <2>; 216 L2_600: l2-cache { 217 compatible = "cache"; 218 cache-level = <2>; 219 cache-unified; 220 next-level-cache = <&L3_0>; 221 }; 222 }; 223 224 CPU7: cpu@700 { 225 device_type = "cpu"; 226 compatible = "arm,cortex-x3"; 227 reg = <0 0x700>; 228 clocks = <&cpufreq_hw 2>; 229 enable-method = "psci"; 230 next-level-cache = <&L2_700>; 231 power-domains = <&CPU_PD7>; 232 power-domain-names = "psci"; 233 qcom,freq-domain = <&cpufreq_hw 2>; 234 capacity-dmips-mhz = <1894>; 235 dynamic-power-coefficient = <588>; 236 #cooling-cells = <2>; 237 L2_700: l2-cache { 238 compatible = "cache"; 239 cache-level = <2>; 240 cache-unified; 241 next-level-cache = <&L3_0>; 242 }; 243 }; 244 245 cpu-map { 246 cluster0 { 247 core0 { 248 cpu = <&CPU0>; 249 }; 250 251 core1 { 252 cpu = <&CPU1>; 253 }; 254 255 core2 { 256 cpu = <&CPU2>; 257 }; 258 259 core3 { 260 cpu = <&CPU3>; 261 }; 262 263 core4 { 264 cpu = <&CPU4>; 265 }; 266 267 core5 { 268 cpu = <&CPU5>; 269 }; 270 271 core6 { 272 cpu = <&CPU6>; 273 }; 274 275 core7 { 276 cpu = <&CPU7>; 277 }; 278 }; 279 }; 280 281 idle-states { 282 entry-method = "psci"; 283 284 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 285 compatible = "arm,idle-state"; 286 idle-state-name = "silver-rail-power-collapse"; 287 arm,psci-suspend-param = <0x40000004>; 288 entry-latency-us = <800>; 289 exit-latency-us = <750>; 290 min-residency-us = <4090>; 291 local-timer-stop; 292 }; 293 294 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 295 compatible = "arm,idle-state"; 296 idle-state-name = "gold-rail-power-collapse"; 297 arm,psci-suspend-param = <0x40000004>; 298 entry-latency-us = <600>; 299 exit-latency-us = <1550>; 300 min-residency-us = <4791>; 301 local-timer-stop; 302 }; 303 }; 304 305 domain-idle-states { 306 CLUSTER_SLEEP_0: cluster-sleep-0 { 307 compatible = "domain-idle-state"; 308 arm,psci-suspend-param = <0x41000044>; 309 entry-latency-us = <1050>; 310 exit-latency-us = <2500>; 311 min-residency-us = <5309>; 312 }; 313 314 CLUSTER_SLEEP_1: cluster-sleep-1 { 315 compatible = "domain-idle-state"; 316 arm,psci-suspend-param = <0x4100c344>; 317 entry-latency-us = <2700>; 318 exit-latency-us = <3500>; 319 min-residency-us = <13959>; 320 }; 321 }; 322 }; 323 324 firmware { 325 scm: scm { 326 compatible = "qcom,scm-sm8550", "qcom,scm"; 327 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 328 }; 329 }; 330 331 clk_virt: interconnect-0 { 332 compatible = "qcom,sm8550-clk-virt"; 333 #interconnect-cells = <2>; 334 qcom,bcm-voters = <&apps_bcm_voter>; 335 }; 336 337 mc_virt: interconnect-1 { 338 compatible = "qcom,sm8550-mc-virt"; 339 #interconnect-cells = <2>; 340 qcom,bcm-voters = <&apps_bcm_voter>; 341 }; 342 343 memory@a0000000 { 344 device_type = "memory"; 345 /* We expect the bootloader to fill in the size */ 346 reg = <0 0xa0000000 0 0>; 347 }; 348 349 pmu { 350 compatible = "arm,armv8-pmuv3"; 351 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 352 }; 353 354 psci { 355 compatible = "arm,psci-1.0"; 356 method = "smc"; 357 358 CPU_PD0: power-domain-cpu0 { 359 #power-domain-cells = <0>; 360 power-domains = <&CLUSTER_PD>; 361 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 362 }; 363 364 CPU_PD1: power-domain-cpu1 { 365 #power-domain-cells = <0>; 366 power-domains = <&CLUSTER_PD>; 367 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 368 }; 369 370 CPU_PD2: power-domain-cpu2 { 371 #power-domain-cells = <0>; 372 power-domains = <&CLUSTER_PD>; 373 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 374 }; 375 376 CPU_PD3: power-domain-cpu3 { 377 #power-domain-cells = <0>; 378 power-domains = <&CLUSTER_PD>; 379 domain-idle-states = <&BIG_CPU_SLEEP_0>; 380 }; 381 382 CPU_PD4: power-domain-cpu4 { 383 #power-domain-cells = <0>; 384 power-domains = <&CLUSTER_PD>; 385 domain-idle-states = <&BIG_CPU_SLEEP_0>; 386 }; 387 388 CPU_PD5: power-domain-cpu5 { 389 #power-domain-cells = <0>; 390 power-domains = <&CLUSTER_PD>; 391 domain-idle-states = <&BIG_CPU_SLEEP_0>; 392 }; 393 394 CPU_PD6: power-domain-cpu6 { 395 #power-domain-cells = <0>; 396 power-domains = <&CLUSTER_PD>; 397 domain-idle-states = <&BIG_CPU_SLEEP_0>; 398 }; 399 400 CPU_PD7: power-domain-cpu7 { 401 #power-domain-cells = <0>; 402 power-domains = <&CLUSTER_PD>; 403 domain-idle-states = <&BIG_CPU_SLEEP_0>; 404 }; 405 406 CLUSTER_PD: power-domain-cluster { 407 #power-domain-cells = <0>; 408 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 409 }; 410 }; 411 412 reserved_memory: reserved-memory { 413 #address-cells = <2>; 414 #size-cells = <2>; 415 ranges; 416 417 hyp_mem: hyp-region@80000000 { 418 reg = <0 0x80000000 0 0xa00000>; 419 no-map; 420 }; 421 422 cpusys_vm_mem: cpusys-vm-region@80a00000 { 423 reg = <0 0x80a00000 0 0x400000>; 424 no-map; 425 }; 426 427 hyp_tags_mem: hyp-tags-region@80e00000 { 428 reg = <0 0x80e00000 0 0x3d0000>; 429 no-map; 430 }; 431 432 xbl_sc_mem: xbl-sc-region@d8100000 { 433 reg = <0 0xd8100000 0 0x40000>; 434 no-map; 435 }; 436 437 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 438 reg = <0 0x811d0000 0 0x30000>; 439 no-map; 440 }; 441 442 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 443 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 444 reg = <0 0x81a00000 0 0x260000>; 445 no-map; 446 }; 447 448 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 449 compatible = "qcom,cmd-db"; 450 reg = <0 0x81c60000 0 0x20000>; 451 no-map; 452 }; 453 454 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 455 aop_config_merged_mem: aop-config-merged-region@81c80000 { 456 reg = <0 0x81c80000 0 0x74000>; 457 no-map; 458 }; 459 460 /* secdata region can be reused by apps */ 461 smem: smem@81d00000 { 462 compatible = "qcom,smem"; 463 reg = <0 0x81d00000 0 0x200000>; 464 hwlocks = <&tcsr_mutex 3>; 465 no-map; 466 }; 467 468 adsp_mhi_mem: adsp-mhi-region@81f00000 { 469 reg = <0 0x81f00000 0 0x20000>; 470 no-map; 471 }; 472 473 global_sync_mem: global-sync-region@82600000 { 474 reg = <0 0x82600000 0 0x100000>; 475 no-map; 476 }; 477 478 tz_stat_mem: tz-stat-region@82700000 { 479 reg = <0 0x82700000 0 0x100000>; 480 no-map; 481 }; 482 483 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 484 reg = <0 0x82800000 0 0x4600000>; 485 no-map; 486 }; 487 488 mpss_mem: mpss-region@8a800000 { 489 reg = <0 0x8a800000 0 0x10800000>; 490 no-map; 491 }; 492 493 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 494 reg = <0 0x9b000000 0 0x80000>; 495 no-map; 496 }; 497 498 ipa_fw_mem: ipa-fw-region@9b080000 { 499 reg = <0 0x9b080000 0 0x10000>; 500 no-map; 501 }; 502 503 ipa_gsi_mem: ipa-gsi-region@9b090000 { 504 reg = <0 0x9b090000 0 0xa000>; 505 no-map; 506 }; 507 508 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 509 reg = <0 0x9b09a000 0 0x2000>; 510 no-map; 511 }; 512 513 spss_region_mem: spss-region@9b100000 { 514 reg = <0 0x9b100000 0 0x180000>; 515 no-map; 516 }; 517 518 /* First part of the "SPU secure shared memory" region */ 519 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 520 reg = <0 0x9b280000 0 0x60000>; 521 no-map; 522 }; 523 524 /* Second part of the "SPU secure shared memory" region */ 525 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 526 reg = <0 0x9b2e0000 0 0x20000>; 527 no-map; 528 }; 529 530 camera_mem: camera-region@9b300000 { 531 reg = <0 0x9b300000 0 0x800000>; 532 no-map; 533 }; 534 535 video_mem: video-region@9bb00000 { 536 reg = <0 0x9bb00000 0 0x700000>; 537 no-map; 538 }; 539 540 cvp_mem: cvp-region@9c200000 { 541 reg = <0 0x9c200000 0 0x700000>; 542 no-map; 543 }; 544 545 cdsp_mem: cdsp-region@9c900000 { 546 reg = <0 0x9c900000 0 0x2000000>; 547 no-map; 548 }; 549 550 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 551 reg = <0 0x9e900000 0 0x80000>; 552 no-map; 553 }; 554 555 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 556 reg = <0 0x9e980000 0 0x80000>; 557 no-map; 558 }; 559 560 adspslpi_mem: adspslpi-region@9ea00000 { 561 reg = <0 0x9ea00000 0 0x4080000>; 562 no-map; 563 }; 564 565 /* uefi region can be reused by apps */ 566 567 /* Linux kernel image is loaded at 0xa8000000 */ 568 569 rmtfs_mem: rmtfs-region@d4a80000 { 570 compatible = "qcom,rmtfs-mem"; 571 reg = <0x0 0xd4a80000 0x0 0x280000>; 572 no-map; 573 574 qcom,client-id = <1>; 575 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 576 }; 577 578 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 579 reg = <0 0xd4d00000 0 0x3300000>; 580 no-map; 581 }; 582 583 tz_reserved_mem: tz-reserved-region@d8000000 { 584 reg = <0 0xd8000000 0 0x100000>; 585 no-map; 586 }; 587 588 cpucp_fw_mem: cpucp-fw-region@d8140000 { 589 reg = <0 0xd8140000 0 0x1c0000>; 590 no-map; 591 }; 592 593 qtee_mem: qtee-region@d8300000 { 594 reg = <0 0xd8300000 0 0x500000>; 595 no-map; 596 }; 597 598 ta_mem: ta-region@d8800000 { 599 reg = <0 0xd8800000 0 0x8a00000>; 600 no-map; 601 }; 602 603 tz_tags_mem: tz-tags-region@e1200000 { 604 reg = <0 0xe1200000 0 0x2740000>; 605 no-map; 606 }; 607 608 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 609 reg = <0 0xe6440000 0 0x279000>; 610 no-map; 611 }; 612 613 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 614 reg = <0 0xf3600000 0 0x4aee000>; 615 no-map; 616 }; 617 618 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 619 reg = <0 0xf80ee000 0 0x1000>; 620 no-map; 621 }; 622 623 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 624 reg = <0 0xf80ef000 0 0x9000>; 625 no-map; 626 }; 627 628 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 629 reg = <0 0xf80f8000 0 0x4000>; 630 no-map; 631 }; 632 633 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 634 reg = <0 0xf80fc000 0 0x4000>; 635 no-map; 636 }; 637 638 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 639 reg = <0 0xf8100000 0 0x100000>; 640 no-map; 641 }; 642 643 oem_vm_mem: oem-vm-region@f8400000 { 644 reg = <0 0xf8400000 0 0x4800000>; 645 no-map; 646 }; 647 648 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 649 reg = <0 0xfcc00000 0 0x4000>; 650 no-map; 651 }; 652 653 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 654 reg = <0 0xfcc04000 0 0x100000>; 655 no-map; 656 }; 657 658 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 659 reg = <0 0xfce00000 0 0x2900000>; 660 no-map; 661 }; 662 663 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 664 reg = <0 0xff700000 0 0x100000>; 665 no-map; 666 }; 667 }; 668 669 smp2p-adsp { 670 compatible = "qcom,smp2p"; 671 qcom,smem = <443>, <429>; 672 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 673 IPCC_MPROC_SIGNAL_SMP2P 674 IRQ_TYPE_EDGE_RISING>; 675 mboxes = <&ipcc IPCC_CLIENT_LPASS 676 IPCC_MPROC_SIGNAL_SMP2P>; 677 678 qcom,local-pid = <0>; 679 qcom,remote-pid = <2>; 680 681 smp2p_adsp_out: master-kernel { 682 qcom,entry-name = "master-kernel"; 683 #qcom,smem-state-cells = <1>; 684 }; 685 686 smp2p_adsp_in: slave-kernel { 687 qcom,entry-name = "slave-kernel"; 688 interrupt-controller; 689 #interrupt-cells = <2>; 690 }; 691 }; 692 693 smp2p-cdsp { 694 compatible = "qcom,smp2p"; 695 qcom,smem = <94>, <432>; 696 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 697 IPCC_MPROC_SIGNAL_SMP2P 698 IRQ_TYPE_EDGE_RISING>; 699 mboxes = <&ipcc IPCC_CLIENT_CDSP 700 IPCC_MPROC_SIGNAL_SMP2P>; 701 702 qcom,local-pid = <0>; 703 qcom,remote-pid = <5>; 704 705 smp2p_cdsp_out: master-kernel { 706 qcom,entry-name = "master-kernel"; 707 #qcom,smem-state-cells = <1>; 708 }; 709 710 smp2p_cdsp_in: slave-kernel { 711 qcom,entry-name = "slave-kernel"; 712 interrupt-controller; 713 #interrupt-cells = <2>; 714 }; 715 }; 716 717 smp2p-modem { 718 compatible = "qcom,smp2p"; 719 qcom,smem = <435>, <428>; 720 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 721 IPCC_MPROC_SIGNAL_SMP2P 722 IRQ_TYPE_EDGE_RISING>; 723 mboxes = <&ipcc IPCC_CLIENT_MPSS 724 IPCC_MPROC_SIGNAL_SMP2P>; 725 726 qcom,local-pid = <0>; 727 qcom,remote-pid = <1>; 728 729 smp2p_modem_out: master-kernel { 730 qcom,entry-name = "master-kernel"; 731 #qcom,smem-state-cells = <1>; 732 }; 733 734 smp2p_modem_in: slave-kernel { 735 qcom,entry-name = "slave-kernel"; 736 interrupt-controller; 737 #interrupt-cells = <2>; 738 }; 739 740 ipa_smp2p_out: ipa-ap-to-modem { 741 qcom,entry-name = "ipa"; 742 #qcom,smem-state-cells = <1>; 743 }; 744 745 ipa_smp2p_in: ipa-modem-to-ap { 746 qcom,entry-name = "ipa"; 747 interrupt-controller; 748 #interrupt-cells = <2>; 749 }; 750 }; 751 752 soc: soc@0 { 753 compatible = "simple-bus"; 754 ranges = <0 0 0 0 0x10 0>; 755 dma-ranges = <0 0 0 0 0x10 0>; 756 757 #address-cells = <2>; 758 #size-cells = <2>; 759 760 gcc: clock-controller@100000 { 761 compatible = "qcom,sm8550-gcc"; 762 reg = <0 0x00100000 0 0x1f4200>; 763 #clock-cells = <1>; 764 #reset-cells = <1>; 765 #power-domain-cells = <1>; 766 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 767 <&pcie0_phy>, 768 <&pcie1_phy>, 769 <&pcie_1_phy_aux_clk>, 770 <&ufs_mem_phy 0>, 771 <&ufs_mem_phy 1>, 772 <&ufs_mem_phy 2>, 773 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 774 }; 775 776 ipcc: mailbox@408000 { 777 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 778 reg = <0 0x00408000 0 0x1000>; 779 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 780 interrupt-controller; 781 #interrupt-cells = <3>; 782 #mbox-cells = <2>; 783 }; 784 785 gpi_dma2: dma-controller@800000 { 786 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 787 #dma-cells = <3>; 788 reg = <0 0x00800000 0 0x60000>; 789 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 801 dma-channels = <12>; 802 dma-channel-mask = <0x3e>; 803 iommus = <&apps_smmu 0x436 0>; 804 status = "disabled"; 805 }; 806 807 qupv3_id_1: geniqup@8c0000 { 808 compatible = "qcom,geni-se-qup"; 809 reg = <0 0x008c0000 0 0x2000>; 810 ranges; 811 clock-names = "m-ahb", "s-ahb"; 812 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 813 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 814 iommus = <&apps_smmu 0x423 0>; 815 #address-cells = <2>; 816 #size-cells = <2>; 817 status = "disabled"; 818 819 i2c8: i2c@880000 { 820 compatible = "qcom,geni-i2c"; 821 reg = <0 0x00880000 0 0x4000>; 822 clock-names = "se"; 823 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 824 pinctrl-names = "default"; 825 pinctrl-0 = <&qup_i2c8_data_clk>; 826 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 830 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 831 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 832 interconnect-names = "qup-core", "qup-config", "qup-memory"; 833 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 834 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 835 dma-names = "tx", "rx"; 836 status = "disabled"; 837 }; 838 839 spi8: spi@880000 { 840 compatible = "qcom,geni-spi"; 841 reg = <0 0x00880000 0 0x4000>; 842 clock-names = "se"; 843 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 844 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 845 pinctrl-names = "default"; 846 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 847 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 848 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 849 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 850 interconnect-names = "qup-core", "qup-config", "qup-memory"; 851 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 852 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 853 dma-names = "tx", "rx"; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 status = "disabled"; 857 }; 858 859 i2c9: i2c@884000 { 860 compatible = "qcom,geni-i2c"; 861 reg = <0 0x00884000 0 0x4000>; 862 clock-names = "se"; 863 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 864 pinctrl-names = "default"; 865 pinctrl-0 = <&qup_i2c9_data_clk>; 866 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 870 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 871 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 872 interconnect-names = "qup-core", "qup-config", "qup-memory"; 873 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 874 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 875 dma-names = "tx", "rx"; 876 status = "disabled"; 877 }; 878 879 spi9: spi@884000 { 880 compatible = "qcom,geni-spi"; 881 reg = <0 0x00884000 0 0x4000>; 882 clock-names = "se"; 883 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 884 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 885 pinctrl-names = "default"; 886 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 887 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 888 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 889 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 890 interconnect-names = "qup-core", "qup-config", "qup-memory"; 891 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 892 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 893 dma-names = "tx", "rx"; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 status = "disabled"; 897 }; 898 899 i2c10: i2c@888000 { 900 compatible = "qcom,geni-i2c"; 901 reg = <0 0x00888000 0 0x4000>; 902 clock-names = "se"; 903 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 904 pinctrl-names = "default"; 905 pinctrl-0 = <&qup_i2c10_data_clk>; 906 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 907 #address-cells = <1>; 908 #size-cells = <0>; 909 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 910 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 911 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 912 interconnect-names = "qup-core", "qup-config", "qup-memory"; 913 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 914 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 915 dma-names = "tx", "rx"; 916 status = "disabled"; 917 }; 918 919 spi10: spi@888000 { 920 compatible = "qcom,geni-spi"; 921 reg = <0 0x00888000 0 0x4000>; 922 clock-names = "se"; 923 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 924 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 925 pinctrl-names = "default"; 926 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 927 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 928 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 929 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 930 interconnect-names = "qup-core", "qup-config", "qup-memory"; 931 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 932 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 933 dma-names = "tx", "rx"; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 status = "disabled"; 937 }; 938 939 i2c11: i2c@88c000 { 940 compatible = "qcom,geni-i2c"; 941 reg = <0 0x0088c000 0 0x4000>; 942 clock-names = "se"; 943 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 944 pinctrl-names = "default"; 945 pinctrl-0 = <&qup_i2c11_data_clk>; 946 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 947 #address-cells = <1>; 948 #size-cells = <0>; 949 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 950 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 951 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 952 interconnect-names = "qup-core", "qup-config", "qup-memory"; 953 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 954 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 955 dma-names = "tx", "rx"; 956 status = "disabled"; 957 }; 958 959 spi11: spi@88c000 { 960 compatible = "qcom,geni-spi"; 961 reg = <0 0x0088c000 0 0x4000>; 962 clock-names = "se"; 963 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 964 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 967 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 968 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 969 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 970 interconnect-names = "qup-core", "qup-config", "qup-memory"; 971 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 972 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 973 dma-names = "tx", "rx"; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 status = "disabled"; 977 }; 978 979 i2c12: i2c@890000 { 980 compatible = "qcom,geni-i2c"; 981 reg = <0 0x00890000 0 0x4000>; 982 clock-names = "se"; 983 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&qup_i2c12_data_clk>; 986 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 990 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 991 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 992 interconnect-names = "qup-core", "qup-config", "qup-memory"; 993 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 994 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 995 dma-names = "tx", "rx"; 996 status = "disabled"; 997 }; 998 999 spi12: spi@890000 { 1000 compatible = "qcom,geni-spi"; 1001 reg = <0 0x00890000 0 0x4000>; 1002 clock-names = "se"; 1003 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1004 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1007 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1008 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1009 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1010 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1011 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1012 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1013 dma-names = "tx", "rx"; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 status = "disabled"; 1017 }; 1018 1019 i2c13: i2c@894000 { 1020 compatible = "qcom,geni-i2c"; 1021 reg = <0 0x00894000 0 0x4000>; 1022 clock-names = "se"; 1023 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&qup_i2c13_data_clk>; 1026 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1030 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1031 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1032 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1033 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1034 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1035 dma-names = "tx", "rx"; 1036 status = "disabled"; 1037 }; 1038 1039 spi13: spi@894000 { 1040 compatible = "qcom,geni-spi"; 1041 reg = <0 0x00894000 0 0x4000>; 1042 clock-names = "se"; 1043 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1044 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1047 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1048 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1049 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1050 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1051 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1052 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1053 dma-names = "tx", "rx"; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 status = "disabled"; 1057 }; 1058 1059 uart14: serial@898000 { 1060 compatible = "qcom,geni-uart"; 1061 reg = <0 0x898000 0 0x4000>; 1062 clock-names = "se"; 1063 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1064 pinctrl-names = "default"; 1065 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1066 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1067 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1068 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1069 interconnect-names = "qup-core", "qup-config"; 1070 status = "disabled"; 1071 }; 1072 1073 i2c15: i2c@89c000 { 1074 compatible = "qcom,geni-i2c"; 1075 reg = <0 0x0089c000 0 0x4000>; 1076 clock-names = "se"; 1077 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1078 pinctrl-names = "default"; 1079 pinctrl-0 = <&qup_i2c15_data_clk>; 1080 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1084 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1085 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1086 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1087 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1088 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1089 dma-names = "tx", "rx"; 1090 status = "disabled"; 1091 }; 1092 1093 spi15: spi@89c000 { 1094 compatible = "qcom,geni-spi"; 1095 reg = <0 0x0089c000 0 0x4000>; 1096 clock-names = "se"; 1097 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1098 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1099 pinctrl-names = "default"; 1100 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1101 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1102 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1103 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1104 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1105 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1106 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1107 dma-names = "tx", "rx"; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 }; 1113 1114 i2c_master_hub_0: geniqup@9c0000 { 1115 compatible = "qcom,geni-se-i2c-master-hub"; 1116 reg = <0x0 0x009c0000 0x0 0x2000>; 1117 clock-names = "s-ahb"; 1118 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1119 #address-cells = <2>; 1120 #size-cells = <2>; 1121 ranges; 1122 status = "disabled"; 1123 1124 i2c_hub_0: i2c@980000 { 1125 compatible = "qcom,geni-i2c-master-hub"; 1126 reg = <0x0 0x00980000 0x0 0x4000>; 1127 clock-names = "se", "core"; 1128 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1129 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1130 pinctrl-names = "default"; 1131 pinctrl-0 = <&hub_i2c0_data_clk>; 1132 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1136 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1137 interconnect-names = "qup-core", "qup-config"; 1138 status = "disabled"; 1139 }; 1140 1141 i2c_hub_1: i2c@984000 { 1142 compatible = "qcom,geni-i2c-master-hub"; 1143 reg = <0x0 0x00984000 0x0 0x4000>; 1144 clock-names = "se", "core"; 1145 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1146 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&hub_i2c1_data_clk>; 1149 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1153 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1154 interconnect-names = "qup-core", "qup-config"; 1155 status = "disabled"; 1156 }; 1157 1158 i2c_hub_2: i2c@988000 { 1159 compatible = "qcom,geni-i2c-master-hub"; 1160 reg = <0x0 0x00988000 0x0 0x4000>; 1161 clock-names = "se", "core"; 1162 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1163 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&hub_i2c2_data_clk>; 1166 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1170 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1171 interconnect-names = "qup-core", "qup-config"; 1172 status = "disabled"; 1173 }; 1174 1175 i2c_hub_3: i2c@98c000 { 1176 compatible = "qcom,geni-i2c-master-hub"; 1177 reg = <0x0 0x0098c000 0x0 0x4000>; 1178 clock-names = "se", "core"; 1179 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1180 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1181 pinctrl-names = "default"; 1182 pinctrl-0 = <&hub_i2c3_data_clk>; 1183 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1187 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1188 interconnect-names = "qup-core", "qup-config"; 1189 status = "disabled"; 1190 }; 1191 1192 i2c_hub_4: i2c@990000 { 1193 compatible = "qcom,geni-i2c-master-hub"; 1194 reg = <0x0 0x00990000 0x0 0x4000>; 1195 clock-names = "se", "core"; 1196 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1197 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&hub_i2c4_data_clk>; 1200 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1204 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1205 interconnect-names = "qup-core", "qup-config"; 1206 status = "disabled"; 1207 }; 1208 1209 i2c_hub_5: i2c@994000 { 1210 compatible = "qcom,geni-i2c-master-hub"; 1211 reg = <0 0x00994000 0 0x4000>; 1212 clock-names = "se", "core"; 1213 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1214 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1215 pinctrl-names = "default"; 1216 pinctrl-0 = <&hub_i2c5_data_clk>; 1217 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1222 interconnect-names = "qup-core", "qup-config"; 1223 status = "disabled"; 1224 }; 1225 1226 i2c_hub_6: i2c@998000 { 1227 compatible = "qcom,geni-i2c-master-hub"; 1228 reg = <0 0x00998000 0 0x4000>; 1229 clock-names = "se", "core"; 1230 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1231 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&hub_i2c6_data_clk>; 1234 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1238 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1239 interconnect-names = "qup-core", "qup-config"; 1240 status = "disabled"; 1241 }; 1242 1243 i2c_hub_7: i2c@99c000 { 1244 compatible = "qcom,geni-i2c-master-hub"; 1245 reg = <0 0x0099c000 0 0x4000>; 1246 clock-names = "se", "core"; 1247 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1248 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&hub_i2c7_data_clk>; 1251 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1255 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1256 interconnect-names = "qup-core", "qup-config"; 1257 status = "disabled"; 1258 }; 1259 1260 i2c_hub_8: i2c@9a0000 { 1261 compatible = "qcom,geni-i2c-master-hub"; 1262 reg = <0 0x009a0000 0 0x4000>; 1263 clock-names = "se", "core"; 1264 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1265 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&hub_i2c8_data_clk>; 1268 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1272 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1273 interconnect-names = "qup-core", "qup-config"; 1274 status = "disabled"; 1275 }; 1276 1277 i2c_hub_9: i2c@9a4000 { 1278 compatible = "qcom,geni-i2c-master-hub"; 1279 reg = <0 0x009a4000 0 0x4000>; 1280 clock-names = "se", "core"; 1281 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1282 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&hub_i2c9_data_clk>; 1285 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1289 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1290 interconnect-names = "qup-core", "qup-config"; 1291 status = "disabled"; 1292 }; 1293 }; 1294 1295 gpi_dma1: dma-controller@a00000 { 1296 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1297 #dma-cells = <3>; 1298 reg = <0 0x00a00000 0 0x60000>; 1299 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1311 dma-channels = <12>; 1312 dma-channel-mask = <0x1e>; 1313 iommus = <&apps_smmu 0xb6 0>; 1314 status = "disabled"; 1315 }; 1316 1317 qupv3_id_0: geniqup@ac0000 { 1318 compatible = "qcom,geni-se-qup"; 1319 reg = <0 0x00ac0000 0 0x2000>; 1320 ranges; 1321 clock-names = "m-ahb", "s-ahb"; 1322 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1323 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1324 iommus = <&apps_smmu 0xa3 0>; 1325 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1326 interconnect-names = "qup-core"; 1327 #address-cells = <2>; 1328 #size-cells = <2>; 1329 status = "disabled"; 1330 1331 i2c0: i2c@a80000 { 1332 compatible = "qcom,geni-i2c"; 1333 reg = <0 0x00a80000 0 0x4000>; 1334 clock-names = "se"; 1335 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1336 pinctrl-names = "default"; 1337 pinctrl-0 = <&qup_i2c0_data_clk>; 1338 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1342 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1343 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1344 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1345 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1346 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1347 dma-names = "tx", "rx"; 1348 status = "disabled"; 1349 }; 1350 1351 spi0: spi@a80000 { 1352 compatible = "qcom,geni-spi"; 1353 reg = <0 0x00a80000 0 0x4000>; 1354 clock-names = "se"; 1355 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1356 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1357 pinctrl-names = "default"; 1358 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1359 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1360 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1361 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1362 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1363 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1364 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1365 dma-names = "tx", "rx"; 1366 #address-cells = <1>; 1367 #size-cells = <0>; 1368 status = "disabled"; 1369 }; 1370 1371 i2c1: i2c@a84000 { 1372 compatible = "qcom,geni-i2c"; 1373 reg = <0 0x00a84000 0 0x4000>; 1374 clock-names = "se"; 1375 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1376 pinctrl-names = "default"; 1377 pinctrl-0 = <&qup_i2c1_data_clk>; 1378 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1379 #address-cells = <1>; 1380 #size-cells = <0>; 1381 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1382 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1383 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1384 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1385 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1386 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1387 dma-names = "tx", "rx"; 1388 status = "disabled"; 1389 }; 1390 1391 spi1: spi@a84000 { 1392 compatible = "qcom,geni-spi"; 1393 reg = <0 0x00a84000 0 0x4000>; 1394 clock-names = "se"; 1395 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1396 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1397 pinctrl-names = "default"; 1398 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1399 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1400 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1401 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1402 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1403 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1404 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1405 dma-names = "tx", "rx"; 1406 #address-cells = <1>; 1407 #size-cells = <0>; 1408 status = "disabled"; 1409 }; 1410 1411 i2c2: i2c@a88000 { 1412 compatible = "qcom,geni-i2c"; 1413 reg = <0 0x00a88000 0 0x4000>; 1414 clock-names = "se"; 1415 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1416 pinctrl-names = "default"; 1417 pinctrl-0 = <&qup_i2c2_data_clk>; 1418 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1422 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1423 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1424 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1425 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1426 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1427 dma-names = "tx", "rx"; 1428 status = "disabled"; 1429 }; 1430 1431 spi2: spi@a88000 { 1432 compatible = "qcom,geni-spi"; 1433 reg = <0 0x00a88000 0 0x4000>; 1434 clock-names = "se"; 1435 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1436 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1439 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1440 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1441 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1442 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1443 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1444 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1445 dma-names = "tx", "rx"; 1446 #address-cells = <1>; 1447 #size-cells = <0>; 1448 status = "disabled"; 1449 }; 1450 1451 i2c3: i2c@a8c000 { 1452 compatible = "qcom,geni-i2c"; 1453 reg = <0 0x00a8c000 0 0x4000>; 1454 clock-names = "se"; 1455 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1456 pinctrl-names = "default"; 1457 pinctrl-0 = <&qup_i2c3_data_clk>; 1458 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1462 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1463 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1464 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1465 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1466 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1467 dma-names = "tx", "rx"; 1468 status = "disabled"; 1469 }; 1470 1471 spi3: spi@a8c000 { 1472 compatible = "qcom,geni-spi"; 1473 reg = <0 0x00a8c000 0 0x4000>; 1474 clock-names = "se"; 1475 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1476 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1477 pinctrl-names = "default"; 1478 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1479 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1480 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1481 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1482 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1483 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1484 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1485 dma-names = "tx", "rx"; 1486 #address-cells = <1>; 1487 #size-cells = <0>; 1488 status = "disabled"; 1489 }; 1490 1491 i2c4: i2c@a90000 { 1492 compatible = "qcom,geni-i2c"; 1493 reg = <0 0x00a90000 0 0x4000>; 1494 clock-names = "se"; 1495 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1496 pinctrl-names = "default"; 1497 pinctrl-0 = <&qup_i2c4_data_clk>; 1498 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1499 #address-cells = <1>; 1500 #size-cells = <0>; 1501 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1502 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1503 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1504 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1505 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1506 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1507 dma-names = "tx", "rx"; 1508 status = "disabled"; 1509 }; 1510 1511 spi4: spi@a90000 { 1512 compatible = "qcom,geni-spi"; 1513 reg = <0 0x00a90000 0 0x4000>; 1514 clock-names = "se"; 1515 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1516 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1517 pinctrl-names = "default"; 1518 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1519 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1520 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1521 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1522 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1523 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1524 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1525 dma-names = "tx", "rx"; 1526 #address-cells = <1>; 1527 #size-cells = <0>; 1528 status = "disabled"; 1529 }; 1530 1531 i2c5: i2c@a94000 { 1532 compatible = "qcom,geni-i2c"; 1533 reg = <0 0x00a94000 0 0x4000>; 1534 clock-names = "se"; 1535 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1536 pinctrl-names = "default"; 1537 pinctrl-0 = <&qup_i2c5_data_clk>; 1538 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1539 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1540 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1541 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1542 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1543 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1544 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1545 dma-names = "tx", "rx"; 1546 #address-cells = <1>; 1547 #size-cells = <0>; 1548 status = "disabled"; 1549 }; 1550 1551 spi5: spi@a94000 { 1552 compatible = "qcom,geni-spi"; 1553 reg = <0 0x00a94000 0 0x4000>; 1554 clock-names = "se"; 1555 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1556 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1557 pinctrl-names = "default"; 1558 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1559 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1560 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1561 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1562 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1563 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1564 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1565 dma-names = "tx", "rx"; 1566 #address-cells = <1>; 1567 #size-cells = <0>; 1568 status = "disabled"; 1569 }; 1570 1571 i2c6: i2c@a98000 { 1572 compatible = "qcom,geni-i2c"; 1573 reg = <0 0x00a98000 0 0x4000>; 1574 clock-names = "se"; 1575 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1576 pinctrl-names = "default"; 1577 pinctrl-0 = <&qup_i2c6_data_clk>; 1578 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1579 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1580 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1581 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1582 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1583 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1584 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1585 dma-names = "tx", "rx"; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 status = "disabled"; 1589 }; 1590 1591 spi6: spi@a98000 { 1592 compatible = "qcom,geni-spi"; 1593 reg = <0 0x00a98000 0 0x4000>; 1594 clock-names = "se"; 1595 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1596 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1597 pinctrl-names = "default"; 1598 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1599 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1600 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1601 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1602 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1603 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1604 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1605 dma-names = "tx", "rx"; 1606 #address-cells = <1>; 1607 #size-cells = <0>; 1608 status = "disabled"; 1609 }; 1610 1611 uart7: serial@a9c000 { 1612 compatible = "qcom,geni-debug-uart"; 1613 reg = <0 0x00a9c000 0 0x4000>; 1614 clock-names = "se"; 1615 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1616 pinctrl-names = "default"; 1617 pinctrl-0 = <&qup_uart7_default>; 1618 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1619 interconnect-names = "qup-core", "qup-config"; 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1621 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1622 status = "disabled"; 1623 }; 1624 }; 1625 1626 cnoc_main: interconnect@1500000 { 1627 compatible = "qcom,sm8550-cnoc-main"; 1628 reg = <0 0x01500000 0 0x13080>; 1629 #interconnect-cells = <2>; 1630 qcom,bcm-voters = <&apps_bcm_voter>; 1631 }; 1632 1633 config_noc: interconnect@1600000 { 1634 compatible = "qcom,sm8550-config-noc"; 1635 reg = <0 0x01600000 0 0x6200>; 1636 #interconnect-cells = <2>; 1637 qcom,bcm-voters = <&apps_bcm_voter>; 1638 }; 1639 1640 system_noc: interconnect@1680000 { 1641 compatible = "qcom,sm8550-system-noc"; 1642 reg = <0 0x01680000 0 0x1d080>; 1643 #interconnect-cells = <2>; 1644 qcom,bcm-voters = <&apps_bcm_voter>; 1645 }; 1646 1647 pcie_noc: interconnect@16c0000 { 1648 compatible = "qcom,sm8550-pcie-anoc"; 1649 reg = <0 0x016c0000 0 0x12200>; 1650 #interconnect-cells = <2>; 1651 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1652 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1653 qcom,bcm-voters = <&apps_bcm_voter>; 1654 }; 1655 1656 aggre1_noc: interconnect@16e0000 { 1657 compatible = "qcom,sm8550-aggre1-noc"; 1658 reg = <0 0x016e0000 0 0x14400>; 1659 #interconnect-cells = <2>; 1660 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1661 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1662 qcom,bcm-voters = <&apps_bcm_voter>; 1663 }; 1664 1665 aggre2_noc: interconnect@1700000 { 1666 compatible = "qcom,sm8550-aggre2-noc"; 1667 reg = <0 0x01700000 0 0x1e400>; 1668 #interconnect-cells = <2>; 1669 clocks = <&rpmhcc RPMH_IPA_CLK>; 1670 qcom,bcm-voters = <&apps_bcm_voter>; 1671 }; 1672 1673 mmss_noc: interconnect@1780000 { 1674 compatible = "qcom,sm8550-mmss-noc"; 1675 reg = <0 0x01780000 0 0x5b800>; 1676 #interconnect-cells = <2>; 1677 qcom,bcm-voters = <&apps_bcm_voter>; 1678 }; 1679 1680 pcie0: pci@1c00000 { 1681 device_type = "pci"; 1682 compatible = "qcom,pcie-sm8550"; 1683 reg = <0 0x01c00000 0 0x3000>, 1684 <0 0x60000000 0 0xf1d>, 1685 <0 0x60000f20 0 0xa8>, 1686 <0 0x60001000 0 0x1000>, 1687 <0 0x60100000 0 0x100000>; 1688 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1689 #address-cells = <3>; 1690 #size-cells = <2>; 1691 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1692 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1693 bus-range = <0x00 0xff>; 1694 1695 dma-coherent; 1696 1697 linux,pci-domain = <0>; 1698 num-lanes = <2>; 1699 1700 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1701 interrupt-names = "msi"; 1702 1703 #interrupt-cells = <1>; 1704 interrupt-map-mask = <0 0 0 0x7>; 1705 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1706 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1707 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1708 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1709 1710 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1711 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1712 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1713 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1714 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1715 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1716 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1717 clock-names = "aux", 1718 "cfg", 1719 "bus_master", 1720 "bus_slave", 1721 "slave_q2a", 1722 "ddrss_sf_tbu", 1723 "noc_aggr"; 1724 1725 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 1726 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; 1727 interconnect-names = "pcie-mem", "cpu-pcie"; 1728 1729 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 1730 <0x100 &apps_smmu 0x1401 0x1>; 1731 1732 resets = <&gcc GCC_PCIE_0_BCR>; 1733 reset-names = "pci"; 1734 1735 power-domains = <&gcc PCIE_0_GDSC>; 1736 1737 phys = <&pcie0_phy>; 1738 phy-names = "pciephy"; 1739 1740 status = "disabled"; 1741 }; 1742 1743 pcie0_phy: phy@1c06000 { 1744 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 1745 reg = <0 0x01c06000 0 0x2000>; 1746 1747 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1748 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1749 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1750 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1751 <&gcc GCC_PCIE_0_PIPE_CLK>; 1752 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1753 "pipe"; 1754 1755 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1756 reset-names = "phy"; 1757 1758 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1759 assigned-clock-rates = <100000000>; 1760 1761 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1762 1763 #clock-cells = <0>; 1764 clock-output-names = "pcie0_pipe_clk"; 1765 1766 #phy-cells = <0>; 1767 1768 status = "disabled"; 1769 }; 1770 1771 pcie1: pci@1c08000 { 1772 device_type = "pci"; 1773 compatible = "qcom,pcie-sm8550"; 1774 reg = <0x0 0x01c08000 0x0 0x3000>, 1775 <0x0 0x40000000 0x0 0xf1d>, 1776 <0x0 0x40000f20 0x0 0xa8>, 1777 <0x0 0x40001000 0x0 0x1000>, 1778 <0x0 0x40100000 0x0 0x100000>; 1779 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1780 #address-cells = <3>; 1781 #size-cells = <2>; 1782 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1783 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1784 bus-range = <0x00 0xff>; 1785 1786 dma-coherent; 1787 1788 linux,pci-domain = <1>; 1789 num-lanes = <2>; 1790 1791 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1792 interrupt-names = "msi"; 1793 1794 #interrupt-cells = <1>; 1795 interrupt-map-mask = <0 0 0 0x7>; 1796 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1797 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1798 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1799 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1800 1801 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1802 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1803 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1804 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1805 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1806 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1807 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1808 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 1809 clock-names = "aux", 1810 "cfg", 1811 "bus_master", 1812 "bus_slave", 1813 "slave_q2a", 1814 "ddrss_sf_tbu", 1815 "noc_aggr", 1816 "cnoc_sf_axi"; 1817 1818 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1819 assigned-clock-rates = <19200000>; 1820 1821 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 1822 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; 1823 interconnect-names = "pcie-mem", "cpu-pcie"; 1824 1825 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 1826 <0x100 &apps_smmu 0x1481 0x1>; 1827 1828 resets = <&gcc GCC_PCIE_1_BCR>, 1829 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1830 reset-names = "pci", "link_down"; 1831 1832 power-domains = <&gcc PCIE_1_GDSC>; 1833 1834 phys = <&pcie1_phy>; 1835 phy-names = "pciephy"; 1836 1837 status = "disabled"; 1838 }; 1839 1840 pcie1_phy: phy@1c0e000 { 1841 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 1842 reg = <0x0 0x01c0e000 0x0 0x2000>; 1843 1844 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1845 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1846 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1847 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1848 <&gcc GCC_PCIE_1_PIPE_CLK>; 1849 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1850 "pipe"; 1851 1852 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 1853 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 1854 reset-names = "phy", "phy_nocsr"; 1855 1856 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1857 assigned-clock-rates = <100000000>; 1858 1859 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1860 1861 #clock-cells = <0>; 1862 clock-output-names = "pcie1_pipe_clk"; 1863 1864 #phy-cells = <0>; 1865 1866 status = "disabled"; 1867 }; 1868 1869 cryptobam: dma-controller@1dc4000 { 1870 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1871 reg = <0x0 0x01dc4000 0x0 0x28000>; 1872 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1873 #dma-cells = <1>; 1874 qcom,ee = <0>; 1875 qcom,controlled-remotely; 1876 iommus = <&apps_smmu 0x480 0x0>, 1877 <&apps_smmu 0x481 0x0>; 1878 }; 1879 1880 crypto: crypto@1dfa000 { 1881 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 1882 reg = <0x0 0x01dfa000 0x0 0x6000>; 1883 dmas = <&cryptobam 4>, <&cryptobam 5>; 1884 dma-names = "rx", "tx"; 1885 iommus = <&apps_smmu 0x480 0x0>, 1886 <&apps_smmu 0x481 0x0>; 1887 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1888 interconnect-names = "memory"; 1889 }; 1890 1891 ufs_mem_phy: phy@1d80000 { 1892 compatible = "qcom,sm8550-qmp-ufs-phy"; 1893 reg = <0x0 0x01d80000 0x0 0x2000>; 1894 clocks = <&tcsr TCSR_UFS_CLKREF_EN>, 1895 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1896 clock-names = "ref", "ref_aux"; 1897 1898 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1899 1900 resets = <&ufs_mem_hc 0>; 1901 reset-names = "ufsphy"; 1902 1903 #clock-cells = <1>; 1904 #phy-cells = <0>; 1905 1906 status = "disabled"; 1907 }; 1908 1909 ufs_mem_hc: ufs@1d84000 { 1910 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 1911 "jedec,ufs-2.0"; 1912 reg = <0x0 0x01d84000 0x0 0x3000>; 1913 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1914 phys = <&ufs_mem_phy>; 1915 phy-names = "ufsphy"; 1916 lanes-per-direction = <2>; 1917 #reset-cells = <1>; 1918 resets = <&gcc GCC_UFS_PHY_BCR>; 1919 reset-names = "rst"; 1920 1921 power-domains = <&gcc UFS_PHY_GDSC>; 1922 required-opps = <&rpmhpd_opp_nom>; 1923 1924 iommus = <&apps_smmu 0x60 0x0>; 1925 dma-coherent; 1926 1927 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 1928 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 1929 1930 interconnect-names = "ufs-ddr", "cpu-ufs"; 1931 clock-names = "core_clk", 1932 "bus_aggr_clk", 1933 "iface_clk", 1934 "core_clk_unipro", 1935 "ref_clk", 1936 "tx_lane0_sync_clk", 1937 "rx_lane0_sync_clk", 1938 "rx_lane1_sync_clk"; 1939 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1940 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1941 <&gcc GCC_UFS_PHY_AHB_CLK>, 1942 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1943 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 1944 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1945 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1946 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1947 freq-table-hz = 1948 <75000000 300000000>, 1949 <0 0>, 1950 <0 0>, 1951 <75000000 300000000>, 1952 <100000000 403000000>, 1953 <0 0>, 1954 <0 0>, 1955 <0 0>; 1956 qcom,ice = <&ice>; 1957 1958 status = "disabled"; 1959 }; 1960 1961 ice: crypto@1d88000 { 1962 compatible = "qcom,sm8550-inline-crypto-engine", 1963 "qcom,inline-crypto-engine"; 1964 reg = <0 0x01d88000 0 0x8000>; 1965 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1966 }; 1967 1968 tcsr_mutex: hwlock@1f40000 { 1969 compatible = "qcom,tcsr-mutex"; 1970 reg = <0 0x01f40000 0 0x20000>; 1971 #hwlock-cells = <1>; 1972 }; 1973 1974 tcsr: clock-controller@1fc0000 { 1975 compatible = "qcom,sm8550-tcsr", "syscon"; 1976 reg = <0 0x01fc0000 0 0x30000>; 1977 clocks = <&rpmhcc RPMH_CXO_CLK>; 1978 #clock-cells = <1>; 1979 #reset-cells = <1>; 1980 }; 1981 1982 gpucc: clock-controller@3d90000 { 1983 compatible = "qcom,sm8550-gpucc"; 1984 reg = <0 0x03d90000 0 0xa000>; 1985 clocks = <&bi_tcxo_div2>, 1986 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1987 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1988 #clock-cells = <1>; 1989 #reset-cells = <1>; 1990 #power-domain-cells = <1>; 1991 }; 1992 1993 remoteproc_mpss: remoteproc@4080000 { 1994 compatible = "qcom,sm8550-mpss-pas"; 1995 reg = <0x0 0x04080000 0x0 0x4040>; 1996 1997 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1998 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1999 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2000 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2001 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2002 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2003 interrupt-names = "wdog", "fatal", "ready", "handover", 2004 "stop-ack", "shutdown-ack"; 2005 2006 clocks = <&rpmhcc RPMH_CXO_CLK>; 2007 clock-names = "xo"; 2008 2009 power-domains = <&rpmhpd RPMHPD_CX>, 2010 <&rpmhpd RPMHPD_MSS>; 2011 power-domain-names = "cx", "mss"; 2012 2013 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2014 2015 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 2016 2017 qcom,qmp = <&aoss_qmp>; 2018 2019 qcom,smem-states = <&smp2p_modem_out 0>; 2020 qcom,smem-state-names = "stop"; 2021 2022 status = "disabled"; 2023 2024 glink-edge { 2025 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2026 IPCC_MPROC_SIGNAL_GLINK_QMP 2027 IRQ_TYPE_EDGE_RISING>; 2028 mboxes = <&ipcc IPCC_CLIENT_MPSS 2029 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2030 label = "mpss"; 2031 qcom,remote-pid = <1>; 2032 }; 2033 }; 2034 2035 lpass_wsa2macro: codec@6aa0000 { 2036 compatible = "qcom,sm8550-lpass-wsa-macro"; 2037 reg = <0 0x06aa0000 0 0x1000>; 2038 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2039 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2040 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2041 <&lpass_vamacro>; 2042 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2043 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2044 assigned-clock-rates = <19200000>; 2045 2046 #clock-cells = <0>; 2047 clock-output-names = "wsa2-mclk"; 2048 pinctrl-names = "default"; 2049 pinctrl-0 = <&wsa2_swr_active>; 2050 #sound-dai-cells = <1>; 2051 }; 2052 2053 swr3: soundwire-controller@6ab0000 { 2054 compatible = "qcom,soundwire-v2.0.0"; 2055 reg = <0 0x06ab0000 0 0x10000>; 2056 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2057 clocks = <&lpass_wsa2macro>; 2058 clock-names = "iface"; 2059 label = "WSA2"; 2060 2061 qcom,din-ports = <4>; 2062 qcom,dout-ports = <9>; 2063 2064 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2065 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2066 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2067 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2068 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2069 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2070 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2071 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2072 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2073 2074 #address-cells = <2>; 2075 #size-cells = <0>; 2076 #sound-dai-cells = <1>; 2077 status = "disabled"; 2078 }; 2079 2080 lpass_rxmacro: codec@6ac0000 { 2081 compatible = "qcom,sm8550-lpass-rx-macro"; 2082 reg = <0 0x06ac0000 0 0x1000>; 2083 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2084 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2085 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2086 <&lpass_vamacro>; 2087 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2088 2089 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2090 assigned-clock-rates = <19200000>; 2091 2092 #clock-cells = <0>; 2093 clock-output-names = "mclk"; 2094 pinctrl-names = "default"; 2095 pinctrl-0 = <&rx_swr_active>; 2096 #sound-dai-cells = <1>; 2097 }; 2098 2099 swr1: soundwire-controller@6ad0000 { 2100 compatible = "qcom,soundwire-v2.0.0"; 2101 reg = <0 0x06ad0000 0 0x10000>; 2102 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2103 clocks = <&lpass_rxmacro>; 2104 clock-names = "iface"; 2105 label = "RX"; 2106 2107 qcom,din-ports = <0>; 2108 qcom,dout-ports = <10>; 2109 2110 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>; 2111 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>; 2112 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; 2113 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; 2114 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; 2115 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>; 2116 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; 2117 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2118 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; 2119 2120 #address-cells = <2>; 2121 #size-cells = <0>; 2122 #sound-dai-cells = <1>; 2123 status = "disabled"; 2124 }; 2125 2126 lpass_txmacro: codec@6ae0000 { 2127 compatible = "qcom,sm8550-lpass-tx-macro"; 2128 reg = <0 0x06ae0000 0 0x1000>; 2129 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2130 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2131 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2132 <&lpass_vamacro>; 2133 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2134 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2135 2136 assigned-clock-rates = <19200000>; 2137 2138 #clock-cells = <0>; 2139 clock-output-names = "mclk"; 2140 pinctrl-names = "default"; 2141 pinctrl-0 = <&tx_swr_active>; 2142 #sound-dai-cells = <1>; 2143 }; 2144 2145 lpass_wsamacro: codec@6b00000 { 2146 compatible = "qcom,sm8550-lpass-wsa-macro"; 2147 reg = <0 0x06b00000 0 0x1000>; 2148 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2149 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2150 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2151 <&lpass_vamacro>; 2152 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2153 2154 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2155 assigned-clock-rates = <19200000>; 2156 2157 #clock-cells = <0>; 2158 clock-output-names = "mclk"; 2159 pinctrl-names = "default"; 2160 pinctrl-0 = <&wsa_swr_active>; 2161 #sound-dai-cells = <1>; 2162 }; 2163 2164 swr0: soundwire-controller@6b10000 { 2165 compatible = "qcom,soundwire-v2.0.0"; 2166 reg = <0 0x06b10000 0 0x10000>; 2167 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2168 clocks = <&lpass_wsamacro>; 2169 clock-names = "iface"; 2170 label = "WSA"; 2171 2172 qcom,din-ports = <4>; 2173 qcom,dout-ports = <9>; 2174 2175 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2176 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2177 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2178 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2179 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2180 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2181 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2182 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2183 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2184 2185 #address-cells = <2>; 2186 #size-cells = <0>; 2187 #sound-dai-cells = <1>; 2188 status = "disabled"; 2189 }; 2190 2191 swr2: soundwire-controller@6d30000 { 2192 compatible = "qcom,soundwire-v2.0.0"; 2193 reg = <0 0x06d30000 0 0x10000>; 2194 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2195 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2196 interrupt-names = "core", "wakeup"; 2197 clocks = <&lpass_vamacro>; 2198 clock-names = "iface"; 2199 label = "TX"; 2200 2201 qcom,din-ports = <4>; 2202 qcom,dout-ports = <0>; 2203 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2204 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2205 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2206 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2207 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2208 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2209 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2210 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2211 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2212 2213 #address-cells = <2>; 2214 #size-cells = <0>; 2215 #sound-dai-cells = <1>; 2216 status = "disabled"; 2217 }; 2218 2219 lpass_vamacro: codec@6d44000 { 2220 compatible = "qcom,sm8550-lpass-va-macro"; 2221 reg = <0 0x06d44000 0 0x1000>; 2222 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2223 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2224 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2225 clock-names = "mclk", "macro", "dcodec"; 2226 2227 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2228 assigned-clock-rates = <19200000>; 2229 2230 #clock-cells = <0>; 2231 clock-output-names = "fsgen"; 2232 #sound-dai-cells = <1>; 2233 }; 2234 2235 lpass_tlmm: pinctrl@6e80000 { 2236 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 2237 reg = <0 0x06e80000 0 0x20000>, 2238 <0 0x07250000 0 0x10000>; 2239 gpio-controller; 2240 #gpio-cells = <2>; 2241 gpio-ranges = <&lpass_tlmm 0 0 23>; 2242 2243 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2244 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2245 clock-names = "core", "audio"; 2246 2247 tx_swr_active: tx-swr-active-state { 2248 clk-pins { 2249 pins = "gpio0"; 2250 function = "swr_tx_clk"; 2251 drive-strength = <2>; 2252 slew-rate = <1>; 2253 bias-disable; 2254 }; 2255 2256 data-pins { 2257 pins = "gpio1", "gpio2", "gpio14"; 2258 function = "swr_tx_data"; 2259 drive-strength = <2>; 2260 slew-rate = <1>; 2261 bias-bus-hold; 2262 }; 2263 }; 2264 2265 rx_swr_active: rx-swr-active-state { 2266 clk-pins { 2267 pins = "gpio3"; 2268 function = "swr_rx_clk"; 2269 drive-strength = <2>; 2270 slew-rate = <1>; 2271 bias-disable; 2272 }; 2273 2274 data-pins { 2275 pins = "gpio4", "gpio5"; 2276 function = "swr_rx_data"; 2277 drive-strength = <2>; 2278 slew-rate = <1>; 2279 bias-bus-hold; 2280 }; 2281 }; 2282 2283 dmic01_default: dmic01-default-state { 2284 clk-pins { 2285 pins = "gpio6"; 2286 function = "dmic1_clk"; 2287 drive-strength = <8>; 2288 output-high; 2289 }; 2290 2291 data-pins { 2292 pins = "gpio7"; 2293 function = "dmic1_data"; 2294 drive-strength = <8>; 2295 input-enable; 2296 }; 2297 }; 2298 2299 dmic02_default: dmic02-default-state { 2300 clk-pins { 2301 pins = "gpio8"; 2302 function = "dmic2_clk"; 2303 drive-strength = <8>; 2304 output-high; 2305 }; 2306 2307 data-pins { 2308 pins = "gpio9"; 2309 function = "dmic2_data"; 2310 drive-strength = <8>; 2311 input-enable; 2312 }; 2313 }; 2314 2315 wsa_swr_active: wsa-swr-active-state { 2316 clk-pins { 2317 pins = "gpio10"; 2318 function = "wsa_swr_clk"; 2319 drive-strength = <2>; 2320 slew-rate = <1>; 2321 bias-disable; 2322 }; 2323 2324 data-pins { 2325 pins = "gpio11"; 2326 function = "wsa_swr_data"; 2327 drive-strength = <2>; 2328 slew-rate = <1>; 2329 bias-bus-hold; 2330 }; 2331 }; 2332 2333 wsa2_swr_active: wsa2-swr-active-state { 2334 clk-pins { 2335 pins = "gpio15"; 2336 function = "wsa2_swr_clk"; 2337 drive-strength = <2>; 2338 slew-rate = <1>; 2339 bias-disable; 2340 }; 2341 2342 data-pins { 2343 pins = "gpio16"; 2344 function = "wsa2_swr_data"; 2345 drive-strength = <2>; 2346 slew-rate = <1>; 2347 bias-bus-hold; 2348 }; 2349 }; 2350 }; 2351 2352 lpass_lpiaon_noc: interconnect@7400000 { 2353 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 2354 reg = <0 0x07400000 0 0x19080>; 2355 #interconnect-cells = <2>; 2356 qcom,bcm-voters = <&apps_bcm_voter>; 2357 }; 2358 2359 lpass_lpicx_noc: interconnect@7430000 { 2360 compatible = "qcom,sm8550-lpass-lpicx-noc"; 2361 reg = <0 0x07430000 0 0x3a200>; 2362 #interconnect-cells = <2>; 2363 qcom,bcm-voters = <&apps_bcm_voter>; 2364 }; 2365 2366 lpass_ag_noc: interconnect@7e40000 { 2367 compatible = "qcom,sm8550-lpass-ag-noc"; 2368 reg = <0 0x07e40000 0 0xe080>; 2369 #interconnect-cells = <2>; 2370 qcom,bcm-voters = <&apps_bcm_voter>; 2371 }; 2372 2373 sdhc_2: mmc@8804000 { 2374 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 2375 reg = <0 0x08804000 0 0x1000>; 2376 2377 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2378 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2379 interrupt-names = "hc_irq", "pwr_irq"; 2380 2381 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2382 <&gcc GCC_SDCC2_APPS_CLK>, 2383 <&rpmhcc RPMH_CXO_CLK>; 2384 clock-names = "iface", "core", "xo"; 2385 iommus = <&apps_smmu 0x540 0>; 2386 qcom,dll-config = <0x0007642c>; 2387 qcom,ddr-config = <0x80040868>; 2388 power-domains = <&rpmhpd RPMHPD_CX>; 2389 operating-points-v2 = <&sdhc2_opp_table>; 2390 2391 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2392 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2393 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 2394 bus-width = <4>; 2395 dma-coherent; 2396 2397 /* Forbid SDR104/SDR50 - broken hw! */ 2398 sdhci-caps-mask = <0x3 0>; 2399 2400 status = "disabled"; 2401 2402 sdhc2_opp_table: opp-table { 2403 compatible = "operating-points-v2"; 2404 2405 opp-19200000 { 2406 opp-hz = /bits/ 64 <19200000>; 2407 required-opps = <&rpmhpd_opp_min_svs>; 2408 }; 2409 2410 opp-50000000 { 2411 opp-hz = /bits/ 64 <50000000>; 2412 required-opps = <&rpmhpd_opp_low_svs>; 2413 }; 2414 2415 opp-100000000 { 2416 opp-hz = /bits/ 64 <100000000>; 2417 required-opps = <&rpmhpd_opp_svs>; 2418 }; 2419 2420 opp-202000000 { 2421 opp-hz = /bits/ 64 <202000000>; 2422 required-opps = <&rpmhpd_opp_svs_l1>; 2423 }; 2424 }; 2425 }; 2426 2427 videocc: clock-controller@aaf0000 { 2428 compatible = "qcom,sm8550-videocc"; 2429 reg = <0 0x0aaf0000 0 0x10000>; 2430 clocks = <&bi_tcxo_div2>, 2431 <&gcc GCC_VIDEO_AHB_CLK>; 2432 power-domains = <&rpmhpd RPMHPD_MMCX>; 2433 required-opps = <&rpmhpd_opp_low_svs>; 2434 #clock-cells = <1>; 2435 #reset-cells = <1>; 2436 #power-domain-cells = <1>; 2437 }; 2438 2439 camcc: clock-controller@ade0000 { 2440 compatible = "qcom,sm8550-camcc"; 2441 reg = <0 0x0ade0000 0 0x20000>; 2442 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2443 <&bi_tcxo_div2>, 2444 <&bi_tcxo_ao_div2>, 2445 <&sleep_clk>; 2446 power-domains = <&rpmhpd SM8550_MMCX>; 2447 required-opps = <&rpmhpd_opp_low_svs>; 2448 #clock-cells = <1>; 2449 #reset-cells = <1>; 2450 #power-domain-cells = <1>; 2451 }; 2452 2453 mdss: display-subsystem@ae00000 { 2454 compatible = "qcom,sm8550-mdss"; 2455 reg = <0 0x0ae00000 0 0x1000>; 2456 reg-names = "mdss"; 2457 2458 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2459 interrupt-controller; 2460 #interrupt-cells = <1>; 2461 2462 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2463 <&gcc GCC_DISP_AHB_CLK>, 2464 <&gcc GCC_DISP_HF_AXI_CLK>, 2465 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2466 2467 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2468 2469 power-domains = <&dispcc MDSS_GDSC>; 2470 2471 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, 2472 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2473 interconnect-names = "mdp0-mem", "mdp1-mem"; 2474 2475 iommus = <&apps_smmu 0x1c00 0x2>; 2476 2477 #address-cells = <2>; 2478 #size-cells = <2>; 2479 ranges; 2480 2481 status = "disabled"; 2482 2483 mdss_mdp: display-controller@ae01000 { 2484 compatible = "qcom,sm8550-dpu"; 2485 reg = <0 0x0ae01000 0 0x8f000>, 2486 <0 0x0aeb0000 0 0x2008>; 2487 reg-names = "mdp", "vbif"; 2488 2489 interrupt-parent = <&mdss>; 2490 interrupts = <0>; 2491 2492 clocks = <&gcc GCC_DISP_AHB_CLK>, 2493 <&gcc GCC_DISP_HF_AXI_CLK>, 2494 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2495 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2496 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2497 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2498 clock-names = "bus", 2499 "nrt_bus", 2500 "iface", 2501 "lut", 2502 "core", 2503 "vsync"; 2504 2505 power-domains = <&rpmhpd RPMHPD_MMCX>; 2506 2507 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2508 assigned-clock-rates = <19200000>; 2509 2510 operating-points-v2 = <&mdp_opp_table>; 2511 2512 ports { 2513 #address-cells = <1>; 2514 #size-cells = <0>; 2515 2516 port@0 { 2517 reg = <0>; 2518 dpu_intf1_out: endpoint { 2519 remote-endpoint = <&mdss_dsi0_in>; 2520 }; 2521 }; 2522 2523 port@1 { 2524 reg = <1>; 2525 dpu_intf2_out: endpoint { 2526 remote-endpoint = <&mdss_dsi1_in>; 2527 }; 2528 }; 2529 2530 port@2 { 2531 reg = <2>; 2532 dpu_intf0_out: endpoint { 2533 remote-endpoint = <&mdss_dp0_in>; 2534 }; 2535 }; 2536 }; 2537 2538 mdp_opp_table: opp-table { 2539 compatible = "operating-points-v2"; 2540 2541 opp-200000000 { 2542 opp-hz = /bits/ 64 <200000000>; 2543 required-opps = <&rpmhpd_opp_low_svs>; 2544 }; 2545 2546 opp-325000000 { 2547 opp-hz = /bits/ 64 <325000000>; 2548 required-opps = <&rpmhpd_opp_svs>; 2549 }; 2550 2551 opp-375000000 { 2552 opp-hz = /bits/ 64 <375000000>; 2553 required-opps = <&rpmhpd_opp_svs_l1>; 2554 }; 2555 2556 opp-514000000 { 2557 opp-hz = /bits/ 64 <514000000>; 2558 required-opps = <&rpmhpd_opp_nom>; 2559 }; 2560 }; 2561 }; 2562 2563 mdss_dp0: displayport-controller@ae90000 { 2564 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 2565 reg = <0 0xae90000 0 0x200>, 2566 <0 0xae90200 0 0x200>, 2567 <0 0xae90400 0 0xc00>, 2568 <0 0xae91000 0 0x400>, 2569 <0 0xae91400 0 0x400>; 2570 interrupt-parent = <&mdss>; 2571 interrupts = <12>; 2572 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2573 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2574 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2575 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2576 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2577 clock-names = "core_iface", 2578 "core_aux", 2579 "ctrl_link", 2580 "ctrl_link_iface", 2581 "stream_pixel"; 2582 2583 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2584 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2585 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2586 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2587 2588 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 2589 phy-names = "dp"; 2590 2591 #sound-dai-cells = <0>; 2592 2593 operating-points-v2 = <&dp_opp_table>; 2594 power-domains = <&rpmhpd RPMHPD_MMCX>; 2595 2596 status = "disabled"; 2597 2598 ports { 2599 #address-cells = <1>; 2600 #size-cells = <0>; 2601 2602 port@0 { 2603 reg = <0>; 2604 mdss_dp0_in: endpoint { 2605 remote-endpoint = <&dpu_intf0_out>; 2606 }; 2607 }; 2608 2609 port@1 { 2610 reg = <1>; 2611 mdss_dp0_out: endpoint { 2612 }; 2613 }; 2614 }; 2615 2616 dp_opp_table: opp-table { 2617 compatible = "operating-points-v2"; 2618 2619 opp-162000000 { 2620 opp-hz = /bits/ 64 <162000000>; 2621 required-opps = <&rpmhpd_opp_low_svs_d1>; 2622 }; 2623 2624 opp-270000000 { 2625 opp-hz = /bits/ 64 <270000000>; 2626 required-opps = <&rpmhpd_opp_low_svs>; 2627 }; 2628 2629 opp-540000000 { 2630 opp-hz = /bits/ 64 <540000000>; 2631 required-opps = <&rpmhpd_opp_svs_l1>; 2632 }; 2633 2634 opp-810000000 { 2635 opp-hz = /bits/ 64 <810000000>; 2636 required-opps = <&rpmhpd_opp_nom>; 2637 }; 2638 }; 2639 }; 2640 2641 mdss_dsi0: dsi@ae94000 { 2642 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2643 reg = <0 0x0ae94000 0 0x400>; 2644 reg-names = "dsi_ctrl"; 2645 2646 interrupt-parent = <&mdss>; 2647 interrupts = <4>; 2648 2649 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2650 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2651 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2652 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2653 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2654 <&gcc GCC_DISP_HF_AXI_CLK>; 2655 clock-names = "byte", 2656 "byte_intf", 2657 "pixel", 2658 "core", 2659 "iface", 2660 "bus"; 2661 2662 power-domains = <&rpmhpd RPMHPD_MMCX>; 2663 2664 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2665 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2666 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2667 <&mdss_dsi0_phy 1>; 2668 2669 operating-points-v2 = <&mdss_dsi_opp_table>; 2670 2671 phys = <&mdss_dsi0_phy>; 2672 phy-names = "dsi"; 2673 2674 #address-cells = <1>; 2675 #size-cells = <0>; 2676 2677 status = "disabled"; 2678 2679 ports { 2680 #address-cells = <1>; 2681 #size-cells = <0>; 2682 2683 port@0 { 2684 reg = <0>; 2685 mdss_dsi0_in: endpoint { 2686 remote-endpoint = <&dpu_intf1_out>; 2687 }; 2688 }; 2689 2690 port@1 { 2691 reg = <1>; 2692 mdss_dsi0_out: endpoint { 2693 }; 2694 }; 2695 }; 2696 2697 mdss_dsi_opp_table: opp-table { 2698 compatible = "operating-points-v2"; 2699 2700 opp-187500000 { 2701 opp-hz = /bits/ 64 <187500000>; 2702 required-opps = <&rpmhpd_opp_low_svs>; 2703 }; 2704 2705 opp-300000000 { 2706 opp-hz = /bits/ 64 <300000000>; 2707 required-opps = <&rpmhpd_opp_svs>; 2708 }; 2709 2710 opp-358000000 { 2711 opp-hz = /bits/ 64 <358000000>; 2712 required-opps = <&rpmhpd_opp_svs_l1>; 2713 }; 2714 }; 2715 }; 2716 2717 mdss_dsi0_phy: phy@ae95000 { 2718 compatible = "qcom,sm8550-dsi-phy-4nm"; 2719 reg = <0 0x0ae95000 0 0x200>, 2720 <0 0x0ae95200 0 0x280>, 2721 <0 0x0ae95500 0 0x400>; 2722 reg-names = "dsi_phy", 2723 "dsi_phy_lane", 2724 "dsi_pll"; 2725 2726 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2727 <&rpmhcc RPMH_CXO_CLK>; 2728 clock-names = "iface", "ref"; 2729 2730 #clock-cells = <1>; 2731 #phy-cells = <0>; 2732 2733 status = "disabled"; 2734 }; 2735 2736 mdss_dsi1: dsi@ae96000 { 2737 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2738 reg = <0 0x0ae96000 0 0x400>; 2739 reg-names = "dsi_ctrl"; 2740 2741 interrupt-parent = <&mdss>; 2742 interrupts = <5>; 2743 2744 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2745 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2746 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2747 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2748 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2749 <&gcc GCC_DISP_HF_AXI_CLK>; 2750 clock-names = "byte", 2751 "byte_intf", 2752 "pixel", 2753 "core", 2754 "iface", 2755 "bus"; 2756 2757 power-domains = <&rpmhpd RPMHPD_MMCX>; 2758 2759 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2760 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2761 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2762 <&mdss_dsi1_phy 1>; 2763 2764 operating-points-v2 = <&mdss_dsi_opp_table>; 2765 2766 phys = <&mdss_dsi1_phy>; 2767 phy-names = "dsi"; 2768 2769 #address-cells = <1>; 2770 #size-cells = <0>; 2771 2772 status = "disabled"; 2773 2774 ports { 2775 #address-cells = <1>; 2776 #size-cells = <0>; 2777 2778 port@0 { 2779 reg = <0>; 2780 mdss_dsi1_in: endpoint { 2781 remote-endpoint = <&dpu_intf2_out>; 2782 }; 2783 }; 2784 2785 port@1 { 2786 reg = <1>; 2787 mdss_dsi1_out: endpoint { 2788 }; 2789 }; 2790 }; 2791 }; 2792 2793 mdss_dsi1_phy: phy@ae97000 { 2794 compatible = "qcom,sm8550-dsi-phy-4nm"; 2795 reg = <0 0x0ae97000 0 0x200>, 2796 <0 0x0ae97200 0 0x280>, 2797 <0 0x0ae97500 0 0x400>; 2798 reg-names = "dsi_phy", 2799 "dsi_phy_lane", 2800 "dsi_pll"; 2801 2802 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2803 <&rpmhcc RPMH_CXO_CLK>; 2804 clock-names = "iface", "ref"; 2805 2806 #clock-cells = <1>; 2807 #phy-cells = <0>; 2808 2809 status = "disabled"; 2810 }; 2811 }; 2812 2813 dispcc: clock-controller@af00000 { 2814 compatible = "qcom,sm8550-dispcc"; 2815 reg = <0 0x0af00000 0 0x20000>; 2816 clocks = <&bi_tcxo_div2>, 2817 <&bi_tcxo_ao_div2>, 2818 <&gcc GCC_DISP_AHB_CLK>, 2819 <&sleep_clk>, 2820 <&mdss_dsi0_phy 0>, 2821 <&mdss_dsi0_phy 1>, 2822 <&mdss_dsi1_phy 0>, 2823 <&mdss_dsi1_phy 1>, 2824 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2825 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 2826 <0>, /* dp1 */ 2827 <0>, 2828 <0>, /* dp2 */ 2829 <0>, 2830 <0>, /* dp3 */ 2831 <0>; 2832 power-domains = <&rpmhpd RPMHPD_MMCX>; 2833 required-opps = <&rpmhpd_opp_low_svs>; 2834 #clock-cells = <1>; 2835 #reset-cells = <1>; 2836 #power-domain-cells = <1>; 2837 }; 2838 2839 usb_1_hsphy: phy@88e3000 { 2840 compatible = "qcom,sm8550-snps-eusb2-phy"; 2841 reg = <0x0 0x088e3000 0x0 0x154>; 2842 #phy-cells = <0>; 2843 2844 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 2845 clock-names = "ref"; 2846 2847 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2848 2849 status = "disabled"; 2850 }; 2851 2852 usb_dp_qmpphy: phy@88e8000 { 2853 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 2854 reg = <0x0 0x088e8000 0x0 0x3000>; 2855 2856 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2857 <&rpmhcc RPMH_CXO_CLK>, 2858 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2859 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2860 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2861 2862 power-domains = <&gcc USB3_PHY_GDSC>; 2863 2864 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2865 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2866 reset-names = "phy", "common"; 2867 2868 #clock-cells = <1>; 2869 #phy-cells = <1>; 2870 2871 status = "disabled"; 2872 2873 ports { 2874 #address-cells = <1>; 2875 #size-cells = <0>; 2876 2877 port@0 { 2878 reg = <0>; 2879 2880 usb_dp_qmpphy_out: endpoint { 2881 }; 2882 }; 2883 2884 port@1 { 2885 reg = <1>; 2886 2887 usb_dp_qmpphy_usb_ss_in: endpoint { 2888 }; 2889 }; 2890 2891 port@2 { 2892 reg = <2>; 2893 2894 usb_dp_qmpphy_dp_in: endpoint { 2895 }; 2896 }; 2897 }; 2898 }; 2899 2900 usb_1: usb@a6f8800 { 2901 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 2902 reg = <0x0 0x0a6f8800 0x0 0x400>; 2903 #address-cells = <2>; 2904 #size-cells = <2>; 2905 ranges; 2906 2907 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2908 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2909 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2910 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2911 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2912 <&tcsr TCSR_USB3_CLKREF_EN>; 2913 clock-names = "cfg_noc", 2914 "core", 2915 "iface", 2916 "sleep", 2917 "mock_utmi", 2918 "xo"; 2919 2920 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2921 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2922 assigned-clock-rates = <19200000>, <200000000>; 2923 2924 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2925 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2926 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 2927 <&pdc 14 IRQ_TYPE_EDGE_RISING>; 2928 interrupt-names = "hs_phy_irq", 2929 "ss_phy_irq", 2930 "dm_hs_phy_irq", 2931 "dp_hs_phy_irq"; 2932 2933 power-domains = <&gcc USB30_PRIM_GDSC>; 2934 required-opps = <&rpmhpd_opp_nom>; 2935 2936 resets = <&gcc GCC_USB30_PRIM_BCR>; 2937 2938 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2939 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2940 interconnect-names = "usb-ddr", "apps-usb"; 2941 2942 status = "disabled"; 2943 2944 usb_1_dwc3: usb@a600000 { 2945 compatible = "snps,dwc3"; 2946 reg = <0x0 0x0a600000 0x0 0xcd00>; 2947 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2948 iommus = <&apps_smmu 0x40 0x0>; 2949 snps,dis_u2_susphy_quirk; 2950 snps,dis_enblslpm_quirk; 2951 snps,usb3_lpm_capable; 2952 phys = <&usb_1_hsphy>, 2953 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 2954 phy-names = "usb2-phy", "usb3-phy"; 2955 2956 ports { 2957 #address-cells = <1>; 2958 #size-cells = <0>; 2959 2960 port@0 { 2961 reg = <0>; 2962 2963 usb_1_dwc3_hs: endpoint { 2964 }; 2965 }; 2966 2967 port@1 { 2968 reg = <1>; 2969 2970 usb_1_dwc3_ss: endpoint { 2971 }; 2972 }; 2973 }; 2974 }; 2975 }; 2976 2977 pdc: interrupt-controller@b220000 { 2978 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 2979 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 2980 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2981 <125 63 1>, <126 716 12>, 2982 <138 251 5>; 2983 #interrupt-cells = <2>; 2984 interrupt-parent = <&intc>; 2985 interrupt-controller; 2986 }; 2987 2988 tsens0: thermal-sensor@c271000 { 2989 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2990 reg = <0 0x0c271000 0 0x1000>, /* TM */ 2991 <0 0x0c222000 0 0x1000>; /* SROT */ 2992 #qcom,sensors = <16>; 2993 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2994 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 2995 interrupt-names = "uplow", "critical"; 2996 #thermal-sensor-cells = <1>; 2997 }; 2998 2999 tsens1: thermal-sensor@c272000 { 3000 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3001 reg = <0 0x0c272000 0 0x1000>, /* TM */ 3002 <0 0x0c223000 0 0x1000>; /* SROT */ 3003 #qcom,sensors = <16>; 3004 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3005 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 3006 interrupt-names = "uplow", "critical"; 3007 #thermal-sensor-cells = <1>; 3008 }; 3009 3010 tsens2: thermal-sensor@c273000 { 3011 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3012 reg = <0 0x0c273000 0 0x1000>, /* TM */ 3013 <0 0x0c224000 0 0x1000>; /* SROT */ 3014 #qcom,sensors = <16>; 3015 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 3016 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 3017 interrupt-names = "uplow", "critical"; 3018 #thermal-sensor-cells = <1>; 3019 }; 3020 3021 aoss_qmp: power-management@c300000 { 3022 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 3023 reg = <0 0x0c300000 0 0x400>; 3024 interrupt-parent = <&ipcc>; 3025 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3026 IRQ_TYPE_EDGE_RISING>; 3027 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3028 3029 #clock-cells = <0>; 3030 }; 3031 3032 sram@c3f0000 { 3033 compatible = "qcom,rpmh-stats"; 3034 reg = <0 0x0c3f0000 0 0x400>; 3035 }; 3036 3037 spmi_bus: spmi@c400000 { 3038 compatible = "qcom,spmi-pmic-arb"; 3039 reg = <0 0x0c400000 0 0x3000>, 3040 <0 0x0c500000 0 0x4000000>, 3041 <0 0x0c440000 0 0x80000>, 3042 <0 0x0c4c0000 0 0x20000>, 3043 <0 0x0c42d000 0 0x4000>; 3044 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3045 interrupt-names = "periph_irq"; 3046 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3047 qcom,ee = <0>; 3048 qcom,channel = <0>; 3049 qcom,bus-id = <0>; 3050 #address-cells = <2>; 3051 #size-cells = <0>; 3052 interrupt-controller; 3053 #interrupt-cells = <4>; 3054 }; 3055 3056 tlmm: pinctrl@f100000 { 3057 compatible = "qcom,sm8550-tlmm"; 3058 reg = <0 0x0f100000 0 0x300000>; 3059 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3060 gpio-controller; 3061 #gpio-cells = <2>; 3062 interrupt-controller; 3063 #interrupt-cells = <2>; 3064 gpio-ranges = <&tlmm 0 0 211>; 3065 wakeup-parent = <&pdc>; 3066 3067 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3068 /* SDA, SCL */ 3069 pins = "gpio16", "gpio17"; 3070 function = "i2chub0_se0"; 3071 drive-strength = <2>; 3072 bias-pull-up; 3073 }; 3074 3075 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 3076 /* SDA, SCL */ 3077 pins = "gpio18", "gpio19"; 3078 function = "i2chub0_se1"; 3079 drive-strength = <2>; 3080 bias-pull-up; 3081 }; 3082 3083 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 3084 /* SDA, SCL */ 3085 pins = "gpio20", "gpio21"; 3086 function = "i2chub0_se2"; 3087 drive-strength = <2>; 3088 bias-pull-up; 3089 }; 3090 3091 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 3092 /* SDA, SCL */ 3093 pins = "gpio22", "gpio23"; 3094 function = "i2chub0_se3"; 3095 drive-strength = <2>; 3096 bias-pull-up; 3097 }; 3098 3099 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 3100 /* SDA, SCL */ 3101 pins = "gpio4", "gpio5"; 3102 function = "i2chub0_se4"; 3103 drive-strength = <2>; 3104 bias-pull-up; 3105 }; 3106 3107 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 3108 /* SDA, SCL */ 3109 pins = "gpio6", "gpio7"; 3110 function = "i2chub0_se5"; 3111 drive-strength = <2>; 3112 bias-pull-up; 3113 }; 3114 3115 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 3116 /* SDA, SCL */ 3117 pins = "gpio8", "gpio9"; 3118 function = "i2chub0_se6"; 3119 drive-strength = <2>; 3120 bias-pull-up; 3121 }; 3122 3123 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 3124 /* SDA, SCL */ 3125 pins = "gpio10", "gpio11"; 3126 function = "i2chub0_se7"; 3127 drive-strength = <2>; 3128 bias-pull-up; 3129 }; 3130 3131 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 3132 /* SDA, SCL */ 3133 pins = "gpio206", "gpio207"; 3134 function = "i2chub0_se8"; 3135 drive-strength = <2>; 3136 bias-pull-up; 3137 }; 3138 3139 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 3140 /* SDA, SCL */ 3141 pins = "gpio84", "gpio85"; 3142 function = "i2chub0_se9"; 3143 drive-strength = <2>; 3144 bias-pull-up; 3145 }; 3146 3147 pcie0_default_state: pcie0-default-state { 3148 perst-pins { 3149 pins = "gpio94"; 3150 function = "gpio"; 3151 drive-strength = <2>; 3152 bias-pull-down; 3153 }; 3154 3155 clkreq-pins { 3156 pins = "gpio95"; 3157 function = "pcie0_clk_req_n"; 3158 drive-strength = <2>; 3159 bias-pull-up; 3160 }; 3161 3162 wake-pins { 3163 pins = "gpio96"; 3164 function = "gpio"; 3165 drive-strength = <2>; 3166 bias-pull-up; 3167 }; 3168 }; 3169 3170 pcie1_default_state: pcie1-default-state { 3171 perst-pins { 3172 pins = "gpio97"; 3173 function = "gpio"; 3174 drive-strength = <2>; 3175 bias-pull-down; 3176 }; 3177 3178 clkreq-pins { 3179 pins = "gpio98"; 3180 function = "pcie1_clk_req_n"; 3181 drive-strength = <2>; 3182 bias-pull-up; 3183 }; 3184 3185 wake-pins { 3186 pins = "gpio99"; 3187 function = "gpio"; 3188 drive-strength = <2>; 3189 bias-pull-up; 3190 }; 3191 }; 3192 3193 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3194 /* SDA, SCL */ 3195 pins = "gpio28", "gpio29"; 3196 function = "qup1_se0"; 3197 drive-strength = <2>; 3198 bias-pull-up = <2200>; 3199 }; 3200 3201 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3202 /* SDA, SCL */ 3203 pins = "gpio32", "gpio33"; 3204 function = "qup1_se1"; 3205 drive-strength = <2>; 3206 bias-pull-up = <2200>; 3207 }; 3208 3209 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3210 /* SDA, SCL */ 3211 pins = "gpio36", "gpio37"; 3212 function = "qup1_se2"; 3213 drive-strength = <2>; 3214 bias-pull-up = <2200>; 3215 }; 3216 3217 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3218 /* SDA, SCL */ 3219 pins = "gpio40", "gpio41"; 3220 function = "qup1_se3"; 3221 drive-strength = <2>; 3222 bias-pull-up = <2200>; 3223 }; 3224 3225 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3226 /* SDA, SCL */ 3227 pins = "gpio44", "gpio45"; 3228 function = "qup1_se4"; 3229 drive-strength = <2>; 3230 bias-pull-up = <2200>; 3231 }; 3232 3233 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3234 /* SDA, SCL */ 3235 pins = "gpio52", "gpio53"; 3236 function = "qup1_se5"; 3237 drive-strength = <2>; 3238 bias-pull-up = <2200>; 3239 }; 3240 3241 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3242 /* SDA, SCL */ 3243 pins = "gpio48", "gpio49"; 3244 function = "qup1_se6"; 3245 drive-strength = <2>; 3246 bias-pull-up = <2200>; 3247 }; 3248 3249 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3250 scl-pins { 3251 pins = "gpio57"; 3252 function = "qup2_se0_l1_mira"; 3253 drive-strength = <2>; 3254 bias-pull-up = <2200>; 3255 }; 3256 3257 sda-pins { 3258 pins = "gpio56"; 3259 function = "qup2_se0_l0_mira"; 3260 drive-strength = <2>; 3261 bias-pull-up = <2200>; 3262 }; 3263 }; 3264 3265 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3266 /* SDA, SCL */ 3267 pins = "gpio60", "gpio61"; 3268 function = "qup2_se1"; 3269 drive-strength = <2>; 3270 bias-pull-up = <2200>; 3271 }; 3272 3273 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3274 /* SDA, SCL */ 3275 pins = "gpio64", "gpio65"; 3276 function = "qup2_se2"; 3277 drive-strength = <2>; 3278 bias-pull-up = <2200>; 3279 }; 3280 3281 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3282 /* SDA, SCL */ 3283 pins = "gpio68", "gpio69"; 3284 function = "qup2_se3"; 3285 drive-strength = <2>; 3286 bias-pull-up = <2200>; 3287 }; 3288 3289 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3290 /* SDA, SCL */ 3291 pins = "gpio2", "gpio3"; 3292 function = "qup2_se4"; 3293 drive-strength = <2>; 3294 bias-pull-up = <2200>; 3295 }; 3296 3297 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3298 /* SDA, SCL */ 3299 pins = "gpio80", "gpio81"; 3300 function = "qup2_se5"; 3301 drive-strength = <2>; 3302 bias-pull-up = <2200>; 3303 }; 3304 3305 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3306 /* SDA, SCL */ 3307 pins = "gpio72", "gpio106"; 3308 function = "qup2_se7"; 3309 drive-strength = <2>; 3310 bias-pull-up = <2200>; 3311 }; 3312 3313 qup_spi0_cs: qup-spi0-cs-state { 3314 pins = "gpio31"; 3315 function = "qup1_se0"; 3316 drive-strength = <6>; 3317 bias-disable; 3318 }; 3319 3320 qup_spi0_data_clk: qup-spi0-data-clk-state { 3321 /* MISO, MOSI, CLK */ 3322 pins = "gpio28", "gpio29", "gpio30"; 3323 function = "qup1_se0"; 3324 drive-strength = <6>; 3325 bias-disable; 3326 }; 3327 3328 qup_spi1_cs: qup-spi1-cs-state { 3329 pins = "gpio35"; 3330 function = "qup1_se1"; 3331 drive-strength = <6>; 3332 bias-disable; 3333 }; 3334 3335 qup_spi1_data_clk: qup-spi1-data-clk-state { 3336 /* MISO, MOSI, CLK */ 3337 pins = "gpio32", "gpio33", "gpio34"; 3338 function = "qup1_se1"; 3339 drive-strength = <6>; 3340 bias-disable; 3341 }; 3342 3343 qup_spi2_cs: qup-spi2-cs-state { 3344 pins = "gpio39"; 3345 function = "qup1_se2"; 3346 drive-strength = <6>; 3347 bias-disable; 3348 }; 3349 3350 qup_spi2_data_clk: qup-spi2-data-clk-state { 3351 /* MISO, MOSI, CLK */ 3352 pins = "gpio36", "gpio37", "gpio38"; 3353 function = "qup1_se2"; 3354 drive-strength = <6>; 3355 bias-disable; 3356 }; 3357 3358 qup_spi3_cs: qup-spi3-cs-state { 3359 pins = "gpio43"; 3360 function = "qup1_se3"; 3361 drive-strength = <6>; 3362 bias-disable; 3363 }; 3364 3365 qup_spi3_data_clk: qup-spi3-data-clk-state { 3366 /* MISO, MOSI, CLK */ 3367 pins = "gpio40", "gpio41", "gpio42"; 3368 function = "qup1_se3"; 3369 drive-strength = <6>; 3370 bias-disable; 3371 }; 3372 3373 qup_spi4_cs: qup-spi4-cs-state { 3374 pins = "gpio47"; 3375 function = "qup1_se4"; 3376 drive-strength = <6>; 3377 bias-disable; 3378 }; 3379 3380 qup_spi4_data_clk: qup-spi4-data-clk-state { 3381 /* MISO, MOSI, CLK */ 3382 pins = "gpio44", "gpio45", "gpio46"; 3383 function = "qup1_se4"; 3384 drive-strength = <6>; 3385 bias-disable; 3386 }; 3387 3388 qup_spi5_cs: qup-spi5-cs-state { 3389 pins = "gpio55"; 3390 function = "qup1_se5"; 3391 drive-strength = <6>; 3392 bias-disable; 3393 }; 3394 3395 qup_spi5_data_clk: qup-spi5-data-clk-state { 3396 /* MISO, MOSI, CLK */ 3397 pins = "gpio52", "gpio53", "gpio54"; 3398 function = "qup1_se5"; 3399 drive-strength = <6>; 3400 bias-disable; 3401 }; 3402 3403 qup_spi6_cs: qup-spi6-cs-state { 3404 pins = "gpio51"; 3405 function = "qup1_se6"; 3406 drive-strength = <6>; 3407 bias-disable; 3408 }; 3409 3410 qup_spi6_data_clk: qup-spi6-data-clk-state { 3411 /* MISO, MOSI, CLK */ 3412 pins = "gpio48", "gpio49", "gpio50"; 3413 function = "qup1_se6"; 3414 drive-strength = <6>; 3415 bias-disable; 3416 }; 3417 3418 qup_spi8_cs: qup-spi8-cs-state { 3419 pins = "gpio59"; 3420 function = "qup2_se0_l3_mira"; 3421 drive-strength = <6>; 3422 bias-disable; 3423 }; 3424 3425 qup_spi8_data_clk: qup-spi8-data-clk-state { 3426 /* MISO, MOSI, CLK */ 3427 pins = "gpio56", "gpio57", "gpio58"; 3428 function = "qup2_se0_l2_mira"; 3429 drive-strength = <6>; 3430 bias-disable; 3431 }; 3432 3433 qup_spi9_cs: qup-spi9-cs-state { 3434 pins = "gpio63"; 3435 function = "qup2_se1"; 3436 drive-strength = <6>; 3437 bias-disable; 3438 }; 3439 3440 qup_spi9_data_clk: qup-spi9-data-clk-state { 3441 /* MISO, MOSI, CLK */ 3442 pins = "gpio60", "gpio61", "gpio62"; 3443 function = "qup2_se1"; 3444 drive-strength = <6>; 3445 bias-disable; 3446 }; 3447 3448 qup_spi10_cs: qup-spi10-cs-state { 3449 pins = "gpio67"; 3450 function = "qup2_se2"; 3451 drive-strength = <6>; 3452 bias-disable; 3453 }; 3454 3455 qup_spi10_data_clk: qup-spi10-data-clk-state { 3456 /* MISO, MOSI, CLK */ 3457 pins = "gpio64", "gpio65", "gpio66"; 3458 function = "qup2_se2"; 3459 drive-strength = <6>; 3460 bias-disable; 3461 }; 3462 3463 qup_spi11_cs: qup-spi11-cs-state { 3464 pins = "gpio71"; 3465 function = "qup2_se3"; 3466 drive-strength = <6>; 3467 bias-disable; 3468 }; 3469 3470 qup_spi11_data_clk: qup-spi11-data-clk-state { 3471 /* MISO, MOSI, CLK */ 3472 pins = "gpio68", "gpio69", "gpio70"; 3473 function = "qup2_se3"; 3474 drive-strength = <6>; 3475 bias-disable; 3476 }; 3477 3478 qup_spi12_cs: qup-spi12-cs-state { 3479 pins = "gpio119"; 3480 function = "qup2_se4"; 3481 drive-strength = <6>; 3482 bias-disable; 3483 }; 3484 3485 qup_spi12_data_clk: qup-spi12-data-clk-state { 3486 /* MISO, MOSI, CLK */ 3487 pins = "gpio2", "gpio3", "gpio118"; 3488 function = "qup2_se4"; 3489 drive-strength = <6>; 3490 bias-disable; 3491 }; 3492 3493 qup_spi13_cs: qup-spi13-cs-state { 3494 pins = "gpio83"; 3495 function = "qup2_se5"; 3496 drive-strength = <6>; 3497 bias-disable; 3498 }; 3499 3500 qup_spi13_data_clk: qup-spi13-data-clk-state { 3501 /* MISO, MOSI, CLK */ 3502 pins = "gpio80", "gpio81", "gpio82"; 3503 function = "qup2_se5"; 3504 drive-strength = <6>; 3505 bias-disable; 3506 }; 3507 3508 qup_spi15_cs: qup-spi15-cs-state { 3509 pins = "gpio75"; 3510 function = "qup2_se7"; 3511 drive-strength = <6>; 3512 bias-disable; 3513 }; 3514 3515 qup_spi15_data_clk: qup-spi15-data-clk-state { 3516 /* MISO, MOSI, CLK */ 3517 pins = "gpio72", "gpio106", "gpio74"; 3518 function = "qup2_se7"; 3519 drive-strength = <6>; 3520 bias-disable; 3521 }; 3522 3523 qup_uart7_default: qup-uart7-default-state { 3524 /* TX, RX */ 3525 pins = "gpio26", "gpio27"; 3526 function = "qup1_se7"; 3527 drive-strength = <2>; 3528 bias-disable; 3529 }; 3530 3531 qup_uart14_default: qup-uart14-default-state { 3532 /* TX, RX */ 3533 pins = "gpio78", "gpio79"; 3534 function = "qup2_se6"; 3535 drive-strength = <2>; 3536 bias-pull-up; 3537 }; 3538 3539 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 3540 /* CTS, RTS */ 3541 pins = "gpio76", "gpio77"; 3542 function = "qup2_se6"; 3543 drive-strength = <2>; 3544 bias-pull-down; 3545 }; 3546 3547 sdc2_sleep: sdc2-sleep-state { 3548 clk-pins { 3549 pins = "sdc2_clk"; 3550 bias-disable; 3551 drive-strength = <2>; 3552 }; 3553 3554 cmd-pins { 3555 pins = "sdc2_cmd"; 3556 bias-pull-up; 3557 drive-strength = <2>; 3558 }; 3559 3560 data-pins { 3561 pins = "sdc2_data"; 3562 bias-pull-up; 3563 drive-strength = <2>; 3564 }; 3565 }; 3566 3567 sdc2_default: sdc2-default-state { 3568 clk-pins { 3569 pins = "sdc2_clk"; 3570 bias-disable; 3571 drive-strength = <16>; 3572 }; 3573 3574 cmd-pins { 3575 pins = "sdc2_cmd"; 3576 bias-pull-up; 3577 drive-strength = <10>; 3578 }; 3579 3580 data-pins { 3581 pins = "sdc2_data"; 3582 bias-pull-up; 3583 drive-strength = <10>; 3584 }; 3585 }; 3586 }; 3587 3588 apps_smmu: iommu@15000000 { 3589 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3590 reg = <0 0x15000000 0 0x100000>; 3591 #iommu-cells = <2>; 3592 #global-interrupts = <1>; 3593 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3594 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3595 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3596 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3597 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3598 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3599 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3600 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3601 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3602 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3603 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3604 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3605 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3613 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3614 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3630 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3631 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3632 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3633 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3645 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3647 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3652 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3653 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3654 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3656 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3657 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3658 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3659 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3660 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3661 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3662 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3663 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3665 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3666 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3667 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3668 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3669 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3670 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3671 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3672 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3673 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3674 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3675 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3676 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3677 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3678 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3679 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3680 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3681 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3682 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3683 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3684 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3685 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3686 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3687 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3688 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3689 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 3690 }; 3691 3692 intc: interrupt-controller@17100000 { 3693 compatible = "arm,gic-v3"; 3694 reg = <0 0x17100000 0 0x10000>, /* GICD */ 3695 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 3696 ranges; 3697 #interrupt-cells = <3>; 3698 interrupt-controller; 3699 #redistributor-regions = <1>; 3700 redistributor-stride = <0 0x40000>; 3701 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3702 #address-cells = <2>; 3703 #size-cells = <2>; 3704 3705 gic_its: msi-controller@17140000 { 3706 compatible = "arm,gic-v3-its"; 3707 reg = <0 0x17140000 0 0x20000>; 3708 msi-controller; 3709 #msi-cells = <1>; 3710 }; 3711 }; 3712 3713 timer@17420000 { 3714 compatible = "arm,armv7-timer-mem"; 3715 reg = <0 0x17420000 0 0x1000>; 3716 ranges = <0 0 0 0x20000000>; 3717 #address-cells = <1>; 3718 #size-cells = <1>; 3719 3720 frame@17421000 { 3721 reg = <0x17421000 0x1000>, 3722 <0x17422000 0x1000>; 3723 frame-number = <0>; 3724 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3726 }; 3727 3728 frame@17423000 { 3729 reg = <0x17423000 0x1000>; 3730 frame-number = <1>; 3731 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3732 status = "disabled"; 3733 }; 3734 3735 frame@17425000 { 3736 reg = <0x17425000 0x1000>; 3737 frame-number = <2>; 3738 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3739 status = "disabled"; 3740 }; 3741 3742 frame@17427000 { 3743 reg = <0x17427000 0x1000>; 3744 frame-number = <3>; 3745 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3746 status = "disabled"; 3747 }; 3748 3749 frame@17429000 { 3750 reg = <0x17429000 0x1000>; 3751 frame-number = <4>; 3752 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3753 status = "disabled"; 3754 }; 3755 3756 frame@1742b000 { 3757 reg = <0x1742b000 0x1000>; 3758 frame-number = <5>; 3759 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3760 status = "disabled"; 3761 }; 3762 3763 frame@1742d000 { 3764 reg = <0x1742d000 0x1000>; 3765 frame-number = <6>; 3766 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3767 status = "disabled"; 3768 }; 3769 }; 3770 3771 apps_rsc: rsc@17a00000 { 3772 label = "apps_rsc"; 3773 compatible = "qcom,rpmh-rsc"; 3774 reg = <0 0x17a00000 0 0x10000>, 3775 <0 0x17a10000 0 0x10000>, 3776 <0 0x17a20000 0 0x10000>, 3777 <0 0x17a30000 0 0x10000>; 3778 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3779 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3782 qcom,tcs-offset = <0xd00>; 3783 qcom,drv-id = <2>; 3784 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3785 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3786 power-domains = <&CLUSTER_PD>; 3787 3788 apps_bcm_voter: bcm-voter { 3789 compatible = "qcom,bcm-voter"; 3790 }; 3791 3792 rpmhcc: clock-controller { 3793 compatible = "qcom,sm8550-rpmh-clk"; 3794 #clock-cells = <1>; 3795 clock-names = "xo"; 3796 clocks = <&xo_board>; 3797 }; 3798 3799 rpmhpd: power-controller { 3800 compatible = "qcom,sm8550-rpmhpd"; 3801 #power-domain-cells = <1>; 3802 operating-points-v2 = <&rpmhpd_opp_table>; 3803 3804 rpmhpd_opp_table: opp-table { 3805 compatible = "operating-points-v2"; 3806 3807 rpmhpd_opp_ret: opp-16 { 3808 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3809 }; 3810 3811 rpmhpd_opp_min_svs: opp-48 { 3812 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3813 }; 3814 3815 rpmhpd_opp_low_svs_d2: opp-52 { 3816 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 3817 }; 3818 3819 rpmhpd_opp_low_svs_d1: opp-56 { 3820 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3821 }; 3822 3823 rpmhpd_opp_low_svs_d0: opp-60 { 3824 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 3825 }; 3826 3827 rpmhpd_opp_low_svs: opp-64 { 3828 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3829 }; 3830 3831 rpmhpd_opp_low_svs_l1: opp-80 { 3832 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 3833 }; 3834 3835 rpmhpd_opp_svs: opp-128 { 3836 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3837 }; 3838 3839 rpmhpd_opp_svs_l0: opp-144 { 3840 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 3841 }; 3842 3843 rpmhpd_opp_svs_l1: opp-192 { 3844 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3845 }; 3846 3847 rpmhpd_opp_nom: opp-256 { 3848 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3849 }; 3850 3851 rpmhpd_opp_nom_l1: opp-320 { 3852 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3853 }; 3854 3855 rpmhpd_opp_nom_l2: opp-336 { 3856 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3857 }; 3858 3859 rpmhpd_opp_turbo: opp-384 { 3860 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3861 }; 3862 3863 rpmhpd_opp_turbo_l1: opp-416 { 3864 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3865 }; 3866 }; 3867 }; 3868 }; 3869 3870 cpufreq_hw: cpufreq@17d91000 { 3871 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 3872 reg = <0 0x17d91000 0 0x1000>, 3873 <0 0x17d92000 0 0x1000>, 3874 <0 0x17d93000 0 0x1000>; 3875 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3876 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 3877 clock-names = "xo", "alternate"; 3878 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3879 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3880 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3881 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 3882 #freq-domain-cells = <1>; 3883 #clock-cells = <1>; 3884 }; 3885 3886 pmu@24091000 { 3887 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3888 reg = <0 0x24091000 0 0x1000>; 3889 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3890 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3891 3892 operating-points-v2 = <&llcc_bwmon_opp_table>; 3893 3894 llcc_bwmon_opp_table: opp-table { 3895 compatible = "operating-points-v2"; 3896 3897 opp-0 { 3898 opp-peak-kBps = <2086000>; 3899 }; 3900 3901 opp-1 { 3902 opp-peak-kBps = <2929000>; 3903 }; 3904 3905 opp-2 { 3906 opp-peak-kBps = <5931000>; 3907 }; 3908 3909 opp-3 { 3910 opp-peak-kBps = <6515000>; 3911 }; 3912 3913 opp-4 { 3914 opp-peak-kBps = <7980000>; 3915 }; 3916 3917 opp-5 { 3918 opp-peak-kBps = <10437000>; 3919 }; 3920 3921 opp-6 { 3922 opp-peak-kBps = <12157000>; 3923 }; 3924 3925 opp-7 { 3926 opp-peak-kBps = <14060000>; 3927 }; 3928 3929 opp-8 { 3930 opp-peak-kBps = <16113000>; 3931 }; 3932 }; 3933 }; 3934 3935 pmu@240b6400 { 3936 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 3937 reg = <0 0x240b6400 0 0x600>; 3938 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3939 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3940 3941 operating-points-v2 = <&cpu_bwmon_opp_table>; 3942 3943 cpu_bwmon_opp_table: opp-table { 3944 compatible = "operating-points-v2"; 3945 3946 opp-0 { 3947 opp-peak-kBps = <4577000>; 3948 }; 3949 3950 opp-1 { 3951 opp-peak-kBps = <7110000>; 3952 }; 3953 3954 opp-2 { 3955 opp-peak-kBps = <9155000>; 3956 }; 3957 3958 opp-3 { 3959 opp-peak-kBps = <12298000>; 3960 }; 3961 3962 opp-4 { 3963 opp-peak-kBps = <14236000>; 3964 }; 3965 3966 opp-5 { 3967 opp-peak-kBps = <16265000>; 3968 }; 3969 }; 3970 }; 3971 3972 gem_noc: interconnect@24100000 { 3973 compatible = "qcom,sm8550-gem-noc"; 3974 reg = <0 0x24100000 0 0xbb800>; 3975 #interconnect-cells = <2>; 3976 qcom,bcm-voters = <&apps_bcm_voter>; 3977 }; 3978 3979 system-cache-controller@25000000 { 3980 compatible = "qcom,sm8550-llcc"; 3981 reg = <0 0x25000000 0 0x200000>, 3982 <0 0x25200000 0 0x200000>, 3983 <0 0x25400000 0 0x200000>, 3984 <0 0x25600000 0 0x200000>, 3985 <0 0x25800000 0 0x200000>; 3986 reg-names = "llcc0_base", 3987 "llcc1_base", 3988 "llcc2_base", 3989 "llcc3_base", 3990 "llcc_broadcast_base"; 3991 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3992 }; 3993 3994 remoteproc_adsp: remoteproc@30000000 { 3995 compatible = "qcom,sm8550-adsp-pas"; 3996 reg = <0x0 0x30000000 0x0 0x100>; 3997 3998 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3999 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4000 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4001 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4002 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4003 interrupt-names = "wdog", "fatal", "ready", 4004 "handover", "stop-ack"; 4005 4006 clocks = <&rpmhcc RPMH_CXO_CLK>; 4007 clock-names = "xo"; 4008 4009 power-domains = <&rpmhpd RPMHPD_LCX>, 4010 <&rpmhpd RPMHPD_LMX>; 4011 power-domain-names = "lcx", "lmx"; 4012 4013 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 4014 4015 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 4016 4017 qcom,qmp = <&aoss_qmp>; 4018 4019 qcom,smem-states = <&smp2p_adsp_out 0>; 4020 qcom,smem-state-names = "stop"; 4021 4022 status = "disabled"; 4023 4024 remoteproc_adsp_glink: glink-edge { 4025 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4026 IPCC_MPROC_SIGNAL_GLINK_QMP 4027 IRQ_TYPE_EDGE_RISING>; 4028 mboxes = <&ipcc IPCC_CLIENT_LPASS 4029 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4030 4031 label = "lpass"; 4032 qcom,remote-pid = <2>; 4033 4034 fastrpc { 4035 compatible = "qcom,fastrpc"; 4036 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4037 label = "adsp"; 4038 #address-cells = <1>; 4039 #size-cells = <0>; 4040 4041 compute-cb@3 { 4042 compatible = "qcom,fastrpc-compute-cb"; 4043 reg = <3>; 4044 iommus = <&apps_smmu 0x1003 0x80>, 4045 <&apps_smmu 0x1063 0x0>; 4046 }; 4047 4048 compute-cb@4 { 4049 compatible = "qcom,fastrpc-compute-cb"; 4050 reg = <4>; 4051 iommus = <&apps_smmu 0x1004 0x80>, 4052 <&apps_smmu 0x1064 0x0>; 4053 }; 4054 4055 compute-cb@5 { 4056 compatible = "qcom,fastrpc-compute-cb"; 4057 reg = <5>; 4058 iommus = <&apps_smmu 0x1005 0x80>, 4059 <&apps_smmu 0x1065 0x0>; 4060 }; 4061 4062 compute-cb@6 { 4063 compatible = "qcom,fastrpc-compute-cb"; 4064 reg = <6>; 4065 iommus = <&apps_smmu 0x1006 0x80>, 4066 <&apps_smmu 0x1066 0x0>; 4067 }; 4068 4069 compute-cb@7 { 4070 compatible = "qcom,fastrpc-compute-cb"; 4071 reg = <7>; 4072 iommus = <&apps_smmu 0x1007 0x80>, 4073 <&apps_smmu 0x1067 0x0>; 4074 }; 4075 }; 4076 4077 gpr { 4078 compatible = "qcom,gpr"; 4079 qcom,glink-channels = "adsp_apps"; 4080 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4081 qcom,intents = <512 20>; 4082 #address-cells = <1>; 4083 #size-cells = <0>; 4084 4085 q6apm: service@1 { 4086 compatible = "qcom,q6apm"; 4087 reg = <GPR_APM_MODULE_IID>; 4088 #sound-dai-cells = <0>; 4089 qcom,protection-domain = "avs/audio", 4090 "msm/adsp/audio_pd"; 4091 4092 q6apmdai: dais { 4093 compatible = "qcom,q6apm-dais"; 4094 iommus = <&apps_smmu 0x1001 0x80>, 4095 <&apps_smmu 0x1061 0x0>; 4096 }; 4097 4098 q6apmbedai: bedais { 4099 compatible = "qcom,q6apm-lpass-dais"; 4100 #sound-dai-cells = <1>; 4101 }; 4102 }; 4103 4104 q6prm: service@2 { 4105 compatible = "qcom,q6prm"; 4106 reg = <GPR_PRM_MODULE_IID>; 4107 qcom,protection-domain = "avs/audio", 4108 "msm/adsp/audio_pd"; 4109 4110 q6prmcc: clock-controller { 4111 compatible = "qcom,q6prm-lpass-clocks"; 4112 #clock-cells = <2>; 4113 }; 4114 }; 4115 }; 4116 }; 4117 }; 4118 4119 nsp_noc: interconnect@320c0000 { 4120 compatible = "qcom,sm8550-nsp-noc"; 4121 reg = <0 0x320c0000 0 0xe080>; 4122 #interconnect-cells = <2>; 4123 qcom,bcm-voters = <&apps_bcm_voter>; 4124 }; 4125 4126 remoteproc_cdsp: remoteproc@32300000 { 4127 compatible = "qcom,sm8550-cdsp-pas"; 4128 reg = <0x0 0x32300000 0x0 0x1400000>; 4129 4130 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4131 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 4132 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 4133 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 4134 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 4135 interrupt-names = "wdog", "fatal", "ready", 4136 "handover", "stop-ack"; 4137 4138 clocks = <&rpmhcc RPMH_CXO_CLK>; 4139 clock-names = "xo"; 4140 4141 power-domains = <&rpmhpd RPMHPD_CX>, 4142 <&rpmhpd RPMHPD_MXC>, 4143 <&rpmhpd RPMHPD_NSP>; 4144 power-domain-names = "cx", "mxc", "nsp"; 4145 4146 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4147 4148 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 4149 4150 qcom,qmp = <&aoss_qmp>; 4151 4152 qcom,smem-states = <&smp2p_cdsp_out 0>; 4153 qcom,smem-state-names = "stop"; 4154 4155 status = "disabled"; 4156 4157 glink-edge { 4158 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4159 IPCC_MPROC_SIGNAL_GLINK_QMP 4160 IRQ_TYPE_EDGE_RISING>; 4161 mboxes = <&ipcc IPCC_CLIENT_CDSP 4162 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4163 4164 label = "cdsp"; 4165 qcom,remote-pid = <5>; 4166 4167 fastrpc { 4168 compatible = "qcom,fastrpc"; 4169 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4170 label = "cdsp"; 4171 #address-cells = <1>; 4172 #size-cells = <0>; 4173 4174 compute-cb@1 { 4175 compatible = "qcom,fastrpc-compute-cb"; 4176 reg = <1>; 4177 iommus = <&apps_smmu 0x1961 0x0>, 4178 <&apps_smmu 0x0c01 0x20>, 4179 <&apps_smmu 0x19c1 0x10>; 4180 }; 4181 4182 compute-cb@2 { 4183 compatible = "qcom,fastrpc-compute-cb"; 4184 reg = <2>; 4185 iommus = <&apps_smmu 0x1962 0x0>, 4186 <&apps_smmu 0x0c02 0x20>, 4187 <&apps_smmu 0x19c2 0x10>; 4188 }; 4189 4190 compute-cb@3 { 4191 compatible = "qcom,fastrpc-compute-cb"; 4192 reg = <3>; 4193 iommus = <&apps_smmu 0x1963 0x0>, 4194 <&apps_smmu 0x0c03 0x20>, 4195 <&apps_smmu 0x19c3 0x10>; 4196 }; 4197 4198 compute-cb@4 { 4199 compatible = "qcom,fastrpc-compute-cb"; 4200 reg = <4>; 4201 iommus = <&apps_smmu 0x1964 0x0>, 4202 <&apps_smmu 0x0c04 0x20>, 4203 <&apps_smmu 0x19c4 0x10>; 4204 }; 4205 4206 compute-cb@5 { 4207 compatible = "qcom,fastrpc-compute-cb"; 4208 reg = <5>; 4209 iommus = <&apps_smmu 0x1965 0x0>, 4210 <&apps_smmu 0x0c05 0x20>, 4211 <&apps_smmu 0x19c5 0x10>; 4212 }; 4213 4214 compute-cb@6 { 4215 compatible = "qcom,fastrpc-compute-cb"; 4216 reg = <6>; 4217 iommus = <&apps_smmu 0x1966 0x0>, 4218 <&apps_smmu 0x0c06 0x20>, 4219 <&apps_smmu 0x19c6 0x10>; 4220 }; 4221 4222 compute-cb@7 { 4223 compatible = "qcom,fastrpc-compute-cb"; 4224 reg = <7>; 4225 iommus = <&apps_smmu 0x1967 0x0>, 4226 <&apps_smmu 0x0c07 0x20>, 4227 <&apps_smmu 0x19c7 0x10>; 4228 }; 4229 4230 compute-cb@8 { 4231 compatible = "qcom,fastrpc-compute-cb"; 4232 reg = <8>; 4233 iommus = <&apps_smmu 0x1968 0x0>, 4234 <&apps_smmu 0x0c08 0x20>, 4235 <&apps_smmu 0x19c8 0x10>; 4236 }; 4237 4238 /* note: secure cb9 in downstream */ 4239 }; 4240 }; 4241 }; 4242 }; 4243 4244 thermal-zones { 4245 aoss0-thermal { 4246 polling-delay-passive = <0>; 4247 polling-delay = <0>; 4248 thermal-sensors = <&tsens0 0>; 4249 4250 trips { 4251 thermal-engine-config { 4252 temperature = <125000>; 4253 hysteresis = <1000>; 4254 type = "passive"; 4255 }; 4256 4257 reset-mon-config { 4258 temperature = <115000>; 4259 hysteresis = <5000>; 4260 type = "passive"; 4261 }; 4262 }; 4263 }; 4264 4265 cpuss0-thermal { 4266 polling-delay-passive = <0>; 4267 polling-delay = <0>; 4268 thermal-sensors = <&tsens0 1>; 4269 4270 trips { 4271 thermal-engine-config { 4272 temperature = <125000>; 4273 hysteresis = <1000>; 4274 type = "passive"; 4275 }; 4276 4277 reset-mon-config { 4278 temperature = <115000>; 4279 hysteresis = <5000>; 4280 type = "passive"; 4281 }; 4282 }; 4283 }; 4284 4285 cpuss1-thermal { 4286 polling-delay-passive = <0>; 4287 polling-delay = <0>; 4288 thermal-sensors = <&tsens0 2>; 4289 4290 trips { 4291 thermal-engine-config { 4292 temperature = <125000>; 4293 hysteresis = <1000>; 4294 type = "passive"; 4295 }; 4296 4297 reset-mon-config { 4298 temperature = <115000>; 4299 hysteresis = <5000>; 4300 type = "passive"; 4301 }; 4302 }; 4303 }; 4304 4305 cpuss2-thermal { 4306 polling-delay-passive = <0>; 4307 polling-delay = <0>; 4308 thermal-sensors = <&tsens0 3>; 4309 4310 trips { 4311 thermal-engine-config { 4312 temperature = <125000>; 4313 hysteresis = <1000>; 4314 type = "passive"; 4315 }; 4316 4317 reset-mon-config { 4318 temperature = <115000>; 4319 hysteresis = <5000>; 4320 type = "passive"; 4321 }; 4322 }; 4323 }; 4324 4325 cpuss3-thermal { 4326 polling-delay-passive = <0>; 4327 polling-delay = <0>; 4328 thermal-sensors = <&tsens0 4>; 4329 4330 trips { 4331 thermal-engine-config { 4332 temperature = <125000>; 4333 hysteresis = <1000>; 4334 type = "passive"; 4335 }; 4336 4337 reset-mon-config { 4338 temperature = <115000>; 4339 hysteresis = <5000>; 4340 type = "passive"; 4341 }; 4342 }; 4343 }; 4344 4345 cpu3-top-thermal { 4346 polling-delay-passive = <0>; 4347 polling-delay = <0>; 4348 thermal-sensors = <&tsens0 5>; 4349 4350 trips { 4351 cpu3_top_alert0: trip-point0 { 4352 temperature = <90000>; 4353 hysteresis = <2000>; 4354 type = "passive"; 4355 }; 4356 4357 cpu3_top_alert1: trip-point1 { 4358 temperature = <95000>; 4359 hysteresis = <2000>; 4360 type = "passive"; 4361 }; 4362 4363 cpu3_top_crit: cpu-critical { 4364 temperature = <110000>; 4365 hysteresis = <1000>; 4366 type = "critical"; 4367 }; 4368 }; 4369 }; 4370 4371 cpu3-bottom-thermal { 4372 polling-delay-passive = <0>; 4373 polling-delay = <0>; 4374 thermal-sensors = <&tsens0 6>; 4375 4376 trips { 4377 cpu3_bottom_alert0: trip-point0 { 4378 temperature = <90000>; 4379 hysteresis = <2000>; 4380 type = "passive"; 4381 }; 4382 4383 cpu3_bottom_alert1: trip-point1 { 4384 temperature = <95000>; 4385 hysteresis = <2000>; 4386 type = "passive"; 4387 }; 4388 4389 cpu3_bottom_crit: cpu-critical { 4390 temperature = <110000>; 4391 hysteresis = <1000>; 4392 type = "critical"; 4393 }; 4394 }; 4395 }; 4396 4397 cpu4-top-thermal { 4398 polling-delay-passive = <0>; 4399 polling-delay = <0>; 4400 thermal-sensors = <&tsens0 7>; 4401 4402 trips { 4403 cpu4_top_alert0: trip-point0 { 4404 temperature = <90000>; 4405 hysteresis = <2000>; 4406 type = "passive"; 4407 }; 4408 4409 cpu4_top_alert1: trip-point1 { 4410 temperature = <95000>; 4411 hysteresis = <2000>; 4412 type = "passive"; 4413 }; 4414 4415 cpu4_top_crit: cpu-critical { 4416 temperature = <110000>; 4417 hysteresis = <1000>; 4418 type = "critical"; 4419 }; 4420 }; 4421 }; 4422 4423 cpu4-bottom-thermal { 4424 polling-delay-passive = <0>; 4425 polling-delay = <0>; 4426 thermal-sensors = <&tsens0 8>; 4427 4428 trips { 4429 cpu4_bottom_alert0: trip-point0 { 4430 temperature = <90000>; 4431 hysteresis = <2000>; 4432 type = "passive"; 4433 }; 4434 4435 cpu4_bottom_alert1: trip-point1 { 4436 temperature = <95000>; 4437 hysteresis = <2000>; 4438 type = "passive"; 4439 }; 4440 4441 cpu4_bottom_crit: cpu-critical { 4442 temperature = <110000>; 4443 hysteresis = <1000>; 4444 type = "critical"; 4445 }; 4446 }; 4447 }; 4448 4449 cpu5-top-thermal { 4450 polling-delay-passive = <0>; 4451 polling-delay = <0>; 4452 thermal-sensors = <&tsens0 9>; 4453 4454 trips { 4455 cpu5_top_alert0: trip-point0 { 4456 temperature = <90000>; 4457 hysteresis = <2000>; 4458 type = "passive"; 4459 }; 4460 4461 cpu5_top_alert1: trip-point1 { 4462 temperature = <95000>; 4463 hysteresis = <2000>; 4464 type = "passive"; 4465 }; 4466 4467 cpu5_top_crit: cpu-critical { 4468 temperature = <110000>; 4469 hysteresis = <1000>; 4470 type = "critical"; 4471 }; 4472 }; 4473 }; 4474 4475 cpu5-bottom-thermal { 4476 polling-delay-passive = <0>; 4477 polling-delay = <0>; 4478 thermal-sensors = <&tsens0 10>; 4479 4480 trips { 4481 cpu5_bottom_alert0: trip-point0 { 4482 temperature = <90000>; 4483 hysteresis = <2000>; 4484 type = "passive"; 4485 }; 4486 4487 cpu5_bottom_alert1: trip-point1 { 4488 temperature = <95000>; 4489 hysteresis = <2000>; 4490 type = "passive"; 4491 }; 4492 4493 cpu5_bottom_crit: cpu-critical { 4494 temperature = <110000>; 4495 hysteresis = <1000>; 4496 type = "critical"; 4497 }; 4498 }; 4499 }; 4500 4501 cpu6-top-thermal { 4502 polling-delay-passive = <0>; 4503 polling-delay = <0>; 4504 thermal-sensors = <&tsens0 11>; 4505 4506 trips { 4507 cpu6_top_alert0: trip-point0 { 4508 temperature = <90000>; 4509 hysteresis = <2000>; 4510 type = "passive"; 4511 }; 4512 4513 cpu6_top_alert1: trip-point1 { 4514 temperature = <95000>; 4515 hysteresis = <2000>; 4516 type = "passive"; 4517 }; 4518 4519 cpu6_top_crit: cpu-critical { 4520 temperature = <110000>; 4521 hysteresis = <1000>; 4522 type = "critical"; 4523 }; 4524 }; 4525 }; 4526 4527 cpu6-bottom-thermal { 4528 polling-delay-passive = <0>; 4529 polling-delay = <0>; 4530 thermal-sensors = <&tsens0 12>; 4531 4532 trips { 4533 cpu6_bottom_alert0: trip-point0 { 4534 temperature = <90000>; 4535 hysteresis = <2000>; 4536 type = "passive"; 4537 }; 4538 4539 cpu6_bottom_alert1: trip-point1 { 4540 temperature = <95000>; 4541 hysteresis = <2000>; 4542 type = "passive"; 4543 }; 4544 4545 cpu6_bottom_crit: cpu-critical { 4546 temperature = <110000>; 4547 hysteresis = <1000>; 4548 type = "critical"; 4549 }; 4550 }; 4551 }; 4552 4553 cpu7-top-thermal { 4554 polling-delay-passive = <0>; 4555 polling-delay = <0>; 4556 thermal-sensors = <&tsens0 13>; 4557 4558 trips { 4559 cpu7_top_alert0: trip-point0 { 4560 temperature = <90000>; 4561 hysteresis = <2000>; 4562 type = "passive"; 4563 }; 4564 4565 cpu7_top_alert1: trip-point1 { 4566 temperature = <95000>; 4567 hysteresis = <2000>; 4568 type = "passive"; 4569 }; 4570 4571 cpu7_top_crit: cpu-critical { 4572 temperature = <110000>; 4573 hysteresis = <1000>; 4574 type = "critical"; 4575 }; 4576 }; 4577 }; 4578 4579 cpu7-middle-thermal { 4580 polling-delay-passive = <0>; 4581 polling-delay = <0>; 4582 thermal-sensors = <&tsens0 14>; 4583 4584 trips { 4585 cpu7_middle_alert0: trip-point0 { 4586 temperature = <90000>; 4587 hysteresis = <2000>; 4588 type = "passive"; 4589 }; 4590 4591 cpu7_middle_alert1: trip-point1 { 4592 temperature = <95000>; 4593 hysteresis = <2000>; 4594 type = "passive"; 4595 }; 4596 4597 cpu7_middle_crit: cpu-critical { 4598 temperature = <110000>; 4599 hysteresis = <1000>; 4600 type = "critical"; 4601 }; 4602 }; 4603 }; 4604 4605 cpu7-bottom-thermal { 4606 polling-delay-passive = <0>; 4607 polling-delay = <0>; 4608 thermal-sensors = <&tsens0 15>; 4609 4610 trips { 4611 cpu7_bottom_alert0: trip-point0 { 4612 temperature = <90000>; 4613 hysteresis = <2000>; 4614 type = "passive"; 4615 }; 4616 4617 cpu7_bottom_alert1: trip-point1 { 4618 temperature = <95000>; 4619 hysteresis = <2000>; 4620 type = "passive"; 4621 }; 4622 4623 cpu7_bottom_crit: cpu-critical { 4624 temperature = <110000>; 4625 hysteresis = <1000>; 4626 type = "critical"; 4627 }; 4628 }; 4629 }; 4630 4631 aoss1-thermal { 4632 polling-delay-passive = <0>; 4633 polling-delay = <0>; 4634 thermal-sensors = <&tsens1 0>; 4635 4636 trips { 4637 thermal-engine-config { 4638 temperature = <125000>; 4639 hysteresis = <1000>; 4640 type = "passive"; 4641 }; 4642 4643 reset-mon-config { 4644 temperature = <115000>; 4645 hysteresis = <5000>; 4646 type = "passive"; 4647 }; 4648 }; 4649 }; 4650 4651 cpu0-thermal { 4652 polling-delay-passive = <0>; 4653 polling-delay = <0>; 4654 thermal-sensors = <&tsens1 1>; 4655 4656 trips { 4657 cpu0_alert0: trip-point0 { 4658 temperature = <90000>; 4659 hysteresis = <2000>; 4660 type = "passive"; 4661 }; 4662 4663 cpu0_alert1: trip-point1 { 4664 temperature = <95000>; 4665 hysteresis = <2000>; 4666 type = "passive"; 4667 }; 4668 4669 cpu0_crit: cpu-critical { 4670 temperature = <110000>; 4671 hysteresis = <1000>; 4672 type = "critical"; 4673 }; 4674 }; 4675 }; 4676 4677 cpu1-thermal { 4678 polling-delay-passive = <0>; 4679 polling-delay = <0>; 4680 thermal-sensors = <&tsens1 2>; 4681 4682 trips { 4683 cpu1_alert0: trip-point0 { 4684 temperature = <90000>; 4685 hysteresis = <2000>; 4686 type = "passive"; 4687 }; 4688 4689 cpu1_alert1: trip-point1 { 4690 temperature = <95000>; 4691 hysteresis = <2000>; 4692 type = "passive"; 4693 }; 4694 4695 cpu1_crit: cpu-critical { 4696 temperature = <110000>; 4697 hysteresis = <1000>; 4698 type = "critical"; 4699 }; 4700 }; 4701 }; 4702 4703 cpu2-thermal { 4704 polling-delay-passive = <0>; 4705 polling-delay = <0>; 4706 thermal-sensors = <&tsens1 3>; 4707 4708 trips { 4709 cpu2_alert0: trip-point0 { 4710 temperature = <90000>; 4711 hysteresis = <2000>; 4712 type = "passive"; 4713 }; 4714 4715 cpu2_alert1: trip-point1 { 4716 temperature = <95000>; 4717 hysteresis = <2000>; 4718 type = "passive"; 4719 }; 4720 4721 cpu2_crit: cpu-critical { 4722 temperature = <110000>; 4723 hysteresis = <1000>; 4724 type = "critical"; 4725 }; 4726 }; 4727 }; 4728 4729 cdsp0-thermal { 4730 polling-delay-passive = <10>; 4731 polling-delay = <0>; 4732 thermal-sensors = <&tsens2 4>; 4733 4734 trips { 4735 thermal-engine-config { 4736 temperature = <125000>; 4737 hysteresis = <1000>; 4738 type = "passive"; 4739 }; 4740 4741 thermal-hal-config { 4742 temperature = <125000>; 4743 hysteresis = <1000>; 4744 type = "passive"; 4745 }; 4746 4747 reset-mon-config { 4748 temperature = <115000>; 4749 hysteresis = <5000>; 4750 type = "passive"; 4751 }; 4752 4753 cdsp0_junction_config: junction-config { 4754 temperature = <95000>; 4755 hysteresis = <5000>; 4756 type = "passive"; 4757 }; 4758 }; 4759 }; 4760 4761 cdsp1-thermal { 4762 polling-delay-passive = <10>; 4763 polling-delay = <0>; 4764 thermal-sensors = <&tsens2 5>; 4765 4766 trips { 4767 thermal-engine-config { 4768 temperature = <125000>; 4769 hysteresis = <1000>; 4770 type = "passive"; 4771 }; 4772 4773 thermal-hal-config { 4774 temperature = <125000>; 4775 hysteresis = <1000>; 4776 type = "passive"; 4777 }; 4778 4779 reset-mon-config { 4780 temperature = <115000>; 4781 hysteresis = <5000>; 4782 type = "passive"; 4783 }; 4784 4785 cdsp1_junction_config: junction-config { 4786 temperature = <95000>; 4787 hysteresis = <5000>; 4788 type = "passive"; 4789 }; 4790 }; 4791 }; 4792 4793 cdsp2-thermal { 4794 polling-delay-passive = <10>; 4795 polling-delay = <0>; 4796 thermal-sensors = <&tsens2 6>; 4797 4798 trips { 4799 thermal-engine-config { 4800 temperature = <125000>; 4801 hysteresis = <1000>; 4802 type = "passive"; 4803 }; 4804 4805 thermal-hal-config { 4806 temperature = <125000>; 4807 hysteresis = <1000>; 4808 type = "passive"; 4809 }; 4810 4811 reset-mon-config { 4812 temperature = <115000>; 4813 hysteresis = <5000>; 4814 type = "passive"; 4815 }; 4816 4817 cdsp2_junction_config: junction-config { 4818 temperature = <95000>; 4819 hysteresis = <5000>; 4820 type = "passive"; 4821 }; 4822 }; 4823 }; 4824 4825 cdsp3-thermal { 4826 polling-delay-passive = <10>; 4827 polling-delay = <0>; 4828 thermal-sensors = <&tsens2 7>; 4829 4830 trips { 4831 thermal-engine-config { 4832 temperature = <125000>; 4833 hysteresis = <1000>; 4834 type = "passive"; 4835 }; 4836 4837 thermal-hal-config { 4838 temperature = <125000>; 4839 hysteresis = <1000>; 4840 type = "passive"; 4841 }; 4842 4843 reset-mon-config { 4844 temperature = <115000>; 4845 hysteresis = <5000>; 4846 type = "passive"; 4847 }; 4848 4849 cdsp3_junction_config: junction-config { 4850 temperature = <95000>; 4851 hysteresis = <5000>; 4852 type = "passive"; 4853 }; 4854 }; 4855 }; 4856 4857 video-thermal { 4858 polling-delay-passive = <0>; 4859 polling-delay = <0>; 4860 thermal-sensors = <&tsens1 8>; 4861 4862 trips { 4863 thermal-engine-config { 4864 temperature = <125000>; 4865 hysteresis = <1000>; 4866 type = "passive"; 4867 }; 4868 4869 reset-mon-config { 4870 temperature = <115000>; 4871 hysteresis = <5000>; 4872 type = "passive"; 4873 }; 4874 }; 4875 }; 4876 4877 mem-thermal { 4878 polling-delay-passive = <10>; 4879 polling-delay = <0>; 4880 thermal-sensors = <&tsens1 9>; 4881 4882 trips { 4883 thermal-engine-config { 4884 temperature = <125000>; 4885 hysteresis = <1000>; 4886 type = "passive"; 4887 }; 4888 4889 ddr_config0: ddr0-config { 4890 temperature = <90000>; 4891 hysteresis = <5000>; 4892 type = "passive"; 4893 }; 4894 4895 reset-mon-config { 4896 temperature = <115000>; 4897 hysteresis = <5000>; 4898 type = "passive"; 4899 }; 4900 }; 4901 }; 4902 4903 modem0-thermal { 4904 polling-delay-passive = <0>; 4905 polling-delay = <0>; 4906 thermal-sensors = <&tsens1 10>; 4907 4908 trips { 4909 thermal-engine-config { 4910 temperature = <125000>; 4911 hysteresis = <1000>; 4912 type = "passive"; 4913 }; 4914 4915 mdmss0_config0: mdmss0-config0 { 4916 temperature = <102000>; 4917 hysteresis = <3000>; 4918 type = "passive"; 4919 }; 4920 4921 mdmss0_config1: mdmss0-config1 { 4922 temperature = <105000>; 4923 hysteresis = <3000>; 4924 type = "passive"; 4925 }; 4926 4927 reset-mon-config { 4928 temperature = <115000>; 4929 hysteresis = <5000>; 4930 type = "passive"; 4931 }; 4932 }; 4933 }; 4934 4935 modem1-thermal { 4936 polling-delay-passive = <0>; 4937 polling-delay = <0>; 4938 thermal-sensors = <&tsens1 11>; 4939 4940 trips { 4941 thermal-engine-config { 4942 temperature = <125000>; 4943 hysteresis = <1000>; 4944 type = "passive"; 4945 }; 4946 4947 mdmss1_config0: mdmss1-config0 { 4948 temperature = <102000>; 4949 hysteresis = <3000>; 4950 type = "passive"; 4951 }; 4952 4953 mdmss1_config1: mdmss1-config1 { 4954 temperature = <105000>; 4955 hysteresis = <3000>; 4956 type = "passive"; 4957 }; 4958 4959 reset-mon-config { 4960 temperature = <115000>; 4961 hysteresis = <5000>; 4962 type = "passive"; 4963 }; 4964 }; 4965 }; 4966 4967 modem2-thermal { 4968 polling-delay-passive = <0>; 4969 polling-delay = <0>; 4970 thermal-sensors = <&tsens1 12>; 4971 4972 trips { 4973 thermal-engine-config { 4974 temperature = <125000>; 4975 hysteresis = <1000>; 4976 type = "passive"; 4977 }; 4978 4979 mdmss2_config0: mdmss2-config0 { 4980 temperature = <102000>; 4981 hysteresis = <3000>; 4982 type = "passive"; 4983 }; 4984 4985 mdmss2_config1: mdmss2-config1 { 4986 temperature = <105000>; 4987 hysteresis = <3000>; 4988 type = "passive"; 4989 }; 4990 4991 reset-mon-config { 4992 temperature = <115000>; 4993 hysteresis = <5000>; 4994 type = "passive"; 4995 }; 4996 }; 4997 }; 4998 4999 modem3-thermal { 5000 polling-delay-passive = <0>; 5001 polling-delay = <0>; 5002 thermal-sensors = <&tsens1 13>; 5003 5004 trips { 5005 thermal-engine-config { 5006 temperature = <125000>; 5007 hysteresis = <1000>; 5008 type = "passive"; 5009 }; 5010 5011 mdmss3_config0: mdmss3-config0 { 5012 temperature = <102000>; 5013 hysteresis = <3000>; 5014 type = "passive"; 5015 }; 5016 5017 mdmss3_config1: mdmss3-config1 { 5018 temperature = <105000>; 5019 hysteresis = <3000>; 5020 type = "passive"; 5021 }; 5022 5023 reset-mon-config { 5024 temperature = <115000>; 5025 hysteresis = <5000>; 5026 type = "passive"; 5027 }; 5028 }; 5029 }; 5030 5031 camera0-thermal { 5032 polling-delay-passive = <0>; 5033 polling-delay = <0>; 5034 thermal-sensors = <&tsens1 14>; 5035 5036 trips { 5037 thermal-engine-config { 5038 temperature = <125000>; 5039 hysteresis = <1000>; 5040 type = "passive"; 5041 }; 5042 5043 reset-mon-config { 5044 temperature = <115000>; 5045 hysteresis = <5000>; 5046 type = "passive"; 5047 }; 5048 }; 5049 }; 5050 5051 camera1-thermal { 5052 polling-delay-passive = <0>; 5053 polling-delay = <0>; 5054 thermal-sensors = <&tsens1 15>; 5055 5056 trips { 5057 thermal-engine-config { 5058 temperature = <125000>; 5059 hysteresis = <1000>; 5060 type = "passive"; 5061 }; 5062 5063 reset-mon-config { 5064 temperature = <115000>; 5065 hysteresis = <5000>; 5066 type = "passive"; 5067 }; 5068 }; 5069 }; 5070 5071 aoss2-thermal { 5072 polling-delay-passive = <0>; 5073 polling-delay = <0>; 5074 thermal-sensors = <&tsens2 0>; 5075 5076 trips { 5077 thermal-engine-config { 5078 temperature = <125000>; 5079 hysteresis = <1000>; 5080 type = "passive"; 5081 }; 5082 5083 reset-mon-config { 5084 temperature = <115000>; 5085 hysteresis = <5000>; 5086 type = "passive"; 5087 }; 5088 }; 5089 }; 5090 5091 gpuss-0-thermal { 5092 polling-delay-passive = <10>; 5093 polling-delay = <0>; 5094 thermal-sensors = <&tsens2 1>; 5095 5096 trips { 5097 thermal-engine-config { 5098 temperature = <125000>; 5099 hysteresis = <1000>; 5100 type = "passive"; 5101 }; 5102 5103 thermal-hal-config { 5104 temperature = <125000>; 5105 hysteresis = <1000>; 5106 type = "passive"; 5107 }; 5108 5109 reset-mon-config { 5110 temperature = <115000>; 5111 hysteresis = <5000>; 5112 type = "passive"; 5113 }; 5114 5115 gpu0_junction_config: junction-config { 5116 temperature = <95000>; 5117 hysteresis = <5000>; 5118 type = "passive"; 5119 }; 5120 }; 5121 }; 5122 5123 gpuss-1-thermal { 5124 polling-delay-passive = <10>; 5125 polling-delay = <0>; 5126 thermal-sensors = <&tsens2 2>; 5127 5128 trips { 5129 thermal-engine-config { 5130 temperature = <125000>; 5131 hysteresis = <1000>; 5132 type = "passive"; 5133 }; 5134 5135 thermal-hal-config { 5136 temperature = <125000>; 5137 hysteresis = <1000>; 5138 type = "passive"; 5139 }; 5140 5141 reset-mon-config { 5142 temperature = <115000>; 5143 hysteresis = <5000>; 5144 type = "passive"; 5145 }; 5146 5147 gpu1_junction_config: junction-config { 5148 temperature = <95000>; 5149 hysteresis = <5000>; 5150 type = "passive"; 5151 }; 5152 }; 5153 }; 5154 5155 gpuss-2-thermal { 5156 polling-delay-passive = <10>; 5157 polling-delay = <0>; 5158 thermal-sensors = <&tsens2 3>; 5159 5160 trips { 5161 thermal-engine-config { 5162 temperature = <125000>; 5163 hysteresis = <1000>; 5164 type = "passive"; 5165 }; 5166 5167 thermal-hal-config { 5168 temperature = <125000>; 5169 hysteresis = <1000>; 5170 type = "passive"; 5171 }; 5172 5173 reset-mon-config { 5174 temperature = <115000>; 5175 hysteresis = <5000>; 5176 type = "passive"; 5177 }; 5178 5179 gpu2_junction_config: junction-config { 5180 temperature = <95000>; 5181 hysteresis = <5000>; 5182 type = "passive"; 5183 }; 5184 }; 5185 }; 5186 5187 gpuss-3-thermal { 5188 polling-delay-passive = <10>; 5189 polling-delay = <0>; 5190 thermal-sensors = <&tsens2 4>; 5191 5192 trips { 5193 thermal-engine-config { 5194 temperature = <125000>; 5195 hysteresis = <1000>; 5196 type = "passive"; 5197 }; 5198 5199 thermal-hal-config { 5200 temperature = <125000>; 5201 hysteresis = <1000>; 5202 type = "passive"; 5203 }; 5204 5205 reset-mon-config { 5206 temperature = <115000>; 5207 hysteresis = <5000>; 5208 type = "passive"; 5209 }; 5210 5211 gpu3_junction_config: junction-config { 5212 temperature = <95000>; 5213 hysteresis = <5000>; 5214 type = "passive"; 5215 }; 5216 }; 5217 }; 5218 5219 gpuss-4-thermal { 5220 polling-delay-passive = <10>; 5221 polling-delay = <0>; 5222 thermal-sensors = <&tsens2 5>; 5223 5224 trips { 5225 thermal-engine-config { 5226 temperature = <125000>; 5227 hysteresis = <1000>; 5228 type = "passive"; 5229 }; 5230 5231 thermal-hal-config { 5232 temperature = <125000>; 5233 hysteresis = <1000>; 5234 type = "passive"; 5235 }; 5236 5237 reset-mon-config { 5238 temperature = <115000>; 5239 hysteresis = <5000>; 5240 type = "passive"; 5241 }; 5242 5243 gpu4_junction_config: junction-config { 5244 temperature = <95000>; 5245 hysteresis = <5000>; 5246 type = "passive"; 5247 }; 5248 }; 5249 }; 5250 5251 gpuss-5-thermal { 5252 polling-delay-passive = <10>; 5253 polling-delay = <0>; 5254 thermal-sensors = <&tsens2 6>; 5255 5256 trips { 5257 thermal-engine-config { 5258 temperature = <125000>; 5259 hysteresis = <1000>; 5260 type = "passive"; 5261 }; 5262 5263 thermal-hal-config { 5264 temperature = <125000>; 5265 hysteresis = <1000>; 5266 type = "passive"; 5267 }; 5268 5269 reset-mon-config { 5270 temperature = <115000>; 5271 hysteresis = <5000>; 5272 type = "passive"; 5273 }; 5274 5275 gpu5_junction_config: junction-config { 5276 temperature = <95000>; 5277 hysteresis = <5000>; 5278 type = "passive"; 5279 }; 5280 }; 5281 }; 5282 5283 gpuss-6-thermal { 5284 polling-delay-passive = <10>; 5285 polling-delay = <0>; 5286 thermal-sensors = <&tsens2 7>; 5287 5288 trips { 5289 thermal-engine-config { 5290 temperature = <125000>; 5291 hysteresis = <1000>; 5292 type = "passive"; 5293 }; 5294 5295 thermal-hal-config { 5296 temperature = <125000>; 5297 hysteresis = <1000>; 5298 type = "passive"; 5299 }; 5300 5301 reset-mon-config { 5302 temperature = <115000>; 5303 hysteresis = <5000>; 5304 type = "passive"; 5305 }; 5306 5307 gpu6_junction_config: junction-config { 5308 temperature = <95000>; 5309 hysteresis = <5000>; 5310 type = "passive"; 5311 }; 5312 }; 5313 }; 5314 5315 gpuss-7-thermal { 5316 polling-delay-passive = <10>; 5317 polling-delay = <0>; 5318 thermal-sensors = <&tsens2 8>; 5319 5320 trips { 5321 thermal-engine-config { 5322 temperature = <125000>; 5323 hysteresis = <1000>; 5324 type = "passive"; 5325 }; 5326 5327 thermal-hal-config { 5328 temperature = <125000>; 5329 hysteresis = <1000>; 5330 type = "passive"; 5331 }; 5332 5333 reset-mon-config { 5334 temperature = <115000>; 5335 hysteresis = <5000>; 5336 type = "passive"; 5337 }; 5338 5339 gpu7_junction_config: junction-config { 5340 temperature = <95000>; 5341 hysteresis = <5000>; 5342 type = "passive"; 5343 }; 5344 }; 5345 }; 5346 }; 5347 5348 timer { 5349 compatible = "arm,armv8-timer"; 5350 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5351 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5352 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5353 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5354 }; 5355}; 5356