1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8550-gcc.h> 8#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 9#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,gpr.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/thermal/thermal.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 }; 40 41 bi_tcxo_div2: bi-tcxo-div2-clk { 42 #clock-cells = <0>; 43 compatible = "fixed-factor-clock"; 44 clocks = <&rpmhcc RPMH_CXO_CLK>; 45 clock-mult = <1>; 46 clock-div = <2>; 47 }; 48 49 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 50 #clock-cells = <0>; 51 compatible = "fixed-factor-clock"; 52 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 53 clock-mult = <1>; 54 clock-div = <2>; 55 }; 56 57 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 }; 61 }; 62 63 cpus { 64 #address-cells = <2>; 65 #size-cells = <0>; 66 67 CPU0: cpu@0 { 68 device_type = "cpu"; 69 compatible = "qcom,kryo"; 70 reg = <0 0>; 71 enable-method = "psci"; 72 next-level-cache = <&L2_0>; 73 power-domains = <&CPU_PD0>; 74 power-domain-names = "psci"; 75 qcom,freq-domain = <&cpufreq_hw 0>; 76 capacity-dmips-mhz = <1024>; 77 dynamic-power-coefficient = <100>; 78 #cooling-cells = <2>; 79 L2_0: l2-cache { 80 compatible = "cache"; 81 cache-level = <2>; 82 next-level-cache = <&L3_0>; 83 L3_0: l3-cache { 84 compatible = "cache"; 85 cache-level = <3>; 86 }; 87 }; 88 }; 89 90 CPU1: cpu@100 { 91 device_type = "cpu"; 92 compatible = "qcom,kryo"; 93 reg = <0 0x100>; 94 enable-method = "psci"; 95 next-level-cache = <&L2_100>; 96 power-domains = <&CPU_PD1>; 97 power-domain-names = "psci"; 98 qcom,freq-domain = <&cpufreq_hw 0>; 99 capacity-dmips-mhz = <1024>; 100 dynamic-power-coefficient = <100>; 101 #cooling-cells = <2>; 102 L2_100: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 next-level-cache = <&L3_0>; 106 }; 107 }; 108 109 CPU2: cpu@200 { 110 device_type = "cpu"; 111 compatible = "qcom,kryo"; 112 reg = <0 0x200>; 113 enable-method = "psci"; 114 next-level-cache = <&L2_200>; 115 power-domains = <&CPU_PD2>; 116 power-domain-names = "psci"; 117 qcom,freq-domain = <&cpufreq_hw 0>; 118 capacity-dmips-mhz = <1024>; 119 dynamic-power-coefficient = <100>; 120 #cooling-cells = <2>; 121 L2_200: l2-cache { 122 compatible = "cache"; 123 cache-level = <2>; 124 next-level-cache = <&L3_0>; 125 }; 126 }; 127 128 CPU3: cpu@300 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo"; 131 reg = <0 0x300>; 132 enable-method = "psci"; 133 next-level-cache = <&L2_300>; 134 power-domains = <&CPU_PD3>; 135 power-domain-names = "psci"; 136 qcom,freq-domain = <&cpufreq_hw 1>; 137 capacity-dmips-mhz = <1792>; 138 dynamic-power-coefficient = <270>; 139 #cooling-cells = <2>; 140 L2_300: l2-cache { 141 compatible = "cache"; 142 cache-level = <2>; 143 next-level-cache = <&L3_0>; 144 }; 145 }; 146 147 CPU4: cpu@400 { 148 device_type = "cpu"; 149 compatible = "qcom,kryo"; 150 reg = <0 0x400>; 151 enable-method = "psci"; 152 next-level-cache = <&L2_400>; 153 power-domains = <&CPU_PD4>; 154 power-domain-names = "psci"; 155 qcom,freq-domain = <&cpufreq_hw 1>; 156 capacity-dmips-mhz = <1792>; 157 dynamic-power-coefficient = <270>; 158 #cooling-cells = <2>; 159 L2_400: l2-cache { 160 compatible = "cache"; 161 cache-level = <2>; 162 next-level-cache = <&L3_0>; 163 }; 164 }; 165 166 CPU5: cpu@500 { 167 device_type = "cpu"; 168 compatible = "qcom,kryo"; 169 reg = <0 0x500>; 170 enable-method = "psci"; 171 next-level-cache = <&L2_500>; 172 power-domains = <&CPU_PD5>; 173 power-domain-names = "psci"; 174 qcom,freq-domain = <&cpufreq_hw 1>; 175 capacity-dmips-mhz = <1792>; 176 dynamic-power-coefficient = <270>; 177 #cooling-cells = <2>; 178 L2_500: l2-cache { 179 compatible = "cache"; 180 cache-level = <2>; 181 next-level-cache = <&L3_0>; 182 }; 183 }; 184 185 CPU6: cpu@600 { 186 device_type = "cpu"; 187 compatible = "qcom,kryo"; 188 reg = <0 0x600>; 189 enable-method = "psci"; 190 next-level-cache = <&L2_600>; 191 power-domains = <&CPU_PD6>; 192 power-domain-names = "psci"; 193 qcom,freq-domain = <&cpufreq_hw 1>; 194 capacity-dmips-mhz = <1792>; 195 dynamic-power-coefficient = <270>; 196 #cooling-cells = <2>; 197 L2_600: l2-cache { 198 compatible = "cache"; 199 cache-level = <2>; 200 next-level-cache = <&L3_0>; 201 }; 202 }; 203 204 CPU7: cpu@700 { 205 device_type = "cpu"; 206 compatible = "qcom,kryo"; 207 reg = <0 0x700>; 208 enable-method = "psci"; 209 next-level-cache = <&L2_700>; 210 power-domains = <&CPU_PD7>; 211 power-domain-names = "psci"; 212 qcom,freq-domain = <&cpufreq_hw 2>; 213 capacity-dmips-mhz = <1894>; 214 dynamic-power-coefficient = <588>; 215 #cooling-cells = <2>; 216 L2_700: l2-cache { 217 compatible = "cache"; 218 cache-level = <2>; 219 next-level-cache = <&L3_0>; 220 }; 221 }; 222 223 cpu-map { 224 cluster0 { 225 core0 { 226 cpu = <&CPU0>; 227 }; 228 229 core1 { 230 cpu = <&CPU1>; 231 }; 232 233 core2 { 234 cpu = <&CPU2>; 235 }; 236 237 core3 { 238 cpu = <&CPU3>; 239 }; 240 241 core4 { 242 cpu = <&CPU4>; 243 }; 244 245 core5 { 246 cpu = <&CPU5>; 247 }; 248 249 core6 { 250 cpu = <&CPU6>; 251 }; 252 253 core7 { 254 cpu = <&CPU7>; 255 }; 256 }; 257 }; 258 259 idle-states { 260 entry-method = "psci"; 261 262 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 263 compatible = "arm,idle-state"; 264 idle-state-name = "silver-rail-power-collapse"; 265 arm,psci-suspend-param = <0x40000004>; 266 entry-latency-us = <800>; 267 exit-latency-us = <750>; 268 min-residency-us = <4090>; 269 local-timer-stop; 270 }; 271 272 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 273 compatible = "arm,idle-state"; 274 idle-state-name = "gold-rail-power-collapse"; 275 arm,psci-suspend-param = <0x40000004>; 276 entry-latency-us = <600>; 277 exit-latency-us = <1550>; 278 min-residency-us = <4791>; 279 local-timer-stop; 280 }; 281 }; 282 283 domain-idle-states { 284 CLUSTER_SLEEP_0: cluster-sleep-0 { 285 compatible = "domain-idle-state"; 286 arm,psci-suspend-param = <0x41000044>; 287 entry-latency-us = <1050>; 288 exit-latency-us = <2500>; 289 min-residency-us = <5309>; 290 }; 291 292 CLUSTER_SLEEP_1: cluster-sleep-1 { 293 compatible = "domain-idle-state"; 294 arm,psci-suspend-param = <0x4100c344>; 295 entry-latency-us = <2700>; 296 exit-latency-us = <3500>; 297 min-residency-us = <13959>; 298 }; 299 }; 300 }; 301 302 firmware { 303 scm: scm { 304 compatible = "qcom,scm-sm8550", "qcom,scm"; 305 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 306 }; 307 }; 308 309 clk_virt: interconnect-0 { 310 compatible = "qcom,sm8550-clk-virt"; 311 #interconnect-cells = <2>; 312 qcom,bcm-voters = <&apps_bcm_voter>; 313 }; 314 315 mc_virt: interconnect-1 { 316 compatible = "qcom,sm8550-mc-virt"; 317 #interconnect-cells = <2>; 318 qcom,bcm-voters = <&apps_bcm_voter>; 319 }; 320 321 memory@a0000000 { 322 device_type = "memory"; 323 /* We expect the bootloader to fill in the size */ 324 reg = <0 0xa0000000 0 0>; 325 }; 326 327 pmu { 328 compatible = "arm,armv8-pmuv3"; 329 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 330 }; 331 332 psci { 333 compatible = "arm,psci-1.0"; 334 method = "smc"; 335 336 CPU_PD0: power-domain-cpu0 { 337 #power-domain-cells = <0>; 338 power-domains = <&CLUSTER_PD>; 339 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 340 }; 341 342 CPU_PD1: power-domain-cpu1 { 343 #power-domain-cells = <0>; 344 power-domains = <&CLUSTER_PD>; 345 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 346 }; 347 348 CPU_PD2: power-domain-cpu2 { 349 #power-domain-cells = <0>; 350 power-domains = <&CLUSTER_PD>; 351 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 352 }; 353 354 CPU_PD3: power-domain-cpu3 { 355 #power-domain-cells = <0>; 356 power-domains = <&CLUSTER_PD>; 357 domain-idle-states = <&BIG_CPU_SLEEP_0>; 358 }; 359 360 CPU_PD4: power-domain-cpu4 { 361 #power-domain-cells = <0>; 362 power-domains = <&CLUSTER_PD>; 363 domain-idle-states = <&BIG_CPU_SLEEP_0>; 364 }; 365 366 CPU_PD5: power-domain-cpu5 { 367 #power-domain-cells = <0>; 368 power-domains = <&CLUSTER_PD>; 369 domain-idle-states = <&BIG_CPU_SLEEP_0>; 370 }; 371 372 CPU_PD6: power-domain-cpu6 { 373 #power-domain-cells = <0>; 374 power-domains = <&CLUSTER_PD>; 375 domain-idle-states = <&BIG_CPU_SLEEP_0>; 376 }; 377 378 CPU_PD7: power-domain-cpu7 { 379 #power-domain-cells = <0>; 380 power-domains = <&CLUSTER_PD>; 381 domain-idle-states = <&BIG_CPU_SLEEP_0>; 382 }; 383 384 CLUSTER_PD: power-domain-cluster { 385 #power-domain-cells = <0>; 386 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 387 }; 388 }; 389 390 reserved_memory: reserved-memory { 391 #address-cells = <2>; 392 #size-cells = <2>; 393 ranges; 394 395 hyp_mem: hyp-region@80000000 { 396 reg = <0 0x80000000 0 0xa00000>; 397 no-map; 398 }; 399 400 cpusys_vm_mem: cpusys-vm-region@80a00000 { 401 reg = <0 0x80a00000 0 0x400000>; 402 no-map; 403 }; 404 405 hyp_tags_mem: hyp-tags-region@80e00000 { 406 reg = <0 0x80e00000 0 0x3d0000>; 407 no-map; 408 }; 409 410 xbl_sc_mem: xbl-sc-region@d8100000 { 411 reg = <0 0xd8100000 0 0x40000>; 412 no-map; 413 }; 414 415 416 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 417 reg = <0 0x811d0000 0 0x30000>; 418 no-map; 419 }; 420 421 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 422 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 423 reg = <0 0x81a00000 0 0x260000>; 424 no-map; 425 }; 426 427 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 428 compatible = "qcom,cmd-db"; 429 reg = <0 0x81c60000 0 0x20000>; 430 no-map; 431 }; 432 433 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 434 aop_config_merged_mem: aop-config-merged-region@81c80000 { 435 reg = <0 0x81c80000 0 0x74000>; 436 no-map; 437 }; 438 439 /* secdata region can be reused by apps */ 440 smem: smem@81d00000 { 441 compatible = "qcom,smem"; 442 reg = <0 0x81d00000 0 0x200000>; 443 hwlocks = <&tcsr_mutex 3>; 444 no-map; 445 }; 446 447 adsp_mhi_mem: adsp-mhi-region@81f00000 { 448 reg = <0 0x81f00000 0 0x20000>; 449 no-map; 450 }; 451 452 global_sync_mem: global-sync-region@82600000 { 453 reg = <0 0x82600000 0 0x100000>; 454 no-map; 455 }; 456 457 tz_stat_mem: tz-stat-region@82700000 { 458 reg = <0 0x82700000 0 0x100000>; 459 no-map; 460 }; 461 462 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 463 reg = <0 0x82800000 0 0x4600000>; 464 no-map; 465 }; 466 467 mpss_mem: mpss-region@8a800000 { 468 reg = <0 0x8a800000 0 0x10800000>; 469 no-map; 470 }; 471 472 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 473 reg = <0 0x9b000000 0 0x80000>; 474 no-map; 475 }; 476 477 ipa_fw_mem: ipa-fw-region@9b080000 { 478 reg = <0 0x9b080000 0 0x10000>; 479 no-map; 480 }; 481 482 ipa_gsi_mem: ipa-gsi-region@9b090000 { 483 reg = <0 0x9b090000 0 0xa000>; 484 no-map; 485 }; 486 487 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 488 reg = <0 0x9b09a000 0 0x2000>; 489 no-map; 490 }; 491 492 spss_region_mem: spss-region@9b100000 { 493 reg = <0 0x9b100000 0 0x180000>; 494 no-map; 495 }; 496 497 /* First part of the "SPU secure shared memory" region */ 498 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 499 reg = <0 0x9b280000 0 0x60000>; 500 no-map; 501 }; 502 503 /* Second part of the "SPU secure shared memory" region */ 504 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 505 reg = <0 0x9b2e0000 0 0x20000>; 506 no-map; 507 }; 508 509 camera_mem: camera-region@9b300000 { 510 reg = <0 0x9b300000 0 0x800000>; 511 no-map; 512 }; 513 514 video_mem: video-region@9bb00000 { 515 reg = <0 0x9bb00000 0 0x700000>; 516 no-map; 517 }; 518 519 cvp_mem: cvp-region@9c200000 { 520 reg = <0 0x9c200000 0 0x700000>; 521 no-map; 522 }; 523 524 cdsp_mem: cdsp-region@9c900000 { 525 reg = <0 0x9c900000 0 0x2000000>; 526 no-map; 527 }; 528 529 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 530 reg = <0 0x9e900000 0 0x80000>; 531 no-map; 532 }; 533 534 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 535 reg = <0 0x9e980000 0 0x80000>; 536 no-map; 537 }; 538 539 adspslpi_mem: adspslpi-region@9ea00000 { 540 reg = <0 0x9ea00000 0 0x4080000>; 541 no-map; 542 }; 543 544 /* uefi region can be reused by apps */ 545 546 /* Linux kernel image is loaded at 0xa8000000 */ 547 548 rmtfs_mem: rmtfs-region@d4a80000 { 549 compatible = "qcom,rmtfs-mem"; 550 reg = <0x0 0xd4a80000 0x0 0x280000>; 551 no-map; 552 553 qcom,client-id = <1>; 554 qcom,vmid = <15>; 555 }; 556 557 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 558 reg = <0 0xd4d00000 0 0x3300000>; 559 no-map; 560 }; 561 562 tz_reserved_mem: tz-reserved-region@d8000000 { 563 reg = <0 0xd8000000 0 0x100000>; 564 no-map; 565 }; 566 567 cpucp_fw_mem: cpucp-fw-region@d8140000 { 568 reg = <0 0xd8140000 0 0x1c0000>; 569 no-map; 570 }; 571 572 qtee_mem: qtee-region@d8300000 { 573 reg = <0 0xd8300000 0 0x500000>; 574 no-map; 575 }; 576 577 ta_mem: ta-region@d8800000 { 578 reg = <0 0xd8800000 0 0x8a00000>; 579 no-map; 580 }; 581 582 tz_tags_mem: tz-tags-region@e1200000 { 583 reg = <0 0xe1200000 0 0x2740000>; 584 no-map; 585 }; 586 587 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 588 reg = <0 0xe6440000 0 0x279000>; 589 no-map; 590 }; 591 592 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 593 reg = <0 0xf3600000 0 0x4aee000>; 594 no-map; 595 }; 596 597 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 598 reg = <0 0xf80ee000 0 0x1000>; 599 no-map; 600 }; 601 602 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 603 reg = <0 0xf80ef000 0 0x9000>; 604 no-map; 605 }; 606 607 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 608 reg = <0 0xf80f8000 0 0x4000>; 609 no-map; 610 }; 611 612 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 613 reg = <0 0xf80fc000 0 0x4000>; 614 no-map; 615 }; 616 617 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 618 reg = <0 0xf8100000 0 0x100000>; 619 no-map; 620 }; 621 622 oem_vm_mem: oem-vm-region@f8400000 { 623 reg = <0 0xf8400000 0 0x4800000>; 624 no-map; 625 }; 626 627 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 628 reg = <0 0xfcc00000 0 0x4000>; 629 no-map; 630 }; 631 632 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 633 reg = <0 0xfcc04000 0 0x100000>; 634 no-map; 635 }; 636 637 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 638 reg = <0 0xfce00000 0 0x2900000>; 639 no-map; 640 }; 641 642 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 643 reg = <0 0xff700000 0 0x100000>; 644 no-map; 645 }; 646 }; 647 648 smp2p-adsp { 649 compatible = "qcom,smp2p"; 650 qcom,smem = <443>, <429>; 651 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 652 IPCC_MPROC_SIGNAL_SMP2P 653 IRQ_TYPE_EDGE_RISING>; 654 mboxes = <&ipcc IPCC_CLIENT_LPASS 655 IPCC_MPROC_SIGNAL_SMP2P>; 656 657 qcom,local-pid = <0>; 658 qcom,remote-pid = <2>; 659 660 smp2p_adsp_out: master-kernel { 661 qcom,entry-name = "master-kernel"; 662 #qcom,smem-state-cells = <1>; 663 }; 664 665 smp2p_adsp_in: slave-kernel { 666 qcom,entry-name = "slave-kernel"; 667 interrupt-controller; 668 #interrupt-cells = <2>; 669 }; 670 }; 671 672 smp2p-cdsp { 673 compatible = "qcom,smp2p"; 674 qcom,smem = <94>, <432>; 675 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 676 IPCC_MPROC_SIGNAL_SMP2P 677 IRQ_TYPE_EDGE_RISING>; 678 mboxes = <&ipcc IPCC_CLIENT_CDSP 679 IPCC_MPROC_SIGNAL_SMP2P>; 680 681 qcom,local-pid = <0>; 682 qcom,remote-pid = <5>; 683 684 smp2p_cdsp_out: master-kernel { 685 qcom,entry-name = "master-kernel"; 686 #qcom,smem-state-cells = <1>; 687 }; 688 689 smp2p_cdsp_in: slave-kernel { 690 qcom,entry-name = "slave-kernel"; 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 }; 694 }; 695 696 smp2p-modem { 697 compatible = "qcom,smp2p"; 698 qcom,smem = <435>, <428>; 699 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 700 IPCC_MPROC_SIGNAL_SMP2P 701 IRQ_TYPE_EDGE_RISING>; 702 mboxes = <&ipcc IPCC_CLIENT_MPSS 703 IPCC_MPROC_SIGNAL_SMP2P>; 704 705 qcom,local-pid = <0>; 706 qcom,remote-pid = <1>; 707 708 smp2p_modem_out: master-kernel { 709 qcom,entry-name = "master-kernel"; 710 #qcom,smem-state-cells = <1>; 711 }; 712 713 smp2p_modem_in: slave-kernel { 714 qcom,entry-name = "slave-kernel"; 715 interrupt-controller; 716 #interrupt-cells = <2>; 717 }; 718 719 ipa_smp2p_out: ipa-ap-to-modem { 720 qcom,entry-name = "ipa"; 721 #qcom,smem-state-cells = <1>; 722 }; 723 724 ipa_smp2p_in: ipa-modem-to-ap { 725 qcom,entry-name = "ipa"; 726 interrupt-controller; 727 #interrupt-cells = <2>; 728 }; 729 }; 730 731 soc: soc@0 { 732 compatible = "simple-bus"; 733 ranges = <0 0 0 0 0x10 0>; 734 dma-ranges = <0 0 0 0 0x10 0>; 735 736 #address-cells = <2>; 737 #size-cells = <2>; 738 739 gcc: clock-controller@100000 { 740 compatible = "qcom,sm8550-gcc"; 741 reg = <0 0x00100000 0 0x1f4200>; 742 #clock-cells = <1>; 743 #reset-cells = <1>; 744 #power-domain-cells = <1>; 745 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 746 <&pcie0_phy>, 747 <&pcie1_phy>, 748 <&pcie_1_phy_aux_clk>, 749 <&ufs_mem_phy 0>, 750 <&ufs_mem_phy 1>, 751 <&ufs_mem_phy 2>, 752 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 753 }; 754 755 ipcc: mailbox@408000 { 756 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 757 reg = <0 0x00408000 0 0x1000>; 758 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 759 interrupt-controller; 760 #interrupt-cells = <3>; 761 #mbox-cells = <2>; 762 }; 763 764 gpi_dma2: dma-controller@800000 { 765 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 766 #dma-cells = <3>; 767 reg = <0 0x00800000 0 0x60000>; 768 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 780 dma-channels = <12>; 781 dma-channel-mask = <0x3e>; 782 iommus = <&apps_smmu 0x436 0>; 783 status = "disabled"; 784 }; 785 786 qupv3_id_1: geniqup@8c0000 { 787 compatible = "qcom,geni-se-qup"; 788 reg = <0 0x008c0000 0 0x2000>; 789 ranges; 790 clock-names = "m-ahb", "s-ahb"; 791 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 792 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 793 iommus = <&apps_smmu 0x423 0>; 794 #address-cells = <2>; 795 #size-cells = <2>; 796 status = "disabled"; 797 798 i2c8: i2c@880000 { 799 compatible = "qcom,geni-i2c"; 800 reg = <0 0x00880000 0 0x4000>; 801 clock-names = "se"; 802 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&qup_i2c8_data_clk>; 805 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 809 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 810 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 811 interconnect-names = "qup-core", "qup-config", "qup-memory"; 812 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 813 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 814 dma-names = "tx", "rx"; 815 status = "disabled"; 816 }; 817 818 spi8: spi@880000 { 819 compatible = "qcom,geni-spi"; 820 reg = <0 0x00880000 0 0x4000>; 821 clock-names = "se"; 822 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 823 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 824 pinctrl-names = "default"; 825 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 826 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 827 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 828 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 829 interconnect-names = "qup-core", "qup-config", "qup-memory"; 830 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 831 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 832 dma-names = "tx", "rx"; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 status = "disabled"; 836 }; 837 838 i2c9: i2c@884000 { 839 compatible = "qcom,geni-i2c"; 840 reg = <0 0x00884000 0 0x4000>; 841 clock-names = "se"; 842 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&qup_i2c9_data_clk>; 845 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 849 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 850 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 851 interconnect-names = "qup-core", "qup-config", "qup-memory"; 852 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 853 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 854 dma-names = "tx", "rx"; 855 status = "disabled"; 856 }; 857 858 spi9: spi@884000 { 859 compatible = "qcom,geni-spi"; 860 reg = <0 0x00884000 0 0x4000>; 861 clock-names = "se"; 862 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 863 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 864 pinctrl-names = "default"; 865 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 866 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 867 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 868 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 869 interconnect-names = "qup-core", "qup-config", "qup-memory"; 870 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 871 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 872 dma-names = "tx", "rx"; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 status = "disabled"; 876 }; 877 878 i2c10: i2c@888000 { 879 compatible = "qcom,geni-i2c"; 880 reg = <0 0x00888000 0 0x4000>; 881 clock-names = "se"; 882 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 883 pinctrl-names = "default"; 884 pinctrl-0 = <&qup_i2c10_data_clk>; 885 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 886 #address-cells = <1>; 887 #size-cells = <0>; 888 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 889 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 890 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 891 interconnect-names = "qup-core", "qup-config", "qup-memory"; 892 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 893 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 894 dma-names = "tx", "rx"; 895 status = "disabled"; 896 }; 897 898 spi10: spi@888000 { 899 compatible = "qcom,geni-spi"; 900 reg = <0 0x00888000 0 0x4000>; 901 clock-names = "se"; 902 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 903 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 904 pinctrl-names = "default"; 905 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 906 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 907 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 908 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 909 interconnect-names = "qup-core", "qup-config", "qup-memory"; 910 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 911 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 912 dma-names = "tx", "rx"; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 status = "disabled"; 916 }; 917 918 i2c11: i2c@88c000 { 919 compatible = "qcom,geni-i2c"; 920 reg = <0 0x0088c000 0 0x4000>; 921 clock-names = "se"; 922 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 923 pinctrl-names = "default"; 924 pinctrl-0 = <&qup_i2c11_data_clk>; 925 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 929 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 930 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 931 interconnect-names = "qup-core", "qup-config", "qup-memory"; 932 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 933 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 934 dma-names = "tx", "rx"; 935 status = "disabled"; 936 }; 937 938 spi11: spi@88c000 { 939 compatible = "qcom,geni-spi"; 940 reg = <0 0x0088c000 0 0x4000>; 941 clock-names = "se"; 942 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 943 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 944 pinctrl-names = "default"; 945 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 946 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 947 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 948 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 949 interconnect-names = "qup-core", "qup-config", "qup-memory"; 950 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 951 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 952 dma-names = "tx", "rx"; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 status = "disabled"; 956 }; 957 958 i2c12: i2c@890000 { 959 compatible = "qcom,geni-i2c"; 960 reg = <0 0x00890000 0 0x4000>; 961 clock-names = "se"; 962 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&qup_i2c12_data_clk>; 965 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 969 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 970 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 971 interconnect-names = "qup-core", "qup-config", "qup-memory"; 972 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 973 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 974 dma-names = "tx", "rx"; 975 status = "disabled"; 976 }; 977 978 spi12: spi@890000 { 979 compatible = "qcom,geni-spi"; 980 reg = <0 0x00890000 0 0x4000>; 981 clock-names = "se"; 982 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 983 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 986 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 987 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 988 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 989 interconnect-names = "qup-core", "qup-config", "qup-memory"; 990 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 991 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 992 dma-names = "tx", "rx"; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 status = "disabled"; 996 }; 997 998 i2c13: i2c@894000 { 999 compatible = "qcom,geni-i2c"; 1000 reg = <0 0x00894000 0 0x4000>; 1001 clock-names = "se"; 1002 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1003 pinctrl-names = "default"; 1004 pinctrl-0 = <&qup_i2c13_data_clk>; 1005 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1009 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1010 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1011 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1012 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1013 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1014 dma-names = "tx", "rx"; 1015 status = "disabled"; 1016 }; 1017 1018 spi13: spi@894000 { 1019 compatible = "qcom,geni-spi"; 1020 reg = <0 0x00894000 0 0x4000>; 1021 clock-names = "se"; 1022 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1023 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1026 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1027 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1028 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1029 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1030 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1031 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1032 dma-names = "tx", "rx"; 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 status = "disabled"; 1036 }; 1037 1038 i2c15: i2c@89c000 { 1039 compatible = "qcom,geni-i2c"; 1040 reg = <0 0x0089c000 0 0x4000>; 1041 clock-names = "se"; 1042 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&qup_i2c15_data_clk>; 1045 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1049 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1050 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1051 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1052 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1053 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1054 dma-names = "tx", "rx"; 1055 status = "disabled"; 1056 }; 1057 1058 spi15: spi@89c000 { 1059 compatible = "qcom,geni-spi"; 1060 reg = <0 0x0089c000 0 0x4000>; 1061 clock-names = "se"; 1062 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1063 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1064 pinctrl-names = "default"; 1065 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1066 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1067 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1068 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1069 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1070 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1071 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1072 dma-names = "tx", "rx"; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 status = "disabled"; 1076 }; 1077 }; 1078 1079 i2c_master_hub_0: geniqup@9c0000 { 1080 compatible = "qcom,geni-se-i2c-master-hub"; 1081 reg = <0x0 0x009c0000 0x0 0x2000>; 1082 clock-names = "s-ahb"; 1083 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1084 #address-cells = <2>; 1085 #size-cells = <2>; 1086 ranges; 1087 status = "disabled"; 1088 1089 i2c_hub_0: i2c@980000 { 1090 compatible = "qcom,geni-i2c-master-hub"; 1091 reg = <0x0 0x00980000 0x0 0x4000>; 1092 clock-names = "se", "core"; 1093 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1094 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&hub_i2c0_data_clk>; 1097 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1101 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1102 interconnect-names = "qup-core", "qup-config"; 1103 status = "disabled"; 1104 }; 1105 1106 i2c_hub_1: i2c@984000 { 1107 compatible = "qcom,geni-i2c-master-hub"; 1108 reg = <0x0 0x00984000 0x0 0x4000>; 1109 clock-names = "se", "core"; 1110 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1111 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&hub_i2c1_data_clk>; 1114 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1118 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1119 interconnect-names = "qup-core", "qup-config"; 1120 status = "disabled"; 1121 }; 1122 1123 i2c_hub_2: i2c@988000 { 1124 compatible = "qcom,geni-i2c-master-hub"; 1125 reg = <0x0 0x00988000 0x0 0x4000>; 1126 clock-names = "se", "core"; 1127 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1128 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1129 pinctrl-names = "default"; 1130 pinctrl-0 = <&hub_i2c2_data_clk>; 1131 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1135 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1136 interconnect-names = "qup-core", "qup-config"; 1137 status = "disabled"; 1138 }; 1139 1140 i2c_hub_3: i2c@98c000 { 1141 compatible = "qcom,geni-i2c-master-hub"; 1142 reg = <0x0 0x0098c000 0x0 0x4000>; 1143 clock-names = "se", "core"; 1144 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1145 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1146 pinctrl-names = "default"; 1147 pinctrl-0 = <&hub_i2c3_data_clk>; 1148 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1152 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1153 interconnect-names = "qup-core", "qup-config"; 1154 status = "disabled"; 1155 }; 1156 1157 i2c_hub_4: i2c@990000 { 1158 compatible = "qcom,geni-i2c-master-hub"; 1159 reg = <0x0 0x00990000 0x0 0x4000>; 1160 clock-names = "se", "core"; 1161 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1162 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&hub_i2c4_data_clk>; 1165 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1169 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1170 interconnect-names = "qup-core", "qup-config"; 1171 status = "disabled"; 1172 }; 1173 1174 i2c_hub_5: i2c@994000 { 1175 compatible = "qcom,geni-i2c-master-hub"; 1176 reg = <0 0x00994000 0 0x4000>; 1177 clock-names = "se", "core"; 1178 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1179 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1180 pinctrl-names = "default"; 1181 pinctrl-0 = <&hub_i2c5_data_clk>; 1182 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1186 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1187 interconnect-names = "qup-core", "qup-config"; 1188 status = "disabled"; 1189 }; 1190 1191 i2c_hub_6: i2c@998000 { 1192 compatible = "qcom,geni-i2c-master-hub"; 1193 reg = <0 0x00998000 0 0x4000>; 1194 clock-names = "se", "core"; 1195 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1196 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1197 pinctrl-names = "default"; 1198 pinctrl-0 = <&hub_i2c6_data_clk>; 1199 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1203 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1204 interconnect-names = "qup-core", "qup-config"; 1205 status = "disabled"; 1206 }; 1207 1208 i2c_hub_7: i2c@99c000 { 1209 compatible = "qcom,geni-i2c-master-hub"; 1210 reg = <0 0x0099c000 0 0x4000>; 1211 clock-names = "se", "core"; 1212 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1213 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1214 pinctrl-names = "default"; 1215 pinctrl-0 = <&hub_i2c7_data_clk>; 1216 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1220 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1221 interconnect-names = "qup-core", "qup-config"; 1222 status = "disabled"; 1223 }; 1224 1225 i2c_hub_8: i2c@9a0000 { 1226 compatible = "qcom,geni-i2c-master-hub"; 1227 reg = <0 0x009a0000 0 0x4000>; 1228 clock-names = "se", "core"; 1229 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1230 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1231 pinctrl-names = "default"; 1232 pinctrl-0 = <&hub_i2c8_data_clk>; 1233 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1237 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1238 interconnect-names = "qup-core", "qup-config"; 1239 status = "disabled"; 1240 }; 1241 1242 i2c_hub_9: i2c@9a4000 { 1243 compatible = "qcom,geni-i2c-master-hub"; 1244 reg = <0 0x009a4000 0 0x4000>; 1245 clock-names = "se", "core"; 1246 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1247 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&hub_i2c9_data_clk>; 1250 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1254 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1255 interconnect-names = "qup-core", "qup-config"; 1256 status = "disabled"; 1257 }; 1258 }; 1259 1260 gpi_dma1: dma-controller@a00000 { 1261 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1262 #dma-cells = <3>; 1263 reg = <0 0x00a00000 0 0x60000>; 1264 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1276 dma-channels = <12>; 1277 dma-channel-mask = <0x1e>; 1278 iommus = <&apps_smmu 0xb6 0>; 1279 status = "disabled"; 1280 }; 1281 1282 qupv3_id_0: geniqup@ac0000 { 1283 compatible = "qcom,geni-se-qup"; 1284 reg = <0 0x00ac0000 0 0x2000>; 1285 ranges; 1286 clock-names = "m-ahb", "s-ahb"; 1287 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1288 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1289 iommus = <&apps_smmu 0xa3 0>; 1290 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1291 interconnect-names = "qup-core"; 1292 #address-cells = <2>; 1293 #size-cells = <2>; 1294 status = "disabled"; 1295 1296 i2c0: i2c@a80000 { 1297 compatible = "qcom,geni-i2c"; 1298 reg = <0 0x00a80000 0 0x4000>; 1299 clock-names = "se"; 1300 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&qup_i2c0_data_clk>; 1303 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1307 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1308 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1309 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1310 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1311 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1312 dma-names = "tx", "rx"; 1313 status = "disabled"; 1314 }; 1315 1316 spi0: spi@a80000 { 1317 compatible = "qcom,geni-spi"; 1318 reg = <0 0x00a80000 0 0x4000>; 1319 clock-names = "se"; 1320 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1321 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1322 pinctrl-names = "default"; 1323 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1324 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1325 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1326 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1327 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1328 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1329 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1330 dma-names = "tx", "rx"; 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 status = "disabled"; 1334 }; 1335 1336 i2c1: i2c@a84000 { 1337 compatible = "qcom,geni-i2c"; 1338 reg = <0 0x00a84000 0 0x4000>; 1339 clock-names = "se"; 1340 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&qup_i2c1_data_clk>; 1343 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1347 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1348 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1349 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1350 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1351 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1352 dma-names = "tx", "rx"; 1353 status = "disabled"; 1354 }; 1355 1356 spi1: spi@a84000 { 1357 compatible = "qcom,geni-spi"; 1358 reg = <0 0x00a84000 0 0x4000>; 1359 clock-names = "se"; 1360 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1361 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1362 pinctrl-names = "default"; 1363 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1364 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1365 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1366 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1367 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1368 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1369 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1370 dma-names = "tx", "rx"; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 status = "disabled"; 1374 }; 1375 1376 i2c2: i2c@a88000 { 1377 compatible = "qcom,geni-i2c"; 1378 reg = <0 0x00a88000 0 0x4000>; 1379 clock-names = "se"; 1380 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1381 pinctrl-names = "default"; 1382 pinctrl-0 = <&qup_i2c2_data_clk>; 1383 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1387 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1388 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1389 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1390 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1391 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1392 dma-names = "tx", "rx"; 1393 status = "disabled"; 1394 }; 1395 1396 spi2: spi@a88000 { 1397 compatible = "qcom,geni-spi"; 1398 reg = <0 0x00a88000 0 0x4000>; 1399 clock-names = "se"; 1400 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1401 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1402 pinctrl-names = "default"; 1403 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1404 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1405 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1406 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1407 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1408 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1409 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1410 dma-names = "tx", "rx"; 1411 #address-cells = <1>; 1412 #size-cells = <0>; 1413 status = "disabled"; 1414 }; 1415 1416 i2c3: i2c@a8c000 { 1417 compatible = "qcom,geni-i2c"; 1418 reg = <0 0x00a8c000 0 0x4000>; 1419 clock-names = "se"; 1420 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1421 pinctrl-names = "default"; 1422 pinctrl-0 = <&qup_i2c3_data_clk>; 1423 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1424 #address-cells = <1>; 1425 #size-cells = <0>; 1426 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1427 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1428 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1429 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1430 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1431 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1432 dma-names = "tx", "rx"; 1433 status = "disabled"; 1434 }; 1435 1436 spi3: spi@a8c000 { 1437 compatible = "qcom,geni-spi"; 1438 reg = <0 0x00a8c000 0 0x4000>; 1439 clock-names = "se"; 1440 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1441 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1442 pinctrl-names = "default"; 1443 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1444 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1445 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1446 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1447 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1448 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1449 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1450 dma-names = "tx", "rx"; 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 status = "disabled"; 1454 }; 1455 1456 i2c4: i2c@a90000 { 1457 compatible = "qcom,geni-i2c"; 1458 reg = <0 0x00a90000 0 0x4000>; 1459 clock-names = "se"; 1460 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&qup_i2c4_data_clk>; 1463 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1467 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1468 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1469 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1470 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1471 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1472 dma-names = "tx", "rx"; 1473 status = "disabled"; 1474 }; 1475 1476 spi4: spi@a90000 { 1477 compatible = "qcom,geni-spi"; 1478 reg = <0 0x00a90000 0 0x4000>; 1479 clock-names = "se"; 1480 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1481 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1482 pinctrl-names = "default"; 1483 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1484 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1485 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1486 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1487 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1488 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1489 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1490 dma-names = "tx", "rx"; 1491 #address-cells = <1>; 1492 #size-cells = <0>; 1493 status = "disabled"; 1494 }; 1495 1496 i2c5: i2c@a94000 { 1497 compatible = "qcom,geni-i2c"; 1498 reg = <0 0x00a94000 0 0x4000>; 1499 clock-names = "se"; 1500 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&qup_i2c5_data_clk>; 1503 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1504 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1505 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1506 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1507 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1508 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1509 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1510 dma-names = "tx", "rx"; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 status = "disabled"; 1514 }; 1515 1516 spi5: spi@a94000 { 1517 compatible = "qcom,geni-spi"; 1518 reg = <0 0x00a94000 0 0x4000>; 1519 clock-names = "se"; 1520 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1521 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1522 pinctrl-names = "default"; 1523 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1524 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1525 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1526 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1527 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1528 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1529 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1530 dma-names = "tx", "rx"; 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 status = "disabled"; 1534 }; 1535 1536 i2c6: i2c@a98000 { 1537 compatible = "qcom,geni-i2c"; 1538 reg = <0 0x00a98000 0 0x4000>; 1539 clock-names = "se"; 1540 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1541 pinctrl-names = "default"; 1542 pinctrl-0 = <&qup_i2c6_data_clk>; 1543 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1544 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1545 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1546 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1547 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1548 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1549 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1550 dma-names = "tx", "rx"; 1551 #address-cells = <1>; 1552 #size-cells = <0>; 1553 status = "disabled"; 1554 }; 1555 1556 spi6: spi@a98000 { 1557 compatible = "qcom,geni-spi"; 1558 reg = <0 0x00a98000 0 0x4000>; 1559 clock-names = "se"; 1560 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1561 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1562 pinctrl-names = "default"; 1563 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1564 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1565 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1566 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1567 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1568 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1569 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1570 dma-names = "tx", "rx"; 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 status = "disabled"; 1574 }; 1575 1576 uart7: serial@a9c000 { 1577 compatible = "qcom,geni-debug-uart"; 1578 reg = <0 0x00a9c000 0 0x4000>; 1579 clock-names = "se"; 1580 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1581 pinctrl-names = "default"; 1582 pinctrl-0 = <&qup_uart7_default>; 1583 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1584 interconnect-names = "qup-core", "qup-config"; 1585 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1586 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1587 status = "disabled"; 1588 }; 1589 }; 1590 1591 cnoc_main: interconnect@1500000 { 1592 compatible = "qcom,sm8550-cnoc-main"; 1593 reg = <0 0x01500000 0 0x13080>; 1594 #interconnect-cells = <2>; 1595 qcom,bcm-voters = <&apps_bcm_voter>; 1596 }; 1597 1598 config_noc: interconnect@1600000 { 1599 compatible = "qcom,sm8550-config-noc"; 1600 reg = <0 0x01600000 0 0x6200>; 1601 #interconnect-cells = <2>; 1602 qcom,bcm-voters = <&apps_bcm_voter>; 1603 }; 1604 1605 system_noc: interconnect@1680000 { 1606 compatible = "qcom,sm8550-system-noc"; 1607 reg = <0 0x01680000 0 0x1d080>; 1608 #interconnect-cells = <2>; 1609 qcom,bcm-voters = <&apps_bcm_voter>; 1610 }; 1611 1612 pcie_noc: interconnect@16c0000 { 1613 compatible = "qcom,sm8550-pcie-anoc"; 1614 reg = <0 0x016c0000 0 0x12200>; 1615 #interconnect-cells = <2>; 1616 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1617 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1618 qcom,bcm-voters = <&apps_bcm_voter>; 1619 }; 1620 1621 aggre1_noc: interconnect@16e0000 { 1622 compatible = "qcom,sm8550-aggre1-noc"; 1623 reg = <0 0x016e0000 0 0x14400>; 1624 #interconnect-cells = <2>; 1625 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1626 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1627 qcom,bcm-voters = <&apps_bcm_voter>; 1628 }; 1629 1630 aggre2_noc: interconnect@1700000 { 1631 compatible = "qcom,sm8550-aggre2-noc"; 1632 reg = <0 0x01700000 0 0x1e400>; 1633 #interconnect-cells = <2>; 1634 clocks = <&rpmhcc RPMH_IPA_CLK>; 1635 qcom,bcm-voters = <&apps_bcm_voter>; 1636 }; 1637 1638 mmss_noc: interconnect@1780000 { 1639 compatible = "qcom,sm8550-mmss-noc"; 1640 reg = <0 0x01780000 0 0x5b800>; 1641 #interconnect-cells = <2>; 1642 qcom,bcm-voters = <&apps_bcm_voter>; 1643 }; 1644 1645 pcie0: pci@1c00000 { 1646 device_type = "pci"; 1647 compatible = "qcom,pcie-sm8550"; 1648 reg = <0 0x01c00000 0 0x3000>, 1649 <0 0x60000000 0 0xf1d>, 1650 <0 0x60000f20 0 0xa8>, 1651 <0 0x60001000 0 0x1000>, 1652 <0 0x60100000 0 0x100000>; 1653 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1654 #address-cells = <3>; 1655 #size-cells = <2>; 1656 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1657 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1658 bus-range = <0x00 0xff>; 1659 1660 dma-coherent; 1661 1662 linux,pci-domain = <0>; 1663 num-lanes = <2>; 1664 1665 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1666 interrupt-names = "msi"; 1667 1668 #interrupt-cells = <1>; 1669 interrupt-map-mask = <0 0 0 0x7>; 1670 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1671 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1672 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1673 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1674 1675 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1676 <&gcc GCC_PCIE_0_AUX_CLK>, 1677 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1678 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1679 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1680 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1681 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1682 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1683 clock-names = "pipe", 1684 "aux", 1685 "cfg", 1686 "bus_master", 1687 "bus_slave", 1688 "slave_q2a", 1689 "ddrss_sf_tbu", 1690 "aggre0"; 1691 1692 interconnect-names = "pcie-mem"; 1693 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>; 1694 1695 iommus = <&apps_smmu 0x1400 0x7f>; 1696 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 1697 <0x100 &apps_smmu 0x1401 0x1>; 1698 1699 resets = <&gcc GCC_PCIE_0_BCR>; 1700 reset-names = "pci"; 1701 1702 power-domains = <&gcc PCIE_0_GDSC>; 1703 1704 phys = <&pcie0_phy>; 1705 phy-names = "pciephy"; 1706 1707 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1708 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1709 1710 pinctrl-names = "default"; 1711 pinctrl-0 = <&pcie0_default_state>; 1712 1713 status = "disabled"; 1714 }; 1715 1716 pcie0_phy: phy@1c06000 { 1717 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 1718 reg = <0 0x01c06000 0 0x2000>; 1719 1720 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1721 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1722 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1723 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1724 <&gcc GCC_PCIE_0_PIPE_CLK>; 1725 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1726 "pipe"; 1727 1728 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1729 reset-names = "phy"; 1730 1731 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1732 assigned-clock-rates = <100000000>; 1733 1734 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1735 1736 #clock-cells = <0>; 1737 clock-output-names = "pcie0_pipe_clk"; 1738 1739 #phy-cells = <0>; 1740 1741 status = "disabled"; 1742 }; 1743 1744 pcie1: pci@1c08000 { 1745 device_type = "pci"; 1746 compatible = "qcom,pcie-sm8550"; 1747 reg = <0x0 0x01c08000 0x0 0x3000>, 1748 <0x0 0x40000000 0x0 0xf1d>, 1749 <0x0 0x40000f20 0x0 0xa8>, 1750 <0x0 0x40001000 0x0 0x1000>, 1751 <0x0 0x40100000 0x0 0x100000>; 1752 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1753 #address-cells = <3>; 1754 #size-cells = <2>; 1755 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, 1756 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; 1757 bus-range = <0x00 0xff>; 1758 1759 dma-coherent; 1760 1761 linux,pci-domain = <1>; 1762 num-lanes = <2>; 1763 1764 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1765 interrupt-names = "msi"; 1766 1767 #interrupt-cells = <1>; 1768 interrupt-map-mask = <0 0 0 0x7>; 1769 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1770 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1771 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1772 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1773 1774 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1775 <&gcc GCC_PCIE_1_AUX_CLK>, 1776 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1777 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1778 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1779 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1780 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1781 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1782 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 1783 clock-names = "pipe", 1784 "aux", 1785 "cfg", 1786 "bus_master", 1787 "bus_slave", 1788 "slave_q2a", 1789 "ddrss_sf_tbu", 1790 "aggre1", 1791 "cnoc_pcie_sf_axi"; 1792 1793 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1794 assigned-clock-rates = <19200000>; 1795 1796 interconnect-names = "pcie-mem"; 1797 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>; 1798 1799 iommus = <&apps_smmu 0x1480 0x7f>; 1800 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 1801 <0x100 &apps_smmu 0x1481 0x1>; 1802 1803 resets = <&gcc GCC_PCIE_1_BCR>, 1804 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1805 reset-names = "pci", 1806 "pcie_1_link_down_reset"; 1807 1808 power-domains = <&gcc PCIE_1_GDSC>; 1809 1810 phys = <&pcie1_phy>; 1811 phy-names = "pciephy"; 1812 1813 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 1814 enable-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1815 1816 pinctrl-names = "default"; 1817 pinctrl-0 = <&pcie1_default_state>; 1818 1819 status = "disabled"; 1820 }; 1821 1822 pcie1_phy: phy@1c0e000 { 1823 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 1824 reg = <0x0 0x01c0e000 0x0 0x2000>; 1825 1826 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1827 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1828 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1829 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1830 <&gcc GCC_PCIE_1_PIPE_CLK>, 1831 <&gcc GCC_PCIE_1_PHY_AUX_CLK>; 1832 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1833 "pipe", "aux_phy"; 1834 1835 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 1836 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 1837 reset-names = "phy", "nocsr"; 1838 1839 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1840 assigned-clock-rates = <100000000>; 1841 1842 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1843 1844 #clock-cells = <0>; 1845 clock-output-names = "pcie1_pipe_clk"; 1846 1847 #phy-cells = <0>; 1848 1849 status = "disabled"; 1850 }; 1851 1852 cryptobam: dma-controller@1dc4000 { 1853 compatible = "qcom,bam-v1.7.0"; 1854 reg = <0x0 0x01dc4000 0x0 0x28000>; 1855 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1856 #dma-cells = <1>; 1857 qcom,ee = <0>; 1858 qcom,controlled-remotely; 1859 iommus = <&apps_smmu 0x480 0x0>, 1860 <&apps_smmu 0x481 0x0>; 1861 }; 1862 1863 crypto: crypto@1de0000 { 1864 compatible = "qcom,sm8550-qce"; 1865 reg = <0x0 0x01dfa000 0x0 0x6000>; 1866 dmas = <&cryptobam 4>, <&cryptobam 5>; 1867 dma-names = "rx", "tx"; 1868 iommus = <&apps_smmu 0x480 0x0>, 1869 <&apps_smmu 0x481 0x0>; 1870 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1871 interconnect-names = "memory"; 1872 }; 1873 1874 ufs_mem_phy: phy@1d80000 { 1875 compatible = "qcom,sm8550-qmp-ufs-phy"; 1876 reg = <0x0 0x01d80000 0x0 0x2000>; 1877 clocks = <&tcsr TCSR_UFS_CLKREF_EN>, 1878 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1879 clock-names = "ref", "ref_aux"; 1880 1881 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1882 1883 resets = <&ufs_mem_hc 0>; 1884 reset-names = "ufsphy"; 1885 1886 #clock-cells = <1>; 1887 #phy-cells = <0>; 1888 1889 status = "disabled"; 1890 }; 1891 1892 ufs_mem_hc: ufs@1d84000 { 1893 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 1894 "jedec,ufs-2.0"; 1895 reg = <0x0 0x01d84000 0x0 0x3000>; 1896 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1897 phys = <&ufs_mem_phy>; 1898 phy-names = "ufsphy"; 1899 lanes-per-direction = <2>; 1900 #reset-cells = <1>; 1901 resets = <&gcc GCC_UFS_PHY_BCR>; 1902 reset-names = "rst"; 1903 1904 power-domains = <&gcc UFS_PHY_GDSC>; 1905 required-opps = <&rpmhpd_opp_nom>; 1906 1907 iommus = <&apps_smmu 0x60 0x0>; 1908 1909 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 1910 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 1911 1912 interconnect-names = "ufs-ddr", "cpu-ufs"; 1913 clock-names = "core_clk", 1914 "bus_aggr_clk", 1915 "iface_clk", 1916 "core_clk_unipro", 1917 "ref_clk", 1918 "tx_lane0_sync_clk", 1919 "rx_lane0_sync_clk", 1920 "rx_lane1_sync_clk"; 1921 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1922 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1923 <&gcc GCC_UFS_PHY_AHB_CLK>, 1924 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1925 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 1926 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1927 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1928 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1929 freq-table-hz = 1930 <75000000 300000000>, 1931 <0 0>, 1932 <0 0>, 1933 <75000000 300000000>, 1934 <100000000 403000000>, 1935 <0 0>, 1936 <0 0>, 1937 <0 0>; 1938 status = "disabled"; 1939 }; 1940 1941 tcsr_mutex: hwlock@1f40000 { 1942 compatible = "qcom,tcsr-mutex"; 1943 reg = <0 0x01f40000 0 0x20000>; 1944 #hwlock-cells = <1>; 1945 }; 1946 1947 tcsr: clock-controller@1fc0000 { 1948 compatible = "qcom,sm8550-tcsr", "syscon"; 1949 reg = <0 0x01fc0000 0 0x30000>; 1950 clocks = <&rpmhcc RPMH_CXO_CLK>; 1951 #clock-cells = <1>; 1952 #reset-cells = <1>; 1953 }; 1954 1955 remoteproc_mpss: remoteproc@4080000 { 1956 compatible = "qcom,sm8550-mpss-pas"; 1957 reg = <0x0 0x04080000 0x0 0x4040>; 1958 1959 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1960 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1961 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1962 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1963 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1964 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1965 interrupt-names = "wdog", "fatal", "ready", "handover", 1966 "stop-ack", "shutdown-ack"; 1967 1968 clocks = <&rpmhcc RPMH_CXO_CLK>; 1969 clock-names = "xo"; 1970 1971 power-domains = <&rpmhpd SM8550_CX>, 1972 <&rpmhpd SM8550_MSS>; 1973 power-domain-names = "cx", "mss"; 1974 1975 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 1976 1977 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 1978 1979 qcom,qmp = <&aoss_qmp>; 1980 1981 qcom,smem-states = <&smp2p_modem_out 0>; 1982 qcom,smem-state-names = "stop"; 1983 1984 status = "disabled"; 1985 1986 glink-edge { 1987 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1988 IPCC_MPROC_SIGNAL_GLINK_QMP 1989 IRQ_TYPE_EDGE_RISING>; 1990 mboxes = <&ipcc IPCC_CLIENT_MPSS 1991 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1992 label = "mpss"; 1993 qcom,remote-pid = <1>; 1994 }; 1995 }; 1996 1997 lpass_tlmm: pinctrl@6e80000 { 1998 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 1999 reg = <0 0x06e80000 0 0x20000>, 2000 <0 0x0725a000 0 0x10000>; 2001 gpio-controller; 2002 #gpio-cells = <2>; 2003 gpio-ranges = <&lpass_tlmm 0 0 23>; 2004 2005 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2006 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2007 clock-names = "core", "audio"; 2008 }; 2009 2010 lpass_lpiaon_noc: interconnect@7400000 { 2011 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 2012 reg = <0 0x07400000 0 0x19080>; 2013 #interconnect-cells = <2>; 2014 qcom,bcm-voters = <&apps_bcm_voter>; 2015 }; 2016 2017 lpass_lpicx_noc: interconnect@7430000 { 2018 compatible = "qcom,sm8550-lpass-lpicx-noc"; 2019 reg = <0 0x07430000 0 0x3a200>; 2020 #interconnect-cells = <2>; 2021 qcom,bcm-voters = <&apps_bcm_voter>; 2022 }; 2023 2024 lpass_ag_noc: interconnect@7e40000 { 2025 compatible = "qcom,sm8550-lpass-ag-noc"; 2026 reg = <0 0x07e40000 0 0xe080>; 2027 #interconnect-cells = <2>; 2028 qcom,bcm-voters = <&apps_bcm_voter>; 2029 }; 2030 2031 sdhc_2: mmc@8804000 { 2032 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 2033 reg = <0 0x08804000 0 0x1000>; 2034 2035 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2037 interrupt-names = "hc_irq", "pwr_irq"; 2038 2039 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2040 <&gcc GCC_SDCC2_APPS_CLK>, 2041 <&rpmhcc RPMH_CXO_CLK>; 2042 clock-names = "iface", "core", "xo"; 2043 iommus = <&apps_smmu 0x540 0>; 2044 qcom,dll-config = <0x0007642c>; 2045 qcom,ddr-config = <0x80040868>; 2046 power-domains = <&rpmhpd SM8550_CX>; 2047 operating-points-v2 = <&sdhc2_opp_table>; 2048 2049 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2050 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2051 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 2052 bus-width = <4>; 2053 dma-coherent; 2054 2055 /* Forbid SDR104/SDR50 - broken hw! */ 2056 sdhci-caps-mask = <0x3 0>; 2057 2058 status = "disabled"; 2059 2060 sdhc2_opp_table: opp-table { 2061 compatible = "operating-points-v2"; 2062 2063 opp-19200000 { 2064 opp-hz = /bits/ 64 <19200000>; 2065 required-opps = <&rpmhpd_opp_min_svs>; 2066 }; 2067 2068 opp-50000000 { 2069 opp-hz = /bits/ 64 <50000000>; 2070 required-opps = <&rpmhpd_opp_low_svs>; 2071 }; 2072 2073 opp-100000000 { 2074 opp-hz = /bits/ 64 <100000000>; 2075 required-opps = <&rpmhpd_opp_svs>; 2076 }; 2077 2078 opp-202000000 { 2079 opp-hz = /bits/ 64 <202000000>; 2080 required-opps = <&rpmhpd_opp_svs_l1>; 2081 }; 2082 }; 2083 }; 2084 2085 mdss: display-subsystem@ae00000 { 2086 compatible = "qcom,sm8550-mdss"; 2087 reg = <0 0x0ae00000 0 0x1000>; 2088 reg-names = "mdss"; 2089 2090 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2091 interrupt-controller; 2092 #interrupt-cells = <1>; 2093 2094 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2095 <&gcc GCC_DISP_AHB_CLK>, 2096 <&gcc GCC_DISP_HF_AXI_CLK>, 2097 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2098 2099 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2100 2101 power-domains = <&dispcc MDSS_GDSC>; 2102 2103 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, 2104 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2105 interconnect-names = "mdp0-mem", "mdp1-mem"; 2106 2107 iommus = <&apps_smmu 0x1c00 0x2>; 2108 2109 #address-cells = <2>; 2110 #size-cells = <2>; 2111 ranges; 2112 2113 status = "disabled"; 2114 2115 mdss_mdp: display-controller@ae01000 { 2116 compatible = "qcom,sm8550-dpu"; 2117 reg = <0 0x0ae01000 0 0x8f000>, 2118 <0 0x0aeb0000 0 0x2008>; 2119 reg-names = "mdp", "vbif"; 2120 2121 interrupt-parent = <&mdss>; 2122 interrupts = <0>; 2123 2124 clocks = <&gcc GCC_DISP_AHB_CLK>, 2125 <&gcc GCC_DISP_HF_AXI_CLK>, 2126 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2127 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2128 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2129 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2130 clock-names = "bus", 2131 "nrt_bus", 2132 "iface", 2133 "lut", 2134 "core", 2135 "vsync"; 2136 2137 power-domains = <&rpmhpd SM8550_MMCX>; 2138 2139 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2140 assigned-clock-rates = <19200000>; 2141 2142 operating-points-v2 = <&mdp_opp_table>; 2143 2144 ports { 2145 #address-cells = <1>; 2146 #size-cells = <0>; 2147 2148 port@0 { 2149 reg = <0>; 2150 dpu_intf1_out: endpoint { 2151 remote-endpoint = <&mdss_dsi0_in>; 2152 }; 2153 }; 2154 2155 port@1 { 2156 reg = <1>; 2157 dpu_intf2_out: endpoint { 2158 remote-endpoint = <&mdss_dsi1_in>; 2159 }; 2160 }; 2161 }; 2162 2163 mdp_opp_table: opp-table { 2164 compatible = "operating-points-v2"; 2165 2166 opp-200000000 { 2167 opp-hz = /bits/ 64 <200000000>; 2168 required-opps = <&rpmhpd_opp_low_svs>; 2169 }; 2170 2171 opp-325000000 { 2172 opp-hz = /bits/ 64 <325000000>; 2173 required-opps = <&rpmhpd_opp_svs>; 2174 }; 2175 2176 opp-375000000 { 2177 opp-hz = /bits/ 64 <375000000>; 2178 required-opps = <&rpmhpd_opp_svs_l1>; 2179 }; 2180 2181 opp-514000000 { 2182 opp-hz = /bits/ 64 <514000000>; 2183 required-opps = <&rpmhpd_opp_nom>; 2184 }; 2185 }; 2186 }; 2187 2188 mdss_dsi0: dsi@ae94000 { 2189 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2190 reg = <0 0x0ae94000 0 0x400>; 2191 reg-names = "dsi_ctrl"; 2192 2193 interrupt-parent = <&mdss>; 2194 interrupts = <4>; 2195 2196 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2197 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2198 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2199 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2200 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2201 <&gcc GCC_DISP_HF_AXI_CLK>; 2202 clock-names = "byte", 2203 "byte_intf", 2204 "pixel", 2205 "core", 2206 "iface", 2207 "bus"; 2208 2209 power-domains = <&rpmhpd SM8550_MMCX>; 2210 2211 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2212 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2213 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 2214 2215 operating-points-v2 = <&mdss_dsi_opp_table>; 2216 2217 phys = <&mdss_dsi0_phy>; 2218 phy-names = "dsi"; 2219 2220 #address-cells = <1>; 2221 #size-cells = <0>; 2222 2223 status = "disabled"; 2224 2225 ports { 2226 #address-cells = <1>; 2227 #size-cells = <0>; 2228 2229 port@0 { 2230 reg = <0>; 2231 mdss_dsi0_in: endpoint { 2232 remote-endpoint = <&dpu_intf1_out>; 2233 }; 2234 }; 2235 2236 port@1 { 2237 reg = <1>; 2238 mdss_dsi0_out: endpoint { 2239 }; 2240 }; 2241 }; 2242 2243 mdss_dsi_opp_table: opp-table { 2244 compatible = "operating-points-v2"; 2245 2246 opp-187500000 { 2247 opp-hz = /bits/ 64 <187500000>; 2248 required-opps = <&rpmhpd_opp_low_svs>; 2249 }; 2250 2251 opp-300000000 { 2252 opp-hz = /bits/ 64 <300000000>; 2253 required-opps = <&rpmhpd_opp_svs>; 2254 }; 2255 2256 opp-358000000 { 2257 opp-hz = /bits/ 64 <358000000>; 2258 required-opps = <&rpmhpd_opp_svs_l1>; 2259 }; 2260 }; 2261 }; 2262 2263 mdss_dsi0_phy: phy@ae95000 { 2264 compatible = "qcom,sm8550-dsi-phy-4nm"; 2265 reg = <0 0x0ae95000 0 0x200>, 2266 <0 0x0ae95200 0 0x280>, 2267 <0 0x0ae95500 0 0x400>; 2268 reg-names = "dsi_phy", 2269 "dsi_phy_lane", 2270 "dsi_pll"; 2271 2272 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2273 <&rpmhcc RPMH_CXO_CLK>; 2274 clock-names = "iface", "ref"; 2275 2276 #clock-cells = <1>; 2277 #phy-cells = <0>; 2278 2279 status = "disabled"; 2280 }; 2281 2282 mdss_dsi1: dsi@ae96000 { 2283 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2284 reg = <0 0x0ae96000 0 0x400>; 2285 reg-names = "dsi_ctrl"; 2286 2287 interrupt-parent = <&mdss>; 2288 interrupts = <5>; 2289 2290 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2291 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2292 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2293 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2294 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2295 <&gcc GCC_DISP_HF_AXI_CLK>; 2296 clock-names = "byte", 2297 "byte_intf", 2298 "pixel", 2299 "core", 2300 "iface", 2301 "bus"; 2302 2303 power-domains = <&rpmhpd SM8550_MMCX>; 2304 2305 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2306 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 2307 2308 operating-points-v2 = <&mdss_dsi_opp_table>; 2309 2310 phys = <&mdss_dsi1_phy>; 2311 phy-names = "dsi"; 2312 2313 #address-cells = <1>; 2314 #size-cells = <0>; 2315 2316 status = "disabled"; 2317 2318 ports { 2319 #address-cells = <1>; 2320 #size-cells = <0>; 2321 2322 port@0 { 2323 reg = <0>; 2324 mdss_dsi1_in: endpoint { 2325 remote-endpoint = <&dpu_intf2_out>; 2326 }; 2327 }; 2328 2329 port@1 { 2330 reg = <1>; 2331 mdss_dsi1_out: endpoint { 2332 }; 2333 }; 2334 }; 2335 }; 2336 2337 mdss_dsi1_phy: phy@ae97000 { 2338 compatible = "qcom,sm8550-dsi-phy-4nm"; 2339 reg = <0 0x0ae97000 0 0x200>, 2340 <0 0x0ae97200 0 0x280>, 2341 <0 0x0ae97500 0 0x400>; 2342 reg-names = "dsi_phy", 2343 "dsi_phy_lane", 2344 "dsi_pll"; 2345 2346 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2347 <&rpmhcc RPMH_CXO_CLK>; 2348 clock-names = "iface", "ref"; 2349 2350 #clock-cells = <1>; 2351 #phy-cells = <0>; 2352 2353 status = "disabled"; 2354 }; 2355 }; 2356 2357 dispcc: clock-controller@af00000 { 2358 compatible = "qcom,sm8550-dispcc"; 2359 reg = <0 0x0af00000 0 0x20000>; 2360 clocks = <&bi_tcxo_div2>, 2361 <&bi_tcxo_ao_div2>, 2362 <&gcc GCC_DISP_AHB_CLK>, 2363 <&sleep_clk>, 2364 <&mdss_dsi0_phy 0>, 2365 <&mdss_dsi0_phy 1>, 2366 <&mdss_dsi1_phy 0>, 2367 <&mdss_dsi1_phy 1>, 2368 <0>, /* dp0 */ 2369 <0>, 2370 <0>, /* dp1 */ 2371 <0>, 2372 <0>, /* dp2 */ 2373 <0>, 2374 <0>, /* dp3 */ 2375 <0>; 2376 power-domains = <&rpmhpd SM8550_MMCX>; 2377 required-opps = <&rpmhpd_opp_low_svs>; 2378 #clock-cells = <1>; 2379 #reset-cells = <1>; 2380 #power-domain-cells = <1>; 2381 status = "disabled"; 2382 }; 2383 2384 usb_1_hsphy: phy@88e3000 { 2385 compatible = "qcom,sm8550-snps-eusb2-phy"; 2386 reg = <0x0 0x088e3000 0x0 0x154>; 2387 #phy-cells = <0>; 2388 2389 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 2390 clock-names = "ref"; 2391 2392 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2393 2394 status = "disabled"; 2395 }; 2396 2397 usb_dp_qmpphy: phy@88e8000 { 2398 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 2399 reg = <0x0 0x088e8000 0x0 0x3000>; 2400 2401 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2402 <&rpmhcc RPMH_CXO_CLK>, 2403 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2404 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2405 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2406 2407 power-domains = <&gcc USB3_PHY_GDSC>; 2408 2409 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2410 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2411 reset-names = "phy", "common"; 2412 2413 #clock-cells = <1>; 2414 #phy-cells = <1>; 2415 2416 status = "disabled"; 2417 }; 2418 2419 usb_1: usb@a6f8800 { 2420 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 2421 reg = <0x0 0x0a6f8800 0x0 0x400>; 2422 #address-cells = <2>; 2423 #size-cells = <2>; 2424 ranges; 2425 2426 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2427 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2428 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2429 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2430 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2431 <&tcsr TCSR_USB3_CLKREF_EN>; 2432 clock-names = "cfg_noc", 2433 "core", 2434 "iface", 2435 "sleep", 2436 "mock_utmi", 2437 "xo"; 2438 2439 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2440 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2441 assigned-clock-rates = <19200000>, <200000000>; 2442 2443 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2444 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2445 <&pdc 15 IRQ_TYPE_EDGE_RISING>, 2446 <&pdc 14 IRQ_TYPE_EDGE_RISING>; 2447 interrupt-names = "hs_phy_irq", 2448 "ss_phy_irq", 2449 "dm_hs_phy_irq", 2450 "dp_hs_phy_irq"; 2451 2452 power-domains = <&gcc USB30_PRIM_GDSC>; 2453 required-opps = <&rpmhpd_opp_nom>; 2454 2455 resets = <&gcc GCC_USB30_PRIM_BCR>; 2456 2457 status = "disabled"; 2458 2459 usb_1_dwc3: usb@a600000 { 2460 compatible = "snps,dwc3"; 2461 reg = <0x0 0x0a600000 0x0 0xcd00>; 2462 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2463 iommus = <&apps_smmu 0x40 0x0>; 2464 snps,dis_u2_susphy_quirk; 2465 snps,dis_enblslpm_quirk; 2466 snps,usb3_lpm_capable; 2467 phys = <&usb_1_hsphy>, 2468 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 2469 phy-names = "usb2-phy", "usb3-phy"; 2470 }; 2471 }; 2472 2473 pdc: interrupt-controller@b220000 { 2474 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 2475 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 2476 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2477 <125 63 1>, <126 716 12>, 2478 <138 251 5>; 2479 #interrupt-cells = <2>; 2480 interrupt-parent = <&intc>; 2481 interrupt-controller; 2482 }; 2483 2484 tsens0: thermal-sensor@c271000 { 2485 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2486 reg = <0 0x0c271000 0 0x1000>, /* TM */ 2487 <0 0x0c222000 0 0x1000>; /* SROT */ 2488 #qcom,sensors = <16>; 2489 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 2491 interrupt-names = "uplow", "critical"; 2492 #thermal-sensor-cells = <1>; 2493 }; 2494 2495 tsens1: thermal-sensor@c272000 { 2496 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2497 reg = <0 0x0c272000 0 0x1000>, /* TM */ 2498 <0 0x0c223000 0 0x1000>; /* SROT */ 2499 #qcom,sensors = <16>; 2500 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2502 interrupt-names = "uplow", "critical"; 2503 #thermal-sensor-cells = <1>; 2504 }; 2505 2506 tsens2: thermal-sensor@c273000 { 2507 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 2508 reg = <0 0x0c273000 0 0x1000>, /* TM */ 2509 <0 0x0c224000 0 0x1000>; /* SROT */ 2510 #qcom,sensors = <16>; 2511 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2512 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2513 interrupt-names = "uplow", "critical"; 2514 #thermal-sensor-cells = <1>; 2515 }; 2516 2517 aoss_qmp: power-management@c300000 { 2518 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 2519 reg = <0 0x0c300000 0 0x400>; 2520 interrupt-parent = <&ipcc>; 2521 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2522 IRQ_TYPE_EDGE_RISING>; 2523 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2524 2525 #clock-cells = <0>; 2526 }; 2527 2528 sram@c3f0000 { 2529 compatible = "qcom,rpmh-stats"; 2530 reg = <0 0x0c3f0000 0 0x400>; 2531 }; 2532 2533 spmi_bus: spmi@c400000 { 2534 compatible = "qcom,spmi-pmic-arb"; 2535 reg = <0 0x0c400000 0 0x3000>, 2536 <0 0x0c500000 0 0x4000000>, 2537 <0 0x0c440000 0 0x80000>, 2538 <0 0x0c4c0000 0 0x20000>, 2539 <0 0x0c42d000 0 0x4000>; 2540 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2541 interrupt-names = "periph_irq"; 2542 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2543 qcom,ee = <0>; 2544 qcom,channel = <0>; 2545 qcom,bus-id = <0>; 2546 #address-cells = <2>; 2547 #size-cells = <0>; 2548 interrupt-controller; 2549 #interrupt-cells = <4>; 2550 }; 2551 2552 tlmm: pinctrl@f000000 { 2553 compatible = "qcom,sm8550-tlmm"; 2554 reg = <0 0x0f100000 0 0x300000>; 2555 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2556 gpio-controller; 2557 #gpio-cells = <2>; 2558 interrupt-controller; 2559 #interrupt-cells = <2>; 2560 gpio-ranges = <&tlmm 0 0 211>; 2561 wakeup-parent = <&pdc>; 2562 2563 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 2564 /* SDA, SCL */ 2565 pins = "gpio16", "gpio17"; 2566 function = "i2chub0_se0"; 2567 drive-strength = <2>; 2568 bias-pull-up; 2569 }; 2570 2571 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 2572 /* SDA, SCL */ 2573 pins = "gpio18", "gpio19"; 2574 function = "i2chub0_se1"; 2575 drive-strength = <2>; 2576 bias-pull-up; 2577 }; 2578 2579 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 2580 /* SDA, SCL */ 2581 pins = "gpio20", "gpio21"; 2582 function = "i2chub0_se2"; 2583 drive-strength = <2>; 2584 bias-pull-up; 2585 }; 2586 2587 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 2588 /* SDA, SCL */ 2589 pins = "gpio22", "gpio23"; 2590 function = "i2chub0_se3"; 2591 drive-strength = <2>; 2592 bias-pull-up; 2593 }; 2594 2595 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 2596 /* SDA, SCL */ 2597 pins = "gpio4", "gpio5"; 2598 function = "i2chub0_se4"; 2599 drive-strength = <2>; 2600 bias-pull-up; 2601 }; 2602 2603 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 2604 /* SDA, SCL */ 2605 pins = "gpio6", "gpio7"; 2606 function = "i2chub0_se5"; 2607 drive-strength = <2>; 2608 bias-pull-up; 2609 }; 2610 2611 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 2612 /* SDA, SCL */ 2613 pins = "gpio8", "gpio9"; 2614 function = "i2chub0_se6"; 2615 drive-strength = <2>; 2616 bias-pull-up; 2617 }; 2618 2619 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 2620 /* SDA, SCL */ 2621 pins = "gpio10", "gpio11"; 2622 function = "i2chub0_se7"; 2623 drive-strength = <2>; 2624 bias-pull-up; 2625 }; 2626 2627 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 2628 /* SDA, SCL */ 2629 pins = "gpio206", "gpio207"; 2630 function = "i2chub0_se8"; 2631 drive-strength = <2>; 2632 bias-pull-up; 2633 }; 2634 2635 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 2636 /* SDA, SCL */ 2637 pins = "gpio84", "gpio85"; 2638 function = "i2chub0_se9"; 2639 drive-strength = <2>; 2640 bias-pull-up; 2641 }; 2642 2643 pcie0_default_state: pcie0-default-state { 2644 perst-pins { 2645 pins = "gpio94"; 2646 function = "gpio"; 2647 drive-strength = <2>; 2648 bias-pull-down; 2649 }; 2650 2651 clkreq-pins { 2652 pins = "gpio95"; 2653 function = "pcie0_clk_req_n"; 2654 drive-strength = <2>; 2655 bias-pull-up; 2656 }; 2657 2658 wake-pins { 2659 pins = "gpio96"; 2660 function = "gpio"; 2661 drive-strength = <2>; 2662 bias-pull-up; 2663 }; 2664 }; 2665 2666 pcie1_default_state: pcie1-default-state { 2667 perst-pins { 2668 pins = "gpio97"; 2669 function = "gpio"; 2670 drive-strength = <2>; 2671 bias-pull-down; 2672 }; 2673 2674 clkreq-pins { 2675 pins = "gpio98"; 2676 function = "pcie1_clk_req_n"; 2677 drive-strength = <2>; 2678 bias-pull-up; 2679 }; 2680 2681 wake-pins { 2682 pins = "gpio99"; 2683 function = "gpio"; 2684 drive-strength = <2>; 2685 bias-pull-up; 2686 }; 2687 }; 2688 2689 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 2690 /* SDA, SCL */ 2691 pins = "gpio28", "gpio29"; 2692 function = "qup1_se0"; 2693 drive-strength = <2>; 2694 bias-pull-up; 2695 }; 2696 2697 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2698 /* SDA, SCL */ 2699 pins = "gpio32", "gpio33"; 2700 function = "qup1_se1"; 2701 drive-strength = <2>; 2702 bias-pull-up; 2703 }; 2704 2705 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 2706 /* SDA, SCL */ 2707 pins = "gpio36", "gpio37"; 2708 function = "qup1_se2"; 2709 drive-strength = <2>; 2710 bias-pull-up; 2711 }; 2712 2713 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2714 /* SDA, SCL */ 2715 pins = "gpio40", "gpio41"; 2716 function = "qup1_se3"; 2717 drive-strength = <2>; 2718 bias-pull-up; 2719 }; 2720 2721 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 2722 /* SDA, SCL */ 2723 pins = "gpio44", "gpio45"; 2724 function = "qup1_se4"; 2725 drive-strength = <2>; 2726 bias-pull-up; 2727 }; 2728 2729 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 2730 /* SDA, SCL */ 2731 pins = "gpio52", "gpio53"; 2732 function = "qup1_se5"; 2733 drive-strength = <2>; 2734 bias-pull-up; 2735 }; 2736 2737 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 2738 /* SDA, SCL */ 2739 pins = "gpio48", "gpio49"; 2740 function = "qup1_se6"; 2741 drive-strength = <2>; 2742 bias-pull-up; 2743 }; 2744 2745 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 2746 scl-pins { 2747 pins = "gpio57"; 2748 function = "qup2_se0_l1_mira"; 2749 drive-strength = <2>; 2750 bias-pull-up; 2751 }; 2752 2753 sda-pins { 2754 pins = "gpio56"; 2755 function = "qup2_se0_l0_mira"; 2756 drive-strength = <2>; 2757 bias-pull-up; 2758 }; 2759 }; 2760 2761 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 2762 /* SDA, SCL */ 2763 pins = "gpio60", "gpio61"; 2764 function = "qup2_se1"; 2765 drive-strength = <2>; 2766 bias-pull-up; 2767 }; 2768 2769 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 2770 /* SDA, SCL */ 2771 pins = "gpio64", "gpio65"; 2772 function = "qup2_se2"; 2773 drive-strength = <2>; 2774 bias-pull-up; 2775 }; 2776 2777 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 2778 /* SDA, SCL */ 2779 pins = "gpio68", "gpio69"; 2780 function = "qup2_se3"; 2781 drive-strength = <2>; 2782 bias-pull-up; 2783 }; 2784 2785 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 2786 /* SDA, SCL */ 2787 pins = "gpio2", "gpio3"; 2788 function = "qup2_se4"; 2789 drive-strength = <2>; 2790 bias-pull-up; 2791 }; 2792 2793 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 2794 /* SDA, SCL */ 2795 pins = "gpio80", "gpio81"; 2796 function = "qup2_se5"; 2797 drive-strength = <2>; 2798 bias-pull-up; 2799 }; 2800 2801 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 2802 /* SDA, SCL */ 2803 pins = "gpio72", "gpio106"; 2804 function = "qup2_se7"; 2805 drive-strength = <2>; 2806 bias-pull-up; 2807 }; 2808 2809 qup_spi0_cs: qup-spi0-cs-state { 2810 cs-pins { 2811 pins = "gpio31"; 2812 function = "qup1_se0"; 2813 }; 2814 }; 2815 2816 qup_spi0_data_clk: qup-spi0-data-clk-state { 2817 /* MISO, MOSI, CLK */ 2818 pins = "gpio28", "gpio29", "gpio30"; 2819 function = "qup1_se0"; 2820 drive-strength = <6>; 2821 bias-disable; 2822 }; 2823 2824 qup_spi1_cs: qup-spi1-cs-state { 2825 pins = "gpio35"; 2826 function = "qup1_se1"; 2827 drive-strength = <6>; 2828 bias-disable; 2829 }; 2830 2831 qup_spi1_data_clk: qup-spi1-data-clk-state { 2832 /* MISO, MOSI, CLK */ 2833 pins = "gpio32", "gpio33", "gpio34"; 2834 function = "qup1_se1"; 2835 drive-strength = <6>; 2836 bias-disable; 2837 }; 2838 2839 qup_spi2_cs: qup-spi2-cs-state { 2840 pins = "gpio39"; 2841 function = "qup1_se2"; 2842 drive-strength = <6>; 2843 bias-disable; 2844 }; 2845 2846 qup_spi2_data_clk: qup-spi2-data-clk-state { 2847 /* MISO, MOSI, CLK */ 2848 pins = "gpio36", "gpio37", "gpio38"; 2849 function = "qup1_se2"; 2850 drive-strength = <6>; 2851 bias-disable; 2852 }; 2853 2854 qup_spi3_cs: qup-spi3-cs-state { 2855 pins = "gpio43"; 2856 function = "qup1_se3"; 2857 drive-strength = <6>; 2858 bias-disable; 2859 }; 2860 2861 qup_spi3_data_clk: qup-spi3-data-clk-state { 2862 /* MISO, MOSI, CLK */ 2863 pins = "gpio40", "gpio41", "gpio42"; 2864 function = "qup1_se3"; 2865 drive-strength = <6>; 2866 bias-disable; 2867 }; 2868 2869 qup_spi4_cs: qup-spi4-cs-state { 2870 pins = "gpio47"; 2871 function = "qup1_se4"; 2872 drive-strength = <6>; 2873 bias-disable; 2874 }; 2875 2876 qup_spi4_data_clk: qup-spi4-data-clk-state { 2877 /* MISO, MOSI, CLK */ 2878 pins = "gpio44", "gpio45", "gpio46"; 2879 function = "qup1_se4"; 2880 drive-strength = <6>; 2881 bias-disable; 2882 }; 2883 2884 qup_spi5_cs: qup-spi5-cs-state { 2885 pins = "gpio55"; 2886 function = "qup1_se5"; 2887 drive-strength = <6>; 2888 bias-disable; 2889 }; 2890 2891 qup_spi5_data_clk: qup-spi5-data-clk-state { 2892 /* MISO, MOSI, CLK */ 2893 pins = "gpio52", "gpio53", "gpio54"; 2894 function = "qup1_se5"; 2895 drive-strength = <6>; 2896 bias-disable; 2897 }; 2898 2899 qup_spi6_cs: qup-spi6-cs-state { 2900 pins = "gpio51"; 2901 function = "qup1_se6"; 2902 drive-strength = <6>; 2903 bias-disable; 2904 }; 2905 2906 qup_spi6_data_clk: qup-spi6-data-clk-state { 2907 /* MISO, MOSI, CLK */ 2908 pins = "gpio48", "gpio49", "gpio50"; 2909 function = "qup1_se6"; 2910 drive-strength = <6>; 2911 bias-disable; 2912 }; 2913 2914 qup_spi8_cs: qup-spi8-cs-state { 2915 pins = "gpio59"; 2916 function = "qup2_se0_l3_mira"; 2917 drive-strength = <6>; 2918 bias-disable; 2919 }; 2920 2921 qup_spi8_data_clk: qup-spi8-data-clk-state { 2922 /* MISO, MOSI, CLK */ 2923 pins = "gpio56", "gpio57", "gpio58"; 2924 function = "qup2_se0_l2_mira"; 2925 drive-strength = <6>; 2926 bias-disable; 2927 }; 2928 2929 qup_spi9_cs: qup-spi9-cs-state { 2930 pins = "gpio63"; 2931 function = "qup2_se1"; 2932 drive-strength = <6>; 2933 bias-disable; 2934 }; 2935 2936 qup_spi9_data_clk: qup-spi9-data-clk-state { 2937 /* MISO, MOSI, CLK */ 2938 pins = "gpio60", "gpio61", "gpio62"; 2939 function = "qup2_se1"; 2940 drive-strength = <6>; 2941 bias-disable; 2942 }; 2943 2944 qup_spi10_cs: qup-spi10-cs-state { 2945 pins = "gpio67"; 2946 function = "qup2_se2"; 2947 drive-strength = <6>; 2948 bias-disable; 2949 }; 2950 2951 qup_spi10_data_clk: qup-spi10-data-clk-state { 2952 /* MISO, MOSI, CLK */ 2953 pins = "gpio64", "gpio65", "gpio66"; 2954 function = "qup2_se2"; 2955 drive-strength = <6>; 2956 bias-disable; 2957 }; 2958 2959 qup_spi11_cs: qup-spi11-cs-state { 2960 pins = "gpio71"; 2961 function = "qup2_se3"; 2962 drive-strength = <6>; 2963 bias-disable; 2964 }; 2965 2966 qup_spi11_data_clk: qup-spi11-data-clk-state { 2967 /* MISO, MOSI, CLK */ 2968 pins = "gpio68", "gpio69", "gpio70"; 2969 function = "qup2_se3"; 2970 drive-strength = <6>; 2971 bias-disable; 2972 }; 2973 2974 qup_spi12_cs: qup-spi12-cs-state { 2975 pins = "gpio119"; 2976 function = "qup2_se4"; 2977 drive-strength = <6>; 2978 bias-disable; 2979 }; 2980 2981 qup_spi12_data_clk: qup-spi12-data-clk-state { 2982 /* MISO, MOSI, CLK */ 2983 pins = "gpio2", "gpio3", "gpio118"; 2984 function = "qup2_se4"; 2985 drive-strength = <6>; 2986 bias-disable; 2987 }; 2988 2989 qup_spi13_cs: qup-spi13-cs-state { 2990 pins = "gpio83"; 2991 function = "qup2_se5"; 2992 drive-strength = <6>; 2993 bias-disable; 2994 }; 2995 2996 qup_spi13_data_clk: qup-spi13-data-clk-state { 2997 /* MISO, MOSI, CLK */ 2998 pins = "gpio80", "gpio81", "gpio82"; 2999 function = "qup2_se5"; 3000 drive-strength = <6>; 3001 bias-disable; 3002 }; 3003 3004 qup_spi15_cs: qup-spi15-cs-state { 3005 pins = "gpio75"; 3006 function = "qup2_se7"; 3007 drive-strength = <6>; 3008 bias-disable; 3009 }; 3010 3011 qup_spi15_data_clk: qup-spi15-data-clk-state { 3012 /* MISO, MOSI, CLK */ 3013 pins = "gpio72", "gpio106", "gpio74"; 3014 function = "qup2_se7"; 3015 drive-strength = <6>; 3016 bias-disable; 3017 }; 3018 3019 qup_uart7_default: qup-uart7-default-state { 3020 /* TX, RX */ 3021 pins = "gpio26", "gpio27"; 3022 function = "qup1_se7"; 3023 drive-strength = <2>; 3024 bias-disable; 3025 }; 3026 3027 sdc2_sleep: sdc2-sleep-state { 3028 clk-pins { 3029 pins = "sdc2_clk"; 3030 bias-disable; 3031 drive-strength = <2>; 3032 }; 3033 3034 cmd-pins { 3035 pins = "sdc2_cmd"; 3036 bias-pull-up; 3037 drive-strength = <2>; 3038 }; 3039 3040 data-pins { 3041 pins = "sdc2_data"; 3042 bias-pull-up; 3043 drive-strength = <2>; 3044 }; 3045 }; 3046 3047 sdc2_default: sdc2-default-state { 3048 clk-pins { 3049 pins = "sdc2_clk"; 3050 bias-disable; 3051 drive-strength = <16>; 3052 }; 3053 3054 cmd-pins { 3055 pins = "sdc2_cmd"; 3056 bias-pull-up; 3057 drive-strength = <10>; 3058 }; 3059 3060 data-pins { 3061 pins = "sdc2_data"; 3062 bias-pull-up; 3063 drive-strength = <10>; 3064 }; 3065 }; 3066 }; 3067 3068 apps_smmu: iommu@15000000 { 3069 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3070 reg = <0 0x15000000 0 0x100000>; 3071 #iommu-cells = <2>; 3072 #global-interrupts = <1>; 3073 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3074 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3076 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3077 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3078 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3079 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3080 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3088 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3089 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3090 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3091 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3092 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3095 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3099 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3100 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3101 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3104 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3119 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3124 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3145 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3149 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3150 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3161 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3162 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3163 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3164 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3165 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3166 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3167 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3168 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3169 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 3170 }; 3171 3172 intc: interrupt-controller@17100000 { 3173 compatible = "arm,gic-v3"; 3174 reg = <0 0x17100000 0 0x10000>, /* GICD */ 3175 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 3176 ranges; 3177 #interrupt-cells = <3>; 3178 interrupt-controller; 3179 #redistributor-regions = <1>; 3180 redistributor-stride = <0 0x40000>; 3181 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3182 #address-cells = <2>; 3183 #size-cells = <2>; 3184 3185 gic_its: msi-controller@17140000 { 3186 compatible = "arm,gic-v3-its"; 3187 reg = <0 0x17140000 0 0x20000>; 3188 msi-controller; 3189 #msi-cells = <1>; 3190 }; 3191 }; 3192 3193 timer@17420000 { 3194 compatible = "arm,armv7-timer-mem"; 3195 reg = <0 0x17420000 0 0x1000>; 3196 ranges = <0 0 0 0x20000000>; 3197 #address-cells = <1>; 3198 #size-cells = <1>; 3199 3200 frame@17421000 { 3201 reg = <0x17421000 0x1000>, 3202 <0x17422000 0x1000>; 3203 frame-number = <0>; 3204 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3205 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3206 }; 3207 3208 frame@17423000 { 3209 reg = <0x17423000 0x1000>; 3210 frame-number = <1>; 3211 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3212 status = "disabled"; 3213 }; 3214 3215 frame@17425000 { 3216 reg = <0x17425000 0x1000>; 3217 frame-number = <2>; 3218 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3219 status = "disabled"; 3220 }; 3221 3222 frame@17427000 { 3223 reg = <0x17427000 0x1000>; 3224 frame-number = <3>; 3225 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3226 status = "disabled"; 3227 }; 3228 3229 frame@17429000 { 3230 reg = <0x17429000 0x1000>; 3231 frame-number = <4>; 3232 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3233 status = "disabled"; 3234 }; 3235 3236 frame@1742b000 { 3237 reg = <0x1742b000 0x1000>; 3238 frame-number = <5>; 3239 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3240 status = "disabled"; 3241 }; 3242 3243 frame@1742d000 { 3244 reg = <0x1742d000 0x1000>; 3245 frame-number = <6>; 3246 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3247 status = "disabled"; 3248 }; 3249 }; 3250 3251 apps_rsc: rsc@17a00000 { 3252 label = "apps_rsc"; 3253 compatible = "qcom,rpmh-rsc"; 3254 reg = <0 0x17a00000 0 0x10000>, 3255 <0 0x17a10000 0 0x10000>, 3256 <0 0x17a20000 0 0x10000>, 3257 <0 0x17a30000 0 0x10000>; 3258 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3259 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3262 qcom,tcs-offset = <0xd00>; 3263 qcom,drv-id = <2>; 3264 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3265 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3266 3267 apps_bcm_voter: bcm-voter { 3268 compatible = "qcom,bcm-voter"; 3269 }; 3270 3271 rpmhcc: clock-controller { 3272 compatible = "qcom,sm8550-rpmh-clk"; 3273 #clock-cells = <1>; 3274 clock-names = "xo"; 3275 clocks = <&xo_board>; 3276 }; 3277 3278 rpmhpd: power-controller { 3279 compatible = "qcom,sm8550-rpmhpd"; 3280 #power-domain-cells = <1>; 3281 operating-points-v2 = <&rpmhpd_opp_table>; 3282 3283 rpmhpd_opp_table: opp-table { 3284 compatible = "operating-points-v2"; 3285 3286 rpmhpd_opp_ret: opp1 { 3287 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3288 }; 3289 3290 rpmhpd_opp_min_svs: opp2 { 3291 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3292 }; 3293 3294 rpmhpd_opp_low_svs: opp3 { 3295 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3296 }; 3297 3298 rpmhpd_opp_svs: opp4 { 3299 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3300 }; 3301 3302 rpmhpd_opp_svs_l1: opp5 { 3303 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3304 }; 3305 3306 rpmhpd_opp_nom: opp6 { 3307 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3308 }; 3309 3310 rpmhpd_opp_nom_l1: opp7 { 3311 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3312 }; 3313 3314 rpmhpd_opp_nom_l2: opp8 { 3315 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3316 }; 3317 3318 rpmhpd_opp_turbo: opp9 { 3319 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3320 }; 3321 3322 rpmhpd_opp_turbo_l1: opp10 { 3323 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3324 }; 3325 }; 3326 }; 3327 }; 3328 3329 cpufreq_hw: cpufreq@17d91000 { 3330 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 3331 reg = <0 0x17d91000 0 0x1000>, 3332 <0 0x17d92000 0 0x1000>, 3333 <0 0x17d93000 0 0x1000>; 3334 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3335 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 3336 clock-names = "xo", "alternate"; 3337 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3340 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 3341 #freq-domain-cells = <1>; 3342 }; 3343 3344 pmu@24091000 { 3345 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3346 reg = <0 0x24091000 0 0x1000>; 3347 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3348 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3349 3350 operating-points-v2 = <&llcc_bwmon_opp_table>; 3351 3352 llcc_bwmon_opp_table: opp-table { 3353 compatible = "operating-points-v2"; 3354 3355 opp-0 { 3356 opp-peak-kBps = <2086000>; 3357 }; 3358 3359 opp-1 { 3360 opp-peak-kBps = <2929000>; 3361 }; 3362 3363 opp-2 { 3364 opp-peak-kBps = <5931000>; 3365 }; 3366 3367 opp-3 { 3368 opp-peak-kBps = <6515000>; 3369 }; 3370 3371 opp-4 { 3372 opp-peak-kBps = <7980000>; 3373 }; 3374 3375 opp-5 { 3376 opp-peak-kBps = <10437000>; 3377 }; 3378 3379 opp-6 { 3380 opp-peak-kBps = <12157000>; 3381 }; 3382 3383 opp-7 { 3384 opp-peak-kBps = <14060000>; 3385 }; 3386 3387 opp-8 { 3388 opp-peak-kBps = <16113000>; 3389 }; 3390 }; 3391 }; 3392 3393 pmu@240b6400 { 3394 compatible = "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon"; 3395 reg = <0 0x240b6400 0 0x600>; 3396 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3397 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3398 3399 operating-points-v2 = <&cpu_bwmon_opp_table>; 3400 3401 cpu_bwmon_opp_table: opp-table { 3402 compatible = "operating-points-v2"; 3403 3404 opp-0 { 3405 opp-peak-kBps = <4577000>; 3406 }; 3407 3408 opp-1 { 3409 opp-peak-kBps = <7110000>; 3410 }; 3411 3412 opp-2 { 3413 opp-peak-kBps = <9155000>; 3414 }; 3415 3416 opp-3 { 3417 opp-peak-kBps = <12298000>; 3418 }; 3419 3420 opp-4 { 3421 opp-peak-kBps = <14236000>; 3422 }; 3423 3424 opp-5 { 3425 opp-peak-kBps = <16265000>; 3426 }; 3427 }; 3428 }; 3429 3430 gem_noc: interconnect@24100000 { 3431 compatible = "qcom,sm8550-gem-noc"; 3432 reg = <0 0x24100000 0 0xbb800>; 3433 #interconnect-cells = <2>; 3434 qcom,bcm-voters = <&apps_bcm_voter>; 3435 }; 3436 3437 system-cache-controller@25000000 { 3438 compatible = "qcom,sm8550-llcc"; 3439 reg = <0 0x25000000 0 0x800000>, 3440 <0 0x25800000 0 0x200000>; 3441 reg-names = "llcc_base", "llcc_broadcast_base"; 3442 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3443 }; 3444 3445 remoteproc_adsp: remoteproc@30000000 { 3446 compatible = "qcom,sm8550-adsp-pas"; 3447 reg = <0x0 0x30000000 0x0 0x100>; 3448 3449 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3450 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3451 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3452 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3453 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3454 interrupt-names = "wdog", "fatal", "ready", 3455 "handover", "stop-ack"; 3456 3457 clocks = <&rpmhcc RPMH_CXO_CLK>; 3458 clock-names = "xo"; 3459 3460 power-domains = <&rpmhpd SM8550_LCX>, 3461 <&rpmhpd SM8550_LMX>; 3462 power-domain-names = "lcx", "lmx"; 3463 3464 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 3465 3466 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 3467 3468 qcom,qmp = <&aoss_qmp>; 3469 3470 qcom,smem-states = <&smp2p_adsp_out 0>; 3471 qcom,smem-state-names = "stop"; 3472 3473 status = "disabled"; 3474 3475 remoteproc_adsp_glink: glink-edge { 3476 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3477 IPCC_MPROC_SIGNAL_GLINK_QMP 3478 IRQ_TYPE_EDGE_RISING>; 3479 mboxes = <&ipcc IPCC_CLIENT_LPASS 3480 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3481 3482 label = "lpass"; 3483 qcom,remote-pid = <2>; 3484 3485 fastrpc { 3486 compatible = "qcom,fastrpc"; 3487 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3488 label = "adsp"; 3489 #address-cells = <1>; 3490 #size-cells = <0>; 3491 3492 compute-cb@3 { 3493 compatible = "qcom,fastrpc-compute-cb"; 3494 reg = <3>; 3495 iommus = <&apps_smmu 0x1003 0x80>, 3496 <&apps_smmu 0x1063 0x0>; 3497 }; 3498 3499 compute-cb@4 { 3500 compatible = "qcom,fastrpc-compute-cb"; 3501 reg = <4>; 3502 iommus = <&apps_smmu 0x1004 0x80>, 3503 <&apps_smmu 0x1064 0x0>; 3504 }; 3505 3506 compute-cb@5 { 3507 compatible = "qcom,fastrpc-compute-cb"; 3508 reg = <5>; 3509 iommus = <&apps_smmu 0x1005 0x80>, 3510 <&apps_smmu 0x1065 0x0>; 3511 }; 3512 3513 compute-cb@6 { 3514 compatible = "qcom,fastrpc-compute-cb"; 3515 reg = <6>; 3516 iommus = <&apps_smmu 0x1006 0x80>, 3517 <&apps_smmu 0x1066 0x0>; 3518 }; 3519 3520 compute-cb@7 { 3521 compatible = "qcom,fastrpc-compute-cb"; 3522 reg = <7>; 3523 iommus = <&apps_smmu 0x1007 0x80>, 3524 <&apps_smmu 0x1067 0x0>; 3525 }; 3526 }; 3527 3528 gpr { 3529 compatible = "qcom,gpr"; 3530 qcom,glink-channels = "adsp_apps"; 3531 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 3532 qcom,intents = <512 20>; 3533 #address-cells = <1>; 3534 #size-cells = <0>; 3535 3536 q6apm: service@1 { 3537 compatible = "qcom,q6apm"; 3538 reg = <GPR_APM_MODULE_IID>; 3539 #sound-dai-cells = <0>; 3540 qcom,protection-domain = "avs/audio", 3541 "msm/adsp/audio_pd"; 3542 3543 q6apmdai: dais { 3544 compatible = "qcom,q6apm-dais"; 3545 iommus = <&apps_smmu 0x1001 0x80>, 3546 <&apps_smmu 0x1061 0x0>; 3547 }; 3548 3549 q6apmbedai: bedais { 3550 compatible = "qcom,q6apm-lpass-dais"; 3551 #sound-dai-cells = <1>; 3552 }; 3553 }; 3554 3555 q6prm: service@2 { 3556 compatible = "qcom,q6prm"; 3557 reg = <GPR_PRM_MODULE_IID>; 3558 qcom,protection-domain = "avs/audio", 3559 "msm/adsp/audio_pd"; 3560 3561 q6prmcc: clock-controller { 3562 compatible = "qcom,q6prm-lpass-clocks"; 3563 #clock-cells = <2>; 3564 }; 3565 }; 3566 }; 3567 }; 3568 }; 3569 3570 nsp_noc: interconnect@320c0000 { 3571 compatible = "qcom,sm8550-nsp-noc"; 3572 reg = <0 0x320c0000 0 0xe080>; 3573 #interconnect-cells = <2>; 3574 qcom,bcm-voters = <&apps_bcm_voter>; 3575 }; 3576 3577 remoteproc_cdsp: remoteproc@32300000 { 3578 compatible = "qcom,sm8550-cdsp-pas"; 3579 reg = <0x0 0x32300000 0x0 0x1400000>; 3580 3581 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3582 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3583 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3584 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3585 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3586 interrupt-names = "wdog", "fatal", "ready", 3587 "handover", "stop-ack"; 3588 3589 clocks = <&rpmhcc RPMH_CXO_CLK>; 3590 clock-names = "xo"; 3591 3592 power-domains = <&rpmhpd SM8550_CX>, 3593 <&rpmhpd SM8550_MXC>, 3594 <&rpmhpd SM8550_NSP>; 3595 power-domain-names = "cx", "mxc", "nsp"; 3596 3597 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3598 3599 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 3600 3601 qcom,qmp = <&aoss_qmp>; 3602 3603 qcom,smem-states = <&smp2p_cdsp_out 0>; 3604 qcom,smem-state-names = "stop"; 3605 3606 status = "disabled"; 3607 3608 glink-edge { 3609 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3610 IPCC_MPROC_SIGNAL_GLINK_QMP 3611 IRQ_TYPE_EDGE_RISING>; 3612 mboxes = <&ipcc IPCC_CLIENT_CDSP 3613 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3614 3615 label = "cdsp"; 3616 qcom,remote-pid = <5>; 3617 3618 fastrpc { 3619 compatible = "qcom,fastrpc"; 3620 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3621 label = "cdsp"; 3622 #address-cells = <1>; 3623 #size-cells = <0>; 3624 3625 compute-cb@1 { 3626 compatible = "qcom,fastrpc-compute-cb"; 3627 reg = <1>; 3628 iommus = <&apps_smmu 0x1961 0x0>, 3629 <&apps_smmu 0x0c01 0x20>, 3630 <&apps_smmu 0x19c1 0x10>; 3631 }; 3632 3633 compute-cb@2 { 3634 compatible = "qcom,fastrpc-compute-cb"; 3635 reg = <2>; 3636 iommus = <&apps_smmu 0x1962 0x0>, 3637 <&apps_smmu 0x0c02 0x20>, 3638 <&apps_smmu 0x19c2 0x10>; 3639 }; 3640 3641 compute-cb@3 { 3642 compatible = "qcom,fastrpc-compute-cb"; 3643 reg = <3>; 3644 iommus = <&apps_smmu 0x1963 0x0>, 3645 <&apps_smmu 0x0c03 0x20>, 3646 <&apps_smmu 0x19c3 0x10>; 3647 }; 3648 3649 compute-cb@4 { 3650 compatible = "qcom,fastrpc-compute-cb"; 3651 reg = <4>; 3652 iommus = <&apps_smmu 0x1964 0x0>, 3653 <&apps_smmu 0x0c04 0x20>, 3654 <&apps_smmu 0x19c4 0x10>; 3655 }; 3656 3657 compute-cb@5 { 3658 compatible = "qcom,fastrpc-compute-cb"; 3659 reg = <5>; 3660 iommus = <&apps_smmu 0x1965 0x0>, 3661 <&apps_smmu 0x0c05 0x20>, 3662 <&apps_smmu 0x19c5 0x10>; 3663 }; 3664 3665 compute-cb@6 { 3666 compatible = "qcom,fastrpc-compute-cb"; 3667 reg = <6>; 3668 iommus = <&apps_smmu 0x1966 0x0>, 3669 <&apps_smmu 0x0c06 0x20>, 3670 <&apps_smmu 0x19c6 0x10>; 3671 }; 3672 3673 compute-cb@7 { 3674 compatible = "qcom,fastrpc-compute-cb"; 3675 reg = <7>; 3676 iommus = <&apps_smmu 0x1967 0x0>, 3677 <&apps_smmu 0x0c07 0x20>, 3678 <&apps_smmu 0x19c7 0x10>; 3679 }; 3680 3681 compute-cb@8 { 3682 compatible = "qcom,fastrpc-compute-cb"; 3683 reg = <8>; 3684 iommus = <&apps_smmu 0x1968 0x0>, 3685 <&apps_smmu 0x0c08 0x20>, 3686 <&apps_smmu 0x19c8 0x10>; 3687 }; 3688 3689 /* note: secure cb9 in downstream */ 3690 }; 3691 }; 3692 }; 3693 }; 3694 3695 thermal-zones { 3696 aoss0-thermal { 3697 polling-delay-passive = <0>; 3698 polling-delay = <0>; 3699 thermal-sensors = <&tsens0 0>; 3700 3701 trips { 3702 thermal-engine-config { 3703 temperature = <125000>; 3704 hysteresis = <1000>; 3705 type = "passive"; 3706 }; 3707 3708 reset-mon-config { 3709 temperature = <115000>; 3710 hysteresis = <5000>; 3711 type = "passive"; 3712 }; 3713 }; 3714 }; 3715 3716 cpuss0-thermal { 3717 polling-delay-passive = <0>; 3718 polling-delay = <0>; 3719 thermal-sensors = <&tsens0 1>; 3720 3721 trips { 3722 thermal-engine-config { 3723 temperature = <125000>; 3724 hysteresis = <1000>; 3725 type = "passive"; 3726 }; 3727 3728 reset-mon-config { 3729 temperature = <115000>; 3730 hysteresis = <5000>; 3731 type = "passive"; 3732 }; 3733 }; 3734 }; 3735 3736 cpuss1-thermal { 3737 polling-delay-passive = <0>; 3738 polling-delay = <0>; 3739 thermal-sensors = <&tsens0 2>; 3740 3741 trips { 3742 thermal-engine-config { 3743 temperature = <125000>; 3744 hysteresis = <1000>; 3745 type = "passive"; 3746 }; 3747 3748 reset-mon-config { 3749 temperature = <115000>; 3750 hysteresis = <5000>; 3751 type = "passive"; 3752 }; 3753 }; 3754 }; 3755 3756 cpuss2-thermal { 3757 polling-delay-passive = <0>; 3758 polling-delay = <0>; 3759 thermal-sensors = <&tsens0 3>; 3760 3761 trips { 3762 thermal-engine-config { 3763 temperature = <125000>; 3764 hysteresis = <1000>; 3765 type = "passive"; 3766 }; 3767 3768 reset-mon-config { 3769 temperature = <115000>; 3770 hysteresis = <5000>; 3771 type = "passive"; 3772 }; 3773 }; 3774 }; 3775 3776 cpuss3-thermal { 3777 polling-delay-passive = <0>; 3778 polling-delay = <0>; 3779 thermal-sensors = <&tsens0 4>; 3780 3781 trips { 3782 thermal-engine-config { 3783 temperature = <125000>; 3784 hysteresis = <1000>; 3785 type = "passive"; 3786 }; 3787 3788 reset-mon-config { 3789 temperature = <115000>; 3790 hysteresis = <5000>; 3791 type = "passive"; 3792 }; 3793 }; 3794 }; 3795 3796 cpu3-top-thermal { 3797 polling-delay-passive = <0>; 3798 polling-delay = <0>; 3799 thermal-sensors = <&tsens0 5>; 3800 3801 trips { 3802 cpu3_top_alert0: trip-point0 { 3803 temperature = <90000>; 3804 hysteresis = <2000>; 3805 type = "passive"; 3806 }; 3807 3808 cpu3_top_alert1: trip-point1 { 3809 temperature = <95000>; 3810 hysteresis = <2000>; 3811 type = "passive"; 3812 }; 3813 3814 cpu3_top_crit: cpu-critical { 3815 temperature = <110000>; 3816 hysteresis = <1000>; 3817 type = "critical"; 3818 }; 3819 }; 3820 }; 3821 3822 cpu3-bottom-thermal { 3823 polling-delay-passive = <0>; 3824 polling-delay = <0>; 3825 thermal-sensors = <&tsens0 6>; 3826 3827 trips { 3828 cpu3_bottom_alert0: trip-point0 { 3829 temperature = <90000>; 3830 hysteresis = <2000>; 3831 type = "passive"; 3832 }; 3833 3834 cpu3_bottom_alert1: trip-point1 { 3835 temperature = <95000>; 3836 hysteresis = <2000>; 3837 type = "passive"; 3838 }; 3839 3840 cpu3_bottom_crit: cpu-critical { 3841 temperature = <110000>; 3842 hysteresis = <1000>; 3843 type = "critical"; 3844 }; 3845 }; 3846 }; 3847 3848 cpu4-top-thermal { 3849 polling-delay-passive = <0>; 3850 polling-delay = <0>; 3851 thermal-sensors = <&tsens0 7>; 3852 3853 trips { 3854 cpu4_top_alert0: trip-point0 { 3855 temperature = <90000>; 3856 hysteresis = <2000>; 3857 type = "passive"; 3858 }; 3859 3860 cpu4_top_alert1: trip-point1 { 3861 temperature = <95000>; 3862 hysteresis = <2000>; 3863 type = "passive"; 3864 }; 3865 3866 cpu4_top_crit: cpu-critical { 3867 temperature = <110000>; 3868 hysteresis = <1000>; 3869 type = "critical"; 3870 }; 3871 }; 3872 }; 3873 3874 cpu4-bottom-thermal { 3875 polling-delay-passive = <0>; 3876 polling-delay = <0>; 3877 thermal-sensors = <&tsens0 8>; 3878 3879 trips { 3880 cpu4_bottom_alert0: trip-point0 { 3881 temperature = <90000>; 3882 hysteresis = <2000>; 3883 type = "passive"; 3884 }; 3885 3886 cpu4_bottom_alert1: trip-point1 { 3887 temperature = <95000>; 3888 hysteresis = <2000>; 3889 type = "passive"; 3890 }; 3891 3892 cpu4_bottom_crit: cpu-critical { 3893 temperature = <110000>; 3894 hysteresis = <1000>; 3895 type = "critical"; 3896 }; 3897 }; 3898 }; 3899 3900 cpu5-top-thermal { 3901 polling-delay-passive = <0>; 3902 polling-delay = <0>; 3903 thermal-sensors = <&tsens0 9>; 3904 3905 trips { 3906 cpu5_top_alert0: trip-point0 { 3907 temperature = <90000>; 3908 hysteresis = <2000>; 3909 type = "passive"; 3910 }; 3911 3912 cpu5_top_alert1: trip-point1 { 3913 temperature = <95000>; 3914 hysteresis = <2000>; 3915 type = "passive"; 3916 }; 3917 3918 cpu5_top_crit: cpu-critical { 3919 temperature = <110000>; 3920 hysteresis = <1000>; 3921 type = "critical"; 3922 }; 3923 }; 3924 }; 3925 3926 cpu5-bottom-thermal { 3927 polling-delay-passive = <0>; 3928 polling-delay = <0>; 3929 thermal-sensors = <&tsens0 10>; 3930 3931 trips { 3932 cpu5_bottom_alert0: trip-point0 { 3933 temperature = <90000>; 3934 hysteresis = <2000>; 3935 type = "passive"; 3936 }; 3937 3938 cpu5_bottom_alert1: trip-point1 { 3939 temperature = <95000>; 3940 hysteresis = <2000>; 3941 type = "passive"; 3942 }; 3943 3944 cpu5_bottom_crit: cpu-critical { 3945 temperature = <110000>; 3946 hysteresis = <1000>; 3947 type = "critical"; 3948 }; 3949 }; 3950 }; 3951 3952 cpu6-top-thermal { 3953 polling-delay-passive = <0>; 3954 polling-delay = <0>; 3955 thermal-sensors = <&tsens0 11>; 3956 3957 trips { 3958 cpu6_top_alert0: trip-point0 { 3959 temperature = <90000>; 3960 hysteresis = <2000>; 3961 type = "passive"; 3962 }; 3963 3964 cpu6_top_alert1: trip-point1 { 3965 temperature = <95000>; 3966 hysteresis = <2000>; 3967 type = "passive"; 3968 }; 3969 3970 cpu6_top_crit: cpu-critical { 3971 temperature = <110000>; 3972 hysteresis = <1000>; 3973 type = "critical"; 3974 }; 3975 }; 3976 }; 3977 3978 cpu6-bottom-thermal { 3979 polling-delay-passive = <0>; 3980 polling-delay = <0>; 3981 thermal-sensors = <&tsens0 12>; 3982 3983 trips { 3984 cpu6_bottom_alert0: trip-point0 { 3985 temperature = <90000>; 3986 hysteresis = <2000>; 3987 type = "passive"; 3988 }; 3989 3990 cpu6_bottom_alert1: trip-point1 { 3991 temperature = <95000>; 3992 hysteresis = <2000>; 3993 type = "passive"; 3994 }; 3995 3996 cpu6_bottom_crit: cpu-critical { 3997 temperature = <110000>; 3998 hysteresis = <1000>; 3999 type = "critical"; 4000 }; 4001 }; 4002 }; 4003 4004 cpu7-top-thermal { 4005 polling-delay-passive = <0>; 4006 polling-delay = <0>; 4007 thermal-sensors = <&tsens0 13>; 4008 4009 trips { 4010 cpu7_top_alert0: trip-point0 { 4011 temperature = <90000>; 4012 hysteresis = <2000>; 4013 type = "passive"; 4014 }; 4015 4016 cpu7_top_alert1: trip-point1 { 4017 temperature = <95000>; 4018 hysteresis = <2000>; 4019 type = "passive"; 4020 }; 4021 4022 cpu7_top_crit: cpu-critical { 4023 temperature = <110000>; 4024 hysteresis = <1000>; 4025 type = "critical"; 4026 }; 4027 }; 4028 }; 4029 4030 cpu7-middle-thermal { 4031 polling-delay-passive = <0>; 4032 polling-delay = <0>; 4033 thermal-sensors = <&tsens0 14>; 4034 4035 trips { 4036 cpu7_middle_alert0: trip-point0 { 4037 temperature = <90000>; 4038 hysteresis = <2000>; 4039 type = "passive"; 4040 }; 4041 4042 cpu7_middle_alert1: trip-point1 { 4043 temperature = <95000>; 4044 hysteresis = <2000>; 4045 type = "passive"; 4046 }; 4047 4048 cpu7_middle_crit: cpu-critical { 4049 temperature = <110000>; 4050 hysteresis = <1000>; 4051 type = "critical"; 4052 }; 4053 }; 4054 }; 4055 4056 cpu7-bottom-thermal { 4057 polling-delay-passive = <0>; 4058 polling-delay = <0>; 4059 thermal-sensors = <&tsens0 15>; 4060 4061 trips { 4062 cpu7_bottom_alert0: trip-point0 { 4063 temperature = <90000>; 4064 hysteresis = <2000>; 4065 type = "passive"; 4066 }; 4067 4068 cpu7_bottom_alert1: trip-point1 { 4069 temperature = <95000>; 4070 hysteresis = <2000>; 4071 type = "passive"; 4072 }; 4073 4074 cpu7_bottom_crit: cpu-critical { 4075 temperature = <110000>; 4076 hysteresis = <1000>; 4077 type = "critical"; 4078 }; 4079 }; 4080 }; 4081 4082 aoss1-thermal { 4083 polling-delay-passive = <0>; 4084 polling-delay = <0>; 4085 thermal-sensors = <&tsens1 0>; 4086 4087 trips { 4088 thermal-engine-config { 4089 temperature = <125000>; 4090 hysteresis = <1000>; 4091 type = "passive"; 4092 }; 4093 4094 reset-mon-config { 4095 temperature = <115000>; 4096 hysteresis = <5000>; 4097 type = "passive"; 4098 }; 4099 }; 4100 }; 4101 4102 cpu0-thermal { 4103 polling-delay-passive = <0>; 4104 polling-delay = <0>; 4105 thermal-sensors = <&tsens1 1>; 4106 4107 trips { 4108 cpu0_alert0: trip-point0 { 4109 temperature = <90000>; 4110 hysteresis = <2000>; 4111 type = "passive"; 4112 }; 4113 4114 cpu0_alert1: trip-point1 { 4115 temperature = <95000>; 4116 hysteresis = <2000>; 4117 type = "passive"; 4118 }; 4119 4120 cpu0_crit: cpu-critical { 4121 temperature = <110000>; 4122 hysteresis = <1000>; 4123 type = "critical"; 4124 }; 4125 }; 4126 }; 4127 4128 cpu1-thermal { 4129 polling-delay-passive = <0>; 4130 polling-delay = <0>; 4131 thermal-sensors = <&tsens1 2>; 4132 4133 trips { 4134 cpu1_alert0: trip-point0 { 4135 temperature = <90000>; 4136 hysteresis = <2000>; 4137 type = "passive"; 4138 }; 4139 4140 cpu1_alert1: trip-point1 { 4141 temperature = <95000>; 4142 hysteresis = <2000>; 4143 type = "passive"; 4144 }; 4145 4146 cpu1_crit: cpu-critical { 4147 temperature = <110000>; 4148 hysteresis = <1000>; 4149 type = "critical"; 4150 }; 4151 }; 4152 }; 4153 4154 cpu2-thermal { 4155 polling-delay-passive = <0>; 4156 polling-delay = <0>; 4157 thermal-sensors = <&tsens1 3>; 4158 4159 trips { 4160 cpu2_alert0: trip-point0 { 4161 temperature = <90000>; 4162 hysteresis = <2000>; 4163 type = "passive"; 4164 }; 4165 4166 cpu2_alert1: trip-point1 { 4167 temperature = <95000>; 4168 hysteresis = <2000>; 4169 type = "passive"; 4170 }; 4171 4172 cpu2_crit: cpu-critical { 4173 temperature = <110000>; 4174 hysteresis = <1000>; 4175 type = "critical"; 4176 }; 4177 }; 4178 }; 4179 4180 cdsp0-thermal { 4181 polling-delay-passive = <10>; 4182 polling-delay = <0>; 4183 thermal-sensors = <&tsens2 4>; 4184 4185 trips { 4186 thermal-engine-config { 4187 temperature = <125000>; 4188 hysteresis = <1000>; 4189 type = "passive"; 4190 }; 4191 4192 thermal-hal-config { 4193 temperature = <125000>; 4194 hysteresis = <1000>; 4195 type = "passive"; 4196 }; 4197 4198 reset-mon-config { 4199 temperature = <115000>; 4200 hysteresis = <5000>; 4201 type = "passive"; 4202 }; 4203 4204 cdsp0_junction_config: junction-config { 4205 temperature = <95000>; 4206 hysteresis = <5000>; 4207 type = "passive"; 4208 }; 4209 }; 4210 }; 4211 4212 cdsp1-thermal { 4213 polling-delay-passive = <10>; 4214 polling-delay = <0>; 4215 thermal-sensors = <&tsens2 5>; 4216 4217 trips { 4218 thermal-engine-config { 4219 temperature = <125000>; 4220 hysteresis = <1000>; 4221 type = "passive"; 4222 }; 4223 4224 thermal-hal-config { 4225 temperature = <125000>; 4226 hysteresis = <1000>; 4227 type = "passive"; 4228 }; 4229 4230 reset-mon-config { 4231 temperature = <115000>; 4232 hysteresis = <5000>; 4233 type = "passive"; 4234 }; 4235 4236 cdsp1_junction_config: junction-config { 4237 temperature = <95000>; 4238 hysteresis = <5000>; 4239 type = "passive"; 4240 }; 4241 }; 4242 }; 4243 4244 cdsp2-thermal { 4245 polling-delay-passive = <10>; 4246 polling-delay = <0>; 4247 thermal-sensors = <&tsens2 6>; 4248 4249 trips { 4250 thermal-engine-config { 4251 temperature = <125000>; 4252 hysteresis = <1000>; 4253 type = "passive"; 4254 }; 4255 4256 thermal-hal-config { 4257 temperature = <125000>; 4258 hysteresis = <1000>; 4259 type = "passive"; 4260 }; 4261 4262 reset-mon-config { 4263 temperature = <115000>; 4264 hysteresis = <5000>; 4265 type = "passive"; 4266 }; 4267 4268 cdsp2_junction_config: junction-config { 4269 temperature = <95000>; 4270 hysteresis = <5000>; 4271 type = "passive"; 4272 }; 4273 }; 4274 }; 4275 4276 cdsp3-thermal { 4277 polling-delay-passive = <10>; 4278 polling-delay = <0>; 4279 thermal-sensors = <&tsens2 7>; 4280 4281 trips { 4282 thermal-engine-config { 4283 temperature = <125000>; 4284 hysteresis = <1000>; 4285 type = "passive"; 4286 }; 4287 4288 thermal-hal-config { 4289 temperature = <125000>; 4290 hysteresis = <1000>; 4291 type = "passive"; 4292 }; 4293 4294 reset-mon-config { 4295 temperature = <115000>; 4296 hysteresis = <5000>; 4297 type = "passive"; 4298 }; 4299 4300 cdsp3_junction_config: junction-config { 4301 temperature = <95000>; 4302 hysteresis = <5000>; 4303 type = "passive"; 4304 }; 4305 }; 4306 }; 4307 4308 video-thermal { 4309 polling-delay-passive = <0>; 4310 polling-delay = <0>; 4311 thermal-sensors = <&tsens1 8>; 4312 4313 trips { 4314 thermal-engine-config { 4315 temperature = <125000>; 4316 hysteresis = <1000>; 4317 type = "passive"; 4318 }; 4319 4320 reset-mon-config { 4321 temperature = <115000>; 4322 hysteresis = <5000>; 4323 type = "passive"; 4324 }; 4325 }; 4326 }; 4327 4328 mem-thermal { 4329 polling-delay-passive = <10>; 4330 polling-delay = <0>; 4331 thermal-sensors = <&tsens1 9>; 4332 4333 trips { 4334 thermal-engine-config { 4335 temperature = <125000>; 4336 hysteresis = <1000>; 4337 type = "passive"; 4338 }; 4339 4340 ddr_config0: ddr0-config { 4341 temperature = <90000>; 4342 hysteresis = <5000>; 4343 type = "passive"; 4344 }; 4345 4346 reset-mon-config { 4347 temperature = <115000>; 4348 hysteresis = <5000>; 4349 type = "passive"; 4350 }; 4351 }; 4352 }; 4353 4354 modem0-thermal { 4355 polling-delay-passive = <0>; 4356 polling-delay = <0>; 4357 thermal-sensors = <&tsens1 10>; 4358 4359 trips { 4360 thermal-engine-config { 4361 temperature = <125000>; 4362 hysteresis = <1000>; 4363 type = "passive"; 4364 }; 4365 4366 mdmss0_config0: mdmss0-config0 { 4367 temperature = <102000>; 4368 hysteresis = <3000>; 4369 type = "passive"; 4370 }; 4371 4372 mdmss0_config1: mdmss0-config1 { 4373 temperature = <105000>; 4374 hysteresis = <3000>; 4375 type = "passive"; 4376 }; 4377 4378 reset-mon-config { 4379 temperature = <115000>; 4380 hysteresis = <5000>; 4381 type = "passive"; 4382 }; 4383 }; 4384 }; 4385 4386 modem1-thermal { 4387 polling-delay-passive = <0>; 4388 polling-delay = <0>; 4389 thermal-sensors = <&tsens1 11>; 4390 4391 trips { 4392 thermal-engine-config { 4393 temperature = <125000>; 4394 hysteresis = <1000>; 4395 type = "passive"; 4396 }; 4397 4398 mdmss1_config0: mdmss1-config0 { 4399 temperature = <102000>; 4400 hysteresis = <3000>; 4401 type = "passive"; 4402 }; 4403 4404 mdmss1_config1: mdmss1-config1 { 4405 temperature = <105000>; 4406 hysteresis = <3000>; 4407 type = "passive"; 4408 }; 4409 4410 reset-mon-config { 4411 temperature = <115000>; 4412 hysteresis = <5000>; 4413 type = "passive"; 4414 }; 4415 }; 4416 }; 4417 4418 modem2-thermal { 4419 polling-delay-passive = <0>; 4420 polling-delay = <0>; 4421 thermal-sensors = <&tsens1 12>; 4422 4423 trips { 4424 thermal-engine-config { 4425 temperature = <125000>; 4426 hysteresis = <1000>; 4427 type = "passive"; 4428 }; 4429 4430 mdmss2_config0: mdmss2-config0 { 4431 temperature = <102000>; 4432 hysteresis = <3000>; 4433 type = "passive"; 4434 }; 4435 4436 mdmss2_config1: mdmss2-config1 { 4437 temperature = <105000>; 4438 hysteresis = <3000>; 4439 type = "passive"; 4440 }; 4441 4442 reset-mon-config { 4443 temperature = <115000>; 4444 hysteresis = <5000>; 4445 type = "passive"; 4446 }; 4447 }; 4448 }; 4449 4450 modem3-thermal { 4451 polling-delay-passive = <0>; 4452 polling-delay = <0>; 4453 thermal-sensors = <&tsens1 13>; 4454 4455 trips { 4456 thermal-engine-config { 4457 temperature = <125000>; 4458 hysteresis = <1000>; 4459 type = "passive"; 4460 }; 4461 4462 mdmss3_config0: mdmss3-config0 { 4463 temperature = <102000>; 4464 hysteresis = <3000>; 4465 type = "passive"; 4466 }; 4467 4468 mdmss3_config1: mdmss3-config1 { 4469 temperature = <105000>; 4470 hysteresis = <3000>; 4471 type = "passive"; 4472 }; 4473 4474 reset-mon-config { 4475 temperature = <115000>; 4476 hysteresis = <5000>; 4477 type = "passive"; 4478 }; 4479 }; 4480 }; 4481 4482 camera0-thermal { 4483 polling-delay-passive = <0>; 4484 polling-delay = <0>; 4485 thermal-sensors = <&tsens1 14>; 4486 4487 trips { 4488 thermal-engine-config { 4489 temperature = <125000>; 4490 hysteresis = <1000>; 4491 type = "passive"; 4492 }; 4493 4494 reset-mon-config { 4495 temperature = <115000>; 4496 hysteresis = <5000>; 4497 type = "passive"; 4498 }; 4499 }; 4500 }; 4501 4502 camera1-thermal { 4503 polling-delay-passive = <0>; 4504 polling-delay = <0>; 4505 thermal-sensors = <&tsens1 15>; 4506 4507 trips { 4508 thermal-engine-config { 4509 temperature = <125000>; 4510 hysteresis = <1000>; 4511 type = "passive"; 4512 }; 4513 4514 reset-mon-config { 4515 temperature = <115000>; 4516 hysteresis = <5000>; 4517 type = "passive"; 4518 }; 4519 }; 4520 }; 4521 4522 aoss2-thermal { 4523 polling-delay-passive = <0>; 4524 polling-delay = <0>; 4525 thermal-sensors = <&tsens2 0>; 4526 4527 trips { 4528 thermal-engine-config { 4529 temperature = <125000>; 4530 hysteresis = <1000>; 4531 type = "passive"; 4532 }; 4533 4534 reset-mon-config { 4535 temperature = <115000>; 4536 hysteresis = <5000>; 4537 type = "passive"; 4538 }; 4539 }; 4540 }; 4541 4542 gpuss-0-thermal { 4543 polling-delay-passive = <10>; 4544 polling-delay = <0>; 4545 thermal-sensors = <&tsens2 1>; 4546 4547 trips { 4548 thermal-engine-config { 4549 temperature = <125000>; 4550 hysteresis = <1000>; 4551 type = "passive"; 4552 }; 4553 4554 thermal-hal-config { 4555 temperature = <125000>; 4556 hysteresis = <1000>; 4557 type = "passive"; 4558 }; 4559 4560 reset-mon-config { 4561 temperature = <115000>; 4562 hysteresis = <5000>; 4563 type = "passive"; 4564 }; 4565 4566 gpu0_junction_config: junction-config { 4567 temperature = <95000>; 4568 hysteresis = <5000>; 4569 type = "passive"; 4570 }; 4571 }; 4572 }; 4573 4574 gpuss-1-thermal { 4575 polling-delay-passive = <10>; 4576 polling-delay = <0>; 4577 thermal-sensors = <&tsens2 2>; 4578 4579 trips { 4580 thermal-engine-config { 4581 temperature = <125000>; 4582 hysteresis = <1000>; 4583 type = "passive"; 4584 }; 4585 4586 thermal-hal-config { 4587 temperature = <125000>; 4588 hysteresis = <1000>; 4589 type = "passive"; 4590 }; 4591 4592 reset-mon-config { 4593 temperature = <115000>; 4594 hysteresis = <5000>; 4595 type = "passive"; 4596 }; 4597 4598 gpu1_junction_config: junction-config { 4599 temperature = <95000>; 4600 hysteresis = <5000>; 4601 type = "passive"; 4602 }; 4603 }; 4604 }; 4605 4606 gpuss-2-thermal { 4607 polling-delay-passive = <10>; 4608 polling-delay = <0>; 4609 thermal-sensors = <&tsens2 3>; 4610 4611 trips { 4612 thermal-engine-config { 4613 temperature = <125000>; 4614 hysteresis = <1000>; 4615 type = "passive"; 4616 }; 4617 4618 thermal-hal-config { 4619 temperature = <125000>; 4620 hysteresis = <1000>; 4621 type = "passive"; 4622 }; 4623 4624 reset-mon-config { 4625 temperature = <115000>; 4626 hysteresis = <5000>; 4627 type = "passive"; 4628 }; 4629 4630 gpu2_junction_config: junction-config { 4631 temperature = <95000>; 4632 hysteresis = <5000>; 4633 type = "passive"; 4634 }; 4635 }; 4636 }; 4637 4638 gpuss-3-thermal { 4639 polling-delay-passive = <10>; 4640 polling-delay = <0>; 4641 thermal-sensors = <&tsens2 4>; 4642 4643 trips { 4644 thermal-engine-config { 4645 temperature = <125000>; 4646 hysteresis = <1000>; 4647 type = "passive"; 4648 }; 4649 4650 thermal-hal-config { 4651 temperature = <125000>; 4652 hysteresis = <1000>; 4653 type = "passive"; 4654 }; 4655 4656 reset-mon-config { 4657 temperature = <115000>; 4658 hysteresis = <5000>; 4659 type = "passive"; 4660 }; 4661 4662 gpu3_junction_config: junction-config { 4663 temperature = <95000>; 4664 hysteresis = <5000>; 4665 type = "passive"; 4666 }; 4667 }; 4668 }; 4669 4670 gpuss-4-thermal { 4671 polling-delay-passive = <10>; 4672 polling-delay = <0>; 4673 thermal-sensors = <&tsens2 5>; 4674 4675 trips { 4676 thermal-engine-config { 4677 temperature = <125000>; 4678 hysteresis = <1000>; 4679 type = "passive"; 4680 }; 4681 4682 thermal-hal-config { 4683 temperature = <125000>; 4684 hysteresis = <1000>; 4685 type = "passive"; 4686 }; 4687 4688 reset-mon-config { 4689 temperature = <115000>; 4690 hysteresis = <5000>; 4691 type = "passive"; 4692 }; 4693 4694 gpu4_junction_config: junction-config { 4695 temperature = <95000>; 4696 hysteresis = <5000>; 4697 type = "passive"; 4698 }; 4699 }; 4700 }; 4701 4702 gpuss-5-thermal { 4703 polling-delay-passive = <10>; 4704 polling-delay = <0>; 4705 thermal-sensors = <&tsens2 6>; 4706 4707 trips { 4708 thermal-engine-config { 4709 temperature = <125000>; 4710 hysteresis = <1000>; 4711 type = "passive"; 4712 }; 4713 4714 thermal-hal-config { 4715 temperature = <125000>; 4716 hysteresis = <1000>; 4717 type = "passive"; 4718 }; 4719 4720 reset-mon-config { 4721 temperature = <115000>; 4722 hysteresis = <5000>; 4723 type = "passive"; 4724 }; 4725 4726 gpu5_junction_config: junction-config { 4727 temperature = <95000>; 4728 hysteresis = <5000>; 4729 type = "passive"; 4730 }; 4731 }; 4732 }; 4733 4734 gpuss-6-thermal { 4735 polling-delay-passive = <10>; 4736 polling-delay = <0>; 4737 thermal-sensors = <&tsens2 7>; 4738 4739 trips { 4740 thermal-engine-config { 4741 temperature = <125000>; 4742 hysteresis = <1000>; 4743 type = "passive"; 4744 }; 4745 4746 thermal-hal-config { 4747 temperature = <125000>; 4748 hysteresis = <1000>; 4749 type = "passive"; 4750 }; 4751 4752 reset-mon-config { 4753 temperature = <115000>; 4754 hysteresis = <5000>; 4755 type = "passive"; 4756 }; 4757 4758 gpu6_junction_config: junction-config { 4759 temperature = <95000>; 4760 hysteresis = <5000>; 4761 type = "passive"; 4762 }; 4763 }; 4764 }; 4765 4766 gpuss-7-thermal { 4767 polling-delay-passive = <10>; 4768 polling-delay = <0>; 4769 thermal-sensors = <&tsens2 8>; 4770 4771 trips { 4772 thermal-engine-config { 4773 temperature = <125000>; 4774 hysteresis = <1000>; 4775 type = "passive"; 4776 }; 4777 4778 thermal-hal-config { 4779 temperature = <125000>; 4780 hysteresis = <1000>; 4781 type = "passive"; 4782 }; 4783 4784 reset-mon-config { 4785 temperature = <115000>; 4786 hysteresis = <5000>; 4787 type = "passive"; 4788 }; 4789 4790 gpu7_junction_config: junction-config { 4791 temperature = <95000>; 4792 hysteresis = <5000>; 4793 type = "passive"; 4794 }; 4795 }; 4796 }; 4797 }; 4798 4799 timer { 4800 compatible = "arm,armv8-timer"; 4801 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4802 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4803 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4804 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4805 }; 4806}; 4807