1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8450-videocc.h> 8#include <dt-bindings/clock/qcom,sm8550-camcc.h> 9#include <dt-bindings/clock/qcom,sm8550-gcc.h> 10#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 11#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 12#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 24#include <dt-bindings/phy/phy-qcom-qmp.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 chosen { }; 34 35 clocks { 36 xo_board: xo-board { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 }; 45 46 bi_tcxo_div2: bi-tcxo-div2-clk { 47 #clock-cells = <0>; 48 compatible = "fixed-factor-clock"; 49 clocks = <&rpmhcc RPMH_CXO_CLK>; 50 clock-mult = <1>; 51 clock-div = <2>; 52 }; 53 54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 55 #clock-cells = <0>; 56 compatible = "fixed-factor-clock"; 57 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 58 clock-mult = <1>; 59 clock-div = <2>; 60 }; 61 62 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 }; 66 }; 67 68 cpus { 69 #address-cells = <2>; 70 #size-cells = <0>; 71 72 CPU0: cpu@0 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a510"; 75 reg = <0 0>; 76 clocks = <&cpufreq_hw 0>; 77 enable-method = "psci"; 78 next-level-cache = <&L2_0>; 79 power-domains = <&CPU_PD0>; 80 power-domain-names = "psci"; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 capacity-dmips-mhz = <1024>; 83 dynamic-power-coefficient = <100>; 84 #cooling-cells = <2>; 85 L2_0: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 cache-unified; 89 next-level-cache = <&L3_0>; 90 L3_0: l3-cache { 91 compatible = "cache"; 92 cache-level = <3>; 93 cache-unified; 94 }; 95 }; 96 }; 97 98 CPU1: cpu@100 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a510"; 101 reg = <0 0x100>; 102 clocks = <&cpufreq_hw 0>; 103 enable-method = "psci"; 104 next-level-cache = <&L2_100>; 105 power-domains = <&CPU_PD1>; 106 power-domain-names = "psci"; 107 qcom,freq-domain = <&cpufreq_hw 0>; 108 capacity-dmips-mhz = <1024>; 109 dynamic-power-coefficient = <100>; 110 #cooling-cells = <2>; 111 L2_100: l2-cache { 112 compatible = "cache"; 113 cache-level = <2>; 114 cache-unified; 115 next-level-cache = <&L3_0>; 116 }; 117 }; 118 119 CPU2: cpu@200 { 120 device_type = "cpu"; 121 compatible = "arm,cortex-a510"; 122 reg = <0 0x200>; 123 clocks = <&cpufreq_hw 0>; 124 enable-method = "psci"; 125 next-level-cache = <&L2_200>; 126 power-domains = <&CPU_PD2>; 127 power-domain-names = "psci"; 128 qcom,freq-domain = <&cpufreq_hw 0>; 129 capacity-dmips-mhz = <1024>; 130 dynamic-power-coefficient = <100>; 131 #cooling-cells = <2>; 132 L2_200: l2-cache { 133 compatible = "cache"; 134 cache-level = <2>; 135 cache-unified; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU3: cpu@300 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-a715"; 143 reg = <0 0x300>; 144 clocks = <&cpufreq_hw 1>; 145 enable-method = "psci"; 146 next-level-cache = <&L2_300>; 147 power-domains = <&CPU_PD3>; 148 power-domain-names = "psci"; 149 qcom,freq-domain = <&cpufreq_hw 1>; 150 capacity-dmips-mhz = <1792>; 151 dynamic-power-coefficient = <270>; 152 #cooling-cells = <2>; 153 L2_300: l2-cache { 154 compatible = "cache"; 155 cache-level = <2>; 156 cache-unified; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 161 CPU4: cpu@400 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-a715"; 164 reg = <0 0x400>; 165 clocks = <&cpufreq_hw 1>; 166 enable-method = "psci"; 167 next-level-cache = <&L2_400>; 168 power-domains = <&CPU_PD4>; 169 power-domain-names = "psci"; 170 qcom,freq-domain = <&cpufreq_hw 1>; 171 capacity-dmips-mhz = <1792>; 172 dynamic-power-coefficient = <270>; 173 #cooling-cells = <2>; 174 L2_400: l2-cache { 175 compatible = "cache"; 176 cache-level = <2>; 177 cache-unified; 178 next-level-cache = <&L3_0>; 179 }; 180 }; 181 182 CPU5: cpu@500 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a710"; 185 reg = <0 0x500>; 186 clocks = <&cpufreq_hw 1>; 187 enable-method = "psci"; 188 next-level-cache = <&L2_500>; 189 power-domains = <&CPU_PD5>; 190 power-domain-names = "psci"; 191 qcom,freq-domain = <&cpufreq_hw 1>; 192 capacity-dmips-mhz = <1792>; 193 dynamic-power-coefficient = <270>; 194 #cooling-cells = <2>; 195 L2_500: l2-cache { 196 compatible = "cache"; 197 cache-level = <2>; 198 cache-unified; 199 next-level-cache = <&L3_0>; 200 }; 201 }; 202 203 CPU6: cpu@600 { 204 device_type = "cpu"; 205 compatible = "arm,cortex-a710"; 206 reg = <0 0x600>; 207 clocks = <&cpufreq_hw 1>; 208 enable-method = "psci"; 209 next-level-cache = <&L2_600>; 210 power-domains = <&CPU_PD6>; 211 power-domain-names = "psci"; 212 qcom,freq-domain = <&cpufreq_hw 1>; 213 capacity-dmips-mhz = <1792>; 214 dynamic-power-coefficient = <270>; 215 #cooling-cells = <2>; 216 L2_600: l2-cache { 217 compatible = "cache"; 218 cache-level = <2>; 219 cache-unified; 220 next-level-cache = <&L3_0>; 221 }; 222 }; 223 224 CPU7: cpu@700 { 225 device_type = "cpu"; 226 compatible = "arm,cortex-x3"; 227 reg = <0 0x700>; 228 clocks = <&cpufreq_hw 2>; 229 enable-method = "psci"; 230 next-level-cache = <&L2_700>; 231 power-domains = <&CPU_PD7>; 232 power-domain-names = "psci"; 233 qcom,freq-domain = <&cpufreq_hw 2>; 234 capacity-dmips-mhz = <1894>; 235 dynamic-power-coefficient = <588>; 236 #cooling-cells = <2>; 237 L2_700: l2-cache { 238 compatible = "cache"; 239 cache-level = <2>; 240 cache-unified; 241 next-level-cache = <&L3_0>; 242 }; 243 }; 244 245 cpu-map { 246 cluster0 { 247 core0 { 248 cpu = <&CPU0>; 249 }; 250 251 core1 { 252 cpu = <&CPU1>; 253 }; 254 255 core2 { 256 cpu = <&CPU2>; 257 }; 258 259 core3 { 260 cpu = <&CPU3>; 261 }; 262 263 core4 { 264 cpu = <&CPU4>; 265 }; 266 267 core5 { 268 cpu = <&CPU5>; 269 }; 270 271 core6 { 272 cpu = <&CPU6>; 273 }; 274 275 core7 { 276 cpu = <&CPU7>; 277 }; 278 }; 279 }; 280 281 idle-states { 282 entry-method = "psci"; 283 284 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 285 compatible = "arm,idle-state"; 286 idle-state-name = "silver-rail-power-collapse"; 287 arm,psci-suspend-param = <0x40000004>; 288 entry-latency-us = <550>; 289 exit-latency-us = <750>; 290 min-residency-us = <6700>; 291 local-timer-stop; 292 }; 293 294 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 295 compatible = "arm,idle-state"; 296 idle-state-name = "gold-rail-power-collapse"; 297 arm,psci-suspend-param = <0x40000004>; 298 entry-latency-us = <600>; 299 exit-latency-us = <1300>; 300 min-residency-us = <8136>; 301 local-timer-stop; 302 }; 303 304 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 { 305 compatible = "arm,idle-state"; 306 idle-state-name = "goldplus-rail-power-collapse"; 307 arm,psci-suspend-param = <0x40000004>; 308 entry-latency-us = <500>; 309 exit-latency-us = <1350>; 310 min-residency-us = <7480>; 311 local-timer-stop; 312 }; 313 }; 314 315 domain-idle-states { 316 CLUSTER_SLEEP_0: cluster-sleep-0 { 317 compatible = "domain-idle-state"; 318 arm,psci-suspend-param = <0x41000044>; 319 entry-latency-us = <750>; 320 exit-latency-us = <2350>; 321 min-residency-us = <9144>; 322 }; 323 324 CLUSTER_SLEEP_1: cluster-sleep-1 { 325 compatible = "domain-idle-state"; 326 arm,psci-suspend-param = <0x4100c344>; 327 entry-latency-us = <2800>; 328 exit-latency-us = <4400>; 329 min-residency-us = <10150>; 330 }; 331 }; 332 }; 333 334 firmware { 335 scm: scm { 336 compatible = "qcom,scm-sm8550", "qcom,scm"; 337 qcom,dload-mode = <&tcsr 0x19000>; 338 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 339 }; 340 }; 341 342 clk_virt: interconnect-0 { 343 compatible = "qcom,sm8550-clk-virt"; 344 #interconnect-cells = <2>; 345 qcom,bcm-voters = <&apps_bcm_voter>; 346 }; 347 348 mc_virt: interconnect-1 { 349 compatible = "qcom,sm8550-mc-virt"; 350 #interconnect-cells = <2>; 351 qcom,bcm-voters = <&apps_bcm_voter>; 352 }; 353 354 memory@a0000000 { 355 device_type = "memory"; 356 /* We expect the bootloader to fill in the size */ 357 reg = <0 0xa0000000 0 0>; 358 }; 359 360 pmu { 361 compatible = "arm,armv8-pmuv3"; 362 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 363 }; 364 365 psci { 366 compatible = "arm,psci-1.0"; 367 method = "smc"; 368 369 CPU_PD0: power-domain-cpu0 { 370 #power-domain-cells = <0>; 371 power-domains = <&CLUSTER_PD>; 372 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 373 }; 374 375 CPU_PD1: power-domain-cpu1 { 376 #power-domain-cells = <0>; 377 power-domains = <&CLUSTER_PD>; 378 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 379 }; 380 381 CPU_PD2: power-domain-cpu2 { 382 #power-domain-cells = <0>; 383 power-domains = <&CLUSTER_PD>; 384 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 385 }; 386 387 CPU_PD3: power-domain-cpu3 { 388 #power-domain-cells = <0>; 389 power-domains = <&CLUSTER_PD>; 390 domain-idle-states = <&BIG_CPU_SLEEP_0>; 391 }; 392 393 CPU_PD4: power-domain-cpu4 { 394 #power-domain-cells = <0>; 395 power-domains = <&CLUSTER_PD>; 396 domain-idle-states = <&BIG_CPU_SLEEP_0>; 397 }; 398 399 CPU_PD5: power-domain-cpu5 { 400 #power-domain-cells = <0>; 401 power-domains = <&CLUSTER_PD>; 402 domain-idle-states = <&BIG_CPU_SLEEP_0>; 403 }; 404 405 CPU_PD6: power-domain-cpu6 { 406 #power-domain-cells = <0>; 407 power-domains = <&CLUSTER_PD>; 408 domain-idle-states = <&BIG_CPU_SLEEP_0>; 409 }; 410 411 CPU_PD7: power-domain-cpu7 { 412 #power-domain-cells = <0>; 413 power-domains = <&CLUSTER_PD>; 414 domain-idle-states = <&PRIME_CPU_SLEEP_0>; 415 }; 416 417 CLUSTER_PD: power-domain-cluster { 418 #power-domain-cells = <0>; 419 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 420 }; 421 }; 422 423 reserved_memory: reserved-memory { 424 #address-cells = <2>; 425 #size-cells = <2>; 426 ranges; 427 428 hyp_mem: hyp-region@80000000 { 429 reg = <0 0x80000000 0 0xa00000>; 430 no-map; 431 }; 432 433 cpusys_vm_mem: cpusys-vm-region@80a00000 { 434 reg = <0 0x80a00000 0 0x400000>; 435 no-map; 436 }; 437 438 hyp_tags_mem: hyp-tags-region@80e00000 { 439 reg = <0 0x80e00000 0 0x3d0000>; 440 no-map; 441 }; 442 443 xbl_sc_mem: xbl-sc-region@d8100000 { 444 reg = <0 0xd8100000 0 0x40000>; 445 no-map; 446 }; 447 448 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 449 reg = <0 0x811d0000 0 0x30000>; 450 no-map; 451 }; 452 453 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 454 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 455 reg = <0 0x81a00000 0 0x260000>; 456 no-map; 457 }; 458 459 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 460 compatible = "qcom,cmd-db"; 461 reg = <0 0x81c60000 0 0x20000>; 462 no-map; 463 }; 464 465 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 466 aop_config_merged_mem: aop-config-merged-region@81c80000 { 467 reg = <0 0x81c80000 0 0x74000>; 468 no-map; 469 }; 470 471 /* secdata region can be reused by apps */ 472 smem: smem@81d00000 { 473 compatible = "qcom,smem"; 474 reg = <0 0x81d00000 0 0x200000>; 475 hwlocks = <&tcsr_mutex 3>; 476 no-map; 477 }; 478 479 adsp_mhi_mem: adsp-mhi-region@81f00000 { 480 reg = <0 0x81f00000 0 0x20000>; 481 no-map; 482 }; 483 484 global_sync_mem: global-sync-region@82600000 { 485 reg = <0 0x82600000 0 0x100000>; 486 no-map; 487 }; 488 489 tz_stat_mem: tz-stat-region@82700000 { 490 reg = <0 0x82700000 0 0x100000>; 491 no-map; 492 }; 493 494 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 495 reg = <0 0x82800000 0 0x4600000>; 496 no-map; 497 }; 498 499 mpss_mem: mpss-region@8a800000 { 500 reg = <0 0x8a800000 0 0x10800000>; 501 no-map; 502 }; 503 504 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 505 reg = <0 0x9b000000 0 0x80000>; 506 no-map; 507 }; 508 509 ipa_fw_mem: ipa-fw-region@9b080000 { 510 reg = <0 0x9b080000 0 0x10000>; 511 no-map; 512 }; 513 514 ipa_gsi_mem: ipa-gsi-region@9b090000 { 515 reg = <0 0x9b090000 0 0xa000>; 516 no-map; 517 }; 518 519 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 520 reg = <0 0x9b09a000 0 0x2000>; 521 no-map; 522 }; 523 524 spss_region_mem: spss-region@9b100000 { 525 reg = <0 0x9b100000 0 0x180000>; 526 no-map; 527 }; 528 529 /* First part of the "SPU secure shared memory" region */ 530 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 531 reg = <0 0x9b280000 0 0x60000>; 532 no-map; 533 }; 534 535 /* Second part of the "SPU secure shared memory" region */ 536 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 537 reg = <0 0x9b2e0000 0 0x20000>; 538 no-map; 539 }; 540 541 camera_mem: camera-region@9b300000 { 542 reg = <0 0x9b300000 0 0x800000>; 543 no-map; 544 }; 545 546 video_mem: video-region@9bb00000 { 547 reg = <0 0x9bb00000 0 0x700000>; 548 no-map; 549 }; 550 551 cvp_mem: cvp-region@9c200000 { 552 reg = <0 0x9c200000 0 0x700000>; 553 no-map; 554 }; 555 556 cdsp_mem: cdsp-region@9c900000 { 557 reg = <0 0x9c900000 0 0x2000000>; 558 no-map; 559 }; 560 561 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 562 reg = <0 0x9e900000 0 0x80000>; 563 no-map; 564 }; 565 566 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 567 reg = <0 0x9e980000 0 0x80000>; 568 no-map; 569 }; 570 571 adspslpi_mem: adspslpi-region@9ea00000 { 572 reg = <0 0x9ea00000 0 0x4080000>; 573 no-map; 574 }; 575 576 /* uefi region can be reused by apps */ 577 578 /* Linux kernel image is loaded at 0xa8000000 */ 579 580 rmtfs_mem: rmtfs-region@d4a80000 { 581 compatible = "qcom,rmtfs-mem"; 582 reg = <0x0 0xd4a80000 0x0 0x280000>; 583 no-map; 584 585 qcom,client-id = <1>; 586 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 587 }; 588 589 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 590 reg = <0 0xd4d00000 0 0x3300000>; 591 no-map; 592 }; 593 594 tz_reserved_mem: tz-reserved-region@d8000000 { 595 reg = <0 0xd8000000 0 0x100000>; 596 no-map; 597 }; 598 599 cpucp_fw_mem: cpucp-fw-region@d8140000 { 600 reg = <0 0xd8140000 0 0x1c0000>; 601 no-map; 602 }; 603 604 qtee_mem: qtee-region@d8300000 { 605 reg = <0 0xd8300000 0 0x500000>; 606 no-map; 607 }; 608 609 ta_mem: ta-region@d8800000 { 610 reg = <0 0xd8800000 0 0x8a00000>; 611 no-map; 612 }; 613 614 tz_tags_mem: tz-tags-region@e1200000 { 615 reg = <0 0xe1200000 0 0x2740000>; 616 no-map; 617 }; 618 619 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 620 reg = <0 0xe6440000 0 0x279000>; 621 no-map; 622 }; 623 624 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 625 reg = <0 0xf3600000 0 0x4aee000>; 626 no-map; 627 }; 628 629 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 630 reg = <0 0xf80ee000 0 0x1000>; 631 no-map; 632 }; 633 634 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 635 reg = <0 0xf80ef000 0 0x9000>; 636 no-map; 637 }; 638 639 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 640 reg = <0 0xf80f8000 0 0x4000>; 641 no-map; 642 }; 643 644 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 645 reg = <0 0xf80fc000 0 0x4000>; 646 no-map; 647 }; 648 649 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 650 reg = <0 0xf8100000 0 0x100000>; 651 no-map; 652 }; 653 654 oem_vm_mem: oem-vm-region@f8400000 { 655 reg = <0 0xf8400000 0 0x4800000>; 656 no-map; 657 }; 658 659 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 660 reg = <0 0xfcc00000 0 0x4000>; 661 no-map; 662 }; 663 664 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 665 reg = <0 0xfcc04000 0 0x100000>; 666 no-map; 667 }; 668 669 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 670 reg = <0 0xfce00000 0 0x2900000>; 671 no-map; 672 }; 673 674 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 675 reg = <0 0xff700000 0 0x100000>; 676 no-map; 677 }; 678 }; 679 680 smp2p-adsp { 681 compatible = "qcom,smp2p"; 682 qcom,smem = <443>, <429>; 683 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 684 IPCC_MPROC_SIGNAL_SMP2P 685 IRQ_TYPE_EDGE_RISING>; 686 mboxes = <&ipcc IPCC_CLIENT_LPASS 687 IPCC_MPROC_SIGNAL_SMP2P>; 688 689 qcom,local-pid = <0>; 690 qcom,remote-pid = <2>; 691 692 smp2p_adsp_out: master-kernel { 693 qcom,entry-name = "master-kernel"; 694 #qcom,smem-state-cells = <1>; 695 }; 696 697 smp2p_adsp_in: slave-kernel { 698 qcom,entry-name = "slave-kernel"; 699 interrupt-controller; 700 #interrupt-cells = <2>; 701 }; 702 }; 703 704 smp2p-cdsp { 705 compatible = "qcom,smp2p"; 706 qcom,smem = <94>, <432>; 707 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 708 IPCC_MPROC_SIGNAL_SMP2P 709 IRQ_TYPE_EDGE_RISING>; 710 mboxes = <&ipcc IPCC_CLIENT_CDSP 711 IPCC_MPROC_SIGNAL_SMP2P>; 712 713 qcom,local-pid = <0>; 714 qcom,remote-pid = <5>; 715 716 smp2p_cdsp_out: master-kernel { 717 qcom,entry-name = "master-kernel"; 718 #qcom,smem-state-cells = <1>; 719 }; 720 721 smp2p_cdsp_in: slave-kernel { 722 qcom,entry-name = "slave-kernel"; 723 interrupt-controller; 724 #interrupt-cells = <2>; 725 }; 726 }; 727 728 smp2p-modem { 729 compatible = "qcom,smp2p"; 730 qcom,smem = <435>, <428>; 731 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 732 IPCC_MPROC_SIGNAL_SMP2P 733 IRQ_TYPE_EDGE_RISING>; 734 mboxes = <&ipcc IPCC_CLIENT_MPSS 735 IPCC_MPROC_SIGNAL_SMP2P>; 736 737 qcom,local-pid = <0>; 738 qcom,remote-pid = <1>; 739 740 smp2p_modem_out: master-kernel { 741 qcom,entry-name = "master-kernel"; 742 #qcom,smem-state-cells = <1>; 743 }; 744 745 smp2p_modem_in: slave-kernel { 746 qcom,entry-name = "slave-kernel"; 747 interrupt-controller; 748 #interrupt-cells = <2>; 749 }; 750 751 ipa_smp2p_out: ipa-ap-to-modem { 752 qcom,entry-name = "ipa"; 753 #qcom,smem-state-cells = <1>; 754 }; 755 756 ipa_smp2p_in: ipa-modem-to-ap { 757 qcom,entry-name = "ipa"; 758 interrupt-controller; 759 #interrupt-cells = <2>; 760 }; 761 }; 762 763 soc: soc@0 { 764 compatible = "simple-bus"; 765 ranges = <0 0 0 0 0x10 0>; 766 dma-ranges = <0 0 0 0 0x10 0>; 767 768 #address-cells = <2>; 769 #size-cells = <2>; 770 771 gcc: clock-controller@100000 { 772 compatible = "qcom,sm8550-gcc"; 773 reg = <0 0x00100000 0 0x1f4200>; 774 #clock-cells = <1>; 775 #reset-cells = <1>; 776 #power-domain-cells = <1>; 777 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 778 <&pcie0_phy>, 779 <&pcie1_phy>, 780 <&pcie_1_phy_aux_clk>, 781 <&ufs_mem_phy 0>, 782 <&ufs_mem_phy 1>, 783 <&ufs_mem_phy 2>, 784 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 785 }; 786 787 ipcc: mailbox@408000 { 788 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 789 reg = <0 0x00408000 0 0x1000>; 790 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 791 interrupt-controller; 792 #interrupt-cells = <3>; 793 #mbox-cells = <2>; 794 }; 795 796 gpi_dma2: dma-controller@800000 { 797 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 798 #dma-cells = <3>; 799 reg = <0 0x00800000 0 0x60000>; 800 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 812 dma-channels = <12>; 813 dma-channel-mask = <0x3e>; 814 iommus = <&apps_smmu 0x436 0>; 815 dma-coherent; 816 status = "disabled"; 817 }; 818 819 qupv3_id_1: geniqup@8c0000 { 820 compatible = "qcom,geni-se-qup"; 821 reg = <0 0x008c0000 0 0x2000>; 822 ranges; 823 clock-names = "m-ahb", "s-ahb"; 824 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 825 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 826 iommus = <&apps_smmu 0x423 0>; 827 dma-coherent; 828 #address-cells = <2>; 829 #size-cells = <2>; 830 status = "disabled"; 831 832 i2c8: i2c@880000 { 833 compatible = "qcom,geni-i2c"; 834 reg = <0 0x00880000 0 0x4000>; 835 clock-names = "se"; 836 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&qup_i2c8_data_clk>; 839 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 843 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 844 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 845 interconnect-names = "qup-core", "qup-config", "qup-memory"; 846 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 847 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 848 dma-names = "tx", "rx"; 849 status = "disabled"; 850 }; 851 852 spi8: spi@880000 { 853 compatible = "qcom,geni-spi"; 854 reg = <0 0x00880000 0 0x4000>; 855 clock-names = "se"; 856 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 857 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 858 pinctrl-names = "default"; 859 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 860 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 861 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 862 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 863 interconnect-names = "qup-core", "qup-config", "qup-memory"; 864 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 865 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 866 dma-names = "tx", "rx"; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 status = "disabled"; 870 }; 871 872 i2c9: i2c@884000 { 873 compatible = "qcom,geni-i2c"; 874 reg = <0 0x00884000 0 0x4000>; 875 clock-names = "se"; 876 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 877 pinctrl-names = "default"; 878 pinctrl-0 = <&qup_i2c9_data_clk>; 879 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 883 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 884 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 885 interconnect-names = "qup-core", "qup-config", "qup-memory"; 886 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 887 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 888 dma-names = "tx", "rx"; 889 status = "disabled"; 890 }; 891 892 spi9: spi@884000 { 893 compatible = "qcom,geni-spi"; 894 reg = <0 0x00884000 0 0x4000>; 895 clock-names = "se"; 896 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 897 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 898 pinctrl-names = "default"; 899 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 900 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 901 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 902 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 903 interconnect-names = "qup-core", "qup-config", "qup-memory"; 904 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 905 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 906 dma-names = "tx", "rx"; 907 #address-cells = <1>; 908 #size-cells = <0>; 909 status = "disabled"; 910 }; 911 912 i2c10: i2c@888000 { 913 compatible = "qcom,geni-i2c"; 914 reg = <0 0x00888000 0 0x4000>; 915 clock-names = "se"; 916 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 917 pinctrl-names = "default"; 918 pinctrl-0 = <&qup_i2c10_data_clk>; 919 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 923 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 924 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 925 interconnect-names = "qup-core", "qup-config", "qup-memory"; 926 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 927 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 928 dma-names = "tx", "rx"; 929 status = "disabled"; 930 }; 931 932 spi10: spi@888000 { 933 compatible = "qcom,geni-spi"; 934 reg = <0 0x00888000 0 0x4000>; 935 clock-names = "se"; 936 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 937 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 938 pinctrl-names = "default"; 939 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 940 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 941 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 942 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 943 interconnect-names = "qup-core", "qup-config", "qup-memory"; 944 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 945 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 946 dma-names = "tx", "rx"; 947 #address-cells = <1>; 948 #size-cells = <0>; 949 status = "disabled"; 950 }; 951 952 i2c11: i2c@88c000 { 953 compatible = "qcom,geni-i2c"; 954 reg = <0 0x0088c000 0 0x4000>; 955 clock-names = "se"; 956 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 957 pinctrl-names = "default"; 958 pinctrl-0 = <&qup_i2c11_data_clk>; 959 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 963 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 964 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 965 interconnect-names = "qup-core", "qup-config", "qup-memory"; 966 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 967 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 968 dma-names = "tx", "rx"; 969 status = "disabled"; 970 }; 971 972 spi11: spi@88c000 { 973 compatible = "qcom,geni-spi"; 974 reg = <0 0x0088c000 0 0x4000>; 975 clock-names = "se"; 976 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 977 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 978 pinctrl-names = "default"; 979 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 980 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 981 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 982 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 983 interconnect-names = "qup-core", "qup-config", "qup-memory"; 984 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 985 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 986 dma-names = "tx", "rx"; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 status = "disabled"; 990 }; 991 992 i2c12: i2c@890000 { 993 compatible = "qcom,geni-i2c"; 994 reg = <0 0x00890000 0 0x4000>; 995 clock-names = "se"; 996 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&qup_i2c12_data_clk>; 999 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1003 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1004 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1005 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1006 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1007 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1008 dma-names = "tx", "rx"; 1009 status = "disabled"; 1010 }; 1011 1012 spi12: spi@890000 { 1013 compatible = "qcom,geni-spi"; 1014 reg = <0 0x00890000 0 0x4000>; 1015 clock-names = "se"; 1016 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1017 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1020 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1021 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1022 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1023 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1024 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1025 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1026 dma-names = "tx", "rx"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 status = "disabled"; 1030 }; 1031 1032 i2c13: i2c@894000 { 1033 compatible = "qcom,geni-i2c"; 1034 reg = <0 0x00894000 0 0x4000>; 1035 clock-names = "se"; 1036 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&qup_i2c13_data_clk>; 1039 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1043 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1044 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1045 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1046 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1047 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1048 dma-names = "tx", "rx"; 1049 status = "disabled"; 1050 }; 1051 1052 spi13: spi@894000 { 1053 compatible = "qcom,geni-spi"; 1054 reg = <0 0x00894000 0 0x4000>; 1055 clock-names = "se"; 1056 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1057 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1060 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1061 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1062 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1063 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1064 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1065 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1066 dma-names = "tx", "rx"; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 uart14: serial@898000 { 1073 compatible = "qcom,geni-uart"; 1074 reg = <0 0x898000 0 0x4000>; 1075 clock-names = "se"; 1076 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1077 pinctrl-names = "default"; 1078 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; 1079 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1080 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1081 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1082 interconnect-names = "qup-core", "qup-config"; 1083 status = "disabled"; 1084 }; 1085 1086 i2c15: i2c@89c000 { 1087 compatible = "qcom,geni-i2c"; 1088 reg = <0 0x0089c000 0 0x4000>; 1089 clock-names = "se"; 1090 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1091 pinctrl-names = "default"; 1092 pinctrl-0 = <&qup_i2c15_data_clk>; 1093 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1097 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1098 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1099 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1100 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1101 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1102 dma-names = "tx", "rx"; 1103 status = "disabled"; 1104 }; 1105 1106 spi15: spi@89c000 { 1107 compatible = "qcom,geni-spi"; 1108 reg = <0 0x0089c000 0 0x4000>; 1109 clock-names = "se"; 1110 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1111 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1114 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1115 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1116 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1117 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1118 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1119 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1120 dma-names = "tx", "rx"; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 }; 1126 1127 i2c_master_hub_0: geniqup@9c0000 { 1128 compatible = "qcom,geni-se-i2c-master-hub"; 1129 reg = <0x0 0x009c0000 0x0 0x2000>; 1130 clock-names = "s-ahb"; 1131 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1132 #address-cells = <2>; 1133 #size-cells = <2>; 1134 ranges; 1135 status = "disabled"; 1136 1137 i2c_hub_0: i2c@980000 { 1138 compatible = "qcom,geni-i2c-master-hub"; 1139 reg = <0x0 0x00980000 0x0 0x4000>; 1140 clock-names = "se", "core"; 1141 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1142 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1143 pinctrl-names = "default"; 1144 pinctrl-0 = <&hub_i2c0_data_clk>; 1145 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1149 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1150 interconnect-names = "qup-core", "qup-config"; 1151 status = "disabled"; 1152 }; 1153 1154 i2c_hub_1: i2c@984000 { 1155 compatible = "qcom,geni-i2c-master-hub"; 1156 reg = <0x0 0x00984000 0x0 0x4000>; 1157 clock-names = "se", "core"; 1158 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1159 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1160 pinctrl-names = "default"; 1161 pinctrl-0 = <&hub_i2c1_data_clk>; 1162 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1166 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1167 interconnect-names = "qup-core", "qup-config"; 1168 status = "disabled"; 1169 }; 1170 1171 i2c_hub_2: i2c@988000 { 1172 compatible = "qcom,geni-i2c-master-hub"; 1173 reg = <0x0 0x00988000 0x0 0x4000>; 1174 clock-names = "se", "core"; 1175 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1176 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1177 pinctrl-names = "default"; 1178 pinctrl-0 = <&hub_i2c2_data_clk>; 1179 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1183 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1184 interconnect-names = "qup-core", "qup-config"; 1185 status = "disabled"; 1186 }; 1187 1188 i2c_hub_3: i2c@98c000 { 1189 compatible = "qcom,geni-i2c-master-hub"; 1190 reg = <0x0 0x0098c000 0x0 0x4000>; 1191 clock-names = "se", "core"; 1192 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1193 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&hub_i2c3_data_clk>; 1196 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1200 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1201 interconnect-names = "qup-core", "qup-config"; 1202 status = "disabled"; 1203 }; 1204 1205 i2c_hub_4: i2c@990000 { 1206 compatible = "qcom,geni-i2c-master-hub"; 1207 reg = <0x0 0x00990000 0x0 0x4000>; 1208 clock-names = "se", "core"; 1209 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1210 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&hub_i2c4_data_clk>; 1213 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1217 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1218 interconnect-names = "qup-core", "qup-config"; 1219 status = "disabled"; 1220 }; 1221 1222 i2c_hub_5: i2c@994000 { 1223 compatible = "qcom,geni-i2c-master-hub"; 1224 reg = <0 0x00994000 0 0x4000>; 1225 clock-names = "se", "core"; 1226 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1227 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1228 pinctrl-names = "default"; 1229 pinctrl-0 = <&hub_i2c5_data_clk>; 1230 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1234 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1235 interconnect-names = "qup-core", "qup-config"; 1236 status = "disabled"; 1237 }; 1238 1239 i2c_hub_6: i2c@998000 { 1240 compatible = "qcom,geni-i2c-master-hub"; 1241 reg = <0 0x00998000 0 0x4000>; 1242 clock-names = "se", "core"; 1243 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1244 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1245 pinctrl-names = "default"; 1246 pinctrl-0 = <&hub_i2c6_data_clk>; 1247 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1251 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1252 interconnect-names = "qup-core", "qup-config"; 1253 status = "disabled"; 1254 }; 1255 1256 i2c_hub_7: i2c@99c000 { 1257 compatible = "qcom,geni-i2c-master-hub"; 1258 reg = <0 0x0099c000 0 0x4000>; 1259 clock-names = "se", "core"; 1260 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1261 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1262 pinctrl-names = "default"; 1263 pinctrl-0 = <&hub_i2c7_data_clk>; 1264 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1268 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1269 interconnect-names = "qup-core", "qup-config"; 1270 status = "disabled"; 1271 }; 1272 1273 i2c_hub_8: i2c@9a0000 { 1274 compatible = "qcom,geni-i2c-master-hub"; 1275 reg = <0 0x009a0000 0 0x4000>; 1276 clock-names = "se", "core"; 1277 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1278 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&hub_i2c8_data_clk>; 1281 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1285 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1286 interconnect-names = "qup-core", "qup-config"; 1287 status = "disabled"; 1288 }; 1289 1290 i2c_hub_9: i2c@9a4000 { 1291 compatible = "qcom,geni-i2c-master-hub"; 1292 reg = <0 0x009a4000 0 0x4000>; 1293 clock-names = "se", "core"; 1294 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1295 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1296 pinctrl-names = "default"; 1297 pinctrl-0 = <&hub_i2c9_data_clk>; 1298 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1302 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1303 interconnect-names = "qup-core", "qup-config"; 1304 status = "disabled"; 1305 }; 1306 }; 1307 1308 gpi_dma1: dma-controller@a00000 { 1309 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1310 #dma-cells = <3>; 1311 reg = <0 0x00a00000 0 0x60000>; 1312 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1313 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1319 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1320 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1324 dma-channels = <12>; 1325 dma-channel-mask = <0x1e>; 1326 iommus = <&apps_smmu 0xb6 0>; 1327 dma-coherent; 1328 status = "disabled"; 1329 }; 1330 1331 qupv3_id_0: geniqup@ac0000 { 1332 compatible = "qcom,geni-se-qup"; 1333 reg = <0 0x00ac0000 0 0x2000>; 1334 ranges; 1335 clock-names = "m-ahb", "s-ahb"; 1336 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1337 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1338 iommus = <&apps_smmu 0xa3 0>; 1339 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1340 interconnect-names = "qup-core"; 1341 dma-coherent; 1342 #address-cells = <2>; 1343 #size-cells = <2>; 1344 status = "disabled"; 1345 1346 i2c0: i2c@a80000 { 1347 compatible = "qcom,geni-i2c"; 1348 reg = <0 0x00a80000 0 0x4000>; 1349 clock-names = "se"; 1350 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1351 pinctrl-names = "default"; 1352 pinctrl-0 = <&qup_i2c0_data_clk>; 1353 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1357 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1358 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1359 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1360 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1361 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1362 dma-names = "tx", "rx"; 1363 status = "disabled"; 1364 }; 1365 1366 spi0: spi@a80000 { 1367 compatible = "qcom,geni-spi"; 1368 reg = <0 0x00a80000 0 0x4000>; 1369 clock-names = "se"; 1370 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1371 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1372 pinctrl-names = "default"; 1373 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1374 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1375 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1376 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1377 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1378 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1379 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1380 dma-names = "tx", "rx"; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 status = "disabled"; 1384 }; 1385 1386 i2c1: i2c@a84000 { 1387 compatible = "qcom,geni-i2c"; 1388 reg = <0 0x00a84000 0 0x4000>; 1389 clock-names = "se"; 1390 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_i2c1_data_clk>; 1393 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1397 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1398 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1399 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1400 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1401 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1402 dma-names = "tx", "rx"; 1403 status = "disabled"; 1404 }; 1405 1406 spi1: spi@a84000 { 1407 compatible = "qcom,geni-spi"; 1408 reg = <0 0x00a84000 0 0x4000>; 1409 clock-names = "se"; 1410 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1411 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1412 pinctrl-names = "default"; 1413 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1414 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1415 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1416 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1417 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1418 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1419 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1420 dma-names = "tx", "rx"; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 status = "disabled"; 1424 }; 1425 1426 i2c2: i2c@a88000 { 1427 compatible = "qcom,geni-i2c"; 1428 reg = <0 0x00a88000 0 0x4000>; 1429 clock-names = "se"; 1430 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1431 pinctrl-names = "default"; 1432 pinctrl-0 = <&qup_i2c2_data_clk>; 1433 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1437 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1438 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1439 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1440 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1441 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1442 dma-names = "tx", "rx"; 1443 status = "disabled"; 1444 }; 1445 1446 spi2: spi@a88000 { 1447 compatible = "qcom,geni-spi"; 1448 reg = <0 0x00a88000 0 0x4000>; 1449 clock-names = "se"; 1450 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1451 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1452 pinctrl-names = "default"; 1453 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1454 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1455 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1456 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1457 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1458 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1459 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1460 dma-names = "tx", "rx"; 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 status = "disabled"; 1464 }; 1465 1466 i2c3: i2c@a8c000 { 1467 compatible = "qcom,geni-i2c"; 1468 reg = <0 0x00a8c000 0 0x4000>; 1469 clock-names = "se"; 1470 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1471 pinctrl-names = "default"; 1472 pinctrl-0 = <&qup_i2c3_data_clk>; 1473 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1477 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1478 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1479 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1480 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1481 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1482 dma-names = "tx", "rx"; 1483 status = "disabled"; 1484 }; 1485 1486 spi3: spi@a8c000 { 1487 compatible = "qcom,geni-spi"; 1488 reg = <0 0x00a8c000 0 0x4000>; 1489 clock-names = "se"; 1490 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1491 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1492 pinctrl-names = "default"; 1493 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1494 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1495 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1496 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1497 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1498 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1499 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1500 dma-names = "tx", "rx"; 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 status = "disabled"; 1504 }; 1505 1506 i2c4: i2c@a90000 { 1507 compatible = "qcom,geni-i2c"; 1508 reg = <0 0x00a90000 0 0x4000>; 1509 clock-names = "se"; 1510 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&qup_i2c4_data_clk>; 1513 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1514 #address-cells = <1>; 1515 #size-cells = <0>; 1516 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1517 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1518 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1519 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1520 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1521 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1522 dma-names = "tx", "rx"; 1523 status = "disabled"; 1524 }; 1525 1526 spi4: spi@a90000 { 1527 compatible = "qcom,geni-spi"; 1528 reg = <0 0x00a90000 0 0x4000>; 1529 clock-names = "se"; 1530 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1531 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1532 pinctrl-names = "default"; 1533 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1534 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1535 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1536 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1537 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1538 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1539 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1540 dma-names = "tx", "rx"; 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 status = "disabled"; 1544 }; 1545 1546 i2c5: i2c@a94000 { 1547 compatible = "qcom,geni-i2c"; 1548 reg = <0 0x00a94000 0 0x4000>; 1549 clock-names = "se"; 1550 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1551 pinctrl-names = "default"; 1552 pinctrl-0 = <&qup_i2c5_data_clk>; 1553 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1554 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1555 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1556 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1557 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1558 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1559 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1560 dma-names = "tx", "rx"; 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 status = "disabled"; 1564 }; 1565 1566 spi5: spi@a94000 { 1567 compatible = "qcom,geni-spi"; 1568 reg = <0 0x00a94000 0 0x4000>; 1569 clock-names = "se"; 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1571 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1572 pinctrl-names = "default"; 1573 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1574 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1575 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1576 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1577 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1578 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1579 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1580 dma-names = "tx", "rx"; 1581 #address-cells = <1>; 1582 #size-cells = <0>; 1583 status = "disabled"; 1584 }; 1585 1586 i2c6: i2c@a98000 { 1587 compatible = "qcom,geni-i2c"; 1588 reg = <0 0x00a98000 0 0x4000>; 1589 clock-names = "se"; 1590 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1591 pinctrl-names = "default"; 1592 pinctrl-0 = <&qup_i2c6_data_clk>; 1593 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1594 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1595 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1596 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1597 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1598 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1599 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1600 dma-names = "tx", "rx"; 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 status = "disabled"; 1604 }; 1605 1606 spi6: spi@a98000 { 1607 compatible = "qcom,geni-spi"; 1608 reg = <0 0x00a98000 0 0x4000>; 1609 clock-names = "se"; 1610 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1611 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1612 pinctrl-names = "default"; 1613 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1614 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1615 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1616 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1617 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1618 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1619 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1620 dma-names = "tx", "rx"; 1621 #address-cells = <1>; 1622 #size-cells = <0>; 1623 status = "disabled"; 1624 }; 1625 1626 uart7: serial@a9c000 { 1627 compatible = "qcom,geni-debug-uart"; 1628 reg = <0 0x00a9c000 0 0x4000>; 1629 clock-names = "se"; 1630 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1631 pinctrl-names = "default"; 1632 pinctrl-0 = <&qup_uart7_default>; 1633 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1634 interconnect-names = "qup-core", "qup-config"; 1635 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1636 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1637 status = "disabled"; 1638 }; 1639 }; 1640 1641 cnoc_main: interconnect@1500000 { 1642 compatible = "qcom,sm8550-cnoc-main"; 1643 reg = <0 0x01500000 0 0x13080>; 1644 #interconnect-cells = <2>; 1645 qcom,bcm-voters = <&apps_bcm_voter>; 1646 }; 1647 1648 config_noc: interconnect@1600000 { 1649 compatible = "qcom,sm8550-config-noc"; 1650 reg = <0 0x01600000 0 0x6200>; 1651 #interconnect-cells = <2>; 1652 qcom,bcm-voters = <&apps_bcm_voter>; 1653 }; 1654 1655 system_noc: interconnect@1680000 { 1656 compatible = "qcom,sm8550-system-noc"; 1657 reg = <0 0x01680000 0 0x1d080>; 1658 #interconnect-cells = <2>; 1659 qcom,bcm-voters = <&apps_bcm_voter>; 1660 }; 1661 1662 pcie_noc: interconnect@16c0000 { 1663 compatible = "qcom,sm8550-pcie-anoc"; 1664 reg = <0 0x016c0000 0 0x12200>; 1665 #interconnect-cells = <2>; 1666 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1667 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1668 qcom,bcm-voters = <&apps_bcm_voter>; 1669 }; 1670 1671 aggre1_noc: interconnect@16e0000 { 1672 compatible = "qcom,sm8550-aggre1-noc"; 1673 reg = <0 0x016e0000 0 0x14400>; 1674 #interconnect-cells = <2>; 1675 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1676 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1677 qcom,bcm-voters = <&apps_bcm_voter>; 1678 }; 1679 1680 aggre2_noc: interconnect@1700000 { 1681 compatible = "qcom,sm8550-aggre2-noc"; 1682 reg = <0 0x01700000 0 0x1e400>; 1683 #interconnect-cells = <2>; 1684 clocks = <&rpmhcc RPMH_IPA_CLK>; 1685 qcom,bcm-voters = <&apps_bcm_voter>; 1686 }; 1687 1688 mmss_noc: interconnect@1780000 { 1689 compatible = "qcom,sm8550-mmss-noc"; 1690 reg = <0 0x01780000 0 0x5b800>; 1691 #interconnect-cells = <2>; 1692 qcom,bcm-voters = <&apps_bcm_voter>; 1693 }; 1694 1695 rng: rng@10c3000 { 1696 compatible = "qcom,sm8550-trng", "qcom,trng"; 1697 reg = <0 0x010c3000 0 0x1000>; 1698 }; 1699 1700 pcie0: pcie@1c00000 { 1701 device_type = "pci"; 1702 compatible = "qcom,pcie-sm8550"; 1703 reg = <0 0x01c00000 0 0x3000>, 1704 <0 0x60000000 0 0xf1d>, 1705 <0 0x60000f20 0 0xa8>, 1706 <0 0x60001000 0 0x1000>, 1707 <0 0x60100000 0 0x100000>; 1708 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1709 #address-cells = <3>; 1710 #size-cells = <2>; 1711 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1712 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1713 bus-range = <0x00 0xff>; 1714 1715 dma-coherent; 1716 1717 linux,pci-domain = <0>; 1718 num-lanes = <2>; 1719 1720 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1728 interrupt-names = "msi0", 1729 "msi1", 1730 "msi2", 1731 "msi3", 1732 "msi4", 1733 "msi5", 1734 "msi6", 1735 "msi7"; 1736 #interrupt-cells = <1>; 1737 interrupt-map-mask = <0 0 0 0x7>; 1738 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1739 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1740 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1741 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1742 1743 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1744 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1745 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1746 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1747 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1748 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1749 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1750 clock-names = "aux", 1751 "cfg", 1752 "bus_master", 1753 "bus_slave", 1754 "slave_q2a", 1755 "ddrss_sf_tbu", 1756 "noc_aggr"; 1757 1758 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 1759 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; 1760 interconnect-names = "pcie-mem", "cpu-pcie"; 1761 1762 msi-map = <0x0 &gic_its 0x1400 0x1>, 1763 <0x100 &gic_its 0x1401 0x1>; 1764 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 1765 <0x100 &apps_smmu 0x1401 0x1>; 1766 1767 resets = <&gcc GCC_PCIE_0_BCR>; 1768 reset-names = "pci"; 1769 1770 power-domains = <&gcc PCIE_0_GDSC>; 1771 1772 phys = <&pcie0_phy>; 1773 phy-names = "pciephy"; 1774 1775 status = "disabled"; 1776 1777 pcie@0 { 1778 device_type = "pci"; 1779 reg = <0x0 0x0 0x0 0x0 0x0>; 1780 bus-range = <0x01 0xff>; 1781 1782 #address-cells = <3>; 1783 #size-cells = <2>; 1784 ranges; 1785 }; 1786 }; 1787 1788 pcie0_phy: phy@1c06000 { 1789 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 1790 reg = <0 0x01c06000 0 0x2000>; 1791 1792 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1793 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1794 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1795 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1796 <&gcc GCC_PCIE_0_PIPE_CLK>; 1797 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1798 "pipe"; 1799 1800 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1801 reset-names = "phy"; 1802 1803 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1804 assigned-clock-rates = <100000000>; 1805 1806 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1807 1808 #clock-cells = <0>; 1809 clock-output-names = "pcie0_pipe_clk"; 1810 1811 #phy-cells = <0>; 1812 1813 status = "disabled"; 1814 }; 1815 1816 pcie1: pcie@1c08000 { 1817 device_type = "pci"; 1818 compatible = "qcom,pcie-sm8550"; 1819 reg = <0x0 0x01c08000 0x0 0x3000>, 1820 <0x0 0x40000000 0x0 0xf1d>, 1821 <0x0 0x40000f20 0x0 0xa8>, 1822 <0x0 0x40001000 0x0 0x1000>, 1823 <0x0 0x40100000 0x0 0x100000>; 1824 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1825 #address-cells = <3>; 1826 #size-cells = <2>; 1827 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1828 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1829 bus-range = <0x00 0xff>; 1830 1831 dma-coherent; 1832 1833 linux,pci-domain = <1>; 1834 num-lanes = <2>; 1835 1836 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1844 interrupt-names = "msi0", 1845 "msi1", 1846 "msi2", 1847 "msi3", 1848 "msi4", 1849 "msi5", 1850 "msi6", 1851 "msi7"; 1852 #interrupt-cells = <1>; 1853 interrupt-map-mask = <0 0 0 0x7>; 1854 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1855 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1856 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1857 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1858 1859 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1860 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1861 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1862 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1863 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1864 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1865 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1866 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 1867 clock-names = "aux", 1868 "cfg", 1869 "bus_master", 1870 "bus_slave", 1871 "slave_q2a", 1872 "ddrss_sf_tbu", 1873 "noc_aggr", 1874 "cnoc_sf_axi"; 1875 1876 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1877 assigned-clock-rates = <19200000>; 1878 1879 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 1880 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; 1881 interconnect-names = "pcie-mem", "cpu-pcie"; 1882 1883 msi-map = <0x0 &gic_its 0x1480 0x1>, 1884 <0x100 &gic_its 0x1481 0x1>; 1885 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 1886 <0x100 &apps_smmu 0x1481 0x1>; 1887 1888 resets = <&gcc GCC_PCIE_1_BCR>, 1889 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1890 reset-names = "pci", "link_down"; 1891 1892 power-domains = <&gcc PCIE_1_GDSC>; 1893 1894 phys = <&pcie1_phy>; 1895 phy-names = "pciephy"; 1896 1897 status = "disabled"; 1898 1899 pcie@0 { 1900 device_type = "pci"; 1901 reg = <0x0 0x0 0x0 0x0 0x0>; 1902 bus-range = <0x01 0xff>; 1903 1904 #address-cells = <3>; 1905 #size-cells = <2>; 1906 ranges; 1907 }; 1908 }; 1909 1910 pcie1_phy: phy@1c0e000 { 1911 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 1912 reg = <0x0 0x01c0e000 0x0 0x2000>; 1913 1914 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1915 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1916 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1917 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1918 <&gcc GCC_PCIE_1_PIPE_CLK>; 1919 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1920 "pipe"; 1921 1922 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 1923 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 1924 reset-names = "phy", "phy_nocsr"; 1925 1926 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1927 assigned-clock-rates = <100000000>; 1928 1929 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1930 1931 #clock-cells = <0>; 1932 clock-output-names = "pcie1_pipe_clk"; 1933 1934 #phy-cells = <0>; 1935 1936 status = "disabled"; 1937 }; 1938 1939 cryptobam: dma-controller@1dc4000 { 1940 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1941 reg = <0x0 0x01dc4000 0x0 0x28000>; 1942 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1943 #dma-cells = <1>; 1944 qcom,ee = <0>; 1945 qcom,controlled-remotely; 1946 iommus = <&apps_smmu 0x480 0x0>, 1947 <&apps_smmu 0x481 0x0>; 1948 }; 1949 1950 crypto: crypto@1dfa000 { 1951 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 1952 reg = <0x0 0x01dfa000 0x0 0x6000>; 1953 dmas = <&cryptobam 4>, <&cryptobam 5>; 1954 dma-names = "rx", "tx"; 1955 iommus = <&apps_smmu 0x480 0x0>, 1956 <&apps_smmu 0x481 0x0>; 1957 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1958 interconnect-names = "memory"; 1959 }; 1960 1961 ufs_mem_phy: phy@1d80000 { 1962 compatible = "qcom,sm8550-qmp-ufs-phy"; 1963 reg = <0x0 0x01d80000 0x0 0x2000>; 1964 clocks = <&rpmhcc RPMH_CXO_CLK>, 1965 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1966 <&tcsr TCSR_UFS_CLKREF_EN>; 1967 clock-names = "ref", 1968 "ref_aux", 1969 "qref"; 1970 1971 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1972 1973 resets = <&ufs_mem_hc 0>; 1974 reset-names = "ufsphy"; 1975 1976 #clock-cells = <1>; 1977 #phy-cells = <0>; 1978 1979 status = "disabled"; 1980 }; 1981 1982 ufs_mem_hc: ufs@1d84000 { 1983 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 1984 "jedec,ufs-2.0"; 1985 reg = <0x0 0x01d84000 0x0 0x3000>; 1986 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1987 phys = <&ufs_mem_phy>; 1988 phy-names = "ufsphy"; 1989 lanes-per-direction = <2>; 1990 #reset-cells = <1>; 1991 resets = <&gcc GCC_UFS_PHY_BCR>; 1992 reset-names = "rst"; 1993 1994 power-domains = <&gcc UFS_PHY_GDSC>; 1995 required-opps = <&rpmhpd_opp_nom>; 1996 1997 iommus = <&apps_smmu 0x60 0x0>; 1998 dma-coherent; 1999 2000 operating-points-v2 = <&ufs_opp_table>; 2001 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 2002 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2003 2004 interconnect-names = "ufs-ddr", "cpu-ufs"; 2005 clock-names = "core_clk", 2006 "bus_aggr_clk", 2007 "iface_clk", 2008 "core_clk_unipro", 2009 "ref_clk", 2010 "tx_lane0_sync_clk", 2011 "rx_lane0_sync_clk", 2012 "rx_lane1_sync_clk"; 2013 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2014 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2015 <&gcc GCC_UFS_PHY_AHB_CLK>, 2016 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2017 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 2018 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2019 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2020 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2021 qcom,ice = <&ice>; 2022 2023 status = "disabled"; 2024 2025 ufs_opp_table: opp-table { 2026 compatible = "operating-points-v2"; 2027 2028 opp-75000000 { 2029 opp-hz = /bits/ 64 <75000000>, 2030 /bits/ 64 <0>, 2031 /bits/ 64 <0>, 2032 /bits/ 64 <75000000>, 2033 /bits/ 64 <0>, 2034 /bits/ 64 <0>, 2035 /bits/ 64 <0>, 2036 /bits/ 64 <0>; 2037 required-opps = <&rpmhpd_opp_low_svs>; 2038 }; 2039 2040 opp-150000000 { 2041 opp-hz = /bits/ 64 <150000000>, 2042 /bits/ 64 <0>, 2043 /bits/ 64 <0>, 2044 /bits/ 64 <150000000>, 2045 /bits/ 64 <0>, 2046 /bits/ 64 <0>, 2047 /bits/ 64 <0>, 2048 /bits/ 64 <0>; 2049 required-opps = <&rpmhpd_opp_svs>; 2050 }; 2051 2052 opp-300000000 { 2053 opp-hz = /bits/ 64 <300000000>, 2054 /bits/ 64 <0>, 2055 /bits/ 64 <0>, 2056 /bits/ 64 <300000000>, 2057 /bits/ 64 <0>, 2058 /bits/ 64 <0>, 2059 /bits/ 64 <0>, 2060 /bits/ 64 <0>; 2061 required-opps = <&rpmhpd_opp_nom>; 2062 }; 2063 }; 2064 }; 2065 2066 ice: crypto@1d88000 { 2067 compatible = "qcom,sm8550-inline-crypto-engine", 2068 "qcom,inline-crypto-engine"; 2069 reg = <0 0x01d88000 0 0x8000>; 2070 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2071 }; 2072 2073 tcsr_mutex: hwlock@1f40000 { 2074 compatible = "qcom,tcsr-mutex"; 2075 reg = <0 0x01f40000 0 0x20000>; 2076 #hwlock-cells = <1>; 2077 }; 2078 2079 tcsr: clock-controller@1fc0000 { 2080 compatible = "qcom,sm8550-tcsr", "syscon"; 2081 reg = <0 0x01fc0000 0 0x30000>; 2082 clocks = <&rpmhcc RPMH_CXO_CLK>; 2083 #clock-cells = <1>; 2084 #reset-cells = <1>; 2085 }; 2086 2087 gpu: gpu@3d00000 { 2088 compatible = "qcom,adreno-43050a01", "qcom,adreno"; 2089 reg = <0x0 0x03d00000 0x0 0x40000>, 2090 <0x0 0x03d9e000 0x0 0x1000>, 2091 <0x0 0x03d61000 0x0 0x800>; 2092 reg-names = "kgsl_3d0_reg_memory", 2093 "cx_mem", 2094 "cx_dbgc"; 2095 2096 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2097 2098 iommus = <&adreno_smmu 0 0x0>, 2099 <&adreno_smmu 1 0x0>; 2100 2101 operating-points-v2 = <&gpu_opp_table>; 2102 2103 qcom,gmu = <&gmu>; 2104 #cooling-cells = <2>; 2105 2106 status = "disabled"; 2107 2108 zap-shader { 2109 memory-region = <&gpu_micro_code_mem>; 2110 }; 2111 2112 /* Speedbin needs more work on A740+, keep only lower freqs */ 2113 gpu_opp_table: opp-table { 2114 compatible = "operating-points-v2"; 2115 2116 opp-680000000 { 2117 opp-hz = /bits/ 64 <680000000>; 2118 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2119 }; 2120 2121 opp-615000000 { 2122 opp-hz = /bits/ 64 <615000000>; 2123 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2124 }; 2125 2126 opp-550000000 { 2127 opp-hz = /bits/ 64 <550000000>; 2128 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2129 }; 2130 2131 opp-475000000 { 2132 opp-hz = /bits/ 64 <475000000>; 2133 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2134 }; 2135 2136 opp-401000000 { 2137 opp-hz = /bits/ 64 <401000000>; 2138 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2139 }; 2140 2141 opp-348000000 { 2142 opp-hz = /bits/ 64 <348000000>; 2143 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 2144 }; 2145 2146 opp-295000000 { 2147 opp-hz = /bits/ 64 <295000000>; 2148 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2149 }; 2150 2151 opp-220000000 { 2152 opp-hz = /bits/ 64 <220000000>; 2153 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 2154 }; 2155 }; 2156 }; 2157 2158 gmu: gmu@3d6a000 { 2159 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu"; 2160 reg = <0x0 0x03d6a000 0x0 0x35000>, 2161 <0x0 0x03d50000 0x0 0x10000>, 2162 <0x0 0x0b280000 0x0 0x10000>; 2163 reg-names = "gmu", "rscc", "gmu_pdc"; 2164 2165 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2167 interrupt-names = "hfi", "gmu"; 2168 2169 clocks = <&gpucc GPU_CC_AHB_CLK>, 2170 <&gpucc GPU_CC_CX_GMU_CLK>, 2171 <&gpucc GPU_CC_CXO_CLK>, 2172 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2173 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2174 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2175 <&gpucc GPU_CC_DEMET_CLK>; 2176 clock-names = "ahb", 2177 "gmu", 2178 "cxo", 2179 "axi", 2180 "memnoc", 2181 "hub", 2182 "demet"; 2183 2184 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2185 <&gpucc GPU_CC_GX_GDSC>; 2186 power-domain-names = "cx", 2187 "gx"; 2188 2189 iommus = <&adreno_smmu 5 0x0>; 2190 2191 qcom,qmp = <&aoss_qmp>; 2192 2193 operating-points-v2 = <&gmu_opp_table>; 2194 2195 gmu_opp_table: opp-table { 2196 compatible = "operating-points-v2"; 2197 2198 opp-500000000 { 2199 opp-hz = /bits/ 64 <500000000>; 2200 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2201 }; 2202 2203 opp-200000000 { 2204 opp-hz = /bits/ 64 <200000000>; 2205 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2206 }; 2207 }; 2208 }; 2209 2210 gpucc: clock-controller@3d90000 { 2211 compatible = "qcom,sm8550-gpucc"; 2212 reg = <0 0x03d90000 0 0xa000>; 2213 clocks = <&bi_tcxo_div2>, 2214 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2215 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2216 #clock-cells = <1>; 2217 #reset-cells = <1>; 2218 #power-domain-cells = <1>; 2219 }; 2220 2221 adreno_smmu: iommu@3da0000 { 2222 compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", 2223 "qcom,smmu-500", "arm,mmu-500"; 2224 reg = <0x0 0x03da0000 0x0 0x40000>; 2225 #iommu-cells = <2>; 2226 #global-interrupts = <1>; 2227 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2228 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>, 2229 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2231 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2236 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2237 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2238 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2239 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2240 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2241 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2242 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2243 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2244 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2245 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2246 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2247 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2248 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2249 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2250 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2251 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2252 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 2253 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2254 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2255 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2256 <&gpucc GPU_CC_AHB_CLK>; 2257 clock-names = "hlos", 2258 "bus", 2259 "iface", 2260 "ahb"; 2261 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2262 dma-coherent; 2263 }; 2264 2265 ipa: ipa@3f40000 { 2266 compatible = "qcom,sm8550-ipa"; 2267 2268 iommus = <&apps_smmu 0x4a0 0x0>, 2269 <&apps_smmu 0x4a2 0x0>; 2270 reg = <0 0x3f40000 0 0x10000>, 2271 <0 0x3f50000 0 0x5000>, 2272 <0 0x3e04000 0 0xfc000>; 2273 reg-names = "ipa-reg", 2274 "ipa-shared", 2275 "gsi"; 2276 2277 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2278 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2279 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2280 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2281 interrupt-names = "ipa", 2282 "gsi", 2283 "ipa-clock-query", 2284 "ipa-setup-ready"; 2285 2286 clocks = <&rpmhcc RPMH_IPA_CLK>; 2287 clock-names = "core"; 2288 2289 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2290 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 2291 interconnect-names = "memory", 2292 "config"; 2293 2294 qcom,qmp = <&aoss_qmp>; 2295 2296 qcom,smem-states = <&ipa_smp2p_out 0>, 2297 <&ipa_smp2p_out 1>; 2298 qcom,smem-state-names = "ipa-clock-enabled-valid", 2299 "ipa-clock-enabled"; 2300 2301 status = "disabled"; 2302 }; 2303 2304 remoteproc_mpss: remoteproc@4080000 { 2305 compatible = "qcom,sm8550-mpss-pas"; 2306 reg = <0x0 0x04080000 0x0 0x4040>; 2307 2308 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2309 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2310 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2311 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2312 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2313 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2314 interrupt-names = "wdog", "fatal", "ready", "handover", 2315 "stop-ack", "shutdown-ack"; 2316 2317 clocks = <&rpmhcc RPMH_CXO_CLK>; 2318 clock-names = "xo"; 2319 2320 power-domains = <&rpmhpd RPMHPD_CX>, 2321 <&rpmhpd RPMHPD_MSS>; 2322 power-domain-names = "cx", "mss"; 2323 2324 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2325 2326 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 2327 2328 qcom,qmp = <&aoss_qmp>; 2329 2330 qcom,smem-states = <&smp2p_modem_out 0>; 2331 qcom,smem-state-names = "stop"; 2332 2333 status = "disabled"; 2334 2335 glink-edge { 2336 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2337 IPCC_MPROC_SIGNAL_GLINK_QMP 2338 IRQ_TYPE_EDGE_RISING>; 2339 mboxes = <&ipcc IPCC_CLIENT_MPSS 2340 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2341 label = "mpss"; 2342 qcom,remote-pid = <1>; 2343 }; 2344 }; 2345 2346 lpass_wsa2macro: codec@6aa0000 { 2347 compatible = "qcom,sm8550-lpass-wsa-macro"; 2348 reg = <0 0x06aa0000 0 0x1000>; 2349 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2350 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2351 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2352 <&lpass_vamacro>; 2353 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2354 2355 #clock-cells = <0>; 2356 clock-output-names = "wsa2-mclk"; 2357 #sound-dai-cells = <1>; 2358 }; 2359 2360 swr3: soundwire@6ab0000 { 2361 compatible = "qcom,soundwire-v2.0.0"; 2362 reg = <0 0x06ab0000 0 0x10000>; 2363 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2364 clocks = <&lpass_wsa2macro>; 2365 clock-names = "iface"; 2366 label = "WSA2"; 2367 2368 pinctrl-0 = <&wsa2_swr_active>; 2369 pinctrl-names = "default"; 2370 2371 qcom,din-ports = <4>; 2372 qcom,dout-ports = <9>; 2373 2374 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2375 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2376 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2377 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2378 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2379 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2380 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2381 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2382 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2383 2384 #address-cells = <2>; 2385 #size-cells = <0>; 2386 #sound-dai-cells = <1>; 2387 status = "disabled"; 2388 }; 2389 2390 lpass_rxmacro: codec@6ac0000 { 2391 compatible = "qcom,sm8550-lpass-rx-macro"; 2392 reg = <0 0x06ac0000 0 0x1000>; 2393 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2394 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2395 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2396 <&lpass_vamacro>; 2397 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2398 2399 #clock-cells = <0>; 2400 clock-output-names = "mclk"; 2401 #sound-dai-cells = <1>; 2402 }; 2403 2404 swr1: soundwire@6ad0000 { 2405 compatible = "qcom,soundwire-v2.0.0"; 2406 reg = <0 0x06ad0000 0 0x10000>; 2407 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2408 clocks = <&lpass_rxmacro>; 2409 clock-names = "iface"; 2410 label = "RX"; 2411 2412 pinctrl-0 = <&rx_swr_active>; 2413 pinctrl-names = "default"; 2414 2415 qcom,din-ports = <1>; 2416 qcom,dout-ports = <11>; 2417 2418 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>; 2419 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2420 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2421 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2422 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2423 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>; 2424 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2425 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2426 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2427 2428 #address-cells = <2>; 2429 #size-cells = <0>; 2430 #sound-dai-cells = <1>; 2431 status = "disabled"; 2432 }; 2433 2434 lpass_txmacro: codec@6ae0000 { 2435 compatible = "qcom,sm8550-lpass-tx-macro"; 2436 reg = <0 0x06ae0000 0 0x1000>; 2437 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2438 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2439 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2440 <&lpass_vamacro>; 2441 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2442 2443 #clock-cells = <0>; 2444 clock-output-names = "mclk"; 2445 #sound-dai-cells = <1>; 2446 }; 2447 2448 lpass_wsamacro: codec@6b00000 { 2449 compatible = "qcom,sm8550-lpass-wsa-macro"; 2450 reg = <0 0x06b00000 0 0x1000>; 2451 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2452 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2453 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2454 <&lpass_vamacro>; 2455 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2456 2457 #clock-cells = <0>; 2458 clock-output-names = "mclk"; 2459 #sound-dai-cells = <1>; 2460 }; 2461 2462 swr0: soundwire@6b10000 { 2463 compatible = "qcom,soundwire-v2.0.0"; 2464 reg = <0 0x06b10000 0 0x10000>; 2465 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2466 clocks = <&lpass_wsamacro>; 2467 clock-names = "iface"; 2468 label = "WSA"; 2469 2470 pinctrl-0 = <&wsa_swr_active>; 2471 pinctrl-names = "default"; 2472 2473 qcom,din-ports = <4>; 2474 qcom,dout-ports = <9>; 2475 2476 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2477 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2478 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2479 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2480 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2481 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2482 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2483 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2484 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2485 2486 #address-cells = <2>; 2487 #size-cells = <0>; 2488 #sound-dai-cells = <1>; 2489 status = "disabled"; 2490 }; 2491 2492 swr2: soundwire@6d30000 { 2493 compatible = "qcom,soundwire-v2.0.0"; 2494 reg = <0 0x06d30000 0 0x10000>; 2495 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2496 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2497 interrupt-names = "core", "wakeup"; 2498 clocks = <&lpass_txmacro>; 2499 clock-names = "iface"; 2500 label = "TX"; 2501 2502 pinctrl-0 = <&tx_swr_active>; 2503 pinctrl-names = "default"; 2504 2505 qcom,din-ports = <4>; 2506 qcom,dout-ports = <0>; 2507 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2508 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2509 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2510 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2511 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2512 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2513 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2514 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2515 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2516 2517 #address-cells = <2>; 2518 #size-cells = <0>; 2519 #sound-dai-cells = <1>; 2520 status = "disabled"; 2521 }; 2522 2523 lpass_vamacro: codec@6d44000 { 2524 compatible = "qcom,sm8550-lpass-va-macro"; 2525 reg = <0 0x06d44000 0 0x1000>; 2526 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2527 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2528 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2529 clock-names = "mclk", "macro", "dcodec"; 2530 2531 #clock-cells = <0>; 2532 clock-output-names = "fsgen"; 2533 #sound-dai-cells = <1>; 2534 }; 2535 2536 lpass_tlmm: pinctrl@6e80000 { 2537 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 2538 reg = <0 0x06e80000 0 0x20000>, 2539 <0 0x07250000 0 0x10000>; 2540 gpio-controller; 2541 #gpio-cells = <2>; 2542 gpio-ranges = <&lpass_tlmm 0 0 23>; 2543 2544 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2545 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2546 clock-names = "core", "audio"; 2547 2548 tx_swr_active: tx-swr-active-state { 2549 clk-pins { 2550 pins = "gpio0"; 2551 function = "swr_tx_clk"; 2552 drive-strength = <2>; 2553 slew-rate = <1>; 2554 bias-disable; 2555 }; 2556 2557 data-pins { 2558 pins = "gpio1", "gpio2", "gpio14"; 2559 function = "swr_tx_data"; 2560 drive-strength = <2>; 2561 slew-rate = <1>; 2562 bias-bus-hold; 2563 }; 2564 }; 2565 2566 rx_swr_active: rx-swr-active-state { 2567 clk-pins { 2568 pins = "gpio3"; 2569 function = "swr_rx_clk"; 2570 drive-strength = <2>; 2571 slew-rate = <1>; 2572 bias-disable; 2573 }; 2574 2575 data-pins { 2576 pins = "gpio4", "gpio5"; 2577 function = "swr_rx_data"; 2578 drive-strength = <2>; 2579 slew-rate = <1>; 2580 bias-bus-hold; 2581 }; 2582 }; 2583 2584 dmic01_default: dmic01-default-state { 2585 clk-pins { 2586 pins = "gpio6"; 2587 function = "dmic1_clk"; 2588 drive-strength = <8>; 2589 output-high; 2590 }; 2591 2592 data-pins { 2593 pins = "gpio7"; 2594 function = "dmic1_data"; 2595 drive-strength = <8>; 2596 input-enable; 2597 }; 2598 }; 2599 2600 dmic23_default: dmic23-default-state { 2601 clk-pins { 2602 pins = "gpio8"; 2603 function = "dmic2_clk"; 2604 drive-strength = <8>; 2605 output-high; 2606 }; 2607 2608 data-pins { 2609 pins = "gpio9"; 2610 function = "dmic2_data"; 2611 drive-strength = <8>; 2612 input-enable; 2613 }; 2614 }; 2615 2616 wsa_swr_active: wsa-swr-active-state { 2617 clk-pins { 2618 pins = "gpio10"; 2619 function = "wsa_swr_clk"; 2620 drive-strength = <2>; 2621 slew-rate = <1>; 2622 bias-disable; 2623 }; 2624 2625 data-pins { 2626 pins = "gpio11"; 2627 function = "wsa_swr_data"; 2628 drive-strength = <2>; 2629 slew-rate = <1>; 2630 bias-bus-hold; 2631 }; 2632 }; 2633 2634 wsa2_swr_active: wsa2-swr-active-state { 2635 clk-pins { 2636 pins = "gpio15"; 2637 function = "wsa2_swr_clk"; 2638 drive-strength = <2>; 2639 slew-rate = <1>; 2640 bias-disable; 2641 }; 2642 2643 data-pins { 2644 pins = "gpio16"; 2645 function = "wsa2_swr_data"; 2646 drive-strength = <2>; 2647 slew-rate = <1>; 2648 bias-bus-hold; 2649 }; 2650 }; 2651 }; 2652 2653 lpass_lpiaon_noc: interconnect@7400000 { 2654 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 2655 reg = <0 0x07400000 0 0x19080>; 2656 #interconnect-cells = <2>; 2657 qcom,bcm-voters = <&apps_bcm_voter>; 2658 }; 2659 2660 lpass_lpicx_noc: interconnect@7430000 { 2661 compatible = "qcom,sm8550-lpass-lpicx-noc"; 2662 reg = <0 0x07430000 0 0x3a200>; 2663 #interconnect-cells = <2>; 2664 qcom,bcm-voters = <&apps_bcm_voter>; 2665 }; 2666 2667 lpass_ag_noc: interconnect@7e40000 { 2668 compatible = "qcom,sm8550-lpass-ag-noc"; 2669 reg = <0 0x07e40000 0 0xe080>; 2670 #interconnect-cells = <2>; 2671 qcom,bcm-voters = <&apps_bcm_voter>; 2672 }; 2673 2674 sdhc_2: mmc@8804000 { 2675 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 2676 reg = <0 0x08804000 0 0x1000>; 2677 2678 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2679 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2680 interrupt-names = "hc_irq", "pwr_irq"; 2681 2682 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2683 <&gcc GCC_SDCC2_APPS_CLK>, 2684 <&rpmhcc RPMH_CXO_CLK>; 2685 clock-names = "iface", "core", "xo"; 2686 iommus = <&apps_smmu 0x540 0>; 2687 qcom,dll-config = <0x0007642c>; 2688 qcom,ddr-config = <0x80040868>; 2689 power-domains = <&rpmhpd RPMHPD_CX>; 2690 operating-points-v2 = <&sdhc2_opp_table>; 2691 2692 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2693 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2694 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 2695 bus-width = <4>; 2696 dma-coherent; 2697 2698 /* Forbid SDR104/SDR50 - broken hw! */ 2699 sdhci-caps-mask = <0x3 0>; 2700 2701 status = "disabled"; 2702 2703 sdhc2_opp_table: opp-table { 2704 compatible = "operating-points-v2"; 2705 2706 opp-19200000 { 2707 opp-hz = /bits/ 64 <19200000>; 2708 required-opps = <&rpmhpd_opp_min_svs>; 2709 }; 2710 2711 opp-50000000 { 2712 opp-hz = /bits/ 64 <50000000>; 2713 required-opps = <&rpmhpd_opp_low_svs>; 2714 }; 2715 2716 opp-100000000 { 2717 opp-hz = /bits/ 64 <100000000>; 2718 required-opps = <&rpmhpd_opp_svs>; 2719 }; 2720 2721 opp-202000000 { 2722 opp-hz = /bits/ 64 <202000000>; 2723 required-opps = <&rpmhpd_opp_svs_l1>; 2724 }; 2725 }; 2726 }; 2727 2728 videocc: clock-controller@aaf0000 { 2729 compatible = "qcom,sm8550-videocc"; 2730 reg = <0 0x0aaf0000 0 0x10000>; 2731 clocks = <&bi_tcxo_div2>, 2732 <&gcc GCC_VIDEO_AHB_CLK>; 2733 power-domains = <&rpmhpd RPMHPD_MMCX>; 2734 required-opps = <&rpmhpd_opp_low_svs>; 2735 #clock-cells = <1>; 2736 #reset-cells = <1>; 2737 #power-domain-cells = <1>; 2738 }; 2739 2740 camcc: clock-controller@ade0000 { 2741 compatible = "qcom,sm8550-camcc"; 2742 reg = <0 0x0ade0000 0 0x20000>; 2743 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2744 <&bi_tcxo_div2>, 2745 <&bi_tcxo_ao_div2>, 2746 <&sleep_clk>; 2747 power-domains = <&rpmhpd SM8550_MMCX>; 2748 required-opps = <&rpmhpd_opp_low_svs>; 2749 #clock-cells = <1>; 2750 #reset-cells = <1>; 2751 #power-domain-cells = <1>; 2752 }; 2753 2754 mdss: display-subsystem@ae00000 { 2755 compatible = "qcom,sm8550-mdss"; 2756 reg = <0 0x0ae00000 0 0x1000>; 2757 reg-names = "mdss"; 2758 2759 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2760 interrupt-controller; 2761 #interrupt-cells = <1>; 2762 2763 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2764 <&gcc GCC_DISP_AHB_CLK>, 2765 <&gcc GCC_DISP_HF_AXI_CLK>, 2766 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2767 2768 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2769 2770 power-domains = <&dispcc MDSS_GDSC>; 2771 2772 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, 2773 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2774 interconnect-names = "mdp0-mem", "mdp1-mem"; 2775 2776 iommus = <&apps_smmu 0x1c00 0x2>; 2777 2778 #address-cells = <2>; 2779 #size-cells = <2>; 2780 ranges; 2781 2782 status = "disabled"; 2783 2784 mdss_mdp: display-controller@ae01000 { 2785 compatible = "qcom,sm8550-dpu"; 2786 reg = <0 0x0ae01000 0 0x8f000>, 2787 <0 0x0aeb0000 0 0x2008>; 2788 reg-names = "mdp", "vbif"; 2789 2790 interrupt-parent = <&mdss>; 2791 interrupts = <0>; 2792 2793 clocks = <&gcc GCC_DISP_AHB_CLK>, 2794 <&gcc GCC_DISP_HF_AXI_CLK>, 2795 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2796 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2797 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2798 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2799 clock-names = "bus", 2800 "nrt_bus", 2801 "iface", 2802 "lut", 2803 "core", 2804 "vsync"; 2805 2806 power-domains = <&rpmhpd RPMHPD_MMCX>; 2807 2808 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2809 assigned-clock-rates = <19200000>; 2810 2811 operating-points-v2 = <&mdp_opp_table>; 2812 2813 ports { 2814 #address-cells = <1>; 2815 #size-cells = <0>; 2816 2817 port@0 { 2818 reg = <0>; 2819 dpu_intf1_out: endpoint { 2820 remote-endpoint = <&mdss_dsi0_in>; 2821 }; 2822 }; 2823 2824 port@1 { 2825 reg = <1>; 2826 dpu_intf2_out: endpoint { 2827 remote-endpoint = <&mdss_dsi1_in>; 2828 }; 2829 }; 2830 2831 port@2 { 2832 reg = <2>; 2833 dpu_intf0_out: endpoint { 2834 remote-endpoint = <&mdss_dp0_in>; 2835 }; 2836 }; 2837 }; 2838 2839 mdp_opp_table: opp-table { 2840 compatible = "operating-points-v2"; 2841 2842 opp-200000000 { 2843 opp-hz = /bits/ 64 <200000000>; 2844 required-opps = <&rpmhpd_opp_low_svs>; 2845 }; 2846 2847 opp-325000000 { 2848 opp-hz = /bits/ 64 <325000000>; 2849 required-opps = <&rpmhpd_opp_svs>; 2850 }; 2851 2852 opp-375000000 { 2853 opp-hz = /bits/ 64 <375000000>; 2854 required-opps = <&rpmhpd_opp_svs_l1>; 2855 }; 2856 2857 opp-514000000 { 2858 opp-hz = /bits/ 64 <514000000>; 2859 required-opps = <&rpmhpd_opp_nom>; 2860 }; 2861 }; 2862 }; 2863 2864 mdss_dp0: displayport-controller@ae90000 { 2865 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 2866 reg = <0 0xae90000 0 0x200>, 2867 <0 0xae90200 0 0x200>, 2868 <0 0xae90400 0 0xc00>, 2869 <0 0xae91000 0 0x400>, 2870 <0 0xae91400 0 0x400>; 2871 interrupt-parent = <&mdss>; 2872 interrupts = <12>; 2873 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2874 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2875 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2876 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2877 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2878 clock-names = "core_iface", 2879 "core_aux", 2880 "ctrl_link", 2881 "ctrl_link_iface", 2882 "stream_pixel"; 2883 2884 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2885 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2886 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2887 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2888 2889 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 2890 phy-names = "dp"; 2891 2892 #sound-dai-cells = <0>; 2893 2894 operating-points-v2 = <&dp_opp_table>; 2895 power-domains = <&rpmhpd RPMHPD_MMCX>; 2896 2897 status = "disabled"; 2898 2899 ports { 2900 #address-cells = <1>; 2901 #size-cells = <0>; 2902 2903 port@0 { 2904 reg = <0>; 2905 mdss_dp0_in: endpoint { 2906 remote-endpoint = <&dpu_intf0_out>; 2907 }; 2908 }; 2909 2910 port@1 { 2911 reg = <1>; 2912 mdss_dp0_out: endpoint { 2913 }; 2914 }; 2915 }; 2916 2917 dp_opp_table: opp-table { 2918 compatible = "operating-points-v2"; 2919 2920 opp-162000000 { 2921 opp-hz = /bits/ 64 <162000000>; 2922 required-opps = <&rpmhpd_opp_low_svs_d1>; 2923 }; 2924 2925 opp-270000000 { 2926 opp-hz = /bits/ 64 <270000000>; 2927 required-opps = <&rpmhpd_opp_low_svs>; 2928 }; 2929 2930 opp-540000000 { 2931 opp-hz = /bits/ 64 <540000000>; 2932 required-opps = <&rpmhpd_opp_svs_l1>; 2933 }; 2934 2935 opp-810000000 { 2936 opp-hz = /bits/ 64 <810000000>; 2937 required-opps = <&rpmhpd_opp_nom>; 2938 }; 2939 }; 2940 }; 2941 2942 mdss_dsi0: dsi@ae94000 { 2943 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2944 reg = <0 0x0ae94000 0 0x400>; 2945 reg-names = "dsi_ctrl"; 2946 2947 interrupt-parent = <&mdss>; 2948 interrupts = <4>; 2949 2950 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2951 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2952 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2953 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2954 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2955 <&gcc GCC_DISP_HF_AXI_CLK>; 2956 clock-names = "byte", 2957 "byte_intf", 2958 "pixel", 2959 "core", 2960 "iface", 2961 "bus"; 2962 2963 power-domains = <&rpmhpd RPMHPD_MMCX>; 2964 2965 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2966 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2967 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2968 <&mdss_dsi0_phy 1>; 2969 2970 operating-points-v2 = <&mdss_dsi_opp_table>; 2971 2972 phys = <&mdss_dsi0_phy>; 2973 phy-names = "dsi"; 2974 2975 #address-cells = <1>; 2976 #size-cells = <0>; 2977 2978 status = "disabled"; 2979 2980 ports { 2981 #address-cells = <1>; 2982 #size-cells = <0>; 2983 2984 port@0 { 2985 reg = <0>; 2986 mdss_dsi0_in: endpoint { 2987 remote-endpoint = <&dpu_intf1_out>; 2988 }; 2989 }; 2990 2991 port@1 { 2992 reg = <1>; 2993 mdss_dsi0_out: endpoint { 2994 }; 2995 }; 2996 }; 2997 2998 mdss_dsi_opp_table: opp-table { 2999 compatible = "operating-points-v2"; 3000 3001 opp-187500000 { 3002 opp-hz = /bits/ 64 <187500000>; 3003 required-opps = <&rpmhpd_opp_low_svs>; 3004 }; 3005 3006 opp-300000000 { 3007 opp-hz = /bits/ 64 <300000000>; 3008 required-opps = <&rpmhpd_opp_svs>; 3009 }; 3010 3011 opp-358000000 { 3012 opp-hz = /bits/ 64 <358000000>; 3013 required-opps = <&rpmhpd_opp_svs_l1>; 3014 }; 3015 }; 3016 }; 3017 3018 mdss_dsi0_phy: phy@ae95000 { 3019 compatible = "qcom,sm8550-dsi-phy-4nm"; 3020 reg = <0 0x0ae95000 0 0x200>, 3021 <0 0x0ae95200 0 0x280>, 3022 <0 0x0ae95500 0 0x400>; 3023 reg-names = "dsi_phy", 3024 "dsi_phy_lane", 3025 "dsi_pll"; 3026 3027 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3028 <&rpmhcc RPMH_CXO_CLK>; 3029 clock-names = "iface", "ref"; 3030 3031 #clock-cells = <1>; 3032 #phy-cells = <0>; 3033 3034 status = "disabled"; 3035 }; 3036 3037 mdss_dsi1: dsi@ae96000 { 3038 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3039 reg = <0 0x0ae96000 0 0x400>; 3040 reg-names = "dsi_ctrl"; 3041 3042 interrupt-parent = <&mdss>; 3043 interrupts = <5>; 3044 3045 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3046 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3047 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3048 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3049 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3050 <&gcc GCC_DISP_HF_AXI_CLK>; 3051 clock-names = "byte", 3052 "byte_intf", 3053 "pixel", 3054 "core", 3055 "iface", 3056 "bus"; 3057 3058 power-domains = <&rpmhpd RPMHPD_MMCX>; 3059 3060 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3061 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3062 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3063 <&mdss_dsi1_phy 1>; 3064 3065 operating-points-v2 = <&mdss_dsi_opp_table>; 3066 3067 phys = <&mdss_dsi1_phy>; 3068 phy-names = "dsi"; 3069 3070 #address-cells = <1>; 3071 #size-cells = <0>; 3072 3073 status = "disabled"; 3074 3075 ports { 3076 #address-cells = <1>; 3077 #size-cells = <0>; 3078 3079 port@0 { 3080 reg = <0>; 3081 mdss_dsi1_in: endpoint { 3082 remote-endpoint = <&dpu_intf2_out>; 3083 }; 3084 }; 3085 3086 port@1 { 3087 reg = <1>; 3088 mdss_dsi1_out: endpoint { 3089 }; 3090 }; 3091 }; 3092 }; 3093 3094 mdss_dsi1_phy: phy@ae97000 { 3095 compatible = "qcom,sm8550-dsi-phy-4nm"; 3096 reg = <0 0x0ae97000 0 0x200>, 3097 <0 0x0ae97200 0 0x280>, 3098 <0 0x0ae97500 0 0x400>; 3099 reg-names = "dsi_phy", 3100 "dsi_phy_lane", 3101 "dsi_pll"; 3102 3103 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3104 <&rpmhcc RPMH_CXO_CLK>; 3105 clock-names = "iface", "ref"; 3106 3107 #clock-cells = <1>; 3108 #phy-cells = <0>; 3109 3110 status = "disabled"; 3111 }; 3112 }; 3113 3114 dispcc: clock-controller@af00000 { 3115 compatible = "qcom,sm8550-dispcc"; 3116 reg = <0 0x0af00000 0 0x20000>; 3117 clocks = <&bi_tcxo_div2>, 3118 <&bi_tcxo_ao_div2>, 3119 <&gcc GCC_DISP_AHB_CLK>, 3120 <&sleep_clk>, 3121 <&mdss_dsi0_phy 0>, 3122 <&mdss_dsi0_phy 1>, 3123 <&mdss_dsi1_phy 0>, 3124 <&mdss_dsi1_phy 1>, 3125 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3126 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3127 <0>, /* dp1 */ 3128 <0>, 3129 <0>, /* dp2 */ 3130 <0>, 3131 <0>, /* dp3 */ 3132 <0>; 3133 power-domains = <&rpmhpd RPMHPD_MMCX>; 3134 required-opps = <&rpmhpd_opp_low_svs>; 3135 #clock-cells = <1>; 3136 #reset-cells = <1>; 3137 #power-domain-cells = <1>; 3138 }; 3139 3140 usb_1_hsphy: phy@88e3000 { 3141 compatible = "qcom,sm8550-snps-eusb2-phy"; 3142 reg = <0x0 0x088e3000 0x0 0x154>; 3143 #phy-cells = <0>; 3144 3145 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 3146 clock-names = "ref"; 3147 3148 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3149 3150 status = "disabled"; 3151 }; 3152 3153 usb_dp_qmpphy: phy@88e8000 { 3154 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 3155 reg = <0x0 0x088e8000 0x0 0x3000>; 3156 3157 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3158 <&rpmhcc RPMH_CXO_CLK>, 3159 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3160 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3161 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3162 3163 power-domains = <&gcc USB3_PHY_GDSC>; 3164 3165 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3166 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 3167 reset-names = "phy", "common"; 3168 3169 #clock-cells = <1>; 3170 #phy-cells = <1>; 3171 3172 status = "disabled"; 3173 3174 ports { 3175 #address-cells = <1>; 3176 #size-cells = <0>; 3177 3178 port@0 { 3179 reg = <0>; 3180 3181 usb_dp_qmpphy_out: endpoint { 3182 }; 3183 }; 3184 3185 port@1 { 3186 reg = <1>; 3187 3188 usb_dp_qmpphy_usb_ss_in: endpoint { 3189 }; 3190 }; 3191 3192 port@2 { 3193 reg = <2>; 3194 3195 usb_dp_qmpphy_dp_in: endpoint { 3196 }; 3197 }; 3198 }; 3199 }; 3200 3201 usb_1: usb@a6f8800 { 3202 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 3203 reg = <0x0 0x0a6f8800 0x0 0x400>; 3204 #address-cells = <2>; 3205 #size-cells = <2>; 3206 ranges; 3207 3208 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3209 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3210 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3211 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3212 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3213 <&tcsr TCSR_USB3_CLKREF_EN>; 3214 clock-names = "cfg_noc", 3215 "core", 3216 "iface", 3217 "sleep", 3218 "mock_utmi", 3219 "xo"; 3220 3221 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3222 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3223 assigned-clock-rates = <19200000>, <200000000>; 3224 3225 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3226 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3227 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3228 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3229 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3230 interrupt-names = "pwr_event", 3231 "hs_phy_irq", 3232 "dp_hs_phy_irq", 3233 "dm_hs_phy_irq", 3234 "ss_phy_irq"; 3235 3236 power-domains = <&gcc USB30_PRIM_GDSC>; 3237 required-opps = <&rpmhpd_opp_nom>; 3238 3239 resets = <&gcc GCC_USB30_PRIM_BCR>; 3240 3241 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3242 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3243 interconnect-names = "usb-ddr", "apps-usb"; 3244 3245 status = "disabled"; 3246 3247 usb_1_dwc3: usb@a600000 { 3248 compatible = "snps,dwc3"; 3249 reg = <0x0 0x0a600000 0x0 0xcd00>; 3250 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3251 iommus = <&apps_smmu 0x40 0x0>; 3252 phys = <&usb_1_hsphy>, 3253 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 3254 phy-names = "usb2-phy", "usb3-phy"; 3255 snps,hird-threshold = /bits/ 8 <0x0>; 3256 snps,usb2-gadget-lpm-disable; 3257 snps,dis_u2_susphy_quirk; 3258 snps,dis_enblslpm_quirk; 3259 snps,dis-u1-entry-quirk; 3260 snps,dis-u2-entry-quirk; 3261 snps,is-utmi-l1-suspend; 3262 snps,usb3_lpm_capable; 3263 snps,usb2-lpm-disable; 3264 snps,has-lpm-erratum; 3265 tx-fifo-resize; 3266 dma-coherent; 3267 3268 ports { 3269 #address-cells = <1>; 3270 #size-cells = <0>; 3271 3272 port@0 { 3273 reg = <0>; 3274 3275 usb_1_dwc3_hs: endpoint { 3276 }; 3277 }; 3278 3279 port@1 { 3280 reg = <1>; 3281 3282 usb_1_dwc3_ss: endpoint { 3283 }; 3284 }; 3285 }; 3286 }; 3287 }; 3288 3289 pdc: interrupt-controller@b220000 { 3290 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 3291 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3292 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3293 <125 63 1>, <126 716 12>, 3294 <138 251 5>; 3295 #interrupt-cells = <2>; 3296 interrupt-parent = <&intc>; 3297 interrupt-controller; 3298 }; 3299 3300 tsens0: thermal-sensor@c271000 { 3301 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3302 reg = <0 0x0c271000 0 0x1000>, /* TM */ 3303 <0 0x0c222000 0 0x1000>; /* SROT */ 3304 #qcom,sensors = <16>; 3305 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 3307 interrupt-names = "uplow", "critical"; 3308 #thermal-sensor-cells = <1>; 3309 }; 3310 3311 tsens1: thermal-sensor@c272000 { 3312 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3313 reg = <0 0x0c272000 0 0x1000>, /* TM */ 3314 <0 0x0c223000 0 0x1000>; /* SROT */ 3315 #qcom,sensors = <16>; 3316 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 3318 interrupt-names = "uplow", "critical"; 3319 #thermal-sensor-cells = <1>; 3320 }; 3321 3322 tsens2: thermal-sensor@c273000 { 3323 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3324 reg = <0 0x0c273000 0 0x1000>, /* TM */ 3325 <0 0x0c224000 0 0x1000>; /* SROT */ 3326 #qcom,sensors = <16>; 3327 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 3329 interrupt-names = "uplow", "critical"; 3330 #thermal-sensor-cells = <1>; 3331 }; 3332 3333 aoss_qmp: power-management@c300000 { 3334 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 3335 reg = <0 0x0c300000 0 0x400>; 3336 interrupt-parent = <&ipcc>; 3337 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3338 IRQ_TYPE_EDGE_RISING>; 3339 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3340 3341 #clock-cells = <0>; 3342 }; 3343 3344 sram@c3f0000 { 3345 compatible = "qcom,rpmh-stats"; 3346 reg = <0 0x0c3f0000 0 0x400>; 3347 }; 3348 3349 spmi_bus: spmi@c400000 { 3350 compatible = "qcom,spmi-pmic-arb"; 3351 reg = <0 0x0c400000 0 0x3000>, 3352 <0 0x0c500000 0 0x400000>, 3353 <0 0x0c440000 0 0x80000>, 3354 <0 0x0c4c0000 0 0x20000>, 3355 <0 0x0c42d000 0 0x4000>; 3356 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3357 interrupt-names = "periph_irq"; 3358 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3359 qcom,ee = <0>; 3360 qcom,channel = <0>; 3361 qcom,bus-id = <0>; 3362 #address-cells = <2>; 3363 #size-cells = <0>; 3364 interrupt-controller; 3365 #interrupt-cells = <4>; 3366 }; 3367 3368 tlmm: pinctrl@f100000 { 3369 compatible = "qcom,sm8550-tlmm"; 3370 reg = <0 0x0f100000 0 0x300000>; 3371 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3372 gpio-controller; 3373 #gpio-cells = <2>; 3374 interrupt-controller; 3375 #interrupt-cells = <2>; 3376 gpio-ranges = <&tlmm 0 0 211>; 3377 wakeup-parent = <&pdc>; 3378 3379 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3380 /* SDA, SCL */ 3381 pins = "gpio16", "gpio17"; 3382 function = "i2chub0_se0"; 3383 drive-strength = <2>; 3384 bias-pull-up; 3385 }; 3386 3387 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 3388 /* SDA, SCL */ 3389 pins = "gpio18", "gpio19"; 3390 function = "i2chub0_se1"; 3391 drive-strength = <2>; 3392 bias-pull-up; 3393 }; 3394 3395 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 3396 /* SDA, SCL */ 3397 pins = "gpio20", "gpio21"; 3398 function = "i2chub0_se2"; 3399 drive-strength = <2>; 3400 bias-pull-up; 3401 }; 3402 3403 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 3404 /* SDA, SCL */ 3405 pins = "gpio22", "gpio23"; 3406 function = "i2chub0_se3"; 3407 drive-strength = <2>; 3408 bias-pull-up; 3409 }; 3410 3411 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 3412 /* SDA, SCL */ 3413 pins = "gpio4", "gpio5"; 3414 function = "i2chub0_se4"; 3415 drive-strength = <2>; 3416 bias-pull-up; 3417 }; 3418 3419 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 3420 /* SDA, SCL */ 3421 pins = "gpio6", "gpio7"; 3422 function = "i2chub0_se5"; 3423 drive-strength = <2>; 3424 bias-pull-up; 3425 }; 3426 3427 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 3428 /* SDA, SCL */ 3429 pins = "gpio8", "gpio9"; 3430 function = "i2chub0_se6"; 3431 drive-strength = <2>; 3432 bias-pull-up; 3433 }; 3434 3435 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 3436 /* SDA, SCL */ 3437 pins = "gpio10", "gpio11"; 3438 function = "i2chub0_se7"; 3439 drive-strength = <2>; 3440 bias-pull-up; 3441 }; 3442 3443 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 3444 /* SDA, SCL */ 3445 pins = "gpio206", "gpio207"; 3446 function = "i2chub0_se8"; 3447 drive-strength = <2>; 3448 bias-pull-up; 3449 }; 3450 3451 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 3452 /* SDA, SCL */ 3453 pins = "gpio84", "gpio85"; 3454 function = "i2chub0_se9"; 3455 drive-strength = <2>; 3456 bias-pull-up; 3457 }; 3458 3459 pcie0_default_state: pcie0-default-state { 3460 perst-pins { 3461 pins = "gpio94"; 3462 function = "gpio"; 3463 drive-strength = <2>; 3464 bias-pull-down; 3465 }; 3466 3467 clkreq-pins { 3468 pins = "gpio95"; 3469 function = "pcie0_clk_req_n"; 3470 drive-strength = <2>; 3471 bias-pull-up; 3472 }; 3473 3474 wake-pins { 3475 pins = "gpio96"; 3476 function = "gpio"; 3477 drive-strength = <2>; 3478 bias-pull-up; 3479 }; 3480 }; 3481 3482 pcie1_default_state: pcie1-default-state { 3483 perst-pins { 3484 pins = "gpio97"; 3485 function = "gpio"; 3486 drive-strength = <2>; 3487 bias-pull-down; 3488 }; 3489 3490 clkreq-pins { 3491 pins = "gpio98"; 3492 function = "pcie1_clk_req_n"; 3493 drive-strength = <2>; 3494 bias-pull-up; 3495 }; 3496 3497 wake-pins { 3498 pins = "gpio99"; 3499 function = "gpio"; 3500 drive-strength = <2>; 3501 bias-pull-up; 3502 }; 3503 }; 3504 3505 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3506 /* SDA, SCL */ 3507 pins = "gpio28", "gpio29"; 3508 function = "qup1_se0"; 3509 drive-strength = <2>; 3510 bias-pull-up = <2200>; 3511 }; 3512 3513 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3514 /* SDA, SCL */ 3515 pins = "gpio32", "gpio33"; 3516 function = "qup1_se1"; 3517 drive-strength = <2>; 3518 bias-pull-up = <2200>; 3519 }; 3520 3521 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3522 /* SDA, SCL */ 3523 pins = "gpio36", "gpio37"; 3524 function = "qup1_se2"; 3525 drive-strength = <2>; 3526 bias-pull-up = <2200>; 3527 }; 3528 3529 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3530 /* SDA, SCL */ 3531 pins = "gpio40", "gpio41"; 3532 function = "qup1_se3"; 3533 drive-strength = <2>; 3534 bias-pull-up = <2200>; 3535 }; 3536 3537 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3538 /* SDA, SCL */ 3539 pins = "gpio44", "gpio45"; 3540 function = "qup1_se4"; 3541 drive-strength = <2>; 3542 bias-pull-up = <2200>; 3543 }; 3544 3545 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3546 /* SDA, SCL */ 3547 pins = "gpio52", "gpio53"; 3548 function = "qup1_se5"; 3549 drive-strength = <2>; 3550 bias-pull-up = <2200>; 3551 }; 3552 3553 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3554 /* SDA, SCL */ 3555 pins = "gpio48", "gpio49"; 3556 function = "qup1_se6"; 3557 drive-strength = <2>; 3558 bias-pull-up = <2200>; 3559 }; 3560 3561 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3562 scl-pins { 3563 pins = "gpio57"; 3564 function = "qup2_se0_l1_mira"; 3565 drive-strength = <2>; 3566 bias-pull-up = <2200>; 3567 }; 3568 3569 sda-pins { 3570 pins = "gpio56"; 3571 function = "qup2_se0_l0_mira"; 3572 drive-strength = <2>; 3573 bias-pull-up = <2200>; 3574 }; 3575 }; 3576 3577 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3578 /* SDA, SCL */ 3579 pins = "gpio60", "gpio61"; 3580 function = "qup2_se1"; 3581 drive-strength = <2>; 3582 bias-pull-up = <2200>; 3583 }; 3584 3585 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3586 /* SDA, SCL */ 3587 pins = "gpio64", "gpio65"; 3588 function = "qup2_se2"; 3589 drive-strength = <2>; 3590 bias-pull-up = <2200>; 3591 }; 3592 3593 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3594 /* SDA, SCL */ 3595 pins = "gpio68", "gpio69"; 3596 function = "qup2_se3"; 3597 drive-strength = <2>; 3598 bias-pull-up = <2200>; 3599 }; 3600 3601 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3602 /* SDA, SCL */ 3603 pins = "gpio2", "gpio3"; 3604 function = "qup2_se4"; 3605 drive-strength = <2>; 3606 bias-pull-up = <2200>; 3607 }; 3608 3609 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3610 /* SDA, SCL */ 3611 pins = "gpio80", "gpio81"; 3612 function = "qup2_se5"; 3613 drive-strength = <2>; 3614 bias-pull-up = <2200>; 3615 }; 3616 3617 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3618 /* SDA, SCL */ 3619 pins = "gpio72", "gpio106"; 3620 function = "qup2_se7"; 3621 drive-strength = <2>; 3622 bias-pull-up = <2200>; 3623 }; 3624 3625 qup_spi0_cs: qup-spi0-cs-state { 3626 pins = "gpio31"; 3627 function = "qup1_se0"; 3628 drive-strength = <6>; 3629 bias-disable; 3630 }; 3631 3632 qup_spi0_data_clk: qup-spi0-data-clk-state { 3633 /* MISO, MOSI, CLK */ 3634 pins = "gpio28", "gpio29", "gpio30"; 3635 function = "qup1_se0"; 3636 drive-strength = <6>; 3637 bias-disable; 3638 }; 3639 3640 qup_spi1_cs: qup-spi1-cs-state { 3641 pins = "gpio35"; 3642 function = "qup1_se1"; 3643 drive-strength = <6>; 3644 bias-disable; 3645 }; 3646 3647 qup_spi1_data_clk: qup-spi1-data-clk-state { 3648 /* MISO, MOSI, CLK */ 3649 pins = "gpio32", "gpio33", "gpio34"; 3650 function = "qup1_se1"; 3651 drive-strength = <6>; 3652 bias-disable; 3653 }; 3654 3655 qup_spi2_cs: qup-spi2-cs-state { 3656 pins = "gpio39"; 3657 function = "qup1_se2"; 3658 drive-strength = <6>; 3659 bias-disable; 3660 }; 3661 3662 qup_spi2_data_clk: qup-spi2-data-clk-state { 3663 /* MISO, MOSI, CLK */ 3664 pins = "gpio36", "gpio37", "gpio38"; 3665 function = "qup1_se2"; 3666 drive-strength = <6>; 3667 bias-disable; 3668 }; 3669 3670 qup_spi3_cs: qup-spi3-cs-state { 3671 pins = "gpio43"; 3672 function = "qup1_se3"; 3673 drive-strength = <6>; 3674 bias-disable; 3675 }; 3676 3677 qup_spi3_data_clk: qup-spi3-data-clk-state { 3678 /* MISO, MOSI, CLK */ 3679 pins = "gpio40", "gpio41", "gpio42"; 3680 function = "qup1_se3"; 3681 drive-strength = <6>; 3682 bias-disable; 3683 }; 3684 3685 qup_spi4_cs: qup-spi4-cs-state { 3686 pins = "gpio47"; 3687 function = "qup1_se4"; 3688 drive-strength = <6>; 3689 bias-disable; 3690 }; 3691 3692 qup_spi4_data_clk: qup-spi4-data-clk-state { 3693 /* MISO, MOSI, CLK */ 3694 pins = "gpio44", "gpio45", "gpio46"; 3695 function = "qup1_se4"; 3696 drive-strength = <6>; 3697 bias-disable; 3698 }; 3699 3700 qup_spi5_cs: qup-spi5-cs-state { 3701 pins = "gpio55"; 3702 function = "qup1_se5"; 3703 drive-strength = <6>; 3704 bias-disable; 3705 }; 3706 3707 qup_spi5_data_clk: qup-spi5-data-clk-state { 3708 /* MISO, MOSI, CLK */ 3709 pins = "gpio52", "gpio53", "gpio54"; 3710 function = "qup1_se5"; 3711 drive-strength = <6>; 3712 bias-disable; 3713 }; 3714 3715 qup_spi6_cs: qup-spi6-cs-state { 3716 pins = "gpio51"; 3717 function = "qup1_se6"; 3718 drive-strength = <6>; 3719 bias-disable; 3720 }; 3721 3722 qup_spi6_data_clk: qup-spi6-data-clk-state { 3723 /* MISO, MOSI, CLK */ 3724 pins = "gpio48", "gpio49", "gpio50"; 3725 function = "qup1_se6"; 3726 drive-strength = <6>; 3727 bias-disable; 3728 }; 3729 3730 qup_spi8_cs: qup-spi8-cs-state { 3731 pins = "gpio59"; 3732 function = "qup2_se0_l3_mira"; 3733 drive-strength = <6>; 3734 bias-disable; 3735 }; 3736 3737 qup_spi8_data_clk: qup-spi8-data-clk-state { 3738 /* MISO, MOSI, CLK */ 3739 pins = "gpio56", "gpio57", "gpio58"; 3740 function = "qup2_se0_l2_mira"; 3741 drive-strength = <6>; 3742 bias-disable; 3743 }; 3744 3745 qup_spi9_cs: qup-spi9-cs-state { 3746 pins = "gpio63"; 3747 function = "qup2_se1"; 3748 drive-strength = <6>; 3749 bias-disable; 3750 }; 3751 3752 qup_spi9_data_clk: qup-spi9-data-clk-state { 3753 /* MISO, MOSI, CLK */ 3754 pins = "gpio60", "gpio61", "gpio62"; 3755 function = "qup2_se1"; 3756 drive-strength = <6>; 3757 bias-disable; 3758 }; 3759 3760 qup_spi10_cs: qup-spi10-cs-state { 3761 pins = "gpio67"; 3762 function = "qup2_se2"; 3763 drive-strength = <6>; 3764 bias-disable; 3765 }; 3766 3767 qup_spi10_data_clk: qup-spi10-data-clk-state { 3768 /* MISO, MOSI, CLK */ 3769 pins = "gpio64", "gpio65", "gpio66"; 3770 function = "qup2_se2"; 3771 drive-strength = <6>; 3772 bias-disable; 3773 }; 3774 3775 qup_spi11_cs: qup-spi11-cs-state { 3776 pins = "gpio71"; 3777 function = "qup2_se3"; 3778 drive-strength = <6>; 3779 bias-disable; 3780 }; 3781 3782 qup_spi11_data_clk: qup-spi11-data-clk-state { 3783 /* MISO, MOSI, CLK */ 3784 pins = "gpio68", "gpio69", "gpio70"; 3785 function = "qup2_se3"; 3786 drive-strength = <6>; 3787 bias-disable; 3788 }; 3789 3790 qup_spi12_cs: qup-spi12-cs-state { 3791 pins = "gpio119"; 3792 function = "qup2_se4"; 3793 drive-strength = <6>; 3794 bias-disable; 3795 }; 3796 3797 qup_spi12_data_clk: qup-spi12-data-clk-state { 3798 /* MISO, MOSI, CLK */ 3799 pins = "gpio2", "gpio3", "gpio118"; 3800 function = "qup2_se4"; 3801 drive-strength = <6>; 3802 bias-disable; 3803 }; 3804 3805 qup_spi13_cs: qup-spi13-cs-state { 3806 pins = "gpio83"; 3807 function = "qup2_se5"; 3808 drive-strength = <6>; 3809 bias-disable; 3810 }; 3811 3812 qup_spi13_data_clk: qup-spi13-data-clk-state { 3813 /* MISO, MOSI, CLK */ 3814 pins = "gpio80", "gpio81", "gpio82"; 3815 function = "qup2_se5"; 3816 drive-strength = <6>; 3817 bias-disable; 3818 }; 3819 3820 qup_spi15_cs: qup-spi15-cs-state { 3821 pins = "gpio75"; 3822 function = "qup2_se7"; 3823 drive-strength = <6>; 3824 bias-disable; 3825 }; 3826 3827 qup_spi15_data_clk: qup-spi15-data-clk-state { 3828 /* MISO, MOSI, CLK */ 3829 pins = "gpio72", "gpio106", "gpio74"; 3830 function = "qup2_se7"; 3831 drive-strength = <6>; 3832 bias-disable; 3833 }; 3834 3835 qup_uart7_default: qup-uart7-default-state { 3836 /* TX, RX */ 3837 pins = "gpio26", "gpio27"; 3838 function = "qup1_se7"; 3839 drive-strength = <2>; 3840 bias-disable; 3841 }; 3842 3843 qup_uart14_default: qup-uart14-default-state { 3844 /* TX, RX */ 3845 pins = "gpio78", "gpio79"; 3846 function = "qup2_se6"; 3847 drive-strength = <2>; 3848 bias-pull-up; 3849 }; 3850 3851 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 3852 /* CTS, RTS */ 3853 pins = "gpio76", "gpio77"; 3854 function = "qup2_se6"; 3855 drive-strength = <2>; 3856 bias-pull-down; 3857 }; 3858 3859 sdc2_sleep: sdc2-sleep-state { 3860 clk-pins { 3861 pins = "sdc2_clk"; 3862 bias-disable; 3863 drive-strength = <2>; 3864 }; 3865 3866 cmd-pins { 3867 pins = "sdc2_cmd"; 3868 bias-pull-up; 3869 drive-strength = <2>; 3870 }; 3871 3872 data-pins { 3873 pins = "sdc2_data"; 3874 bias-pull-up; 3875 drive-strength = <2>; 3876 }; 3877 }; 3878 3879 sdc2_default: sdc2-default-state { 3880 clk-pins { 3881 pins = "sdc2_clk"; 3882 bias-disable; 3883 drive-strength = <16>; 3884 }; 3885 3886 cmd-pins { 3887 pins = "sdc2_cmd"; 3888 bias-pull-up; 3889 drive-strength = <10>; 3890 }; 3891 3892 data-pins { 3893 pins = "sdc2_data"; 3894 bias-pull-up; 3895 drive-strength = <10>; 3896 }; 3897 }; 3898 }; 3899 3900 apps_smmu: iommu@15000000 { 3901 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3902 reg = <0 0x15000000 0 0x100000>; 3903 #iommu-cells = <2>; 3904 #global-interrupts = <1>; 3905 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3906 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3907 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3908 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3909 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3910 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3911 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3912 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3913 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3914 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3915 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3916 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3917 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3918 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3919 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3920 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3921 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3922 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3923 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3924 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3925 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3926 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3927 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3928 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3929 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3930 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3931 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3932 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3933 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3934 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3935 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3936 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3937 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3938 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3939 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3940 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3941 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3942 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3943 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3944 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3945 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3946 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3947 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3948 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3949 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3950 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3951 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3952 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3953 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3954 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3955 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3956 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3957 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3958 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3959 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3960 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3961 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3962 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3963 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3964 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3965 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3966 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3967 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3968 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3969 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3970 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3971 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3972 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3973 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3974 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3975 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3976 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3977 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3978 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3979 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3980 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3981 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3982 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3983 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3984 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3985 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3986 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3987 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3988 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3989 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3990 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3991 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3992 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3993 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3994 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3995 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3996 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3997 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3998 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3999 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4000 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4001 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 4002 dma-coherent; 4003 }; 4004 4005 intc: interrupt-controller@17100000 { 4006 compatible = "arm,gic-v3"; 4007 reg = <0 0x17100000 0 0x10000>, /* GICD */ 4008 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 4009 ranges; 4010 #interrupt-cells = <3>; 4011 interrupt-controller; 4012 #redistributor-regions = <1>; 4013 redistributor-stride = <0 0x40000>; 4014 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 4015 #address-cells = <2>; 4016 #size-cells = <2>; 4017 4018 gic_its: msi-controller@17140000 { 4019 compatible = "arm,gic-v3-its"; 4020 reg = <0 0x17140000 0 0x20000>; 4021 msi-controller; 4022 #msi-cells = <1>; 4023 }; 4024 }; 4025 4026 timer@17420000 { 4027 compatible = "arm,armv7-timer-mem"; 4028 reg = <0 0x17420000 0 0x1000>; 4029 ranges = <0 0 0 0x20000000>; 4030 #address-cells = <1>; 4031 #size-cells = <1>; 4032 4033 frame@17421000 { 4034 reg = <0x17421000 0x1000>, 4035 <0x17422000 0x1000>; 4036 frame-number = <0>; 4037 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4038 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4039 }; 4040 4041 frame@17423000 { 4042 reg = <0x17423000 0x1000>; 4043 frame-number = <1>; 4044 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4045 status = "disabled"; 4046 }; 4047 4048 frame@17425000 { 4049 reg = <0x17425000 0x1000>; 4050 frame-number = <2>; 4051 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4052 status = "disabled"; 4053 }; 4054 4055 frame@17427000 { 4056 reg = <0x17427000 0x1000>; 4057 frame-number = <3>; 4058 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4059 status = "disabled"; 4060 }; 4061 4062 frame@17429000 { 4063 reg = <0x17429000 0x1000>; 4064 frame-number = <4>; 4065 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4066 status = "disabled"; 4067 }; 4068 4069 frame@1742b000 { 4070 reg = <0x1742b000 0x1000>; 4071 frame-number = <5>; 4072 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4073 status = "disabled"; 4074 }; 4075 4076 frame@1742d000 { 4077 reg = <0x1742d000 0x1000>; 4078 frame-number = <6>; 4079 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4080 status = "disabled"; 4081 }; 4082 }; 4083 4084 apps_rsc: rsc@17a00000 { 4085 label = "apps_rsc"; 4086 compatible = "qcom,rpmh-rsc"; 4087 reg = <0 0x17a00000 0 0x10000>, 4088 <0 0x17a10000 0 0x10000>, 4089 <0 0x17a20000 0 0x10000>, 4090 <0 0x17a30000 0 0x10000>; 4091 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 4092 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4095 qcom,tcs-offset = <0xd00>; 4096 qcom,drv-id = <2>; 4097 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4098 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4099 power-domains = <&CLUSTER_PD>; 4100 4101 apps_bcm_voter: bcm-voter { 4102 compatible = "qcom,bcm-voter"; 4103 }; 4104 4105 rpmhcc: clock-controller { 4106 compatible = "qcom,sm8550-rpmh-clk"; 4107 #clock-cells = <1>; 4108 clock-names = "xo"; 4109 clocks = <&xo_board>; 4110 }; 4111 4112 rpmhpd: power-controller { 4113 compatible = "qcom,sm8550-rpmhpd"; 4114 #power-domain-cells = <1>; 4115 operating-points-v2 = <&rpmhpd_opp_table>; 4116 4117 rpmhpd_opp_table: opp-table { 4118 compatible = "operating-points-v2"; 4119 4120 rpmhpd_opp_ret: opp-16 { 4121 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4122 }; 4123 4124 rpmhpd_opp_min_svs: opp-48 { 4125 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4126 }; 4127 4128 rpmhpd_opp_low_svs_d2: opp-52 { 4129 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 4130 }; 4131 4132 rpmhpd_opp_low_svs_d1: opp-56 { 4133 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4134 }; 4135 4136 rpmhpd_opp_low_svs_d0: opp-60 { 4137 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 4138 }; 4139 4140 rpmhpd_opp_low_svs: opp-64 { 4141 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4142 }; 4143 4144 rpmhpd_opp_low_svs_l1: opp-80 { 4145 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4146 }; 4147 4148 rpmhpd_opp_svs: opp-128 { 4149 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4150 }; 4151 4152 rpmhpd_opp_svs_l0: opp-144 { 4153 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4154 }; 4155 4156 rpmhpd_opp_svs_l1: opp-192 { 4157 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4158 }; 4159 4160 rpmhpd_opp_nom: opp-256 { 4161 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4162 }; 4163 4164 rpmhpd_opp_nom_l1: opp-320 { 4165 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4166 }; 4167 4168 rpmhpd_opp_nom_l2: opp-336 { 4169 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4170 }; 4171 4172 rpmhpd_opp_turbo: opp-384 { 4173 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4174 }; 4175 4176 rpmhpd_opp_turbo_l1: opp-416 { 4177 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4178 }; 4179 }; 4180 }; 4181 }; 4182 4183 cpufreq_hw: cpufreq@17d91000 { 4184 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 4185 reg = <0 0x17d91000 0 0x1000>, 4186 <0 0x17d92000 0 0x1000>, 4187 <0 0x17d93000 0 0x1000>; 4188 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4189 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 4190 clock-names = "xo", "alternate"; 4191 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4192 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4194 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4195 #freq-domain-cells = <1>; 4196 #clock-cells = <1>; 4197 }; 4198 4199 pmu@24091000 { 4200 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4201 reg = <0 0x24091000 0 0x1000>; 4202 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4203 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 4204 4205 operating-points-v2 = <&llcc_bwmon_opp_table>; 4206 4207 llcc_bwmon_opp_table: opp-table { 4208 compatible = "operating-points-v2"; 4209 4210 opp-0 { 4211 opp-peak-kBps = <2086000>; 4212 }; 4213 4214 opp-1 { 4215 opp-peak-kBps = <2929000>; 4216 }; 4217 4218 opp-2 { 4219 opp-peak-kBps = <5931000>; 4220 }; 4221 4222 opp-3 { 4223 opp-peak-kBps = <6515000>; 4224 }; 4225 4226 opp-4 { 4227 opp-peak-kBps = <7980000>; 4228 }; 4229 4230 opp-5 { 4231 opp-peak-kBps = <10437000>; 4232 }; 4233 4234 opp-6 { 4235 opp-peak-kBps = <12157000>; 4236 }; 4237 4238 opp-7 { 4239 opp-peak-kBps = <14060000>; 4240 }; 4241 4242 opp-8 { 4243 opp-peak-kBps = <16113000>; 4244 }; 4245 }; 4246 }; 4247 4248 pmu@240b6400 { 4249 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 4250 reg = <0 0x240b6400 0 0x600>; 4251 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4252 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 4253 4254 operating-points-v2 = <&cpu_bwmon_opp_table>; 4255 4256 cpu_bwmon_opp_table: opp-table { 4257 compatible = "operating-points-v2"; 4258 4259 opp-0 { 4260 opp-peak-kBps = <4577000>; 4261 }; 4262 4263 opp-1 { 4264 opp-peak-kBps = <7110000>; 4265 }; 4266 4267 opp-2 { 4268 opp-peak-kBps = <9155000>; 4269 }; 4270 4271 opp-3 { 4272 opp-peak-kBps = <12298000>; 4273 }; 4274 4275 opp-4 { 4276 opp-peak-kBps = <14236000>; 4277 }; 4278 4279 opp-5 { 4280 opp-peak-kBps = <16265000>; 4281 }; 4282 }; 4283 }; 4284 4285 gem_noc: interconnect@24100000 { 4286 compatible = "qcom,sm8550-gem-noc"; 4287 reg = <0 0x24100000 0 0xbb800>; 4288 #interconnect-cells = <2>; 4289 qcom,bcm-voters = <&apps_bcm_voter>; 4290 }; 4291 4292 system-cache-controller@25000000 { 4293 compatible = "qcom,sm8550-llcc"; 4294 reg = <0 0x25000000 0 0x200000>, 4295 <0 0x25200000 0 0x200000>, 4296 <0 0x25400000 0 0x200000>, 4297 <0 0x25600000 0 0x200000>, 4298 <0 0x25800000 0 0x200000>; 4299 reg-names = "llcc0_base", 4300 "llcc1_base", 4301 "llcc2_base", 4302 "llcc3_base", 4303 "llcc_broadcast_base"; 4304 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4305 }; 4306 4307 remoteproc_adsp: remoteproc@30000000 { 4308 compatible = "qcom,sm8550-adsp-pas"; 4309 reg = <0x0 0x30000000 0x0 0x100>; 4310 4311 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4312 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4313 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4314 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4315 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4316 interrupt-names = "wdog", "fatal", "ready", 4317 "handover", "stop-ack"; 4318 4319 clocks = <&rpmhcc RPMH_CXO_CLK>; 4320 clock-names = "xo"; 4321 4322 power-domains = <&rpmhpd RPMHPD_LCX>, 4323 <&rpmhpd RPMHPD_LMX>; 4324 power-domain-names = "lcx", "lmx"; 4325 4326 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 4327 4328 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 4329 4330 qcom,qmp = <&aoss_qmp>; 4331 4332 qcom,smem-states = <&smp2p_adsp_out 0>; 4333 qcom,smem-state-names = "stop"; 4334 4335 status = "disabled"; 4336 4337 remoteproc_adsp_glink: glink-edge { 4338 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4339 IPCC_MPROC_SIGNAL_GLINK_QMP 4340 IRQ_TYPE_EDGE_RISING>; 4341 mboxes = <&ipcc IPCC_CLIENT_LPASS 4342 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4343 4344 label = "lpass"; 4345 qcom,remote-pid = <2>; 4346 4347 fastrpc { 4348 compatible = "qcom,fastrpc"; 4349 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4350 label = "adsp"; 4351 qcom,non-secure-domain; 4352 #address-cells = <1>; 4353 #size-cells = <0>; 4354 4355 compute-cb@3 { 4356 compatible = "qcom,fastrpc-compute-cb"; 4357 reg = <3>; 4358 iommus = <&apps_smmu 0x1003 0x80>, 4359 <&apps_smmu 0x1063 0x0>; 4360 dma-coherent; 4361 }; 4362 4363 compute-cb@4 { 4364 compatible = "qcom,fastrpc-compute-cb"; 4365 reg = <4>; 4366 iommus = <&apps_smmu 0x1004 0x80>, 4367 <&apps_smmu 0x1064 0x0>; 4368 dma-coherent; 4369 }; 4370 4371 compute-cb@5 { 4372 compatible = "qcom,fastrpc-compute-cb"; 4373 reg = <5>; 4374 iommus = <&apps_smmu 0x1005 0x80>, 4375 <&apps_smmu 0x1065 0x0>; 4376 dma-coherent; 4377 }; 4378 4379 compute-cb@6 { 4380 compatible = "qcom,fastrpc-compute-cb"; 4381 reg = <6>; 4382 iommus = <&apps_smmu 0x1006 0x80>, 4383 <&apps_smmu 0x1066 0x0>; 4384 dma-coherent; 4385 }; 4386 4387 compute-cb@7 { 4388 compatible = "qcom,fastrpc-compute-cb"; 4389 reg = <7>; 4390 iommus = <&apps_smmu 0x1007 0x80>, 4391 <&apps_smmu 0x1067 0x0>; 4392 dma-coherent; 4393 }; 4394 }; 4395 4396 gpr { 4397 compatible = "qcom,gpr"; 4398 qcom,glink-channels = "adsp_apps"; 4399 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4400 qcom,intents = <512 20>; 4401 #address-cells = <1>; 4402 #size-cells = <0>; 4403 4404 q6apm: service@1 { 4405 compatible = "qcom,q6apm"; 4406 reg = <GPR_APM_MODULE_IID>; 4407 #sound-dai-cells = <0>; 4408 qcom,protection-domain = "avs/audio", 4409 "msm/adsp/audio_pd"; 4410 4411 q6apmdai: dais { 4412 compatible = "qcom,q6apm-dais"; 4413 iommus = <&apps_smmu 0x1001 0x80>, 4414 <&apps_smmu 0x1061 0x0>; 4415 }; 4416 4417 q6apmbedai: bedais { 4418 compatible = "qcom,q6apm-lpass-dais"; 4419 #sound-dai-cells = <1>; 4420 }; 4421 }; 4422 4423 q6prm: service@2 { 4424 compatible = "qcom,q6prm"; 4425 reg = <GPR_PRM_MODULE_IID>; 4426 qcom,protection-domain = "avs/audio", 4427 "msm/adsp/audio_pd"; 4428 4429 q6prmcc: clock-controller { 4430 compatible = "qcom,q6prm-lpass-clocks"; 4431 #clock-cells = <2>; 4432 }; 4433 }; 4434 }; 4435 }; 4436 }; 4437 4438 nsp_noc: interconnect@320c0000 { 4439 compatible = "qcom,sm8550-nsp-noc"; 4440 reg = <0 0x320c0000 0 0xe080>; 4441 #interconnect-cells = <2>; 4442 qcom,bcm-voters = <&apps_bcm_voter>; 4443 }; 4444 4445 remoteproc_cdsp: remoteproc@32300000 { 4446 compatible = "qcom,sm8550-cdsp-pas"; 4447 reg = <0x0 0x32300000 0x0 0x1400000>; 4448 4449 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4450 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 4451 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 4452 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 4453 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 4454 interrupt-names = "wdog", "fatal", "ready", 4455 "handover", "stop-ack"; 4456 4457 clocks = <&rpmhcc RPMH_CXO_CLK>; 4458 clock-names = "xo"; 4459 4460 power-domains = <&rpmhpd RPMHPD_CX>, 4461 <&rpmhpd RPMHPD_MXC>, 4462 <&rpmhpd RPMHPD_NSP>; 4463 power-domain-names = "cx", "mxc", "nsp"; 4464 4465 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4466 4467 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 4468 4469 qcom,qmp = <&aoss_qmp>; 4470 4471 qcom,smem-states = <&smp2p_cdsp_out 0>; 4472 qcom,smem-state-names = "stop"; 4473 4474 status = "disabled"; 4475 4476 glink-edge { 4477 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4478 IPCC_MPROC_SIGNAL_GLINK_QMP 4479 IRQ_TYPE_EDGE_RISING>; 4480 mboxes = <&ipcc IPCC_CLIENT_CDSP 4481 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4482 4483 label = "cdsp"; 4484 qcom,remote-pid = <5>; 4485 4486 fastrpc { 4487 compatible = "qcom,fastrpc"; 4488 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4489 label = "cdsp"; 4490 qcom,non-secure-domain; 4491 #address-cells = <1>; 4492 #size-cells = <0>; 4493 4494 compute-cb@1 { 4495 compatible = "qcom,fastrpc-compute-cb"; 4496 reg = <1>; 4497 iommus = <&apps_smmu 0x1961 0x0>, 4498 <&apps_smmu 0x0c01 0x20>, 4499 <&apps_smmu 0x19c1 0x10>; 4500 dma-coherent; 4501 }; 4502 4503 compute-cb@2 { 4504 compatible = "qcom,fastrpc-compute-cb"; 4505 reg = <2>; 4506 iommus = <&apps_smmu 0x1962 0x0>, 4507 <&apps_smmu 0x0c02 0x20>, 4508 <&apps_smmu 0x19c2 0x10>; 4509 dma-coherent; 4510 }; 4511 4512 compute-cb@3 { 4513 compatible = "qcom,fastrpc-compute-cb"; 4514 reg = <3>; 4515 iommus = <&apps_smmu 0x1963 0x0>, 4516 <&apps_smmu 0x0c03 0x20>, 4517 <&apps_smmu 0x19c3 0x10>; 4518 dma-coherent; 4519 }; 4520 4521 compute-cb@4 { 4522 compatible = "qcom,fastrpc-compute-cb"; 4523 reg = <4>; 4524 iommus = <&apps_smmu 0x1964 0x0>, 4525 <&apps_smmu 0x0c04 0x20>, 4526 <&apps_smmu 0x19c4 0x10>; 4527 dma-coherent; 4528 }; 4529 4530 compute-cb@5 { 4531 compatible = "qcom,fastrpc-compute-cb"; 4532 reg = <5>; 4533 iommus = <&apps_smmu 0x1965 0x0>, 4534 <&apps_smmu 0x0c05 0x20>, 4535 <&apps_smmu 0x19c5 0x10>; 4536 dma-coherent; 4537 }; 4538 4539 compute-cb@6 { 4540 compatible = "qcom,fastrpc-compute-cb"; 4541 reg = <6>; 4542 iommus = <&apps_smmu 0x1966 0x0>, 4543 <&apps_smmu 0x0c06 0x20>, 4544 <&apps_smmu 0x19c6 0x10>; 4545 dma-coherent; 4546 }; 4547 4548 compute-cb@7 { 4549 compatible = "qcom,fastrpc-compute-cb"; 4550 reg = <7>; 4551 iommus = <&apps_smmu 0x1967 0x0>, 4552 <&apps_smmu 0x0c07 0x20>, 4553 <&apps_smmu 0x19c7 0x10>; 4554 dma-coherent; 4555 }; 4556 4557 compute-cb@8 { 4558 compatible = "qcom,fastrpc-compute-cb"; 4559 reg = <8>; 4560 iommus = <&apps_smmu 0x1968 0x0>, 4561 <&apps_smmu 0x0c08 0x20>, 4562 <&apps_smmu 0x19c8 0x10>; 4563 dma-coherent; 4564 }; 4565 4566 /* note: secure cb9 in downstream */ 4567 }; 4568 }; 4569 }; 4570 }; 4571 4572 thermal-zones { 4573 aoss0-thermal { 4574 polling-delay-passive = <0>; 4575 polling-delay = <0>; 4576 thermal-sensors = <&tsens0 0>; 4577 4578 trips { 4579 thermal-engine-config { 4580 temperature = <125000>; 4581 hysteresis = <1000>; 4582 type = "passive"; 4583 }; 4584 4585 reset-mon-config { 4586 temperature = <115000>; 4587 hysteresis = <5000>; 4588 type = "passive"; 4589 }; 4590 }; 4591 }; 4592 4593 cpuss0-thermal { 4594 polling-delay-passive = <0>; 4595 polling-delay = <0>; 4596 thermal-sensors = <&tsens0 1>; 4597 4598 trips { 4599 thermal-engine-config { 4600 temperature = <125000>; 4601 hysteresis = <1000>; 4602 type = "passive"; 4603 }; 4604 4605 reset-mon-config { 4606 temperature = <115000>; 4607 hysteresis = <5000>; 4608 type = "passive"; 4609 }; 4610 }; 4611 }; 4612 4613 cpuss1-thermal { 4614 polling-delay-passive = <0>; 4615 polling-delay = <0>; 4616 thermal-sensors = <&tsens0 2>; 4617 4618 trips { 4619 thermal-engine-config { 4620 temperature = <125000>; 4621 hysteresis = <1000>; 4622 type = "passive"; 4623 }; 4624 4625 reset-mon-config { 4626 temperature = <115000>; 4627 hysteresis = <5000>; 4628 type = "passive"; 4629 }; 4630 }; 4631 }; 4632 4633 cpuss2-thermal { 4634 polling-delay-passive = <0>; 4635 polling-delay = <0>; 4636 thermal-sensors = <&tsens0 3>; 4637 4638 trips { 4639 thermal-engine-config { 4640 temperature = <125000>; 4641 hysteresis = <1000>; 4642 type = "passive"; 4643 }; 4644 4645 reset-mon-config { 4646 temperature = <115000>; 4647 hysteresis = <5000>; 4648 type = "passive"; 4649 }; 4650 }; 4651 }; 4652 4653 cpuss3-thermal { 4654 polling-delay-passive = <0>; 4655 polling-delay = <0>; 4656 thermal-sensors = <&tsens0 4>; 4657 4658 trips { 4659 thermal-engine-config { 4660 temperature = <125000>; 4661 hysteresis = <1000>; 4662 type = "passive"; 4663 }; 4664 4665 reset-mon-config { 4666 temperature = <115000>; 4667 hysteresis = <5000>; 4668 type = "passive"; 4669 }; 4670 }; 4671 }; 4672 4673 cpu3-top-thermal { 4674 polling-delay-passive = <0>; 4675 polling-delay = <0>; 4676 thermal-sensors = <&tsens0 5>; 4677 4678 trips { 4679 cpu3_top_alert0: trip-point0 { 4680 temperature = <90000>; 4681 hysteresis = <2000>; 4682 type = "passive"; 4683 }; 4684 4685 cpu3_top_alert1: trip-point1 { 4686 temperature = <95000>; 4687 hysteresis = <2000>; 4688 type = "passive"; 4689 }; 4690 4691 cpu3_top_crit: cpu-critical { 4692 temperature = <110000>; 4693 hysteresis = <1000>; 4694 type = "critical"; 4695 }; 4696 }; 4697 }; 4698 4699 cpu3-bottom-thermal { 4700 polling-delay-passive = <0>; 4701 polling-delay = <0>; 4702 thermal-sensors = <&tsens0 6>; 4703 4704 trips { 4705 cpu3_bottom_alert0: trip-point0 { 4706 temperature = <90000>; 4707 hysteresis = <2000>; 4708 type = "passive"; 4709 }; 4710 4711 cpu3_bottom_alert1: trip-point1 { 4712 temperature = <95000>; 4713 hysteresis = <2000>; 4714 type = "passive"; 4715 }; 4716 4717 cpu3_bottom_crit: cpu-critical { 4718 temperature = <110000>; 4719 hysteresis = <1000>; 4720 type = "critical"; 4721 }; 4722 }; 4723 }; 4724 4725 cpu4-top-thermal { 4726 polling-delay-passive = <0>; 4727 polling-delay = <0>; 4728 thermal-sensors = <&tsens0 7>; 4729 4730 trips { 4731 cpu4_top_alert0: trip-point0 { 4732 temperature = <90000>; 4733 hysteresis = <2000>; 4734 type = "passive"; 4735 }; 4736 4737 cpu4_top_alert1: trip-point1 { 4738 temperature = <95000>; 4739 hysteresis = <2000>; 4740 type = "passive"; 4741 }; 4742 4743 cpu4_top_crit: cpu-critical { 4744 temperature = <110000>; 4745 hysteresis = <1000>; 4746 type = "critical"; 4747 }; 4748 }; 4749 }; 4750 4751 cpu4-bottom-thermal { 4752 polling-delay-passive = <0>; 4753 polling-delay = <0>; 4754 thermal-sensors = <&tsens0 8>; 4755 4756 trips { 4757 cpu4_bottom_alert0: trip-point0 { 4758 temperature = <90000>; 4759 hysteresis = <2000>; 4760 type = "passive"; 4761 }; 4762 4763 cpu4_bottom_alert1: trip-point1 { 4764 temperature = <95000>; 4765 hysteresis = <2000>; 4766 type = "passive"; 4767 }; 4768 4769 cpu4_bottom_crit: cpu-critical { 4770 temperature = <110000>; 4771 hysteresis = <1000>; 4772 type = "critical"; 4773 }; 4774 }; 4775 }; 4776 4777 cpu5-top-thermal { 4778 polling-delay-passive = <0>; 4779 polling-delay = <0>; 4780 thermal-sensors = <&tsens0 9>; 4781 4782 trips { 4783 cpu5_top_alert0: trip-point0 { 4784 temperature = <90000>; 4785 hysteresis = <2000>; 4786 type = "passive"; 4787 }; 4788 4789 cpu5_top_alert1: trip-point1 { 4790 temperature = <95000>; 4791 hysteresis = <2000>; 4792 type = "passive"; 4793 }; 4794 4795 cpu5_top_crit: cpu-critical { 4796 temperature = <110000>; 4797 hysteresis = <1000>; 4798 type = "critical"; 4799 }; 4800 }; 4801 }; 4802 4803 cpu5-bottom-thermal { 4804 polling-delay-passive = <0>; 4805 polling-delay = <0>; 4806 thermal-sensors = <&tsens0 10>; 4807 4808 trips { 4809 cpu5_bottom_alert0: trip-point0 { 4810 temperature = <90000>; 4811 hysteresis = <2000>; 4812 type = "passive"; 4813 }; 4814 4815 cpu5_bottom_alert1: trip-point1 { 4816 temperature = <95000>; 4817 hysteresis = <2000>; 4818 type = "passive"; 4819 }; 4820 4821 cpu5_bottom_crit: cpu-critical { 4822 temperature = <110000>; 4823 hysteresis = <1000>; 4824 type = "critical"; 4825 }; 4826 }; 4827 }; 4828 4829 cpu6-top-thermal { 4830 polling-delay-passive = <0>; 4831 polling-delay = <0>; 4832 thermal-sensors = <&tsens0 11>; 4833 4834 trips { 4835 cpu6_top_alert0: trip-point0 { 4836 temperature = <90000>; 4837 hysteresis = <2000>; 4838 type = "passive"; 4839 }; 4840 4841 cpu6_top_alert1: trip-point1 { 4842 temperature = <95000>; 4843 hysteresis = <2000>; 4844 type = "passive"; 4845 }; 4846 4847 cpu6_top_crit: cpu-critical { 4848 temperature = <110000>; 4849 hysteresis = <1000>; 4850 type = "critical"; 4851 }; 4852 }; 4853 }; 4854 4855 cpu6-bottom-thermal { 4856 polling-delay-passive = <0>; 4857 polling-delay = <0>; 4858 thermal-sensors = <&tsens0 12>; 4859 4860 trips { 4861 cpu6_bottom_alert0: trip-point0 { 4862 temperature = <90000>; 4863 hysteresis = <2000>; 4864 type = "passive"; 4865 }; 4866 4867 cpu6_bottom_alert1: trip-point1 { 4868 temperature = <95000>; 4869 hysteresis = <2000>; 4870 type = "passive"; 4871 }; 4872 4873 cpu6_bottom_crit: cpu-critical { 4874 temperature = <110000>; 4875 hysteresis = <1000>; 4876 type = "critical"; 4877 }; 4878 }; 4879 }; 4880 4881 cpu7-top-thermal { 4882 polling-delay-passive = <0>; 4883 polling-delay = <0>; 4884 thermal-sensors = <&tsens0 13>; 4885 4886 trips { 4887 cpu7_top_alert0: trip-point0 { 4888 temperature = <90000>; 4889 hysteresis = <2000>; 4890 type = "passive"; 4891 }; 4892 4893 cpu7_top_alert1: trip-point1 { 4894 temperature = <95000>; 4895 hysteresis = <2000>; 4896 type = "passive"; 4897 }; 4898 4899 cpu7_top_crit: cpu-critical { 4900 temperature = <110000>; 4901 hysteresis = <1000>; 4902 type = "critical"; 4903 }; 4904 }; 4905 }; 4906 4907 cpu7-middle-thermal { 4908 polling-delay-passive = <0>; 4909 polling-delay = <0>; 4910 thermal-sensors = <&tsens0 14>; 4911 4912 trips { 4913 cpu7_middle_alert0: trip-point0 { 4914 temperature = <90000>; 4915 hysteresis = <2000>; 4916 type = "passive"; 4917 }; 4918 4919 cpu7_middle_alert1: trip-point1 { 4920 temperature = <95000>; 4921 hysteresis = <2000>; 4922 type = "passive"; 4923 }; 4924 4925 cpu7_middle_crit: cpu-critical { 4926 temperature = <110000>; 4927 hysteresis = <1000>; 4928 type = "critical"; 4929 }; 4930 }; 4931 }; 4932 4933 cpu7-bottom-thermal { 4934 polling-delay-passive = <0>; 4935 polling-delay = <0>; 4936 thermal-sensors = <&tsens0 15>; 4937 4938 trips { 4939 cpu7_bottom_alert0: trip-point0 { 4940 temperature = <90000>; 4941 hysteresis = <2000>; 4942 type = "passive"; 4943 }; 4944 4945 cpu7_bottom_alert1: trip-point1 { 4946 temperature = <95000>; 4947 hysteresis = <2000>; 4948 type = "passive"; 4949 }; 4950 4951 cpu7_bottom_crit: cpu-critical { 4952 temperature = <110000>; 4953 hysteresis = <1000>; 4954 type = "critical"; 4955 }; 4956 }; 4957 }; 4958 4959 aoss1-thermal { 4960 polling-delay-passive = <0>; 4961 polling-delay = <0>; 4962 thermal-sensors = <&tsens1 0>; 4963 4964 trips { 4965 thermal-engine-config { 4966 temperature = <125000>; 4967 hysteresis = <1000>; 4968 type = "passive"; 4969 }; 4970 4971 reset-mon-config { 4972 temperature = <115000>; 4973 hysteresis = <5000>; 4974 type = "passive"; 4975 }; 4976 }; 4977 }; 4978 4979 cpu0-thermal { 4980 polling-delay-passive = <0>; 4981 polling-delay = <0>; 4982 thermal-sensors = <&tsens1 1>; 4983 4984 trips { 4985 cpu0_alert0: trip-point0 { 4986 temperature = <90000>; 4987 hysteresis = <2000>; 4988 type = "passive"; 4989 }; 4990 4991 cpu0_alert1: trip-point1 { 4992 temperature = <95000>; 4993 hysteresis = <2000>; 4994 type = "passive"; 4995 }; 4996 4997 cpu0_crit: cpu-critical { 4998 temperature = <110000>; 4999 hysteresis = <1000>; 5000 type = "critical"; 5001 }; 5002 }; 5003 }; 5004 5005 cpu1-thermal { 5006 polling-delay-passive = <0>; 5007 polling-delay = <0>; 5008 thermal-sensors = <&tsens1 2>; 5009 5010 trips { 5011 cpu1_alert0: trip-point0 { 5012 temperature = <90000>; 5013 hysteresis = <2000>; 5014 type = "passive"; 5015 }; 5016 5017 cpu1_alert1: trip-point1 { 5018 temperature = <95000>; 5019 hysteresis = <2000>; 5020 type = "passive"; 5021 }; 5022 5023 cpu1_crit: cpu-critical { 5024 temperature = <110000>; 5025 hysteresis = <1000>; 5026 type = "critical"; 5027 }; 5028 }; 5029 }; 5030 5031 cpu2-thermal { 5032 polling-delay-passive = <0>; 5033 polling-delay = <0>; 5034 thermal-sensors = <&tsens1 3>; 5035 5036 trips { 5037 cpu2_alert0: trip-point0 { 5038 temperature = <90000>; 5039 hysteresis = <2000>; 5040 type = "passive"; 5041 }; 5042 5043 cpu2_alert1: trip-point1 { 5044 temperature = <95000>; 5045 hysteresis = <2000>; 5046 type = "passive"; 5047 }; 5048 5049 cpu2_crit: cpu-critical { 5050 temperature = <110000>; 5051 hysteresis = <1000>; 5052 type = "critical"; 5053 }; 5054 }; 5055 }; 5056 5057 cdsp0-thermal { 5058 polling-delay-passive = <10>; 5059 polling-delay = <0>; 5060 thermal-sensors = <&tsens2 4>; 5061 5062 trips { 5063 thermal-engine-config { 5064 temperature = <125000>; 5065 hysteresis = <1000>; 5066 type = "passive"; 5067 }; 5068 5069 thermal-hal-config { 5070 temperature = <125000>; 5071 hysteresis = <1000>; 5072 type = "passive"; 5073 }; 5074 5075 reset-mon-config { 5076 temperature = <115000>; 5077 hysteresis = <5000>; 5078 type = "passive"; 5079 }; 5080 5081 cdsp0_junction_config: junction-config { 5082 temperature = <95000>; 5083 hysteresis = <5000>; 5084 type = "passive"; 5085 }; 5086 }; 5087 }; 5088 5089 cdsp1-thermal { 5090 polling-delay-passive = <10>; 5091 polling-delay = <0>; 5092 thermal-sensors = <&tsens2 5>; 5093 5094 trips { 5095 thermal-engine-config { 5096 temperature = <125000>; 5097 hysteresis = <1000>; 5098 type = "passive"; 5099 }; 5100 5101 thermal-hal-config { 5102 temperature = <125000>; 5103 hysteresis = <1000>; 5104 type = "passive"; 5105 }; 5106 5107 reset-mon-config { 5108 temperature = <115000>; 5109 hysteresis = <5000>; 5110 type = "passive"; 5111 }; 5112 5113 cdsp1_junction_config: junction-config { 5114 temperature = <95000>; 5115 hysteresis = <5000>; 5116 type = "passive"; 5117 }; 5118 }; 5119 }; 5120 5121 cdsp2-thermal { 5122 polling-delay-passive = <10>; 5123 polling-delay = <0>; 5124 thermal-sensors = <&tsens2 6>; 5125 5126 trips { 5127 thermal-engine-config { 5128 temperature = <125000>; 5129 hysteresis = <1000>; 5130 type = "passive"; 5131 }; 5132 5133 thermal-hal-config { 5134 temperature = <125000>; 5135 hysteresis = <1000>; 5136 type = "passive"; 5137 }; 5138 5139 reset-mon-config { 5140 temperature = <115000>; 5141 hysteresis = <5000>; 5142 type = "passive"; 5143 }; 5144 5145 cdsp2_junction_config: junction-config { 5146 temperature = <95000>; 5147 hysteresis = <5000>; 5148 type = "passive"; 5149 }; 5150 }; 5151 }; 5152 5153 cdsp3-thermal { 5154 polling-delay-passive = <10>; 5155 polling-delay = <0>; 5156 thermal-sensors = <&tsens2 7>; 5157 5158 trips { 5159 thermal-engine-config { 5160 temperature = <125000>; 5161 hysteresis = <1000>; 5162 type = "passive"; 5163 }; 5164 5165 thermal-hal-config { 5166 temperature = <125000>; 5167 hysteresis = <1000>; 5168 type = "passive"; 5169 }; 5170 5171 reset-mon-config { 5172 temperature = <115000>; 5173 hysteresis = <5000>; 5174 type = "passive"; 5175 }; 5176 5177 cdsp3_junction_config: junction-config { 5178 temperature = <95000>; 5179 hysteresis = <5000>; 5180 type = "passive"; 5181 }; 5182 }; 5183 }; 5184 5185 video-thermal { 5186 polling-delay-passive = <0>; 5187 polling-delay = <0>; 5188 thermal-sensors = <&tsens1 8>; 5189 5190 trips { 5191 thermal-engine-config { 5192 temperature = <125000>; 5193 hysteresis = <1000>; 5194 type = "passive"; 5195 }; 5196 5197 reset-mon-config { 5198 temperature = <115000>; 5199 hysteresis = <5000>; 5200 type = "passive"; 5201 }; 5202 }; 5203 }; 5204 5205 mem-thermal { 5206 polling-delay-passive = <10>; 5207 polling-delay = <0>; 5208 thermal-sensors = <&tsens1 9>; 5209 5210 trips { 5211 thermal-engine-config { 5212 temperature = <125000>; 5213 hysteresis = <1000>; 5214 type = "passive"; 5215 }; 5216 5217 ddr_config0: ddr0-config { 5218 temperature = <90000>; 5219 hysteresis = <5000>; 5220 type = "passive"; 5221 }; 5222 5223 reset-mon-config { 5224 temperature = <115000>; 5225 hysteresis = <5000>; 5226 type = "passive"; 5227 }; 5228 }; 5229 }; 5230 5231 modem0-thermal { 5232 polling-delay-passive = <0>; 5233 polling-delay = <0>; 5234 thermal-sensors = <&tsens1 10>; 5235 5236 trips { 5237 thermal-engine-config { 5238 temperature = <125000>; 5239 hysteresis = <1000>; 5240 type = "passive"; 5241 }; 5242 5243 mdmss0_config0: mdmss0-config0 { 5244 temperature = <102000>; 5245 hysteresis = <3000>; 5246 type = "passive"; 5247 }; 5248 5249 mdmss0_config1: mdmss0-config1 { 5250 temperature = <105000>; 5251 hysteresis = <3000>; 5252 type = "passive"; 5253 }; 5254 5255 reset-mon-config { 5256 temperature = <115000>; 5257 hysteresis = <5000>; 5258 type = "passive"; 5259 }; 5260 }; 5261 }; 5262 5263 modem1-thermal { 5264 polling-delay-passive = <0>; 5265 polling-delay = <0>; 5266 thermal-sensors = <&tsens1 11>; 5267 5268 trips { 5269 thermal-engine-config { 5270 temperature = <125000>; 5271 hysteresis = <1000>; 5272 type = "passive"; 5273 }; 5274 5275 mdmss1_config0: mdmss1-config0 { 5276 temperature = <102000>; 5277 hysteresis = <3000>; 5278 type = "passive"; 5279 }; 5280 5281 mdmss1_config1: mdmss1-config1 { 5282 temperature = <105000>; 5283 hysteresis = <3000>; 5284 type = "passive"; 5285 }; 5286 5287 reset-mon-config { 5288 temperature = <115000>; 5289 hysteresis = <5000>; 5290 type = "passive"; 5291 }; 5292 }; 5293 }; 5294 5295 modem2-thermal { 5296 polling-delay-passive = <0>; 5297 polling-delay = <0>; 5298 thermal-sensors = <&tsens1 12>; 5299 5300 trips { 5301 thermal-engine-config { 5302 temperature = <125000>; 5303 hysteresis = <1000>; 5304 type = "passive"; 5305 }; 5306 5307 mdmss2_config0: mdmss2-config0 { 5308 temperature = <102000>; 5309 hysteresis = <3000>; 5310 type = "passive"; 5311 }; 5312 5313 mdmss2_config1: mdmss2-config1 { 5314 temperature = <105000>; 5315 hysteresis = <3000>; 5316 type = "passive"; 5317 }; 5318 5319 reset-mon-config { 5320 temperature = <115000>; 5321 hysteresis = <5000>; 5322 type = "passive"; 5323 }; 5324 }; 5325 }; 5326 5327 modem3-thermal { 5328 polling-delay-passive = <0>; 5329 polling-delay = <0>; 5330 thermal-sensors = <&tsens1 13>; 5331 5332 trips { 5333 thermal-engine-config { 5334 temperature = <125000>; 5335 hysteresis = <1000>; 5336 type = "passive"; 5337 }; 5338 5339 mdmss3_config0: mdmss3-config0 { 5340 temperature = <102000>; 5341 hysteresis = <3000>; 5342 type = "passive"; 5343 }; 5344 5345 mdmss3_config1: mdmss3-config1 { 5346 temperature = <105000>; 5347 hysteresis = <3000>; 5348 type = "passive"; 5349 }; 5350 5351 reset-mon-config { 5352 temperature = <115000>; 5353 hysteresis = <5000>; 5354 type = "passive"; 5355 }; 5356 }; 5357 }; 5358 5359 camera0-thermal { 5360 polling-delay-passive = <0>; 5361 polling-delay = <0>; 5362 thermal-sensors = <&tsens1 14>; 5363 5364 trips { 5365 thermal-engine-config { 5366 temperature = <125000>; 5367 hysteresis = <1000>; 5368 type = "passive"; 5369 }; 5370 5371 reset-mon-config { 5372 temperature = <115000>; 5373 hysteresis = <5000>; 5374 type = "passive"; 5375 }; 5376 }; 5377 }; 5378 5379 camera1-thermal { 5380 polling-delay-passive = <0>; 5381 polling-delay = <0>; 5382 thermal-sensors = <&tsens1 15>; 5383 5384 trips { 5385 thermal-engine-config { 5386 temperature = <125000>; 5387 hysteresis = <1000>; 5388 type = "passive"; 5389 }; 5390 5391 reset-mon-config { 5392 temperature = <115000>; 5393 hysteresis = <5000>; 5394 type = "passive"; 5395 }; 5396 }; 5397 }; 5398 5399 aoss2-thermal { 5400 polling-delay-passive = <0>; 5401 polling-delay = <0>; 5402 thermal-sensors = <&tsens2 0>; 5403 5404 trips { 5405 thermal-engine-config { 5406 temperature = <125000>; 5407 hysteresis = <1000>; 5408 type = "passive"; 5409 }; 5410 5411 reset-mon-config { 5412 temperature = <115000>; 5413 hysteresis = <5000>; 5414 type = "passive"; 5415 }; 5416 }; 5417 }; 5418 5419 gpuss-0-thermal { 5420 polling-delay-passive = <10>; 5421 polling-delay = <0>; 5422 thermal-sensors = <&tsens2 1>; 5423 5424 cooling-maps { 5425 map0 { 5426 trip = <&gpu0_junction_config>; 5427 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5428 }; 5429 }; 5430 5431 trips { 5432 thermal-engine-config { 5433 temperature = <125000>; 5434 hysteresis = <1000>; 5435 type = "passive"; 5436 }; 5437 5438 thermal-hal-config { 5439 temperature = <125000>; 5440 hysteresis = <1000>; 5441 type = "passive"; 5442 }; 5443 5444 reset-mon-config { 5445 temperature = <115000>; 5446 hysteresis = <5000>; 5447 type = "passive"; 5448 }; 5449 5450 gpu0_junction_config: junction-config { 5451 temperature = <95000>; 5452 hysteresis = <5000>; 5453 type = "passive"; 5454 }; 5455 }; 5456 }; 5457 5458 gpuss-1-thermal { 5459 polling-delay-passive = <10>; 5460 polling-delay = <0>; 5461 thermal-sensors = <&tsens2 2>; 5462 5463 cooling-maps { 5464 map0 { 5465 trip = <&gpu1_junction_config>; 5466 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5467 }; 5468 }; 5469 5470 trips { 5471 thermal-engine-config { 5472 temperature = <125000>; 5473 hysteresis = <1000>; 5474 type = "passive"; 5475 }; 5476 5477 thermal-hal-config { 5478 temperature = <125000>; 5479 hysteresis = <1000>; 5480 type = "passive"; 5481 }; 5482 5483 reset-mon-config { 5484 temperature = <115000>; 5485 hysteresis = <5000>; 5486 type = "passive"; 5487 }; 5488 5489 gpu1_junction_config: junction-config { 5490 temperature = <95000>; 5491 hysteresis = <5000>; 5492 type = "passive"; 5493 }; 5494 }; 5495 }; 5496 5497 gpuss-2-thermal { 5498 polling-delay-passive = <10>; 5499 polling-delay = <0>; 5500 thermal-sensors = <&tsens2 3>; 5501 5502 cooling-maps { 5503 map0 { 5504 trip = <&gpu2_junction_config>; 5505 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5506 }; 5507 }; 5508 5509 trips { 5510 thermal-engine-config { 5511 temperature = <125000>; 5512 hysteresis = <1000>; 5513 type = "passive"; 5514 }; 5515 5516 thermal-hal-config { 5517 temperature = <125000>; 5518 hysteresis = <1000>; 5519 type = "passive"; 5520 }; 5521 5522 reset-mon-config { 5523 temperature = <115000>; 5524 hysteresis = <5000>; 5525 type = "passive"; 5526 }; 5527 5528 gpu2_junction_config: junction-config { 5529 temperature = <95000>; 5530 hysteresis = <5000>; 5531 type = "passive"; 5532 }; 5533 }; 5534 }; 5535 5536 gpuss-3-thermal { 5537 polling-delay-passive = <10>; 5538 polling-delay = <0>; 5539 thermal-sensors = <&tsens2 4>; 5540 5541 cooling-maps { 5542 map0 { 5543 trip = <&gpu3_junction_config>; 5544 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5545 }; 5546 }; 5547 5548 trips { 5549 thermal-engine-config { 5550 temperature = <125000>; 5551 hysteresis = <1000>; 5552 type = "passive"; 5553 }; 5554 5555 thermal-hal-config { 5556 temperature = <125000>; 5557 hysteresis = <1000>; 5558 type = "passive"; 5559 }; 5560 5561 reset-mon-config { 5562 temperature = <115000>; 5563 hysteresis = <5000>; 5564 type = "passive"; 5565 }; 5566 5567 gpu3_junction_config: junction-config { 5568 temperature = <95000>; 5569 hysteresis = <5000>; 5570 type = "passive"; 5571 }; 5572 }; 5573 }; 5574 5575 gpuss-4-thermal { 5576 polling-delay-passive = <10>; 5577 polling-delay = <0>; 5578 thermal-sensors = <&tsens2 5>; 5579 5580 cooling-maps { 5581 map0 { 5582 trip = <&gpu4_junction_config>; 5583 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5584 }; 5585 }; 5586 5587 trips { 5588 thermal-engine-config { 5589 temperature = <125000>; 5590 hysteresis = <1000>; 5591 type = "passive"; 5592 }; 5593 5594 thermal-hal-config { 5595 temperature = <125000>; 5596 hysteresis = <1000>; 5597 type = "passive"; 5598 }; 5599 5600 reset-mon-config { 5601 temperature = <115000>; 5602 hysteresis = <5000>; 5603 type = "passive"; 5604 }; 5605 5606 gpu4_junction_config: junction-config { 5607 temperature = <95000>; 5608 hysteresis = <5000>; 5609 type = "passive"; 5610 }; 5611 }; 5612 }; 5613 5614 gpuss-5-thermal { 5615 polling-delay-passive = <10>; 5616 polling-delay = <0>; 5617 thermal-sensors = <&tsens2 6>; 5618 5619 cooling-maps { 5620 map0 { 5621 trip = <&gpu5_junction_config>; 5622 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5623 }; 5624 }; 5625 5626 trips { 5627 thermal-engine-config { 5628 temperature = <125000>; 5629 hysteresis = <1000>; 5630 type = "passive"; 5631 }; 5632 5633 thermal-hal-config { 5634 temperature = <125000>; 5635 hysteresis = <1000>; 5636 type = "passive"; 5637 }; 5638 5639 reset-mon-config { 5640 temperature = <115000>; 5641 hysteresis = <5000>; 5642 type = "passive"; 5643 }; 5644 5645 gpu5_junction_config: junction-config { 5646 temperature = <95000>; 5647 hysteresis = <5000>; 5648 type = "passive"; 5649 }; 5650 }; 5651 }; 5652 5653 gpuss-6-thermal { 5654 polling-delay-passive = <10>; 5655 polling-delay = <0>; 5656 thermal-sensors = <&tsens2 7>; 5657 5658 cooling-maps { 5659 map0 { 5660 trip = <&gpu6_junction_config>; 5661 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5662 }; 5663 }; 5664 5665 trips { 5666 thermal-engine-config { 5667 temperature = <125000>; 5668 hysteresis = <1000>; 5669 type = "passive"; 5670 }; 5671 5672 thermal-hal-config { 5673 temperature = <125000>; 5674 hysteresis = <1000>; 5675 type = "passive"; 5676 }; 5677 5678 reset-mon-config { 5679 temperature = <115000>; 5680 hysteresis = <5000>; 5681 type = "passive"; 5682 }; 5683 5684 gpu6_junction_config: junction-config { 5685 temperature = <95000>; 5686 hysteresis = <5000>; 5687 type = "passive"; 5688 }; 5689 }; 5690 }; 5691 5692 gpuss-7-thermal { 5693 polling-delay-passive = <10>; 5694 polling-delay = <0>; 5695 thermal-sensors = <&tsens2 8>; 5696 5697 cooling-maps { 5698 map0 { 5699 trip = <&gpu7_junction_config>; 5700 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5701 }; 5702 }; 5703 5704 trips { 5705 thermal-engine-config { 5706 temperature = <125000>; 5707 hysteresis = <1000>; 5708 type = "passive"; 5709 }; 5710 5711 thermal-hal-config { 5712 temperature = <125000>; 5713 hysteresis = <1000>; 5714 type = "passive"; 5715 }; 5716 5717 reset-mon-config { 5718 temperature = <115000>; 5719 hysteresis = <5000>; 5720 type = "passive"; 5721 }; 5722 5723 gpu7_junction_config: junction-config { 5724 temperature = <95000>; 5725 hysteresis = <5000>; 5726 type = "passive"; 5727 }; 5728 }; 5729 }; 5730 }; 5731 5732 timer { 5733 compatible = "arm,armv8-timer"; 5734 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5735 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5736 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5737 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5738 }; 5739}; 5740