1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 11#include <dt-bindings/clock/qcom,sm8450-gpucc.h> 12#include <dt-bindings/clock/qcom,sm8450-videocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/interconnect/qcom,icc.h> 21#include <dt-bindings/interconnect/qcom,sm8450.h> 22#include <dt-bindings/reset/qcom,sm8450-gpucc.h> 23#include <dt-bindings/soc/qcom,gpr.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 clocks { 37 xo_board: xo-board { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <76800000>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <32000>; 47 }; 48 }; 49 50 cpus { 51 #address-cells = <2>; 52 #size-cells = <0>; 53 54 cpu0: cpu@0 { 55 device_type = "cpu"; 56 compatible = "qcom,kryo780"; 57 reg = <0x0 0x0>; 58 enable-method = "psci"; 59 next-level-cache = <&l2_0>; 60 power-domains = <&cpu_pd0>; 61 power-domain-names = "psci"; 62 qcom,freq-domain = <&cpufreq_hw 0>; 63 #cooling-cells = <2>; 64 clocks = <&cpufreq_hw 0>; 65 l2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&l3_0>; 70 l3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 cpu1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo780"; 81 reg = <0x0 0x100>; 82 enable-method = "psci"; 83 next-level-cache = <&l2_100>; 84 power-domains = <&cpu_pd1>; 85 power-domain-names = "psci"; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 #cooling-cells = <2>; 88 clocks = <&cpufreq_hw 0>; 89 l2_100: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 next-level-cache = <&l3_0>; 94 }; 95 }; 96 97 cpu2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo780"; 100 reg = <0x0 0x200>; 101 enable-method = "psci"; 102 next-level-cache = <&l2_200>; 103 power-domains = <&cpu_pd2>; 104 power-domain-names = "psci"; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 #cooling-cells = <2>; 107 clocks = <&cpufreq_hw 0>; 108 l2_200: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&l3_0>; 113 }; 114 }; 115 116 cpu3: cpu@300 { 117 device_type = "cpu"; 118 compatible = "qcom,kryo780"; 119 reg = <0x0 0x300>; 120 enable-method = "psci"; 121 next-level-cache = <&l2_300>; 122 power-domains = <&cpu_pd3>; 123 power-domain-names = "psci"; 124 qcom,freq-domain = <&cpufreq_hw 0>; 125 #cooling-cells = <2>; 126 clocks = <&cpufreq_hw 0>; 127 l2_300: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 next-level-cache = <&l3_0>; 132 }; 133 }; 134 135 cpu4: cpu@400 { 136 device_type = "cpu"; 137 compatible = "qcom,kryo780"; 138 reg = <0x0 0x400>; 139 enable-method = "psci"; 140 next-level-cache = <&l2_400>; 141 power-domains = <&cpu_pd4>; 142 power-domain-names = "psci"; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 #cooling-cells = <2>; 145 clocks = <&cpufreq_hw 1>; 146 l2_400: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&l3_0>; 151 }; 152 }; 153 154 cpu5: cpu@500 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo780"; 157 reg = <0x0 0x500>; 158 enable-method = "psci"; 159 next-level-cache = <&l2_500>; 160 power-domains = <&cpu_pd5>; 161 power-domain-names = "psci"; 162 qcom,freq-domain = <&cpufreq_hw 1>; 163 #cooling-cells = <2>; 164 clocks = <&cpufreq_hw 1>; 165 l2_500: l2-cache { 166 compatible = "cache"; 167 cache-level = <2>; 168 cache-unified; 169 next-level-cache = <&l3_0>; 170 }; 171 }; 172 173 cpu6: cpu@600 { 174 device_type = "cpu"; 175 compatible = "qcom,kryo780"; 176 reg = <0x0 0x600>; 177 enable-method = "psci"; 178 next-level-cache = <&l2_600>; 179 power-domains = <&cpu_pd6>; 180 power-domain-names = "psci"; 181 qcom,freq-domain = <&cpufreq_hw 1>; 182 #cooling-cells = <2>; 183 clocks = <&cpufreq_hw 1>; 184 l2_600: l2-cache { 185 compatible = "cache"; 186 cache-level = <2>; 187 cache-unified; 188 next-level-cache = <&l3_0>; 189 }; 190 }; 191 192 cpu7: cpu@700 { 193 device_type = "cpu"; 194 compatible = "qcom,kryo780"; 195 reg = <0x0 0x700>; 196 enable-method = "psci"; 197 next-level-cache = <&l2_700>; 198 power-domains = <&cpu_pd7>; 199 power-domain-names = "psci"; 200 qcom,freq-domain = <&cpufreq_hw 2>; 201 #cooling-cells = <2>; 202 clocks = <&cpufreq_hw 2>; 203 l2_700: l2-cache { 204 compatible = "cache"; 205 cache-level = <2>; 206 cache-unified; 207 next-level-cache = <&l3_0>; 208 }; 209 }; 210 211 cpu-map { 212 cluster0 { 213 core0 { 214 cpu = <&cpu0>; 215 }; 216 217 core1 { 218 cpu = <&cpu1>; 219 }; 220 221 core2 { 222 cpu = <&cpu2>; 223 }; 224 225 core3 { 226 cpu = <&cpu3>; 227 }; 228 229 core4 { 230 cpu = <&cpu4>; 231 }; 232 233 core5 { 234 cpu = <&cpu5>; 235 }; 236 237 core6 { 238 cpu = <&cpu6>; 239 }; 240 241 core7 { 242 cpu = <&cpu7>; 243 }; 244 }; 245 }; 246 247 idle-states { 248 entry-method = "psci"; 249 250 little_cpu_sleep_0: cpu-sleep-0-0 { 251 compatible = "arm,idle-state"; 252 idle-state-name = "silver-rail-power-collapse"; 253 arm,psci-suspend-param = <0x40000004>; 254 entry-latency-us = <800>; 255 exit-latency-us = <750>; 256 min-residency-us = <4090>; 257 local-timer-stop; 258 }; 259 260 big_cpu_sleep_0: cpu-sleep-1-0 { 261 compatible = "arm,idle-state"; 262 idle-state-name = "gold-rail-power-collapse"; 263 arm,psci-suspend-param = <0x40000004>; 264 entry-latency-us = <600>; 265 exit-latency-us = <1550>; 266 min-residency-us = <4791>; 267 local-timer-stop; 268 }; 269 }; 270 271 domain-idle-states { 272 cluster_sleep_0: cluster-sleep-0 { 273 compatible = "domain-idle-state"; 274 arm,psci-suspend-param = <0x41000044>; 275 entry-latency-us = <1050>; 276 exit-latency-us = <2500>; 277 min-residency-us = <5309>; 278 }; 279 280 cluster_sleep_1: cluster-sleep-1 { 281 compatible = "domain-idle-state"; 282 arm,psci-suspend-param = <0x4100c344>; 283 entry-latency-us = <2700>; 284 exit-latency-us = <3500>; 285 min-residency-us = <13959>; 286 }; 287 }; 288 }; 289 290 firmware { 291 scm: scm { 292 compatible = "qcom,scm-sm8450", "qcom,scm"; 293 qcom,dload-mode = <&tcsr 0x13000>; 294 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 295 #reset-cells = <1>; 296 }; 297 }; 298 299 clk_virt: interconnect-0 { 300 compatible = "qcom,sm8450-clk-virt"; 301 #interconnect-cells = <2>; 302 qcom,bcm-voters = <&apps_bcm_voter>; 303 }; 304 305 mc_virt: interconnect-1 { 306 compatible = "qcom,sm8450-mc-virt"; 307 #interconnect-cells = <2>; 308 qcom,bcm-voters = <&apps_bcm_voter>; 309 }; 310 311 memory@a0000000 { 312 device_type = "memory"; 313 /* We expect the bootloader to fill in the size */ 314 reg = <0x0 0xa0000000 0x0 0x0>; 315 }; 316 317 pmu { 318 compatible = "arm,armv8-pmuv3"; 319 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 320 }; 321 322 psci { 323 compatible = "arm,psci-1.0"; 324 method = "smc"; 325 326 cpu_pd0: power-domain-cpu0 { 327 #power-domain-cells = <0>; 328 power-domains = <&cluster_pd>; 329 domain-idle-states = <&little_cpu_sleep_0>; 330 }; 331 332 cpu_pd1: power-domain-cpu1 { 333 #power-domain-cells = <0>; 334 power-domains = <&cluster_pd>; 335 domain-idle-states = <&little_cpu_sleep_0>; 336 }; 337 338 cpu_pd2: power-domain-cpu2 { 339 #power-domain-cells = <0>; 340 power-domains = <&cluster_pd>; 341 domain-idle-states = <&little_cpu_sleep_0>; 342 }; 343 344 cpu_pd3: power-domain-cpu3 { 345 #power-domain-cells = <0>; 346 power-domains = <&cluster_pd>; 347 domain-idle-states = <&little_cpu_sleep_0>; 348 }; 349 350 cpu_pd4: power-domain-cpu4 { 351 #power-domain-cells = <0>; 352 power-domains = <&cluster_pd>; 353 domain-idle-states = <&big_cpu_sleep_0>; 354 }; 355 356 cpu_pd5: power-domain-cpu5 { 357 #power-domain-cells = <0>; 358 power-domains = <&cluster_pd>; 359 domain-idle-states = <&big_cpu_sleep_0>; 360 }; 361 362 cpu_pd6: power-domain-cpu6 { 363 #power-domain-cells = <0>; 364 power-domains = <&cluster_pd>; 365 domain-idle-states = <&big_cpu_sleep_0>; 366 }; 367 368 cpu_pd7: power-domain-cpu7 { 369 #power-domain-cells = <0>; 370 power-domains = <&cluster_pd>; 371 domain-idle-states = <&big_cpu_sleep_0>; 372 }; 373 374 cluster_pd: power-domain-cpu-cluster0 { 375 #power-domain-cells = <0>; 376 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; 377 }; 378 }; 379 380 qup_opp_table_100mhz: opp-table-qup { 381 compatible = "operating-points-v2"; 382 383 opp-50000000 { 384 opp-hz = /bits/ 64 <50000000>; 385 required-opps = <&rpmhpd_opp_min_svs>; 386 }; 387 388 opp-75000000 { 389 opp-hz = /bits/ 64 <75000000>; 390 required-opps = <&rpmhpd_opp_low_svs>; 391 }; 392 393 opp-100000000 { 394 opp-hz = /bits/ 64 <100000000>; 395 required-opps = <&rpmhpd_opp_svs>; 396 }; 397 }; 398 399 reserved_memory: reserved-memory { 400 #address-cells = <2>; 401 #size-cells = <2>; 402 ranges; 403 404 hyp_mem: memory@80000000 { 405 reg = <0x0 0x80000000 0x0 0x600000>; 406 no-map; 407 }; 408 409 xbl_dt_log_mem: memory@80600000 { 410 reg = <0x0 0x80600000 0x0 0x40000>; 411 no-map; 412 }; 413 414 xbl_ramdump_mem: memory@80640000 { 415 reg = <0x0 0x80640000 0x0 0x180000>; 416 no-map; 417 }; 418 419 xbl_sc_mem: memory@807c0000 { 420 reg = <0x0 0x807c0000 0x0 0x40000>; 421 no-map; 422 }; 423 424 aop_image_mem: memory@80800000 { 425 reg = <0x0 0x80800000 0x0 0x60000>; 426 no-map; 427 }; 428 429 aop_cmd_db_mem: memory@80860000 { 430 compatible = "qcom,cmd-db"; 431 reg = <0x0 0x80860000 0x0 0x20000>; 432 no-map; 433 }; 434 435 aop_config_mem: memory@80880000 { 436 reg = <0x0 0x80880000 0x0 0x20000>; 437 no-map; 438 }; 439 440 tme_crash_dump_mem: memory@808a0000 { 441 reg = <0x0 0x808a0000 0x0 0x40000>; 442 no-map; 443 }; 444 445 tme_log_mem: memory@808e0000 { 446 reg = <0x0 0x808e0000 0x0 0x4000>; 447 no-map; 448 }; 449 450 uefi_log_mem: memory@808e4000 { 451 reg = <0x0 0x808e4000 0x0 0x10000>; 452 no-map; 453 }; 454 455 /* secdata region can be reused by apps */ 456 smem: memory@80900000 { 457 compatible = "qcom,smem"; 458 reg = <0x0 0x80900000 0x0 0x200000>; 459 hwlocks = <&tcsr_mutex 3>; 460 no-map; 461 }; 462 463 cpucp_fw_mem: memory@80b00000 { 464 reg = <0x0 0x80b00000 0x0 0x100000>; 465 no-map; 466 }; 467 468 cdsp_secure_heap: memory@80c00000 { 469 reg = <0x0 0x80c00000 0x0 0x4600000>; 470 no-map; 471 }; 472 473 video_mem: memory@85700000 { 474 reg = <0x0 0x85700000 0x0 0x700000>; 475 no-map; 476 }; 477 478 adsp_mem: memory@85e00000 { 479 reg = <0x0 0x85e00000 0x0 0x2100000>; 480 no-map; 481 }; 482 483 slpi_mem: memory@88000000 { 484 reg = <0x0 0x88000000 0x0 0x1900000>; 485 no-map; 486 }; 487 488 cdsp_mem: memory@89900000 { 489 reg = <0x0 0x89900000 0x0 0x2000000>; 490 no-map; 491 }; 492 493 ipa_fw_mem: memory@8b900000 { 494 reg = <0x0 0x8b900000 0x0 0x10000>; 495 no-map; 496 }; 497 498 ipa_gsi_mem: memory@8b910000 { 499 reg = <0x0 0x8b910000 0x0 0xa000>; 500 no-map; 501 }; 502 503 gpu_micro_code_mem: memory@8b91a000 { 504 reg = <0x0 0x8b91a000 0x0 0x2000>; 505 no-map; 506 }; 507 508 spss_region_mem: memory@8ba00000 { 509 reg = <0x0 0x8ba00000 0x0 0x180000>; 510 no-map; 511 }; 512 513 /* First part of the "SPU secure shared memory" region */ 514 spu_tz_shared_mem: memory@8bb80000 { 515 reg = <0x0 0x8bb80000 0x0 0x60000>; 516 no-map; 517 }; 518 519 /* Second part of the "SPU secure shared memory" region */ 520 spu_modem_shared_mem: memory@8bbe0000 { 521 reg = <0x0 0x8bbe0000 0x0 0x20000>; 522 no-map; 523 }; 524 525 mpss_mem: memory@8bc00000 { 526 reg = <0x0 0x8bc00000 0x0 0x13200000>; 527 no-map; 528 }; 529 530 cvp_mem: memory@9ee00000 { 531 reg = <0x0 0x9ee00000 0x0 0x700000>; 532 no-map; 533 }; 534 535 camera_mem: memory@9f500000 { 536 reg = <0x0 0x9f500000 0x0 0x800000>; 537 no-map; 538 }; 539 540 rmtfs_mem: memory@9fd00000 { 541 compatible = "qcom,rmtfs-mem"; 542 reg = <0x0 0x9fd00000 0x0 0x280000>; 543 no-map; 544 545 qcom,client-id = <1>; 546 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 547 }; 548 549 xbl_sc_mem2: memory@a6e00000 { 550 reg = <0x0 0xa6e00000 0x0 0x40000>; 551 no-map; 552 }; 553 554 global_sync_mem: memory@a6f00000 { 555 reg = <0x0 0xa6f00000 0x0 0x100000>; 556 no-map; 557 }; 558 559 /* uefi region can be reused by APPS */ 560 561 /* Linux kernel image is loaded at 0xa0000000 */ 562 563 oem_vm_mem: memory@bb000000 { 564 reg = <0x0 0xbb000000 0x0 0x5000000>; 565 no-map; 566 }; 567 568 mte_mem: memory@c0000000 { 569 reg = <0x0 0xc0000000 0x0 0x20000000>; 570 no-map; 571 }; 572 573 qheebsp_reserved_mem: memory@e0000000 { 574 reg = <0x0 0xe0000000 0x0 0x600000>; 575 no-map; 576 }; 577 578 cpusys_vm_mem: memory@e0600000 { 579 reg = <0x0 0xe0600000 0x0 0x400000>; 580 no-map; 581 }; 582 583 hyp_reserved_mem: memory@e0a00000 { 584 reg = <0x0 0xe0a00000 0x0 0x100000>; 585 no-map; 586 }; 587 588 trust_ui_vm_mem: memory@e0b00000 { 589 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 590 no-map; 591 }; 592 593 trust_ui_vm_qrtr: memory@e55f3000 { 594 reg = <0x0 0xe55f3000 0x0 0x9000>; 595 no-map; 596 }; 597 598 trust_ui_vm_vblk0_ring: memory@e55fc000 { 599 reg = <0x0 0xe55fc000 0x0 0x4000>; 600 no-map; 601 }; 602 603 trust_ui_vm_swiotlb: memory@e5600000 { 604 reg = <0x0 0xe5600000 0x0 0x100000>; 605 no-map; 606 }; 607 608 tz_stat_mem: memory@e8800000 { 609 reg = <0x0 0xe8800000 0x0 0x100000>; 610 no-map; 611 }; 612 613 tags_mem: memory@e8900000 { 614 reg = <0x0 0xe8900000 0x0 0x1200000>; 615 no-map; 616 }; 617 618 qtee_mem: memory@e9b00000 { 619 reg = <0x0 0xe9b00000 0x0 0x500000>; 620 no-map; 621 }; 622 623 trusted_apps_mem: memory@ea000000 { 624 reg = <0x0 0xea000000 0x0 0x3900000>; 625 no-map; 626 }; 627 628 trusted_apps_ext_mem: memory@ed900000 { 629 reg = <0x0 0xed900000 0x0 0x3b00000>; 630 no-map; 631 }; 632 }; 633 634 smp2p-adsp { 635 compatible = "qcom,smp2p"; 636 qcom,smem = <443>, <429>; 637 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 638 IPCC_MPROC_SIGNAL_SMP2P 639 IRQ_TYPE_EDGE_RISING>; 640 mboxes = <&ipcc IPCC_CLIENT_LPASS 641 IPCC_MPROC_SIGNAL_SMP2P>; 642 643 qcom,local-pid = <0>; 644 qcom,remote-pid = <2>; 645 646 smp2p_adsp_out: master-kernel { 647 qcom,entry-name = "master-kernel"; 648 #qcom,smem-state-cells = <1>; 649 }; 650 651 smp2p_adsp_in: slave-kernel { 652 qcom,entry-name = "slave-kernel"; 653 interrupt-controller; 654 #interrupt-cells = <2>; 655 }; 656 }; 657 658 smp2p-cdsp { 659 compatible = "qcom,smp2p"; 660 qcom,smem = <94>, <432>; 661 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 662 IPCC_MPROC_SIGNAL_SMP2P 663 IRQ_TYPE_EDGE_RISING>; 664 mboxes = <&ipcc IPCC_CLIENT_CDSP 665 IPCC_MPROC_SIGNAL_SMP2P>; 666 667 qcom,local-pid = <0>; 668 qcom,remote-pid = <5>; 669 670 smp2p_cdsp_out: master-kernel { 671 qcom,entry-name = "master-kernel"; 672 #qcom,smem-state-cells = <1>; 673 }; 674 675 smp2p_cdsp_in: slave-kernel { 676 qcom,entry-name = "slave-kernel"; 677 interrupt-controller; 678 #interrupt-cells = <2>; 679 }; 680 }; 681 682 smp2p-modem { 683 compatible = "qcom,smp2p"; 684 qcom,smem = <435>, <428>; 685 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 686 IPCC_MPROC_SIGNAL_SMP2P 687 IRQ_TYPE_EDGE_RISING>; 688 mboxes = <&ipcc IPCC_CLIENT_MPSS 689 IPCC_MPROC_SIGNAL_SMP2P>; 690 691 qcom,local-pid = <0>; 692 qcom,remote-pid = <1>; 693 694 smp2p_modem_out: master-kernel { 695 qcom,entry-name = "master-kernel"; 696 #qcom,smem-state-cells = <1>; 697 }; 698 699 smp2p_modem_in: slave-kernel { 700 qcom,entry-name = "slave-kernel"; 701 interrupt-controller; 702 #interrupt-cells = <2>; 703 }; 704 705 ipa_smp2p_out: ipa-ap-to-modem { 706 qcom,entry-name = "ipa"; 707 #qcom,smem-state-cells = <1>; 708 }; 709 710 ipa_smp2p_in: ipa-modem-to-ap { 711 qcom,entry-name = "ipa"; 712 interrupt-controller; 713 #interrupt-cells = <2>; 714 }; 715 }; 716 717 smp2p-slpi { 718 compatible = "qcom,smp2p"; 719 qcom,smem = <481>, <430>; 720 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 721 IPCC_MPROC_SIGNAL_SMP2P 722 IRQ_TYPE_EDGE_RISING>; 723 mboxes = <&ipcc IPCC_CLIENT_SLPI 724 IPCC_MPROC_SIGNAL_SMP2P>; 725 726 qcom,local-pid = <0>; 727 qcom,remote-pid = <3>; 728 729 smp2p_slpi_out: master-kernel { 730 qcom,entry-name = "master-kernel"; 731 #qcom,smem-state-cells = <1>; 732 }; 733 734 smp2p_slpi_in: slave-kernel { 735 qcom,entry-name = "slave-kernel"; 736 interrupt-controller; 737 #interrupt-cells = <2>; 738 }; 739 }; 740 741 soc: soc@0 { 742 #address-cells = <2>; 743 #size-cells = <2>; 744 ranges = <0 0 0 0 0x10 0>; 745 dma-ranges = <0 0 0 0 0x10 0>; 746 compatible = "simple-bus"; 747 748 gcc: clock-controller@100000 { 749 compatible = "qcom,gcc-sm8450"; 750 reg = <0x0 0x00100000 0x0 0x1f4200>; 751 #clock-cells = <1>; 752 #reset-cells = <1>; 753 #power-domain-cells = <1>; 754 clocks = <&rpmhcc RPMH_CXO_CLK>, 755 <&sleep_clk>, 756 <&pcie0_phy>, 757 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 758 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 759 <&ufs_mem_phy 0>, 760 <&ufs_mem_phy 1>, 761 <&ufs_mem_phy 2>, 762 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 763 clock-names = "bi_tcxo", 764 "sleep_clk", 765 "pcie_0_pipe_clk", 766 "pcie_1_pipe_clk", 767 "pcie_1_phy_aux_clk", 768 "ufs_phy_rx_symbol_0_clk", 769 "ufs_phy_rx_symbol_1_clk", 770 "ufs_phy_tx_symbol_0_clk", 771 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 772 }; 773 774 gpi_dma2: dma-controller@800000 { 775 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 776 #dma-cells = <3>; 777 reg = <0 0x00800000 0 0x60000>; 778 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 790 dma-channels = <12>; 791 dma-channel-mask = <0x7e>; 792 iommus = <&apps_smmu 0x496 0x0>; 793 status = "disabled"; 794 }; 795 796 qupv3_id_2: geniqup@8c0000 { 797 compatible = "qcom,geni-se-qup"; 798 reg = <0x0 0x008c0000 0x0 0x2000>; 799 clock-names = "m-ahb", "s-ahb"; 800 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 801 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 802 iommus = <&apps_smmu 0x483 0x0>; 803 #address-cells = <2>; 804 #size-cells = <2>; 805 ranges; 806 status = "disabled"; 807 808 i2c15: i2c@880000 { 809 compatible = "qcom,geni-i2c"; 810 reg = <0x0 0x00880000 0x0 0x4000>; 811 clock-names = "se"; 812 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&qup_i2c15_data_clk>; 815 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 819 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 820 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 821 interconnect-names = "qup-core", "qup-config", "qup-memory"; 822 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 823 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 824 dma-names = "tx", "rx"; 825 status = "disabled"; 826 }; 827 828 spi15: spi@880000 { 829 compatible = "qcom,geni-spi"; 830 reg = <0x0 0x00880000 0x0 0x4000>; 831 clock-names = "se"; 832 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 833 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 836 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 837 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 838 interconnect-names = "qup-core", "qup-config"; 839 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 840 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 841 dma-names = "tx", "rx"; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 status = "disabled"; 845 }; 846 847 i2c16: i2c@884000 { 848 compatible = "qcom,geni-i2c"; 849 reg = <0x0 0x00884000 0x0 0x4000>; 850 clock-names = "se"; 851 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 852 pinctrl-names = "default"; 853 pinctrl-0 = <&qup_i2c16_data_clk>; 854 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 858 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 859 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 860 interconnect-names = "qup-core", "qup-config", "qup-memory"; 861 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 862 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 863 dma-names = "tx", "rx"; 864 status = "disabled"; 865 }; 866 867 spi16: spi@884000 { 868 compatible = "qcom,geni-spi"; 869 reg = <0x0 0x00884000 0x0 0x4000>; 870 clock-names = "se"; 871 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 872 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 875 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 876 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 877 interconnect-names = "qup-core", "qup-config"; 878 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 879 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 880 dma-names = "tx", "rx"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 status = "disabled"; 884 }; 885 886 i2c17: i2c@888000 { 887 compatible = "qcom,geni-i2c"; 888 reg = <0x0 0x00888000 0x0 0x4000>; 889 clock-names = "se"; 890 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 891 pinctrl-names = "default"; 892 pinctrl-0 = <&qup_i2c17_data_clk>; 893 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 897 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 898 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 899 interconnect-names = "qup-core", "qup-config", "qup-memory"; 900 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 901 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 902 dma-names = "tx", "rx"; 903 status = "disabled"; 904 }; 905 906 spi17: spi@888000 { 907 compatible = "qcom,geni-spi"; 908 reg = <0x0 0x00888000 0x0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 911 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 914 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 915 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 916 interconnect-names = "qup-core", "qup-config"; 917 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 918 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 919 dma-names = "tx", "rx"; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 status = "disabled"; 923 }; 924 925 i2c18: i2c@88c000 { 926 compatible = "qcom,geni-i2c"; 927 reg = <0x0 0x0088c000 0x0 0x4000>; 928 clock-names = "se"; 929 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 930 pinctrl-names = "default"; 931 pinctrl-0 = <&qup_i2c18_data_clk>; 932 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 936 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 937 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 938 interconnect-names = "qup-core", "qup-config", "qup-memory"; 939 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 940 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 941 dma-names = "tx", "rx"; 942 status = "disabled"; 943 }; 944 945 spi18: spi@88c000 { 946 compatible = "qcom,geni-spi"; 947 reg = <0 0x0088c000 0 0x4000>; 948 clock-names = "se"; 949 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 950 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 953 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 954 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 955 interconnect-names = "qup-core", "qup-config"; 956 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 957 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 958 dma-names = "tx", "rx"; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 status = "disabled"; 962 }; 963 964 i2c19: i2c@890000 { 965 compatible = "qcom,geni-i2c"; 966 reg = <0x0 0x00890000 0x0 0x4000>; 967 clock-names = "se"; 968 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 969 pinctrl-names = "default"; 970 pinctrl-0 = <&qup_i2c19_data_clk>; 971 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 975 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 976 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 977 interconnect-names = "qup-core", "qup-config", "qup-memory"; 978 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 979 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 980 dma-names = "tx", "rx"; 981 status = "disabled"; 982 }; 983 984 spi19: spi@890000 { 985 compatible = "qcom,geni-spi"; 986 reg = <0 0x00890000 0 0x4000>; 987 clock-names = "se"; 988 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 989 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 990 pinctrl-names = "default"; 991 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 992 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 993 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 994 interconnect-names = "qup-core", "qup-config"; 995 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 996 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 997 dma-names = "tx", "rx"; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 i2c20: i2c@894000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0x0 0x00894000 0x0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&qup_i2c20_data_clk>; 1010 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1014 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1015 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1016 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1017 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1018 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1019 dma-names = "tx", "rx"; 1020 status = "disabled"; 1021 }; 1022 1023 uart20: serial@894000 { 1024 compatible = "qcom,geni-uart"; 1025 reg = <0 0x00894000 0 0x4000>; 1026 clock-names = "se"; 1027 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1028 pinctrl-names = "default"; 1029 pinctrl-0 = <&qup_uart20_default>; 1030 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1031 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1032 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1033 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1034 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1035 interconnect-names = "qup-core", 1036 "qup-config"; 1037 status = "disabled"; 1038 }; 1039 1040 spi20: spi@894000 { 1041 compatible = "qcom,geni-spi"; 1042 reg = <0 0x00894000 0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1045 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1046 pinctrl-names = "default"; 1047 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1048 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1049 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1050 interconnect-names = "qup-core", "qup-config"; 1051 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1052 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1053 dma-names = "tx", "rx"; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 status = "disabled"; 1057 }; 1058 1059 i2c21: i2c@898000 { 1060 compatible = "qcom,geni-i2c"; 1061 reg = <0x0 0x00898000 0x0 0x4000>; 1062 clock-names = "se"; 1063 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1064 pinctrl-names = "default"; 1065 pinctrl-0 = <&qup_i2c21_data_clk>; 1066 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1070 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1071 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1072 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1073 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1074 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1075 dma-names = "tx", "rx"; 1076 status = "disabled"; 1077 }; 1078 1079 spi21: spi@898000 { 1080 compatible = "qcom,geni-spi"; 1081 reg = <0 0x00898000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1084 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1085 pinctrl-names = "default"; 1086 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1087 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1088 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1089 interconnect-names = "qup-core", "qup-config"; 1090 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1091 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1092 dma-names = "tx", "rx"; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 status = "disabled"; 1096 }; 1097 }; 1098 1099 gpi_dma0: dma-controller@900000 { 1100 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1101 #dma-cells = <3>; 1102 reg = <0 0x00900000 0 0x60000>; 1103 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1115 dma-channels = <12>; 1116 dma-channel-mask = <0x7e>; 1117 iommus = <&apps_smmu 0x5b6 0x0>; 1118 status = "disabled"; 1119 }; 1120 1121 qupv3_id_0: geniqup@9c0000 { 1122 compatible = "qcom,geni-se-qup"; 1123 reg = <0x0 0x009c0000 0x0 0x2000>; 1124 clock-names = "m-ahb", "s-ahb"; 1125 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1126 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1127 iommus = <&apps_smmu 0x5a3 0x0>; 1128 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1129 interconnect-names = "qup-core"; 1130 #address-cells = <2>; 1131 #size-cells = <2>; 1132 ranges; 1133 status = "disabled"; 1134 1135 i2c0: i2c@980000 { 1136 compatible = "qcom,geni-i2c"; 1137 reg = <0x0 0x00980000 0x0 0x4000>; 1138 clock-names = "se"; 1139 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1140 pinctrl-names = "default"; 1141 pinctrl-0 = <&qup_i2c0_data_clk>; 1142 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1146 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1147 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1148 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1149 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1150 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1151 dma-names = "tx", "rx"; 1152 status = "disabled"; 1153 }; 1154 1155 spi0: spi@980000 { 1156 compatible = "qcom,geni-spi"; 1157 reg = <0x0 0x00980000 0x0 0x4000>; 1158 clock-names = "se"; 1159 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1160 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1163 power-domains = <&rpmhpd RPMHPD_CX>; 1164 operating-points-v2 = <&qup_opp_table_100mhz>; 1165 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1166 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1167 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1168 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1169 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1170 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1171 dma-names = "tx", "rx"; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 i2c1: i2c@984000 { 1178 compatible = "qcom,geni-i2c"; 1179 reg = <0x0 0x00984000 0x0 0x4000>; 1180 clock-names = "se"; 1181 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1182 pinctrl-names = "default"; 1183 pinctrl-0 = <&qup_i2c1_data_clk>; 1184 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1188 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1189 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1190 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1191 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1192 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1193 dma-names = "tx", "rx"; 1194 status = "disabled"; 1195 }; 1196 1197 spi1: spi@984000 { 1198 compatible = "qcom,geni-spi"; 1199 reg = <0x0 0x00984000 0x0 0x4000>; 1200 clock-names = "se"; 1201 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1202 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1203 pinctrl-names = "default"; 1204 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1205 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1206 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1207 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1208 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1209 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1210 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1211 dma-names = "tx", "rx"; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 status = "disabled"; 1215 }; 1216 1217 i2c2: i2c@988000 { 1218 compatible = "qcom,geni-i2c"; 1219 reg = <0x0 0x00988000 0x0 0x4000>; 1220 clock-names = "se"; 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&qup_i2c2_data_clk>; 1224 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1225 #address-cells = <1>; 1226 #size-cells = <0>; 1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1228 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1229 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1230 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1231 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1232 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1233 dma-names = "tx", "rx"; 1234 status = "disabled"; 1235 }; 1236 1237 spi2: spi@988000 { 1238 compatible = "qcom,geni-spi"; 1239 reg = <0x0 0x00988000 0x0 0x4000>; 1240 clock-names = "se"; 1241 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1242 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1245 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1246 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1247 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1248 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1249 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1250 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1251 dma-names = "tx", "rx"; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 status = "disabled"; 1255 }; 1256 1257 1258 i2c3: i2c@98c000 { 1259 compatible = "qcom,geni-i2c"; 1260 reg = <0x0 0x0098c000 0x0 0x4000>; 1261 clock-names = "se"; 1262 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1263 pinctrl-names = "default"; 1264 pinctrl-0 = <&qup_i2c3_data_clk>; 1265 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1266 #address-cells = <1>; 1267 #size-cells = <0>; 1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1269 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1270 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1271 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1272 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1273 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1274 dma-names = "tx", "rx"; 1275 status = "disabled"; 1276 }; 1277 1278 spi3: spi@98c000 { 1279 compatible = "qcom,geni-spi"; 1280 reg = <0x0 0x0098c000 0x0 0x4000>; 1281 clock-names = "se"; 1282 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1283 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1286 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1287 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1288 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1289 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1290 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1291 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1292 dma-names = "tx", "rx"; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 status = "disabled"; 1296 }; 1297 1298 i2c4: i2c@990000 { 1299 compatible = "qcom,geni-i2c"; 1300 reg = <0x0 0x00990000 0x0 0x4000>; 1301 clock-names = "se"; 1302 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&qup_i2c4_data_clk>; 1305 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1309 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1310 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1311 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1312 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1313 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1314 dma-names = "tx", "rx"; 1315 status = "disabled"; 1316 }; 1317 1318 spi4: spi@990000 { 1319 compatible = "qcom,geni-spi"; 1320 reg = <0x0 0x00990000 0x0 0x4000>; 1321 clock-names = "se"; 1322 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1323 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1324 pinctrl-names = "default"; 1325 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1326 power-domains = <&rpmhpd RPMHPD_CX>; 1327 operating-points-v2 = <&qup_opp_table_100mhz>; 1328 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1329 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1330 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1331 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1332 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1333 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1334 dma-names = "tx", "rx"; 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 status = "disabled"; 1338 }; 1339 1340 i2c5: i2c@994000 { 1341 compatible = "qcom,geni-i2c"; 1342 reg = <0x0 0x00994000 0x0 0x4000>; 1343 clock-names = "se"; 1344 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1345 pinctrl-names = "default"; 1346 pinctrl-0 = <&qup_i2c5_data_clk>; 1347 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1351 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1352 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1353 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1354 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1355 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1356 dma-names = "tx", "rx"; 1357 status = "disabled"; 1358 }; 1359 1360 spi5: spi@994000 { 1361 compatible = "qcom,geni-spi"; 1362 reg = <0x0 0x00994000 0x0 0x4000>; 1363 clock-names = "se"; 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1365 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1366 pinctrl-names = "default"; 1367 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1368 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1369 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1370 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1371 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1372 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1373 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1374 dma-names = "tx", "rx"; 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 status = "disabled"; 1378 }; 1379 1380 1381 i2c6: i2c@998000 { 1382 compatible = "qcom,geni-i2c"; 1383 reg = <0x0 0x00998000 0x0 0x4000>; 1384 clock-names = "se"; 1385 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1386 pinctrl-names = "default"; 1387 pinctrl-0 = <&qup_i2c6_data_clk>; 1388 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1392 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1393 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1394 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1395 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1396 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1397 dma-names = "tx", "rx"; 1398 status = "disabled"; 1399 }; 1400 1401 spi6: spi@998000 { 1402 compatible = "qcom,geni-spi"; 1403 reg = <0x0 0x00998000 0x0 0x4000>; 1404 clock-names = "se"; 1405 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1406 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1407 pinctrl-names = "default"; 1408 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1409 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1410 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1411 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1412 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1413 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1414 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1415 dma-names = "tx", "rx"; 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 status = "disabled"; 1419 }; 1420 1421 uart7: serial@99c000 { 1422 compatible = "qcom,geni-debug-uart"; 1423 reg = <0 0x0099c000 0 0x4000>; 1424 clock-names = "se"; 1425 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1426 pinctrl-names = "default"; 1427 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1428 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1429 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1430 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1431 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1432 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1433 interconnect-names = "qup-core", 1434 "qup-config"; 1435 status = "disabled"; 1436 }; 1437 }; 1438 1439 gpi_dma1: dma-controller@a00000 { 1440 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1441 #dma-cells = <3>; 1442 reg = <0 0x00a00000 0 0x60000>; 1443 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1455 dma-channels = <12>; 1456 dma-channel-mask = <0x7e>; 1457 iommus = <&apps_smmu 0x56 0x0>; 1458 status = "disabled"; 1459 }; 1460 1461 qupv3_id_1: geniqup@ac0000 { 1462 compatible = "qcom,geni-se-qup"; 1463 reg = <0x0 0x00ac0000 0x0 0x6000>; 1464 clock-names = "m-ahb", "s-ahb"; 1465 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1466 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1467 iommus = <&apps_smmu 0x43 0x0>; 1468 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1469 interconnect-names = "qup-core"; 1470 #address-cells = <2>; 1471 #size-cells = <2>; 1472 ranges; 1473 status = "disabled"; 1474 1475 i2c8: i2c@a80000 { 1476 compatible = "qcom,geni-i2c"; 1477 reg = <0x0 0x00a80000 0x0 0x4000>; 1478 clock-names = "se"; 1479 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_i2c8_data_clk>; 1482 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1486 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1487 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1488 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1489 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1490 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1491 dma-names = "tx", "rx"; 1492 status = "disabled"; 1493 }; 1494 1495 spi8: spi@a80000 { 1496 compatible = "qcom,geni-spi"; 1497 reg = <0x0 0x00a80000 0x0 0x4000>; 1498 clock-names = "se"; 1499 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1500 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1503 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1504 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1505 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1506 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1507 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1508 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1509 dma-names = "tx", "rx"; 1510 #address-cells = <1>; 1511 #size-cells = <0>; 1512 status = "disabled"; 1513 }; 1514 1515 i2c9: i2c@a84000 { 1516 compatible = "qcom,geni-i2c"; 1517 reg = <0x0 0x00a84000 0x0 0x4000>; 1518 clock-names = "se"; 1519 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1520 pinctrl-names = "default"; 1521 pinctrl-0 = <&qup_i2c9_data_clk>; 1522 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1523 #address-cells = <1>; 1524 #size-cells = <0>; 1525 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1526 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1527 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1528 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1529 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1530 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1531 dma-names = "tx", "rx"; 1532 status = "disabled"; 1533 }; 1534 1535 spi9: spi@a84000 { 1536 compatible = "qcom,geni-spi"; 1537 reg = <0x0 0x00a84000 0x0 0x4000>; 1538 clock-names = "se"; 1539 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1540 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1541 pinctrl-names = "default"; 1542 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1544 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1545 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1546 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1547 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1548 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1549 dma-names = "tx", "rx"; 1550 #address-cells = <1>; 1551 #size-cells = <0>; 1552 status = "disabled"; 1553 }; 1554 1555 i2c10: i2c@a88000 { 1556 compatible = "qcom,geni-i2c"; 1557 reg = <0x0 0x00a88000 0x0 0x4000>; 1558 clock-names = "se"; 1559 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1560 pinctrl-names = "default"; 1561 pinctrl-0 = <&qup_i2c10_data_clk>; 1562 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1566 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1567 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1568 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1569 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1570 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1571 dma-names = "tx", "rx"; 1572 status = "disabled"; 1573 }; 1574 1575 spi10: spi@a88000 { 1576 compatible = "qcom,geni-spi"; 1577 reg = <0x0 0x00a88000 0x0 0x4000>; 1578 clock-names = "se"; 1579 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1580 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1581 pinctrl-names = "default"; 1582 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1584 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1585 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1586 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1587 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1588 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1589 dma-names = "tx", "rx"; 1590 #address-cells = <1>; 1591 #size-cells = <0>; 1592 status = "disabled"; 1593 }; 1594 1595 i2c11: i2c@a8c000 { 1596 compatible = "qcom,geni-i2c"; 1597 reg = <0x0 0x00a8c000 0x0 0x4000>; 1598 clock-names = "se"; 1599 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1600 pinctrl-names = "default"; 1601 pinctrl-0 = <&qup_i2c11_data_clk>; 1602 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1606 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1607 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1608 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1609 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1610 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1611 dma-names = "tx", "rx"; 1612 status = "disabled"; 1613 }; 1614 1615 spi11: spi@a8c000 { 1616 compatible = "qcom,geni-spi"; 1617 reg = <0x0 0x00a8c000 0x0 0x4000>; 1618 clock-names = "se"; 1619 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1620 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1621 pinctrl-names = "default"; 1622 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1624 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1625 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1626 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1627 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1628 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1629 dma-names = "tx", "rx"; 1630 #address-cells = <1>; 1631 #size-cells = <0>; 1632 status = "disabled"; 1633 }; 1634 1635 i2c12: i2c@a90000 { 1636 compatible = "qcom,geni-i2c"; 1637 reg = <0x0 0x00a90000 0x0 0x4000>; 1638 clock-names = "se"; 1639 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1640 pinctrl-names = "default"; 1641 pinctrl-0 = <&qup_i2c12_data_clk>; 1642 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1646 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1647 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1648 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1649 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1650 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1651 dma-names = "tx", "rx"; 1652 status = "disabled"; 1653 }; 1654 1655 spi12: spi@a90000 { 1656 compatible = "qcom,geni-spi"; 1657 reg = <0x0 0x00a90000 0x0 0x4000>; 1658 clock-names = "se"; 1659 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1660 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1661 pinctrl-names = "default"; 1662 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1663 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1664 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1665 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1666 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1667 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1668 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1669 dma-names = "tx", "rx"; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 status = "disabled"; 1673 }; 1674 1675 i2c13: i2c@a94000 { 1676 compatible = "qcom,geni-i2c"; 1677 reg = <0 0x00a94000 0 0x4000>; 1678 clock-names = "se"; 1679 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1680 pinctrl-names = "default"; 1681 pinctrl-0 = <&qup_i2c13_data_clk>; 1682 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1684 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1685 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1686 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1687 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1688 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1689 dma-names = "tx", "rx"; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 status = "disabled"; 1693 }; 1694 1695 spi13: spi@a94000 { 1696 compatible = "qcom,geni-spi"; 1697 reg = <0x0 0x00a94000 0x0 0x4000>; 1698 clock-names = "se"; 1699 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1700 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1701 pinctrl-names = "default"; 1702 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1703 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1704 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1705 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1706 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1707 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1708 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1709 dma-names = "tx", "rx"; 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 status = "disabled"; 1713 }; 1714 1715 i2c14: i2c@a98000 { 1716 compatible = "qcom,geni-i2c"; 1717 reg = <0 0x00a98000 0 0x4000>; 1718 clock-names = "se"; 1719 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1720 pinctrl-names = "default"; 1721 pinctrl-0 = <&qup_i2c14_data_clk>; 1722 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1723 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1724 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1725 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1726 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1727 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1728 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1729 dma-names = "tx", "rx"; 1730 #address-cells = <1>; 1731 #size-cells = <0>; 1732 status = "disabled"; 1733 }; 1734 1735 spi14: spi@a98000 { 1736 compatible = "qcom,geni-spi"; 1737 reg = <0x0 0x00a98000 0x0 0x4000>; 1738 clock-names = "se"; 1739 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1740 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1741 pinctrl-names = "default"; 1742 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1743 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1744 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1745 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1746 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1747 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1748 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1749 dma-names = "tx", "rx"; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 status = "disabled"; 1753 }; 1754 }; 1755 1756 rng: rng@10c3000 { 1757 compatible = "qcom,sm8450-trng", "qcom,trng"; 1758 reg = <0 0x010c3000 0 0x1000>; 1759 }; 1760 1761 pcie0: pcie@1c00000 { 1762 compatible = "qcom,pcie-sm8450-pcie0"; 1763 reg = <0 0x01c00000 0 0x3000>, 1764 <0 0x60000000 0 0xf1d>, 1765 <0 0x60000f20 0 0xa8>, 1766 <0 0x60001000 0 0x1000>, 1767 <0 0x60100000 0 0x100000>; 1768 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1769 device_type = "pci"; 1770 linux,pci-domain = <0>; 1771 bus-range = <0x00 0xff>; 1772 num-lanes = <1>; 1773 1774 #address-cells = <3>; 1775 #size-cells = <2>; 1776 1777 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1778 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1779 1780 msi-map = <0x0 &gic_its 0x5980 0x1>, 1781 <0x100 &gic_its 0x5981 0x1>; 1782 msi-map-mask = <0xff00>; 1783 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1792 interrupt-names = "msi0", 1793 "msi1", 1794 "msi2", 1795 "msi3", 1796 "msi4", 1797 "msi5", 1798 "msi6", 1799 "msi7", 1800 "global"; 1801 #interrupt-cells = <1>; 1802 interrupt-map-mask = <0 0 0 0x7>; 1803 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1804 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1805 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1806 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1807 1808 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 1809 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1810 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1811 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 1812 interconnect-names = "pcie-mem", "cpu-pcie"; 1813 1814 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1815 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1816 <&pcie0_phy>, 1817 <&rpmhcc RPMH_CXO_CLK>, 1818 <&gcc GCC_PCIE_0_AUX_CLK>, 1819 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1820 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1821 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1822 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1823 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1824 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1825 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1826 clock-names = "pipe", 1827 "pipe_mux", 1828 "phy_pipe", 1829 "ref", 1830 "aux", 1831 "cfg", 1832 "bus_master", 1833 "bus_slave", 1834 "slave_q2a", 1835 "ddrss_sf_tbu", 1836 "aggre0", 1837 "aggre1"; 1838 1839 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1840 <0x100 &apps_smmu 0x1c01 0x1>; 1841 1842 resets = <&gcc GCC_PCIE_0_BCR>; 1843 reset-names = "pci"; 1844 1845 power-domains = <&gcc PCIE_0_GDSC>; 1846 1847 phys = <&pcie0_phy>; 1848 phy-names = "pciephy"; 1849 1850 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1851 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1852 1853 pinctrl-names = "default"; 1854 pinctrl-0 = <&pcie0_default_state>; 1855 1856 operating-points-v2 = <&pcie0_opp_table>; 1857 1858 status = "disabled"; 1859 1860 pcie0_opp_table: opp-table { 1861 compatible = "operating-points-v2"; 1862 1863 /* GEN 1 x1 */ 1864 opp-2500000 { 1865 opp-hz = /bits/ 64 <2500000>; 1866 required-opps = <&rpmhpd_opp_low_svs>; 1867 opp-peak-kBps = <250000 1>; 1868 }; 1869 1870 /* GEN 2 x1 */ 1871 opp-5000000 { 1872 opp-hz = /bits/ 64 <5000000>; 1873 required-opps = <&rpmhpd_opp_low_svs>; 1874 opp-peak-kBps = <500000 1>; 1875 }; 1876 1877 /* GEN 3 x1 */ 1878 opp-8000000 { 1879 opp-hz = /bits/ 64 <8000000>; 1880 required-opps = <&rpmhpd_opp_nom>; 1881 opp-peak-kBps = <984500 1>; 1882 }; 1883 }; 1884 1885 pcieport0: pcie@0 { 1886 device_type = "pci"; 1887 reg = <0x0 0x0 0x0 0x0 0x0>; 1888 bus-range = <0x01 0xff>; 1889 1890 #address-cells = <3>; 1891 #size-cells = <2>; 1892 ranges; 1893 }; 1894 }; 1895 1896 pcie0_phy: phy@1c06000 { 1897 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1898 reg = <0 0x01c06000 0 0x2000>; 1899 1900 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1901 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1902 <&gcc GCC_PCIE_0_CLKREF_EN>, 1903 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1904 <&gcc GCC_PCIE_0_PIPE_CLK>; 1905 clock-names = "aux", 1906 "cfg_ahb", 1907 "ref", 1908 "rchng", 1909 "pipe"; 1910 1911 clock-output-names = "pcie_0_pipe_clk"; 1912 #clock-cells = <0>; 1913 1914 #phy-cells = <0>; 1915 1916 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1917 reset-names = "phy"; 1918 1919 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1920 assigned-clock-rates = <100000000>; 1921 1922 status = "disabled"; 1923 }; 1924 1925 pcie1: pcie@1c08000 { 1926 compatible = "qcom,pcie-sm8450-pcie1"; 1927 reg = <0 0x01c08000 0 0x3000>, 1928 <0 0x40000000 0 0xf1d>, 1929 <0 0x40000f20 0 0xa8>, 1930 <0 0x40001000 0 0x1000>, 1931 <0 0x40100000 0 0x100000>; 1932 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1933 device_type = "pci"; 1934 linux,pci-domain = <1>; 1935 bus-range = <0x00 0xff>; 1936 num-lanes = <2>; 1937 1938 #address-cells = <3>; 1939 #size-cells = <2>; 1940 1941 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1942 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1943 1944 msi-map = <0x0 &gic_its 0x5a00 0x1>, 1945 <0x100 &gic_its 0x5a01 0x1>; 1946 msi-map-mask = <0xff00>; 1947 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1956 interrupt-names = "msi0", 1957 "msi1", 1958 "msi2", 1959 "msi3", 1960 "msi4", 1961 "msi5", 1962 "msi6", 1963 "msi7", 1964 "global"; 1965 #interrupt-cells = <1>; 1966 interrupt-map-mask = <0 0 0 0x7>; 1967 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1968 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1969 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1970 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1971 1972 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 1973 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1974 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1975 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; 1976 interconnect-names = "pcie-mem", "cpu-pcie"; 1977 1978 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1979 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1980 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 1981 <&rpmhcc RPMH_CXO_CLK>, 1982 <&gcc GCC_PCIE_1_AUX_CLK>, 1983 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1984 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1985 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1986 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1987 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1988 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1989 clock-names = "pipe", 1990 "pipe_mux", 1991 "phy_pipe", 1992 "ref", 1993 "aux", 1994 "cfg", 1995 "bus_master", 1996 "bus_slave", 1997 "slave_q2a", 1998 "ddrss_sf_tbu", 1999 "aggre1"; 2000 2001 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2002 <0x100 &apps_smmu 0x1c81 0x1>; 2003 2004 resets = <&gcc GCC_PCIE_1_BCR>; 2005 reset-names = "pci"; 2006 2007 power-domains = <&gcc PCIE_1_GDSC>; 2008 2009 phys = <&pcie1_phy>; 2010 phy-names = "pciephy"; 2011 2012 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 2013 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 2014 2015 pinctrl-names = "default"; 2016 pinctrl-0 = <&pcie1_default_state>; 2017 2018 operating-points-v2 = <&pcie1_opp_table>; 2019 2020 status = "disabled"; 2021 2022 pcie1_opp_table: opp-table { 2023 compatible = "operating-points-v2"; 2024 2025 /* GEN 1 x1 */ 2026 opp-2500000 { 2027 opp-hz = /bits/ 64 <2500000>; 2028 required-opps = <&rpmhpd_opp_low_svs>; 2029 opp-peak-kBps = <250000 1>; 2030 }; 2031 2032 /* GEN 1 x2 and GEN 2 x1 */ 2033 opp-5000000 { 2034 opp-hz = /bits/ 64 <5000000>; 2035 required-opps = <&rpmhpd_opp_low_svs>; 2036 opp-peak-kBps = <500000 1>; 2037 }; 2038 2039 /* GEN 2 x2 */ 2040 opp-10000000 { 2041 opp-hz = /bits/ 64 <10000000>; 2042 required-opps = <&rpmhpd_opp_low_svs>; 2043 opp-peak-kBps = <1000000 1>; 2044 }; 2045 2046 /* GEN 3 x1 */ 2047 opp-8000000 { 2048 opp-hz = /bits/ 64 <8000000>; 2049 required-opps = <&rpmhpd_opp_nom>; 2050 opp-peak-kBps = <984500 1>; 2051 }; 2052 2053 /* GEN 3 x2 and GEN 4 x1 */ 2054 opp-16000000 { 2055 opp-hz = /bits/ 64 <16000000>; 2056 required-opps = <&rpmhpd_opp_nom>; 2057 opp-peak-kBps = <1969000 1>; 2058 }; 2059 2060 /* GEN 4 x2 */ 2061 opp-32000000 { 2062 opp-hz = /bits/ 64 <32000000>; 2063 required-opps = <&rpmhpd_opp_nom>; 2064 opp-peak-kBps = <3938000 1>; 2065 }; 2066 }; 2067 2068 pcie@0 { 2069 device_type = "pci"; 2070 reg = <0x0 0x0 0x0 0x0 0x0>; 2071 bus-range = <0x01 0xff>; 2072 2073 #address-cells = <3>; 2074 #size-cells = <2>; 2075 ranges; 2076 }; 2077 }; 2078 2079 pcie1_phy: phy@1c0e000 { 2080 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 2081 reg = <0 0x01c0e000 0 0x2000>; 2082 2083 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2084 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2085 <&gcc GCC_PCIE_1_CLKREF_EN>, 2086 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2087 <&gcc GCC_PCIE_1_PIPE_CLK>; 2088 clock-names = "aux", 2089 "cfg_ahb", 2090 "ref", 2091 "rchng", 2092 "pipe"; 2093 2094 clock-output-names = "pcie_1_pipe_clk"; 2095 #clock-cells = <1>; 2096 2097 #phy-cells = <0>; 2098 2099 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2100 reset-names = "phy"; 2101 2102 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2103 assigned-clock-rates = <100000000>; 2104 2105 status = "disabled"; 2106 }; 2107 2108 config_noc: interconnect@1500000 { 2109 compatible = "qcom,sm8450-config-noc"; 2110 reg = <0 0x01500000 0 0x1c000>; 2111 #interconnect-cells = <2>; 2112 qcom,bcm-voters = <&apps_bcm_voter>; 2113 }; 2114 2115 system_noc: interconnect@1680000 { 2116 compatible = "qcom,sm8450-system-noc"; 2117 reg = <0 0x01680000 0 0x1e200>; 2118 #interconnect-cells = <2>; 2119 qcom,bcm-voters = <&apps_bcm_voter>; 2120 }; 2121 2122 pcie_noc: interconnect@16c0000 { 2123 compatible = "qcom,sm8450-pcie-anoc"; 2124 reg = <0 0x016c0000 0 0xe280>; 2125 #interconnect-cells = <2>; 2126 qcom,bcm-voters = <&apps_bcm_voter>; 2127 }; 2128 2129 aggre1_noc: interconnect@16e0000 { 2130 compatible = "qcom,sm8450-aggre1-noc"; 2131 reg = <0 0x016e0000 0 0x1c080>; 2132 #interconnect-cells = <2>; 2133 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2134 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2135 qcom,bcm-voters = <&apps_bcm_voter>; 2136 }; 2137 2138 aggre2_noc: interconnect@1700000 { 2139 compatible = "qcom,sm8450-aggre2-noc"; 2140 reg = <0 0x01700000 0 0x31080>; 2141 #interconnect-cells = <2>; 2142 qcom,bcm-voters = <&apps_bcm_voter>; 2143 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2144 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 2145 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2146 <&rpmhcc RPMH_IPA_CLK>; 2147 }; 2148 2149 mmss_noc: interconnect@1740000 { 2150 compatible = "qcom,sm8450-mmss-noc"; 2151 reg = <0 0x01740000 0 0x1f080>; 2152 #interconnect-cells = <2>; 2153 qcom,bcm-voters = <&apps_bcm_voter>; 2154 }; 2155 2156 tcsr_mutex: hwlock@1f40000 { 2157 compatible = "qcom,tcsr-mutex"; 2158 reg = <0x0 0x01f40000 0x0 0x40000>; 2159 #hwlock-cells = <1>; 2160 }; 2161 2162 tcsr: syscon@1fc0000 { 2163 compatible = "qcom,sm8450-tcsr", "syscon"; 2164 reg = <0x0 0x1fc0000 0x0 0x30000>; 2165 }; 2166 2167 gpu: gpu@3d00000 { 2168 compatible = "qcom,adreno-730.1", "qcom,adreno"; 2169 reg = <0x0 0x03d00000 0x0 0x40000>, 2170 <0x0 0x03d9e000 0x0 0x1000>, 2171 <0x0 0x03d61000 0x0 0x800>; 2172 reg-names = "kgsl_3d0_reg_memory", 2173 "cx_mem", 2174 "cx_dbgc"; 2175 2176 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2177 2178 iommus = <&adreno_smmu 0 0x400>, 2179 <&adreno_smmu 1 0x400>; 2180 2181 operating-points-v2 = <&gpu_opp_table>; 2182 2183 qcom,gmu = <&gmu>; 2184 #cooling-cells = <2>; 2185 2186 status = "disabled"; 2187 2188 zap-shader { 2189 memory-region = <&gpu_micro_code_mem>; 2190 }; 2191 2192 gpu_opp_table: opp-table { 2193 compatible = "operating-points-v2"; 2194 2195 opp-818000000 { 2196 opp-hz = /bits/ 64 <818000000>; 2197 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2198 }; 2199 2200 opp-791000000 { 2201 opp-hz = /bits/ 64 <791000000>; 2202 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2203 }; 2204 2205 opp-734000000 { 2206 opp-hz = /bits/ 64 <734000000>; 2207 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2208 }; 2209 2210 opp-640000000 { 2211 opp-hz = /bits/ 64 <640000000>; 2212 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2213 }; 2214 2215 opp-599000000 { 2216 opp-hz = /bits/ 64 <599000000>; 2217 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2218 }; 2219 2220 opp-545000000 { 2221 opp-hz = /bits/ 64 <545000000>; 2222 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2223 }; 2224 2225 opp-492000000 { 2226 opp-hz = /bits/ 64 <492000000>; 2227 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2228 }; 2229 2230 opp-421000000 { 2231 opp-hz = /bits/ 64 <421000000>; 2232 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2233 }; 2234 2235 opp-350000000 { 2236 opp-hz = /bits/ 64 <350000000>; 2237 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2238 }; 2239 2240 opp-317000000 { 2241 opp-hz = /bits/ 64 <317000000>; 2242 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2243 }; 2244 2245 opp-285000000 { 2246 opp-hz = /bits/ 64 <285000000>; 2247 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2248 }; 2249 2250 opp-220000000 { 2251 opp-hz = /bits/ 64 <220000000>; 2252 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2253 }; 2254 }; 2255 }; 2256 2257 gmu: gmu@3d6a000 { 2258 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu"; 2259 reg = <0x0 0x03d6a000 0x0 0x35000>, 2260 <0x0 0x03d50000 0x0 0x10000>, 2261 <0x0 0x0b290000 0x0 0x10000>; 2262 reg-names = "gmu", "rscc", "gmu_pdc"; 2263 2264 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2265 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2266 interrupt-names = "hfi", "gmu"; 2267 2268 clocks = <&gpucc GPU_CC_AHB_CLK>, 2269 <&gpucc GPU_CC_CX_GMU_CLK>, 2270 <&gpucc GPU_CC_CXO_CLK>, 2271 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2272 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2273 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2274 <&gpucc GPU_CC_DEMET_CLK>; 2275 clock-names = "ahb", 2276 "gmu", 2277 "cxo", 2278 "axi", 2279 "memnoc", 2280 "hub", 2281 "demet"; 2282 2283 power-domains = <&gpucc GPU_CX_GDSC>, 2284 <&gpucc GPU_GX_GDSC>; 2285 power-domain-names = "cx", 2286 "gx"; 2287 2288 iommus = <&adreno_smmu 5 0x400>; 2289 2290 qcom,qmp = <&aoss_qmp>; 2291 2292 operating-points-v2 = <&gmu_opp_table>; 2293 2294 gmu_opp_table: opp-table { 2295 compatible = "operating-points-v2"; 2296 2297 opp-500000000 { 2298 opp-hz = /bits/ 64 <500000000>; 2299 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2300 }; 2301 2302 opp-200000000 { 2303 opp-hz = /bits/ 64 <200000000>; 2304 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2305 }; 2306 }; 2307 }; 2308 2309 gpucc: clock-controller@3d90000 { 2310 compatible = "qcom,sm8450-gpucc"; 2311 reg = <0x0 0x03d90000 0x0 0xa000>; 2312 clocks = <&rpmhcc RPMH_CXO_CLK>, 2313 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2314 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2315 #clock-cells = <1>; 2316 #reset-cells = <1>; 2317 #power-domain-cells = <1>; 2318 }; 2319 2320 adreno_smmu: iommu@3da0000 { 2321 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu", 2322 "qcom,smmu-500", "arm,mmu-500"; 2323 reg = <0x0 0x03da0000 0x0 0x40000>; 2324 #iommu-cells = <2>; 2325 #global-interrupts = <1>; 2326 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2327 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2328 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2329 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2330 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2331 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2332 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2333 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2334 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2335 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2336 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2338 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2339 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2340 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2341 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2342 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2343 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2344 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2345 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2346 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2347 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2348 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2349 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2350 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, 2351 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 2352 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2353 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2354 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2355 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2356 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2357 <&gpucc GPU_CC_AHB_CLK>; 2358 clock-names = "gmu", 2359 "hub", 2360 "hlos", 2361 "bus", 2362 "iface", 2363 "ahb"; 2364 power-domains = <&gpucc GPU_CX_GDSC>; 2365 dma-coherent; 2366 }; 2367 2368 usb_1_hsphy: phy@88e3000 { 2369 compatible = "qcom,sm8450-usb-hs-phy", 2370 "qcom,usb-snps-hs-7nm-phy"; 2371 reg = <0 0x088e3000 0 0x400>; 2372 status = "disabled"; 2373 #phy-cells = <0>; 2374 2375 clocks = <&rpmhcc RPMH_CXO_CLK>; 2376 clock-names = "ref"; 2377 2378 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2379 }; 2380 2381 usb_1_qmpphy: phy@88e8000 { 2382 compatible = "qcom,sm8450-qmp-usb3-dp-phy"; 2383 reg = <0 0x088e8000 0 0x3000>; 2384 2385 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2386 <&rpmhcc RPMH_CXO_CLK>, 2387 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2388 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2389 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2390 2391 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2392 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2393 reset-names = "phy", "common"; 2394 2395 #clock-cells = <1>; 2396 #phy-cells = <1>; 2397 2398 orientation-switch; 2399 2400 status = "disabled"; 2401 2402 ports { 2403 #address-cells = <1>; 2404 #size-cells = <0>; 2405 2406 port@0 { 2407 reg = <0>; 2408 2409 usb_1_qmpphy_out: endpoint { 2410 }; 2411 }; 2412 2413 port@1 { 2414 reg = <1>; 2415 2416 usb_1_qmpphy_usb_ss_in: endpoint { 2417 remote-endpoint = <&usb_1_dwc3_ss>; 2418 }; 2419 }; 2420 2421 port@2 { 2422 reg = <2>; 2423 2424 usb_1_qmpphy_dp_in: endpoint { 2425 remote-endpoint = <&mdss_dp0_out>; 2426 }; 2427 }; 2428 }; 2429 }; 2430 2431 remoteproc_slpi: remoteproc@2400000 { 2432 compatible = "qcom,sm8450-slpi-pas"; 2433 reg = <0 0x02400000 0 0x4000>; 2434 2435 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2436 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2437 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2438 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2439 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2440 interrupt-names = "wdog", "fatal", "ready", 2441 "handover", "stop-ack"; 2442 2443 clocks = <&rpmhcc RPMH_CXO_CLK>; 2444 clock-names = "xo"; 2445 2446 power-domains = <&rpmhpd RPMHPD_LCX>, 2447 <&rpmhpd RPMHPD_LMX>; 2448 power-domain-names = "lcx", "lmx"; 2449 2450 memory-region = <&slpi_mem>; 2451 2452 qcom,qmp = <&aoss_qmp>; 2453 2454 qcom,smem-states = <&smp2p_slpi_out 0>; 2455 qcom,smem-state-names = "stop"; 2456 2457 status = "disabled"; 2458 2459 glink-edge { 2460 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2461 IPCC_MPROC_SIGNAL_GLINK_QMP 2462 IRQ_TYPE_EDGE_RISING>; 2463 mboxes = <&ipcc IPCC_CLIENT_SLPI 2464 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2465 2466 label = "slpi"; 2467 qcom,remote-pid = <3>; 2468 2469 fastrpc { 2470 compatible = "qcom,fastrpc"; 2471 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2472 label = "sdsp"; 2473 qcom,non-secure-domain; 2474 #address-cells = <1>; 2475 #size-cells = <0>; 2476 2477 compute-cb@1 { 2478 compatible = "qcom,fastrpc-compute-cb"; 2479 reg = <1>; 2480 iommus = <&apps_smmu 0x0541 0x0>; 2481 }; 2482 2483 compute-cb@2 { 2484 compatible = "qcom,fastrpc-compute-cb"; 2485 reg = <2>; 2486 iommus = <&apps_smmu 0x0542 0x0>; 2487 }; 2488 2489 compute-cb@3 { 2490 compatible = "qcom,fastrpc-compute-cb"; 2491 reg = <3>; 2492 iommus = <&apps_smmu 0x0543 0x0>; 2493 /* note: shared-cb = <4> in downstream */ 2494 }; 2495 }; 2496 }; 2497 }; 2498 2499 wsa2macro: codec@31e0000 { 2500 compatible = "qcom,sm8450-lpass-wsa-macro"; 2501 reg = <0 0x031e0000 0 0x1000>; 2502 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2503 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2504 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2505 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2506 <&vamacro>; 2507 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2508 2509 #clock-cells = <0>; 2510 clock-output-names = "wsa2-mclk"; 2511 #sound-dai-cells = <1>; 2512 }; 2513 2514 swr4: soundwire@31f0000 { 2515 compatible = "qcom,soundwire-v1.7.0"; 2516 reg = <0 0x031f0000 0 0x2000>; 2517 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2518 clocks = <&wsa2macro>; 2519 clock-names = "iface"; 2520 label = "WSA2"; 2521 2522 pinctrl-0 = <&wsa2_swr_active>; 2523 pinctrl-names = "default"; 2524 2525 qcom,din-ports = <2>; 2526 qcom,dout-ports = <6>; 2527 2528 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2529 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2530 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2531 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2532 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2533 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2534 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2535 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2536 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2537 2538 #address-cells = <2>; 2539 #size-cells = <0>; 2540 #sound-dai-cells = <1>; 2541 status = "disabled"; 2542 }; 2543 2544 rxmacro: codec@3200000 { 2545 compatible = "qcom,sm8450-lpass-rx-macro"; 2546 reg = <0 0x03200000 0 0x1000>; 2547 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2548 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2549 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2550 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2551 <&vamacro>; 2552 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2553 2554 #clock-cells = <0>; 2555 clock-output-names = "mclk"; 2556 #sound-dai-cells = <1>; 2557 }; 2558 2559 swr1: soundwire@3210000 { 2560 compatible = "qcom,soundwire-v1.7.0"; 2561 reg = <0 0x03210000 0 0x2000>; 2562 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2563 clocks = <&rxmacro>; 2564 clock-names = "iface"; 2565 label = "RX"; 2566 qcom,din-ports = <0>; 2567 qcom,dout-ports = <5>; 2568 2569 pinctrl-0 = <&rx_swr_active>; 2570 pinctrl-names = "default"; 2571 2572 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2573 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2574 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2575 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2576 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2577 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2578 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2579 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2580 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2581 2582 #address-cells = <2>; 2583 #size-cells = <0>; 2584 #sound-dai-cells = <1>; 2585 status = "disabled"; 2586 }; 2587 2588 txmacro: codec@3220000 { 2589 compatible = "qcom,sm8450-lpass-tx-macro"; 2590 reg = <0 0x03220000 0 0x1000>; 2591 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2592 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2593 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2594 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2595 <&vamacro>; 2596 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2597 2598 #clock-cells = <0>; 2599 clock-output-names = "mclk"; 2600 #sound-dai-cells = <1>; 2601 }; 2602 2603 wsamacro: codec@3240000 { 2604 compatible = "qcom,sm8450-lpass-wsa-macro"; 2605 reg = <0 0x03240000 0 0x1000>; 2606 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2607 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2608 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2609 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2610 <&vamacro>; 2611 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2612 2613 #clock-cells = <0>; 2614 clock-output-names = "mclk"; 2615 #sound-dai-cells = <1>; 2616 }; 2617 2618 swr0: soundwire@3250000 { 2619 compatible = "qcom,soundwire-v1.7.0"; 2620 reg = <0 0x03250000 0 0x2000>; 2621 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2622 clocks = <&wsamacro>; 2623 clock-names = "iface"; 2624 label = "WSA"; 2625 2626 pinctrl-0 = <&wsa_swr_active>; 2627 pinctrl-names = "default"; 2628 2629 qcom,din-ports = <2>; 2630 qcom,dout-ports = <6>; 2631 2632 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2633 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2634 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2635 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2636 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2637 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2638 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2639 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2640 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2641 2642 #address-cells = <2>; 2643 #size-cells = <0>; 2644 #sound-dai-cells = <1>; 2645 status = "disabled"; 2646 }; 2647 2648 swr2: soundwire@33b0000 { 2649 compatible = "qcom,soundwire-v1.7.0"; 2650 reg = <0 0x033b0000 0 0x2000>; 2651 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2652 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2653 interrupt-names = "core", "wakeup"; 2654 2655 clocks = <&txmacro>; 2656 clock-names = "iface"; 2657 label = "TX"; 2658 2659 pinctrl-0 = <&tx_swr_active>; 2660 pinctrl-names = "default"; 2661 2662 qcom,din-ports = <4>; 2663 qcom,dout-ports = <0>; 2664 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2665 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2666 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2667 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2668 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2669 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2670 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2671 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2672 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2673 2674 #address-cells = <2>; 2675 #size-cells = <0>; 2676 #sound-dai-cells = <1>; 2677 status = "disabled"; 2678 }; 2679 2680 vamacro: codec@33f0000 { 2681 compatible = "qcom,sm8450-lpass-va-macro"; 2682 reg = <0 0x033f0000 0 0x1000>; 2683 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2684 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2685 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2686 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2687 clock-names = "mclk", "macro", "dcodec", "npl"; 2688 2689 #clock-cells = <0>; 2690 clock-output-names = "fsgen"; 2691 #sound-dai-cells = <1>; 2692 status = "disabled"; 2693 }; 2694 2695 remoteproc_adsp: remoteproc@30000000 { 2696 compatible = "qcom,sm8450-adsp-pas"; 2697 reg = <0 0x30000000 0 0x100>; 2698 2699 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2700 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2701 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2702 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2703 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2704 interrupt-names = "wdog", "fatal", "ready", 2705 "handover", "stop-ack"; 2706 2707 clocks = <&rpmhcc RPMH_CXO_CLK>; 2708 clock-names = "xo"; 2709 2710 power-domains = <&rpmhpd RPMHPD_LCX>, 2711 <&rpmhpd RPMHPD_LMX>; 2712 power-domain-names = "lcx", "lmx"; 2713 2714 memory-region = <&adsp_mem>; 2715 2716 qcom,qmp = <&aoss_qmp>; 2717 2718 qcom,smem-states = <&smp2p_adsp_out 0>; 2719 qcom,smem-state-names = "stop"; 2720 2721 status = "disabled"; 2722 2723 remoteproc_adsp_glink: glink-edge { 2724 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2725 IPCC_MPROC_SIGNAL_GLINK_QMP 2726 IRQ_TYPE_EDGE_RISING>; 2727 mboxes = <&ipcc IPCC_CLIENT_LPASS 2728 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2729 2730 label = "lpass"; 2731 qcom,remote-pid = <2>; 2732 2733 gpr { 2734 compatible = "qcom,gpr"; 2735 qcom,glink-channels = "adsp_apps"; 2736 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2737 qcom,intents = <512 20>; 2738 #address-cells = <1>; 2739 #size-cells = <0>; 2740 2741 q6apm: service@1 { 2742 compatible = "qcom,q6apm"; 2743 reg = <GPR_APM_MODULE_IID>; 2744 #sound-dai-cells = <0>; 2745 qcom,protection-domain = "avs/audio", 2746 "msm/adsp/audio_pd"; 2747 2748 q6apmdai: dais { 2749 compatible = "qcom,q6apm-dais"; 2750 iommus = <&apps_smmu 0x1801 0x0>; 2751 }; 2752 2753 q6apmbedai: bedais { 2754 compatible = "qcom,q6apm-lpass-dais"; 2755 #sound-dai-cells = <1>; 2756 }; 2757 }; 2758 2759 q6prm: service@2 { 2760 compatible = "qcom,q6prm"; 2761 reg = <GPR_PRM_MODULE_IID>; 2762 qcom,protection-domain = "avs/audio", 2763 "msm/adsp/audio_pd"; 2764 2765 q6prmcc: clock-controller { 2766 compatible = "qcom,q6prm-lpass-clocks"; 2767 #clock-cells = <2>; 2768 }; 2769 }; 2770 }; 2771 2772 fastrpc { 2773 compatible = "qcom,fastrpc"; 2774 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2775 label = "adsp"; 2776 qcom,non-secure-domain; 2777 #address-cells = <1>; 2778 #size-cells = <0>; 2779 2780 compute-cb@3 { 2781 compatible = "qcom,fastrpc-compute-cb"; 2782 reg = <3>; 2783 iommus = <&apps_smmu 0x1803 0x0>; 2784 }; 2785 2786 compute-cb@4 { 2787 compatible = "qcom,fastrpc-compute-cb"; 2788 reg = <4>; 2789 iommus = <&apps_smmu 0x1804 0x0>; 2790 }; 2791 2792 compute-cb@5 { 2793 compatible = "qcom,fastrpc-compute-cb"; 2794 reg = <5>; 2795 iommus = <&apps_smmu 0x1805 0x0>; 2796 }; 2797 }; 2798 }; 2799 }; 2800 2801 remoteproc_cdsp: remoteproc@32300000 { 2802 compatible = "qcom,sm8450-cdsp-pas"; 2803 reg = <0 0x32300000 0 0x1400000>; 2804 2805 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2806 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2807 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2808 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2809 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2810 interrupt-names = "wdog", "fatal", "ready", 2811 "handover", "stop-ack"; 2812 2813 clocks = <&rpmhcc RPMH_CXO_CLK>; 2814 clock-names = "xo"; 2815 2816 power-domains = <&rpmhpd RPMHPD_CX>, 2817 <&rpmhpd RPMHPD_MXC>; 2818 power-domain-names = "cx", "mxc"; 2819 2820 memory-region = <&cdsp_mem>; 2821 2822 qcom,qmp = <&aoss_qmp>; 2823 2824 qcom,smem-states = <&smp2p_cdsp_out 0>; 2825 qcom,smem-state-names = "stop"; 2826 2827 status = "disabled"; 2828 2829 glink-edge { 2830 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2831 IPCC_MPROC_SIGNAL_GLINK_QMP 2832 IRQ_TYPE_EDGE_RISING>; 2833 mboxes = <&ipcc IPCC_CLIENT_CDSP 2834 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2835 2836 label = "cdsp"; 2837 qcom,remote-pid = <5>; 2838 2839 fastrpc { 2840 compatible = "qcom,fastrpc"; 2841 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2842 label = "cdsp"; 2843 qcom,non-secure-domain; 2844 #address-cells = <1>; 2845 #size-cells = <0>; 2846 2847 compute-cb@1 { 2848 compatible = "qcom,fastrpc-compute-cb"; 2849 reg = <1>; 2850 iommus = <&apps_smmu 0x2161 0x0400>, 2851 <&apps_smmu 0x1021 0x1420>; 2852 }; 2853 2854 compute-cb@2 { 2855 compatible = "qcom,fastrpc-compute-cb"; 2856 reg = <2>; 2857 iommus = <&apps_smmu 0x2162 0x0400>, 2858 <&apps_smmu 0x1022 0x1420>; 2859 }; 2860 2861 compute-cb@3 { 2862 compatible = "qcom,fastrpc-compute-cb"; 2863 reg = <3>; 2864 iommus = <&apps_smmu 0x2163 0x0400>, 2865 <&apps_smmu 0x1023 0x1420>; 2866 }; 2867 2868 compute-cb@4 { 2869 compatible = "qcom,fastrpc-compute-cb"; 2870 reg = <4>; 2871 iommus = <&apps_smmu 0x2164 0x0400>, 2872 <&apps_smmu 0x1024 0x1420>; 2873 }; 2874 2875 compute-cb@5 { 2876 compatible = "qcom,fastrpc-compute-cb"; 2877 reg = <5>; 2878 iommus = <&apps_smmu 0x2165 0x0400>, 2879 <&apps_smmu 0x1025 0x1420>; 2880 }; 2881 2882 compute-cb@6 { 2883 compatible = "qcom,fastrpc-compute-cb"; 2884 reg = <6>; 2885 iommus = <&apps_smmu 0x2166 0x0400>, 2886 <&apps_smmu 0x1026 0x1420>; 2887 }; 2888 2889 compute-cb@7 { 2890 compatible = "qcom,fastrpc-compute-cb"; 2891 reg = <7>; 2892 iommus = <&apps_smmu 0x2167 0x0400>, 2893 <&apps_smmu 0x1027 0x1420>; 2894 }; 2895 2896 compute-cb@8 { 2897 compatible = "qcom,fastrpc-compute-cb"; 2898 reg = <8>; 2899 iommus = <&apps_smmu 0x2168 0x0400>, 2900 <&apps_smmu 0x1028 0x1420>; 2901 }; 2902 2903 /* note: secure cb9 in downstream */ 2904 }; 2905 }; 2906 }; 2907 2908 remoteproc_mpss: remoteproc@4080000 { 2909 compatible = "qcom,sm8450-mpss-pas"; 2910 reg = <0x0 0x04080000 0x0 0x4040>; 2911 2912 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2913 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2914 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2915 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2916 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2917 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2918 interrupt-names = "wdog", "fatal", "ready", "handover", 2919 "stop-ack", "shutdown-ack"; 2920 2921 clocks = <&rpmhcc RPMH_CXO_CLK>; 2922 clock-names = "xo"; 2923 2924 power-domains = <&rpmhpd RPMHPD_CX>, 2925 <&rpmhpd RPMHPD_MSS>; 2926 power-domain-names = "cx", "mss"; 2927 2928 memory-region = <&mpss_mem>; 2929 2930 qcom,qmp = <&aoss_qmp>; 2931 2932 qcom,smem-states = <&smp2p_modem_out 0>; 2933 qcom,smem-state-names = "stop"; 2934 2935 status = "disabled"; 2936 2937 glink-edge { 2938 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2939 IPCC_MPROC_SIGNAL_GLINK_QMP 2940 IRQ_TYPE_EDGE_RISING>; 2941 mboxes = <&ipcc IPCC_CLIENT_MPSS 2942 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2943 label = "modem"; 2944 qcom,remote-pid = <1>; 2945 }; 2946 }; 2947 2948 videocc: clock-controller@aaf0000 { 2949 compatible = "qcom,sm8450-videocc"; 2950 reg = <0 0x0aaf0000 0 0x10000>; 2951 clocks = <&rpmhcc RPMH_CXO_CLK>, 2952 <&gcc GCC_VIDEO_AHB_CLK>; 2953 power-domains = <&rpmhpd RPMHPD_MMCX>; 2954 required-opps = <&rpmhpd_opp_low_svs>; 2955 #clock-cells = <1>; 2956 #reset-cells = <1>; 2957 #power-domain-cells = <1>; 2958 }; 2959 2960 cci0: cci@ac15000 { 2961 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2962 reg = <0 0x0ac15000 0 0x1000>; 2963 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 2964 power-domains = <&camcc TITAN_TOP_GDSC>; 2965 2966 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2967 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2968 <&camcc CAM_CC_CPAS_AHB_CLK>, 2969 <&camcc CAM_CC_CCI_0_CLK>, 2970 <&camcc CAM_CC_CCI_0_CLK_SRC>; 2971 clock-names = "camnoc_axi", 2972 "slow_ahb_src", 2973 "cpas_ahb", 2974 "cci", 2975 "cci_src"; 2976 pinctrl-0 = <&cci0_default &cci1_default>; 2977 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2978 pinctrl-names = "default", "sleep"; 2979 2980 status = "disabled"; 2981 #address-cells = <1>; 2982 #size-cells = <0>; 2983 2984 cci0_i2c0: i2c-bus@0 { 2985 reg = <0>; 2986 clock-frequency = <1000000>; 2987 #address-cells = <1>; 2988 #size-cells = <0>; 2989 }; 2990 2991 cci0_i2c1: i2c-bus@1 { 2992 reg = <1>; 2993 clock-frequency = <1000000>; 2994 #address-cells = <1>; 2995 #size-cells = <0>; 2996 }; 2997 }; 2998 2999 cci1: cci@ac16000 { 3000 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 3001 reg = <0 0x0ac16000 0 0x1000>; 3002 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3003 power-domains = <&camcc TITAN_TOP_GDSC>; 3004 3005 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3006 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3007 <&camcc CAM_CC_CPAS_AHB_CLK>, 3008 <&camcc CAM_CC_CCI_1_CLK>, 3009 <&camcc CAM_CC_CCI_1_CLK_SRC>; 3010 clock-names = "camnoc_axi", 3011 "slow_ahb_src", 3012 "cpas_ahb", 3013 "cci", 3014 "cci_src"; 3015 pinctrl-0 = <&cci2_default &cci3_default>; 3016 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 3017 pinctrl-names = "default", "sleep"; 3018 3019 status = "disabled"; 3020 #address-cells = <1>; 3021 #size-cells = <0>; 3022 3023 cci1_i2c0: i2c-bus@0 { 3024 reg = <0>; 3025 clock-frequency = <1000000>; 3026 #address-cells = <1>; 3027 #size-cells = <0>; 3028 }; 3029 3030 cci1_i2c1: i2c-bus@1 { 3031 reg = <1>; 3032 clock-frequency = <1000000>; 3033 #address-cells = <1>; 3034 #size-cells = <0>; 3035 }; 3036 }; 3037 3038 camcc: clock-controller@ade0000 { 3039 compatible = "qcom,sm8450-camcc"; 3040 reg = <0 0x0ade0000 0 0x20000>; 3041 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3042 <&rpmhcc RPMH_CXO_CLK>, 3043 <&rpmhcc RPMH_CXO_CLK_A>, 3044 <&sleep_clk>; 3045 power-domains = <&rpmhpd RPMHPD_MMCX>; 3046 required-opps = <&rpmhpd_opp_low_svs>; 3047 #clock-cells = <1>; 3048 #reset-cells = <1>; 3049 #power-domain-cells = <1>; 3050 status = "disabled"; 3051 }; 3052 3053 mdss: display-subsystem@ae00000 { 3054 compatible = "qcom,sm8450-mdss"; 3055 reg = <0 0x0ae00000 0 0x1000>; 3056 reg-names = "mdss"; 3057 3058 /* same path used twice */ 3059 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 3060 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 3061 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3062 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3063 interconnect-names = "mdp0-mem", 3064 "mdp1-mem", 3065 "cpu-cfg"; 3066 3067 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3068 3069 power-domains = <&dispcc MDSS_GDSC>; 3070 3071 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3072 <&gcc GCC_DISP_HF_AXI_CLK>, 3073 <&gcc GCC_DISP_SF_AXI_CLK>, 3074 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3075 3076 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3077 interrupt-controller; 3078 #interrupt-cells = <1>; 3079 3080 iommus = <&apps_smmu 0x2800 0x402>; 3081 3082 #address-cells = <2>; 3083 #size-cells = <2>; 3084 ranges; 3085 3086 status = "disabled"; 3087 3088 mdss_mdp: display-controller@ae01000 { 3089 compatible = "qcom,sm8450-dpu"; 3090 reg = <0 0x0ae01000 0 0x8f000>, 3091 <0 0x0aeb0000 0 0x2008>; 3092 reg-names = "mdp", "vbif"; 3093 3094 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3095 <&gcc GCC_DISP_SF_AXI_CLK>, 3096 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3097 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3098 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3099 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3100 clock-names = "bus", 3101 "nrt_bus", 3102 "iface", 3103 "lut", 3104 "core", 3105 "vsync"; 3106 3107 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3108 assigned-clock-rates = <19200000>; 3109 3110 operating-points-v2 = <&mdp_opp_table>; 3111 power-domains = <&rpmhpd RPMHPD_MMCX>; 3112 3113 interrupt-parent = <&mdss>; 3114 interrupts = <0>; 3115 3116 ports { 3117 #address-cells = <1>; 3118 #size-cells = <0>; 3119 3120 port@0 { 3121 reg = <0>; 3122 dpu_intf1_out: endpoint { 3123 remote-endpoint = <&mdss_dsi0_in>; 3124 }; 3125 }; 3126 3127 port@1 { 3128 reg = <1>; 3129 dpu_intf2_out: endpoint { 3130 remote-endpoint = <&mdss_dsi1_in>; 3131 }; 3132 }; 3133 3134 port@2 { 3135 reg = <2>; 3136 dpu_intf0_out: endpoint { 3137 remote-endpoint = <&mdss_dp0_in>; 3138 }; 3139 }; 3140 }; 3141 3142 mdp_opp_table: opp-table { 3143 compatible = "operating-points-v2"; 3144 3145 opp-172000000 { 3146 opp-hz = /bits/ 64 <172000000>; 3147 required-opps = <&rpmhpd_opp_low_svs_d1>; 3148 }; 3149 3150 opp-200000000 { 3151 opp-hz = /bits/ 64 <200000000>; 3152 required-opps = <&rpmhpd_opp_low_svs>; 3153 }; 3154 3155 opp-325000000 { 3156 opp-hz = /bits/ 64 <325000000>; 3157 required-opps = <&rpmhpd_opp_svs>; 3158 }; 3159 3160 opp-375000000 { 3161 opp-hz = /bits/ 64 <375000000>; 3162 required-opps = <&rpmhpd_opp_svs_l1>; 3163 }; 3164 3165 opp-500000000 { 3166 opp-hz = /bits/ 64 <500000000>; 3167 required-opps = <&rpmhpd_opp_nom>; 3168 }; 3169 }; 3170 }; 3171 3172 mdss_dp0: displayport-controller@ae90000 { 3173 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; 3174 reg = <0 0xae90000 0 0x200>, 3175 <0 0xae90200 0 0x200>, 3176 <0 0xae90400 0 0xc00>, 3177 <0 0xae91000 0 0x400>, 3178 <0 0xae91400 0 0x400>; 3179 interrupt-parent = <&mdss>; 3180 interrupts = <12>; 3181 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3182 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3183 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3184 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3185 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3186 clock-names = "core_iface", 3187 "core_aux", 3188 "ctrl_link", 3189 "ctrl_link_iface", 3190 "stream_pixel"; 3191 3192 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3193 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3194 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3195 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3196 3197 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3198 phy-names = "dp"; 3199 3200 #sound-dai-cells = <0>; 3201 3202 operating-points-v2 = <&dp_opp_table>; 3203 power-domains = <&rpmhpd RPMHPD_MMCX>; 3204 3205 status = "disabled"; 3206 3207 ports { 3208 #address-cells = <1>; 3209 #size-cells = <0>; 3210 3211 port@0 { 3212 reg = <0>; 3213 mdss_dp0_in: endpoint { 3214 remote-endpoint = <&dpu_intf0_out>; 3215 }; 3216 }; 3217 3218 port@1 { 3219 reg = <1>; 3220 3221 mdss_dp0_out: endpoint { 3222 remote-endpoint = <&usb_1_qmpphy_dp_in>; 3223 }; 3224 }; 3225 }; 3226 3227 dp_opp_table: opp-table { 3228 compatible = "operating-points-v2"; 3229 3230 opp-160000000 { 3231 opp-hz = /bits/ 64 <160000000>; 3232 required-opps = <&rpmhpd_opp_low_svs>; 3233 }; 3234 3235 opp-270000000 { 3236 opp-hz = /bits/ 64 <270000000>; 3237 required-opps = <&rpmhpd_opp_svs>; 3238 }; 3239 3240 opp-540000000 { 3241 opp-hz = /bits/ 64 <540000000>; 3242 required-opps = <&rpmhpd_opp_svs_l1>; 3243 }; 3244 3245 opp-810000000 { 3246 opp-hz = /bits/ 64 <810000000>; 3247 required-opps = <&rpmhpd_opp_nom>; 3248 }; 3249 }; 3250 }; 3251 3252 mdss_dsi0: dsi@ae94000 { 3253 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3254 reg = <0 0x0ae94000 0 0x400>; 3255 reg-names = "dsi_ctrl"; 3256 3257 interrupt-parent = <&mdss>; 3258 interrupts = <4>; 3259 3260 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3261 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3262 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3263 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3264 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3265 <&gcc GCC_DISP_HF_AXI_CLK>; 3266 clock-names = "byte", 3267 "byte_intf", 3268 "pixel", 3269 "core", 3270 "iface", 3271 "bus"; 3272 3273 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3274 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 3275 3276 operating-points-v2 = <&mdss_dsi_opp_table>; 3277 power-domains = <&rpmhpd RPMHPD_MMCX>; 3278 3279 phys = <&mdss_dsi0_phy>; 3280 phy-names = "dsi"; 3281 3282 #address-cells = <1>; 3283 #size-cells = <0>; 3284 3285 status = "disabled"; 3286 3287 ports { 3288 #address-cells = <1>; 3289 #size-cells = <0>; 3290 3291 port@0 { 3292 reg = <0>; 3293 mdss_dsi0_in: endpoint { 3294 remote-endpoint = <&dpu_intf1_out>; 3295 }; 3296 }; 3297 3298 port@1 { 3299 reg = <1>; 3300 mdss_dsi0_out: endpoint { 3301 }; 3302 }; 3303 }; 3304 3305 mdss_dsi_opp_table: opp-table { 3306 compatible = "operating-points-v2"; 3307 3308 opp-187500000 { 3309 opp-hz = /bits/ 64 <187500000>; 3310 required-opps = <&rpmhpd_opp_low_svs>; 3311 }; 3312 3313 opp-300000000 { 3314 opp-hz = /bits/ 64 <300000000>; 3315 required-opps = <&rpmhpd_opp_svs>; 3316 }; 3317 3318 opp-358000000 { 3319 opp-hz = /bits/ 64 <358000000>; 3320 required-opps = <&rpmhpd_opp_svs_l1>; 3321 }; 3322 }; 3323 }; 3324 3325 mdss_dsi0_phy: phy@ae94400 { 3326 compatible = "qcom,sm8450-dsi-phy-5nm"; 3327 reg = <0 0x0ae94400 0 0x200>, 3328 <0 0x0ae94600 0 0x280>, 3329 <0 0x0ae94900 0 0x260>; 3330 reg-names = "dsi_phy", 3331 "dsi_phy_lane", 3332 "dsi_pll"; 3333 3334 #clock-cells = <1>; 3335 #phy-cells = <0>; 3336 3337 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3338 <&rpmhcc RPMH_CXO_CLK>; 3339 clock-names = "iface", "ref"; 3340 3341 status = "disabled"; 3342 }; 3343 3344 mdss_dsi1: dsi@ae96000 { 3345 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3346 reg = <0 0x0ae96000 0 0x400>; 3347 reg-names = "dsi_ctrl"; 3348 3349 interrupt-parent = <&mdss>; 3350 interrupts = <5>; 3351 3352 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3353 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3354 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3355 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3356 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3357 <&gcc GCC_DISP_HF_AXI_CLK>; 3358 clock-names = "byte", 3359 "byte_intf", 3360 "pixel", 3361 "core", 3362 "iface", 3363 "bus"; 3364 3365 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3366 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 3367 3368 operating-points-v2 = <&mdss_dsi_opp_table>; 3369 power-domains = <&rpmhpd RPMHPD_MMCX>; 3370 3371 phys = <&mdss_dsi1_phy>; 3372 phy-names = "dsi"; 3373 3374 #address-cells = <1>; 3375 #size-cells = <0>; 3376 3377 status = "disabled"; 3378 3379 ports { 3380 #address-cells = <1>; 3381 #size-cells = <0>; 3382 3383 port@0 { 3384 reg = <0>; 3385 mdss_dsi1_in: endpoint { 3386 remote-endpoint = <&dpu_intf2_out>; 3387 }; 3388 }; 3389 3390 port@1 { 3391 reg = <1>; 3392 mdss_dsi1_out: endpoint { 3393 }; 3394 }; 3395 }; 3396 }; 3397 3398 mdss_dsi1_phy: phy@ae96400 { 3399 compatible = "qcom,sm8450-dsi-phy-5nm"; 3400 reg = <0 0x0ae96400 0 0x200>, 3401 <0 0x0ae96600 0 0x280>, 3402 <0 0x0ae96900 0 0x260>; 3403 reg-names = "dsi_phy", 3404 "dsi_phy_lane", 3405 "dsi_pll"; 3406 3407 #clock-cells = <1>; 3408 #phy-cells = <0>; 3409 3410 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3411 <&rpmhcc RPMH_CXO_CLK>; 3412 clock-names = "iface", "ref"; 3413 3414 status = "disabled"; 3415 }; 3416 }; 3417 3418 dispcc: clock-controller@af00000 { 3419 compatible = "qcom,sm8450-dispcc"; 3420 reg = <0 0x0af00000 0 0x20000>; 3421 clocks = <&rpmhcc RPMH_CXO_CLK>, 3422 <&rpmhcc RPMH_CXO_CLK_A>, 3423 <&gcc GCC_DISP_AHB_CLK>, 3424 <&sleep_clk>, 3425 <&mdss_dsi0_phy 0>, 3426 <&mdss_dsi0_phy 1>, 3427 <&mdss_dsi1_phy 0>, 3428 <&mdss_dsi1_phy 1>, 3429 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3430 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3431 <0>, /* dp1 */ 3432 <0>, 3433 <0>, /* dp2 */ 3434 <0>, 3435 <0>, /* dp3 */ 3436 <0>; 3437 power-domains = <&rpmhpd RPMHPD_MMCX>; 3438 required-opps = <&rpmhpd_opp_low_svs>; 3439 #clock-cells = <1>; 3440 #reset-cells = <1>; 3441 #power-domain-cells = <1>; 3442 }; 3443 3444 pdc: interrupt-controller@b220000 { 3445 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 3446 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3447 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 3448 <94 609 31>, <125 63 1>, <126 716 12>; 3449 #interrupt-cells = <2>; 3450 interrupt-parent = <&intc>; 3451 interrupt-controller; 3452 }; 3453 3454 tsens0: thermal-sensor@c263000 { 3455 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3456 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3457 <0 0x0c222000 0 0x1000>; /* SROT */ 3458 #qcom,sensors = <16>; 3459 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3460 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3461 interrupt-names = "uplow", "critical"; 3462 #thermal-sensor-cells = <1>; 3463 }; 3464 3465 tsens1: thermal-sensor@c265000 { 3466 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3467 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3468 <0 0x0c223000 0 0x1000>; /* SROT */ 3469 #qcom,sensors = <16>; 3470 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3472 interrupt-names = "uplow", "critical"; 3473 #thermal-sensor-cells = <1>; 3474 }; 3475 3476 aoss_qmp: power-management@c300000 { 3477 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3478 reg = <0 0x0c300000 0 0x400>; 3479 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3480 IRQ_TYPE_EDGE_RISING>; 3481 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3482 3483 #clock-cells = <0>; 3484 }; 3485 3486 sram@c3f0000 { 3487 compatible = "qcom,rpmh-stats"; 3488 reg = <0 0x0c3f0000 0 0x400>; 3489 }; 3490 3491 spmi_bus: spmi@c400000 { 3492 compatible = "qcom,spmi-pmic-arb"; 3493 reg = <0 0x0c400000 0 0x00003000>, 3494 <0 0x0c500000 0 0x00400000>, 3495 <0 0x0c440000 0 0x00080000>, 3496 <0 0x0c4c0000 0 0x00010000>, 3497 <0 0x0c42d000 0 0x00010000>; 3498 reg-names = "core", 3499 "chnls", 3500 "obsrvr", 3501 "intr", 3502 "cnfg"; 3503 interrupt-names = "periph_irq"; 3504 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3505 qcom,ee = <0>; 3506 qcom,channel = <0>; 3507 interrupt-controller; 3508 #interrupt-cells = <4>; 3509 #address-cells = <2>; 3510 #size-cells = <0>; 3511 }; 3512 3513 ipcc: mailbox@ed18000 { 3514 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3515 reg = <0 0x0ed18000 0 0x1000>; 3516 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3517 interrupt-controller; 3518 #interrupt-cells = <3>; 3519 #mbox-cells = <2>; 3520 }; 3521 3522 tlmm: pinctrl@f100000 { 3523 compatible = "qcom,sm8450-tlmm"; 3524 reg = <0 0x0f100000 0 0x300000>; 3525 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3526 gpio-controller; 3527 #gpio-cells = <2>; 3528 interrupt-controller; 3529 #interrupt-cells = <2>; 3530 gpio-ranges = <&tlmm 0 0 211>; 3531 wakeup-parent = <&pdc>; 3532 3533 sdc2_default_state: sdc2-default-state { 3534 clk-pins { 3535 pins = "sdc2_clk"; 3536 drive-strength = <16>; 3537 bias-disable; 3538 }; 3539 3540 cmd-pins { 3541 pins = "sdc2_cmd"; 3542 drive-strength = <16>; 3543 bias-pull-up; 3544 }; 3545 3546 data-pins { 3547 pins = "sdc2_data"; 3548 drive-strength = <16>; 3549 bias-pull-up; 3550 }; 3551 }; 3552 3553 sdc2_sleep_state: sdc2-sleep-state { 3554 clk-pins { 3555 pins = "sdc2_clk"; 3556 drive-strength = <2>; 3557 bias-disable; 3558 }; 3559 3560 cmd-pins { 3561 pins = "sdc2_cmd"; 3562 drive-strength = <2>; 3563 bias-pull-up; 3564 }; 3565 3566 data-pins { 3567 pins = "sdc2_data"; 3568 drive-strength = <2>; 3569 bias-pull-up; 3570 }; 3571 }; 3572 3573 cci0_default: cci0-default-state { 3574 /* SDA, SCL */ 3575 pins = "gpio110", "gpio111"; 3576 function = "cci_i2c"; 3577 drive-strength = <2>; 3578 bias-pull-up; 3579 }; 3580 3581 cci0_sleep: cci0-sleep-state { 3582 /* SDA, SCL */ 3583 pins = "gpio110", "gpio111"; 3584 function = "cci_i2c"; 3585 drive-strength = <2>; 3586 bias-pull-down; 3587 }; 3588 3589 cci1_default: cci1-default-state { 3590 /* SDA, SCL */ 3591 pins = "gpio112", "gpio113"; 3592 function = "cci_i2c"; 3593 drive-strength = <2>; 3594 bias-pull-up; 3595 }; 3596 3597 cci1_sleep: cci1-sleep-state { 3598 /* SDA, SCL */ 3599 pins = "gpio112", "gpio113"; 3600 function = "cci_i2c"; 3601 drive-strength = <2>; 3602 bias-pull-down; 3603 }; 3604 3605 cci2_default: cci2-default-state { 3606 /* SDA, SCL */ 3607 pins = "gpio114", "gpio115"; 3608 function = "cci_i2c"; 3609 drive-strength = <2>; 3610 bias-pull-up; 3611 }; 3612 3613 cci2_sleep: cci2-sleep-state { 3614 /* SDA, SCL */ 3615 pins = "gpio114", "gpio115"; 3616 function = "cci_i2c"; 3617 drive-strength = <2>; 3618 bias-pull-down; 3619 }; 3620 3621 cci3_default: cci3-default-state { 3622 /* SDA, SCL */ 3623 pins = "gpio208", "gpio209"; 3624 function = "cci_i2c"; 3625 drive-strength = <2>; 3626 bias-pull-up; 3627 }; 3628 3629 cci3_sleep: cci3-sleep-state { 3630 /* SDA, SCL */ 3631 pins = "gpio208", "gpio209"; 3632 function = "cci_i2c"; 3633 drive-strength = <2>; 3634 bias-pull-down; 3635 }; 3636 3637 pcie0_default_state: pcie0-default-state { 3638 perst-pins { 3639 pins = "gpio94"; 3640 function = "gpio"; 3641 drive-strength = <2>; 3642 bias-pull-down; 3643 }; 3644 3645 clkreq-pins { 3646 pins = "gpio95"; 3647 function = "pcie0_clkreqn"; 3648 drive-strength = <2>; 3649 bias-pull-up; 3650 }; 3651 3652 wake-pins { 3653 pins = "gpio96"; 3654 function = "gpio"; 3655 drive-strength = <2>; 3656 bias-pull-up; 3657 }; 3658 }; 3659 3660 pcie1_default_state: pcie1-default-state { 3661 perst-pins { 3662 pins = "gpio97"; 3663 function = "gpio"; 3664 drive-strength = <2>; 3665 bias-pull-down; 3666 }; 3667 3668 clkreq-pins { 3669 pins = "gpio98"; 3670 function = "pcie1_clkreqn"; 3671 drive-strength = <2>; 3672 bias-pull-up; 3673 }; 3674 3675 wake-pins { 3676 pins = "gpio99"; 3677 function = "gpio"; 3678 drive-strength = <2>; 3679 bias-pull-up; 3680 }; 3681 }; 3682 3683 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3684 pins = "gpio0", "gpio1"; 3685 function = "qup0"; 3686 }; 3687 3688 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3689 pins = "gpio4", "gpio5"; 3690 function = "qup1"; 3691 }; 3692 3693 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3694 pins = "gpio8", "gpio9"; 3695 function = "qup2"; 3696 }; 3697 3698 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3699 pins = "gpio12", "gpio13"; 3700 function = "qup3"; 3701 }; 3702 3703 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3704 pins = "gpio16", "gpio17"; 3705 function = "qup4"; 3706 }; 3707 3708 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3709 pins = "gpio206", "gpio207"; 3710 function = "qup5"; 3711 }; 3712 3713 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3714 pins = "gpio20", "gpio21"; 3715 function = "qup6"; 3716 }; 3717 3718 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3719 pins = "gpio28", "gpio29"; 3720 function = "qup8"; 3721 }; 3722 3723 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3724 pins = "gpio32", "gpio33"; 3725 function = "qup9"; 3726 }; 3727 3728 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3729 pins = "gpio36", "gpio37"; 3730 function = "qup10"; 3731 }; 3732 3733 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3734 pins = "gpio40", "gpio41"; 3735 function = "qup11"; 3736 }; 3737 3738 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3739 pins = "gpio44", "gpio45"; 3740 function = "qup12"; 3741 }; 3742 3743 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3744 pins = "gpio48", "gpio49"; 3745 function = "qup13"; 3746 drive-strength = <2>; 3747 bias-pull-up; 3748 }; 3749 3750 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3751 pins = "gpio52", "gpio53"; 3752 function = "qup14"; 3753 drive-strength = <2>; 3754 bias-pull-up; 3755 }; 3756 3757 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3758 pins = "gpio56", "gpio57"; 3759 function = "qup15"; 3760 }; 3761 3762 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 3763 pins = "gpio60", "gpio61"; 3764 function = "qup16"; 3765 }; 3766 3767 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 3768 pins = "gpio64", "gpio65"; 3769 function = "qup17"; 3770 }; 3771 3772 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 3773 pins = "gpio68", "gpio69"; 3774 function = "qup18"; 3775 }; 3776 3777 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 3778 pins = "gpio72", "gpio73"; 3779 function = "qup19"; 3780 }; 3781 3782 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 3783 pins = "gpio76", "gpio77"; 3784 function = "qup20"; 3785 }; 3786 3787 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 3788 pins = "gpio80", "gpio81"; 3789 function = "qup21"; 3790 }; 3791 3792 qup_spi0_cs: qup-spi0-cs-state { 3793 pins = "gpio3"; 3794 function = "qup0"; 3795 }; 3796 3797 qup_spi0_data_clk: qup-spi0-data-clk-state { 3798 pins = "gpio0", "gpio1", "gpio2"; 3799 function = "qup0"; 3800 }; 3801 3802 qup_spi1_cs: qup-spi1-cs-state { 3803 pins = "gpio7"; 3804 function = "qup1"; 3805 }; 3806 3807 qup_spi1_data_clk: qup-spi1-data-clk-state { 3808 pins = "gpio4", "gpio5", "gpio6"; 3809 function = "qup1"; 3810 }; 3811 3812 qup_spi2_cs: qup-spi2-cs-state { 3813 pins = "gpio11"; 3814 function = "qup2"; 3815 }; 3816 3817 qup_spi2_data_clk: qup-spi2-data-clk-state { 3818 pins = "gpio8", "gpio9", "gpio10"; 3819 function = "qup2"; 3820 }; 3821 3822 qup_spi3_cs: qup-spi3-cs-state { 3823 pins = "gpio15"; 3824 function = "qup3"; 3825 }; 3826 3827 qup_spi3_data_clk: qup-spi3-data-clk-state { 3828 pins = "gpio12", "gpio13", "gpio14"; 3829 function = "qup3"; 3830 }; 3831 3832 qup_spi4_cs: qup-spi4-cs-state { 3833 pins = "gpio19"; 3834 function = "qup4"; 3835 drive-strength = <6>; 3836 bias-disable; 3837 }; 3838 3839 qup_spi4_data_clk: qup-spi4-data-clk-state { 3840 pins = "gpio16", "gpio17", "gpio18"; 3841 function = "qup4"; 3842 }; 3843 3844 qup_spi5_cs: qup-spi5-cs-state { 3845 pins = "gpio85"; 3846 function = "qup5"; 3847 }; 3848 3849 qup_spi5_data_clk: qup-spi5-data-clk-state { 3850 pins = "gpio206", "gpio207", "gpio84"; 3851 function = "qup5"; 3852 }; 3853 3854 qup_spi6_cs: qup-spi6-cs-state { 3855 pins = "gpio23"; 3856 function = "qup6"; 3857 }; 3858 3859 qup_spi6_data_clk: qup-spi6-data-clk-state { 3860 pins = "gpio20", "gpio21", "gpio22"; 3861 function = "qup6"; 3862 }; 3863 3864 qup_spi8_cs: qup-spi8-cs-state { 3865 pins = "gpio31"; 3866 function = "qup8"; 3867 }; 3868 3869 qup_spi8_data_clk: qup-spi8-data-clk-state { 3870 pins = "gpio28", "gpio29", "gpio30"; 3871 function = "qup8"; 3872 }; 3873 3874 qup_spi9_cs: qup-spi9-cs-state { 3875 pins = "gpio35"; 3876 function = "qup9"; 3877 }; 3878 3879 qup_spi9_data_clk: qup-spi9-data-clk-state { 3880 pins = "gpio32", "gpio33", "gpio34"; 3881 function = "qup9"; 3882 }; 3883 3884 qup_spi10_cs: qup-spi10-cs-state { 3885 pins = "gpio39"; 3886 function = "qup10"; 3887 }; 3888 3889 qup_spi10_data_clk: qup-spi10-data-clk-state { 3890 pins = "gpio36", "gpio37", "gpio38"; 3891 function = "qup10"; 3892 }; 3893 3894 qup_spi11_cs: qup-spi11-cs-state { 3895 pins = "gpio43"; 3896 function = "qup11"; 3897 }; 3898 3899 qup_spi11_data_clk: qup-spi11-data-clk-state { 3900 pins = "gpio40", "gpio41", "gpio42"; 3901 function = "qup11"; 3902 }; 3903 3904 qup_spi12_cs: qup-spi12-cs-state { 3905 pins = "gpio47"; 3906 function = "qup12"; 3907 }; 3908 3909 qup_spi12_data_clk: qup-spi12-data-clk-state { 3910 pins = "gpio44", "gpio45", "gpio46"; 3911 function = "qup12"; 3912 }; 3913 3914 qup_spi13_cs: qup-spi13-cs-state { 3915 pins = "gpio51"; 3916 function = "qup13"; 3917 }; 3918 3919 qup_spi13_data_clk: qup-spi13-data-clk-state { 3920 pins = "gpio48", "gpio49", "gpio50"; 3921 function = "qup13"; 3922 }; 3923 3924 qup_spi14_cs: qup-spi14-cs-state { 3925 pins = "gpio55"; 3926 function = "qup14"; 3927 }; 3928 3929 qup_spi14_data_clk: qup-spi14-data-clk-state { 3930 pins = "gpio52", "gpio53", "gpio54"; 3931 function = "qup14"; 3932 }; 3933 3934 qup_spi15_cs: qup-spi15-cs-state { 3935 pins = "gpio59"; 3936 function = "qup15"; 3937 }; 3938 3939 qup_spi15_data_clk: qup-spi15-data-clk-state { 3940 pins = "gpio56", "gpio57", "gpio58"; 3941 function = "qup15"; 3942 }; 3943 3944 qup_spi16_cs: qup-spi16-cs-state { 3945 pins = "gpio63"; 3946 function = "qup16"; 3947 }; 3948 3949 qup_spi16_data_clk: qup-spi16-data-clk-state { 3950 pins = "gpio60", "gpio61", "gpio62"; 3951 function = "qup16"; 3952 }; 3953 3954 qup_spi17_cs: qup-spi17-cs-state { 3955 pins = "gpio67"; 3956 function = "qup17"; 3957 }; 3958 3959 qup_spi17_data_clk: qup-spi17-data-clk-state { 3960 pins = "gpio64", "gpio65", "gpio66"; 3961 function = "qup17"; 3962 }; 3963 3964 qup_spi18_cs: qup-spi18-cs-state { 3965 pins = "gpio71"; 3966 function = "qup18"; 3967 drive-strength = <6>; 3968 bias-disable; 3969 }; 3970 3971 qup_spi18_data_clk: qup-spi18-data-clk-state { 3972 pins = "gpio68", "gpio69", "gpio70"; 3973 function = "qup18"; 3974 drive-strength = <6>; 3975 bias-disable; 3976 }; 3977 3978 qup_spi19_cs: qup-spi19-cs-state { 3979 pins = "gpio75"; 3980 function = "qup19"; 3981 drive-strength = <6>; 3982 bias-disable; 3983 }; 3984 3985 qup_spi19_data_clk: qup-spi19-data-clk-state { 3986 pins = "gpio72", "gpio73", "gpio74"; 3987 function = "qup19"; 3988 drive-strength = <6>; 3989 bias-disable; 3990 }; 3991 3992 qup_spi20_cs: qup-spi20-cs-state { 3993 pins = "gpio79"; 3994 function = "qup20"; 3995 }; 3996 3997 qup_spi20_data_clk: qup-spi20-data-clk-state { 3998 pins = "gpio76", "gpio77", "gpio78"; 3999 function = "qup20"; 4000 }; 4001 4002 qup_spi21_cs: qup-spi21-cs-state { 4003 pins = "gpio83"; 4004 function = "qup21"; 4005 }; 4006 4007 qup_spi21_data_clk: qup-spi21-data-clk-state { 4008 pins = "gpio80", "gpio81", "gpio82"; 4009 function = "qup21"; 4010 }; 4011 4012 qup_uart7_rx: qup-uart7-rx-state { 4013 pins = "gpio26"; 4014 function = "qup7"; 4015 drive-strength = <2>; 4016 bias-disable; 4017 }; 4018 4019 qup_uart7_tx: qup-uart7-tx-state { 4020 pins = "gpio27"; 4021 function = "qup7"; 4022 drive-strength = <2>; 4023 bias-disable; 4024 }; 4025 4026 qup_uart20_default: qup-uart20-default-state { 4027 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 4028 function = "qup20"; 4029 }; 4030 }; 4031 4032 lpass_tlmm: pinctrl@3440000 { 4033 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 4034 reg = <0 0x03440000 0x0 0x20000>, 4035 <0 0x034d0000 0x0 0x10000>; 4036 gpio-controller; 4037 #gpio-cells = <2>; 4038 gpio-ranges = <&lpass_tlmm 0 0 23>; 4039 4040 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4041 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4042 clock-names = "core", "audio"; 4043 4044 tx_swr_active: tx-swr-active-state { 4045 clk-pins { 4046 pins = "gpio0"; 4047 function = "swr_tx_clk"; 4048 drive-strength = <2>; 4049 slew-rate = <1>; 4050 bias-disable; 4051 }; 4052 4053 data-pins { 4054 pins = "gpio1", "gpio2", "gpio14"; 4055 function = "swr_tx_data"; 4056 drive-strength = <2>; 4057 slew-rate = <1>; 4058 bias-bus-hold; 4059 }; 4060 }; 4061 4062 rx_swr_active: rx-swr-active-state { 4063 clk-pins { 4064 pins = "gpio3"; 4065 function = "swr_rx_clk"; 4066 drive-strength = <2>; 4067 slew-rate = <1>; 4068 bias-disable; 4069 }; 4070 4071 data-pins { 4072 pins = "gpio4", "gpio5"; 4073 function = "swr_rx_data"; 4074 drive-strength = <2>; 4075 slew-rate = <1>; 4076 bias-bus-hold; 4077 }; 4078 }; 4079 4080 dmic01_default: dmic01-default-state { 4081 clk-pins { 4082 pins = "gpio6"; 4083 function = "dmic1_clk"; 4084 drive-strength = <8>; 4085 output-high; 4086 }; 4087 4088 data-pins { 4089 pins = "gpio7"; 4090 function = "dmic1_data"; 4091 drive-strength = <8>; 4092 }; 4093 }; 4094 4095 dmic23_default: dmic23-default-state { 4096 clk-pins { 4097 pins = "gpio8"; 4098 function = "dmic2_clk"; 4099 drive-strength = <8>; 4100 output-high; 4101 }; 4102 4103 data-pins { 4104 pins = "gpio9"; 4105 function = "dmic2_data"; 4106 drive-strength = <8>; 4107 }; 4108 }; 4109 4110 wsa_swr_active: wsa-swr-active-state { 4111 clk-pins { 4112 pins = "gpio10"; 4113 function = "wsa_swr_clk"; 4114 drive-strength = <2>; 4115 slew-rate = <1>; 4116 bias-disable; 4117 }; 4118 4119 data-pins { 4120 pins = "gpio11"; 4121 function = "wsa_swr_data"; 4122 drive-strength = <2>; 4123 slew-rate = <1>; 4124 bias-bus-hold; 4125 }; 4126 }; 4127 4128 wsa2_swr_active: wsa2-swr-active-state { 4129 clk-pins { 4130 pins = "gpio15"; 4131 function = "wsa2_swr_clk"; 4132 drive-strength = <2>; 4133 slew-rate = <1>; 4134 bias-disable; 4135 }; 4136 4137 data-pins { 4138 pins = "gpio16"; 4139 function = "wsa2_swr_data"; 4140 drive-strength = <2>; 4141 slew-rate = <1>; 4142 bias-bus-hold; 4143 }; 4144 }; 4145 }; 4146 4147 sram@146aa000 { 4148 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; 4149 reg = <0 0x146aa000 0 0x1000>; 4150 ranges = <0 0 0x146aa000 0x1000>; 4151 4152 #address-cells = <1>; 4153 #size-cells = <1>; 4154 4155 pil-reloc@94c { 4156 compatible = "qcom,pil-reloc-info"; 4157 reg = <0x94c 0xc8>; 4158 }; 4159 }; 4160 4161 apps_smmu: iommu@15000000 { 4162 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 4163 reg = <0 0x15000000 0 0x100000>; 4164 #iommu-cells = <2>; 4165 #global-interrupts = <1>; 4166 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4167 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4168 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4169 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4170 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4171 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4172 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4173 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4174 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4175 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4176 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4178 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4179 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4180 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4181 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4182 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4183 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4184 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4185 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4186 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4187 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4188 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4189 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4190 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4191 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4192 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4194 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4195 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4197 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4198 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4199 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4200 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4201 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4202 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4203 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4204 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4205 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4206 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4207 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4208 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4209 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4210 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4211 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4212 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4213 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4214 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4215 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4216 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4217 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4218 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4219 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4220 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4221 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4222 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4223 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4224 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4225 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4226 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4227 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4228 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4229 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4230 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4231 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4232 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4233 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4234 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4235 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4236 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4237 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4238 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4239 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4240 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4241 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4242 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4243 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4244 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4245 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4246 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4247 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4248 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4249 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4250 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4251 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4252 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4253 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4254 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4255 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4256 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4257 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4258 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4259 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4260 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4261 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4262 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 4263 dma-coherent; 4264 }; 4265 4266 intc: interrupt-controller@17100000 { 4267 compatible = "arm,gic-v3"; 4268 #interrupt-cells = <3>; 4269 interrupt-controller; 4270 #redistributor-regions = <1>; 4271 redistributor-stride = <0x0 0x40000>; 4272 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 4273 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 4274 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4275 #address-cells = <2>; 4276 #size-cells = <2>; 4277 ranges; 4278 4279 gic_its: msi-controller@17140000 { 4280 compatible = "arm,gic-v3-its"; 4281 reg = <0x0 0x17140000 0x0 0x20000>; 4282 msi-controller; 4283 #msi-cells = <1>; 4284 }; 4285 }; 4286 4287 timer@17420000 { 4288 compatible = "arm,armv7-timer-mem"; 4289 #address-cells = <1>; 4290 #size-cells = <1>; 4291 ranges = <0 0 0 0x20000000>; 4292 reg = <0x0 0x17420000 0x0 0x1000>; 4293 clock-frequency = <19200000>; 4294 4295 frame@17421000 { 4296 frame-number = <0>; 4297 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4298 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4299 reg = <0x17421000 0x1000>, 4300 <0x17422000 0x1000>; 4301 }; 4302 4303 frame@17423000 { 4304 frame-number = <1>; 4305 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4306 reg = <0x17423000 0x1000>; 4307 status = "disabled"; 4308 }; 4309 4310 frame@17425000 { 4311 frame-number = <2>; 4312 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4313 reg = <0x17425000 0x1000>; 4314 status = "disabled"; 4315 }; 4316 4317 frame@17427000 { 4318 frame-number = <3>; 4319 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4320 reg = <0x17427000 0x1000>; 4321 status = "disabled"; 4322 }; 4323 4324 frame@17429000 { 4325 frame-number = <4>; 4326 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4327 reg = <0x17429000 0x1000>; 4328 status = "disabled"; 4329 }; 4330 4331 frame@1742b000 { 4332 frame-number = <5>; 4333 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4334 reg = <0x1742b000 0x1000>; 4335 status = "disabled"; 4336 }; 4337 4338 frame@1742d000 { 4339 frame-number = <6>; 4340 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4341 reg = <0x1742d000 0x1000>; 4342 status = "disabled"; 4343 }; 4344 }; 4345 4346 apps_rsc: rsc@17a00000 { 4347 label = "apps_rsc"; 4348 compatible = "qcom,rpmh-rsc"; 4349 reg = <0x0 0x17a00000 0x0 0x10000>, 4350 <0x0 0x17a10000 0x0 0x10000>, 4351 <0x0 0x17a20000 0x0 0x10000>, 4352 <0x0 0x17a30000 0x0 0x10000>; 4353 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 4354 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4355 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4356 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4357 qcom,tcs-offset = <0xd00>; 4358 qcom,drv-id = <2>; 4359 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4360 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4361 power-domains = <&cluster_pd>; 4362 4363 apps_bcm_voter: bcm-voter { 4364 compatible = "qcom,bcm-voter"; 4365 }; 4366 4367 rpmhcc: clock-controller { 4368 compatible = "qcom,sm8450-rpmh-clk"; 4369 #clock-cells = <1>; 4370 clock-names = "xo"; 4371 clocks = <&xo_board>; 4372 }; 4373 4374 rpmhpd: power-controller { 4375 compatible = "qcom,sm8450-rpmhpd"; 4376 #power-domain-cells = <1>; 4377 operating-points-v2 = <&rpmhpd_opp_table>; 4378 4379 rpmhpd_opp_table: opp-table { 4380 compatible = "operating-points-v2"; 4381 4382 rpmhpd_opp_ret: opp1 { 4383 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4384 }; 4385 4386 rpmhpd_opp_min_svs: opp2 { 4387 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4388 }; 4389 4390 rpmhpd_opp_low_svs_d1: opp3 { 4391 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4392 }; 4393 4394 rpmhpd_opp_low_svs: opp4 { 4395 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4396 }; 4397 4398 rpmhpd_opp_low_svs_l1: opp5 { 4399 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4400 }; 4401 4402 rpmhpd_opp_svs: opp6 { 4403 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4404 }; 4405 4406 rpmhpd_opp_svs_l0: opp7 { 4407 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4408 }; 4409 4410 rpmhpd_opp_svs_l1: opp8 { 4411 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4412 }; 4413 4414 rpmhpd_opp_svs_l2: opp9 { 4415 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4416 }; 4417 4418 rpmhpd_opp_nom: opp10 { 4419 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4420 }; 4421 4422 rpmhpd_opp_nom_l1: opp11 { 4423 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4424 }; 4425 4426 rpmhpd_opp_nom_l2: opp12 { 4427 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4428 }; 4429 4430 rpmhpd_opp_turbo: opp13 { 4431 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4432 }; 4433 4434 rpmhpd_opp_turbo_l1: opp14 { 4435 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4436 }; 4437 }; 4438 }; 4439 }; 4440 4441 cpufreq_hw: cpufreq@17d91000 { 4442 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 4443 reg = <0 0x17d91000 0 0x1000>, 4444 <0 0x17d92000 0 0x1000>, 4445 <0 0x17d93000 0 0x1000>; 4446 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4447 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4448 clock-names = "xo", "alternate"; 4449 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4450 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4451 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4452 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4453 #freq-domain-cells = <1>; 4454 #clock-cells = <1>; 4455 }; 4456 4457 gem_noc: interconnect@19100000 { 4458 compatible = "qcom,sm8450-gem-noc"; 4459 reg = <0 0x19100000 0 0xbb800>; 4460 #interconnect-cells = <2>; 4461 qcom,bcm-voters = <&apps_bcm_voter>; 4462 }; 4463 4464 system-cache-controller@19200000 { 4465 compatible = "qcom,sm8450-llcc"; 4466 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, 4467 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, 4468 <0 0x19a00000 0 0x80000>, <0 0x19c00000 0 0x80000>; 4469 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4470 "llcc3_base", "llcc_broadcast_base", 4471 "llcc_broadcast_and_base"; 4472 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4473 }; 4474 4475 ufs_mem_hc: ufshc@1d84000 { 4476 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 4477 "jedec,ufs-2.0"; 4478 reg = <0 0x01d84000 0 0x3000>; 4479 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 4480 phys = <&ufs_mem_phy>; 4481 phy-names = "ufsphy"; 4482 lanes-per-direction = <2>; 4483 #reset-cells = <1>; 4484 resets = <&gcc GCC_UFS_PHY_BCR>; 4485 reset-names = "rst"; 4486 4487 power-domains = <&gcc UFS_PHY_GDSC>; 4488 4489 iommus = <&apps_smmu 0xe0 0x0>; 4490 dma-coherent; 4491 4492 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 4493 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 4494 interconnect-names = "ufs-ddr", "cpu-ufs"; 4495 clock-names = 4496 "core_clk", 4497 "bus_aggr_clk", 4498 "iface_clk", 4499 "core_clk_unipro", 4500 "ref_clk", 4501 "tx_lane0_sync_clk", 4502 "rx_lane0_sync_clk", 4503 "rx_lane1_sync_clk"; 4504 clocks = 4505 <&gcc GCC_UFS_PHY_AXI_CLK>, 4506 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 4507 <&gcc GCC_UFS_PHY_AHB_CLK>, 4508 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 4509 <&rpmhcc RPMH_CXO_CLK>, 4510 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 4511 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 4512 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 4513 freq-table-hz = 4514 <75000000 300000000>, 4515 <0 0>, 4516 <0 0>, 4517 <75000000 300000000>, 4518 <75000000 300000000>, 4519 <0 0>, 4520 <0 0>, 4521 <0 0>; 4522 qcom,ice = <&ice>; 4523 4524 status = "disabled"; 4525 }; 4526 4527 ufs_mem_phy: phy@1d87000 { 4528 compatible = "qcom,sm8450-qmp-ufs-phy"; 4529 reg = <0 0x01d87000 0 0x1000>; 4530 4531 clock-names = "ref", "ref_aux", "qref"; 4532 clocks = <&rpmhcc RPMH_CXO_CLK>, 4533 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 4534 <&gcc GCC_UFS_0_CLKREF_EN>; 4535 4536 power-domains = <&gcc UFS_PHY_GDSC>; 4537 4538 resets = <&ufs_mem_hc 0>; 4539 reset-names = "ufsphy"; 4540 4541 #clock-cells = <1>; 4542 #phy-cells = <0>; 4543 4544 status = "disabled"; 4545 }; 4546 4547 ice: crypto@1d88000 { 4548 compatible = "qcom,sm8450-inline-crypto-engine", 4549 "qcom,inline-crypto-engine"; 4550 reg = <0 0x01d88000 0 0x8000>; 4551 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4552 }; 4553 4554 cryptobam: dma-controller@1dc4000 { 4555 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 4556 reg = <0 0x01dc4000 0 0x28000>; 4557 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 4558 #dma-cells = <1>; 4559 qcom,ee = <0>; 4560 qcom,controlled-remotely; 4561 iommus = <&apps_smmu 0x584 0x11>, 4562 <&apps_smmu 0x588 0x0>, 4563 <&apps_smmu 0x598 0x5>, 4564 <&apps_smmu 0x59a 0x0>, 4565 <&apps_smmu 0x59f 0x0>; 4566 }; 4567 4568 crypto: crypto@1dfa000 { 4569 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; 4570 reg = <0 0x01dfa000 0 0x6000>; 4571 dmas = <&cryptobam 4>, <&cryptobam 5>; 4572 dma-names = "rx", "tx"; 4573 iommus = <&apps_smmu 0x584 0x11>, 4574 <&apps_smmu 0x588 0x0>, 4575 <&apps_smmu 0x598 0x5>, 4576 <&apps_smmu 0x59a 0x0>, 4577 <&apps_smmu 0x59f 0x0>; 4578 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 4579 interconnect-names = "memory"; 4580 }; 4581 4582 sdhc_2: mmc@8804000 { 4583 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 4584 reg = <0 0x08804000 0 0x1000>; 4585 4586 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4587 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4588 interrupt-names = "hc_irq", "pwr_irq"; 4589 4590 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4591 <&gcc GCC_SDCC2_APPS_CLK>, 4592 <&rpmhcc RPMH_CXO_CLK>; 4593 clock-names = "iface", "core", "xo"; 4594 resets = <&gcc GCC_SDCC2_BCR>; 4595 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4596 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 4597 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4598 iommus = <&apps_smmu 0x4a0 0x0>; 4599 power-domains = <&rpmhpd RPMHPD_CX>; 4600 operating-points-v2 = <&sdhc2_opp_table>; 4601 bus-width = <4>; 4602 dma-coherent; 4603 4604 /* Forbid SDR104/SDR50 - broken hw! */ 4605 sdhci-caps-mask = <0x3 0x0>; 4606 4607 status = "disabled"; 4608 4609 sdhc2_opp_table: opp-table { 4610 compatible = "operating-points-v2"; 4611 4612 opp-100000000 { 4613 opp-hz = /bits/ 64 <100000000>; 4614 required-opps = <&rpmhpd_opp_low_svs>; 4615 }; 4616 4617 opp-202000000 { 4618 opp-hz = /bits/ 64 <202000000>; 4619 required-opps = <&rpmhpd_opp_svs_l1>; 4620 }; 4621 }; 4622 }; 4623 4624 usb_1: usb@a6f8800 { 4625 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 4626 reg = <0 0x0a6f8800 0 0x400>; 4627 status = "disabled"; 4628 #address-cells = <2>; 4629 #size-cells = <2>; 4630 ranges; 4631 4632 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4633 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4634 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4635 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4636 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4637 <&gcc GCC_USB3_0_CLKREF_EN>; 4638 clock-names = "cfg_noc", 4639 "core", 4640 "iface", 4641 "sleep", 4642 "mock_utmi", 4643 "xo"; 4644 4645 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4646 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4647 assigned-clock-rates = <19200000>, <200000000>; 4648 4649 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4650 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4651 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4652 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4653 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4654 interrupt-names = "pwr_event", 4655 "hs_phy_irq", 4656 "dp_hs_phy_irq", 4657 "dm_hs_phy_irq", 4658 "ss_phy_irq"; 4659 4660 power-domains = <&gcc USB30_PRIM_GDSC>; 4661 4662 resets = <&gcc GCC_USB30_PRIM_BCR>; 4663 4664 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4665 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4666 interconnect-names = "usb-ddr", "apps-usb"; 4667 4668 usb_1_dwc3: usb@a600000 { 4669 compatible = "snps,dwc3"; 4670 reg = <0 0x0a600000 0 0xcd00>; 4671 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4672 iommus = <&apps_smmu 0x0 0x0>; 4673 snps,dis_u2_susphy_quirk; 4674 snps,dis_enblslpm_quirk; 4675 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4676 phy-names = "usb2-phy", "usb3-phy"; 4677 4678 ports { 4679 #address-cells = <1>; 4680 #size-cells = <0>; 4681 4682 port@0 { 4683 reg = <0>; 4684 4685 usb_1_dwc3_hs: endpoint { 4686 }; 4687 }; 4688 4689 port@1 { 4690 reg = <1>; 4691 4692 usb_1_dwc3_ss: endpoint { 4693 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4694 }; 4695 }; 4696 }; 4697 }; 4698 }; 4699 4700 nsp_noc: interconnect@320c0000 { 4701 compatible = "qcom,sm8450-nsp-noc"; 4702 reg = <0 0x320c0000 0 0x10000>; 4703 #interconnect-cells = <2>; 4704 qcom,bcm-voters = <&apps_bcm_voter>; 4705 }; 4706 4707 lpass_ag_noc: interconnect@3c40000 { 4708 compatible = "qcom,sm8450-lpass-ag-noc"; 4709 reg = <0 0x03c40000 0 0x17200>; 4710 #interconnect-cells = <2>; 4711 qcom,bcm-voters = <&apps_bcm_voter>; 4712 }; 4713 }; 4714 4715 sound: sound { 4716 }; 4717 4718 thermal-zones { 4719 aoss0-thermal { 4720 thermal-sensors = <&tsens0 0>; 4721 4722 trips { 4723 thermal-engine-config { 4724 temperature = <125000>; 4725 hysteresis = <1000>; 4726 type = "passive"; 4727 }; 4728 4729 reset-mon-cfg { 4730 temperature = <115000>; 4731 hysteresis = <5000>; 4732 type = "passive"; 4733 }; 4734 }; 4735 }; 4736 4737 cpuss0-thermal { 4738 thermal-sensors = <&tsens0 1>; 4739 4740 trips { 4741 thermal-engine-config { 4742 temperature = <125000>; 4743 hysteresis = <1000>; 4744 type = "passive"; 4745 }; 4746 4747 reset-mon-cfg { 4748 temperature = <115000>; 4749 hysteresis = <5000>; 4750 type = "passive"; 4751 }; 4752 }; 4753 }; 4754 4755 cpuss1-thermal { 4756 thermal-sensors = <&tsens0 2>; 4757 4758 trips { 4759 thermal-engine-config { 4760 temperature = <125000>; 4761 hysteresis = <1000>; 4762 type = "passive"; 4763 }; 4764 4765 reset-mon-cfg { 4766 temperature = <115000>; 4767 hysteresis = <5000>; 4768 type = "passive"; 4769 }; 4770 }; 4771 }; 4772 4773 cpuss3-thermal { 4774 thermal-sensors = <&tsens0 3>; 4775 4776 trips { 4777 thermal-engine-config { 4778 temperature = <125000>; 4779 hysteresis = <1000>; 4780 type = "passive"; 4781 }; 4782 4783 reset-mon-cfg { 4784 temperature = <115000>; 4785 hysteresis = <5000>; 4786 type = "passive"; 4787 }; 4788 }; 4789 }; 4790 4791 cpuss4-thermal { 4792 thermal-sensors = <&tsens0 4>; 4793 4794 trips { 4795 thermal-engine-config { 4796 temperature = <125000>; 4797 hysteresis = <1000>; 4798 type = "passive"; 4799 }; 4800 4801 reset-mon-cfg { 4802 temperature = <115000>; 4803 hysteresis = <5000>; 4804 type = "passive"; 4805 }; 4806 }; 4807 }; 4808 4809 cpu4-top-thermal { 4810 thermal-sensors = <&tsens0 5>; 4811 4812 trips { 4813 cpu4_top_alert0: trip-point0 { 4814 temperature = <90000>; 4815 hysteresis = <2000>; 4816 type = "passive"; 4817 }; 4818 4819 cpu4_top_alert1: trip-point1 { 4820 temperature = <95000>; 4821 hysteresis = <2000>; 4822 type = "passive"; 4823 }; 4824 4825 cpu4_top_crit: cpu-crit { 4826 temperature = <110000>; 4827 hysteresis = <1000>; 4828 type = "critical"; 4829 }; 4830 }; 4831 }; 4832 4833 cpu4-bottom-thermal { 4834 thermal-sensors = <&tsens0 6>; 4835 4836 trips { 4837 cpu4_bottom_alert0: trip-point0 { 4838 temperature = <90000>; 4839 hysteresis = <2000>; 4840 type = "passive"; 4841 }; 4842 4843 cpu4_bottom_alert1: trip-point1 { 4844 temperature = <95000>; 4845 hysteresis = <2000>; 4846 type = "passive"; 4847 }; 4848 4849 cpu4_bottom_crit: cpu-crit { 4850 temperature = <110000>; 4851 hysteresis = <1000>; 4852 type = "critical"; 4853 }; 4854 }; 4855 }; 4856 4857 cpu5-top-thermal { 4858 thermal-sensors = <&tsens0 7>; 4859 4860 trips { 4861 cpu5_top_alert0: trip-point0 { 4862 temperature = <90000>; 4863 hysteresis = <2000>; 4864 type = "passive"; 4865 }; 4866 4867 cpu5_top_alert1: trip-point1 { 4868 temperature = <95000>; 4869 hysteresis = <2000>; 4870 type = "passive"; 4871 }; 4872 4873 cpu5_top_crit: cpu-crit { 4874 temperature = <110000>; 4875 hysteresis = <1000>; 4876 type = "critical"; 4877 }; 4878 }; 4879 }; 4880 4881 cpu5-bottom-thermal { 4882 thermal-sensors = <&tsens0 8>; 4883 4884 trips { 4885 cpu5_bottom_alert0: trip-point0 { 4886 temperature = <90000>; 4887 hysteresis = <2000>; 4888 type = "passive"; 4889 }; 4890 4891 cpu5_bottom_alert1: trip-point1 { 4892 temperature = <95000>; 4893 hysteresis = <2000>; 4894 type = "passive"; 4895 }; 4896 4897 cpu5_bottom_crit: cpu-crit { 4898 temperature = <110000>; 4899 hysteresis = <1000>; 4900 type = "critical"; 4901 }; 4902 }; 4903 }; 4904 4905 cpu6-top-thermal { 4906 thermal-sensors = <&tsens0 9>; 4907 4908 trips { 4909 cpu6_top_alert0: trip-point0 { 4910 temperature = <90000>; 4911 hysteresis = <2000>; 4912 type = "passive"; 4913 }; 4914 4915 cpu6_top_alert1: trip-point1 { 4916 temperature = <95000>; 4917 hysteresis = <2000>; 4918 type = "passive"; 4919 }; 4920 4921 cpu6_top_crit: cpu-crit { 4922 temperature = <110000>; 4923 hysteresis = <1000>; 4924 type = "critical"; 4925 }; 4926 }; 4927 }; 4928 4929 cpu6-bottom-thermal { 4930 thermal-sensors = <&tsens0 10>; 4931 4932 trips { 4933 cpu6_bottom_alert0: trip-point0 { 4934 temperature = <90000>; 4935 hysteresis = <2000>; 4936 type = "passive"; 4937 }; 4938 4939 cpu6_bottom_alert1: trip-point1 { 4940 temperature = <95000>; 4941 hysteresis = <2000>; 4942 type = "passive"; 4943 }; 4944 4945 cpu6_bottom_crit: cpu-crit { 4946 temperature = <110000>; 4947 hysteresis = <1000>; 4948 type = "critical"; 4949 }; 4950 }; 4951 }; 4952 4953 cpu7-top-thermal { 4954 thermal-sensors = <&tsens0 11>; 4955 4956 trips { 4957 cpu7_top_alert0: trip-point0 { 4958 temperature = <90000>; 4959 hysteresis = <2000>; 4960 type = "passive"; 4961 }; 4962 4963 cpu7_top_alert1: trip-point1 { 4964 temperature = <95000>; 4965 hysteresis = <2000>; 4966 type = "passive"; 4967 }; 4968 4969 cpu7_top_crit: cpu-crit { 4970 temperature = <110000>; 4971 hysteresis = <1000>; 4972 type = "critical"; 4973 }; 4974 }; 4975 }; 4976 4977 cpu7-middle-thermal { 4978 thermal-sensors = <&tsens0 12>; 4979 4980 trips { 4981 cpu7_middle_alert0: trip-point0 { 4982 temperature = <90000>; 4983 hysteresis = <2000>; 4984 type = "passive"; 4985 }; 4986 4987 cpu7_middle_alert1: trip-point1 { 4988 temperature = <95000>; 4989 hysteresis = <2000>; 4990 type = "passive"; 4991 }; 4992 4993 cpu7_middle_crit: cpu-crit { 4994 temperature = <110000>; 4995 hysteresis = <1000>; 4996 type = "critical"; 4997 }; 4998 }; 4999 }; 5000 5001 cpu7-bottom-thermal { 5002 thermal-sensors = <&tsens0 13>; 5003 5004 trips { 5005 cpu7_bottom_alert0: trip-point0 { 5006 temperature = <90000>; 5007 hysteresis = <2000>; 5008 type = "passive"; 5009 }; 5010 5011 cpu7_bottom_alert1: trip-point1 { 5012 temperature = <95000>; 5013 hysteresis = <2000>; 5014 type = "passive"; 5015 }; 5016 5017 cpu7_bottom_crit: cpu-crit { 5018 temperature = <110000>; 5019 hysteresis = <1000>; 5020 type = "critical"; 5021 }; 5022 }; 5023 }; 5024 5025 gpu-top-thermal { 5026 polling-delay-passive = <10>; 5027 5028 thermal-sensors = <&tsens0 14>; 5029 5030 cooling-maps { 5031 map0 { 5032 trip = <&gpu_top_alert0>; 5033 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5034 }; 5035 }; 5036 5037 trips { 5038 gpu_top_alert0: trip-point0 { 5039 temperature = <85000>; 5040 hysteresis = <1000>; 5041 type = "passive"; 5042 }; 5043 5044 trip-point1 { 5045 temperature = <90000>; 5046 hysteresis = <1000>; 5047 type = "hot"; 5048 }; 5049 5050 trip-point2 { 5051 temperature = <110000>; 5052 hysteresis = <1000>; 5053 type = "critical"; 5054 }; 5055 }; 5056 }; 5057 5058 gpu-bottom-thermal { 5059 polling-delay-passive = <10>; 5060 5061 thermal-sensors = <&tsens0 15>; 5062 5063 cooling-maps { 5064 map0 { 5065 trip = <&gpu_bottom_alert0>; 5066 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5067 }; 5068 }; 5069 5070 trips { 5071 gpu_bottom_alert0: trip-point0 { 5072 temperature = <85000>; 5073 hysteresis = <1000>; 5074 type = "passive"; 5075 }; 5076 5077 trip-point1 { 5078 temperature = <90000>; 5079 hysteresis = <1000>; 5080 type = "hot"; 5081 }; 5082 5083 trip-point2 { 5084 temperature = <110000>; 5085 hysteresis = <1000>; 5086 type = "critical"; 5087 }; 5088 }; 5089 }; 5090 5091 aoss1-thermal { 5092 thermal-sensors = <&tsens1 0>; 5093 5094 trips { 5095 thermal-engine-config { 5096 temperature = <125000>; 5097 hysteresis = <1000>; 5098 type = "passive"; 5099 }; 5100 5101 reset-mon-cfg { 5102 temperature = <115000>; 5103 hysteresis = <5000>; 5104 type = "passive"; 5105 }; 5106 }; 5107 }; 5108 5109 cpu0-thermal { 5110 thermal-sensors = <&tsens1 1>; 5111 5112 trips { 5113 cpu0_alert0: trip-point0 { 5114 temperature = <90000>; 5115 hysteresis = <2000>; 5116 type = "passive"; 5117 }; 5118 5119 cpu0_alert1: trip-point1 { 5120 temperature = <95000>; 5121 hysteresis = <2000>; 5122 type = "passive"; 5123 }; 5124 5125 cpu0_crit: cpu-crit { 5126 temperature = <110000>; 5127 hysteresis = <1000>; 5128 type = "critical"; 5129 }; 5130 }; 5131 }; 5132 5133 cpu1-thermal { 5134 thermal-sensors = <&tsens1 2>; 5135 5136 trips { 5137 cpu1_alert0: trip-point0 { 5138 temperature = <90000>; 5139 hysteresis = <2000>; 5140 type = "passive"; 5141 }; 5142 5143 cpu1_alert1: trip-point1 { 5144 temperature = <95000>; 5145 hysteresis = <2000>; 5146 type = "passive"; 5147 }; 5148 5149 cpu1_crit: cpu-crit { 5150 temperature = <110000>; 5151 hysteresis = <1000>; 5152 type = "critical"; 5153 }; 5154 }; 5155 }; 5156 5157 cpu2-thermal { 5158 thermal-sensors = <&tsens1 3>; 5159 5160 trips { 5161 cpu2_alert0: trip-point0 { 5162 temperature = <90000>; 5163 hysteresis = <2000>; 5164 type = "passive"; 5165 }; 5166 5167 cpu2_alert1: trip-point1 { 5168 temperature = <95000>; 5169 hysteresis = <2000>; 5170 type = "passive"; 5171 }; 5172 5173 cpu2_crit: cpu-crit { 5174 temperature = <110000>; 5175 hysteresis = <1000>; 5176 type = "critical"; 5177 }; 5178 }; 5179 }; 5180 5181 cpu3-thermal { 5182 thermal-sensors = <&tsens1 4>; 5183 5184 trips { 5185 cpu3_alert0: trip-point0 { 5186 temperature = <90000>; 5187 hysteresis = <2000>; 5188 type = "passive"; 5189 }; 5190 5191 cpu3_alert1: trip-point1 { 5192 temperature = <95000>; 5193 hysteresis = <2000>; 5194 type = "passive"; 5195 }; 5196 5197 cpu3_crit: cpu-crit { 5198 temperature = <110000>; 5199 hysteresis = <1000>; 5200 type = "critical"; 5201 }; 5202 }; 5203 }; 5204 5205 cdsp0-thermal { 5206 polling-delay-passive = <10>; 5207 5208 thermal-sensors = <&tsens1 5>; 5209 5210 trips { 5211 thermal-engine-config { 5212 temperature = <125000>; 5213 hysteresis = <1000>; 5214 type = "passive"; 5215 }; 5216 5217 thermal-hal-config { 5218 temperature = <125000>; 5219 hysteresis = <1000>; 5220 type = "passive"; 5221 }; 5222 5223 reset-mon-cfg { 5224 temperature = <115000>; 5225 hysteresis = <5000>; 5226 type = "passive"; 5227 }; 5228 5229 cdsp_0_config: junction-config { 5230 temperature = <95000>; 5231 hysteresis = <5000>; 5232 type = "passive"; 5233 }; 5234 }; 5235 }; 5236 5237 cdsp1-thermal { 5238 polling-delay-passive = <10>; 5239 5240 thermal-sensors = <&tsens1 6>; 5241 5242 trips { 5243 thermal-engine-config { 5244 temperature = <125000>; 5245 hysteresis = <1000>; 5246 type = "passive"; 5247 }; 5248 5249 thermal-hal-config { 5250 temperature = <125000>; 5251 hysteresis = <1000>; 5252 type = "passive"; 5253 }; 5254 5255 reset-mon-cfg { 5256 temperature = <115000>; 5257 hysteresis = <5000>; 5258 type = "passive"; 5259 }; 5260 5261 cdsp_1_config: junction-config { 5262 temperature = <95000>; 5263 hysteresis = <5000>; 5264 type = "passive"; 5265 }; 5266 }; 5267 }; 5268 5269 cdsp2-thermal { 5270 polling-delay-passive = <10>; 5271 5272 thermal-sensors = <&tsens1 7>; 5273 5274 trips { 5275 thermal-engine-config { 5276 temperature = <125000>; 5277 hysteresis = <1000>; 5278 type = "passive"; 5279 }; 5280 5281 thermal-hal-config { 5282 temperature = <125000>; 5283 hysteresis = <1000>; 5284 type = "passive"; 5285 }; 5286 5287 reset-mon-cfg { 5288 temperature = <115000>; 5289 hysteresis = <5000>; 5290 type = "passive"; 5291 }; 5292 5293 cdsp_2_config: junction-config { 5294 temperature = <95000>; 5295 hysteresis = <5000>; 5296 type = "passive"; 5297 }; 5298 }; 5299 }; 5300 5301 video-thermal { 5302 thermal-sensors = <&tsens1 8>; 5303 5304 trips { 5305 thermal-engine-config { 5306 temperature = <125000>; 5307 hysteresis = <1000>; 5308 type = "passive"; 5309 }; 5310 5311 reset-mon-cfg { 5312 temperature = <115000>; 5313 hysteresis = <5000>; 5314 type = "passive"; 5315 }; 5316 }; 5317 }; 5318 5319 mem-thermal { 5320 polling-delay-passive = <10>; 5321 5322 thermal-sensors = <&tsens1 9>; 5323 5324 trips { 5325 thermal-engine-config { 5326 temperature = <125000>; 5327 hysteresis = <1000>; 5328 type = "passive"; 5329 }; 5330 5331 ddr_config0: ddr0-config { 5332 temperature = <90000>; 5333 hysteresis = <5000>; 5334 type = "passive"; 5335 }; 5336 5337 reset-mon-cfg { 5338 temperature = <115000>; 5339 hysteresis = <5000>; 5340 type = "passive"; 5341 }; 5342 }; 5343 }; 5344 5345 modem0-thermal { 5346 thermal-sensors = <&tsens1 10>; 5347 5348 trips { 5349 thermal-engine-config { 5350 temperature = <125000>; 5351 hysteresis = <1000>; 5352 type = "passive"; 5353 }; 5354 5355 mdmss0_config0: mdmss0-config0 { 5356 temperature = <102000>; 5357 hysteresis = <3000>; 5358 type = "passive"; 5359 }; 5360 5361 mdmss0_config1: mdmss0-config1 { 5362 temperature = <105000>; 5363 hysteresis = <3000>; 5364 type = "passive"; 5365 }; 5366 5367 reset-mon-cfg { 5368 temperature = <115000>; 5369 hysteresis = <5000>; 5370 type = "passive"; 5371 }; 5372 }; 5373 }; 5374 5375 modem1-thermal { 5376 thermal-sensors = <&tsens1 11>; 5377 5378 trips { 5379 thermal-engine-config { 5380 temperature = <125000>; 5381 hysteresis = <1000>; 5382 type = "passive"; 5383 }; 5384 5385 mdmss1_config0: mdmss1-config0 { 5386 temperature = <102000>; 5387 hysteresis = <3000>; 5388 type = "passive"; 5389 }; 5390 5391 mdmss1_config1: mdmss1-config1 { 5392 temperature = <105000>; 5393 hysteresis = <3000>; 5394 type = "passive"; 5395 }; 5396 5397 reset-mon-cfg { 5398 temperature = <115000>; 5399 hysteresis = <5000>; 5400 type = "passive"; 5401 }; 5402 }; 5403 }; 5404 5405 modem2-thermal { 5406 thermal-sensors = <&tsens1 12>; 5407 5408 trips { 5409 thermal-engine-config { 5410 temperature = <125000>; 5411 hysteresis = <1000>; 5412 type = "passive"; 5413 }; 5414 5415 mdmss2_config0: mdmss2-config0 { 5416 temperature = <102000>; 5417 hysteresis = <3000>; 5418 type = "passive"; 5419 }; 5420 5421 mdmss2_config1: mdmss2-config1 { 5422 temperature = <105000>; 5423 hysteresis = <3000>; 5424 type = "passive"; 5425 }; 5426 5427 reset-mon-cfg { 5428 temperature = <115000>; 5429 hysteresis = <5000>; 5430 type = "passive"; 5431 }; 5432 }; 5433 }; 5434 5435 modem3-thermal { 5436 thermal-sensors = <&tsens1 13>; 5437 5438 trips { 5439 thermal-engine-config { 5440 temperature = <125000>; 5441 hysteresis = <1000>; 5442 type = "passive"; 5443 }; 5444 5445 mdmss3_config0: mdmss3-config0 { 5446 temperature = <102000>; 5447 hysteresis = <3000>; 5448 type = "passive"; 5449 }; 5450 5451 mdmss3_config1: mdmss3-config1 { 5452 temperature = <105000>; 5453 hysteresis = <3000>; 5454 type = "passive"; 5455 }; 5456 5457 reset-mon-cfg { 5458 temperature = <115000>; 5459 hysteresis = <5000>; 5460 type = "passive"; 5461 }; 5462 }; 5463 }; 5464 5465 camera0-thermal { 5466 thermal-sensors = <&tsens1 14>; 5467 5468 trips { 5469 thermal-engine-config { 5470 temperature = <125000>; 5471 hysteresis = <1000>; 5472 type = "passive"; 5473 }; 5474 5475 reset-mon-cfg { 5476 temperature = <115000>; 5477 hysteresis = <5000>; 5478 type = "passive"; 5479 }; 5480 }; 5481 }; 5482 5483 camera1-thermal { 5484 thermal-sensors = <&tsens1 15>; 5485 5486 trips { 5487 thermal-engine-config { 5488 temperature = <125000>; 5489 hysteresis = <1000>; 5490 type = "passive"; 5491 }; 5492 5493 reset-mon-cfg { 5494 temperature = <115000>; 5495 hysteresis = <5000>; 5496 type = "passive"; 5497 }; 5498 }; 5499 }; 5500 }; 5501 5502 timer { 5503 compatible = "arm,armv8-timer"; 5504 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5505 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5506 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5507 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5508 clock-frequency = <19200000>; 5509 }; 5510}; 5511