xref: /linux/arch/arm64/boot/dts/qcom/sm8450.dtsi (revision c5288cda69ee2d8607f5026bd599a5cebf0ee783)
1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Copyright (c) 2021, Linaro Limited
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/qcom,gcc-sm8450.h>
8#include <dt-bindings/clock/qcom,rpmh.h>
9#include <dt-bindings/clock/qcom,sm8450-camcc.h>
10#include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11#include <dt-bindings/clock/qcom,sm8450-gpucc.h>
12#include <dt-bindings/clock/qcom,sm8450-videocc.h>
13#include <dt-bindings/dma/qcom-gpi.h>
14#include <dt-bindings/firmware/qcom,scm.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/mailbox/qcom-ipcc.h>
17#include <dt-bindings/phy/phy-qcom-qmp.h>
18#include <dt-bindings/power/qcom,rpmhpd.h>
19#include <dt-bindings/power/qcom-rpmpd.h>
20#include <dt-bindings/interconnect/qcom,icc.h>
21#include <dt-bindings/interconnect/qcom,sm8450.h>
22#include <dt-bindings/reset/qcom,sm8450-gpucc.h>
23#include <dt-bindings/soc/qcom,gpr.h>
24#include <dt-bindings/soc/qcom,rpmh-rsc.h>
25#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
26#include <dt-bindings/thermal/thermal.h>
27
28/ {
29	interrupt-parent = <&intc>;
30
31	#address-cells = <2>;
32	#size-cells = <2>;
33
34	chosen { };
35
36	clocks {
37		xo_board: xo-board {
38			compatible = "fixed-clock";
39			#clock-cells = <0>;
40			clock-frequency = <76800000>;
41		};
42
43		sleep_clk: sleep-clk {
44			compatible = "fixed-clock";
45			#clock-cells = <0>;
46			clock-frequency = <32000>;
47		};
48	};
49
50	cpus {
51		#address-cells = <2>;
52		#size-cells = <0>;
53
54		CPU0: cpu@0 {
55			device_type = "cpu";
56			compatible = "qcom,kryo780";
57			reg = <0x0 0x0>;
58			enable-method = "psci";
59			next-level-cache = <&L2_0>;
60			power-domains = <&CPU_PD0>;
61			power-domain-names = "psci";
62			qcom,freq-domain = <&cpufreq_hw 0>;
63			#cooling-cells = <2>;
64			clocks = <&cpufreq_hw 0>;
65			L2_0: l2-cache {
66				compatible = "cache";
67				cache-level = <2>;
68				cache-unified;
69				next-level-cache = <&L3_0>;
70				L3_0: l3-cache {
71					compatible = "cache";
72					cache-level = <3>;
73					cache-unified;
74				};
75			};
76		};
77
78		CPU1: cpu@100 {
79			device_type = "cpu";
80			compatible = "qcom,kryo780";
81			reg = <0x0 0x100>;
82			enable-method = "psci";
83			next-level-cache = <&L2_100>;
84			power-domains = <&CPU_PD1>;
85			power-domain-names = "psci";
86			qcom,freq-domain = <&cpufreq_hw 0>;
87			#cooling-cells = <2>;
88			clocks = <&cpufreq_hw 0>;
89			L2_100: l2-cache {
90				compatible = "cache";
91				cache-level = <2>;
92				cache-unified;
93				next-level-cache = <&L3_0>;
94			};
95		};
96
97		CPU2: cpu@200 {
98			device_type = "cpu";
99			compatible = "qcom,kryo780";
100			reg = <0x0 0x200>;
101			enable-method = "psci";
102			next-level-cache = <&L2_200>;
103			power-domains = <&CPU_PD2>;
104			power-domain-names = "psci";
105			qcom,freq-domain = <&cpufreq_hw 0>;
106			#cooling-cells = <2>;
107			clocks = <&cpufreq_hw 0>;
108			L2_200: l2-cache {
109				compatible = "cache";
110				cache-level = <2>;
111				cache-unified;
112				next-level-cache = <&L3_0>;
113			};
114		};
115
116		CPU3: cpu@300 {
117			device_type = "cpu";
118			compatible = "qcom,kryo780";
119			reg = <0x0 0x300>;
120			enable-method = "psci";
121			next-level-cache = <&L2_300>;
122			power-domains = <&CPU_PD3>;
123			power-domain-names = "psci";
124			qcom,freq-domain = <&cpufreq_hw 0>;
125			#cooling-cells = <2>;
126			clocks = <&cpufreq_hw 0>;
127			L2_300: l2-cache {
128				compatible = "cache";
129				cache-level = <2>;
130				cache-unified;
131				next-level-cache = <&L3_0>;
132			};
133		};
134
135		CPU4: cpu@400 {
136			device_type = "cpu";
137			compatible = "qcom,kryo780";
138			reg = <0x0 0x400>;
139			enable-method = "psci";
140			next-level-cache = <&L2_400>;
141			power-domains = <&CPU_PD4>;
142			power-domain-names = "psci";
143			qcom,freq-domain = <&cpufreq_hw 1>;
144			#cooling-cells = <2>;
145			clocks = <&cpufreq_hw 1>;
146			L2_400: l2-cache {
147				compatible = "cache";
148				cache-level = <2>;
149				cache-unified;
150				next-level-cache = <&L3_0>;
151			};
152		};
153
154		CPU5: cpu@500 {
155			device_type = "cpu";
156			compatible = "qcom,kryo780";
157			reg = <0x0 0x500>;
158			enable-method = "psci";
159			next-level-cache = <&L2_500>;
160			power-domains = <&CPU_PD5>;
161			power-domain-names = "psci";
162			qcom,freq-domain = <&cpufreq_hw 1>;
163			#cooling-cells = <2>;
164			clocks = <&cpufreq_hw 1>;
165			L2_500: l2-cache {
166				compatible = "cache";
167				cache-level = <2>;
168				cache-unified;
169				next-level-cache = <&L3_0>;
170			};
171		};
172
173		CPU6: cpu@600 {
174			device_type = "cpu";
175			compatible = "qcom,kryo780";
176			reg = <0x0 0x600>;
177			enable-method = "psci";
178			next-level-cache = <&L2_600>;
179			power-domains = <&CPU_PD6>;
180			power-domain-names = "psci";
181			qcom,freq-domain = <&cpufreq_hw 1>;
182			#cooling-cells = <2>;
183			clocks = <&cpufreq_hw 1>;
184			L2_600: l2-cache {
185				compatible = "cache";
186				cache-level = <2>;
187				cache-unified;
188				next-level-cache = <&L3_0>;
189			};
190		};
191
192		CPU7: cpu@700 {
193			device_type = "cpu";
194			compatible = "qcom,kryo780";
195			reg = <0x0 0x700>;
196			enable-method = "psci";
197			next-level-cache = <&L2_700>;
198			power-domains = <&CPU_PD7>;
199			power-domain-names = "psci";
200			qcom,freq-domain = <&cpufreq_hw 2>;
201			#cooling-cells = <2>;
202			clocks = <&cpufreq_hw 2>;
203			L2_700: l2-cache {
204				compatible = "cache";
205				cache-level = <2>;
206				cache-unified;
207				next-level-cache = <&L3_0>;
208			};
209		};
210
211		cpu-map {
212			cluster0 {
213				core0 {
214					cpu = <&CPU0>;
215				};
216
217				core1 {
218					cpu = <&CPU1>;
219				};
220
221				core2 {
222					cpu = <&CPU2>;
223				};
224
225				core3 {
226					cpu = <&CPU3>;
227				};
228
229				core4 {
230					cpu = <&CPU4>;
231				};
232
233				core5 {
234					cpu = <&CPU5>;
235				};
236
237				core6 {
238					cpu = <&CPU6>;
239				};
240
241				core7 {
242					cpu = <&CPU7>;
243				};
244			};
245		};
246
247		idle-states {
248			entry-method = "psci";
249
250			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
251				compatible = "arm,idle-state";
252				idle-state-name = "silver-rail-power-collapse";
253				arm,psci-suspend-param = <0x40000004>;
254				entry-latency-us = <800>;
255				exit-latency-us = <750>;
256				min-residency-us = <4090>;
257				local-timer-stop;
258			};
259
260			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
261				compatible = "arm,idle-state";
262				idle-state-name = "gold-rail-power-collapse";
263				arm,psci-suspend-param = <0x40000004>;
264				entry-latency-us = <600>;
265				exit-latency-us = <1550>;
266				min-residency-us = <4791>;
267				local-timer-stop;
268			};
269		};
270
271		domain-idle-states {
272			CLUSTER_SLEEP_0: cluster-sleep-0 {
273				compatible = "domain-idle-state";
274				arm,psci-suspend-param = <0x41000044>;
275				entry-latency-us = <1050>;
276				exit-latency-us = <2500>;
277				min-residency-us = <5309>;
278			};
279
280			CLUSTER_SLEEP_1: cluster-sleep-1 {
281				compatible = "domain-idle-state";
282				arm,psci-suspend-param = <0x4100c344>;
283				entry-latency-us = <2700>;
284				exit-latency-us = <3500>;
285				min-residency-us = <13959>;
286			};
287		};
288	};
289
290	firmware {
291		scm: scm {
292			compatible = "qcom,scm-sm8450", "qcom,scm";
293			qcom,dload-mode = <&tcsr 0x13000>;
294			interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
295			#reset-cells = <1>;
296		};
297	};
298
299	clk_virt: interconnect-0 {
300		compatible = "qcom,sm8450-clk-virt";
301		#interconnect-cells = <2>;
302		qcom,bcm-voters = <&apps_bcm_voter>;
303	};
304
305	mc_virt: interconnect-1 {
306		compatible = "qcom,sm8450-mc-virt";
307		#interconnect-cells = <2>;
308		qcom,bcm-voters = <&apps_bcm_voter>;
309	};
310
311	memory@a0000000 {
312		device_type = "memory";
313		/* We expect the bootloader to fill in the size */
314		reg = <0x0 0xa0000000 0x0 0x0>;
315	};
316
317	pmu {
318		compatible = "arm,armv8-pmuv3";
319		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
320	};
321
322	psci {
323		compatible = "arm,psci-1.0";
324		method = "smc";
325
326		CPU_PD0: power-domain-cpu0 {
327			#power-domain-cells = <0>;
328			power-domains = <&CLUSTER_PD>;
329			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
330		};
331
332		CPU_PD1: power-domain-cpu1 {
333			#power-domain-cells = <0>;
334			power-domains = <&CLUSTER_PD>;
335			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
336		};
337
338		CPU_PD2: power-domain-cpu2 {
339			#power-domain-cells = <0>;
340			power-domains = <&CLUSTER_PD>;
341			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
342		};
343
344		CPU_PD3: power-domain-cpu3 {
345			#power-domain-cells = <0>;
346			power-domains = <&CLUSTER_PD>;
347			domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
348		};
349
350		CPU_PD4: power-domain-cpu4 {
351			#power-domain-cells = <0>;
352			power-domains = <&CLUSTER_PD>;
353			domain-idle-states = <&BIG_CPU_SLEEP_0>;
354		};
355
356		CPU_PD5: power-domain-cpu5 {
357			#power-domain-cells = <0>;
358			power-domains = <&CLUSTER_PD>;
359			domain-idle-states = <&BIG_CPU_SLEEP_0>;
360		};
361
362		CPU_PD6: power-domain-cpu6 {
363			#power-domain-cells = <0>;
364			power-domains = <&CLUSTER_PD>;
365			domain-idle-states = <&BIG_CPU_SLEEP_0>;
366		};
367
368		CPU_PD7: power-domain-cpu7 {
369			#power-domain-cells = <0>;
370			power-domains = <&CLUSTER_PD>;
371			domain-idle-states = <&BIG_CPU_SLEEP_0>;
372		};
373
374		CLUSTER_PD: power-domain-cpu-cluster0 {
375			#power-domain-cells = <0>;
376			domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
377		};
378	};
379
380	qup_opp_table_100mhz: opp-table-qup {
381		compatible = "operating-points-v2";
382
383		opp-50000000 {
384			opp-hz = /bits/ 64 <50000000>;
385			required-opps = <&rpmhpd_opp_min_svs>;
386		};
387
388		opp-75000000 {
389			opp-hz = /bits/ 64 <75000000>;
390			required-opps = <&rpmhpd_opp_low_svs>;
391		};
392
393		opp-100000000 {
394			opp-hz = /bits/ 64 <100000000>;
395			required-opps = <&rpmhpd_opp_svs>;
396		};
397	};
398
399	reserved_memory: reserved-memory {
400		#address-cells = <2>;
401		#size-cells = <2>;
402		ranges;
403
404		hyp_mem: memory@80000000 {
405			reg = <0x0 0x80000000 0x0 0x600000>;
406			no-map;
407		};
408
409		xbl_dt_log_mem: memory@80600000 {
410			reg = <0x0 0x80600000 0x0 0x40000>;
411			no-map;
412		};
413
414		xbl_ramdump_mem: memory@80640000 {
415			reg = <0x0 0x80640000 0x0 0x180000>;
416			no-map;
417		};
418
419		xbl_sc_mem: memory@807c0000 {
420			reg = <0x0 0x807c0000 0x0 0x40000>;
421			no-map;
422		};
423
424		aop_image_mem: memory@80800000 {
425			reg = <0x0 0x80800000 0x0 0x60000>;
426			no-map;
427		};
428
429		aop_cmd_db_mem: memory@80860000 {
430			compatible = "qcom,cmd-db";
431			reg = <0x0 0x80860000 0x0 0x20000>;
432			no-map;
433		};
434
435		aop_config_mem: memory@80880000 {
436			reg = <0x0 0x80880000 0x0 0x20000>;
437			no-map;
438		};
439
440		tme_crash_dump_mem: memory@808a0000 {
441			reg = <0x0 0x808a0000 0x0 0x40000>;
442			no-map;
443		};
444
445		tme_log_mem: memory@808e0000 {
446			reg = <0x0 0x808e0000 0x0 0x4000>;
447			no-map;
448		};
449
450		uefi_log_mem: memory@808e4000 {
451			reg = <0x0 0x808e4000 0x0 0x10000>;
452			no-map;
453		};
454
455		/* secdata region can be reused by apps */
456		smem: memory@80900000 {
457			compatible = "qcom,smem";
458			reg = <0x0 0x80900000 0x0 0x200000>;
459			hwlocks = <&tcsr_mutex 3>;
460			no-map;
461		};
462
463		cpucp_fw_mem: memory@80b00000 {
464			reg = <0x0 0x80b00000 0x0 0x100000>;
465			no-map;
466		};
467
468		cdsp_secure_heap: memory@80c00000 {
469			reg = <0x0 0x80c00000 0x0 0x4600000>;
470			no-map;
471		};
472
473		video_mem: memory@85700000 {
474			reg = <0x0 0x85700000 0x0 0x700000>;
475			no-map;
476		};
477
478		adsp_mem: memory@85e00000 {
479			reg = <0x0 0x85e00000 0x0 0x2100000>;
480			no-map;
481		};
482
483		slpi_mem: memory@88000000 {
484			reg = <0x0 0x88000000 0x0 0x1900000>;
485			no-map;
486		};
487
488		cdsp_mem: memory@89900000 {
489			reg = <0x0 0x89900000 0x0 0x2000000>;
490			no-map;
491		};
492
493		ipa_fw_mem: memory@8b900000 {
494			reg = <0x0 0x8b900000 0x0 0x10000>;
495			no-map;
496		};
497
498		ipa_gsi_mem: memory@8b910000 {
499			reg = <0x0 0x8b910000 0x0 0xa000>;
500			no-map;
501		};
502
503		gpu_micro_code_mem: memory@8b91a000 {
504			reg = <0x0 0x8b91a000 0x0 0x2000>;
505			no-map;
506		};
507
508		spss_region_mem: memory@8ba00000 {
509			reg = <0x0 0x8ba00000 0x0 0x180000>;
510			no-map;
511		};
512
513		/* First part of the "SPU secure shared memory" region */
514		spu_tz_shared_mem: memory@8bb80000 {
515			reg = <0x0 0x8bb80000 0x0 0x60000>;
516			no-map;
517		};
518
519		/* Second part of the "SPU secure shared memory" region */
520		spu_modem_shared_mem: memory@8bbe0000 {
521			reg = <0x0 0x8bbe0000 0x0 0x20000>;
522			no-map;
523		};
524
525		mpss_mem: memory@8bc00000 {
526			reg = <0x0 0x8bc00000 0x0 0x13200000>;
527			no-map;
528		};
529
530		cvp_mem: memory@9ee00000 {
531			reg = <0x0 0x9ee00000 0x0 0x700000>;
532			no-map;
533		};
534
535		camera_mem: memory@9f500000 {
536			reg = <0x0 0x9f500000 0x0 0x800000>;
537			no-map;
538		};
539
540		rmtfs_mem: memory@9fd00000 {
541			compatible = "qcom,rmtfs-mem";
542			reg = <0x0 0x9fd00000 0x0 0x280000>;
543			no-map;
544
545			qcom,client-id = <1>;
546			qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
547		};
548
549		xbl_sc_mem2: memory@a6e00000 {
550			reg = <0x0 0xa6e00000 0x0 0x40000>;
551			no-map;
552		};
553
554		global_sync_mem: memory@a6f00000 {
555			reg = <0x0 0xa6f00000 0x0 0x100000>;
556			no-map;
557		};
558
559		/* uefi region can be reused by APPS */
560
561		/* Linux kernel image is loaded at 0xa0000000 */
562
563		oem_vm_mem: memory@bb000000 {
564			reg = <0x0 0xbb000000 0x0 0x5000000>;
565			no-map;
566		};
567
568		mte_mem: memory@c0000000 {
569			reg = <0x0 0xc0000000 0x0 0x20000000>;
570			no-map;
571		};
572
573		qheebsp_reserved_mem: memory@e0000000 {
574			reg = <0x0 0xe0000000 0x0 0x600000>;
575			no-map;
576		};
577
578		cpusys_vm_mem: memory@e0600000 {
579			reg = <0x0 0xe0600000 0x0 0x400000>;
580			no-map;
581		};
582
583		hyp_reserved_mem: memory@e0a00000 {
584			reg = <0x0 0xe0a00000 0x0 0x100000>;
585			no-map;
586		};
587
588		trust_ui_vm_mem: memory@e0b00000 {
589			reg = <0x0 0xe0b00000 0x0 0x4af3000>;
590			no-map;
591		};
592
593		trust_ui_vm_qrtr: memory@e55f3000 {
594			reg = <0x0 0xe55f3000 0x0 0x9000>;
595			no-map;
596		};
597
598		trust_ui_vm_vblk0_ring: memory@e55fc000 {
599			reg = <0x0 0xe55fc000 0x0 0x4000>;
600			no-map;
601		};
602
603		trust_ui_vm_swiotlb: memory@e5600000 {
604			reg = <0x0 0xe5600000 0x0 0x100000>;
605			no-map;
606		};
607
608		tz_stat_mem: memory@e8800000 {
609			reg = <0x0 0xe8800000 0x0 0x100000>;
610			no-map;
611		};
612
613		tags_mem: memory@e8900000 {
614			reg = <0x0 0xe8900000 0x0 0x1200000>;
615			no-map;
616		};
617
618		qtee_mem: memory@e9b00000 {
619			reg = <0x0 0xe9b00000 0x0 0x500000>;
620			no-map;
621		};
622
623		trusted_apps_mem: memory@ea000000 {
624			reg = <0x0 0xea000000 0x0 0x3900000>;
625			no-map;
626		};
627
628		trusted_apps_ext_mem: memory@ed900000 {
629			reg = <0x0 0xed900000 0x0 0x3b00000>;
630			no-map;
631		};
632	};
633
634	smp2p-adsp {
635		compatible = "qcom,smp2p";
636		qcom,smem = <443>, <429>;
637		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
638					     IPCC_MPROC_SIGNAL_SMP2P
639					     IRQ_TYPE_EDGE_RISING>;
640		mboxes = <&ipcc IPCC_CLIENT_LPASS
641				IPCC_MPROC_SIGNAL_SMP2P>;
642
643		qcom,local-pid = <0>;
644		qcom,remote-pid = <2>;
645
646		smp2p_adsp_out: master-kernel {
647			qcom,entry-name = "master-kernel";
648			#qcom,smem-state-cells = <1>;
649		};
650
651		smp2p_adsp_in: slave-kernel {
652			qcom,entry-name = "slave-kernel";
653			interrupt-controller;
654			#interrupt-cells = <2>;
655		};
656	};
657
658	smp2p-cdsp {
659		compatible = "qcom,smp2p";
660		qcom,smem = <94>, <432>;
661		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
662					     IPCC_MPROC_SIGNAL_SMP2P
663					     IRQ_TYPE_EDGE_RISING>;
664		mboxes = <&ipcc IPCC_CLIENT_CDSP
665				IPCC_MPROC_SIGNAL_SMP2P>;
666
667		qcom,local-pid = <0>;
668		qcom,remote-pid = <5>;
669
670		smp2p_cdsp_out: master-kernel {
671			qcom,entry-name = "master-kernel";
672			#qcom,smem-state-cells = <1>;
673		};
674
675		smp2p_cdsp_in: slave-kernel {
676			qcom,entry-name = "slave-kernel";
677			interrupt-controller;
678			#interrupt-cells = <2>;
679		};
680	};
681
682	smp2p-modem {
683		compatible = "qcom,smp2p";
684		qcom,smem = <435>, <428>;
685		interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
686					     IPCC_MPROC_SIGNAL_SMP2P
687					     IRQ_TYPE_EDGE_RISING>;
688		mboxes = <&ipcc IPCC_CLIENT_MPSS
689				IPCC_MPROC_SIGNAL_SMP2P>;
690
691		qcom,local-pid = <0>;
692		qcom,remote-pid = <1>;
693
694		smp2p_modem_out: master-kernel {
695			qcom,entry-name = "master-kernel";
696			#qcom,smem-state-cells = <1>;
697		};
698
699		smp2p_modem_in: slave-kernel {
700			qcom,entry-name = "slave-kernel";
701			interrupt-controller;
702			#interrupt-cells = <2>;
703		};
704
705		ipa_smp2p_out: ipa-ap-to-modem {
706			qcom,entry-name = "ipa";
707			#qcom,smem-state-cells = <1>;
708		};
709
710		ipa_smp2p_in: ipa-modem-to-ap {
711			qcom,entry-name = "ipa";
712			interrupt-controller;
713			#interrupt-cells = <2>;
714		};
715	};
716
717	smp2p-slpi {
718		compatible = "qcom,smp2p";
719		qcom,smem = <481>, <430>;
720		interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
721					     IPCC_MPROC_SIGNAL_SMP2P
722					     IRQ_TYPE_EDGE_RISING>;
723		mboxes = <&ipcc IPCC_CLIENT_SLPI
724				IPCC_MPROC_SIGNAL_SMP2P>;
725
726		qcom,local-pid = <0>;
727		qcom,remote-pid = <3>;
728
729		smp2p_slpi_out: master-kernel {
730			qcom,entry-name = "master-kernel";
731			#qcom,smem-state-cells = <1>;
732		};
733
734		smp2p_slpi_in: slave-kernel {
735			qcom,entry-name = "slave-kernel";
736			interrupt-controller;
737			#interrupt-cells = <2>;
738		};
739	};
740
741	soc: soc@0 {
742		#address-cells = <2>;
743		#size-cells = <2>;
744		ranges = <0 0 0 0 0x10 0>;
745		dma-ranges = <0 0 0 0 0x10 0>;
746		compatible = "simple-bus";
747
748		gcc: clock-controller@100000 {
749			compatible = "qcom,gcc-sm8450";
750			reg = <0x0 0x00100000 0x0 0x1f4200>;
751			#clock-cells = <1>;
752			#reset-cells = <1>;
753			#power-domain-cells = <1>;
754			clocks = <&rpmhcc RPMH_CXO_CLK>,
755				 <&sleep_clk>,
756				 <&pcie0_phy>,
757				 <&pcie1_phy>,
758				 <0>,
759				 <&ufs_mem_phy 0>,
760				 <&ufs_mem_phy 1>,
761				 <&ufs_mem_phy 2>,
762				 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
763			clock-names = "bi_tcxo",
764				      "sleep_clk",
765				      "pcie_0_pipe_clk",
766				      "pcie_1_pipe_clk",
767				      "pcie_1_phy_aux_clk",
768				      "ufs_phy_rx_symbol_0_clk",
769				      "ufs_phy_rx_symbol_1_clk",
770				      "ufs_phy_tx_symbol_0_clk",
771				      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
772		};
773
774		gpi_dma2: dma-controller@800000 {
775			compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
776			#dma-cells = <3>;
777			reg = <0 0x00800000 0 0x60000>;
778			interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
779				     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
780				     <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
781				     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
782				     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
783				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
784				     <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
785				     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
786				     <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
787				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
788				     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
789				     <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
790			dma-channels = <12>;
791			dma-channel-mask = <0x7e>;
792			iommus = <&apps_smmu 0x496 0x0>;
793			status = "disabled";
794		};
795
796		qupv3_id_2: geniqup@8c0000 {
797			compatible = "qcom,geni-se-qup";
798			reg = <0x0 0x008c0000 0x0 0x2000>;
799			clock-names = "m-ahb", "s-ahb";
800			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
801				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
802			iommus = <&apps_smmu 0x483 0x0>;
803			#address-cells = <2>;
804			#size-cells = <2>;
805			ranges;
806			status = "disabled";
807
808			i2c15: i2c@880000 {
809				compatible = "qcom,geni-i2c";
810				reg = <0x0 0x00880000 0x0 0x4000>;
811				clock-names = "se";
812				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
813				pinctrl-names = "default";
814				pinctrl-0 = <&qup_i2c15_data_clk>;
815				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
816				#address-cells = <1>;
817				#size-cells = <0>;
818				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
819						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
820						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
821				interconnect-names = "qup-core", "qup-config", "qup-memory";
822				dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
823				       <&gpi_dma2 1 0 QCOM_GPI_I2C>;
824				dma-names = "tx", "rx";
825				status = "disabled";
826			};
827
828			spi15: spi@880000 {
829				compatible = "qcom,geni-spi";
830				reg = <0x0 0x00880000 0x0 0x4000>;
831				clock-names = "se";
832				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
833				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
834				pinctrl-names = "default";
835				pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
836				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
837						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
838				interconnect-names = "qup-core", "qup-config";
839				dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
840				       <&gpi_dma2 1 0 QCOM_GPI_SPI>;
841				dma-names = "tx", "rx";
842				#address-cells = <1>;
843				#size-cells = <0>;
844				status = "disabled";
845			};
846
847			i2c16: i2c@884000 {
848				compatible = "qcom,geni-i2c";
849				reg = <0x0 0x00884000 0x0 0x4000>;
850				clock-names = "se";
851				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
852				pinctrl-names = "default";
853				pinctrl-0 = <&qup_i2c16_data_clk>;
854				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
855				#address-cells = <1>;
856				#size-cells = <0>;
857				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
858						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
859						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
860				interconnect-names = "qup-core", "qup-config", "qup-memory";
861				dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
862				       <&gpi_dma2 1 1 QCOM_GPI_I2C>;
863				dma-names = "tx", "rx";
864				status = "disabled";
865			};
866
867			spi16: spi@884000 {
868				compatible = "qcom,geni-spi";
869				reg = <0x0 0x00884000 0x0 0x4000>;
870				clock-names = "se";
871				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
872				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
873				pinctrl-names = "default";
874				pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
875				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
876						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
877				interconnect-names = "qup-core", "qup-config";
878				dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879				       <&gpi_dma2 1 1 QCOM_GPI_SPI>;
880				dma-names = "tx", "rx";
881				#address-cells = <1>;
882				#size-cells = <0>;
883				status = "disabled";
884			};
885
886			i2c17: i2c@888000 {
887				compatible = "qcom,geni-i2c";
888				reg = <0x0 0x00888000 0x0 0x4000>;
889				clock-names = "se";
890				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
891				pinctrl-names = "default";
892				pinctrl-0 = <&qup_i2c17_data_clk>;
893				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
894				#address-cells = <1>;
895				#size-cells = <0>;
896				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
897						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
898						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
899				interconnect-names = "qup-core", "qup-config", "qup-memory";
900				dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
901				       <&gpi_dma2 1 2 QCOM_GPI_I2C>;
902				dma-names = "tx", "rx";
903				status = "disabled";
904			};
905
906			spi17: spi@888000 {
907				compatible = "qcom,geni-spi";
908				reg = <0x0 0x00888000 0x0 0x4000>;
909				clock-names = "se";
910				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
911				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
912				pinctrl-names = "default";
913				pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
914				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
915						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
916				interconnect-names = "qup-core", "qup-config";
917				dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
918				       <&gpi_dma2 1 2 QCOM_GPI_SPI>;
919				dma-names = "tx", "rx";
920				#address-cells = <1>;
921				#size-cells = <0>;
922				status = "disabled";
923			};
924
925			i2c18: i2c@88c000 {
926				compatible = "qcom,geni-i2c";
927				reg = <0x0 0x0088c000 0x0 0x4000>;
928				clock-names = "se";
929				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
930				pinctrl-names = "default";
931				pinctrl-0 = <&qup_i2c18_data_clk>;
932				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
933				#address-cells = <1>;
934				#size-cells = <0>;
935				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
936						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
937						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
938				interconnect-names = "qup-core", "qup-config", "qup-memory";
939				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
940				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
941				dma-names = "tx", "rx";
942				status = "disabled";
943			};
944
945			spi18: spi@88c000 {
946				compatible = "qcom,geni-spi";
947				reg = <0 0x0088c000 0 0x4000>;
948				clock-names = "se";
949				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
950				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
951				pinctrl-names = "default";
952				pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
953				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
954						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
955				interconnect-names = "qup-core", "qup-config";
956				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
957				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
958				dma-names = "tx", "rx";
959				#address-cells = <1>;
960				#size-cells = <0>;
961				status = "disabled";
962			};
963
964			i2c19: i2c@890000 {
965				compatible = "qcom,geni-i2c";
966				reg = <0x0 0x00890000 0x0 0x4000>;
967				clock-names = "se";
968				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
969				pinctrl-names = "default";
970				pinctrl-0 = <&qup_i2c19_data_clk>;
971				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
972				#address-cells = <1>;
973				#size-cells = <0>;
974				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
975						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
976						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
977				interconnect-names = "qup-core", "qup-config", "qup-memory";
978				dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
979				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
980				dma-names = "tx", "rx";
981				status = "disabled";
982			};
983
984			spi19: spi@890000 {
985				compatible = "qcom,geni-spi";
986				reg = <0 0x00890000 0 0x4000>;
987				clock-names = "se";
988				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
989				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
990				pinctrl-names = "default";
991				pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
992				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
993						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
994				interconnect-names = "qup-core", "qup-config";
995				dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
996				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
997				dma-names = "tx", "rx";
998				#address-cells = <1>;
999				#size-cells = <0>;
1000				status = "disabled";
1001			};
1002
1003			i2c20: i2c@894000 {
1004				compatible = "qcom,geni-i2c";
1005				reg = <0x0 0x00894000 0x0 0x4000>;
1006				clock-names = "se";
1007				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1008				pinctrl-names = "default";
1009				pinctrl-0 = <&qup_i2c20_data_clk>;
1010				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1011				#address-cells = <1>;
1012				#size-cells = <0>;
1013				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1014						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1015						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1016				interconnect-names = "qup-core", "qup-config", "qup-memory";
1017				dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1018				       <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1019				dma-names = "tx", "rx";
1020				status = "disabled";
1021			};
1022
1023			uart20: serial@894000 {
1024				compatible = "qcom,geni-uart";
1025				reg = <0 0x00894000 0 0x4000>;
1026				clock-names = "se";
1027				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1028				pinctrl-names = "default";
1029				pinctrl-0 = <&qup_uart20_default>;
1030				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1031				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1032						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1033						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1034						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1035				interconnect-names = "qup-core",
1036						     "qup-config";
1037				status = "disabled";
1038			};
1039
1040			spi20: spi@894000 {
1041				compatible = "qcom,geni-spi";
1042				reg = <0 0x00894000 0 0x4000>;
1043				clock-names = "se";
1044				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1045				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1046				pinctrl-names = "default";
1047				pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1048				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1049						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1050				interconnect-names = "qup-core", "qup-config";
1051				dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1052				       <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1053				dma-names = "tx", "rx";
1054				#address-cells = <1>;
1055				#size-cells = <0>;
1056				status = "disabled";
1057			};
1058
1059			i2c21: i2c@898000 {
1060				compatible = "qcom,geni-i2c";
1061				reg = <0x0 0x00898000 0x0 0x4000>;
1062				clock-names = "se";
1063				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1064				pinctrl-names = "default";
1065				pinctrl-0 = <&qup_i2c21_data_clk>;
1066				interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1067				#address-cells = <1>;
1068				#size-cells = <0>;
1069				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1070						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1071						<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1072				interconnect-names = "qup-core", "qup-config", "qup-memory";
1073				dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1074				       <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1075				dma-names = "tx", "rx";
1076				status = "disabled";
1077			};
1078
1079			spi21: spi@898000 {
1080				compatible = "qcom,geni-spi";
1081				reg = <0 0x00898000 0 0x4000>;
1082				clock-names = "se";
1083				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1084				interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1085				pinctrl-names = "default";
1086				pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1087				interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1088						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1089				interconnect-names = "qup-core", "qup-config";
1090				dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1091				       <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1092				dma-names = "tx", "rx";
1093				#address-cells = <1>;
1094				#size-cells = <0>;
1095				status = "disabled";
1096			};
1097		};
1098
1099		gpi_dma0: dma-controller@900000 {
1100			compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1101			#dma-cells = <3>;
1102			reg = <0 0x00900000 0 0x60000>;
1103			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1104				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1105				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1106				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1107				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1108				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1109				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1110				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1111				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1112				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1113				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1114				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1115			dma-channels = <12>;
1116			dma-channel-mask = <0x7e>;
1117			iommus = <&apps_smmu 0x5b6 0x0>;
1118			status = "disabled";
1119		};
1120
1121		qupv3_id_0: geniqup@9c0000 {
1122			compatible = "qcom,geni-se-qup";
1123			reg = <0x0 0x009c0000 0x0 0x2000>;
1124			clock-names = "m-ahb", "s-ahb";
1125			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1126				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1127			iommus = <&apps_smmu 0x5a3 0x0>;
1128			interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1129			interconnect-names = "qup-core";
1130			#address-cells = <2>;
1131			#size-cells = <2>;
1132			ranges;
1133			status = "disabled";
1134
1135			i2c0: i2c@980000 {
1136				compatible = "qcom,geni-i2c";
1137				reg = <0x0 0x00980000 0x0 0x4000>;
1138				clock-names = "se";
1139				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1140				pinctrl-names = "default";
1141				pinctrl-0 = <&qup_i2c0_data_clk>;
1142				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1143				#address-cells = <1>;
1144				#size-cells = <0>;
1145				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1146						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1147						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1148				interconnect-names = "qup-core", "qup-config", "qup-memory";
1149				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1150				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1151				dma-names = "tx", "rx";
1152				status = "disabled";
1153			};
1154
1155			spi0: spi@980000 {
1156				compatible = "qcom,geni-spi";
1157				reg = <0x0 0x00980000 0x0 0x4000>;
1158				clock-names = "se";
1159				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1160				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1161				pinctrl-names = "default";
1162				pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1163				power-domains = <&rpmhpd RPMHPD_CX>;
1164				operating-points-v2 = <&qup_opp_table_100mhz>;
1165				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1166						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1167						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1168				interconnect-names = "qup-core", "qup-config", "qup-memory";
1169				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1170				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1171				dma-names = "tx", "rx";
1172				#address-cells = <1>;
1173				#size-cells = <0>;
1174				status = "disabled";
1175			};
1176
1177			i2c1: i2c@984000 {
1178				compatible = "qcom,geni-i2c";
1179				reg = <0x0 0x00984000 0x0 0x4000>;
1180				clock-names = "se";
1181				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1182				pinctrl-names = "default";
1183				pinctrl-0 = <&qup_i2c1_data_clk>;
1184				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1185				#address-cells = <1>;
1186				#size-cells = <0>;
1187				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1189						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1190				interconnect-names = "qup-core", "qup-config", "qup-memory";
1191				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1193				dma-names = "tx", "rx";
1194				status = "disabled";
1195			};
1196
1197			spi1: spi@984000 {
1198				compatible = "qcom,geni-spi";
1199				reg = <0x0 0x00984000 0x0 0x4000>;
1200				clock-names = "se";
1201				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1202				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1203				pinctrl-names = "default";
1204				pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1205				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1207						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208				interconnect-names = "qup-core", "qup-config", "qup-memory";
1209				dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210				       <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1211				dma-names = "tx", "rx";
1212				#address-cells = <1>;
1213				#size-cells = <0>;
1214				status = "disabled";
1215			};
1216
1217			i2c2: i2c@988000 {
1218				compatible = "qcom,geni-i2c";
1219				reg = <0x0 0x00988000 0x0 0x4000>;
1220				clock-names = "se";
1221				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1222				pinctrl-names = "default";
1223				pinctrl-0 = <&qup_i2c2_data_clk>;
1224				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1225				#address-cells = <1>;
1226				#size-cells = <0>;
1227				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230				interconnect-names = "qup-core", "qup-config", "qup-memory";
1231				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1232				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1233				dma-names = "tx", "rx";
1234				status = "disabled";
1235			};
1236
1237			spi2: spi@988000 {
1238				compatible = "qcom,geni-spi";
1239				reg = <0x0 0x00988000 0x0 0x4000>;
1240				clock-names = "se";
1241				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1242				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1243				pinctrl-names = "default";
1244				pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1245				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1248				interconnect-names = "qup-core", "qup-config", "qup-memory";
1249				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1250				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1251				dma-names = "tx", "rx";
1252				#address-cells = <1>;
1253				#size-cells = <0>;
1254				status = "disabled";
1255			};
1256
1257
1258			i2c3: i2c@98c000 {
1259				compatible = "qcom,geni-i2c";
1260				reg = <0x0 0x0098c000 0x0 0x4000>;
1261				clock-names = "se";
1262				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1263				pinctrl-names = "default";
1264				pinctrl-0 = <&qup_i2c3_data_clk>;
1265				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1266				#address-cells = <1>;
1267				#size-cells = <0>;
1268				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1270						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1271				interconnect-names = "qup-core", "qup-config", "qup-memory";
1272				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1273				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1274				dma-names = "tx", "rx";
1275				status = "disabled";
1276			};
1277
1278			spi3: spi@98c000 {
1279				compatible = "qcom,geni-spi";
1280				reg = <0x0 0x0098c000 0x0 0x4000>;
1281				clock-names = "se";
1282				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1283				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1284				pinctrl-names = "default";
1285				pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1286				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1287						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1288						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1289				interconnect-names = "qup-core", "qup-config", "qup-memory";
1290				dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1291				       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1292				dma-names = "tx", "rx";
1293				#address-cells = <1>;
1294				#size-cells = <0>;
1295				status = "disabled";
1296			};
1297
1298			i2c4: i2c@990000 {
1299				compatible = "qcom,geni-i2c";
1300				reg = <0x0 0x00990000 0x0 0x4000>;
1301				clock-names = "se";
1302				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1303				pinctrl-names = "default";
1304				pinctrl-0 = <&qup_i2c4_data_clk>;
1305				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1306				#address-cells = <1>;
1307				#size-cells = <0>;
1308				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1309						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1310						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1311				interconnect-names = "qup-core", "qup-config", "qup-memory";
1312				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1313				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1314				dma-names = "tx", "rx";
1315				status = "disabled";
1316			};
1317
1318			spi4: spi@990000 {
1319				compatible = "qcom,geni-spi";
1320				reg = <0x0 0x00990000 0x0 0x4000>;
1321				clock-names = "se";
1322				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1323				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1324				pinctrl-names = "default";
1325				pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1326				power-domains = <&rpmhpd RPMHPD_CX>;
1327				operating-points-v2 = <&qup_opp_table_100mhz>;
1328				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1329						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1330						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1331				interconnect-names = "qup-core", "qup-config", "qup-memory";
1332				dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1333				       <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1334				dma-names = "tx", "rx";
1335				#address-cells = <1>;
1336				#size-cells = <0>;
1337				status = "disabled";
1338			};
1339
1340			i2c5: i2c@994000 {
1341				compatible = "qcom,geni-i2c";
1342				reg = <0x0 0x00994000 0x0 0x4000>;
1343				clock-names = "se";
1344				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345				pinctrl-names = "default";
1346				pinctrl-0 = <&qup_i2c5_data_clk>;
1347				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1348				#address-cells = <1>;
1349				#size-cells = <0>;
1350				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353				interconnect-names = "qup-core", "qup-config", "qup-memory";
1354				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1355				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1356				dma-names = "tx", "rx";
1357				status = "disabled";
1358			};
1359
1360			spi5: spi@994000 {
1361				compatible = "qcom,geni-spi";
1362				reg = <0x0 0x00994000 0x0 0x4000>;
1363				clock-names = "se";
1364				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1365				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1366				pinctrl-names = "default";
1367				pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1368				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371				interconnect-names = "qup-core", "qup-config", "qup-memory";
1372				dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1373				       <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1374				dma-names = "tx", "rx";
1375				#address-cells = <1>;
1376				#size-cells = <0>;
1377				status = "disabled";
1378			};
1379
1380
1381			i2c6: i2c@998000 {
1382				compatible = "qcom,geni-i2c";
1383				reg = <0x0 0x00998000 0x0 0x4000>;
1384				clock-names = "se";
1385				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1386				pinctrl-names = "default";
1387				pinctrl-0 = <&qup_i2c6_data_clk>;
1388				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1389				#address-cells = <1>;
1390				#size-cells = <0>;
1391				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1392						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1393						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1394				interconnect-names = "qup-core", "qup-config", "qup-memory";
1395				dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1396				       <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1397				dma-names = "tx", "rx";
1398				status = "disabled";
1399			};
1400
1401			spi6: spi@998000 {
1402				compatible = "qcom,geni-spi";
1403				reg = <0x0 0x00998000 0x0 0x4000>;
1404				clock-names = "se";
1405				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1406				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1407				pinctrl-names = "default";
1408				pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1409				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1410						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1411						<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1412				interconnect-names = "qup-core", "qup-config", "qup-memory";
1413				dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1414				       <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1415				dma-names = "tx", "rx";
1416				#address-cells = <1>;
1417				#size-cells = <0>;
1418				status = "disabled";
1419			};
1420
1421			uart7: serial@99c000 {
1422				compatible = "qcom,geni-debug-uart";
1423				reg = <0 0x0099c000 0 0x4000>;
1424				clock-names = "se";
1425				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1426				pinctrl-names = "default";
1427				pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1428				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1429				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1430						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1431						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1432						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
1433				interconnect-names = "qup-core",
1434						     "qup-config";
1435				status = "disabled";
1436			};
1437		};
1438
1439		gpi_dma1: dma-controller@a00000 {
1440			compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1441			#dma-cells = <3>;
1442			reg = <0 0x00a00000 0 0x60000>;
1443			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1444				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1445				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1446				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1447				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1448				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1449				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1450				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1451				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1452				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1453				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1454				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1455			dma-channels = <12>;
1456			dma-channel-mask = <0x7e>;
1457			iommus = <&apps_smmu 0x56 0x0>;
1458			status = "disabled";
1459		};
1460
1461		qupv3_id_1: geniqup@ac0000 {
1462			compatible = "qcom,geni-se-qup";
1463			reg = <0x0 0x00ac0000 0x0 0x6000>;
1464			clock-names = "m-ahb", "s-ahb";
1465			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1466				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1467			iommus = <&apps_smmu 0x43 0x0>;
1468			interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1469			interconnect-names = "qup-core";
1470			#address-cells = <2>;
1471			#size-cells = <2>;
1472			ranges;
1473			status = "disabled";
1474
1475			i2c8: i2c@a80000 {
1476				compatible = "qcom,geni-i2c";
1477				reg = <0x0 0x00a80000 0x0 0x4000>;
1478				clock-names = "se";
1479				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1480				pinctrl-names = "default";
1481				pinctrl-0 = <&qup_i2c8_data_clk>;
1482				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1483				#address-cells = <1>;
1484				#size-cells = <0>;
1485				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1487						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1488				interconnect-names = "qup-core", "qup-config", "qup-memory";
1489				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1490				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1491				dma-names = "tx", "rx";
1492				status = "disabled";
1493			};
1494
1495			spi8: spi@a80000 {
1496				compatible = "qcom,geni-spi";
1497				reg = <0x0 0x00a80000 0x0 0x4000>;
1498				clock-names = "se";
1499				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1500				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1501				pinctrl-names = "default";
1502				pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1503				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1505						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1506				interconnect-names = "qup-core", "qup-config", "qup-memory";
1507				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1508				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1509				dma-names = "tx", "rx";
1510				#address-cells = <1>;
1511				#size-cells = <0>;
1512				status = "disabled";
1513			};
1514
1515			i2c9: i2c@a84000 {
1516				compatible = "qcom,geni-i2c";
1517				reg = <0x0 0x00a84000 0x0 0x4000>;
1518				clock-names = "se";
1519				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1520				pinctrl-names = "default";
1521				pinctrl-0 = <&qup_i2c9_data_clk>;
1522				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1523				#address-cells = <1>;
1524				#size-cells = <0>;
1525				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1526						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1527						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1528				interconnect-names = "qup-core", "qup-config", "qup-memory";
1529				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1531				dma-names = "tx", "rx";
1532				status = "disabled";
1533			};
1534
1535			spi9: spi@a84000 {
1536				compatible = "qcom,geni-spi";
1537				reg = <0x0 0x00a84000 0x0 0x4000>;
1538				clock-names = "se";
1539				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1540				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1541				pinctrl-names = "default";
1542				pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1543				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1545						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1546				interconnect-names = "qup-core", "qup-config", "qup-memory";
1547				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1549				dma-names = "tx", "rx";
1550				#address-cells = <1>;
1551				#size-cells = <0>;
1552				status = "disabled";
1553			};
1554
1555			i2c10: i2c@a88000 {
1556				compatible = "qcom,geni-i2c";
1557				reg = <0x0 0x00a88000 0x0 0x4000>;
1558				clock-names = "se";
1559				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1560				pinctrl-names = "default";
1561				pinctrl-0 = <&qup_i2c10_data_clk>;
1562				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1563				#address-cells = <1>;
1564				#size-cells = <0>;
1565				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1567						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1568				interconnect-names = "qup-core", "qup-config", "qup-memory";
1569				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1570				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1571				dma-names = "tx", "rx";
1572				status = "disabled";
1573			};
1574
1575			spi10: spi@a88000 {
1576				compatible = "qcom,geni-spi";
1577				reg = <0x0 0x00a88000 0x0 0x4000>;
1578				clock-names = "se";
1579				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1580				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581				pinctrl-names = "default";
1582				pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1583				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1585						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586				interconnect-names = "qup-core", "qup-config", "qup-memory";
1587				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1588				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1589				dma-names = "tx", "rx";
1590				#address-cells = <1>;
1591				#size-cells = <0>;
1592				status = "disabled";
1593			};
1594
1595			i2c11: i2c@a8c000 {
1596				compatible = "qcom,geni-i2c";
1597				reg = <0x0 0x00a8c000 0x0 0x4000>;
1598				clock-names = "se";
1599				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1600				pinctrl-names = "default";
1601				pinctrl-0 = <&qup_i2c11_data_clk>;
1602				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1603				#address-cells = <1>;
1604				#size-cells = <0>;
1605				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1607						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1608				interconnect-names = "qup-core", "qup-config", "qup-memory";
1609				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1610				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1611				dma-names = "tx", "rx";
1612				status = "disabled";
1613			};
1614
1615			spi11: spi@a8c000 {
1616				compatible = "qcom,geni-spi";
1617				reg = <0x0 0x00a8c000 0x0 0x4000>;
1618				clock-names = "se";
1619				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1620				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1621				pinctrl-names = "default";
1622				pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1623				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1625						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1626				interconnect-names = "qup-core", "qup-config", "qup-memory";
1627				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1628				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1629				dma-names = "tx", "rx";
1630				#address-cells = <1>;
1631				#size-cells = <0>;
1632				status = "disabled";
1633			};
1634
1635			i2c12: i2c@a90000 {
1636				compatible = "qcom,geni-i2c";
1637				reg = <0x0 0x00a90000 0x0 0x4000>;
1638				clock-names = "se";
1639				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1640				pinctrl-names = "default";
1641				pinctrl-0 = <&qup_i2c12_data_clk>;
1642				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1643				#address-cells = <1>;
1644				#size-cells = <0>;
1645				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1646						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1647						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1648				interconnect-names = "qup-core", "qup-config", "qup-memory";
1649				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1650				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1651				dma-names = "tx", "rx";
1652				status = "disabled";
1653			};
1654
1655			spi12: spi@a90000 {
1656				compatible = "qcom,geni-spi";
1657				reg = <0x0 0x00a90000 0x0 0x4000>;
1658				clock-names = "se";
1659				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1660				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1661				pinctrl-names = "default";
1662				pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1663				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1665						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1666				interconnect-names = "qup-core", "qup-config", "qup-memory";
1667				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1668				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1669				dma-names = "tx", "rx";
1670				#address-cells = <1>;
1671				#size-cells = <0>;
1672				status = "disabled";
1673			};
1674
1675			i2c13: i2c@a94000 {
1676				compatible = "qcom,geni-i2c";
1677				reg = <0 0x00a94000 0 0x4000>;
1678				clock-names = "se";
1679				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1680				pinctrl-names = "default";
1681				pinctrl-0 = <&qup_i2c13_data_clk>;
1682				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1683				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1685						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1686				interconnect-names = "qup-core", "qup-config", "qup-memory";
1687				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1688				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1689				dma-names = "tx", "rx";
1690				#address-cells = <1>;
1691				#size-cells = <0>;
1692				status = "disabled";
1693			};
1694
1695			spi13: spi@a94000 {
1696				compatible = "qcom,geni-spi";
1697				reg = <0x0 0x00a94000 0x0 0x4000>;
1698				clock-names = "se";
1699				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1700				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1701				pinctrl-names = "default";
1702				pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1703				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1704						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1705						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706				interconnect-names = "qup-core", "qup-config", "qup-memory";
1707				dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1708				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1709				dma-names = "tx", "rx";
1710				#address-cells = <1>;
1711				#size-cells = <0>;
1712				status = "disabled";
1713			};
1714
1715			i2c14: i2c@a98000 {
1716				compatible = "qcom,geni-i2c";
1717				reg = <0 0x00a98000 0 0x4000>;
1718				clock-names = "se";
1719				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1720				pinctrl-names = "default";
1721				pinctrl-0 = <&qup_i2c14_data_clk>;
1722				interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1723				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1724						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1725						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1726				interconnect-names = "qup-core", "qup-config", "qup-memory";
1727				dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1728				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1729				dma-names = "tx", "rx";
1730				#address-cells = <1>;
1731				#size-cells = <0>;
1732				status = "disabled";
1733			};
1734
1735			spi14: spi@a98000 {
1736				compatible = "qcom,geni-spi";
1737				reg = <0x0 0x00a98000 0x0 0x4000>;
1738				clock-names = "se";
1739				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1740				interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1741				pinctrl-names = "default";
1742				pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1743				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744						<&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1745						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1746				interconnect-names = "qup-core", "qup-config", "qup-memory";
1747				dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1748				       <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1749				dma-names = "tx", "rx";
1750				#address-cells = <1>;
1751				#size-cells = <0>;
1752				status = "disabled";
1753			};
1754		};
1755
1756		rng: rng@10c3000 {
1757			compatible = "qcom,sm8450-trng", "qcom,trng";
1758			reg = <0 0x010c3000 0 0x1000>;
1759		};
1760
1761		pcie0: pcie@1c00000 {
1762			compatible = "qcom,pcie-sm8450-pcie0";
1763			reg = <0 0x01c00000 0 0x3000>,
1764			      <0 0x60000000 0 0xf1d>,
1765			      <0 0x60000f20 0 0xa8>,
1766			      <0 0x60001000 0 0x1000>,
1767			      <0 0x60100000 0 0x100000>;
1768			reg-names = "parf", "dbi", "elbi", "atu", "config";
1769			device_type = "pci";
1770			linux,pci-domain = <0>;
1771			bus-range = <0x00 0xff>;
1772			num-lanes = <1>;
1773
1774			#address-cells = <3>;
1775			#size-cells = <2>;
1776
1777			ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1778				 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1779
1780			msi-map = <0x0 &gic_its 0x5980 0x1>,
1781				  <0x100 &gic_its 0x5981 0x1>;
1782			msi-map-mask = <0xff00>;
1783			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1784				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1785				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1786				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1787				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1788				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1789				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1790				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1791			interrupt-names = "msi0",
1792					  "msi1",
1793					  "msi2",
1794					  "msi3",
1795					  "msi4",
1796					  "msi5",
1797					  "msi6",
1798					  "msi7";
1799			#interrupt-cells = <1>;
1800			interrupt-map-mask = <0 0 0 0x7>;
1801			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1802					<0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1803					<0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1804					<0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1805
1806			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1807				 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1808				 <&pcie0_phy>,
1809				 <&rpmhcc RPMH_CXO_CLK>,
1810				 <&gcc GCC_PCIE_0_AUX_CLK>,
1811				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1812				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1813				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1814				 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1815				 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1816				 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1817				 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1818			clock-names = "pipe",
1819				      "pipe_mux",
1820				      "phy_pipe",
1821				      "ref",
1822				      "aux",
1823				      "cfg",
1824				      "bus_master",
1825				      "bus_slave",
1826				      "slave_q2a",
1827				      "ddrss_sf_tbu",
1828				      "aggre0",
1829				      "aggre1";
1830
1831			iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1832				    <0x100 &apps_smmu 0x1c01 0x1>;
1833
1834			resets = <&gcc GCC_PCIE_0_BCR>;
1835			reset-names = "pci";
1836
1837			power-domains = <&gcc PCIE_0_GDSC>;
1838
1839			phys = <&pcie0_phy>;
1840			phy-names = "pciephy";
1841
1842			perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1843			wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1844
1845			pinctrl-names = "default";
1846			pinctrl-0 = <&pcie0_default_state>;
1847
1848			status = "disabled";
1849
1850			pcie@0 {
1851				device_type = "pci";
1852				reg = <0x0 0x0 0x0 0x0 0x0>;
1853				bus-range = <0x01 0xff>;
1854
1855				#address-cells = <3>;
1856				#size-cells = <2>;
1857				ranges;
1858			};
1859		};
1860
1861		pcie0_phy: phy@1c06000 {
1862			compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1863			reg = <0 0x01c06000 0 0x2000>;
1864
1865			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1866				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1867				 <&gcc GCC_PCIE_0_CLKREF_EN>,
1868				 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
1869				 <&gcc GCC_PCIE_0_PIPE_CLK>;
1870			clock-names = "aux",
1871				      "cfg_ahb",
1872				      "ref",
1873				      "rchng",
1874				      "pipe";
1875
1876			clock-output-names = "pcie_0_pipe_clk";
1877			#clock-cells = <0>;
1878
1879			#phy-cells = <0>;
1880
1881			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1882			reset-names = "phy";
1883
1884			assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1885			assigned-clock-rates = <100000000>;
1886
1887			status = "disabled";
1888		};
1889
1890		pcie1: pcie@1c08000 {
1891			compatible = "qcom,pcie-sm8450-pcie1";
1892			reg = <0 0x01c08000 0 0x3000>,
1893			      <0 0x40000000 0 0xf1d>,
1894			      <0 0x40000f20 0 0xa8>,
1895			      <0 0x40001000 0 0x1000>,
1896			      <0 0x40100000 0 0x100000>;
1897			reg-names = "parf", "dbi", "elbi", "atu", "config";
1898			device_type = "pci";
1899			linux,pci-domain = <1>;
1900			bus-range = <0x00 0xff>;
1901			num-lanes = <2>;
1902
1903			#address-cells = <3>;
1904			#size-cells = <2>;
1905
1906			ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1907				 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1908
1909			msi-map = <0x0 &gic_its 0x5a00 0x1>,
1910				  <0x100 &gic_its 0x5a01 0x1>;
1911			msi-map-mask = <0xff00>;
1912			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1913				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1914				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1915				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1916				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1917				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1918				     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
1919				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1920			interrupt-names = "msi0",
1921					  "msi1",
1922					  "msi2",
1923					  "msi3",
1924					  "msi4",
1925					  "msi5",
1926					  "msi6",
1927					  "msi7";
1928			#interrupt-cells = <1>;
1929			interrupt-map-mask = <0 0 0 0x7>;
1930			interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1931					<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1932					<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1933					<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1934
1935			clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1936				 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1937				 <&pcie1_phy>,
1938				 <&rpmhcc RPMH_CXO_CLK>,
1939				 <&gcc GCC_PCIE_1_AUX_CLK>,
1940				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1941				 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1942				 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1943				 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1944				 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1945				 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1946			clock-names = "pipe",
1947				      "pipe_mux",
1948				      "phy_pipe",
1949				      "ref",
1950				      "aux",
1951				      "cfg",
1952				      "bus_master",
1953				      "bus_slave",
1954				      "slave_q2a",
1955				      "ddrss_sf_tbu",
1956				      "aggre1";
1957
1958			iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
1959				    <0x100 &apps_smmu 0x1c81 0x1>;
1960
1961			resets = <&gcc GCC_PCIE_1_BCR>;
1962			reset-names = "pci";
1963
1964			power-domains = <&gcc PCIE_1_GDSC>;
1965
1966			phys = <&pcie1_phy>;
1967			phy-names = "pciephy";
1968
1969			perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
1970			wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1971
1972			pinctrl-names = "default";
1973			pinctrl-0 = <&pcie1_default_state>;
1974
1975			status = "disabled";
1976
1977			pcie@0 {
1978				device_type = "pci";
1979				reg = <0x0 0x0 0x0 0x0 0x0>;
1980				bus-range = <0x01 0xff>;
1981
1982				#address-cells = <3>;
1983				#size-cells = <2>;
1984				ranges;
1985			};
1986		};
1987
1988		pcie1_phy: phy@1c0e000 {
1989			compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
1990			reg = <0 0x01c0e000 0 0x2000>;
1991
1992			clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1993				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1994				 <&gcc GCC_PCIE_1_CLKREF_EN>,
1995				 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
1996				 <&gcc GCC_PCIE_1_PIPE_CLK>;
1997			clock-names = "aux",
1998				      "cfg_ahb",
1999				      "ref",
2000				      "rchng",
2001				      "pipe";
2002
2003			clock-output-names = "pcie_1_pipe_clk";
2004			#clock-cells = <0>;
2005
2006			#phy-cells = <0>;
2007
2008			resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2009			reset-names = "phy";
2010
2011			assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2012			assigned-clock-rates = <100000000>;
2013
2014			status = "disabled";
2015		};
2016
2017		config_noc: interconnect@1500000 {
2018			compatible = "qcom,sm8450-config-noc";
2019			reg = <0 0x01500000 0 0x1c000>;
2020			#interconnect-cells = <2>;
2021			qcom,bcm-voters = <&apps_bcm_voter>;
2022		};
2023
2024		system_noc: interconnect@1680000 {
2025			compatible = "qcom,sm8450-system-noc";
2026			reg = <0 0x01680000 0 0x1e200>;
2027			#interconnect-cells = <2>;
2028			qcom,bcm-voters = <&apps_bcm_voter>;
2029		};
2030
2031		pcie_noc: interconnect@16c0000 {
2032			compatible = "qcom,sm8450-pcie-anoc";
2033			reg = <0 0x016c0000 0 0xe280>;
2034			#interconnect-cells = <2>;
2035			qcom,bcm-voters = <&apps_bcm_voter>;
2036		};
2037
2038		aggre1_noc: interconnect@16e0000 {
2039			compatible = "qcom,sm8450-aggre1-noc";
2040			reg = <0 0x016e0000 0 0x1c080>;
2041			#interconnect-cells = <2>;
2042			clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2043				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
2044			qcom,bcm-voters = <&apps_bcm_voter>;
2045		};
2046
2047		aggre2_noc: interconnect@1700000 {
2048			compatible = "qcom,sm8450-aggre2-noc";
2049			reg = <0 0x01700000 0 0x31080>;
2050			#interconnect-cells = <2>;
2051			qcom,bcm-voters = <&apps_bcm_voter>;
2052			clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
2053				 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
2054				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2055				 <&rpmhcc RPMH_IPA_CLK>;
2056		};
2057
2058		mmss_noc: interconnect@1740000 {
2059			compatible = "qcom,sm8450-mmss-noc";
2060			reg = <0 0x01740000 0 0x1f080>;
2061			#interconnect-cells = <2>;
2062			qcom,bcm-voters = <&apps_bcm_voter>;
2063		};
2064
2065		tcsr_mutex: hwlock@1f40000 {
2066			compatible = "qcom,tcsr-mutex";
2067			reg = <0x0 0x01f40000 0x0 0x40000>;
2068			#hwlock-cells = <1>;
2069		};
2070
2071		tcsr: syscon@1fc0000 {
2072			compatible = "qcom,sm8450-tcsr", "syscon";
2073			reg = <0x0 0x1fc0000 0x0 0x30000>;
2074		};
2075
2076		gpu: gpu@3d00000 {
2077			compatible = "qcom,adreno-730.1", "qcom,adreno";
2078			reg = <0x0 0x03d00000 0x0 0x40000>,
2079			      <0x0 0x03d9e000 0x0 0x1000>,
2080			      <0x0 0x03d61000 0x0 0x800>;
2081			reg-names = "kgsl_3d0_reg_memory",
2082				    "cx_mem",
2083				    "cx_dbgc";
2084
2085			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2086
2087			iommus = <&adreno_smmu 0 0x400>,
2088				 <&adreno_smmu 1 0x400>;
2089
2090			operating-points-v2 = <&gpu_opp_table>;
2091
2092			qcom,gmu = <&gmu>;
2093			#cooling-cells = <2>;
2094
2095			status = "disabled";
2096
2097			zap-shader {
2098				memory-region = <&gpu_micro_code_mem>;
2099			};
2100
2101			gpu_opp_table: opp-table {
2102				compatible = "operating-points-v2";
2103
2104				opp-818000000 {
2105					opp-hz = /bits/ 64 <818000000>;
2106					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2107				};
2108
2109				opp-791000000 {
2110					opp-hz = /bits/ 64 <791000000>;
2111					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2112				};
2113
2114				opp-734000000 {
2115					opp-hz = /bits/ 64 <734000000>;
2116					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2117				};
2118
2119				opp-640000000 {
2120					opp-hz = /bits/ 64 <640000000>;
2121					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2122				};
2123
2124				opp-599000000 {
2125					opp-hz = /bits/ 64 <599000000>;
2126					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2127				};
2128
2129				opp-545000000 {
2130					opp-hz = /bits/ 64 <545000000>;
2131					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2132				};
2133
2134				opp-492000000 {
2135					opp-hz = /bits/ 64 <492000000>;
2136					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2137				};
2138
2139				opp-421000000 {
2140					opp-hz = /bits/ 64 <421000000>;
2141					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2142				};
2143
2144				opp-350000000 {
2145					opp-hz = /bits/ 64 <350000000>;
2146					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2147				};
2148
2149				opp-317000000 {
2150					opp-hz = /bits/ 64 <317000000>;
2151					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2152				};
2153
2154				opp-285000000 {
2155					opp-hz = /bits/ 64 <285000000>;
2156					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2157				};
2158
2159				opp-220000000 {
2160					opp-hz = /bits/ 64 <220000000>;
2161					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2162				};
2163			};
2164		};
2165
2166		gmu: gmu@3d6a000 {
2167			compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu";
2168			reg = <0x0 0x03d6a000 0x0 0x35000>,
2169			      <0x0 0x03d50000 0x0 0x10000>,
2170			      <0x0 0x0b290000 0x0 0x10000>;
2171			reg-names = "gmu", "rscc", "gmu_pdc";
2172
2173			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2174				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2175			interrupt-names = "hfi", "gmu";
2176
2177			clocks = <&gpucc GPU_CC_AHB_CLK>,
2178				 <&gpucc GPU_CC_CX_GMU_CLK>,
2179				 <&gpucc GPU_CC_CXO_CLK>,
2180				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2181				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2182				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2183				 <&gpucc GPU_CC_DEMET_CLK>;
2184			clock-names = "ahb",
2185				      "gmu",
2186				      "cxo",
2187				      "axi",
2188				      "memnoc",
2189				      "hub",
2190				      "demet";
2191
2192			power-domains = <&gpucc GPU_CX_GDSC>,
2193					<&gpucc GPU_GX_GDSC>;
2194			power-domain-names = "cx",
2195					     "gx";
2196
2197			iommus = <&adreno_smmu 5 0x400>;
2198
2199			qcom,qmp = <&aoss_qmp>;
2200
2201			operating-points-v2 = <&gmu_opp_table>;
2202
2203			gmu_opp_table: opp-table {
2204				compatible = "operating-points-v2";
2205
2206				opp-500000000 {
2207					opp-hz = /bits/ 64 <500000000>;
2208					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2209				};
2210
2211				opp-200000000 {
2212					opp-hz = /bits/ 64 <200000000>;
2213					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2214				};
2215			};
2216		};
2217
2218		gpucc: clock-controller@3d90000 {
2219			compatible = "qcom,sm8450-gpucc";
2220			reg = <0x0 0x03d90000 0x0 0xa000>;
2221			clocks = <&rpmhcc RPMH_CXO_CLK>,
2222				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2223				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2224			#clock-cells = <1>;
2225			#reset-cells = <1>;
2226			#power-domain-cells = <1>;
2227		};
2228
2229		adreno_smmu: iommu@3da0000 {
2230			compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu",
2231				     "qcom,smmu-500", "arm,mmu-500";
2232			reg = <0x0 0x03da0000 0x0 0x40000>;
2233			#iommu-cells = <2>;
2234			#global-interrupts = <1>;
2235			interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2236				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2237				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2238				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2239				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2240				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2241				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2242				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2243				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2244				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2245				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2246				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2247				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
2248				     <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
2249				     <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
2250				     <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2251				     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
2252				     <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
2253				     <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
2254				     <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
2255				     <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
2256				     <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
2257				     <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
2258				     <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
2259				     <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
2260				     <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
2261			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2262				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2263				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2264				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2265				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2266				 <&gpucc GPU_CC_AHB_CLK>;
2267			clock-names = "gmu",
2268				      "hub",
2269				      "hlos",
2270				      "bus",
2271				      "iface",
2272				      "ahb";
2273			power-domains = <&gpucc GPU_CX_GDSC>;
2274			dma-coherent;
2275		};
2276
2277		usb_1_hsphy: phy@88e3000 {
2278			compatible = "qcom,sm8450-usb-hs-phy",
2279				     "qcom,usb-snps-hs-7nm-phy";
2280			reg = <0 0x088e3000 0 0x400>;
2281			status = "disabled";
2282			#phy-cells = <0>;
2283
2284			clocks = <&rpmhcc RPMH_CXO_CLK>;
2285			clock-names = "ref";
2286
2287			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2288		};
2289
2290		usb_1_qmpphy: phy@88e8000 {
2291			compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2292			reg = <0 0x088e8000 0 0x3000>;
2293
2294			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2295				 <&rpmhcc RPMH_CXO_CLK>,
2296				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2297				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2298			clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2299
2300			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2301				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2302			reset-names = "phy", "common";
2303
2304			#clock-cells = <1>;
2305			#phy-cells = <1>;
2306
2307			status = "disabled";
2308
2309			ports {
2310				#address-cells = <1>;
2311				#size-cells = <0>;
2312
2313				port@0 {
2314					reg = <0>;
2315
2316					usb_1_qmpphy_out: endpoint {
2317					};
2318				};
2319
2320				port@1 {
2321					reg = <1>;
2322
2323					usb_1_qmpphy_usb_ss_in: endpoint {
2324					};
2325				};
2326
2327				port@2 {
2328					reg = <2>;
2329
2330					usb_1_qmpphy_dp_in: endpoint {
2331					};
2332				};
2333			};
2334		};
2335
2336		remoteproc_slpi: remoteproc@2400000 {
2337			compatible = "qcom,sm8450-slpi-pas";
2338			reg = <0 0x02400000 0 0x4000>;
2339
2340			interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2341					      <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2342					      <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2343					      <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2344					      <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2345			interrupt-names = "wdog", "fatal", "ready",
2346					  "handover", "stop-ack";
2347
2348			clocks = <&rpmhcc RPMH_CXO_CLK>;
2349			clock-names = "xo";
2350
2351			power-domains = <&rpmhpd RPMHPD_LCX>,
2352					<&rpmhpd RPMHPD_LMX>;
2353			power-domain-names = "lcx", "lmx";
2354
2355			memory-region = <&slpi_mem>;
2356
2357			qcom,qmp = <&aoss_qmp>;
2358
2359			qcom,smem-states = <&smp2p_slpi_out 0>;
2360			qcom,smem-state-names = "stop";
2361
2362			status = "disabled";
2363
2364			glink-edge {
2365				interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2366							     IPCC_MPROC_SIGNAL_GLINK_QMP
2367							     IRQ_TYPE_EDGE_RISING>;
2368				mboxes = <&ipcc IPCC_CLIENT_SLPI
2369						IPCC_MPROC_SIGNAL_GLINK_QMP>;
2370
2371				label = "slpi";
2372				qcom,remote-pid = <3>;
2373
2374				fastrpc {
2375					compatible = "qcom,fastrpc";
2376					qcom,glink-channels = "fastrpcglink-apps-dsp";
2377					label = "sdsp";
2378					qcom,non-secure-domain;
2379					#address-cells = <1>;
2380					#size-cells = <0>;
2381
2382					compute-cb@1 {
2383						compatible = "qcom,fastrpc-compute-cb";
2384						reg = <1>;
2385						iommus = <&apps_smmu 0x0541 0x0>;
2386					};
2387
2388					compute-cb@2 {
2389						compatible = "qcom,fastrpc-compute-cb";
2390						reg = <2>;
2391						iommus = <&apps_smmu 0x0542 0x0>;
2392					};
2393
2394					compute-cb@3 {
2395						compatible = "qcom,fastrpc-compute-cb";
2396						reg = <3>;
2397						iommus = <&apps_smmu 0x0543 0x0>;
2398						/* note: shared-cb = <4> in downstream */
2399					};
2400				};
2401			};
2402		};
2403
2404		wsa2macro: codec@31e0000 {
2405			compatible = "qcom,sm8450-lpass-wsa-macro";
2406			reg = <0 0x031e0000 0 0x1000>;
2407			clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2408				 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2409				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2410				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2411				 <&vamacro>;
2412			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2413
2414			#clock-cells = <0>;
2415			clock-output-names = "wsa2-mclk";
2416			#sound-dai-cells = <1>;
2417		};
2418
2419		swr4: soundwire@31f0000 {
2420			compatible = "qcom,soundwire-v1.7.0";
2421			reg = <0 0x031f0000 0 0x2000>;
2422			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2423			clocks = <&wsa2macro>;
2424			clock-names = "iface";
2425			label = "WSA2";
2426
2427			pinctrl-0 = <&wsa2_swr_active>;
2428			pinctrl-names = "default";
2429
2430			qcom,din-ports = <2>;
2431			qcom,dout-ports = <6>;
2432
2433			qcom,ports-sinterval-low =	/bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2434			qcom,ports-offset1 =		/bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2435			qcom,ports-offset2 =		/bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2436			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2437			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2438			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2439			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2440			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2441			qcom,ports-lane-control =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2442
2443			#address-cells = <2>;
2444			#size-cells = <0>;
2445			#sound-dai-cells = <1>;
2446			status = "disabled";
2447		};
2448
2449		rxmacro: codec@3200000 {
2450			compatible = "qcom,sm8450-lpass-rx-macro";
2451			reg = <0 0x03200000 0 0x1000>;
2452			clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2453				 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2454				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2455				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2456				 <&vamacro>;
2457			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2458
2459			#clock-cells = <0>;
2460			clock-output-names = "mclk";
2461			#sound-dai-cells = <1>;
2462		};
2463
2464		swr1: soundwire@3210000 {
2465			compatible = "qcom,soundwire-v1.7.0";
2466			reg = <0 0x03210000 0 0x2000>;
2467			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2468			clocks = <&rxmacro>;
2469			clock-names = "iface";
2470			label = "RX";
2471			qcom,din-ports = <0>;
2472			qcom,dout-ports = <5>;
2473
2474			pinctrl-0 = <&rx_swr_active>;
2475			pinctrl-names = "default";
2476
2477			qcom,ports-sinterval-low =	/bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2478			qcom,ports-offset1 =		/bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2479			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2480			qcom,ports-hstart =		/bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2481			qcom,ports-hstop =		/bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2482			qcom,ports-word-length =	/bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2483			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2484			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2485			qcom,ports-lane-control =	/bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2486
2487			#address-cells = <2>;
2488			#size-cells = <0>;
2489			#sound-dai-cells = <1>;
2490			status = "disabled";
2491		};
2492
2493		txmacro: codec@3220000 {
2494			compatible = "qcom,sm8450-lpass-tx-macro";
2495			reg = <0 0x03220000 0 0x1000>;
2496			clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2497				 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2498				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2499				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2500				 <&vamacro>;
2501			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2502
2503			#clock-cells = <0>;
2504			clock-output-names = "mclk";
2505			#sound-dai-cells = <1>;
2506		};
2507
2508		wsamacro: codec@3240000 {
2509			compatible = "qcom,sm8450-lpass-wsa-macro";
2510			reg = <0 0x03240000 0 0x1000>;
2511			clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2512				 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2513				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2514				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2515				 <&vamacro>;
2516			clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2517
2518			#clock-cells = <0>;
2519			clock-output-names = "mclk";
2520			#sound-dai-cells = <1>;
2521		};
2522
2523		swr0: soundwire@3250000 {
2524			compatible = "qcom,soundwire-v1.7.0";
2525			reg = <0 0x03250000 0 0x2000>;
2526			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2527			clocks = <&wsamacro>;
2528			clock-names = "iface";
2529			label = "WSA";
2530
2531			pinctrl-0 = <&wsa_swr_active>;
2532			pinctrl-names = "default";
2533
2534			qcom,din-ports = <2>;
2535			qcom,dout-ports = <6>;
2536
2537			qcom,ports-sinterval-low =	/bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2538			qcom,ports-offset1 =		/bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2539			qcom,ports-offset2 =		/bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2540			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2541			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2542			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2543			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2544			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2545			qcom,ports-lane-control =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2546
2547			#address-cells = <2>;
2548			#size-cells = <0>;
2549			#sound-dai-cells = <1>;
2550			status = "disabled";
2551		};
2552
2553		swr2: soundwire@33b0000 {
2554			compatible = "qcom,soundwire-v1.7.0";
2555			reg = <0 0x033b0000 0 0x2000>;
2556			interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2557				     <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2558			interrupt-names = "core", "wakeup";
2559
2560			clocks = <&txmacro>;
2561			clock-names = "iface";
2562			label = "TX";
2563
2564			pinctrl-0 = <&tx_swr_active>;
2565			pinctrl-names = "default";
2566
2567			qcom,din-ports = <4>;
2568			qcom,dout-ports = <0>;
2569			qcom,ports-sinterval-low =	/bits/ 8 <0x01 0x01 0x03 0x03>;
2570			qcom,ports-offset1 =		/bits/ 8 <0x00 0x00 0x01 0x01>;
2571			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x00 0x00>;
2572			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff>;
2573			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff>;
2574			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff>;
2575			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0xff 0xff>;
2576			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff>;
2577			qcom,ports-lane-control =	/bits/ 8 <0x01 0x02 0x00 0x00>;
2578
2579			#address-cells = <2>;
2580			#size-cells = <0>;
2581			#sound-dai-cells = <1>;
2582			status = "disabled";
2583		};
2584
2585		vamacro: codec@33f0000 {
2586			compatible = "qcom,sm8450-lpass-va-macro";
2587			reg = <0 0x033f0000 0 0x1000>;
2588			clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2589				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2590				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2591				 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2592			clock-names = "mclk", "macro", "dcodec", "npl";
2593
2594			#clock-cells = <0>;
2595			clock-output-names = "fsgen";
2596			#sound-dai-cells = <1>;
2597			status = "disabled";
2598		};
2599
2600		remoteproc_adsp: remoteproc@30000000 {
2601			compatible = "qcom,sm8450-adsp-pas";
2602			reg = <0 0x30000000 0 0x100>;
2603
2604			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2605					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2606					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2607					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2608					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2609			interrupt-names = "wdog", "fatal", "ready",
2610					  "handover", "stop-ack";
2611
2612			clocks = <&rpmhcc RPMH_CXO_CLK>;
2613			clock-names = "xo";
2614
2615			power-domains = <&rpmhpd RPMHPD_LCX>,
2616					<&rpmhpd RPMHPD_LMX>;
2617			power-domain-names = "lcx", "lmx";
2618
2619			memory-region = <&adsp_mem>;
2620
2621			qcom,qmp = <&aoss_qmp>;
2622
2623			qcom,smem-states = <&smp2p_adsp_out 0>;
2624			qcom,smem-state-names = "stop";
2625
2626			status = "disabled";
2627
2628			remoteproc_adsp_glink: glink-edge {
2629				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2630							     IPCC_MPROC_SIGNAL_GLINK_QMP
2631							     IRQ_TYPE_EDGE_RISING>;
2632				mboxes = <&ipcc IPCC_CLIENT_LPASS
2633						IPCC_MPROC_SIGNAL_GLINK_QMP>;
2634
2635				label = "lpass";
2636				qcom,remote-pid = <2>;
2637
2638				gpr {
2639					compatible = "qcom,gpr";
2640					qcom,glink-channels = "adsp_apps";
2641					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2642					qcom,intents = <512 20>;
2643					#address-cells = <1>;
2644					#size-cells = <0>;
2645
2646					q6apm: service@1 {
2647						compatible = "qcom,q6apm";
2648						reg = <GPR_APM_MODULE_IID>;
2649						#sound-dai-cells = <0>;
2650						qcom,protection-domain = "avs/audio",
2651									 "msm/adsp/audio_pd";
2652
2653						q6apmdai: dais {
2654							compatible = "qcom,q6apm-dais";
2655							iommus = <&apps_smmu 0x1801 0x0>;
2656						};
2657
2658						q6apmbedai: bedais {
2659							compatible = "qcom,q6apm-lpass-dais";
2660							#sound-dai-cells = <1>;
2661						};
2662					};
2663
2664					q6prm: service@2 {
2665						compatible = "qcom,q6prm";
2666						reg = <GPR_PRM_MODULE_IID>;
2667						qcom,protection-domain = "avs/audio",
2668									 "msm/adsp/audio_pd";
2669
2670						q6prmcc: clock-controller {
2671							compatible = "qcom,q6prm-lpass-clocks";
2672							#clock-cells = <2>;
2673						};
2674					};
2675				};
2676
2677				fastrpc {
2678					compatible = "qcom,fastrpc";
2679					qcom,glink-channels = "fastrpcglink-apps-dsp";
2680					label = "adsp";
2681					qcom,non-secure-domain;
2682					#address-cells = <1>;
2683					#size-cells = <0>;
2684
2685					compute-cb@3 {
2686						compatible = "qcom,fastrpc-compute-cb";
2687						reg = <3>;
2688						iommus = <&apps_smmu 0x1803 0x0>;
2689					};
2690
2691					compute-cb@4 {
2692						compatible = "qcom,fastrpc-compute-cb";
2693						reg = <4>;
2694						iommus = <&apps_smmu 0x1804 0x0>;
2695					};
2696
2697					compute-cb@5 {
2698						compatible = "qcom,fastrpc-compute-cb";
2699						reg = <5>;
2700						iommus = <&apps_smmu 0x1805 0x0>;
2701					};
2702				};
2703			};
2704		};
2705
2706		remoteproc_cdsp: remoteproc@32300000 {
2707			compatible = "qcom,sm8450-cdsp-pas";
2708			reg = <0 0x32300000 0 0x1400000>;
2709
2710			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2711					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2712					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2713					      <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2714					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2715			interrupt-names = "wdog", "fatal", "ready",
2716					  "handover", "stop-ack";
2717
2718			clocks = <&rpmhcc RPMH_CXO_CLK>;
2719			clock-names = "xo";
2720
2721			power-domains = <&rpmhpd RPMHPD_CX>,
2722					<&rpmhpd RPMHPD_MXC>;
2723			power-domain-names = "cx", "mxc";
2724
2725			memory-region = <&cdsp_mem>;
2726
2727			qcom,qmp = <&aoss_qmp>;
2728
2729			qcom,smem-states = <&smp2p_cdsp_out 0>;
2730			qcom,smem-state-names = "stop";
2731
2732			status = "disabled";
2733
2734			glink-edge {
2735				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2736							     IPCC_MPROC_SIGNAL_GLINK_QMP
2737							     IRQ_TYPE_EDGE_RISING>;
2738				mboxes = <&ipcc IPCC_CLIENT_CDSP
2739						IPCC_MPROC_SIGNAL_GLINK_QMP>;
2740
2741				label = "cdsp";
2742				qcom,remote-pid = <5>;
2743
2744				fastrpc {
2745					compatible = "qcom,fastrpc";
2746					qcom,glink-channels = "fastrpcglink-apps-dsp";
2747					label = "cdsp";
2748					qcom,non-secure-domain;
2749					#address-cells = <1>;
2750					#size-cells = <0>;
2751
2752					compute-cb@1 {
2753						compatible = "qcom,fastrpc-compute-cb";
2754						reg = <1>;
2755						iommus = <&apps_smmu 0x2161 0x0400>,
2756							 <&apps_smmu 0x1021 0x1420>;
2757					};
2758
2759					compute-cb@2 {
2760						compatible = "qcom,fastrpc-compute-cb";
2761						reg = <2>;
2762						iommus = <&apps_smmu 0x2162 0x0400>,
2763							 <&apps_smmu 0x1022 0x1420>;
2764					};
2765
2766					compute-cb@3 {
2767						compatible = "qcom,fastrpc-compute-cb";
2768						reg = <3>;
2769						iommus = <&apps_smmu 0x2163 0x0400>,
2770							 <&apps_smmu 0x1023 0x1420>;
2771					};
2772
2773					compute-cb@4 {
2774						compatible = "qcom,fastrpc-compute-cb";
2775						reg = <4>;
2776						iommus = <&apps_smmu 0x2164 0x0400>,
2777							 <&apps_smmu 0x1024 0x1420>;
2778					};
2779
2780					compute-cb@5 {
2781						compatible = "qcom,fastrpc-compute-cb";
2782						reg = <5>;
2783						iommus = <&apps_smmu 0x2165 0x0400>,
2784							 <&apps_smmu 0x1025 0x1420>;
2785					};
2786
2787					compute-cb@6 {
2788						compatible = "qcom,fastrpc-compute-cb";
2789						reg = <6>;
2790						iommus = <&apps_smmu 0x2166 0x0400>,
2791							 <&apps_smmu 0x1026 0x1420>;
2792					};
2793
2794					compute-cb@7 {
2795						compatible = "qcom,fastrpc-compute-cb";
2796						reg = <7>;
2797						iommus = <&apps_smmu 0x2167 0x0400>,
2798							 <&apps_smmu 0x1027 0x1420>;
2799					};
2800
2801					compute-cb@8 {
2802						compatible = "qcom,fastrpc-compute-cb";
2803						reg = <8>;
2804						iommus = <&apps_smmu 0x2168 0x0400>,
2805							 <&apps_smmu 0x1028 0x1420>;
2806					};
2807
2808					/* note: secure cb9 in downstream */
2809				};
2810			};
2811		};
2812
2813		remoteproc_mpss: remoteproc@4080000 {
2814			compatible = "qcom,sm8450-mpss-pas";
2815			reg = <0x0 0x04080000 0x0 0x4040>;
2816
2817			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2818					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2819					      <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2820					      <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2821					      <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2822					      <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2823			interrupt-names = "wdog", "fatal", "ready", "handover",
2824					  "stop-ack", "shutdown-ack";
2825
2826			clocks = <&rpmhcc RPMH_CXO_CLK>;
2827			clock-names = "xo";
2828
2829			power-domains = <&rpmhpd RPMHPD_CX>,
2830					<&rpmhpd RPMHPD_MSS>;
2831			power-domain-names = "cx", "mss";
2832
2833			memory-region = <&mpss_mem>;
2834
2835			qcom,qmp = <&aoss_qmp>;
2836
2837			qcom,smem-states = <&smp2p_modem_out 0>;
2838			qcom,smem-state-names = "stop";
2839
2840			status = "disabled";
2841
2842			glink-edge {
2843				interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2844							     IPCC_MPROC_SIGNAL_GLINK_QMP
2845							     IRQ_TYPE_EDGE_RISING>;
2846				mboxes = <&ipcc IPCC_CLIENT_MPSS
2847						IPCC_MPROC_SIGNAL_GLINK_QMP>;
2848				label = "modem";
2849				qcom,remote-pid = <1>;
2850			};
2851		};
2852
2853		videocc: clock-controller@aaf0000 {
2854			compatible = "qcom,sm8450-videocc";
2855			reg = <0 0x0aaf0000 0 0x10000>;
2856			clocks = <&rpmhcc RPMH_CXO_CLK>,
2857				 <&gcc GCC_VIDEO_AHB_CLK>;
2858			power-domains = <&rpmhpd RPMHPD_MMCX>;
2859			required-opps = <&rpmhpd_opp_low_svs>;
2860			#clock-cells = <1>;
2861			#reset-cells = <1>;
2862			#power-domain-cells = <1>;
2863		};
2864
2865		cci0: cci@ac15000 {
2866			compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2867			reg = <0 0x0ac15000 0 0x1000>;
2868			interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
2869			power-domains = <&camcc TITAN_TOP_GDSC>;
2870
2871			clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2872				 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2873				 <&camcc CAM_CC_CPAS_AHB_CLK>,
2874				 <&camcc CAM_CC_CCI_0_CLK>,
2875				 <&camcc CAM_CC_CCI_0_CLK_SRC>;
2876			clock-names = "camnoc_axi",
2877				      "slow_ahb_src",
2878				      "cpas_ahb",
2879				      "cci",
2880				      "cci_src";
2881			pinctrl-0 = <&cci0_default &cci1_default>;
2882			pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2883			pinctrl-names = "default", "sleep";
2884
2885			status = "disabled";
2886			#address-cells = <1>;
2887			#size-cells = <0>;
2888
2889			cci0_i2c0: i2c-bus@0 {
2890				reg = <0>;
2891				clock-frequency = <1000000>;
2892				#address-cells = <1>;
2893				#size-cells = <0>;
2894			};
2895
2896			cci0_i2c1: i2c-bus@1 {
2897				reg = <1>;
2898				clock-frequency = <1000000>;
2899				#address-cells = <1>;
2900				#size-cells = <0>;
2901			};
2902		};
2903
2904		cci1: cci@ac16000 {
2905			compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2906			reg = <0 0x0ac16000 0 0x1000>;
2907			interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
2908			power-domains = <&camcc TITAN_TOP_GDSC>;
2909
2910			clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2911				 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2912				 <&camcc CAM_CC_CPAS_AHB_CLK>,
2913				 <&camcc CAM_CC_CCI_1_CLK>,
2914				 <&camcc CAM_CC_CCI_1_CLK_SRC>;
2915			clock-names = "camnoc_axi",
2916				      "slow_ahb_src",
2917				      "cpas_ahb",
2918				      "cci",
2919				      "cci_src";
2920			pinctrl-0 = <&cci2_default &cci3_default>;
2921			pinctrl-1 = <&cci2_sleep &cci3_sleep>;
2922			pinctrl-names = "default", "sleep";
2923
2924			status = "disabled";
2925			#address-cells = <1>;
2926			#size-cells = <0>;
2927
2928			cci1_i2c0: i2c-bus@0 {
2929				reg = <0>;
2930				clock-frequency = <1000000>;
2931				#address-cells = <1>;
2932				#size-cells = <0>;
2933			};
2934
2935			cci1_i2c1: i2c-bus@1 {
2936				reg = <1>;
2937				clock-frequency = <1000000>;
2938				#address-cells = <1>;
2939				#size-cells = <0>;
2940			};
2941		};
2942
2943		camcc: clock-controller@ade0000 {
2944			compatible = "qcom,sm8450-camcc";
2945			reg = <0 0x0ade0000 0 0x20000>;
2946			clocks = <&gcc GCC_CAMERA_AHB_CLK>,
2947				 <&rpmhcc RPMH_CXO_CLK>,
2948				 <&rpmhcc RPMH_CXO_CLK_A>,
2949				 <&sleep_clk>;
2950			power-domains = <&rpmhpd RPMHPD_MMCX>;
2951			required-opps = <&rpmhpd_opp_low_svs>;
2952			#clock-cells = <1>;
2953			#reset-cells = <1>;
2954			#power-domain-cells = <1>;
2955			status = "disabled";
2956		};
2957
2958		mdss: display-subsystem@ae00000 {
2959			compatible = "qcom,sm8450-mdss";
2960			reg = <0 0x0ae00000 0 0x1000>;
2961			reg-names = "mdss";
2962
2963			/* same path used twice */
2964			interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2965					<&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2966					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2967					 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
2968			interconnect-names = "mdp0-mem",
2969					     "mdp1-mem",
2970					     "cpu-cfg";
2971
2972			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2973
2974			power-domains = <&dispcc MDSS_GDSC>;
2975
2976			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2977				 <&gcc GCC_DISP_HF_AXI_CLK>,
2978				 <&gcc GCC_DISP_SF_AXI_CLK>,
2979				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2980
2981			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2982			interrupt-controller;
2983			#interrupt-cells = <1>;
2984
2985			iommus = <&apps_smmu 0x2800 0x402>;
2986
2987			#address-cells = <2>;
2988			#size-cells = <2>;
2989			ranges;
2990
2991			status = "disabled";
2992
2993			mdss_mdp: display-controller@ae01000 {
2994				compatible = "qcom,sm8450-dpu";
2995				reg = <0 0x0ae01000 0 0x8f000>,
2996				      <0 0x0aeb0000 0 0x2008>;
2997				reg-names = "mdp", "vbif";
2998
2999				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3000					<&gcc GCC_DISP_SF_AXI_CLK>,
3001					<&dispcc DISP_CC_MDSS_AHB_CLK>,
3002					<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3003					<&dispcc DISP_CC_MDSS_MDP_CLK>,
3004					<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3005				clock-names = "bus",
3006					      "nrt_bus",
3007					      "iface",
3008					      "lut",
3009					      "core",
3010					      "vsync";
3011
3012				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3013				assigned-clock-rates = <19200000>;
3014
3015				operating-points-v2 = <&mdp_opp_table>;
3016				power-domains = <&rpmhpd RPMHPD_MMCX>;
3017
3018				interrupt-parent = <&mdss>;
3019				interrupts = <0>;
3020
3021				ports {
3022					#address-cells = <1>;
3023					#size-cells = <0>;
3024
3025					port@0 {
3026						reg = <0>;
3027						dpu_intf1_out: endpoint {
3028							remote-endpoint = <&mdss_dsi0_in>;
3029						};
3030					};
3031
3032					port@1 {
3033						reg = <1>;
3034						dpu_intf2_out: endpoint {
3035							remote-endpoint = <&mdss_dsi1_in>;
3036						};
3037					};
3038
3039					port@2 {
3040						reg = <2>;
3041						dpu_intf0_out: endpoint {
3042							remote-endpoint = <&mdss_dp0_in>;
3043						};
3044					};
3045				};
3046
3047				mdp_opp_table: opp-table {
3048					compatible = "operating-points-v2";
3049
3050					opp-172000000 {
3051						opp-hz = /bits/ 64 <172000000>;
3052						required-opps = <&rpmhpd_opp_low_svs_d1>;
3053					};
3054
3055					opp-200000000 {
3056						opp-hz = /bits/ 64 <200000000>;
3057						required-opps = <&rpmhpd_opp_low_svs>;
3058					};
3059
3060					opp-325000000 {
3061						opp-hz = /bits/ 64 <325000000>;
3062						required-opps = <&rpmhpd_opp_svs>;
3063					};
3064
3065					opp-375000000 {
3066						opp-hz = /bits/ 64 <375000000>;
3067						required-opps = <&rpmhpd_opp_svs_l1>;
3068					};
3069
3070					opp-500000000 {
3071						opp-hz = /bits/ 64 <500000000>;
3072						required-opps = <&rpmhpd_opp_nom>;
3073					};
3074				};
3075			};
3076
3077			mdss_dp0: displayport-controller@ae90000 {
3078				compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
3079				reg = <0 0xae90000 0 0x200>,
3080				      <0 0xae90200 0 0x200>,
3081				      <0 0xae90400 0 0xc00>,
3082				      <0 0xae91000 0 0x400>,
3083				      <0 0xae91400 0 0x400>;
3084				interrupt-parent = <&mdss>;
3085				interrupts = <12>;
3086				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3087					 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
3088					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
3089					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
3090					 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
3091				clock-names = "core_iface",
3092					      "core_aux",
3093					      "ctrl_link",
3094					      "ctrl_link_iface",
3095					      "stream_pixel";
3096
3097				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3098						  <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
3099				assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3100							 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3101
3102				phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3103				phy-names = "dp";
3104
3105				#sound-dai-cells = <0>;
3106
3107				operating-points-v2 = <&dp_opp_table>;
3108				power-domains = <&rpmhpd RPMHPD_MMCX>;
3109
3110				status = "disabled";
3111
3112				ports {
3113					#address-cells = <1>;
3114					#size-cells = <0>;
3115
3116					port@0 {
3117						reg = <0>;
3118						mdss_dp0_in: endpoint {
3119							remote-endpoint = <&dpu_intf0_out>;
3120						};
3121					};
3122				};
3123
3124				dp_opp_table: opp-table {
3125					compatible = "operating-points-v2";
3126
3127					opp-160000000 {
3128						opp-hz = /bits/ 64 <160000000>;
3129						required-opps = <&rpmhpd_opp_low_svs>;
3130					};
3131
3132					opp-270000000 {
3133						opp-hz = /bits/ 64 <270000000>;
3134						required-opps = <&rpmhpd_opp_svs>;
3135					};
3136
3137					opp-540000000 {
3138						opp-hz = /bits/ 64 <540000000>;
3139						required-opps = <&rpmhpd_opp_svs_l1>;
3140					};
3141
3142					opp-810000000 {
3143						opp-hz = /bits/ 64 <810000000>;
3144						required-opps = <&rpmhpd_opp_nom>;
3145					};
3146				};
3147			};
3148
3149			mdss_dsi0: dsi@ae94000 {
3150				compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3151				reg = <0 0x0ae94000 0 0x400>;
3152				reg-names = "dsi_ctrl";
3153
3154				interrupt-parent = <&mdss>;
3155				interrupts = <4>;
3156
3157				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3158					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3159					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3160					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3161					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3162					<&gcc GCC_DISP_HF_AXI_CLK>;
3163				clock-names = "byte",
3164					      "byte_intf",
3165					      "pixel",
3166					      "core",
3167					      "iface",
3168					      "bus";
3169
3170				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3171				assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3172
3173				operating-points-v2 = <&mdss_dsi_opp_table>;
3174				power-domains = <&rpmhpd RPMHPD_MMCX>;
3175
3176				phys = <&mdss_dsi0_phy>;
3177				phy-names = "dsi";
3178
3179				#address-cells = <1>;
3180				#size-cells = <0>;
3181
3182				status = "disabled";
3183
3184				ports {
3185					#address-cells = <1>;
3186					#size-cells = <0>;
3187
3188					port@0 {
3189						reg = <0>;
3190						mdss_dsi0_in: endpoint {
3191							remote-endpoint = <&dpu_intf1_out>;
3192						};
3193					};
3194
3195					port@1 {
3196						reg = <1>;
3197						mdss_dsi0_out: endpoint {
3198						};
3199					};
3200				};
3201
3202				mdss_dsi_opp_table: opp-table {
3203					compatible = "operating-points-v2";
3204
3205					opp-187500000 {
3206						opp-hz = /bits/ 64 <187500000>;
3207						required-opps = <&rpmhpd_opp_low_svs>;
3208					};
3209
3210					opp-300000000 {
3211						opp-hz = /bits/ 64 <300000000>;
3212						required-opps = <&rpmhpd_opp_svs>;
3213					};
3214
3215					opp-358000000 {
3216						opp-hz = /bits/ 64 <358000000>;
3217						required-opps = <&rpmhpd_opp_svs_l1>;
3218					};
3219				};
3220			};
3221
3222			mdss_dsi0_phy: phy@ae94400 {
3223				compatible = "qcom,sm8450-dsi-phy-5nm";
3224				reg = <0 0x0ae94400 0 0x200>,
3225				      <0 0x0ae94600 0 0x280>,
3226				      <0 0x0ae94900 0 0x260>;
3227				reg-names = "dsi_phy",
3228					    "dsi_phy_lane",
3229					    "dsi_pll";
3230
3231				#clock-cells = <1>;
3232				#phy-cells = <0>;
3233
3234				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3235					 <&rpmhcc RPMH_CXO_CLK>;
3236				clock-names = "iface", "ref";
3237
3238				status = "disabled";
3239			};
3240
3241			mdss_dsi1: dsi@ae96000 {
3242				compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3243				reg = <0 0x0ae96000 0 0x400>;
3244				reg-names = "dsi_ctrl";
3245
3246				interrupt-parent = <&mdss>;
3247				interrupts = <5>;
3248
3249				clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3250					 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3251					 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3252					 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3253					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3254					 <&gcc GCC_DISP_HF_AXI_CLK>;
3255				clock-names = "byte",
3256					      "byte_intf",
3257					      "pixel",
3258					      "core",
3259					      "iface",
3260					      "bus";
3261
3262				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3263				assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3264
3265				operating-points-v2 = <&mdss_dsi_opp_table>;
3266				power-domains = <&rpmhpd RPMHPD_MMCX>;
3267
3268				phys = <&mdss_dsi1_phy>;
3269				phy-names = "dsi";
3270
3271				#address-cells = <1>;
3272				#size-cells = <0>;
3273
3274				status = "disabled";
3275
3276				ports {
3277					#address-cells = <1>;
3278					#size-cells = <0>;
3279
3280					port@0 {
3281						reg = <0>;
3282						mdss_dsi1_in: endpoint {
3283							remote-endpoint = <&dpu_intf2_out>;
3284						};
3285					};
3286
3287					port@1 {
3288						reg = <1>;
3289						mdss_dsi1_out: endpoint {
3290						};
3291					};
3292				};
3293			};
3294
3295			mdss_dsi1_phy: phy@ae96400 {
3296				compatible = "qcom,sm8450-dsi-phy-5nm";
3297				reg = <0 0x0ae96400 0 0x200>,
3298				      <0 0x0ae96600 0 0x280>,
3299				      <0 0x0ae96900 0 0x260>;
3300				reg-names = "dsi_phy",
3301					    "dsi_phy_lane",
3302					    "dsi_pll";
3303
3304				#clock-cells = <1>;
3305				#phy-cells = <0>;
3306
3307				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3308					 <&rpmhcc RPMH_CXO_CLK>;
3309				clock-names = "iface", "ref";
3310
3311				status = "disabled";
3312			};
3313		};
3314
3315		dispcc: clock-controller@af00000 {
3316			compatible = "qcom,sm8450-dispcc";
3317			reg = <0 0x0af00000 0 0x20000>;
3318			clocks = <&rpmhcc RPMH_CXO_CLK>,
3319				 <&rpmhcc RPMH_CXO_CLK_A>,
3320				 <&gcc GCC_DISP_AHB_CLK>,
3321				 <&sleep_clk>,
3322				 <&mdss_dsi0_phy 0>,
3323				 <&mdss_dsi0_phy 1>,
3324				 <&mdss_dsi1_phy 0>,
3325				 <&mdss_dsi1_phy 1>,
3326				 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3327				 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3328				 <0>, /* dp1 */
3329				 <0>,
3330				 <0>, /* dp2 */
3331				 <0>,
3332				 <0>, /* dp3 */
3333				 <0>;
3334			power-domains = <&rpmhpd RPMHPD_MMCX>;
3335			required-opps = <&rpmhpd_opp_low_svs>;
3336			#clock-cells = <1>;
3337			#reset-cells = <1>;
3338			#power-domain-cells = <1>;
3339			status = "disabled";
3340		};
3341
3342		pdc: interrupt-controller@b220000 {
3343			compatible = "qcom,sm8450-pdc", "qcom,pdc";
3344			reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3345			qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3346					  <94 609 31>, <125 63 1>, <126 716 12>;
3347			#interrupt-cells = <2>;
3348			interrupt-parent = <&intc>;
3349			interrupt-controller;
3350		};
3351
3352		tsens0: thermal-sensor@c263000 {
3353			compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3354			reg = <0 0x0c263000 0 0x1000>, /* TM */
3355			      <0 0x0c222000 0 0x1000>; /* SROT */
3356			#qcom,sensors = <16>;
3357			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3358				     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3359			interrupt-names = "uplow", "critical";
3360			#thermal-sensor-cells = <1>;
3361		};
3362
3363		tsens1: thermal-sensor@c265000 {
3364			compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3365			reg = <0 0x0c265000 0 0x1000>, /* TM */
3366			      <0 0x0c223000 0 0x1000>; /* SROT */
3367			#qcom,sensors = <16>;
3368			interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3369				     <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3370			interrupt-names = "uplow", "critical";
3371			#thermal-sensor-cells = <1>;
3372		};
3373
3374		aoss_qmp: power-management@c300000 {
3375			compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3376			reg = <0 0x0c300000 0 0x400>;
3377			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3378						     IRQ_TYPE_EDGE_RISING>;
3379			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3380
3381			#clock-cells = <0>;
3382		};
3383
3384		sram@c3f0000 {
3385			compatible = "qcom,rpmh-stats";
3386			reg = <0 0x0c3f0000 0 0x400>;
3387		};
3388
3389		spmi_bus: spmi@c400000 {
3390			compatible = "qcom,spmi-pmic-arb";
3391			reg = <0 0x0c400000 0 0x00003000>,
3392			      <0 0x0c500000 0 0x00400000>,
3393			      <0 0x0c440000 0 0x00080000>,
3394			      <0 0x0c4c0000 0 0x00010000>,
3395			      <0 0x0c42d000 0 0x00010000>;
3396			reg-names = "core",
3397				    "chnls",
3398				    "obsrvr",
3399				    "intr",
3400				    "cnfg";
3401			interrupt-names = "periph_irq";
3402			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3403			qcom,ee = <0>;
3404			qcom,channel = <0>;
3405			interrupt-controller;
3406			#interrupt-cells = <4>;
3407			#address-cells = <2>;
3408			#size-cells = <0>;
3409		};
3410
3411		ipcc: mailbox@ed18000 {
3412			compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3413			reg = <0 0x0ed18000 0 0x1000>;
3414			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3415			interrupt-controller;
3416			#interrupt-cells = <3>;
3417			#mbox-cells = <2>;
3418		};
3419
3420		tlmm: pinctrl@f100000 {
3421			compatible = "qcom,sm8450-tlmm";
3422			reg = <0 0x0f100000 0 0x300000>;
3423			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3424			gpio-controller;
3425			#gpio-cells = <2>;
3426			interrupt-controller;
3427			#interrupt-cells = <2>;
3428			gpio-ranges = <&tlmm 0 0 211>;
3429			wakeup-parent = <&pdc>;
3430
3431			sdc2_default_state: sdc2-default-state {
3432				clk-pins {
3433					pins = "sdc2_clk";
3434					drive-strength = <16>;
3435					bias-disable;
3436				};
3437
3438				cmd-pins {
3439					pins = "sdc2_cmd";
3440					drive-strength = <16>;
3441					bias-pull-up;
3442				};
3443
3444				data-pins {
3445					pins = "sdc2_data";
3446					drive-strength = <16>;
3447					bias-pull-up;
3448				};
3449			};
3450
3451			sdc2_sleep_state: sdc2-sleep-state {
3452				clk-pins {
3453					pins = "sdc2_clk";
3454					drive-strength = <2>;
3455					bias-disable;
3456				};
3457
3458				cmd-pins {
3459					pins = "sdc2_cmd";
3460					drive-strength = <2>;
3461					bias-pull-up;
3462				};
3463
3464				data-pins {
3465					pins = "sdc2_data";
3466					drive-strength = <2>;
3467					bias-pull-up;
3468				};
3469			};
3470
3471			cci0_default: cci0-default-state {
3472				/* SDA, SCL */
3473				pins = "gpio110", "gpio111";
3474				function = "cci_i2c";
3475				drive-strength = <2>;
3476				bias-pull-up;
3477			};
3478
3479			cci0_sleep: cci0-sleep-state {
3480				/* SDA, SCL */
3481				pins = "gpio110", "gpio111";
3482				function = "cci_i2c";
3483				drive-strength = <2>;
3484				bias-pull-down;
3485			};
3486
3487			cci1_default: cci1-default-state {
3488				/* SDA, SCL */
3489				pins = "gpio112", "gpio113";
3490				function = "cci_i2c";
3491				drive-strength = <2>;
3492				bias-pull-up;
3493			};
3494
3495			cci1_sleep: cci1-sleep-state {
3496				/* SDA, SCL */
3497				pins = "gpio112", "gpio113";
3498				function = "cci_i2c";
3499				drive-strength = <2>;
3500				bias-pull-down;
3501			};
3502
3503			cci2_default: cci2-default-state {
3504				/* SDA, SCL */
3505				pins = "gpio114", "gpio115";
3506				function = "cci_i2c";
3507				drive-strength = <2>;
3508				bias-pull-up;
3509			};
3510
3511			cci2_sleep: cci2-sleep-state {
3512				/* SDA, SCL */
3513				pins = "gpio114", "gpio115";
3514				function = "cci_i2c";
3515				drive-strength = <2>;
3516				bias-pull-down;
3517			};
3518
3519			cci3_default: cci3-default-state {
3520				/* SDA, SCL */
3521				pins = "gpio208", "gpio209";
3522				function = "cci_i2c";
3523				drive-strength = <2>;
3524				bias-pull-up;
3525			};
3526
3527			cci3_sleep: cci3-sleep-state {
3528				/* SDA, SCL */
3529				pins = "gpio208", "gpio209";
3530				function = "cci_i2c";
3531				drive-strength = <2>;
3532				bias-pull-down;
3533			};
3534
3535			pcie0_default_state: pcie0-default-state {
3536				perst-pins {
3537					pins = "gpio94";
3538					function = "gpio";
3539					drive-strength = <2>;
3540					bias-pull-down;
3541				};
3542
3543				clkreq-pins {
3544					pins = "gpio95";
3545					function = "pcie0_clkreqn";
3546					drive-strength = <2>;
3547					bias-pull-up;
3548				};
3549
3550				wake-pins {
3551					pins = "gpio96";
3552					function = "gpio";
3553					drive-strength = <2>;
3554					bias-pull-up;
3555				};
3556			};
3557
3558			pcie1_default_state: pcie1-default-state {
3559				perst-pins {
3560					pins = "gpio97";
3561					function = "gpio";
3562					drive-strength = <2>;
3563					bias-pull-down;
3564				};
3565
3566				clkreq-pins {
3567					pins = "gpio98";
3568					function = "pcie1_clkreqn";
3569					drive-strength = <2>;
3570					bias-pull-up;
3571				};
3572
3573				wake-pins {
3574					pins = "gpio99";
3575					function = "gpio";
3576					drive-strength = <2>;
3577					bias-pull-up;
3578				};
3579			};
3580
3581			qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3582				pins = "gpio0", "gpio1";
3583				function = "qup0";
3584			};
3585
3586			qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3587				pins = "gpio4", "gpio5";
3588				function = "qup1";
3589			};
3590
3591			qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3592				pins = "gpio8", "gpio9";
3593				function = "qup2";
3594			};
3595
3596			qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3597				pins = "gpio12", "gpio13";
3598				function = "qup3";
3599			};
3600
3601			qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3602				pins = "gpio16", "gpio17";
3603				function = "qup4";
3604			};
3605
3606			qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3607				pins = "gpio206", "gpio207";
3608				function = "qup5";
3609			};
3610
3611			qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3612				pins = "gpio20", "gpio21";
3613				function = "qup6";
3614			};
3615
3616			qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3617				pins = "gpio28", "gpio29";
3618				function = "qup8";
3619			};
3620
3621			qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3622				pins = "gpio32", "gpio33";
3623				function = "qup9";
3624			};
3625
3626			qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3627				pins = "gpio36", "gpio37";
3628				function = "qup10";
3629			};
3630
3631			qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3632				pins = "gpio40", "gpio41";
3633				function = "qup11";
3634			};
3635
3636			qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3637				pins = "gpio44", "gpio45";
3638				function = "qup12";
3639			};
3640
3641			qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3642				pins = "gpio48", "gpio49";
3643				function = "qup13";
3644				drive-strength = <2>;
3645				bias-pull-up;
3646			};
3647
3648			qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3649				pins = "gpio52", "gpio53";
3650				function = "qup14";
3651				drive-strength = <2>;
3652				bias-pull-up;
3653			};
3654
3655			qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3656				pins = "gpio56", "gpio57";
3657				function = "qup15";
3658			};
3659
3660			qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3661				pins = "gpio60", "gpio61";
3662				function = "qup16";
3663			};
3664
3665			qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3666				pins = "gpio64", "gpio65";
3667				function = "qup17";
3668			};
3669
3670			qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3671				pins = "gpio68", "gpio69";
3672				function = "qup18";
3673			};
3674
3675			qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3676				pins = "gpio72", "gpio73";
3677				function = "qup19";
3678			};
3679
3680			qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3681				pins = "gpio76", "gpio77";
3682				function = "qup20";
3683			};
3684
3685			qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3686				pins = "gpio80", "gpio81";
3687				function = "qup21";
3688			};
3689
3690			qup_spi0_cs: qup-spi0-cs-state {
3691				pins = "gpio3";
3692				function = "qup0";
3693			};
3694
3695			qup_spi0_data_clk: qup-spi0-data-clk-state {
3696				pins = "gpio0", "gpio1", "gpio2";
3697				function = "qup0";
3698			};
3699
3700			qup_spi1_cs: qup-spi1-cs-state {
3701				pins = "gpio7";
3702				function = "qup1";
3703			};
3704
3705			qup_spi1_data_clk: qup-spi1-data-clk-state {
3706				pins = "gpio4", "gpio5", "gpio6";
3707				function = "qup1";
3708			};
3709
3710			qup_spi2_cs: qup-spi2-cs-state {
3711				pins = "gpio11";
3712				function = "qup2";
3713			};
3714
3715			qup_spi2_data_clk: qup-spi2-data-clk-state {
3716				pins = "gpio8", "gpio9", "gpio10";
3717				function = "qup2";
3718			};
3719
3720			qup_spi3_cs: qup-spi3-cs-state {
3721				pins = "gpio15";
3722				function = "qup3";
3723			};
3724
3725			qup_spi3_data_clk: qup-spi3-data-clk-state {
3726				pins = "gpio12", "gpio13", "gpio14";
3727				function = "qup3";
3728			};
3729
3730			qup_spi4_cs: qup-spi4-cs-state {
3731				pins = "gpio19";
3732				function = "qup4";
3733				drive-strength = <6>;
3734				bias-disable;
3735			};
3736
3737			qup_spi4_data_clk: qup-spi4-data-clk-state {
3738				pins = "gpio16", "gpio17", "gpio18";
3739				function = "qup4";
3740			};
3741
3742			qup_spi5_cs: qup-spi5-cs-state {
3743				pins = "gpio85";
3744				function = "qup5";
3745			};
3746
3747			qup_spi5_data_clk: qup-spi5-data-clk-state {
3748				pins = "gpio206", "gpio207", "gpio84";
3749				function = "qup5";
3750			};
3751
3752			qup_spi6_cs: qup-spi6-cs-state {
3753				pins = "gpio23";
3754				function = "qup6";
3755			};
3756
3757			qup_spi6_data_clk: qup-spi6-data-clk-state {
3758				pins = "gpio20", "gpio21", "gpio22";
3759				function = "qup6";
3760			};
3761
3762			qup_spi8_cs: qup-spi8-cs-state {
3763				pins = "gpio31";
3764				function = "qup8";
3765			};
3766
3767			qup_spi8_data_clk: qup-spi8-data-clk-state {
3768				pins = "gpio28", "gpio29", "gpio30";
3769				function = "qup8";
3770			};
3771
3772			qup_spi9_cs: qup-spi9-cs-state {
3773				pins = "gpio35";
3774				function = "qup9";
3775			};
3776
3777			qup_spi9_data_clk: qup-spi9-data-clk-state {
3778				pins = "gpio32", "gpio33", "gpio34";
3779				function = "qup9";
3780			};
3781
3782			qup_spi10_cs: qup-spi10-cs-state {
3783				pins = "gpio39";
3784				function = "qup10";
3785			};
3786
3787			qup_spi10_data_clk: qup-spi10-data-clk-state {
3788				pins = "gpio36", "gpio37", "gpio38";
3789				function = "qup10";
3790			};
3791
3792			qup_spi11_cs: qup-spi11-cs-state {
3793				pins = "gpio43";
3794				function = "qup11";
3795			};
3796
3797			qup_spi11_data_clk: qup-spi11-data-clk-state {
3798				pins = "gpio40", "gpio41", "gpio42";
3799				function = "qup11";
3800			};
3801
3802			qup_spi12_cs: qup-spi12-cs-state {
3803				pins = "gpio47";
3804				function = "qup12";
3805			};
3806
3807			qup_spi12_data_clk: qup-spi12-data-clk-state {
3808				pins = "gpio44", "gpio45", "gpio46";
3809				function = "qup12";
3810			};
3811
3812			qup_spi13_cs: qup-spi13-cs-state {
3813				pins = "gpio51";
3814				function = "qup13";
3815			};
3816
3817			qup_spi13_data_clk: qup-spi13-data-clk-state {
3818				pins = "gpio48", "gpio49", "gpio50";
3819				function = "qup13";
3820			};
3821
3822			qup_spi14_cs: qup-spi14-cs-state {
3823				pins = "gpio55";
3824				function = "qup14";
3825			};
3826
3827			qup_spi14_data_clk: qup-spi14-data-clk-state {
3828				pins = "gpio52", "gpio53", "gpio54";
3829				function = "qup14";
3830			};
3831
3832			qup_spi15_cs: qup-spi15-cs-state {
3833				pins = "gpio59";
3834				function = "qup15";
3835			};
3836
3837			qup_spi15_data_clk: qup-spi15-data-clk-state {
3838				pins = "gpio56", "gpio57", "gpio58";
3839				function = "qup15";
3840			};
3841
3842			qup_spi16_cs: qup-spi16-cs-state {
3843				pins = "gpio63";
3844				function = "qup16";
3845			};
3846
3847			qup_spi16_data_clk: qup-spi16-data-clk-state {
3848				pins = "gpio60", "gpio61", "gpio62";
3849				function = "qup16";
3850			};
3851
3852			qup_spi17_cs: qup-spi17-cs-state {
3853				pins = "gpio67";
3854				function = "qup17";
3855			};
3856
3857			qup_spi17_data_clk: qup-spi17-data-clk-state {
3858				pins = "gpio64", "gpio65", "gpio66";
3859				function = "qup17";
3860			};
3861
3862			qup_spi18_cs: qup-spi18-cs-state {
3863				pins = "gpio71";
3864				function = "qup18";
3865				drive-strength = <6>;
3866				bias-disable;
3867			};
3868
3869			qup_spi18_data_clk: qup-spi18-data-clk-state {
3870				pins = "gpio68", "gpio69", "gpio70";
3871				function = "qup18";
3872				drive-strength = <6>;
3873				bias-disable;
3874			};
3875
3876			qup_spi19_cs: qup-spi19-cs-state {
3877				pins = "gpio75";
3878				function = "qup19";
3879				drive-strength = <6>;
3880				bias-disable;
3881			};
3882
3883			qup_spi19_data_clk: qup-spi19-data-clk-state {
3884				pins = "gpio72", "gpio73", "gpio74";
3885				function = "qup19";
3886				drive-strength = <6>;
3887				bias-disable;
3888			};
3889
3890			qup_spi20_cs: qup-spi20-cs-state {
3891				pins = "gpio79";
3892				function = "qup20";
3893			};
3894
3895			qup_spi20_data_clk: qup-spi20-data-clk-state {
3896				pins = "gpio76", "gpio77", "gpio78";
3897				function = "qup20";
3898			};
3899
3900			qup_spi21_cs: qup-spi21-cs-state {
3901				pins = "gpio83";
3902				function = "qup21";
3903			};
3904
3905			qup_spi21_data_clk: qup-spi21-data-clk-state {
3906				pins = "gpio80", "gpio81", "gpio82";
3907				function = "qup21";
3908			};
3909
3910			qup_uart7_rx: qup-uart7-rx-state {
3911				pins = "gpio26";
3912				function = "qup7";
3913				drive-strength = <2>;
3914				bias-disable;
3915			};
3916
3917			qup_uart7_tx: qup-uart7-tx-state {
3918				pins = "gpio27";
3919				function = "qup7";
3920				drive-strength = <2>;
3921				bias-disable;
3922			};
3923
3924			qup_uart20_default: qup-uart20-default-state {
3925				pins = "gpio76", "gpio77", "gpio78", "gpio79";
3926				function = "qup20";
3927			};
3928		};
3929
3930		lpass_tlmm: pinctrl@3440000 {
3931			compatible = "qcom,sm8450-lpass-lpi-pinctrl";
3932			reg = <0 0x03440000 0x0 0x20000>,
3933			      <0 0x034d0000 0x0 0x10000>;
3934			gpio-controller;
3935			#gpio-cells = <2>;
3936			gpio-ranges = <&lpass_tlmm 0 0 23>;
3937
3938			clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3939				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3940			clock-names = "core", "audio";
3941
3942			tx_swr_active: tx-swr-active-state {
3943				clk-pins {
3944					pins = "gpio0";
3945					function = "swr_tx_clk";
3946					drive-strength = <2>;
3947					slew-rate = <1>;
3948					bias-disable;
3949				};
3950
3951				data-pins {
3952					pins = "gpio1", "gpio2", "gpio14";
3953					function = "swr_tx_data";
3954					drive-strength = <2>;
3955					slew-rate = <1>;
3956					bias-bus-hold;
3957				};
3958			};
3959
3960			rx_swr_active: rx-swr-active-state {
3961				clk-pins {
3962					pins = "gpio3";
3963					function = "swr_rx_clk";
3964					drive-strength = <2>;
3965					slew-rate = <1>;
3966					bias-disable;
3967				};
3968
3969				data-pins {
3970					pins = "gpio4", "gpio5";
3971					function = "swr_rx_data";
3972					drive-strength = <2>;
3973					slew-rate = <1>;
3974					bias-bus-hold;
3975				};
3976			};
3977
3978			dmic01_default: dmic01-default-state {
3979				clk-pins {
3980					pins = "gpio6";
3981					function = "dmic1_clk";
3982					drive-strength = <8>;
3983					output-high;
3984				};
3985
3986				data-pins {
3987					pins = "gpio7";
3988					function = "dmic1_data";
3989					drive-strength = <8>;
3990				};
3991			};
3992
3993			dmic23_default: dmic23-default-state {
3994				clk-pins {
3995					pins = "gpio8";
3996					function = "dmic2_clk";
3997					drive-strength = <8>;
3998					output-high;
3999				};
4000
4001				data-pins {
4002					pins = "gpio9";
4003					function = "dmic2_data";
4004					drive-strength = <8>;
4005				};
4006			};
4007
4008			wsa_swr_active: wsa-swr-active-state {
4009				clk-pins {
4010					pins = "gpio10";
4011					function = "wsa_swr_clk";
4012					drive-strength = <2>;
4013					slew-rate = <1>;
4014					bias-disable;
4015				};
4016
4017				data-pins {
4018					pins = "gpio11";
4019					function = "wsa_swr_data";
4020					drive-strength = <2>;
4021					slew-rate = <1>;
4022					bias-bus-hold;
4023				};
4024			};
4025
4026			wsa2_swr_active: wsa2-swr-active-state {
4027				clk-pins {
4028					pins = "gpio15";
4029					function = "wsa2_swr_clk";
4030					drive-strength = <2>;
4031					slew-rate = <1>;
4032					bias-disable;
4033				};
4034
4035				data-pins {
4036					pins = "gpio16";
4037					function = "wsa2_swr_data";
4038					drive-strength = <2>;
4039					slew-rate = <1>;
4040					bias-bus-hold;
4041				};
4042			};
4043		};
4044
4045		sram@146aa000 {
4046			compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
4047			reg = <0 0x146aa000 0 0x1000>;
4048			ranges = <0 0 0x146aa000 0x1000>;
4049
4050			#address-cells = <1>;
4051			#size-cells = <1>;
4052
4053			pil-reloc@94c {
4054				compatible = "qcom,pil-reloc-info";
4055				reg = <0x94c 0xc8>;
4056			};
4057		};
4058
4059		apps_smmu: iommu@15000000 {
4060			compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
4061			reg = <0 0x15000000 0 0x100000>;
4062			#iommu-cells = <2>;
4063			#global-interrupts = <1>;
4064			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4065				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4066				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4067				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4068				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4069				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4070				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4071				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4072				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4073				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4074				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4075				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4076				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4077				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4078				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4079				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4080				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4081				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4082				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4083				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4084				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4085				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4086				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4087				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4088				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4089				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4090				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4091				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4092				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4093				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4094				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4095				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4096				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4097				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4098				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4099				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4100				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4101				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4102				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4103				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4104				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4105				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4106				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4107				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4108				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4109				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4110				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4111				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4112				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4113				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4114				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4115				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4116				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4117				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4118				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4119				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4120				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4121				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4122				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4123				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4124				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4125				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4126				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4127				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4128				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4129				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4130				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4131				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4132				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4133				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4134				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4135				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4136				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4137				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4138				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4139				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4140				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4141				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4142				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4143				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4144				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4145				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4146				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4147				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4148				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4149				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4150				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4151				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4152				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4153				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4154				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4155				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4156				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4157				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4158				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4159				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4160				     <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
4161		};
4162
4163		intc: interrupt-controller@17100000 {
4164			compatible = "arm,gic-v3";
4165			#interrupt-cells = <3>;
4166			interrupt-controller;
4167			#redistributor-regions = <1>;
4168			redistributor-stride = <0x0 0x40000>;
4169			reg = <0x0 0x17100000 0x0 0x10000>,     /* GICD */
4170			      <0x0 0x17180000 0x0 0x200000>;    /* GICR * 8 */
4171			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4172			#address-cells = <2>;
4173			#size-cells = <2>;
4174			ranges;
4175
4176			gic_its: msi-controller@17140000 {
4177				compatible = "arm,gic-v3-its";
4178				reg = <0x0 0x17140000 0x0 0x20000>;
4179				msi-controller;
4180				#msi-cells = <1>;
4181			};
4182		};
4183
4184		timer@17420000 {
4185			compatible = "arm,armv7-timer-mem";
4186			#address-cells = <1>;
4187			#size-cells = <1>;
4188			ranges = <0 0 0 0x20000000>;
4189			reg = <0x0 0x17420000 0x0 0x1000>;
4190			clock-frequency = <19200000>;
4191
4192			frame@17421000 {
4193				frame-number = <0>;
4194				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4195					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4196				reg = <0x17421000 0x1000>,
4197				      <0x17422000 0x1000>;
4198			};
4199
4200			frame@17423000 {
4201				frame-number = <1>;
4202				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4203				reg = <0x17423000 0x1000>;
4204				status = "disabled";
4205			};
4206
4207			frame@17425000 {
4208				frame-number = <2>;
4209				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4210				reg = <0x17425000 0x1000>;
4211				status = "disabled";
4212			};
4213
4214			frame@17427000 {
4215				frame-number = <3>;
4216				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4217				reg = <0x17427000 0x1000>;
4218				status = "disabled";
4219			};
4220
4221			frame@17429000 {
4222				frame-number = <4>;
4223				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4224				reg = <0x17429000 0x1000>;
4225				status = "disabled";
4226			};
4227
4228			frame@1742b000 {
4229				frame-number = <5>;
4230				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4231				reg = <0x1742b000 0x1000>;
4232				status = "disabled";
4233			};
4234
4235			frame@1742d000 {
4236				frame-number = <6>;
4237				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4238				reg = <0x1742d000 0x1000>;
4239				status = "disabled";
4240			};
4241		};
4242
4243		apps_rsc: rsc@17a00000 {
4244			label = "apps_rsc";
4245			compatible = "qcom,rpmh-rsc";
4246			reg = <0x0 0x17a00000 0x0 0x10000>,
4247			      <0x0 0x17a10000 0x0 0x10000>,
4248			      <0x0 0x17a20000 0x0 0x10000>,
4249			      <0x0 0x17a30000 0x0 0x10000>;
4250			reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4251			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4252				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4253				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4254			qcom,tcs-offset = <0xd00>;
4255			qcom,drv-id = <2>;
4256			qcom,tcs-config = <ACTIVE_TCS  3>, <SLEEP_TCS   2>,
4257					  <WAKE_TCS    2>, <CONTROL_TCS 0>;
4258			power-domains = <&CLUSTER_PD>;
4259
4260			apps_bcm_voter: bcm-voter {
4261				compatible = "qcom,bcm-voter";
4262			};
4263
4264			rpmhcc: clock-controller {
4265				compatible = "qcom,sm8450-rpmh-clk";
4266				#clock-cells = <1>;
4267				clock-names = "xo";
4268				clocks = <&xo_board>;
4269			};
4270
4271			rpmhpd: power-controller {
4272				compatible = "qcom,sm8450-rpmhpd";
4273				#power-domain-cells = <1>;
4274				operating-points-v2 = <&rpmhpd_opp_table>;
4275
4276				rpmhpd_opp_table: opp-table {
4277					compatible = "operating-points-v2";
4278
4279					rpmhpd_opp_ret: opp1 {
4280						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4281					};
4282
4283					rpmhpd_opp_min_svs: opp2 {
4284						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4285					};
4286
4287					rpmhpd_opp_low_svs_d1: opp3 {
4288						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4289					};
4290
4291					rpmhpd_opp_low_svs: opp4 {
4292						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4293					};
4294
4295					rpmhpd_opp_low_svs_l1: opp5 {
4296						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4297					};
4298
4299					rpmhpd_opp_svs: opp6 {
4300						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4301					};
4302
4303					rpmhpd_opp_svs_l0: opp7 {
4304						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4305					};
4306
4307					rpmhpd_opp_svs_l1: opp8 {
4308						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4309					};
4310
4311					rpmhpd_opp_svs_l2: opp9 {
4312						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4313					};
4314
4315					rpmhpd_opp_nom: opp10 {
4316						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4317					};
4318
4319					rpmhpd_opp_nom_l1: opp11 {
4320						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4321					};
4322
4323					rpmhpd_opp_nom_l2: opp12 {
4324						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4325					};
4326
4327					rpmhpd_opp_turbo: opp13 {
4328						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4329					};
4330
4331					rpmhpd_opp_turbo_l1: opp14 {
4332						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4333					};
4334				};
4335			};
4336		};
4337
4338		cpufreq_hw: cpufreq@17d91000 {
4339			compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4340			reg = <0 0x17d91000 0 0x1000>,
4341			      <0 0x17d92000 0 0x1000>,
4342			      <0 0x17d93000 0 0x1000>;
4343			reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4344			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4345			clock-names = "xo", "alternate";
4346			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4347				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4348				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4349			interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4350			#freq-domain-cells = <1>;
4351			#clock-cells = <1>;
4352		};
4353
4354		gem_noc: interconnect@19100000 {
4355			compatible = "qcom,sm8450-gem-noc";
4356			reg = <0 0x19100000 0 0xbb800>;
4357			#interconnect-cells = <2>;
4358			qcom,bcm-voters = <&apps_bcm_voter>;
4359		};
4360
4361		system-cache-controller@19200000 {
4362			compatible = "qcom,sm8450-llcc";
4363			reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4364			      <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4365			      <0 0x19a00000 0 0x80000>;
4366			reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4367				    "llcc3_base", "llcc_broadcast_base";
4368			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4369		};
4370
4371		ufs_mem_hc: ufshc@1d84000 {
4372			compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4373				     "jedec,ufs-2.0";
4374			reg = <0 0x01d84000 0 0x3000>;
4375			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4376			phys = <&ufs_mem_phy>;
4377			phy-names = "ufsphy";
4378			lanes-per-direction = <2>;
4379			#reset-cells = <1>;
4380			resets = <&gcc GCC_UFS_PHY_BCR>;
4381			reset-names = "rst";
4382
4383			power-domains = <&gcc UFS_PHY_GDSC>;
4384
4385			iommus = <&apps_smmu 0xe0 0x0>;
4386			dma-coherent;
4387
4388			interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4389					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4390			interconnect-names = "ufs-ddr", "cpu-ufs";
4391			clock-names =
4392				"core_clk",
4393				"bus_aggr_clk",
4394				"iface_clk",
4395				"core_clk_unipro",
4396				"ref_clk",
4397				"tx_lane0_sync_clk",
4398				"rx_lane0_sync_clk",
4399				"rx_lane1_sync_clk";
4400			clocks =
4401				<&gcc GCC_UFS_PHY_AXI_CLK>,
4402				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4403				<&gcc GCC_UFS_PHY_AHB_CLK>,
4404				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4405				<&rpmhcc RPMH_CXO_CLK>,
4406				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4407				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4408				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
4409			freq-table-hz =
4410				<75000000 300000000>,
4411				<0 0>,
4412				<0 0>,
4413				<75000000 300000000>,
4414				<75000000 300000000>,
4415				<0 0>,
4416				<0 0>,
4417				<0 0>;
4418			qcom,ice = <&ice>;
4419
4420			status = "disabled";
4421		};
4422
4423		ufs_mem_phy: phy@1d87000 {
4424			compatible = "qcom,sm8450-qmp-ufs-phy";
4425			reg = <0 0x01d87000 0 0x1000>;
4426
4427			clock-names = "ref", "ref_aux", "qref";
4428			clocks = <&rpmhcc RPMH_CXO_CLK>,
4429				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4430				 <&gcc GCC_UFS_0_CLKREF_EN>;
4431
4432			resets = <&ufs_mem_hc 0>;
4433			reset-names = "ufsphy";
4434
4435			#clock-cells = <1>;
4436			#phy-cells = <0>;
4437
4438			status = "disabled";
4439		};
4440
4441		ice: crypto@1d88000 {
4442			compatible = "qcom,sm8450-inline-crypto-engine",
4443				     "qcom,inline-crypto-engine";
4444			reg = <0 0x01d88000 0 0x8000>;
4445			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4446		};
4447
4448		cryptobam: dma-controller@1dc4000 {
4449			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4450			reg = <0 0x01dc4000 0 0x28000>;
4451			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
4452			#dma-cells = <1>;
4453			qcom,ee = <0>;
4454			qcom,controlled-remotely;
4455			iommus = <&apps_smmu 0x584 0x11>,
4456				 <&apps_smmu 0x588 0x0>,
4457				 <&apps_smmu 0x598 0x5>,
4458				 <&apps_smmu 0x59a 0x0>,
4459				 <&apps_smmu 0x59f 0x0>;
4460		};
4461
4462		crypto: crypto@1dfa000 {
4463			compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4464			reg = <0 0x01dfa000 0 0x6000>;
4465			dmas = <&cryptobam 4>, <&cryptobam 5>;
4466			dma-names = "rx", "tx";
4467			iommus = <&apps_smmu 0x584 0x11>,
4468				 <&apps_smmu 0x588 0x0>,
4469				 <&apps_smmu 0x598 0x5>,
4470				 <&apps_smmu 0x59a 0x0>,
4471				 <&apps_smmu 0x59f 0x0>;
4472			interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
4473			interconnect-names = "memory";
4474		};
4475
4476		sdhc_2: mmc@8804000 {
4477			compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4478			reg = <0 0x08804000 0 0x1000>;
4479
4480			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
4481				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
4482			interrupt-names = "hc_irq", "pwr_irq";
4483
4484			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4485				 <&gcc GCC_SDCC2_APPS_CLK>,
4486				 <&rpmhcc RPMH_CXO_CLK>;
4487			clock-names = "iface", "core", "xo";
4488			resets = <&gcc GCC_SDCC2_BCR>;
4489			interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4490					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4491			interconnect-names = "sdhc-ddr","cpu-sdhc";
4492			iommus = <&apps_smmu 0x4a0 0x0>;
4493			power-domains = <&rpmhpd RPMHPD_CX>;
4494			operating-points-v2 = <&sdhc2_opp_table>;
4495			bus-width = <4>;
4496			dma-coherent;
4497
4498			/* Forbid SDR104/SDR50 - broken hw! */
4499			sdhci-caps-mask = <0x3 0x0>;
4500
4501			status = "disabled";
4502
4503			sdhc2_opp_table: opp-table {
4504				compatible = "operating-points-v2";
4505
4506				opp-100000000 {
4507					opp-hz = /bits/ 64 <100000000>;
4508					required-opps = <&rpmhpd_opp_low_svs>;
4509				};
4510
4511				opp-202000000 {
4512					opp-hz = /bits/ 64 <202000000>;
4513					required-opps = <&rpmhpd_opp_svs_l1>;
4514				};
4515			};
4516		};
4517
4518		usb_1: usb@a6f8800 {
4519			compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4520			reg = <0 0x0a6f8800 0 0x400>;
4521			status = "disabled";
4522			#address-cells = <2>;
4523			#size-cells = <2>;
4524			ranges;
4525
4526			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4527				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4528				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4529				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4530				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4531				 <&gcc GCC_USB3_0_CLKREF_EN>;
4532			clock-names = "cfg_noc",
4533				      "core",
4534				      "iface",
4535				      "sleep",
4536				      "mock_utmi",
4537				      "xo";
4538
4539			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4540					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4541			assigned-clock-rates = <19200000>, <200000000>;
4542
4543			interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4544					      <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4545					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4546					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4547					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4548			interrupt-names = "pwr_event",
4549					  "hs_phy_irq",
4550					  "dp_hs_phy_irq",
4551					  "dm_hs_phy_irq",
4552					  "ss_phy_irq";
4553
4554			power-domains = <&gcc USB30_PRIM_GDSC>;
4555
4556			resets = <&gcc GCC_USB30_PRIM_BCR>;
4557
4558			interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4559					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4560			interconnect-names = "usb-ddr", "apps-usb";
4561
4562			usb_1_dwc3: usb@a600000 {
4563				compatible = "snps,dwc3";
4564				reg = <0 0x0a600000 0 0xcd00>;
4565				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4566				iommus = <&apps_smmu 0x0 0x0>;
4567				snps,dis_u2_susphy_quirk;
4568				snps,dis_enblslpm_quirk;
4569				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4570				phy-names = "usb2-phy", "usb3-phy";
4571
4572				ports {
4573					#address-cells = <1>;
4574					#size-cells = <0>;
4575
4576					port@0 {
4577						reg = <0>;
4578
4579						usb_1_dwc3_hs: endpoint {
4580						};
4581					};
4582
4583					port@1 {
4584						reg = <1>;
4585
4586						usb_1_dwc3_ss: endpoint {
4587						};
4588					};
4589				};
4590			};
4591		};
4592
4593		nsp_noc: interconnect@320c0000 {
4594			compatible = "qcom,sm8450-nsp-noc";
4595			reg = <0 0x320c0000 0 0x10000>;
4596			#interconnect-cells = <2>;
4597			qcom,bcm-voters = <&apps_bcm_voter>;
4598		};
4599
4600		lpass_ag_noc: interconnect@3c40000 {
4601			compatible = "qcom,sm8450-lpass-ag-noc";
4602			reg = <0 0x03c40000 0 0x17200>;
4603			#interconnect-cells = <2>;
4604			qcom,bcm-voters = <&apps_bcm_voter>;
4605		};
4606	};
4607
4608	sound: sound {
4609	};
4610
4611	thermal-zones {
4612		aoss0-thermal {
4613			polling-delay-passive = <0>;
4614			polling-delay = <0>;
4615			thermal-sensors = <&tsens0 0>;
4616
4617			trips {
4618				thermal-engine-config {
4619					temperature = <125000>;
4620					hysteresis = <1000>;
4621					type = "passive";
4622				};
4623
4624				reset-mon-cfg {
4625					temperature = <115000>;
4626					hysteresis = <5000>;
4627					type = "passive";
4628				};
4629			};
4630		};
4631
4632		cpuss0-thermal {
4633			polling-delay-passive = <0>;
4634			polling-delay = <0>;
4635			thermal-sensors = <&tsens0 1>;
4636
4637			trips {
4638				thermal-engine-config {
4639					temperature = <125000>;
4640					hysteresis = <1000>;
4641					type = "passive";
4642				};
4643
4644				reset-mon-cfg {
4645					temperature = <115000>;
4646					hysteresis = <5000>;
4647					type = "passive";
4648				};
4649			};
4650		};
4651
4652		cpuss1-thermal {
4653			polling-delay-passive = <0>;
4654			polling-delay = <0>;
4655			thermal-sensors = <&tsens0 2>;
4656
4657			trips {
4658				thermal-engine-config {
4659					temperature = <125000>;
4660					hysteresis = <1000>;
4661					type = "passive";
4662				};
4663
4664				reset-mon-cfg {
4665					temperature = <115000>;
4666					hysteresis = <5000>;
4667					type = "passive";
4668				};
4669			};
4670		};
4671
4672		cpuss3-thermal {
4673			polling-delay-passive = <0>;
4674			polling-delay = <0>;
4675			thermal-sensors = <&tsens0 3>;
4676
4677			trips {
4678				thermal-engine-config {
4679					temperature = <125000>;
4680					hysteresis = <1000>;
4681					type = "passive";
4682				};
4683
4684				reset-mon-cfg {
4685					temperature = <115000>;
4686					hysteresis = <5000>;
4687					type = "passive";
4688				};
4689			};
4690		};
4691
4692		cpuss4-thermal {
4693			polling-delay-passive = <0>;
4694			polling-delay = <0>;
4695			thermal-sensors = <&tsens0 4>;
4696
4697			trips {
4698				thermal-engine-config {
4699					temperature = <125000>;
4700					hysteresis = <1000>;
4701					type = "passive";
4702				};
4703
4704				reset-mon-cfg {
4705					temperature = <115000>;
4706					hysteresis = <5000>;
4707					type = "passive";
4708				};
4709			};
4710		};
4711
4712		cpu4-top-thermal {
4713			polling-delay-passive = <0>;
4714			polling-delay = <0>;
4715			thermal-sensors = <&tsens0 5>;
4716
4717			trips {
4718				cpu4_top_alert0: trip-point0 {
4719					temperature = <90000>;
4720					hysteresis = <2000>;
4721					type = "passive";
4722				};
4723
4724				cpu4_top_alert1: trip-point1 {
4725					temperature = <95000>;
4726					hysteresis = <2000>;
4727					type = "passive";
4728				};
4729
4730				cpu4_top_crit: cpu-crit {
4731					temperature = <110000>;
4732					hysteresis = <1000>;
4733					type = "critical";
4734				};
4735			};
4736		};
4737
4738		cpu4-bottom-thermal {
4739			polling-delay-passive = <0>;
4740			polling-delay = <0>;
4741			thermal-sensors = <&tsens0 6>;
4742
4743			trips {
4744				cpu4_bottom_alert0: trip-point0 {
4745					temperature = <90000>;
4746					hysteresis = <2000>;
4747					type = "passive";
4748				};
4749
4750				cpu4_bottom_alert1: trip-point1 {
4751					temperature = <95000>;
4752					hysteresis = <2000>;
4753					type = "passive";
4754				};
4755
4756				cpu4_bottom_crit: cpu-crit {
4757					temperature = <110000>;
4758					hysteresis = <1000>;
4759					type = "critical";
4760				};
4761			};
4762		};
4763
4764		cpu5-top-thermal {
4765			polling-delay-passive = <0>;
4766			polling-delay = <0>;
4767			thermal-sensors = <&tsens0 7>;
4768
4769			trips {
4770				cpu5_top_alert0: trip-point0 {
4771					temperature = <90000>;
4772					hysteresis = <2000>;
4773					type = "passive";
4774				};
4775
4776				cpu5_top_alert1: trip-point1 {
4777					temperature = <95000>;
4778					hysteresis = <2000>;
4779					type = "passive";
4780				};
4781
4782				cpu5_top_crit: cpu-crit {
4783					temperature = <110000>;
4784					hysteresis = <1000>;
4785					type = "critical";
4786				};
4787			};
4788		};
4789
4790		cpu5-bottom-thermal {
4791			polling-delay-passive = <0>;
4792			polling-delay = <0>;
4793			thermal-sensors = <&tsens0 8>;
4794
4795			trips {
4796				cpu5_bottom_alert0: trip-point0 {
4797					temperature = <90000>;
4798					hysteresis = <2000>;
4799					type = "passive";
4800				};
4801
4802				cpu5_bottom_alert1: trip-point1 {
4803					temperature = <95000>;
4804					hysteresis = <2000>;
4805					type = "passive";
4806				};
4807
4808				cpu5_bottom_crit: cpu-crit {
4809					temperature = <110000>;
4810					hysteresis = <1000>;
4811					type = "critical";
4812				};
4813			};
4814		};
4815
4816		cpu6-top-thermal {
4817			polling-delay-passive = <0>;
4818			polling-delay = <0>;
4819			thermal-sensors = <&tsens0 9>;
4820
4821			trips {
4822				cpu6_top_alert0: trip-point0 {
4823					temperature = <90000>;
4824					hysteresis = <2000>;
4825					type = "passive";
4826				};
4827
4828				cpu6_top_alert1: trip-point1 {
4829					temperature = <95000>;
4830					hysteresis = <2000>;
4831					type = "passive";
4832				};
4833
4834				cpu6_top_crit: cpu-crit {
4835					temperature = <110000>;
4836					hysteresis = <1000>;
4837					type = "critical";
4838				};
4839			};
4840		};
4841
4842		cpu6-bottom-thermal {
4843			polling-delay-passive = <0>;
4844			polling-delay = <0>;
4845			thermal-sensors = <&tsens0 10>;
4846
4847			trips {
4848				cpu6_bottom_alert0: trip-point0 {
4849					temperature = <90000>;
4850					hysteresis = <2000>;
4851					type = "passive";
4852				};
4853
4854				cpu6_bottom_alert1: trip-point1 {
4855					temperature = <95000>;
4856					hysteresis = <2000>;
4857					type = "passive";
4858				};
4859
4860				cpu6_bottom_crit: cpu-crit {
4861					temperature = <110000>;
4862					hysteresis = <1000>;
4863					type = "critical";
4864				};
4865			};
4866		};
4867
4868		cpu7-top-thermal {
4869			polling-delay-passive = <0>;
4870			polling-delay = <0>;
4871			thermal-sensors = <&tsens0 11>;
4872
4873			trips {
4874				cpu7_top_alert0: trip-point0 {
4875					temperature = <90000>;
4876					hysteresis = <2000>;
4877					type = "passive";
4878				};
4879
4880				cpu7_top_alert1: trip-point1 {
4881					temperature = <95000>;
4882					hysteresis = <2000>;
4883					type = "passive";
4884				};
4885
4886				cpu7_top_crit: cpu-crit {
4887					temperature = <110000>;
4888					hysteresis = <1000>;
4889					type = "critical";
4890				};
4891			};
4892		};
4893
4894		cpu7-middle-thermal {
4895			polling-delay-passive = <0>;
4896			polling-delay = <0>;
4897			thermal-sensors = <&tsens0 12>;
4898
4899			trips {
4900				cpu7_middle_alert0: trip-point0 {
4901					temperature = <90000>;
4902					hysteresis = <2000>;
4903					type = "passive";
4904				};
4905
4906				cpu7_middle_alert1: trip-point1 {
4907					temperature = <95000>;
4908					hysteresis = <2000>;
4909					type = "passive";
4910				};
4911
4912				cpu7_middle_crit: cpu-crit {
4913					temperature = <110000>;
4914					hysteresis = <1000>;
4915					type = "critical";
4916				};
4917			};
4918		};
4919
4920		cpu7-bottom-thermal {
4921			polling-delay-passive = <0>;
4922			polling-delay = <0>;
4923			thermal-sensors = <&tsens0 13>;
4924
4925			trips {
4926				cpu7_bottom_alert0: trip-point0 {
4927					temperature = <90000>;
4928					hysteresis = <2000>;
4929					type = "passive";
4930				};
4931
4932				cpu7_bottom_alert1: trip-point1 {
4933					temperature = <95000>;
4934					hysteresis = <2000>;
4935					type = "passive";
4936				};
4937
4938				cpu7_bottom_crit: cpu-crit {
4939					temperature = <110000>;
4940					hysteresis = <1000>;
4941					type = "critical";
4942				};
4943			};
4944		};
4945
4946		gpu-top-thermal {
4947			polling-delay-passive = <10>;
4948			polling-delay = <0>;
4949			thermal-sensors = <&tsens0 14>;
4950
4951			cooling-maps {
4952				map0 {
4953					trip = <&gpu_top_alert0>;
4954					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4955				};
4956			};
4957
4958			trips {
4959				thermal-engine-config {
4960					temperature = <125000>;
4961					hysteresis = <1000>;
4962					type = "passive";
4963				};
4964
4965				thermal-hal-config {
4966					temperature = <125000>;
4967					hysteresis = <1000>;
4968					type = "passive";
4969				};
4970
4971				reset-mon-cfg {
4972					temperature = <115000>;
4973					hysteresis = <5000>;
4974					type = "passive";
4975				};
4976
4977				gpu_top_alert0: trip-point0 {
4978					temperature = <95000>;
4979					hysteresis = <5000>;
4980					type = "passive";
4981				};
4982			};
4983		};
4984
4985		gpu-bottom-thermal {
4986			polling-delay-passive = <10>;
4987			polling-delay = <0>;
4988			thermal-sensors = <&tsens0 15>;
4989
4990			cooling-maps {
4991				map0 {
4992					trip = <&gpu_bottom_alert0>;
4993					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4994				};
4995			};
4996
4997			trips {
4998				thermal-engine-config {
4999					temperature = <125000>;
5000					hysteresis = <1000>;
5001					type = "passive";
5002				};
5003
5004				thermal-hal-config {
5005					temperature = <125000>;
5006					hysteresis = <1000>;
5007					type = "passive";
5008				};
5009
5010				reset-mon-cfg {
5011					temperature = <115000>;
5012					hysteresis = <5000>;
5013					type = "passive";
5014				};
5015
5016				gpu_bottom_alert0: trip-point0 {
5017					temperature = <95000>;
5018					hysteresis = <5000>;
5019					type = "passive";
5020				};
5021			};
5022		};
5023
5024		aoss1-thermal {
5025			polling-delay-passive = <0>;
5026			polling-delay = <0>;
5027			thermal-sensors = <&tsens1 0>;
5028
5029			trips {
5030				thermal-engine-config {
5031					temperature = <125000>;
5032					hysteresis = <1000>;
5033					type = "passive";
5034				};
5035
5036				reset-mon-cfg {
5037					temperature = <115000>;
5038					hysteresis = <5000>;
5039					type = "passive";
5040				};
5041			};
5042		};
5043
5044		cpu0-thermal {
5045			polling-delay-passive = <0>;
5046			polling-delay = <0>;
5047			thermal-sensors = <&tsens1 1>;
5048
5049			trips {
5050				cpu0_alert0: trip-point0 {
5051					temperature = <90000>;
5052					hysteresis = <2000>;
5053					type = "passive";
5054				};
5055
5056				cpu0_alert1: trip-point1 {
5057					temperature = <95000>;
5058					hysteresis = <2000>;
5059					type = "passive";
5060				};
5061
5062				cpu0_crit: cpu-crit {
5063					temperature = <110000>;
5064					hysteresis = <1000>;
5065					type = "critical";
5066				};
5067			};
5068		};
5069
5070		cpu1-thermal {
5071			polling-delay-passive = <0>;
5072			polling-delay = <0>;
5073			thermal-sensors = <&tsens1 2>;
5074
5075			trips {
5076				cpu1_alert0: trip-point0 {
5077					temperature = <90000>;
5078					hysteresis = <2000>;
5079					type = "passive";
5080				};
5081
5082				cpu1_alert1: trip-point1 {
5083					temperature = <95000>;
5084					hysteresis = <2000>;
5085					type = "passive";
5086				};
5087
5088				cpu1_crit: cpu-crit {
5089					temperature = <110000>;
5090					hysteresis = <1000>;
5091					type = "critical";
5092				};
5093			};
5094		};
5095
5096		cpu2-thermal {
5097			polling-delay-passive = <0>;
5098			polling-delay = <0>;
5099			thermal-sensors = <&tsens1 3>;
5100
5101			trips {
5102				cpu2_alert0: trip-point0 {
5103					temperature = <90000>;
5104					hysteresis = <2000>;
5105					type = "passive";
5106				};
5107
5108				cpu2_alert1: trip-point1 {
5109					temperature = <95000>;
5110					hysteresis = <2000>;
5111					type = "passive";
5112				};
5113
5114				cpu2_crit: cpu-crit {
5115					temperature = <110000>;
5116					hysteresis = <1000>;
5117					type = "critical";
5118				};
5119			};
5120		};
5121
5122		cpu3-thermal {
5123			polling-delay-passive = <0>;
5124			polling-delay = <0>;
5125			thermal-sensors = <&tsens1 4>;
5126
5127			trips {
5128				cpu3_alert0: trip-point0 {
5129					temperature = <90000>;
5130					hysteresis = <2000>;
5131					type = "passive";
5132				};
5133
5134				cpu3_alert1: trip-point1 {
5135					temperature = <95000>;
5136					hysteresis = <2000>;
5137					type = "passive";
5138				};
5139
5140				cpu3_crit: cpu-crit {
5141					temperature = <110000>;
5142					hysteresis = <1000>;
5143					type = "critical";
5144				};
5145			};
5146		};
5147
5148		cdsp0-thermal {
5149			polling-delay-passive = <10>;
5150			polling-delay = <0>;
5151			thermal-sensors = <&tsens1 5>;
5152
5153			trips {
5154				thermal-engine-config {
5155					temperature = <125000>;
5156					hysteresis = <1000>;
5157					type = "passive";
5158				};
5159
5160				thermal-hal-config {
5161					temperature = <125000>;
5162					hysteresis = <1000>;
5163					type = "passive";
5164				};
5165
5166				reset-mon-cfg {
5167					temperature = <115000>;
5168					hysteresis = <5000>;
5169					type = "passive";
5170				};
5171
5172				cdsp_0_config: junction-config {
5173					temperature = <95000>;
5174					hysteresis = <5000>;
5175					type = "passive";
5176				};
5177			};
5178		};
5179
5180		cdsp1-thermal {
5181			polling-delay-passive = <10>;
5182			polling-delay = <0>;
5183			thermal-sensors = <&tsens1 6>;
5184
5185			trips {
5186				thermal-engine-config {
5187					temperature = <125000>;
5188					hysteresis = <1000>;
5189					type = "passive";
5190				};
5191
5192				thermal-hal-config {
5193					temperature = <125000>;
5194					hysteresis = <1000>;
5195					type = "passive";
5196				};
5197
5198				reset-mon-cfg {
5199					temperature = <115000>;
5200					hysteresis = <5000>;
5201					type = "passive";
5202				};
5203
5204				cdsp_1_config: junction-config {
5205					temperature = <95000>;
5206					hysteresis = <5000>;
5207					type = "passive";
5208				};
5209			};
5210		};
5211
5212		cdsp2-thermal {
5213			polling-delay-passive = <10>;
5214			polling-delay = <0>;
5215			thermal-sensors = <&tsens1 7>;
5216
5217			trips {
5218				thermal-engine-config {
5219					temperature = <125000>;
5220					hysteresis = <1000>;
5221					type = "passive";
5222				};
5223
5224				thermal-hal-config {
5225					temperature = <125000>;
5226					hysteresis = <1000>;
5227					type = "passive";
5228				};
5229
5230				reset-mon-cfg {
5231					temperature = <115000>;
5232					hysteresis = <5000>;
5233					type = "passive";
5234				};
5235
5236				cdsp_2_config: junction-config {
5237					temperature = <95000>;
5238					hysteresis = <5000>;
5239					type = "passive";
5240				};
5241			};
5242		};
5243
5244		video-thermal {
5245			polling-delay-passive = <0>;
5246			polling-delay = <0>;
5247			thermal-sensors = <&tsens1 8>;
5248
5249			trips {
5250				thermal-engine-config {
5251					temperature = <125000>;
5252					hysteresis = <1000>;
5253					type = "passive";
5254				};
5255
5256				reset-mon-cfg {
5257					temperature = <115000>;
5258					hysteresis = <5000>;
5259					type = "passive";
5260				};
5261			};
5262		};
5263
5264		mem-thermal {
5265			polling-delay-passive = <10>;
5266			polling-delay = <0>;
5267			thermal-sensors = <&tsens1 9>;
5268
5269			trips {
5270				thermal-engine-config {
5271					temperature = <125000>;
5272					hysteresis = <1000>;
5273					type = "passive";
5274				};
5275
5276				ddr_config0: ddr0-config {
5277					temperature = <90000>;
5278					hysteresis = <5000>;
5279					type = "passive";
5280				};
5281
5282				reset-mon-cfg {
5283					temperature = <115000>;
5284					hysteresis = <5000>;
5285					type = "passive";
5286				};
5287			};
5288		};
5289
5290		modem0-thermal {
5291			polling-delay-passive = <0>;
5292			polling-delay = <0>;
5293			thermal-sensors = <&tsens1 10>;
5294
5295			trips {
5296				thermal-engine-config {
5297					temperature = <125000>;
5298					hysteresis = <1000>;
5299					type = "passive";
5300				};
5301
5302				mdmss0_config0: mdmss0-config0 {
5303					temperature = <102000>;
5304					hysteresis = <3000>;
5305					type = "passive";
5306				};
5307
5308				mdmss0_config1: mdmss0-config1 {
5309					temperature = <105000>;
5310					hysteresis = <3000>;
5311					type = "passive";
5312				};
5313
5314				reset-mon-cfg {
5315					temperature = <115000>;
5316					hysteresis = <5000>;
5317					type = "passive";
5318				};
5319			};
5320		};
5321
5322		modem1-thermal {
5323			polling-delay-passive = <0>;
5324			polling-delay = <0>;
5325			thermal-sensors = <&tsens1 11>;
5326
5327			trips {
5328				thermal-engine-config {
5329					temperature = <125000>;
5330					hysteresis = <1000>;
5331					type = "passive";
5332				};
5333
5334				mdmss1_config0: mdmss1-config0 {
5335					temperature = <102000>;
5336					hysteresis = <3000>;
5337					type = "passive";
5338				};
5339
5340				mdmss1_config1: mdmss1-config1 {
5341					temperature = <105000>;
5342					hysteresis = <3000>;
5343					type = "passive";
5344				};
5345
5346				reset-mon-cfg {
5347					temperature = <115000>;
5348					hysteresis = <5000>;
5349					type = "passive";
5350				};
5351			};
5352		};
5353
5354		modem2-thermal {
5355			polling-delay-passive = <0>;
5356			polling-delay = <0>;
5357			thermal-sensors = <&tsens1 12>;
5358
5359			trips {
5360				thermal-engine-config {
5361					temperature = <125000>;
5362					hysteresis = <1000>;
5363					type = "passive";
5364				};
5365
5366				mdmss2_config0: mdmss2-config0 {
5367					temperature = <102000>;
5368					hysteresis = <3000>;
5369					type = "passive";
5370				};
5371
5372				mdmss2_config1: mdmss2-config1 {
5373					temperature = <105000>;
5374					hysteresis = <3000>;
5375					type = "passive";
5376				};
5377
5378				reset-mon-cfg {
5379					temperature = <115000>;
5380					hysteresis = <5000>;
5381					type = "passive";
5382				};
5383			};
5384		};
5385
5386		modem3-thermal {
5387			polling-delay-passive = <0>;
5388			polling-delay = <0>;
5389			thermal-sensors = <&tsens1 13>;
5390
5391			trips {
5392				thermal-engine-config {
5393					temperature = <125000>;
5394					hysteresis = <1000>;
5395					type = "passive";
5396				};
5397
5398				mdmss3_config0: mdmss3-config0 {
5399					temperature = <102000>;
5400					hysteresis = <3000>;
5401					type = "passive";
5402				};
5403
5404				mdmss3_config1: mdmss3-config1 {
5405					temperature = <105000>;
5406					hysteresis = <3000>;
5407					type = "passive";
5408				};
5409
5410				reset-mon-cfg {
5411					temperature = <115000>;
5412					hysteresis = <5000>;
5413					type = "passive";
5414				};
5415			};
5416		};
5417
5418		camera0-thermal {
5419			polling-delay-passive = <0>;
5420			polling-delay = <0>;
5421			thermal-sensors = <&tsens1 14>;
5422
5423			trips {
5424				thermal-engine-config {
5425					temperature = <125000>;
5426					hysteresis = <1000>;
5427					type = "passive";
5428				};
5429
5430				reset-mon-cfg {
5431					temperature = <115000>;
5432					hysteresis = <5000>;
5433					type = "passive";
5434				};
5435			};
5436		};
5437
5438		camera1-thermal {
5439			polling-delay-passive = <0>;
5440			polling-delay = <0>;
5441			thermal-sensors = <&tsens1 15>;
5442
5443			trips {
5444				thermal-engine-config {
5445					temperature = <125000>;
5446					hysteresis = <1000>;
5447					type = "passive";
5448				};
5449
5450				reset-mon-cfg {
5451					temperature = <115000>;
5452					hysteresis = <5000>;
5453					type = "passive";
5454				};
5455			};
5456		};
5457	};
5458
5459	timer {
5460		compatible = "arm,armv8-timer";
5461		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5462			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5463			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5464			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5465		clock-frequency = <19200000>;
5466	};
5467};
5468