1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/interconnect/qcom,sm8450.h> 16#include <dt-bindings/soc/qcom,gpr.h> 17#include <dt-bindings/soc/qcom,rpmh-rsc.h> 18#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 19#include <dt-bindings/thermal/thermal.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 chosen { }; 28 29 clocks { 30 xo_board: xo-board { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <76800000>; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <32000>; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 CPU0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo780"; 50 reg = <0x0 0x0>; 51 enable-method = "psci"; 52 next-level-cache = <&L2_0>; 53 power-domains = <&CPU_PD0>; 54 power-domain-names = "psci"; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 #cooling-cells = <2>; 57 clocks = <&cpufreq_hw 0>; 58 L2_0: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 next-level-cache = <&L3_0>; 62 L3_0: l3-cache { 63 compatible = "cache"; 64 cache-level = <3>; 65 }; 66 }; 67 }; 68 69 CPU1: cpu@100 { 70 device_type = "cpu"; 71 compatible = "qcom,kryo780"; 72 reg = <0x0 0x100>; 73 enable-method = "psci"; 74 next-level-cache = <&L2_100>; 75 power-domains = <&CPU_PD1>; 76 power-domain-names = "psci"; 77 qcom,freq-domain = <&cpufreq_hw 0>; 78 #cooling-cells = <2>; 79 clocks = <&cpufreq_hw 0>; 80 L2_100: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 next-level-cache = <&L3_0>; 84 }; 85 }; 86 87 CPU2: cpu@200 { 88 device_type = "cpu"; 89 compatible = "qcom,kryo780"; 90 reg = <0x0 0x200>; 91 enable-method = "psci"; 92 next-level-cache = <&L2_200>; 93 power-domains = <&CPU_PD2>; 94 power-domain-names = "psci"; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 #cooling-cells = <2>; 97 clocks = <&cpufreq_hw 0>; 98 L2_200: l2-cache { 99 compatible = "cache"; 100 cache-level = <2>; 101 next-level-cache = <&L3_0>; 102 }; 103 }; 104 105 CPU3: cpu@300 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo780"; 108 reg = <0x0 0x300>; 109 enable-method = "psci"; 110 next-level-cache = <&L2_300>; 111 power-domains = <&CPU_PD3>; 112 power-domain-names = "psci"; 113 qcom,freq-domain = <&cpufreq_hw 0>; 114 #cooling-cells = <2>; 115 clocks = <&cpufreq_hw 0>; 116 L2_300: l2-cache { 117 compatible = "cache"; 118 cache-level = <2>; 119 next-level-cache = <&L3_0>; 120 }; 121 }; 122 123 CPU4: cpu@400 { 124 device_type = "cpu"; 125 compatible = "qcom,kryo780"; 126 reg = <0x0 0x400>; 127 enable-method = "psci"; 128 next-level-cache = <&L2_400>; 129 power-domains = <&CPU_PD4>; 130 power-domain-names = "psci"; 131 qcom,freq-domain = <&cpufreq_hw 1>; 132 #cooling-cells = <2>; 133 clocks = <&cpufreq_hw 1>; 134 L2_400: l2-cache { 135 compatible = "cache"; 136 cache-level = <2>; 137 next-level-cache = <&L3_0>; 138 }; 139 }; 140 141 CPU5: cpu@500 { 142 device_type = "cpu"; 143 compatible = "qcom,kryo780"; 144 reg = <0x0 0x500>; 145 enable-method = "psci"; 146 next-level-cache = <&L2_500>; 147 power-domains = <&CPU_PD5>; 148 power-domain-names = "psci"; 149 qcom,freq-domain = <&cpufreq_hw 1>; 150 #cooling-cells = <2>; 151 clocks = <&cpufreq_hw 1>; 152 L2_500: l2-cache { 153 compatible = "cache"; 154 cache-level = <2>; 155 next-level-cache = <&L3_0>; 156 }; 157 158 }; 159 160 CPU6: cpu@600 { 161 device_type = "cpu"; 162 compatible = "qcom,kryo780"; 163 reg = <0x0 0x600>; 164 enable-method = "psci"; 165 next-level-cache = <&L2_600>; 166 power-domains = <&CPU_PD6>; 167 power-domain-names = "psci"; 168 qcom,freq-domain = <&cpufreq_hw 1>; 169 #cooling-cells = <2>; 170 clocks = <&cpufreq_hw 1>; 171 L2_600: l2-cache { 172 compatible = "cache"; 173 cache-level = <2>; 174 next-level-cache = <&L3_0>; 175 }; 176 }; 177 178 CPU7: cpu@700 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo780"; 181 reg = <0x0 0x700>; 182 enable-method = "psci"; 183 next-level-cache = <&L2_700>; 184 power-domains = <&CPU_PD7>; 185 power-domain-names = "psci"; 186 qcom,freq-domain = <&cpufreq_hw 2>; 187 #cooling-cells = <2>; 188 clocks = <&cpufreq_hw 2>; 189 L2_700: l2-cache { 190 compatible = "cache"; 191 cache-level = <2>; 192 next-level-cache = <&L3_0>; 193 }; 194 }; 195 196 cpu-map { 197 cluster0 { 198 core0 { 199 cpu = <&CPU0>; 200 }; 201 202 core1 { 203 cpu = <&CPU1>; 204 }; 205 206 core2 { 207 cpu = <&CPU2>; 208 }; 209 210 core3 { 211 cpu = <&CPU3>; 212 }; 213 214 core4 { 215 cpu = <&CPU4>; 216 }; 217 218 core5 { 219 cpu = <&CPU5>; 220 }; 221 222 core6 { 223 cpu = <&CPU6>; 224 }; 225 226 core7 { 227 cpu = <&CPU7>; 228 }; 229 }; 230 }; 231 232 idle-states { 233 entry-method = "psci"; 234 235 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 236 compatible = "arm,idle-state"; 237 idle-state-name = "silver-rail-power-collapse"; 238 arm,psci-suspend-param = <0x40000004>; 239 entry-latency-us = <800>; 240 exit-latency-us = <750>; 241 min-residency-us = <4090>; 242 local-timer-stop; 243 }; 244 245 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 246 compatible = "arm,idle-state"; 247 idle-state-name = "gold-rail-power-collapse"; 248 arm,psci-suspend-param = <0x40000004>; 249 entry-latency-us = <600>; 250 exit-latency-us = <1550>; 251 min-residency-us = <4791>; 252 local-timer-stop; 253 }; 254 }; 255 256 domain-idle-states { 257 CLUSTER_SLEEP_0: cluster-sleep-0 { 258 compatible = "domain-idle-state"; 259 idle-state-name = "cluster-l3-off"; 260 arm,psci-suspend-param = <0x41000044>; 261 entry-latency-us = <1050>; 262 exit-latency-us = <2500>; 263 min-residency-us = <5309>; 264 local-timer-stop; 265 }; 266 267 CLUSTER_SLEEP_1: cluster-sleep-1 { 268 compatible = "domain-idle-state"; 269 idle-state-name = "cluster-power-collapse"; 270 arm,psci-suspend-param = <0x4100c344>; 271 entry-latency-us = <2700>; 272 exit-latency-us = <3500>; 273 min-residency-us = <13959>; 274 local-timer-stop; 275 }; 276 }; 277 }; 278 279 firmware { 280 scm: scm { 281 compatible = "qcom,scm-sm8450", "qcom,scm"; 282 qcom,dload-mode = <&tcsr 0x13000>; 283 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 284 #reset-cells = <1>; 285 }; 286 }; 287 288 clk_virt: interconnect-0 { 289 compatible = "qcom,sm8450-clk-virt"; 290 #interconnect-cells = <2>; 291 qcom,bcm-voters = <&apps_bcm_voter>; 292 }; 293 294 mc_virt: interconnect-1 { 295 compatible = "qcom,sm8450-mc-virt"; 296 #interconnect-cells = <2>; 297 qcom,bcm-voters = <&apps_bcm_voter>; 298 }; 299 300 memory@a0000000 { 301 device_type = "memory"; 302 /* We expect the bootloader to fill in the size */ 303 reg = <0x0 0xa0000000 0x0 0x0>; 304 }; 305 306 pmu { 307 compatible = "arm,armv8-pmuv3"; 308 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 309 }; 310 311 psci { 312 compatible = "arm,psci-1.0"; 313 method = "smc"; 314 315 CPU_PD0: power-domain-cpu0 { 316 #power-domain-cells = <0>; 317 power-domains = <&CLUSTER_PD>; 318 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 319 }; 320 321 CPU_PD1: power-domain-cpu1 { 322 #power-domain-cells = <0>; 323 power-domains = <&CLUSTER_PD>; 324 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 325 }; 326 327 CPU_PD2: power-domain-cpu2 { 328 #power-domain-cells = <0>; 329 power-domains = <&CLUSTER_PD>; 330 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 331 }; 332 333 CPU_PD3: power-domain-cpu3 { 334 #power-domain-cells = <0>; 335 power-domains = <&CLUSTER_PD>; 336 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 337 }; 338 339 CPU_PD4: power-domain-cpu4 { 340 #power-domain-cells = <0>; 341 power-domains = <&CLUSTER_PD>; 342 domain-idle-states = <&BIG_CPU_SLEEP_0>; 343 }; 344 345 CPU_PD5: power-domain-cpu5 { 346 #power-domain-cells = <0>; 347 power-domains = <&CLUSTER_PD>; 348 domain-idle-states = <&BIG_CPU_SLEEP_0>; 349 }; 350 351 CPU_PD6: power-domain-cpu6 { 352 #power-domain-cells = <0>; 353 power-domains = <&CLUSTER_PD>; 354 domain-idle-states = <&BIG_CPU_SLEEP_0>; 355 }; 356 357 CPU_PD7: power-domain-cpu7 { 358 #power-domain-cells = <0>; 359 power-domains = <&CLUSTER_PD>; 360 domain-idle-states = <&BIG_CPU_SLEEP_0>; 361 }; 362 363 CLUSTER_PD: power-domain-cpu-cluster0 { 364 #power-domain-cells = <0>; 365 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 366 }; 367 }; 368 369 qup_opp_table_100mhz: opp-table-qup { 370 compatible = "operating-points-v2"; 371 372 opp-50000000 { 373 opp-hz = /bits/ 64 <50000000>; 374 required-opps = <&rpmhpd_opp_min_svs>; 375 }; 376 377 opp-75000000 { 378 opp-hz = /bits/ 64 <75000000>; 379 required-opps = <&rpmhpd_opp_low_svs>; 380 }; 381 382 opp-100000000 { 383 opp-hz = /bits/ 64 <100000000>; 384 required-opps = <&rpmhpd_opp_svs>; 385 }; 386 }; 387 388 reserved_memory: reserved-memory { 389 #address-cells = <2>; 390 #size-cells = <2>; 391 ranges; 392 393 hyp_mem: memory@80000000 { 394 reg = <0x0 0x80000000 0x0 0x600000>; 395 no-map; 396 }; 397 398 xbl_dt_log_mem: memory@80600000 { 399 reg = <0x0 0x80600000 0x0 0x40000>; 400 no-map; 401 }; 402 403 xbl_ramdump_mem: memory@80640000 { 404 reg = <0x0 0x80640000 0x0 0x180000>; 405 no-map; 406 }; 407 408 xbl_sc_mem: memory@807c0000 { 409 reg = <0x0 0x807c0000 0x0 0x40000>; 410 no-map; 411 }; 412 413 aop_image_mem: memory@80800000 { 414 reg = <0x0 0x80800000 0x0 0x60000>; 415 no-map; 416 }; 417 418 aop_cmd_db_mem: memory@80860000 { 419 compatible = "qcom,cmd-db"; 420 reg = <0x0 0x80860000 0x0 0x20000>; 421 no-map; 422 }; 423 424 aop_config_mem: memory@80880000 { 425 reg = <0x0 0x80880000 0x0 0x20000>; 426 no-map; 427 }; 428 429 tme_crash_dump_mem: memory@808a0000 { 430 reg = <0x0 0x808a0000 0x0 0x40000>; 431 no-map; 432 }; 433 434 tme_log_mem: memory@808e0000 { 435 reg = <0x0 0x808e0000 0x0 0x4000>; 436 no-map; 437 }; 438 439 uefi_log_mem: memory@808e4000 { 440 reg = <0x0 0x808e4000 0x0 0x10000>; 441 no-map; 442 }; 443 444 /* secdata region can be reused by apps */ 445 smem: memory@80900000 { 446 compatible = "qcom,smem"; 447 reg = <0x0 0x80900000 0x0 0x200000>; 448 hwlocks = <&tcsr_mutex 3>; 449 no-map; 450 }; 451 452 cpucp_fw_mem: memory@80b00000 { 453 reg = <0x0 0x80b00000 0x0 0x100000>; 454 no-map; 455 }; 456 457 cdsp_secure_heap: memory@80c00000 { 458 reg = <0x0 0x80c00000 0x0 0x4600000>; 459 no-map; 460 }; 461 462 video_mem: memory@85700000 { 463 reg = <0x0 0x85700000 0x0 0x700000>; 464 no-map; 465 }; 466 467 adsp_mem: memory@85e00000 { 468 reg = <0x0 0x85e00000 0x0 0x2100000>; 469 no-map; 470 }; 471 472 slpi_mem: memory@88000000 { 473 reg = <0x0 0x88000000 0x0 0x1900000>; 474 no-map; 475 }; 476 477 cdsp_mem: memory@89900000 { 478 reg = <0x0 0x89900000 0x0 0x2000000>; 479 no-map; 480 }; 481 482 ipa_fw_mem: memory@8b900000 { 483 reg = <0x0 0x8b900000 0x0 0x10000>; 484 no-map; 485 }; 486 487 ipa_gsi_mem: memory@8b910000 { 488 reg = <0x0 0x8b910000 0x0 0xa000>; 489 no-map; 490 }; 491 492 gpu_micro_code_mem: memory@8b91a000 { 493 reg = <0x0 0x8b91a000 0x0 0x2000>; 494 no-map; 495 }; 496 497 spss_region_mem: memory@8ba00000 { 498 reg = <0x0 0x8ba00000 0x0 0x180000>; 499 no-map; 500 }; 501 502 /* First part of the "SPU secure shared memory" region */ 503 spu_tz_shared_mem: memory@8bb80000 { 504 reg = <0x0 0x8bb80000 0x0 0x60000>; 505 no-map; 506 }; 507 508 /* Second part of the "SPU secure shared memory" region */ 509 spu_modem_shared_mem: memory@8bbe0000 { 510 reg = <0x0 0x8bbe0000 0x0 0x20000>; 511 no-map; 512 }; 513 514 mpss_mem: memory@8bc00000 { 515 reg = <0x0 0x8bc00000 0x0 0x13200000>; 516 no-map; 517 }; 518 519 cvp_mem: memory@9ee00000 { 520 reg = <0x0 0x9ee00000 0x0 0x700000>; 521 no-map; 522 }; 523 524 camera_mem: memory@9f500000 { 525 reg = <0x0 0x9f500000 0x0 0x800000>; 526 no-map; 527 }; 528 529 rmtfs_mem: memory@9fd00000 { 530 compatible = "qcom,rmtfs-mem"; 531 reg = <0x0 0x9fd00000 0x0 0x280000>; 532 no-map; 533 534 qcom,client-id = <1>; 535 qcom,vmid = <15>; 536 }; 537 538 xbl_sc_mem2: memory@a6e00000 { 539 reg = <0x0 0xa6e00000 0x0 0x40000>; 540 no-map; 541 }; 542 543 global_sync_mem: memory@a6f00000 { 544 reg = <0x0 0xa6f00000 0x0 0x100000>; 545 no-map; 546 }; 547 548 /* uefi region can be reused by APPS */ 549 550 /* Linux kernel image is loaded at 0xa0000000 */ 551 552 oem_vm_mem: memory@bb000000 { 553 reg = <0x0 0xbb000000 0x0 0x5000000>; 554 no-map; 555 }; 556 557 mte_mem: memory@c0000000 { 558 reg = <0x0 0xc0000000 0x0 0x20000000>; 559 no-map; 560 }; 561 562 qheebsp_reserved_mem: memory@e0000000 { 563 reg = <0x0 0xe0000000 0x0 0x600000>; 564 no-map; 565 }; 566 567 cpusys_vm_mem: memory@e0600000 { 568 reg = <0x0 0xe0600000 0x0 0x400000>; 569 no-map; 570 }; 571 572 hyp_reserved_mem: memory@e0a00000 { 573 reg = <0x0 0xe0a00000 0x0 0x100000>; 574 no-map; 575 }; 576 577 trust_ui_vm_mem: memory@e0b00000 { 578 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 579 no-map; 580 }; 581 582 trust_ui_vm_qrtr: memory@e55f3000 { 583 reg = <0x0 0xe55f3000 0x0 0x9000>; 584 no-map; 585 }; 586 587 trust_ui_vm_vblk0_ring: memory@e55fc000 { 588 reg = <0x0 0xe55fc000 0x0 0x4000>; 589 no-map; 590 }; 591 592 trust_ui_vm_swiotlb: memory@e5600000 { 593 reg = <0x0 0xe5600000 0x0 0x100000>; 594 no-map; 595 }; 596 597 tz_stat_mem: memory@e8800000 { 598 reg = <0x0 0xe8800000 0x0 0x100000>; 599 no-map; 600 }; 601 602 tags_mem: memory@e8900000 { 603 reg = <0x0 0xe8900000 0x0 0x1200000>; 604 no-map; 605 }; 606 607 qtee_mem: memory@e9b00000 { 608 reg = <0x0 0xe9b00000 0x0 0x500000>; 609 no-map; 610 }; 611 612 trusted_apps_mem: memory@ea000000 { 613 reg = <0x0 0xea000000 0x0 0x3900000>; 614 no-map; 615 }; 616 617 trusted_apps_ext_mem: memory@ed900000 { 618 reg = <0x0 0xed900000 0x0 0x3b00000>; 619 no-map; 620 }; 621 }; 622 623 smp2p-adsp { 624 compatible = "qcom,smp2p"; 625 qcom,smem = <443>, <429>; 626 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 627 IPCC_MPROC_SIGNAL_SMP2P 628 IRQ_TYPE_EDGE_RISING>; 629 mboxes = <&ipcc IPCC_CLIENT_LPASS 630 IPCC_MPROC_SIGNAL_SMP2P>; 631 632 qcom,local-pid = <0>; 633 qcom,remote-pid = <2>; 634 635 smp2p_adsp_out: master-kernel { 636 qcom,entry-name = "master-kernel"; 637 #qcom,smem-state-cells = <1>; 638 }; 639 640 smp2p_adsp_in: slave-kernel { 641 qcom,entry-name = "slave-kernel"; 642 interrupt-controller; 643 #interrupt-cells = <2>; 644 }; 645 }; 646 647 smp2p-cdsp { 648 compatible = "qcom,smp2p"; 649 qcom,smem = <94>, <432>; 650 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 651 IPCC_MPROC_SIGNAL_SMP2P 652 IRQ_TYPE_EDGE_RISING>; 653 mboxes = <&ipcc IPCC_CLIENT_CDSP 654 IPCC_MPROC_SIGNAL_SMP2P>; 655 656 qcom,local-pid = <0>; 657 qcom,remote-pid = <5>; 658 659 smp2p_cdsp_out: master-kernel { 660 qcom,entry-name = "master-kernel"; 661 #qcom,smem-state-cells = <1>; 662 }; 663 664 smp2p_cdsp_in: slave-kernel { 665 qcom,entry-name = "slave-kernel"; 666 interrupt-controller; 667 #interrupt-cells = <2>; 668 }; 669 }; 670 671 smp2p-modem { 672 compatible = "qcom,smp2p"; 673 qcom,smem = <435>, <428>; 674 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 675 IPCC_MPROC_SIGNAL_SMP2P 676 IRQ_TYPE_EDGE_RISING>; 677 mboxes = <&ipcc IPCC_CLIENT_MPSS 678 IPCC_MPROC_SIGNAL_SMP2P>; 679 680 qcom,local-pid = <0>; 681 qcom,remote-pid = <1>; 682 683 smp2p_modem_out: master-kernel { 684 qcom,entry-name = "master-kernel"; 685 #qcom,smem-state-cells = <1>; 686 }; 687 688 smp2p_modem_in: slave-kernel { 689 qcom,entry-name = "slave-kernel"; 690 interrupt-controller; 691 #interrupt-cells = <2>; 692 }; 693 694 ipa_smp2p_out: ipa-ap-to-modem { 695 qcom,entry-name = "ipa"; 696 #qcom,smem-state-cells = <1>; 697 }; 698 699 ipa_smp2p_in: ipa-modem-to-ap { 700 qcom,entry-name = "ipa"; 701 interrupt-controller; 702 #interrupt-cells = <2>; 703 }; 704 }; 705 706 smp2p-slpi { 707 compatible = "qcom,smp2p"; 708 qcom,smem = <481>, <430>; 709 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 710 IPCC_MPROC_SIGNAL_SMP2P 711 IRQ_TYPE_EDGE_RISING>; 712 mboxes = <&ipcc IPCC_CLIENT_SLPI 713 IPCC_MPROC_SIGNAL_SMP2P>; 714 715 qcom,local-pid = <0>; 716 qcom,remote-pid = <3>; 717 718 smp2p_slpi_out: master-kernel { 719 qcom,entry-name = "master-kernel"; 720 #qcom,smem-state-cells = <1>; 721 }; 722 723 smp2p_slpi_in: slave-kernel { 724 qcom,entry-name = "slave-kernel"; 725 interrupt-controller; 726 #interrupt-cells = <2>; 727 }; 728 }; 729 730 soc: soc@0 { 731 #address-cells = <2>; 732 #size-cells = <2>; 733 ranges = <0 0 0 0 0x10 0>; 734 dma-ranges = <0 0 0 0 0x10 0>; 735 compatible = "simple-bus"; 736 737 gcc: clock-controller@100000 { 738 compatible = "qcom,gcc-sm8450"; 739 reg = <0x0 0x00100000 0x0 0x1f4200>; 740 #clock-cells = <1>; 741 #reset-cells = <1>; 742 #power-domain-cells = <1>; 743 clocks = <&rpmhcc RPMH_CXO_CLK>, 744 <&sleep_clk>, 745 <&pcie0_lane>, 746 <&pcie1_lane>, 747 <0>, 748 <&ufs_mem_phy_lanes 0>, 749 <&ufs_mem_phy_lanes 1>, 750 <&ufs_mem_phy_lanes 2>, 751 <0>; 752 clock-names = "bi_tcxo", 753 "sleep_clk", 754 "pcie_0_pipe_clk", 755 "pcie_1_pipe_clk", 756 "pcie_1_phy_aux_clk", 757 "ufs_phy_rx_symbol_0_clk", 758 "ufs_phy_rx_symbol_1_clk", 759 "ufs_phy_tx_symbol_0_clk", 760 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 761 }; 762 763 gpi_dma2: dma-controller@800000 { 764 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 765 #dma-cells = <3>; 766 reg = <0 0x00800000 0 0x60000>; 767 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 779 dma-channels = <12>; 780 dma-channel-mask = <0x7e>; 781 iommus = <&apps_smmu 0x496 0x0>; 782 status = "disabled"; 783 }; 784 785 qupv3_id_2: geniqup@8c0000 { 786 compatible = "qcom,geni-se-qup"; 787 reg = <0x0 0x008c0000 0x0 0x2000>; 788 clock-names = "m-ahb", "s-ahb"; 789 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 790 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 791 iommus = <&apps_smmu 0x483 0x0>; 792 #address-cells = <2>; 793 #size-cells = <2>; 794 ranges; 795 status = "disabled"; 796 797 i2c15: i2c@880000 { 798 compatible = "qcom,geni-i2c"; 799 reg = <0x0 0x00880000 0x0 0x4000>; 800 clock-names = "se"; 801 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 802 pinctrl-names = "default"; 803 pinctrl-0 = <&qup_i2c15_data_clk>; 804 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 808 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 809 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 810 interconnect-names = "qup-core", "qup-config", "qup-memory"; 811 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 812 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 813 dma-names = "tx", "rx"; 814 status = "disabled"; 815 }; 816 817 spi15: spi@880000 { 818 compatible = "qcom,geni-spi"; 819 reg = <0x0 0x00880000 0x0 0x4000>; 820 clock-names = "se"; 821 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 822 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 823 pinctrl-names = "default"; 824 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 825 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 826 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 827 interconnect-names = "qup-core", "qup-config"; 828 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 829 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 830 dma-names = "tx", "rx"; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 status = "disabled"; 834 }; 835 836 i2c16: i2c@884000 { 837 compatible = "qcom,geni-i2c"; 838 reg = <0x0 0x00884000 0x0 0x4000>; 839 clock-names = "se"; 840 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 841 pinctrl-names = "default"; 842 pinctrl-0 = <&qup_i2c16_data_clk>; 843 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 847 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 848 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 849 interconnect-names = "qup-core", "qup-config", "qup-memory"; 850 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 851 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 852 dma-names = "tx", "rx"; 853 status = "disabled"; 854 }; 855 856 spi16: spi@884000 { 857 compatible = "qcom,geni-spi"; 858 reg = <0x0 0x00884000 0x0 0x4000>; 859 clock-names = "se"; 860 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 861 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 862 pinctrl-names = "default"; 863 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 864 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 865 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 866 interconnect-names = "qup-core", "qup-config"; 867 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 868 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 869 dma-names = "tx", "rx"; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 status = "disabled"; 873 }; 874 875 i2c17: i2c@888000 { 876 compatible = "qcom,geni-i2c"; 877 reg = <0x0 0x00888000 0x0 0x4000>; 878 clock-names = "se"; 879 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 880 pinctrl-names = "default"; 881 pinctrl-0 = <&qup_i2c17_data_clk>; 882 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 886 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 887 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 888 interconnect-names = "qup-core", "qup-config", "qup-memory"; 889 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 890 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 891 dma-names = "tx", "rx"; 892 status = "disabled"; 893 }; 894 895 spi17: spi@888000 { 896 compatible = "qcom,geni-spi"; 897 reg = <0x0 0x00888000 0x0 0x4000>; 898 clock-names = "se"; 899 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 900 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 901 pinctrl-names = "default"; 902 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 903 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 904 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 905 interconnect-names = "qup-core", "qup-config"; 906 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 907 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 908 dma-names = "tx", "rx"; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 status = "disabled"; 912 }; 913 914 i2c18: i2c@88c000 { 915 compatible = "qcom,geni-i2c"; 916 reg = <0x0 0x0088c000 0x0 0x4000>; 917 clock-names = "se"; 918 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 919 pinctrl-names = "default"; 920 pinctrl-0 = <&qup_i2c18_data_clk>; 921 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 925 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 926 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 927 interconnect-names = "qup-core", "qup-config", "qup-memory"; 928 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 929 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 930 dma-names = "tx", "rx"; 931 status = "disabled"; 932 }; 933 934 spi18: spi@88c000 { 935 compatible = "qcom,geni-spi"; 936 reg = <0 0x0088c000 0 0x4000>; 937 clock-names = "se"; 938 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 939 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 940 pinctrl-names = "default"; 941 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 942 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 943 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 944 interconnect-names = "qup-core", "qup-config"; 945 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 946 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 947 dma-names = "tx", "rx"; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 status = "disabled"; 951 }; 952 953 i2c19: i2c@890000 { 954 compatible = "qcom,geni-i2c"; 955 reg = <0x0 0x00890000 0x0 0x4000>; 956 clock-names = "se"; 957 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 958 pinctrl-names = "default"; 959 pinctrl-0 = <&qup_i2c19_data_clk>; 960 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 964 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 965 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 966 interconnect-names = "qup-core", "qup-config", "qup-memory"; 967 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 968 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 969 dma-names = "tx", "rx"; 970 status = "disabled"; 971 }; 972 973 spi19: spi@890000 { 974 compatible = "qcom,geni-spi"; 975 reg = <0 0x00890000 0 0x4000>; 976 clock-names = "se"; 977 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 978 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 979 pinctrl-names = "default"; 980 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 981 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 982 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 983 interconnect-names = "qup-core", "qup-config"; 984 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 985 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 986 dma-names = "tx", "rx"; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 status = "disabled"; 990 }; 991 992 i2c20: i2c@894000 { 993 compatible = "qcom,geni-i2c"; 994 reg = <0x0 0x00894000 0x0 0x4000>; 995 clock-names = "se"; 996 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&qup_i2c20_data_clk>; 999 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1003 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1004 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1005 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1006 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1007 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1008 dma-names = "tx", "rx"; 1009 status = "disabled"; 1010 }; 1011 1012 uart20: serial@894000 { 1013 compatible = "qcom,geni-uart"; 1014 reg = <0 0x00894000 0 0x4000>; 1015 clock-names = "se"; 1016 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1017 pinctrl-names = "default"; 1018 pinctrl-0 = <&qup_uart20_default>; 1019 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1020 status = "disabled"; 1021 }; 1022 1023 spi20: spi@894000 { 1024 compatible = "qcom,geni-spi"; 1025 reg = <0 0x00894000 0 0x4000>; 1026 clock-names = "se"; 1027 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1028 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1029 pinctrl-names = "default"; 1030 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1031 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1032 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1033 interconnect-names = "qup-core", "qup-config"; 1034 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1035 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1036 dma-names = "tx", "rx"; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 status = "disabled"; 1040 }; 1041 1042 i2c21: i2c@898000 { 1043 compatible = "qcom,geni-i2c"; 1044 reg = <0x0 0x00898000 0x0 0x4000>; 1045 clock-names = "se"; 1046 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&qup_i2c21_data_clk>; 1049 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1053 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1054 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1055 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1056 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1057 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1058 dma-names = "tx", "rx"; 1059 status = "disabled"; 1060 }; 1061 1062 spi21: spi@898000 { 1063 compatible = "qcom,geni-spi"; 1064 reg = <0 0x00898000 0 0x4000>; 1065 clock-names = "se"; 1066 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1067 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1070 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1071 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1072 interconnect-names = "qup-core", "qup-config"; 1073 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1074 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1075 dma-names = "tx", "rx"; 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 status = "disabled"; 1079 }; 1080 }; 1081 1082 gpi_dma0: dma-controller@900000 { 1083 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1084 #dma-cells = <3>; 1085 reg = <0 0x00900000 0 0x60000>; 1086 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1098 dma-channels = <12>; 1099 dma-channel-mask = <0x7e>; 1100 iommus = <&apps_smmu 0x5b6 0x0>; 1101 status = "disabled"; 1102 }; 1103 1104 qupv3_id_0: geniqup@9c0000 { 1105 compatible = "qcom,geni-se-qup"; 1106 reg = <0x0 0x009c0000 0x0 0x2000>; 1107 clock-names = "m-ahb", "s-ahb"; 1108 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1109 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1110 iommus = <&apps_smmu 0x5a3 0x0>; 1111 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1112 interconnect-names = "qup-core"; 1113 #address-cells = <2>; 1114 #size-cells = <2>; 1115 ranges; 1116 status = "disabled"; 1117 1118 i2c0: i2c@980000 { 1119 compatible = "qcom,geni-i2c"; 1120 reg = <0x0 0x00980000 0x0 0x4000>; 1121 clock-names = "se"; 1122 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1123 pinctrl-names = "default"; 1124 pinctrl-0 = <&qup_i2c0_data_clk>; 1125 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1129 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1130 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1131 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1132 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1133 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1134 dma-names = "tx", "rx"; 1135 status = "disabled"; 1136 }; 1137 1138 spi0: spi@980000 { 1139 compatible = "qcom,geni-spi"; 1140 reg = <0x0 0x00980000 0x0 0x4000>; 1141 clock-names = "se"; 1142 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1143 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1144 pinctrl-names = "default"; 1145 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1146 power-domains = <&rpmhpd SM8450_CX>; 1147 operating-points-v2 = <&qup_opp_table_100mhz>; 1148 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1149 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1150 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1151 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1152 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1153 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1154 dma-names = "tx", "rx"; 1155 #address-cells = <1>; 1156 #size-cells = <0>; 1157 status = "disabled"; 1158 }; 1159 1160 i2c1: i2c@984000 { 1161 compatible = "qcom,geni-i2c"; 1162 reg = <0x0 0x00984000 0x0 0x4000>; 1163 clock-names = "se"; 1164 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1165 pinctrl-names = "default"; 1166 pinctrl-0 = <&qup_i2c1_data_clk>; 1167 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1171 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1172 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1173 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1174 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1175 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1176 dma-names = "tx", "rx"; 1177 status = "disabled"; 1178 }; 1179 1180 spi1: spi@984000 { 1181 compatible = "qcom,geni-spi"; 1182 reg = <0x0 0x00984000 0x0 0x4000>; 1183 clock-names = "se"; 1184 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1185 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1186 pinctrl-names = "default"; 1187 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1188 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1189 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1190 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1191 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1192 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1193 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1194 dma-names = "tx", "rx"; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 status = "disabled"; 1198 }; 1199 1200 i2c2: i2c@988000 { 1201 compatible = "qcom,geni-i2c"; 1202 reg = <0x0 0x00988000 0x0 0x4000>; 1203 clock-names = "se"; 1204 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&qup_i2c2_data_clk>; 1207 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1211 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1212 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1213 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1214 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1215 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1216 dma-names = "tx", "rx"; 1217 status = "disabled"; 1218 }; 1219 1220 spi2: spi@988000 { 1221 compatible = "qcom,geni-spi"; 1222 reg = <0x0 0x00988000 0x0 0x4000>; 1223 clock-names = "se"; 1224 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1225 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1226 pinctrl-names = "default"; 1227 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1228 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1229 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1230 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1231 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1232 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1233 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1234 dma-names = "tx", "rx"; 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 status = "disabled"; 1238 }; 1239 1240 1241 i2c3: i2c@98c000 { 1242 compatible = "qcom,geni-i2c"; 1243 reg = <0x0 0x0098c000 0x0 0x4000>; 1244 clock-names = "se"; 1245 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1246 pinctrl-names = "default"; 1247 pinctrl-0 = <&qup_i2c3_data_clk>; 1248 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1252 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1253 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1254 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1255 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1256 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1257 dma-names = "tx", "rx"; 1258 status = "disabled"; 1259 }; 1260 1261 spi3: spi@98c000 { 1262 compatible = "qcom,geni-spi"; 1263 reg = <0x0 0x0098c000 0x0 0x4000>; 1264 clock-names = "se"; 1265 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1266 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1269 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1270 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1271 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1272 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1273 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1274 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1275 dma-names = "tx", "rx"; 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 status = "disabled"; 1279 }; 1280 1281 i2c4: i2c@990000 { 1282 compatible = "qcom,geni-i2c"; 1283 reg = <0x0 0x00990000 0x0 0x4000>; 1284 clock-names = "se"; 1285 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1286 pinctrl-names = "default"; 1287 pinctrl-0 = <&qup_i2c4_data_clk>; 1288 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1289 #address-cells = <1>; 1290 #size-cells = <0>; 1291 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1292 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1293 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1294 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1295 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1296 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1297 dma-names = "tx", "rx"; 1298 status = "disabled"; 1299 }; 1300 1301 spi4: spi@990000 { 1302 compatible = "qcom,geni-spi"; 1303 reg = <0x0 0x00990000 0x0 0x4000>; 1304 clock-names = "se"; 1305 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1306 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1309 power-domains = <&rpmhpd SM8450_CX>; 1310 operating-points-v2 = <&qup_opp_table_100mhz>; 1311 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1312 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1313 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1314 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1315 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1316 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1317 dma-names = "tx", "rx"; 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 status = "disabled"; 1321 }; 1322 1323 i2c5: i2c@994000 { 1324 compatible = "qcom,geni-i2c"; 1325 reg = <0x0 0x00994000 0x0 0x4000>; 1326 clock-names = "se"; 1327 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1328 pinctrl-names = "default"; 1329 pinctrl-0 = <&qup_i2c5_data_clk>; 1330 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1334 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1335 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1336 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1337 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1338 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1339 dma-names = "tx", "rx"; 1340 status = "disabled"; 1341 }; 1342 1343 spi5: spi@994000 { 1344 compatible = "qcom,geni-spi"; 1345 reg = <0x0 0x00994000 0x0 0x4000>; 1346 clock-names = "se"; 1347 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1348 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1349 pinctrl-names = "default"; 1350 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1351 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1352 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1353 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1354 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1355 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1356 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1357 dma-names = "tx", "rx"; 1358 #address-cells = <1>; 1359 #size-cells = <0>; 1360 status = "disabled"; 1361 }; 1362 1363 1364 i2c6: i2c@998000 { 1365 compatible = "qcom,geni-i2c"; 1366 reg = <0x0 0x00998000 0x0 0x4000>; 1367 clock-names = "se"; 1368 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1369 pinctrl-names = "default"; 1370 pinctrl-0 = <&qup_i2c6_data_clk>; 1371 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1375 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1376 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1377 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1378 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1379 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1380 dma-names = "tx", "rx"; 1381 status = "disabled"; 1382 }; 1383 1384 spi6: spi@998000 { 1385 compatible = "qcom,geni-spi"; 1386 reg = <0x0 0x00998000 0x0 0x4000>; 1387 clock-names = "se"; 1388 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1389 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1390 pinctrl-names = "default"; 1391 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1392 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1393 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1394 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1395 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1396 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1397 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1398 dma-names = "tx", "rx"; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 status = "disabled"; 1402 }; 1403 1404 uart7: serial@99c000 { 1405 compatible = "qcom,geni-debug-uart"; 1406 reg = <0 0x0099c000 0 0x4000>; 1407 clock-names = "se"; 1408 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1409 pinctrl-names = "default"; 1410 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1411 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1412 status = "disabled"; 1413 }; 1414 }; 1415 1416 gpi_dma1: dma-controller@a00000 { 1417 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1418 #dma-cells = <3>; 1419 reg = <0 0x00a00000 0 0x60000>; 1420 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1432 dma-channels = <12>; 1433 dma-channel-mask = <0x7e>; 1434 iommus = <&apps_smmu 0x56 0x0>; 1435 status = "disabled"; 1436 }; 1437 1438 qupv3_id_1: geniqup@ac0000 { 1439 compatible = "qcom,geni-se-qup"; 1440 reg = <0x0 0x00ac0000 0x0 0x6000>; 1441 clock-names = "m-ahb", "s-ahb"; 1442 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1443 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1444 iommus = <&apps_smmu 0x43 0x0>; 1445 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1446 interconnect-names = "qup-core"; 1447 #address-cells = <2>; 1448 #size-cells = <2>; 1449 ranges; 1450 status = "disabled"; 1451 1452 i2c8: i2c@a80000 { 1453 compatible = "qcom,geni-i2c"; 1454 reg = <0x0 0x00a80000 0x0 0x4000>; 1455 clock-names = "se"; 1456 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1457 pinctrl-names = "default"; 1458 pinctrl-0 = <&qup_i2c8_data_clk>; 1459 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1463 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1464 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1465 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1466 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1467 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1468 dma-names = "tx", "rx"; 1469 status = "disabled"; 1470 }; 1471 1472 spi8: spi@a80000 { 1473 compatible = "qcom,geni-spi"; 1474 reg = <0x0 0x00a80000 0x0 0x4000>; 1475 clock-names = "se"; 1476 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1477 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1478 pinctrl-names = "default"; 1479 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1480 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1481 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1482 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1483 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1484 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1485 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1486 dma-names = "tx", "rx"; 1487 #address-cells = <1>; 1488 #size-cells = <0>; 1489 status = "disabled"; 1490 }; 1491 1492 i2c9: i2c@a84000 { 1493 compatible = "qcom,geni-i2c"; 1494 reg = <0x0 0x00a84000 0x0 0x4000>; 1495 clock-names = "se"; 1496 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1497 pinctrl-names = "default"; 1498 pinctrl-0 = <&qup_i2c9_data_clk>; 1499 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1503 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1504 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1505 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1506 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1507 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1508 dma-names = "tx", "rx"; 1509 status = "disabled"; 1510 }; 1511 1512 spi9: spi@a84000 { 1513 compatible = "qcom,geni-spi"; 1514 reg = <0x0 0x00a84000 0x0 0x4000>; 1515 clock-names = "se"; 1516 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1517 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1518 pinctrl-names = "default"; 1519 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1520 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1521 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1522 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1523 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1524 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1525 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1526 dma-names = "tx", "rx"; 1527 #address-cells = <1>; 1528 #size-cells = <0>; 1529 status = "disabled"; 1530 }; 1531 1532 i2c10: i2c@a88000 { 1533 compatible = "qcom,geni-i2c"; 1534 reg = <0x0 0x00a88000 0x0 0x4000>; 1535 clock-names = "se"; 1536 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1537 pinctrl-names = "default"; 1538 pinctrl-0 = <&qup_i2c10_data_clk>; 1539 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1543 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1544 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1545 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1546 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1547 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1548 dma-names = "tx", "rx"; 1549 status = "disabled"; 1550 }; 1551 1552 spi10: spi@a88000 { 1553 compatible = "qcom,geni-spi"; 1554 reg = <0x0 0x00a88000 0x0 0x4000>; 1555 clock-names = "se"; 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1557 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1558 pinctrl-names = "default"; 1559 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1560 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1561 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1562 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1563 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1564 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1565 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1566 dma-names = "tx", "rx"; 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 status = "disabled"; 1570 }; 1571 1572 i2c11: i2c@a8c000 { 1573 compatible = "qcom,geni-i2c"; 1574 reg = <0x0 0x00a8c000 0x0 0x4000>; 1575 clock-names = "se"; 1576 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1577 pinctrl-names = "default"; 1578 pinctrl-0 = <&qup_i2c11_data_clk>; 1579 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1580 #address-cells = <1>; 1581 #size-cells = <0>; 1582 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1583 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1584 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1585 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1586 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1587 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1588 dma-names = "tx", "rx"; 1589 status = "disabled"; 1590 }; 1591 1592 spi11: spi@a8c000 { 1593 compatible = "qcom,geni-spi"; 1594 reg = <0x0 0x00a8c000 0x0 0x4000>; 1595 clock-names = "se"; 1596 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1597 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1598 pinctrl-names = "default"; 1599 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1600 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1601 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1602 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1603 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1604 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1605 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1606 dma-names = "tx", "rx"; 1607 #address-cells = <1>; 1608 #size-cells = <0>; 1609 status = "disabled"; 1610 }; 1611 1612 i2c12: i2c@a90000 { 1613 compatible = "qcom,geni-i2c"; 1614 reg = <0x0 0x00a90000 0x0 0x4000>; 1615 clock-names = "se"; 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1617 pinctrl-names = "default"; 1618 pinctrl-0 = <&qup_i2c12_data_clk>; 1619 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1623 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1624 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1625 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1626 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1627 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1628 dma-names = "tx", "rx"; 1629 status = "disabled"; 1630 }; 1631 1632 spi12: spi@a90000 { 1633 compatible = "qcom,geni-spi"; 1634 reg = <0x0 0x00a90000 0x0 0x4000>; 1635 clock-names = "se"; 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1637 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1638 pinctrl-names = "default"; 1639 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1640 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1641 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1642 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1643 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1644 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1645 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1646 dma-names = "tx", "rx"; 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 status = "disabled"; 1650 }; 1651 1652 i2c13: i2c@a94000 { 1653 compatible = "qcom,geni-i2c"; 1654 reg = <0 0x00a94000 0 0x4000>; 1655 clock-names = "se"; 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1657 pinctrl-names = "default"; 1658 pinctrl-0 = <&qup_i2c13_data_clk>; 1659 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1660 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1661 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1662 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1663 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1664 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1665 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1666 dma-names = "tx", "rx"; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 status = "disabled"; 1670 }; 1671 1672 spi13: spi@a94000 { 1673 compatible = "qcom,geni-spi"; 1674 reg = <0x0 0x00a94000 0x0 0x4000>; 1675 clock-names = "se"; 1676 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1677 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1678 pinctrl-names = "default"; 1679 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1681 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1682 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1683 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1684 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1685 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1686 dma-names = "tx", "rx"; 1687 #address-cells = <1>; 1688 #size-cells = <0>; 1689 status = "disabled"; 1690 }; 1691 1692 i2c14: i2c@a98000 { 1693 compatible = "qcom,geni-i2c"; 1694 reg = <0 0x00a98000 0 0x4000>; 1695 clock-names = "se"; 1696 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1697 pinctrl-names = "default"; 1698 pinctrl-0 = <&qup_i2c14_data_clk>; 1699 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1700 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1701 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1702 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1703 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1704 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1705 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1706 dma-names = "tx", "rx"; 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 status = "disabled"; 1710 }; 1711 1712 spi14: spi@a98000 { 1713 compatible = "qcom,geni-spi"; 1714 reg = <0x0 0x00a98000 0x0 0x4000>; 1715 clock-names = "se"; 1716 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1717 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1718 pinctrl-names = "default"; 1719 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1720 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1721 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1722 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1723 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1724 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1725 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1726 dma-names = "tx", "rx"; 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 status = "disabled"; 1730 }; 1731 }; 1732 1733 pcie0: pci@1c00000 { 1734 compatible = "qcom,pcie-sm8450-pcie0"; 1735 reg = <0 0x01c00000 0 0x3000>, 1736 <0 0x60000000 0 0xf1d>, 1737 <0 0x60000f20 0 0xa8>, 1738 <0 0x60001000 0 0x1000>, 1739 <0 0x60100000 0 0x100000>; 1740 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1741 device_type = "pci"; 1742 linux,pci-domain = <0>; 1743 bus-range = <0x00 0xff>; 1744 num-lanes = <1>; 1745 1746 #address-cells = <3>; 1747 #size-cells = <2>; 1748 1749 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1750 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1751 1752 /* 1753 * MSIs for BDF (1:0.0) only works with Device ID 0x5980. 1754 * Hence, the IDs are swapped. 1755 */ 1756 msi-map = <0x0 &gic_its 0x5981 0x1>, 1757 <0x100 &gic_its 0x5980 0x1>; 1758 msi-map-mask = <0xff00>; 1759 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1760 interrupt-names = "msi"; 1761 #interrupt-cells = <1>; 1762 interrupt-map-mask = <0 0 0 0x7>; 1763 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1764 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1765 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1766 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1767 1768 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1769 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1770 <&pcie0_lane>, 1771 <&rpmhcc RPMH_CXO_CLK>, 1772 <&gcc GCC_PCIE_0_AUX_CLK>, 1773 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1774 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1775 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1776 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1777 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1778 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1779 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1780 clock-names = "pipe", 1781 "pipe_mux", 1782 "phy_pipe", 1783 "ref", 1784 "aux", 1785 "cfg", 1786 "bus_master", 1787 "bus_slave", 1788 "slave_q2a", 1789 "ddrss_sf_tbu", 1790 "aggre0", 1791 "aggre1"; 1792 1793 iommus = <&apps_smmu 0x1c00 0x7f>; 1794 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1795 <0x100 &apps_smmu 0x1c01 0x1>; 1796 1797 resets = <&gcc GCC_PCIE_0_BCR>; 1798 reset-names = "pci"; 1799 1800 power-domains = <&gcc PCIE_0_GDSC>; 1801 power-domain-names = "gdsc"; 1802 1803 phys = <&pcie0_lane>; 1804 phy-names = "pciephy"; 1805 1806 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1807 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1808 1809 pinctrl-names = "default"; 1810 pinctrl-0 = <&pcie0_default_state>; 1811 1812 status = "disabled"; 1813 }; 1814 1815 pcie0_phy: phy@1c06000 { 1816 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1817 reg = <0 0x01c06000 0 0x200>; 1818 #address-cells = <2>; 1819 #size-cells = <2>; 1820 ranges; 1821 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1822 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1823 <&gcc GCC_PCIE_0_CLKREF_EN>, 1824 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1825 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1826 1827 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1828 reset-names = "phy"; 1829 1830 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1831 assigned-clock-rates = <100000000>; 1832 1833 status = "disabled"; 1834 1835 pcie0_lane: phy@1c06200 { 1836 reg = <0 0x01c06e00 0 0x200>, /* tx */ 1837 <0 0x01c07000 0 0x200>, /* rx */ 1838 <0 0x01c06200 0 0x200>, /* pcs */ 1839 <0 0x01c06600 0 0x200>; /* pcs_pcie */ 1840 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1841 clock-names = "pipe0"; 1842 1843 #clock-cells = <0>; 1844 #phy-cells = <0>; 1845 clock-output-names = "pcie_0_pipe_clk"; 1846 }; 1847 }; 1848 1849 pcie1: pci@1c08000 { 1850 compatible = "qcom,pcie-sm8450-pcie1"; 1851 reg = <0 0x01c08000 0 0x3000>, 1852 <0 0x40000000 0 0xf1d>, 1853 <0 0x40000f20 0 0xa8>, 1854 <0 0x40001000 0 0x1000>, 1855 <0 0x40100000 0 0x100000>; 1856 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1857 device_type = "pci"; 1858 linux,pci-domain = <1>; 1859 bus-range = <0x00 0xff>; 1860 num-lanes = <2>; 1861 1862 #address-cells = <3>; 1863 #size-cells = <2>; 1864 1865 ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, 1866 <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; 1867 1868 /* 1869 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. 1870 * Hence, the IDs are swapped. 1871 */ 1872 msi-map = <0x0 &gic_its 0x5a01 0x1>, 1873 <0x100 &gic_its 0x5a00 0x1>; 1874 msi-map-mask = <0xff00>; 1875 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1876 interrupt-names = "msi"; 1877 #interrupt-cells = <1>; 1878 interrupt-map-mask = <0 0 0 0x7>; 1879 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1880 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1881 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1882 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1883 1884 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1885 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1886 <&pcie1_lane>, 1887 <&rpmhcc RPMH_CXO_CLK>, 1888 <&gcc GCC_PCIE_1_AUX_CLK>, 1889 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1890 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1891 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1892 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1893 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1894 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1895 clock-names = "pipe", 1896 "pipe_mux", 1897 "phy_pipe", 1898 "ref", 1899 "aux", 1900 "cfg", 1901 "bus_master", 1902 "bus_slave", 1903 "slave_q2a", 1904 "ddrss_sf_tbu", 1905 "aggre1"; 1906 1907 iommus = <&apps_smmu 0x1c80 0x7f>; 1908 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1909 <0x100 &apps_smmu 0x1c81 0x1>; 1910 1911 resets = <&gcc GCC_PCIE_1_BCR>; 1912 reset-names = "pci"; 1913 1914 power-domains = <&gcc PCIE_1_GDSC>; 1915 power-domain-names = "gdsc"; 1916 1917 phys = <&pcie1_lane>; 1918 phy-names = "pciephy"; 1919 1920 perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; 1921 enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1922 1923 pinctrl-names = "default"; 1924 pinctrl-0 = <&pcie1_default_state>; 1925 1926 status = "disabled"; 1927 }; 1928 1929 pcie1_phy: phy@1c0f000 { 1930 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 1931 reg = <0 0x01c0f000 0 0x200>; 1932 #address-cells = <2>; 1933 #size-cells = <2>; 1934 ranges; 1935 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1936 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1937 <&gcc GCC_PCIE_1_CLKREF_EN>, 1938 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1939 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1940 1941 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1942 reset-names = "phy"; 1943 1944 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1945 assigned-clock-rates = <100000000>; 1946 1947 status = "disabled"; 1948 1949 pcie1_lane: phy@1c0e000 { 1950 reg = <0 0x01c0e000 0 0x200>, /* tx */ 1951 <0 0x01c0e200 0 0x300>, /* rx */ 1952 <0 0x01c0f200 0 0x200>, /* pcs */ 1953 <0 0x01c0e800 0 0x200>, /* tx */ 1954 <0 0x01c0ea00 0 0x300>, /* rx */ 1955 <0 0x01c0f400 0 0xc00>; /* pcs_pcie */ 1956 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1957 clock-names = "pipe0"; 1958 1959 #clock-cells = <0>; 1960 #phy-cells = <0>; 1961 clock-output-names = "pcie_1_pipe_clk"; 1962 }; 1963 }; 1964 1965 config_noc: interconnect@1500000 { 1966 compatible = "qcom,sm8450-config-noc"; 1967 reg = <0 0x01500000 0 0x1c000>; 1968 #interconnect-cells = <2>; 1969 qcom,bcm-voters = <&apps_bcm_voter>; 1970 }; 1971 1972 system_noc: interconnect@1680000 { 1973 compatible = "qcom,sm8450-system-noc"; 1974 reg = <0 0x01680000 0 0x1e200>; 1975 #interconnect-cells = <2>; 1976 qcom,bcm-voters = <&apps_bcm_voter>; 1977 }; 1978 1979 pcie_noc: interconnect@16c0000 { 1980 compatible = "qcom,sm8450-pcie-anoc"; 1981 reg = <0 0x016c0000 0 0xe280>; 1982 #interconnect-cells = <2>; 1983 qcom,bcm-voters = <&apps_bcm_voter>; 1984 }; 1985 1986 aggre1_noc: interconnect@16e0000 { 1987 compatible = "qcom,sm8450-aggre1-noc"; 1988 reg = <0 0x016e0000 0 0x1c080>; 1989 #interconnect-cells = <2>; 1990 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1991 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1992 qcom,bcm-voters = <&apps_bcm_voter>; 1993 }; 1994 1995 aggre2_noc: interconnect@1700000 { 1996 compatible = "qcom,sm8450-aggre2-noc"; 1997 reg = <0 0x01700000 0 0x31080>; 1998 #interconnect-cells = <2>; 1999 qcom,bcm-voters = <&apps_bcm_voter>; 2000 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2001 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 2002 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2003 <&rpmhcc RPMH_IPA_CLK>; 2004 }; 2005 2006 mmss_noc: interconnect@1740000 { 2007 compatible = "qcom,sm8450-mmss-noc"; 2008 reg = <0 0x01740000 0 0x1f080>; 2009 #interconnect-cells = <2>; 2010 qcom,bcm-voters = <&apps_bcm_voter>; 2011 }; 2012 2013 tcsr_mutex: hwlock@1f40000 { 2014 compatible = "qcom,tcsr-mutex"; 2015 reg = <0x0 0x01f40000 0x0 0x40000>; 2016 #hwlock-cells = <1>; 2017 }; 2018 2019 tcsr: syscon@1fc0000 { 2020 compatible = "qcom,sm8450-tcsr", "syscon"; 2021 reg = <0x0 0x1fc0000 0x0 0x30000>; 2022 }; 2023 2024 usb_1_hsphy: phy@88e3000 { 2025 compatible = "qcom,sm8450-usb-hs-phy", 2026 "qcom,usb-snps-hs-7nm-phy"; 2027 reg = <0 0x088e3000 0 0x400>; 2028 status = "disabled"; 2029 #phy-cells = <0>; 2030 2031 clocks = <&rpmhcc RPMH_CXO_CLK>; 2032 clock-names = "ref"; 2033 2034 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2035 }; 2036 2037 usb_1_qmpphy: phy-wrapper@88e9000 { 2038 compatible = "qcom,sm8450-qmp-usb3-phy"; 2039 reg = <0 0x088e9000 0 0x200>, 2040 <0 0x088e8000 0 0x20>; 2041 status = "disabled"; 2042 #address-cells = <2>; 2043 #size-cells = <2>; 2044 ranges; 2045 2046 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2047 <&rpmhcc RPMH_CXO_CLK>, 2048 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2049 clock-names = "aux", "ref_clk_src", "com_aux"; 2050 2051 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2052 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2053 reset-names = "phy", "common"; 2054 2055 usb_1_ssphy: phy@88e9200 { 2056 reg = <0 0x088e9200 0 0x200>, 2057 <0 0x088e9400 0 0x200>, 2058 <0 0x088e9c00 0 0x400>, 2059 <0 0x088e9600 0 0x200>, 2060 <0 0x088e9800 0 0x200>, 2061 <0 0x088e9a00 0 0x100>; 2062 #phy-cells = <0>; 2063 #clock-cells = <0>; 2064 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2065 clock-names = "pipe0"; 2066 clock-output-names = "usb3_phy_pipe_clk_src"; 2067 }; 2068 }; 2069 2070 remoteproc_slpi: remoteproc@2400000 { 2071 compatible = "qcom,sm8450-slpi-pas"; 2072 reg = <0 0x02400000 0 0x4000>; 2073 2074 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2075 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2076 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2077 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2078 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2079 interrupt-names = "wdog", "fatal", "ready", 2080 "handover", "stop-ack"; 2081 2082 clocks = <&rpmhcc RPMH_CXO_CLK>; 2083 clock-names = "xo"; 2084 2085 power-domains = <&rpmhpd SM8450_LCX>, 2086 <&rpmhpd SM8450_LMX>; 2087 power-domain-names = "lcx", "lmx"; 2088 2089 memory-region = <&slpi_mem>; 2090 2091 qcom,qmp = <&aoss_qmp>; 2092 2093 qcom,smem-states = <&smp2p_slpi_out 0>; 2094 qcom,smem-state-names = "stop"; 2095 2096 status = "disabled"; 2097 2098 glink-edge { 2099 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2100 IPCC_MPROC_SIGNAL_GLINK_QMP 2101 IRQ_TYPE_EDGE_RISING>; 2102 mboxes = <&ipcc IPCC_CLIENT_SLPI 2103 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2104 2105 label = "slpi"; 2106 qcom,remote-pid = <3>; 2107 2108 fastrpc { 2109 compatible = "qcom,fastrpc"; 2110 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2111 label = "sdsp"; 2112 #address-cells = <1>; 2113 #size-cells = <0>; 2114 2115 compute-cb@1 { 2116 compatible = "qcom,fastrpc-compute-cb"; 2117 reg = <1>; 2118 iommus = <&apps_smmu 0x0541 0x0>; 2119 }; 2120 2121 compute-cb@2 { 2122 compatible = "qcom,fastrpc-compute-cb"; 2123 reg = <2>; 2124 iommus = <&apps_smmu 0x0542 0x0>; 2125 }; 2126 2127 compute-cb@3 { 2128 compatible = "qcom,fastrpc-compute-cb"; 2129 reg = <3>; 2130 iommus = <&apps_smmu 0x0543 0x0>; 2131 /* note: shared-cb = <4> in downstream */ 2132 }; 2133 }; 2134 }; 2135 }; 2136 2137 wsa2macro: codec@31e0000 { 2138 compatible = "qcom,sm8450-lpass-wsa-macro"; 2139 reg = <0 0x031e0000 0 0x1000>; 2140 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2141 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2142 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2143 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2144 <&vamacro>; 2145 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2146 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2147 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2148 assigned-clock-rates = <19200000>, <19200000>; 2149 2150 #clock-cells = <0>; 2151 clock-output-names = "wsa2-mclk"; 2152 pinctrl-names = "default"; 2153 pinctrl-0 = <&wsa2_swr_active>; 2154 #sound-dai-cells = <1>; 2155 }; 2156 2157 /* WSA2 */ 2158 swr4: soundwire-controller@31f0000 { 2159 compatible = "qcom,soundwire-v1.7.0"; 2160 reg = <0 0x031f0000 0 0x2000>; 2161 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2162 clocks = <&wsa2macro>; 2163 clock-names = "iface"; 2164 2165 qcom,din-ports = <2>; 2166 qcom,dout-ports = <6>; 2167 2168 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2169 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2170 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2171 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2172 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2173 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2174 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2175 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2176 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2177 2178 #address-cells = <2>; 2179 #size-cells = <0>; 2180 #sound-dai-cells = <1>; 2181 status = "disabled"; 2182 }; 2183 2184 rxmacro: codec@3200000 { 2185 compatible = "qcom,sm8450-lpass-rx-macro"; 2186 reg = <0 0x03200000 0 0x1000>; 2187 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2188 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2189 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2190 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2191 <&vamacro>; 2192 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2193 2194 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2195 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2196 assigned-clock-rates = <19200000>, <19200000>; 2197 2198 #clock-cells = <0>; 2199 clock-output-names = "mclk"; 2200 pinctrl-names = "default"; 2201 pinctrl-0 = <&rx_swr_active>; 2202 #sound-dai-cells = <1>; 2203 }; 2204 2205 swr1: soundwire-controller@3210000 { 2206 compatible = "qcom,soundwire-v1.7.0"; 2207 reg = <0 0x03210000 0 0x2000>; 2208 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2209 clocks = <&rxmacro>; 2210 clock-names = "iface"; 2211 label = "RX"; 2212 qcom,din-ports = <0>; 2213 qcom,dout-ports = <5>; 2214 2215 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2216 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2217 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2218 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2219 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2220 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2221 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2222 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2223 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2224 2225 #address-cells = <2>; 2226 #size-cells = <0>; 2227 #sound-dai-cells = <1>; 2228 status = "disabled"; 2229 }; 2230 2231 txmacro: codec@3220000 { 2232 compatible = "qcom,sm8450-lpass-tx-macro"; 2233 reg = <0 0x03220000 0 0x1000>; 2234 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2235 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2236 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2237 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2238 <&vamacro>; 2239 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2240 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2241 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2242 assigned-clock-rates = <19200000>, <19200000>; 2243 2244 #clock-cells = <0>; 2245 clock-output-names = "mclk"; 2246 pinctrl-names = "default"; 2247 pinctrl-0 = <&tx_swr_active>; 2248 #sound-dai-cells = <1>; 2249 }; 2250 2251 wsamacro: codec@3240000 { 2252 compatible = "qcom,sm8450-lpass-wsa-macro"; 2253 reg = <0 0x03240000 0 0x1000>; 2254 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2255 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2256 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2257 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2258 <&vamacro>; 2259 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2260 2261 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2262 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2263 assigned-clock-rates = <19200000>, <19200000>; 2264 2265 #clock-cells = <0>; 2266 clock-output-names = "mclk"; 2267 pinctrl-names = "default"; 2268 pinctrl-0 = <&wsa_swr_active>; 2269 #sound-dai-cells = <1>; 2270 }; 2271 2272 /* WSA */ 2273 swr0: soundwire-controller@3250000 { 2274 compatible = "qcom,soundwire-v1.7.0"; 2275 reg = <0 0x03250000 0 0x2000>; 2276 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2277 clocks = <&wsamacro>; 2278 clock-names = "iface"; 2279 2280 qcom,din-ports = <2>; 2281 qcom,dout-ports = <6>; 2282 2283 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2284 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2285 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2286 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2287 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2288 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2289 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2290 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2291 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2292 2293 #address-cells = <2>; 2294 #size-cells = <0>; 2295 #sound-dai-cells = <1>; 2296 status = "disabled"; 2297 }; 2298 2299 swr2: soundwire-controller@33b0000 { 2300 compatible = "qcom,soundwire-v1.7.0"; 2301 reg = <0 0x033b0000 0 0x2000>; 2302 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2303 <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2304 interrupt-names = "core", "wakeup"; 2305 2306 clocks = <&vamacro>; 2307 clock-names = "iface"; 2308 label = "TX"; 2309 2310 qcom,din-ports = <4>; 2311 qcom,dout-ports = <0>; 2312 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2313 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2314 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2315 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2316 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2317 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2318 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2319 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2320 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2321 2322 #address-cells = <2>; 2323 #size-cells = <0>; 2324 #sound-dai-cells = <1>; 2325 status = "disabled"; 2326 }; 2327 2328 vamacro: codec@33f0000 { 2329 compatible = "qcom,sm8450-lpass-va-macro"; 2330 reg = <0 0x033f0000 0 0x1000>; 2331 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2332 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2333 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2334 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2335 clock-names = "mclk", "macro", "dcodec", "npl"; 2336 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2337 assigned-clock-rates = <19200000>; 2338 2339 #clock-cells = <0>; 2340 clock-output-names = "fsgen"; 2341 #sound-dai-cells = <1>; 2342 status = "disabled"; 2343 }; 2344 2345 remoteproc_adsp: remoteproc@30000000 { 2346 compatible = "qcom,sm8450-adsp-pas"; 2347 reg = <0 0x30000000 0 0x100>; 2348 2349 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2350 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2351 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2352 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2353 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2354 interrupt-names = "wdog", "fatal", "ready", 2355 "handover", "stop-ack"; 2356 2357 clocks = <&rpmhcc RPMH_CXO_CLK>; 2358 clock-names = "xo"; 2359 2360 power-domains = <&rpmhpd SM8450_LCX>, 2361 <&rpmhpd SM8450_LMX>; 2362 power-domain-names = "lcx", "lmx"; 2363 2364 memory-region = <&adsp_mem>; 2365 2366 qcom,qmp = <&aoss_qmp>; 2367 2368 qcom,smem-states = <&smp2p_adsp_out 0>; 2369 qcom,smem-state-names = "stop"; 2370 2371 status = "disabled"; 2372 2373 remoteproc_adsp_glink: glink-edge { 2374 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2375 IPCC_MPROC_SIGNAL_GLINK_QMP 2376 IRQ_TYPE_EDGE_RISING>; 2377 mboxes = <&ipcc IPCC_CLIENT_LPASS 2378 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2379 2380 label = "lpass"; 2381 qcom,remote-pid = <2>; 2382 2383 gpr { 2384 compatible = "qcom,gpr"; 2385 qcom,glink-channels = "adsp_apps"; 2386 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2387 qcom,intents = <512 20>; 2388 #address-cells = <1>; 2389 #size-cells = <0>; 2390 2391 q6apm: service@1 { 2392 compatible = "qcom,q6apm"; 2393 reg = <GPR_APM_MODULE_IID>; 2394 #sound-dai-cells = <0>; 2395 qcom,protection-domain = "avs/audio", 2396 "msm/adsp/audio_pd"; 2397 2398 q6apmdai: dais { 2399 compatible = "qcom,q6apm-dais"; 2400 iommus = <&apps_smmu 0x1801 0x0>; 2401 }; 2402 2403 q6apmbedai: bedais { 2404 compatible = "qcom,q6apm-lpass-dais"; 2405 #sound-dai-cells = <1>; 2406 }; 2407 }; 2408 2409 q6prm: service@2 { 2410 compatible = "qcom,q6prm"; 2411 reg = <GPR_PRM_MODULE_IID>; 2412 qcom,protection-domain = "avs/audio", 2413 "msm/adsp/audio_pd"; 2414 2415 q6prmcc: clock-controller { 2416 compatible = "qcom,q6prm-lpass-clocks"; 2417 #clock-cells = <2>; 2418 }; 2419 }; 2420 }; 2421 2422 fastrpc { 2423 compatible = "qcom,fastrpc"; 2424 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2425 label = "adsp"; 2426 #address-cells = <1>; 2427 #size-cells = <0>; 2428 2429 compute-cb@3 { 2430 compatible = "qcom,fastrpc-compute-cb"; 2431 reg = <3>; 2432 iommus = <&apps_smmu 0x1803 0x0>; 2433 }; 2434 2435 compute-cb@4 { 2436 compatible = "qcom,fastrpc-compute-cb"; 2437 reg = <4>; 2438 iommus = <&apps_smmu 0x1804 0x0>; 2439 }; 2440 2441 compute-cb@5 { 2442 compatible = "qcom,fastrpc-compute-cb"; 2443 reg = <5>; 2444 iommus = <&apps_smmu 0x1805 0x0>; 2445 }; 2446 }; 2447 }; 2448 }; 2449 2450 remoteproc_cdsp: remoteproc@32300000 { 2451 compatible = "qcom,sm8450-cdsp-pas"; 2452 reg = <0 0x32300000 0 0x1400000>; 2453 2454 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2455 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2456 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2457 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2458 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2459 interrupt-names = "wdog", "fatal", "ready", 2460 "handover", "stop-ack"; 2461 2462 clocks = <&rpmhcc RPMH_CXO_CLK>; 2463 clock-names = "xo"; 2464 2465 power-domains = <&rpmhpd SM8450_CX>, 2466 <&rpmhpd SM8450_MXC>; 2467 power-domain-names = "cx", "mxc"; 2468 2469 memory-region = <&cdsp_mem>; 2470 2471 qcom,qmp = <&aoss_qmp>; 2472 2473 qcom,smem-states = <&smp2p_cdsp_out 0>; 2474 qcom,smem-state-names = "stop"; 2475 2476 status = "disabled"; 2477 2478 glink-edge { 2479 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2480 IPCC_MPROC_SIGNAL_GLINK_QMP 2481 IRQ_TYPE_EDGE_RISING>; 2482 mboxes = <&ipcc IPCC_CLIENT_CDSP 2483 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2484 2485 label = "cdsp"; 2486 qcom,remote-pid = <5>; 2487 2488 fastrpc { 2489 compatible = "qcom,fastrpc"; 2490 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2491 label = "cdsp"; 2492 #address-cells = <1>; 2493 #size-cells = <0>; 2494 2495 compute-cb@1 { 2496 compatible = "qcom,fastrpc-compute-cb"; 2497 reg = <1>; 2498 iommus = <&apps_smmu 0x2161 0x0400>, 2499 <&apps_smmu 0x1021 0x1420>; 2500 }; 2501 2502 compute-cb@2 { 2503 compatible = "qcom,fastrpc-compute-cb"; 2504 reg = <2>; 2505 iommus = <&apps_smmu 0x2162 0x0400>, 2506 <&apps_smmu 0x1022 0x1420>; 2507 }; 2508 2509 compute-cb@3 { 2510 compatible = "qcom,fastrpc-compute-cb"; 2511 reg = <3>; 2512 iommus = <&apps_smmu 0x2163 0x0400>, 2513 <&apps_smmu 0x1023 0x1420>; 2514 }; 2515 2516 compute-cb@4 { 2517 compatible = "qcom,fastrpc-compute-cb"; 2518 reg = <4>; 2519 iommus = <&apps_smmu 0x2164 0x0400>, 2520 <&apps_smmu 0x1024 0x1420>; 2521 }; 2522 2523 compute-cb@5 { 2524 compatible = "qcom,fastrpc-compute-cb"; 2525 reg = <5>; 2526 iommus = <&apps_smmu 0x2165 0x0400>, 2527 <&apps_smmu 0x1025 0x1420>; 2528 }; 2529 2530 compute-cb@6 { 2531 compatible = "qcom,fastrpc-compute-cb"; 2532 reg = <6>; 2533 iommus = <&apps_smmu 0x2166 0x0400>, 2534 <&apps_smmu 0x1026 0x1420>; 2535 }; 2536 2537 compute-cb@7 { 2538 compatible = "qcom,fastrpc-compute-cb"; 2539 reg = <7>; 2540 iommus = <&apps_smmu 0x2167 0x0400>, 2541 <&apps_smmu 0x1027 0x1420>; 2542 }; 2543 2544 compute-cb@8 { 2545 compatible = "qcom,fastrpc-compute-cb"; 2546 reg = <8>; 2547 iommus = <&apps_smmu 0x2168 0x0400>, 2548 <&apps_smmu 0x1028 0x1420>; 2549 }; 2550 2551 /* note: secure cb9 in downstream */ 2552 }; 2553 }; 2554 }; 2555 2556 remoteproc_mpss: remoteproc@4080000 { 2557 compatible = "qcom,sm8450-mpss-pas"; 2558 reg = <0x0 0x04080000 0x0 0x4040>; 2559 2560 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2561 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2562 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2563 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2564 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2565 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2566 interrupt-names = "wdog", "fatal", "ready", "handover", 2567 "stop-ack", "shutdown-ack"; 2568 2569 clocks = <&rpmhcc RPMH_CXO_CLK>; 2570 clock-names = "xo"; 2571 2572 power-domains = <&rpmhpd SM8450_CX>, 2573 <&rpmhpd SM8450_MSS>; 2574 power-domain-names = "cx", "mss"; 2575 2576 memory-region = <&mpss_mem>; 2577 2578 qcom,qmp = <&aoss_qmp>; 2579 2580 qcom,smem-states = <&smp2p_modem_out 0>; 2581 qcom,smem-state-names = "stop"; 2582 2583 status = "disabled"; 2584 2585 glink-edge { 2586 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2587 IPCC_MPROC_SIGNAL_GLINK_QMP 2588 IRQ_TYPE_EDGE_RISING>; 2589 mboxes = <&ipcc IPCC_CLIENT_MPSS 2590 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2591 label = "modem"; 2592 qcom,remote-pid = <1>; 2593 }; 2594 }; 2595 2596 cci0: cci@ac15000 { 2597 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2598 reg = <0 0x0ac15000 0 0x1000>; 2599 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 2600 power-domains = <&camcc TITAN_TOP_GDSC>; 2601 2602 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2603 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2604 <&camcc CAM_CC_CPAS_AHB_CLK>, 2605 <&camcc CAM_CC_CCI_0_CLK>, 2606 <&camcc CAM_CC_CCI_0_CLK_SRC>; 2607 clock-names = "camnoc_axi", 2608 "slow_ahb_src", 2609 "cpas_ahb", 2610 "cci", 2611 "cci_src"; 2612 pinctrl-0 = <&cci0_default &cci1_default>; 2613 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2614 pinctrl-names = "default", "sleep"; 2615 2616 status = "disabled"; 2617 #address-cells = <1>; 2618 #size-cells = <0>; 2619 2620 cci0_i2c0: i2c-bus@0 { 2621 reg = <0>; 2622 clock-frequency = <1000000>; 2623 #address-cells = <1>; 2624 #size-cells = <0>; 2625 }; 2626 2627 cci0_i2c1: i2c-bus@1 { 2628 reg = <1>; 2629 clock-frequency = <1000000>; 2630 #address-cells = <1>; 2631 #size-cells = <0>; 2632 }; 2633 }; 2634 2635 cci1: cci@ac16000 { 2636 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2637 reg = <0 0x0ac16000 0 0x1000>; 2638 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 2639 power-domains = <&camcc TITAN_TOP_GDSC>; 2640 2641 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2642 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2643 <&camcc CAM_CC_CPAS_AHB_CLK>, 2644 <&camcc CAM_CC_CCI_1_CLK>, 2645 <&camcc CAM_CC_CCI_1_CLK_SRC>; 2646 clock-names = "camnoc_axi", 2647 "slow_ahb_src", 2648 "cpas_ahb", 2649 "cci", 2650 "cci_src"; 2651 pinctrl-0 = <&cci2_default &cci3_default>; 2652 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 2653 pinctrl-names = "default", "sleep"; 2654 2655 status = "disabled"; 2656 #address-cells = <1>; 2657 #size-cells = <0>; 2658 2659 cci1_i2c0: i2c-bus@0 { 2660 reg = <0>; 2661 clock-frequency = <1000000>; 2662 #address-cells = <1>; 2663 #size-cells = <0>; 2664 }; 2665 2666 cci1_i2c1: i2c-bus@1 { 2667 reg = <1>; 2668 clock-frequency = <1000000>; 2669 #address-cells = <1>; 2670 #size-cells = <0>; 2671 }; 2672 }; 2673 2674 camcc: clock-controller@ade0000 { 2675 compatible = "qcom,sm8450-camcc"; 2676 reg = <0 0x0ade0000 0 0x20000>; 2677 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2678 <&rpmhcc RPMH_CXO_CLK>, 2679 <&rpmhcc RPMH_CXO_CLK_A>, 2680 <&sleep_clk>; 2681 power-domains = <&rpmhpd SM8450_MMCX>; 2682 required-opps = <&rpmhpd_opp_low_svs>; 2683 #clock-cells = <1>; 2684 #reset-cells = <1>; 2685 #power-domain-cells = <1>; 2686 status = "disabled"; 2687 }; 2688 2689 mdss: display-subsystem@ae00000 { 2690 compatible = "qcom,sm8450-mdss"; 2691 reg = <0 0x0ae00000 0 0x1000>; 2692 reg-names = "mdss"; 2693 2694 /* same path used twice */ 2695 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2696 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; 2697 interconnect-names = "mdp0-mem", "mdp1-mem"; 2698 2699 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2700 2701 power-domains = <&dispcc MDSS_GDSC>; 2702 2703 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2704 <&gcc GCC_DISP_HF_AXI_CLK>, 2705 <&gcc GCC_DISP_SF_AXI_CLK>, 2706 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2707 2708 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2709 interrupt-controller; 2710 #interrupt-cells = <1>; 2711 2712 iommus = <&apps_smmu 0x2800 0x402>; 2713 2714 #address-cells = <2>; 2715 #size-cells = <2>; 2716 ranges; 2717 2718 status = "disabled"; 2719 2720 mdss_mdp: display-controller@ae01000 { 2721 compatible = "qcom,sm8450-dpu"; 2722 reg = <0 0x0ae01000 0 0x8f000>, 2723 <0 0x0aeb0000 0 0x2008>; 2724 reg-names = "mdp", "vbif"; 2725 2726 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2727 <&gcc GCC_DISP_SF_AXI_CLK>, 2728 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2729 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2730 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2731 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2732 clock-names = "bus", 2733 "nrt_bus", 2734 "iface", 2735 "lut", 2736 "core", 2737 "vsync"; 2738 2739 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2740 assigned-clock-rates = <19200000>; 2741 2742 operating-points-v2 = <&mdp_opp_table>; 2743 power-domains = <&rpmhpd SM8450_MMCX>; 2744 2745 interrupt-parent = <&mdss>; 2746 interrupts = <0>; 2747 2748 ports { 2749 #address-cells = <1>; 2750 #size-cells = <0>; 2751 2752 port@0 { 2753 reg = <0>; 2754 dpu_intf1_out: endpoint { 2755 remote-endpoint = <&mdss_dsi0_in>; 2756 }; 2757 }; 2758 2759 port@1 { 2760 reg = <1>; 2761 dpu_intf2_out: endpoint { 2762 remote-endpoint = <&mdss_dsi1_in>; 2763 }; 2764 }; 2765 2766 }; 2767 2768 mdp_opp_table: opp-table { 2769 compatible = "operating-points-v2"; 2770 2771 opp-172000000 { 2772 opp-hz = /bits/ 64 <172000000>; 2773 required-opps = <&rpmhpd_opp_low_svs_d1>; 2774 }; 2775 2776 opp-200000000 { 2777 opp-hz = /bits/ 64 <200000000>; 2778 required-opps = <&rpmhpd_opp_low_svs>; 2779 }; 2780 2781 opp-325000000 { 2782 opp-hz = /bits/ 64 <325000000>; 2783 required-opps = <&rpmhpd_opp_svs>; 2784 }; 2785 2786 opp-375000000 { 2787 opp-hz = /bits/ 64 <375000000>; 2788 required-opps = <&rpmhpd_opp_svs_l1>; 2789 }; 2790 2791 opp-500000000 { 2792 opp-hz = /bits/ 64 <500000000>; 2793 required-opps = <&rpmhpd_opp_nom>; 2794 }; 2795 }; 2796 }; 2797 2798 mdss_dsi0: dsi@ae94000 { 2799 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2800 reg = <0 0x0ae94000 0 0x400>; 2801 reg-names = "dsi_ctrl"; 2802 2803 interrupt-parent = <&mdss>; 2804 interrupts = <4>; 2805 2806 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2807 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2808 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2809 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2810 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2811 <&gcc GCC_DISP_HF_AXI_CLK>; 2812 clock-names = "byte", 2813 "byte_intf", 2814 "pixel", 2815 "core", 2816 "iface", 2817 "bus"; 2818 2819 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2820 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 2821 2822 operating-points-v2 = <&mdss_dsi_opp_table>; 2823 power-domains = <&rpmhpd SM8450_MMCX>; 2824 2825 phys = <&mdss_dsi0_phy>; 2826 phy-names = "dsi"; 2827 2828 #address-cells = <1>; 2829 #size-cells = <0>; 2830 2831 status = "disabled"; 2832 2833 ports { 2834 #address-cells = <1>; 2835 #size-cells = <0>; 2836 2837 port@0 { 2838 reg = <0>; 2839 mdss_dsi0_in: endpoint { 2840 remote-endpoint = <&dpu_intf1_out>; 2841 }; 2842 }; 2843 2844 port@1 { 2845 reg = <1>; 2846 mdss_dsi0_out: endpoint { 2847 }; 2848 }; 2849 }; 2850 2851 mdss_dsi_opp_table: opp-table { 2852 compatible = "operating-points-v2"; 2853 2854 opp-187500000 { 2855 opp-hz = /bits/ 64 <187500000>; 2856 required-opps = <&rpmhpd_opp_low_svs>; 2857 }; 2858 2859 opp-300000000 { 2860 opp-hz = /bits/ 64 <300000000>; 2861 required-opps = <&rpmhpd_opp_svs>; 2862 }; 2863 2864 opp-358000000 { 2865 opp-hz = /bits/ 64 <358000000>; 2866 required-opps = <&rpmhpd_opp_svs_l1>; 2867 }; 2868 }; 2869 }; 2870 2871 mdss_dsi0_phy: phy@ae94400 { 2872 compatible = "qcom,sm8450-dsi-phy-5nm"; 2873 reg = <0 0x0ae94400 0 0x200>, 2874 <0 0x0ae94600 0 0x280>, 2875 <0 0x0ae94900 0 0x260>; 2876 reg-names = "dsi_phy", 2877 "dsi_phy_lane", 2878 "dsi_pll"; 2879 2880 #clock-cells = <1>; 2881 #phy-cells = <0>; 2882 2883 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2884 <&rpmhcc RPMH_CXO_CLK>; 2885 clock-names = "iface", "ref"; 2886 2887 status = "disabled"; 2888 }; 2889 2890 mdss_dsi1: dsi@ae96000 { 2891 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2892 reg = <0 0x0ae96000 0 0x400>; 2893 reg-names = "dsi_ctrl"; 2894 2895 interrupt-parent = <&mdss>; 2896 interrupts = <5>; 2897 2898 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2899 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2900 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2901 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2902 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2903 <&gcc GCC_DISP_HF_AXI_CLK>; 2904 clock-names = "byte", 2905 "byte_intf", 2906 "pixel", 2907 "core", 2908 "iface", 2909 "bus"; 2910 2911 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2912 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 2913 2914 operating-points-v2 = <&mdss_dsi_opp_table>; 2915 power-domains = <&rpmhpd SM8450_MMCX>; 2916 2917 phys = <&mdss_dsi1_phy>; 2918 phy-names = "dsi"; 2919 2920 #address-cells = <1>; 2921 #size-cells = <0>; 2922 2923 status = "disabled"; 2924 2925 ports { 2926 #address-cells = <1>; 2927 #size-cells = <0>; 2928 2929 port@0 { 2930 reg = <0>; 2931 mdss_dsi1_in: endpoint { 2932 remote-endpoint = <&dpu_intf2_out>; 2933 }; 2934 }; 2935 2936 port@1 { 2937 reg = <1>; 2938 mdss_dsi1_out: endpoint { 2939 }; 2940 }; 2941 }; 2942 }; 2943 2944 mdss_dsi1_phy: phy@ae96400 { 2945 compatible = "qcom,sm8450-dsi-phy-5nm"; 2946 reg = <0 0x0ae96400 0 0x200>, 2947 <0 0x0ae96600 0 0x280>, 2948 <0 0x0ae96900 0 0x260>; 2949 reg-names = "dsi_phy", 2950 "dsi_phy_lane", 2951 "dsi_pll"; 2952 2953 #clock-cells = <1>; 2954 #phy-cells = <0>; 2955 2956 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2957 <&rpmhcc RPMH_CXO_CLK>; 2958 clock-names = "iface", "ref"; 2959 2960 status = "disabled"; 2961 }; 2962 }; 2963 2964 dispcc: clock-controller@af00000 { 2965 compatible = "qcom,sm8450-dispcc"; 2966 reg = <0 0x0af00000 0 0x20000>; 2967 clocks = <&rpmhcc RPMH_CXO_CLK>, 2968 <&rpmhcc RPMH_CXO_CLK_A>, 2969 <&gcc GCC_DISP_AHB_CLK>, 2970 <&sleep_clk>, 2971 <&mdss_dsi0_phy 0>, 2972 <&mdss_dsi0_phy 1>, 2973 <&mdss_dsi1_phy 0>, 2974 <&mdss_dsi1_phy 1>, 2975 <0>, /* dp0 */ 2976 <0>, 2977 <0>, /* dp1 */ 2978 <0>, 2979 <0>, /* dp2 */ 2980 <0>, 2981 <0>, /* dp3 */ 2982 <0>; 2983 power-domains = <&rpmhpd SM8450_MMCX>; 2984 required-opps = <&rpmhpd_opp_low_svs>; 2985 #clock-cells = <1>; 2986 #reset-cells = <1>; 2987 #power-domain-cells = <1>; 2988 status = "disabled"; 2989 }; 2990 2991 pdc: interrupt-controller@b220000 { 2992 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 2993 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 2994 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 2995 <94 609 31>, <125 63 1>, <126 716 12>; 2996 #interrupt-cells = <2>; 2997 interrupt-parent = <&intc>; 2998 interrupt-controller; 2999 }; 3000 3001 tsens0: thermal-sensor@c263000 { 3002 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3003 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3004 <0 0x0c222000 0 0x1000>; /* SROT */ 3005 #qcom,sensors = <16>; 3006 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3007 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3008 interrupt-names = "uplow", "critical"; 3009 #thermal-sensor-cells = <1>; 3010 }; 3011 3012 tsens1: thermal-sensor@c265000 { 3013 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3014 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3015 <0 0x0c223000 0 0x1000>; /* SROT */ 3016 #qcom,sensors = <16>; 3017 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3018 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3019 interrupt-names = "uplow", "critical"; 3020 #thermal-sensor-cells = <1>; 3021 }; 3022 3023 aoss_qmp: power-management@c300000 { 3024 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3025 reg = <0 0x0c300000 0 0x400>; 3026 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3027 IRQ_TYPE_EDGE_RISING>; 3028 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3029 3030 #clock-cells = <0>; 3031 }; 3032 3033 spmi_bus: spmi@c400000 { 3034 compatible = "qcom,spmi-pmic-arb"; 3035 reg = <0 0x0c400000 0 0x00003000>, 3036 <0 0x0c500000 0 0x00400000>, 3037 <0 0x0c440000 0 0x00080000>, 3038 <0 0x0c4c0000 0 0x00010000>, 3039 <0 0x0c42d000 0 0x00010000>; 3040 reg-names = "core", 3041 "chnls", 3042 "obsrvr", 3043 "intr", 3044 "cnfg"; 3045 interrupt-names = "periph_irq"; 3046 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3047 qcom,ee = <0>; 3048 qcom,channel = <0>; 3049 interrupt-controller; 3050 #interrupt-cells = <4>; 3051 #address-cells = <2>; 3052 #size-cells = <0>; 3053 }; 3054 3055 ipcc: mailbox@ed18000 { 3056 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3057 reg = <0 0x0ed18000 0 0x1000>; 3058 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3059 interrupt-controller; 3060 #interrupt-cells = <3>; 3061 #mbox-cells = <2>; 3062 }; 3063 3064 tlmm: pinctrl@f100000 { 3065 compatible = "qcom,sm8450-tlmm"; 3066 reg = <0 0x0f100000 0 0x300000>; 3067 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3068 gpio-controller; 3069 #gpio-cells = <2>; 3070 interrupt-controller; 3071 #interrupt-cells = <2>; 3072 gpio-ranges = <&tlmm 0 0 211>; 3073 wakeup-parent = <&pdc>; 3074 3075 sdc2_default_state: sdc2-default-state { 3076 clk-pins { 3077 pins = "sdc2_clk"; 3078 drive-strength = <16>; 3079 bias-disable; 3080 }; 3081 3082 cmd-pins { 3083 pins = "sdc2_cmd"; 3084 drive-strength = <16>; 3085 bias-pull-up; 3086 }; 3087 3088 data-pins { 3089 pins = "sdc2_data"; 3090 drive-strength = <16>; 3091 bias-pull-up; 3092 }; 3093 }; 3094 3095 sdc2_sleep_state: sdc2-sleep-state { 3096 clk-pins { 3097 pins = "sdc2_clk"; 3098 drive-strength = <2>; 3099 bias-disable; 3100 }; 3101 3102 cmd-pins { 3103 pins = "sdc2_cmd"; 3104 drive-strength = <2>; 3105 bias-pull-up; 3106 }; 3107 3108 data-pins { 3109 pins = "sdc2_data"; 3110 drive-strength = <2>; 3111 bias-pull-up; 3112 }; 3113 }; 3114 3115 cci0_default: cci0-default-state { 3116 /* SDA, SCL */ 3117 pins = "gpio110", "gpio111"; 3118 function = "cci_i2c"; 3119 drive-strength = <2>; 3120 bias-pull-up; 3121 }; 3122 3123 cci0_sleep: cci0-sleep-state { 3124 /* SDA, SCL */ 3125 pins = "gpio110", "gpio111"; 3126 function = "cci_i2c"; 3127 drive-strength = <2>; 3128 bias-pull-down; 3129 }; 3130 3131 cci1_default: cci1-default-state { 3132 /* SDA, SCL */ 3133 pins = "gpio112", "gpio113"; 3134 function = "cci_i2c"; 3135 drive-strength = <2>; 3136 bias-pull-up; 3137 }; 3138 3139 cci1_sleep: cci1-sleep-state { 3140 /* SDA, SCL */ 3141 pins = "gpio112", "gpio113"; 3142 function = "cci_i2c"; 3143 drive-strength = <2>; 3144 bias-pull-down; 3145 }; 3146 3147 cci2_default: cci2-default-state { 3148 /* SDA, SCL */ 3149 pins = "gpio114", "gpio115"; 3150 function = "cci_i2c"; 3151 drive-strength = <2>; 3152 bias-pull-up; 3153 }; 3154 3155 cci2_sleep: cci2-sleep-state { 3156 /* SDA, SCL */ 3157 pins = "gpio114", "gpio115"; 3158 function = "cci_i2c"; 3159 drive-strength = <2>; 3160 bias-pull-down; 3161 }; 3162 3163 cci3_default: cci3-default-state { 3164 /* SDA, SCL */ 3165 pins = "gpio208", "gpio209"; 3166 function = "cci_i2c"; 3167 drive-strength = <2>; 3168 bias-pull-up; 3169 }; 3170 3171 cci3_sleep: cci3-sleep-state { 3172 /* SDA, SCL */ 3173 pins = "gpio208", "gpio209"; 3174 function = "cci_i2c"; 3175 drive-strength = <2>; 3176 bias-pull-down; 3177 }; 3178 3179 pcie0_default_state: pcie0-default-state { 3180 perst-pins { 3181 pins = "gpio94"; 3182 function = "gpio"; 3183 drive-strength = <2>; 3184 bias-pull-down; 3185 }; 3186 3187 clkreq-pins { 3188 pins = "gpio95"; 3189 function = "pcie0_clkreqn"; 3190 drive-strength = <2>; 3191 bias-pull-up; 3192 }; 3193 3194 wake-pins { 3195 pins = "gpio96"; 3196 function = "gpio"; 3197 drive-strength = <2>; 3198 bias-pull-up; 3199 }; 3200 }; 3201 3202 pcie1_default_state: pcie1-default-state { 3203 perst-pins { 3204 pins = "gpio97"; 3205 function = "gpio"; 3206 drive-strength = <2>; 3207 bias-pull-down; 3208 }; 3209 3210 clkreq-pins { 3211 pins = "gpio98"; 3212 function = "pcie1_clkreqn"; 3213 drive-strength = <2>; 3214 bias-pull-up; 3215 }; 3216 3217 wake-pins { 3218 pins = "gpio99"; 3219 function = "gpio"; 3220 drive-strength = <2>; 3221 bias-pull-up; 3222 }; 3223 }; 3224 3225 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3226 pins = "gpio0", "gpio1"; 3227 function = "qup0"; 3228 }; 3229 3230 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3231 pins = "gpio4", "gpio5"; 3232 function = "qup1"; 3233 }; 3234 3235 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3236 pins = "gpio8", "gpio9"; 3237 function = "qup2"; 3238 }; 3239 3240 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3241 pins = "gpio12", "gpio13"; 3242 function = "qup3"; 3243 }; 3244 3245 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3246 pins = "gpio16", "gpio17"; 3247 function = "qup4"; 3248 }; 3249 3250 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3251 pins = "gpio206", "gpio207"; 3252 function = "qup5"; 3253 }; 3254 3255 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3256 pins = "gpio20", "gpio21"; 3257 function = "qup6"; 3258 }; 3259 3260 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3261 pins = "gpio28", "gpio29"; 3262 function = "qup8"; 3263 }; 3264 3265 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3266 pins = "gpio32", "gpio33"; 3267 function = "qup9"; 3268 }; 3269 3270 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3271 pins = "gpio36", "gpio37"; 3272 function = "qup10"; 3273 }; 3274 3275 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3276 pins = "gpio40", "gpio41"; 3277 function = "qup11"; 3278 }; 3279 3280 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3281 pins = "gpio44", "gpio45"; 3282 function = "qup12"; 3283 }; 3284 3285 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3286 pins = "gpio48", "gpio49"; 3287 function = "qup13"; 3288 drive-strength = <2>; 3289 bias-pull-up; 3290 }; 3291 3292 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3293 pins = "gpio52", "gpio53"; 3294 function = "qup14"; 3295 drive-strength = <2>; 3296 bias-pull-up; 3297 }; 3298 3299 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3300 pins = "gpio56", "gpio57"; 3301 function = "qup15"; 3302 }; 3303 3304 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 3305 pins = "gpio60", "gpio61"; 3306 function = "qup16"; 3307 }; 3308 3309 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 3310 pins = "gpio64", "gpio65"; 3311 function = "qup17"; 3312 }; 3313 3314 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 3315 pins = "gpio68", "gpio69"; 3316 function = "qup18"; 3317 }; 3318 3319 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 3320 pins = "gpio72", "gpio73"; 3321 function = "qup19"; 3322 }; 3323 3324 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 3325 pins = "gpio76", "gpio77"; 3326 function = "qup20"; 3327 }; 3328 3329 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 3330 pins = "gpio80", "gpio81"; 3331 function = "qup21"; 3332 }; 3333 3334 qup_spi0_cs: qup-spi0-cs-state { 3335 pins = "gpio3"; 3336 function = "qup0"; 3337 }; 3338 3339 qup_spi0_data_clk: qup-spi0-data-clk-state { 3340 pins = "gpio0", "gpio1", "gpio2"; 3341 function = "qup0"; 3342 }; 3343 3344 qup_spi1_cs: qup-spi1-cs-state { 3345 pins = "gpio7"; 3346 function = "qup1"; 3347 }; 3348 3349 qup_spi1_data_clk: qup-spi1-data-clk-state { 3350 pins = "gpio4", "gpio5", "gpio6"; 3351 function = "qup1"; 3352 }; 3353 3354 qup_spi2_cs: qup-spi2-cs-state { 3355 pins = "gpio11"; 3356 function = "qup2"; 3357 }; 3358 3359 qup_spi2_data_clk: qup-spi2-data-clk-state { 3360 pins = "gpio8", "gpio9", "gpio10"; 3361 function = "qup2"; 3362 }; 3363 3364 qup_spi3_cs: qup-spi3-cs-state { 3365 pins = "gpio15"; 3366 function = "qup3"; 3367 }; 3368 3369 qup_spi3_data_clk: qup-spi3-data-clk-state { 3370 pins = "gpio12", "gpio13", "gpio14"; 3371 function = "qup3"; 3372 }; 3373 3374 qup_spi4_cs: qup-spi4-cs-state { 3375 pins = "gpio19"; 3376 function = "qup4"; 3377 drive-strength = <6>; 3378 bias-disable; 3379 }; 3380 3381 qup_spi4_data_clk: qup-spi4-data-clk-state { 3382 pins = "gpio16", "gpio17", "gpio18"; 3383 function = "qup4"; 3384 }; 3385 3386 qup_spi5_cs: qup-spi5-cs-state { 3387 pins = "gpio85"; 3388 function = "qup5"; 3389 }; 3390 3391 qup_spi5_data_clk: qup-spi5-data-clk-state { 3392 pins = "gpio206", "gpio207", "gpio84"; 3393 function = "qup5"; 3394 }; 3395 3396 qup_spi6_cs: qup-spi6-cs-state { 3397 pins = "gpio23"; 3398 function = "qup6"; 3399 }; 3400 3401 qup_spi6_data_clk: qup-spi6-data-clk-state { 3402 pins = "gpio20", "gpio21", "gpio22"; 3403 function = "qup6"; 3404 }; 3405 3406 qup_spi8_cs: qup-spi8-cs-state { 3407 pins = "gpio31"; 3408 function = "qup8"; 3409 }; 3410 3411 qup_spi8_data_clk: qup-spi8-data-clk-state { 3412 pins = "gpio28", "gpio29", "gpio30"; 3413 function = "qup8"; 3414 }; 3415 3416 qup_spi9_cs: qup-spi9-cs-state { 3417 pins = "gpio35"; 3418 function = "qup9"; 3419 }; 3420 3421 qup_spi9_data_clk: qup-spi9-data-clk-state { 3422 pins = "gpio32", "gpio33", "gpio34"; 3423 function = "qup9"; 3424 }; 3425 3426 qup_spi10_cs: qup-spi10-cs-state { 3427 pins = "gpio39"; 3428 function = "qup10"; 3429 }; 3430 3431 qup_spi10_data_clk: qup-spi10-data-clk-state { 3432 pins = "gpio36", "gpio37", "gpio38"; 3433 function = "qup10"; 3434 }; 3435 3436 qup_spi11_cs: qup-spi11-cs-state { 3437 pins = "gpio43"; 3438 function = "qup11"; 3439 }; 3440 3441 qup_spi11_data_clk: qup-spi11-data-clk-state { 3442 pins = "gpio40", "gpio41", "gpio42"; 3443 function = "qup11"; 3444 }; 3445 3446 qup_spi12_cs: qup-spi12-cs-state { 3447 pins = "gpio47"; 3448 function = "qup12"; 3449 }; 3450 3451 qup_spi12_data_clk: qup-spi12-data-clk-state { 3452 pins = "gpio44", "gpio45", "gpio46"; 3453 function = "qup12"; 3454 }; 3455 3456 qup_spi13_cs: qup-spi13-cs-state { 3457 pins = "gpio51"; 3458 function = "qup13"; 3459 }; 3460 3461 qup_spi13_data_clk: qup-spi13-data-clk-state { 3462 pins = "gpio48", "gpio49", "gpio50"; 3463 function = "qup13"; 3464 }; 3465 3466 qup_spi14_cs: qup-spi14-cs-state { 3467 pins = "gpio55"; 3468 function = "qup14"; 3469 }; 3470 3471 qup_spi14_data_clk: qup-spi14-data-clk-state { 3472 pins = "gpio52", "gpio53", "gpio54"; 3473 function = "qup14"; 3474 }; 3475 3476 qup_spi15_cs: qup-spi15-cs-state { 3477 pins = "gpio59"; 3478 function = "qup15"; 3479 }; 3480 3481 qup_spi15_data_clk: qup-spi15-data-clk-state { 3482 pins = "gpio56", "gpio57", "gpio58"; 3483 function = "qup15"; 3484 }; 3485 3486 qup_spi16_cs: qup-spi16-cs-state { 3487 pins = "gpio63"; 3488 function = "qup16"; 3489 }; 3490 3491 qup_spi16_data_clk: qup-spi16-data-clk-state { 3492 pins = "gpio60", "gpio61", "gpio62"; 3493 function = "qup16"; 3494 }; 3495 3496 qup_spi17_cs: qup-spi17-cs-state { 3497 pins = "gpio67"; 3498 function = "qup17"; 3499 }; 3500 3501 qup_spi17_data_clk: qup-spi17-data-clk-state { 3502 pins = "gpio64", "gpio65", "gpio66"; 3503 function = "qup17"; 3504 }; 3505 3506 qup_spi18_cs: qup-spi18-cs-state { 3507 pins = "gpio71"; 3508 function = "qup18"; 3509 drive-strength = <6>; 3510 bias-disable; 3511 }; 3512 3513 qup_spi18_data_clk: qup-spi18-data-clk-state { 3514 pins = "gpio68", "gpio69", "gpio70"; 3515 function = "qup18"; 3516 drive-strength = <6>; 3517 bias-disable; 3518 }; 3519 3520 qup_spi19_cs: qup-spi19-cs-state { 3521 pins = "gpio75"; 3522 function = "qup19"; 3523 drive-strength = <6>; 3524 bias-disable; 3525 }; 3526 3527 qup_spi19_data_clk: qup-spi19-data-clk-state { 3528 pins = "gpio72", "gpio73", "gpio74"; 3529 function = "qup19"; 3530 drive-strength = <6>; 3531 bias-disable; 3532 }; 3533 3534 qup_spi20_cs: qup-spi20-cs-state { 3535 pins = "gpio79"; 3536 function = "qup20"; 3537 }; 3538 3539 qup_spi20_data_clk: qup-spi20-data-clk-state { 3540 pins = "gpio76", "gpio77", "gpio78"; 3541 function = "qup20"; 3542 }; 3543 3544 qup_spi21_cs: qup-spi21-cs-state { 3545 pins = "gpio83"; 3546 function = "qup21"; 3547 }; 3548 3549 qup_spi21_data_clk: qup-spi21-data-clk-state { 3550 pins = "gpio80", "gpio81", "gpio82"; 3551 function = "qup21"; 3552 }; 3553 3554 qup_uart7_rx: qup-uart7-rx-state { 3555 pins = "gpio26"; 3556 function = "qup7"; 3557 drive-strength = <2>; 3558 bias-disable; 3559 }; 3560 3561 qup_uart7_tx: qup-uart7-tx-state { 3562 pins = "gpio27"; 3563 function = "qup7"; 3564 drive-strength = <2>; 3565 bias-disable; 3566 }; 3567 3568 qup_uart20_default: qup-uart20-default-state { 3569 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 3570 function = "qup20"; 3571 }; 3572 3573 }; 3574 3575 lpass_tlmm: pinctrl@3440000 { 3576 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 3577 reg = <0 0x03440000 0x0 0x20000>, 3578 <0 0x034d0000 0x0 0x10000>; 3579 gpio-controller; 3580 #gpio-cells = <2>; 3581 gpio-ranges = <&lpass_tlmm 0 0 23>; 3582 3583 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3584 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3585 clock-names = "core", "audio"; 3586 3587 tx_swr_active: tx-swr-active-state { 3588 clk-pins { 3589 pins = "gpio0"; 3590 function = "swr_tx_clk"; 3591 drive-strength = <2>; 3592 slew-rate = <1>; 3593 bias-disable; 3594 }; 3595 3596 data-pins { 3597 pins = "gpio1", "gpio2", "gpio14"; 3598 function = "swr_tx_data"; 3599 drive-strength = <2>; 3600 slew-rate = <1>; 3601 bias-bus-hold; 3602 }; 3603 }; 3604 3605 rx_swr_active: rx-swr-active-state { 3606 clk-pins { 3607 pins = "gpio3"; 3608 function = "swr_rx_clk"; 3609 drive-strength = <2>; 3610 slew-rate = <1>; 3611 bias-disable; 3612 }; 3613 3614 data-pins { 3615 pins = "gpio4", "gpio5"; 3616 function = "swr_rx_data"; 3617 drive-strength = <2>; 3618 slew-rate = <1>; 3619 bias-bus-hold; 3620 }; 3621 }; 3622 3623 dmic01_default: dmic01-default-state { 3624 clk-pins { 3625 pins = "gpio6"; 3626 function = "dmic1_clk"; 3627 drive-strength = <8>; 3628 output-high; 3629 }; 3630 3631 data-pins { 3632 pins = "gpio7"; 3633 function = "dmic1_data"; 3634 drive-strength = <8>; 3635 input-enable; 3636 }; 3637 }; 3638 3639 dmic02_default: dmic02-default-state { 3640 clk-pins { 3641 pins = "gpio8"; 3642 function = "dmic2_clk"; 3643 drive-strength = <8>; 3644 output-high; 3645 }; 3646 3647 data-pins { 3648 pins = "gpio9"; 3649 function = "dmic2_data"; 3650 drive-strength = <8>; 3651 input-enable; 3652 }; 3653 }; 3654 3655 wsa_swr_active: wsa-swr-active-state { 3656 clk-pins { 3657 pins = "gpio10"; 3658 function = "wsa_swr_clk"; 3659 drive-strength = <2>; 3660 slew-rate = <1>; 3661 bias-disable; 3662 }; 3663 3664 data-pins { 3665 pins = "gpio11"; 3666 function = "wsa_swr_data"; 3667 drive-strength = <2>; 3668 slew-rate = <1>; 3669 bias-bus-hold; 3670 }; 3671 }; 3672 3673 wsa2_swr_active: wsa2-swr-active-state { 3674 clk-pins { 3675 pins = "gpio15"; 3676 function = "wsa2_swr_clk"; 3677 drive-strength = <2>; 3678 slew-rate = <1>; 3679 bias-disable; 3680 }; 3681 3682 data-pins { 3683 pins = "gpio16"; 3684 function = "wsa2_swr_data"; 3685 drive-strength = <2>; 3686 slew-rate = <1>; 3687 bias-bus-hold; 3688 }; 3689 }; 3690 }; 3691 3692 apps_smmu: iommu@15000000 { 3693 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 3694 reg = <0 0x15000000 0 0x100000>; 3695 #iommu-cells = <2>; 3696 #global-interrupts = <1>; 3697 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3698 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3699 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3700 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3701 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3702 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3703 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3704 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3705 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3706 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3707 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3708 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3709 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3710 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3711 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3712 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3713 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3714 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3715 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3716 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3717 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3718 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3719 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3721 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3722 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3724 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3727 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3728 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3730 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3731 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3732 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3733 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3734 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3736 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3740 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3741 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3742 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3743 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3744 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3745 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3746 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3747 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3748 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3749 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3750 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3751 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3752 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3753 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3754 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3755 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 3794 }; 3795 3796 intc: interrupt-controller@17100000 { 3797 compatible = "arm,gic-v3"; 3798 #interrupt-cells = <3>; 3799 interrupt-controller; 3800 #redistributor-regions = <1>; 3801 redistributor-stride = <0x0 0x40000>; 3802 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 3803 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 3804 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3805 #address-cells = <2>; 3806 #size-cells = <2>; 3807 ranges; 3808 3809 gic_its: msi-controller@17140000 { 3810 compatible = "arm,gic-v3-its"; 3811 reg = <0x0 0x17140000 0x0 0x20000>; 3812 msi-controller; 3813 #msi-cells = <1>; 3814 }; 3815 }; 3816 3817 timer@17420000 { 3818 compatible = "arm,armv7-timer-mem"; 3819 #address-cells = <1>; 3820 #size-cells = <1>; 3821 ranges = <0 0 0 0x20000000>; 3822 reg = <0x0 0x17420000 0x0 0x1000>; 3823 clock-frequency = <19200000>; 3824 3825 frame@17421000 { 3826 frame-number = <0>; 3827 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3828 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3829 reg = <0x17421000 0x1000>, 3830 <0x17422000 0x1000>; 3831 }; 3832 3833 frame@17423000 { 3834 frame-number = <1>; 3835 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3836 reg = <0x17423000 0x1000>; 3837 status = "disabled"; 3838 }; 3839 3840 frame@17425000 { 3841 frame-number = <2>; 3842 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3843 reg = <0x17425000 0x1000>; 3844 status = "disabled"; 3845 }; 3846 3847 frame@17427000 { 3848 frame-number = <3>; 3849 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3850 reg = <0x17427000 0x1000>; 3851 status = "disabled"; 3852 }; 3853 3854 frame@17429000 { 3855 frame-number = <4>; 3856 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3857 reg = <0x17429000 0x1000>; 3858 status = "disabled"; 3859 }; 3860 3861 frame@1742b000 { 3862 frame-number = <5>; 3863 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3864 reg = <0x1742b000 0x1000>; 3865 status = "disabled"; 3866 }; 3867 3868 frame@1742d000 { 3869 frame-number = <6>; 3870 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3871 reg = <0x1742d000 0x1000>; 3872 status = "disabled"; 3873 }; 3874 }; 3875 3876 apps_rsc: rsc@17a00000 { 3877 label = "apps_rsc"; 3878 compatible = "qcom,rpmh-rsc"; 3879 reg = <0x0 0x17a00000 0x0 0x10000>, 3880 <0x0 0x17a10000 0x0 0x10000>, 3881 <0x0 0x17a20000 0x0 0x10000>, 3882 <0x0 0x17a30000 0x0 0x10000>; 3883 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3884 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3885 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3886 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3887 qcom,tcs-offset = <0xd00>; 3888 qcom,drv-id = <2>; 3889 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3890 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3891 power-domains = <&CLUSTER_PD>; 3892 3893 apps_bcm_voter: bcm-voter { 3894 compatible = "qcom,bcm-voter"; 3895 }; 3896 3897 rpmhcc: clock-controller { 3898 compatible = "qcom,sm8450-rpmh-clk"; 3899 #clock-cells = <1>; 3900 clock-names = "xo"; 3901 clocks = <&xo_board>; 3902 }; 3903 3904 rpmhpd: power-controller { 3905 compatible = "qcom,sm8450-rpmhpd"; 3906 #power-domain-cells = <1>; 3907 operating-points-v2 = <&rpmhpd_opp_table>; 3908 3909 rpmhpd_opp_table: opp-table { 3910 compatible = "operating-points-v2"; 3911 3912 rpmhpd_opp_ret: opp1 { 3913 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3914 }; 3915 3916 rpmhpd_opp_min_svs: opp2 { 3917 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3918 }; 3919 3920 rpmhpd_opp_low_svs_d1: opp3 { 3921 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3922 }; 3923 3924 rpmhpd_opp_low_svs: opp4 { 3925 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3926 }; 3927 3928 rpmhpd_opp_svs: opp5 { 3929 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3930 }; 3931 3932 rpmhpd_opp_svs_l1: opp6 { 3933 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3934 }; 3935 3936 rpmhpd_opp_nom: opp7 { 3937 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3938 }; 3939 3940 rpmhpd_opp_nom_l1: opp8 { 3941 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3942 }; 3943 3944 rpmhpd_opp_nom_l2: opp9 { 3945 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3946 }; 3947 3948 rpmhpd_opp_turbo: opp10 { 3949 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3950 }; 3951 3952 rpmhpd_opp_turbo_l1: opp11 { 3953 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3954 }; 3955 }; 3956 }; 3957 }; 3958 3959 cpufreq_hw: cpufreq@17d91000 { 3960 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 3961 reg = <0 0x17d91000 0 0x1000>, 3962 <0 0x17d92000 0 0x1000>, 3963 <0 0x17d93000 0 0x1000>; 3964 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3965 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3966 clock-names = "xo", "alternate"; 3967 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3968 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3969 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3970 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 3971 #freq-domain-cells = <1>; 3972 #clock-cells = <1>; 3973 }; 3974 3975 gem_noc: interconnect@19100000 { 3976 compatible = "qcom,sm8450-gem-noc"; 3977 reg = <0 0x19100000 0 0xbb800>; 3978 #interconnect-cells = <2>; 3979 qcom,bcm-voters = <&apps_bcm_voter>; 3980 }; 3981 3982 system-cache-controller@19200000 { 3983 compatible = "qcom,sm8450-llcc"; 3984 reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; 3985 reg-names = "llcc_base", "llcc_broadcast_base"; 3986 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3987 }; 3988 3989 ufs_mem_hc: ufshc@1d84000 { 3990 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 3991 "jedec,ufs-2.0"; 3992 reg = <0 0x01d84000 0 0x3000>, 3993 <0 0x01d88000 0 0x8000>; 3994 reg-names = "std", "ice"; 3995 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 3996 phys = <&ufs_mem_phy_lanes>; 3997 phy-names = "ufsphy"; 3998 lanes-per-direction = <2>; 3999 #reset-cells = <1>; 4000 resets = <&gcc GCC_UFS_PHY_BCR>; 4001 reset-names = "rst"; 4002 4003 power-domains = <&gcc UFS_PHY_GDSC>; 4004 4005 iommus = <&apps_smmu 0xe0 0x0>; 4006 dma-coherent; 4007 4008 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 4009 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 4010 interconnect-names = "ufs-ddr", "cpu-ufs"; 4011 clock-names = 4012 "core_clk", 4013 "bus_aggr_clk", 4014 "iface_clk", 4015 "core_clk_unipro", 4016 "ref_clk", 4017 "tx_lane0_sync_clk", 4018 "rx_lane0_sync_clk", 4019 "rx_lane1_sync_clk", 4020 "ice_core_clk"; 4021 clocks = 4022 <&gcc GCC_UFS_PHY_AXI_CLK>, 4023 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 4024 <&gcc GCC_UFS_PHY_AHB_CLK>, 4025 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 4026 <&rpmhcc RPMH_CXO_CLK>, 4027 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 4028 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 4029 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 4030 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4031 freq-table-hz = 4032 <75000000 300000000>, 4033 <0 0>, 4034 <0 0>, 4035 <75000000 300000000>, 4036 <75000000 300000000>, 4037 <0 0>, 4038 <0 0>, 4039 <0 0>, 4040 <75000000 300000000>; 4041 status = "disabled"; 4042 }; 4043 4044 ufs_mem_phy: phy@1d87000 { 4045 compatible = "qcom,sm8450-qmp-ufs-phy"; 4046 reg = <0 0x01d87000 0 0x1c4>; 4047 #address-cells = <2>; 4048 #size-cells = <2>; 4049 ranges; 4050 clock-names = "ref", "ref_aux", "qref"; 4051 clocks = <&rpmhcc RPMH_CXO_CLK>, 4052 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 4053 <&gcc GCC_UFS_0_CLKREF_EN>; 4054 4055 resets = <&ufs_mem_hc 0>; 4056 reset-names = "ufsphy"; 4057 status = "disabled"; 4058 4059 ufs_mem_phy_lanes: phy@1d87400 { 4060 reg = <0 0x01d87400 0 0x188>, 4061 <0 0x01d87600 0 0x200>, 4062 <0 0x01d87c00 0 0x200>, 4063 <0 0x01d87800 0 0x188>, 4064 <0 0x01d87a00 0 0x200>; 4065 #clock-cells = <1>; 4066 #phy-cells = <0>; 4067 }; 4068 }; 4069 4070 sdhc_2: mmc@8804000 { 4071 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 4072 reg = <0 0x08804000 0 0x1000>; 4073 4074 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4076 interrupt-names = "hc_irq", "pwr_irq"; 4077 4078 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4079 <&gcc GCC_SDCC2_APPS_CLK>, 4080 <&rpmhcc RPMH_CXO_CLK>; 4081 clock-names = "iface", "core", "xo"; 4082 resets = <&gcc GCC_SDCC2_BCR>; 4083 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4084 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 4085 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4086 iommus = <&apps_smmu 0x4a0 0x0>; 4087 power-domains = <&rpmhpd SM8450_CX>; 4088 operating-points-v2 = <&sdhc2_opp_table>; 4089 bus-width = <4>; 4090 dma-coherent; 4091 4092 /* Forbid SDR104/SDR50 - broken hw! */ 4093 sdhci-caps-mask = <0x3 0x0>; 4094 4095 status = "disabled"; 4096 4097 sdhc2_opp_table: opp-table { 4098 compatible = "operating-points-v2"; 4099 4100 opp-100000000 { 4101 opp-hz = /bits/ 64 <100000000>; 4102 required-opps = <&rpmhpd_opp_low_svs>; 4103 }; 4104 4105 opp-202000000 { 4106 opp-hz = /bits/ 64 <202000000>; 4107 required-opps = <&rpmhpd_opp_svs_l1>; 4108 }; 4109 }; 4110 }; 4111 4112 usb_1: usb@a6f8800 { 4113 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 4114 reg = <0 0x0a6f8800 0 0x400>; 4115 status = "disabled"; 4116 #address-cells = <2>; 4117 #size-cells = <2>; 4118 ranges; 4119 4120 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4121 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4122 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4123 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4124 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4125 <&gcc GCC_USB3_0_CLKREF_EN>; 4126 clock-names = "cfg_noc", 4127 "core", 4128 "iface", 4129 "sleep", 4130 "mock_utmi", 4131 "xo"; 4132 4133 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4134 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4135 assigned-clock-rates = <19200000>, <200000000>; 4136 4137 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4138 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 4139 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4140 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 4141 interrupt-names = "hs_phy_irq", 4142 "ss_phy_irq", 4143 "dm_hs_phy_irq", 4144 "dp_hs_phy_irq"; 4145 4146 power-domains = <&gcc USB30_PRIM_GDSC>; 4147 4148 resets = <&gcc GCC_USB30_PRIM_BCR>; 4149 4150 usb_1_dwc3: usb@a600000 { 4151 compatible = "snps,dwc3"; 4152 reg = <0 0x0a600000 0 0xcd00>; 4153 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4154 iommus = <&apps_smmu 0x0 0x0>; 4155 snps,dis_u2_susphy_quirk; 4156 snps,dis_enblslpm_quirk; 4157 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 4158 phy-names = "usb2-phy", "usb3-phy"; 4159 }; 4160 }; 4161 4162 nsp_noc: interconnect@320c0000 { 4163 compatible = "qcom,sm8450-nsp-noc"; 4164 reg = <0 0x320c0000 0 0x10000>; 4165 #interconnect-cells = <2>; 4166 qcom,bcm-voters = <&apps_bcm_voter>; 4167 }; 4168 4169 lpass_ag_noc: interconnect@3c40000 { 4170 compatible = "qcom,sm8450-lpass-ag-noc"; 4171 reg = <0 0x03c40000 0 0x17200>; 4172 #interconnect-cells = <2>; 4173 qcom,bcm-voters = <&apps_bcm_voter>; 4174 }; 4175 }; 4176 4177 sound: sound { 4178 }; 4179 4180 thermal-zones { 4181 aoss0-thermal { 4182 polling-delay-passive = <0>; 4183 polling-delay = <0>; 4184 thermal-sensors = <&tsens0 0>; 4185 4186 trips { 4187 thermal-engine-config { 4188 temperature = <125000>; 4189 hysteresis = <1000>; 4190 type = "passive"; 4191 }; 4192 4193 reset-mon-cfg { 4194 temperature = <115000>; 4195 hysteresis = <5000>; 4196 type = "passive"; 4197 }; 4198 }; 4199 }; 4200 4201 cpuss0-thermal { 4202 polling-delay-passive = <0>; 4203 polling-delay = <0>; 4204 thermal-sensors = <&tsens0 1>; 4205 4206 trips { 4207 thermal-engine-config { 4208 temperature = <125000>; 4209 hysteresis = <1000>; 4210 type = "passive"; 4211 }; 4212 4213 reset-mon-cfg { 4214 temperature = <115000>; 4215 hysteresis = <5000>; 4216 type = "passive"; 4217 }; 4218 }; 4219 }; 4220 4221 cpuss1-thermal { 4222 polling-delay-passive = <0>; 4223 polling-delay = <0>; 4224 thermal-sensors = <&tsens0 2>; 4225 4226 trips { 4227 thermal-engine-config { 4228 temperature = <125000>; 4229 hysteresis = <1000>; 4230 type = "passive"; 4231 }; 4232 4233 reset-mon-cfg { 4234 temperature = <115000>; 4235 hysteresis = <5000>; 4236 type = "passive"; 4237 }; 4238 }; 4239 }; 4240 4241 cpuss3-thermal { 4242 polling-delay-passive = <0>; 4243 polling-delay = <0>; 4244 thermal-sensors = <&tsens0 3>; 4245 4246 trips { 4247 thermal-engine-config { 4248 temperature = <125000>; 4249 hysteresis = <1000>; 4250 type = "passive"; 4251 }; 4252 4253 reset-mon-cfg { 4254 temperature = <115000>; 4255 hysteresis = <5000>; 4256 type = "passive"; 4257 }; 4258 }; 4259 }; 4260 4261 cpuss4-thermal { 4262 polling-delay-passive = <0>; 4263 polling-delay = <0>; 4264 thermal-sensors = <&tsens0 4>; 4265 4266 trips { 4267 thermal-engine-config { 4268 temperature = <125000>; 4269 hysteresis = <1000>; 4270 type = "passive"; 4271 }; 4272 4273 reset-mon-cfg { 4274 temperature = <115000>; 4275 hysteresis = <5000>; 4276 type = "passive"; 4277 }; 4278 }; 4279 }; 4280 4281 cpu4-top-thermal { 4282 polling-delay-passive = <0>; 4283 polling-delay = <0>; 4284 thermal-sensors = <&tsens0 5>; 4285 4286 trips { 4287 cpu4_top_alert0: trip-point0 { 4288 temperature = <90000>; 4289 hysteresis = <2000>; 4290 type = "passive"; 4291 }; 4292 4293 cpu4_top_alert1: trip-point1 { 4294 temperature = <95000>; 4295 hysteresis = <2000>; 4296 type = "passive"; 4297 }; 4298 4299 cpu4_top_crit: cpu-crit { 4300 temperature = <110000>; 4301 hysteresis = <1000>; 4302 type = "critical"; 4303 }; 4304 }; 4305 }; 4306 4307 cpu4-bottom-thermal { 4308 polling-delay-passive = <0>; 4309 polling-delay = <0>; 4310 thermal-sensors = <&tsens0 6>; 4311 4312 trips { 4313 cpu4_bottom_alert0: trip-point0 { 4314 temperature = <90000>; 4315 hysteresis = <2000>; 4316 type = "passive"; 4317 }; 4318 4319 cpu4_bottom_alert1: trip-point1 { 4320 temperature = <95000>; 4321 hysteresis = <2000>; 4322 type = "passive"; 4323 }; 4324 4325 cpu4_bottom_crit: cpu-crit { 4326 temperature = <110000>; 4327 hysteresis = <1000>; 4328 type = "critical"; 4329 }; 4330 }; 4331 }; 4332 4333 cpu5-top-thermal { 4334 polling-delay-passive = <0>; 4335 polling-delay = <0>; 4336 thermal-sensors = <&tsens0 7>; 4337 4338 trips { 4339 cpu5_top_alert0: trip-point0 { 4340 temperature = <90000>; 4341 hysteresis = <2000>; 4342 type = "passive"; 4343 }; 4344 4345 cpu5_top_alert1: trip-point1 { 4346 temperature = <95000>; 4347 hysteresis = <2000>; 4348 type = "passive"; 4349 }; 4350 4351 cpu5_top_crit: cpu-crit { 4352 temperature = <110000>; 4353 hysteresis = <1000>; 4354 type = "critical"; 4355 }; 4356 }; 4357 }; 4358 4359 cpu5-bottom-thermal { 4360 polling-delay-passive = <0>; 4361 polling-delay = <0>; 4362 thermal-sensors = <&tsens0 8>; 4363 4364 trips { 4365 cpu5_bottom_alert0: trip-point0 { 4366 temperature = <90000>; 4367 hysteresis = <2000>; 4368 type = "passive"; 4369 }; 4370 4371 cpu5_bottom_alert1: trip-point1 { 4372 temperature = <95000>; 4373 hysteresis = <2000>; 4374 type = "passive"; 4375 }; 4376 4377 cpu5_bottom_crit: cpu-crit { 4378 temperature = <110000>; 4379 hysteresis = <1000>; 4380 type = "critical"; 4381 }; 4382 }; 4383 }; 4384 4385 cpu6-top-thermal { 4386 polling-delay-passive = <0>; 4387 polling-delay = <0>; 4388 thermal-sensors = <&tsens0 9>; 4389 4390 trips { 4391 cpu6_top_alert0: trip-point0 { 4392 temperature = <90000>; 4393 hysteresis = <2000>; 4394 type = "passive"; 4395 }; 4396 4397 cpu6_top_alert1: trip-point1 { 4398 temperature = <95000>; 4399 hysteresis = <2000>; 4400 type = "passive"; 4401 }; 4402 4403 cpu6_top_crit: cpu-crit { 4404 temperature = <110000>; 4405 hysteresis = <1000>; 4406 type = "critical"; 4407 }; 4408 }; 4409 }; 4410 4411 cpu6-bottom-thermal { 4412 polling-delay-passive = <0>; 4413 polling-delay = <0>; 4414 thermal-sensors = <&tsens0 10>; 4415 4416 trips { 4417 cpu6_bottom_alert0: trip-point0 { 4418 temperature = <90000>; 4419 hysteresis = <2000>; 4420 type = "passive"; 4421 }; 4422 4423 cpu6_bottom_alert1: trip-point1 { 4424 temperature = <95000>; 4425 hysteresis = <2000>; 4426 type = "passive"; 4427 }; 4428 4429 cpu6_bottom_crit: cpu-crit { 4430 temperature = <110000>; 4431 hysteresis = <1000>; 4432 type = "critical"; 4433 }; 4434 }; 4435 }; 4436 4437 cpu7-top-thermal { 4438 polling-delay-passive = <0>; 4439 polling-delay = <0>; 4440 thermal-sensors = <&tsens0 11>; 4441 4442 trips { 4443 cpu7_top_alert0: trip-point0 { 4444 temperature = <90000>; 4445 hysteresis = <2000>; 4446 type = "passive"; 4447 }; 4448 4449 cpu7_top_alert1: trip-point1 { 4450 temperature = <95000>; 4451 hysteresis = <2000>; 4452 type = "passive"; 4453 }; 4454 4455 cpu7_top_crit: cpu-crit { 4456 temperature = <110000>; 4457 hysteresis = <1000>; 4458 type = "critical"; 4459 }; 4460 }; 4461 }; 4462 4463 cpu7-middle-thermal { 4464 polling-delay-passive = <0>; 4465 polling-delay = <0>; 4466 thermal-sensors = <&tsens0 12>; 4467 4468 trips { 4469 cpu7_middle_alert0: trip-point0 { 4470 temperature = <90000>; 4471 hysteresis = <2000>; 4472 type = "passive"; 4473 }; 4474 4475 cpu7_middle_alert1: trip-point1 { 4476 temperature = <95000>; 4477 hysteresis = <2000>; 4478 type = "passive"; 4479 }; 4480 4481 cpu7_middle_crit: cpu-crit { 4482 temperature = <110000>; 4483 hysteresis = <1000>; 4484 type = "critical"; 4485 }; 4486 }; 4487 }; 4488 4489 cpu7-bottom-thermal { 4490 polling-delay-passive = <0>; 4491 polling-delay = <0>; 4492 thermal-sensors = <&tsens0 13>; 4493 4494 trips { 4495 cpu7_bottom_alert0: trip-point0 { 4496 temperature = <90000>; 4497 hysteresis = <2000>; 4498 type = "passive"; 4499 }; 4500 4501 cpu7_bottom_alert1: trip-point1 { 4502 temperature = <95000>; 4503 hysteresis = <2000>; 4504 type = "passive"; 4505 }; 4506 4507 cpu7_bottom_crit: cpu-crit { 4508 temperature = <110000>; 4509 hysteresis = <1000>; 4510 type = "critical"; 4511 }; 4512 }; 4513 }; 4514 4515 gpu-top-thermal { 4516 polling-delay-passive = <10>; 4517 polling-delay = <0>; 4518 thermal-sensors = <&tsens0 14>; 4519 4520 trips { 4521 thermal-engine-config { 4522 temperature = <125000>; 4523 hysteresis = <1000>; 4524 type = "passive"; 4525 }; 4526 4527 thermal-hal-config { 4528 temperature = <125000>; 4529 hysteresis = <1000>; 4530 type = "passive"; 4531 }; 4532 4533 reset-mon-cfg { 4534 temperature = <115000>; 4535 hysteresis = <5000>; 4536 type = "passive"; 4537 }; 4538 4539 gpu0_tj_cfg: tj-cfg { 4540 temperature = <95000>; 4541 hysteresis = <5000>; 4542 type = "passive"; 4543 }; 4544 }; 4545 }; 4546 4547 gpu-bottom-thermal { 4548 polling-delay-passive = <10>; 4549 polling-delay = <0>; 4550 thermal-sensors = <&tsens0 15>; 4551 4552 trips { 4553 thermal-engine-config { 4554 temperature = <125000>; 4555 hysteresis = <1000>; 4556 type = "passive"; 4557 }; 4558 4559 thermal-hal-config { 4560 temperature = <125000>; 4561 hysteresis = <1000>; 4562 type = "passive"; 4563 }; 4564 4565 reset-mon-cfg { 4566 temperature = <115000>; 4567 hysteresis = <5000>; 4568 type = "passive"; 4569 }; 4570 4571 gpu1_tj_cfg: tj-cfg { 4572 temperature = <95000>; 4573 hysteresis = <5000>; 4574 type = "passive"; 4575 }; 4576 }; 4577 }; 4578 4579 aoss1-thermal { 4580 polling-delay-passive = <0>; 4581 polling-delay = <0>; 4582 thermal-sensors = <&tsens1 0>; 4583 4584 trips { 4585 thermal-engine-config { 4586 temperature = <125000>; 4587 hysteresis = <1000>; 4588 type = "passive"; 4589 }; 4590 4591 reset-mon-cfg { 4592 temperature = <115000>; 4593 hysteresis = <5000>; 4594 type = "passive"; 4595 }; 4596 }; 4597 }; 4598 4599 cpu0-thermal { 4600 polling-delay-passive = <0>; 4601 polling-delay = <0>; 4602 thermal-sensors = <&tsens1 1>; 4603 4604 trips { 4605 cpu0_alert0: trip-point0 { 4606 temperature = <90000>; 4607 hysteresis = <2000>; 4608 type = "passive"; 4609 }; 4610 4611 cpu0_alert1: trip-point1 { 4612 temperature = <95000>; 4613 hysteresis = <2000>; 4614 type = "passive"; 4615 }; 4616 4617 cpu0_crit: cpu-crit { 4618 temperature = <110000>; 4619 hysteresis = <1000>; 4620 type = "critical"; 4621 }; 4622 }; 4623 }; 4624 4625 cpu1-thermal { 4626 polling-delay-passive = <0>; 4627 polling-delay = <0>; 4628 thermal-sensors = <&tsens1 2>; 4629 4630 trips { 4631 cpu1_alert0: trip-point0 { 4632 temperature = <90000>; 4633 hysteresis = <2000>; 4634 type = "passive"; 4635 }; 4636 4637 cpu1_alert1: trip-point1 { 4638 temperature = <95000>; 4639 hysteresis = <2000>; 4640 type = "passive"; 4641 }; 4642 4643 cpu1_crit: cpu-crit { 4644 temperature = <110000>; 4645 hysteresis = <1000>; 4646 type = "critical"; 4647 }; 4648 }; 4649 }; 4650 4651 cpu2-thermal { 4652 polling-delay-passive = <0>; 4653 polling-delay = <0>; 4654 thermal-sensors = <&tsens1 3>; 4655 4656 trips { 4657 cpu2_alert0: trip-point0 { 4658 temperature = <90000>; 4659 hysteresis = <2000>; 4660 type = "passive"; 4661 }; 4662 4663 cpu2_alert1: trip-point1 { 4664 temperature = <95000>; 4665 hysteresis = <2000>; 4666 type = "passive"; 4667 }; 4668 4669 cpu2_crit: cpu-crit { 4670 temperature = <110000>; 4671 hysteresis = <1000>; 4672 type = "critical"; 4673 }; 4674 }; 4675 }; 4676 4677 cpu3-thermal { 4678 polling-delay-passive = <0>; 4679 polling-delay = <0>; 4680 thermal-sensors = <&tsens1 4>; 4681 4682 trips { 4683 cpu3_alert0: trip-point0 { 4684 temperature = <90000>; 4685 hysteresis = <2000>; 4686 type = "passive"; 4687 }; 4688 4689 cpu3_alert1: trip-point1 { 4690 temperature = <95000>; 4691 hysteresis = <2000>; 4692 type = "passive"; 4693 }; 4694 4695 cpu3_crit: cpu-crit { 4696 temperature = <110000>; 4697 hysteresis = <1000>; 4698 type = "critical"; 4699 }; 4700 }; 4701 }; 4702 4703 cdsp0-thermal { 4704 polling-delay-passive = <10>; 4705 polling-delay = <0>; 4706 thermal-sensors = <&tsens1 5>; 4707 4708 trips { 4709 thermal-engine-config { 4710 temperature = <125000>; 4711 hysteresis = <1000>; 4712 type = "passive"; 4713 }; 4714 4715 thermal-hal-config { 4716 temperature = <125000>; 4717 hysteresis = <1000>; 4718 type = "passive"; 4719 }; 4720 4721 reset-mon-cfg { 4722 temperature = <115000>; 4723 hysteresis = <5000>; 4724 type = "passive"; 4725 }; 4726 4727 cdsp_0_config: junction-config { 4728 temperature = <95000>; 4729 hysteresis = <5000>; 4730 type = "passive"; 4731 }; 4732 }; 4733 }; 4734 4735 cdsp1-thermal { 4736 polling-delay-passive = <10>; 4737 polling-delay = <0>; 4738 thermal-sensors = <&tsens1 6>; 4739 4740 trips { 4741 thermal-engine-config { 4742 temperature = <125000>; 4743 hysteresis = <1000>; 4744 type = "passive"; 4745 }; 4746 4747 thermal-hal-config { 4748 temperature = <125000>; 4749 hysteresis = <1000>; 4750 type = "passive"; 4751 }; 4752 4753 reset-mon-cfg { 4754 temperature = <115000>; 4755 hysteresis = <5000>; 4756 type = "passive"; 4757 }; 4758 4759 cdsp_1_config: junction-config { 4760 temperature = <95000>; 4761 hysteresis = <5000>; 4762 type = "passive"; 4763 }; 4764 }; 4765 }; 4766 4767 cdsp2-thermal { 4768 polling-delay-passive = <10>; 4769 polling-delay = <0>; 4770 thermal-sensors = <&tsens1 7>; 4771 4772 trips { 4773 thermal-engine-config { 4774 temperature = <125000>; 4775 hysteresis = <1000>; 4776 type = "passive"; 4777 }; 4778 4779 thermal-hal-config { 4780 temperature = <125000>; 4781 hysteresis = <1000>; 4782 type = "passive"; 4783 }; 4784 4785 reset-mon-cfg { 4786 temperature = <115000>; 4787 hysteresis = <5000>; 4788 type = "passive"; 4789 }; 4790 4791 cdsp_2_config: junction-config { 4792 temperature = <95000>; 4793 hysteresis = <5000>; 4794 type = "passive"; 4795 }; 4796 }; 4797 }; 4798 4799 video-thermal { 4800 polling-delay-passive = <0>; 4801 polling-delay = <0>; 4802 thermal-sensors = <&tsens1 8>; 4803 4804 trips { 4805 thermal-engine-config { 4806 temperature = <125000>; 4807 hysteresis = <1000>; 4808 type = "passive"; 4809 }; 4810 4811 reset-mon-cfg { 4812 temperature = <115000>; 4813 hysteresis = <5000>; 4814 type = "passive"; 4815 }; 4816 }; 4817 }; 4818 4819 mem-thermal { 4820 polling-delay-passive = <10>; 4821 polling-delay = <0>; 4822 thermal-sensors = <&tsens1 9>; 4823 4824 trips { 4825 thermal-engine-config { 4826 temperature = <125000>; 4827 hysteresis = <1000>; 4828 type = "passive"; 4829 }; 4830 4831 ddr_config0: ddr0-config { 4832 temperature = <90000>; 4833 hysteresis = <5000>; 4834 type = "passive"; 4835 }; 4836 4837 reset-mon-cfg { 4838 temperature = <115000>; 4839 hysteresis = <5000>; 4840 type = "passive"; 4841 }; 4842 }; 4843 }; 4844 4845 modem0-thermal { 4846 polling-delay-passive = <0>; 4847 polling-delay = <0>; 4848 thermal-sensors = <&tsens1 10>; 4849 4850 trips { 4851 thermal-engine-config { 4852 temperature = <125000>; 4853 hysteresis = <1000>; 4854 type = "passive"; 4855 }; 4856 4857 mdmss0_config0: mdmss0-config0 { 4858 temperature = <102000>; 4859 hysteresis = <3000>; 4860 type = "passive"; 4861 }; 4862 4863 mdmss0_config1: mdmss0-config1 { 4864 temperature = <105000>; 4865 hysteresis = <3000>; 4866 type = "passive"; 4867 }; 4868 4869 reset-mon-cfg { 4870 temperature = <115000>; 4871 hysteresis = <5000>; 4872 type = "passive"; 4873 }; 4874 }; 4875 }; 4876 4877 modem1-thermal { 4878 polling-delay-passive = <0>; 4879 polling-delay = <0>; 4880 thermal-sensors = <&tsens1 11>; 4881 4882 trips { 4883 thermal-engine-config { 4884 temperature = <125000>; 4885 hysteresis = <1000>; 4886 type = "passive"; 4887 }; 4888 4889 mdmss1_config0: mdmss1-config0 { 4890 temperature = <102000>; 4891 hysteresis = <3000>; 4892 type = "passive"; 4893 }; 4894 4895 mdmss1_config1: mdmss1-config1 { 4896 temperature = <105000>; 4897 hysteresis = <3000>; 4898 type = "passive"; 4899 }; 4900 4901 reset-mon-cfg { 4902 temperature = <115000>; 4903 hysteresis = <5000>; 4904 type = "passive"; 4905 }; 4906 }; 4907 }; 4908 4909 modem2-thermal { 4910 polling-delay-passive = <0>; 4911 polling-delay = <0>; 4912 thermal-sensors = <&tsens1 12>; 4913 4914 trips { 4915 thermal-engine-config { 4916 temperature = <125000>; 4917 hysteresis = <1000>; 4918 type = "passive"; 4919 }; 4920 4921 mdmss2_config0: mdmss2-config0 { 4922 temperature = <102000>; 4923 hysteresis = <3000>; 4924 type = "passive"; 4925 }; 4926 4927 mdmss2_config1: mdmss2-config1 { 4928 temperature = <105000>; 4929 hysteresis = <3000>; 4930 type = "passive"; 4931 }; 4932 4933 reset-mon-cfg { 4934 temperature = <115000>; 4935 hysteresis = <5000>; 4936 type = "passive"; 4937 }; 4938 }; 4939 }; 4940 4941 modem3-thermal { 4942 polling-delay-passive = <0>; 4943 polling-delay = <0>; 4944 thermal-sensors = <&tsens1 13>; 4945 4946 trips { 4947 thermal-engine-config { 4948 temperature = <125000>; 4949 hysteresis = <1000>; 4950 type = "passive"; 4951 }; 4952 4953 mdmss3_config0: mdmss3-config0 { 4954 temperature = <102000>; 4955 hysteresis = <3000>; 4956 type = "passive"; 4957 }; 4958 4959 mdmss3_config1: mdmss3-config1 { 4960 temperature = <105000>; 4961 hysteresis = <3000>; 4962 type = "passive"; 4963 }; 4964 4965 reset-mon-cfg { 4966 temperature = <115000>; 4967 hysteresis = <5000>; 4968 type = "passive"; 4969 }; 4970 }; 4971 }; 4972 4973 camera0-thermal { 4974 polling-delay-passive = <0>; 4975 polling-delay = <0>; 4976 thermal-sensors = <&tsens1 14>; 4977 4978 trips { 4979 thermal-engine-config { 4980 temperature = <125000>; 4981 hysteresis = <1000>; 4982 type = "passive"; 4983 }; 4984 4985 reset-mon-cfg { 4986 temperature = <115000>; 4987 hysteresis = <5000>; 4988 type = "passive"; 4989 }; 4990 }; 4991 }; 4992 4993 camera1-thermal { 4994 polling-delay-passive = <0>; 4995 polling-delay = <0>; 4996 thermal-sensors = <&tsens1 15>; 4997 4998 trips { 4999 thermal-engine-config { 5000 temperature = <125000>; 5001 hysteresis = <1000>; 5002 type = "passive"; 5003 }; 5004 5005 reset-mon-cfg { 5006 temperature = <115000>; 5007 hysteresis = <5000>; 5008 type = "passive"; 5009 }; 5010 }; 5011 }; 5012 }; 5013 5014 timer { 5015 compatible = "arm,armv8-timer"; 5016 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5017 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5018 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5019 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5020 clock-frequency = <19200000>; 5021 }; 5022}; 5023