1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 11#include <dt-bindings/clock/qcom,sm8450-gpucc.h> 12#include <dt-bindings/clock/qcom,sm8450-videocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/interconnect/qcom,icc.h> 21#include <dt-bindings/interconnect/qcom,sm8450.h> 22#include <dt-bindings/reset/qcom,sm8450-gpucc.h> 23#include <dt-bindings/soc/qcom,gpr.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 clocks { 37 xo_board: xo-board { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <76800000>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <32000>; 47 }; 48 }; 49 50 cpus { 51 #address-cells = <2>; 52 #size-cells = <0>; 53 54 CPU0: cpu@0 { 55 device_type = "cpu"; 56 compatible = "qcom,kryo780"; 57 reg = <0x0 0x0>; 58 enable-method = "psci"; 59 next-level-cache = <&L2_0>; 60 power-domains = <&CPU_PD0>; 61 power-domain-names = "psci"; 62 qcom,freq-domain = <&cpufreq_hw 0>; 63 #cooling-cells = <2>; 64 clocks = <&cpufreq_hw 0>; 65 L2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&L3_0>; 70 L3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 CPU1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo780"; 81 reg = <0x0 0x100>; 82 enable-method = "psci"; 83 next-level-cache = <&L2_100>; 84 power-domains = <&CPU_PD1>; 85 power-domain-names = "psci"; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 #cooling-cells = <2>; 88 clocks = <&cpufreq_hw 0>; 89 L2_100: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 next-level-cache = <&L3_0>; 94 }; 95 }; 96 97 CPU2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo780"; 100 reg = <0x0 0x200>; 101 enable-method = "psci"; 102 next-level-cache = <&L2_200>; 103 power-domains = <&CPU_PD2>; 104 power-domain-names = "psci"; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 #cooling-cells = <2>; 107 clocks = <&cpufreq_hw 0>; 108 L2_200: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&L3_0>; 113 }; 114 }; 115 116 CPU3: cpu@300 { 117 device_type = "cpu"; 118 compatible = "qcom,kryo780"; 119 reg = <0x0 0x300>; 120 enable-method = "psci"; 121 next-level-cache = <&L2_300>; 122 power-domains = <&CPU_PD3>; 123 power-domain-names = "psci"; 124 qcom,freq-domain = <&cpufreq_hw 0>; 125 #cooling-cells = <2>; 126 clocks = <&cpufreq_hw 0>; 127 L2_300: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 next-level-cache = <&L3_0>; 132 }; 133 }; 134 135 CPU4: cpu@400 { 136 device_type = "cpu"; 137 compatible = "qcom,kryo780"; 138 reg = <0x0 0x400>; 139 enable-method = "psci"; 140 next-level-cache = <&L2_400>; 141 power-domains = <&CPU_PD4>; 142 power-domain-names = "psci"; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 #cooling-cells = <2>; 145 clocks = <&cpufreq_hw 1>; 146 L2_400: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU5: cpu@500 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo780"; 157 reg = <0x0 0x500>; 158 enable-method = "psci"; 159 next-level-cache = <&L2_500>; 160 power-domains = <&CPU_PD5>; 161 power-domain-names = "psci"; 162 qcom,freq-domain = <&cpufreq_hw 1>; 163 #cooling-cells = <2>; 164 clocks = <&cpufreq_hw 1>; 165 L2_500: l2-cache { 166 compatible = "cache"; 167 cache-level = <2>; 168 cache-unified; 169 next-level-cache = <&L3_0>; 170 }; 171 }; 172 173 CPU6: cpu@600 { 174 device_type = "cpu"; 175 compatible = "qcom,kryo780"; 176 reg = <0x0 0x600>; 177 enable-method = "psci"; 178 next-level-cache = <&L2_600>; 179 power-domains = <&CPU_PD6>; 180 power-domain-names = "psci"; 181 qcom,freq-domain = <&cpufreq_hw 1>; 182 #cooling-cells = <2>; 183 clocks = <&cpufreq_hw 1>; 184 L2_600: l2-cache { 185 compatible = "cache"; 186 cache-level = <2>; 187 cache-unified; 188 next-level-cache = <&L3_0>; 189 }; 190 }; 191 192 CPU7: cpu@700 { 193 device_type = "cpu"; 194 compatible = "qcom,kryo780"; 195 reg = <0x0 0x700>; 196 enable-method = "psci"; 197 next-level-cache = <&L2_700>; 198 power-domains = <&CPU_PD7>; 199 power-domain-names = "psci"; 200 qcom,freq-domain = <&cpufreq_hw 2>; 201 #cooling-cells = <2>; 202 clocks = <&cpufreq_hw 2>; 203 L2_700: l2-cache { 204 compatible = "cache"; 205 cache-level = <2>; 206 cache-unified; 207 next-level-cache = <&L3_0>; 208 }; 209 }; 210 211 cpu-map { 212 cluster0 { 213 core0 { 214 cpu = <&CPU0>; 215 }; 216 217 core1 { 218 cpu = <&CPU1>; 219 }; 220 221 core2 { 222 cpu = <&CPU2>; 223 }; 224 225 core3 { 226 cpu = <&CPU3>; 227 }; 228 229 core4 { 230 cpu = <&CPU4>; 231 }; 232 233 core5 { 234 cpu = <&CPU5>; 235 }; 236 237 core6 { 238 cpu = <&CPU6>; 239 }; 240 241 core7 { 242 cpu = <&CPU7>; 243 }; 244 }; 245 }; 246 247 idle-states { 248 entry-method = "psci"; 249 250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 251 compatible = "arm,idle-state"; 252 idle-state-name = "silver-rail-power-collapse"; 253 arm,psci-suspend-param = <0x40000004>; 254 entry-latency-us = <800>; 255 exit-latency-us = <750>; 256 min-residency-us = <4090>; 257 local-timer-stop; 258 }; 259 260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 261 compatible = "arm,idle-state"; 262 idle-state-name = "gold-rail-power-collapse"; 263 arm,psci-suspend-param = <0x40000004>; 264 entry-latency-us = <600>; 265 exit-latency-us = <1550>; 266 min-residency-us = <4791>; 267 local-timer-stop; 268 }; 269 }; 270 271 domain-idle-states { 272 CLUSTER_SLEEP_0: cluster-sleep-0 { 273 compatible = "domain-idle-state"; 274 arm,psci-suspend-param = <0x41000044>; 275 entry-latency-us = <1050>; 276 exit-latency-us = <2500>; 277 min-residency-us = <5309>; 278 }; 279 280 CLUSTER_SLEEP_1: cluster-sleep-1 { 281 compatible = "domain-idle-state"; 282 arm,psci-suspend-param = <0x4100c344>; 283 entry-latency-us = <2700>; 284 exit-latency-us = <3500>; 285 min-residency-us = <13959>; 286 }; 287 }; 288 }; 289 290 firmware { 291 scm: scm { 292 compatible = "qcom,scm-sm8450", "qcom,scm"; 293 qcom,dload-mode = <&tcsr 0x13000>; 294 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 295 #reset-cells = <1>; 296 }; 297 }; 298 299 clk_virt: interconnect-0 { 300 compatible = "qcom,sm8450-clk-virt"; 301 #interconnect-cells = <2>; 302 qcom,bcm-voters = <&apps_bcm_voter>; 303 }; 304 305 mc_virt: interconnect-1 { 306 compatible = "qcom,sm8450-mc-virt"; 307 #interconnect-cells = <2>; 308 qcom,bcm-voters = <&apps_bcm_voter>; 309 }; 310 311 memory@a0000000 { 312 device_type = "memory"; 313 /* We expect the bootloader to fill in the size */ 314 reg = <0x0 0xa0000000 0x0 0x0>; 315 }; 316 317 pmu { 318 compatible = "arm,armv8-pmuv3"; 319 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 320 }; 321 322 psci { 323 compatible = "arm,psci-1.0"; 324 method = "smc"; 325 326 CPU_PD0: power-domain-cpu0 { 327 #power-domain-cells = <0>; 328 power-domains = <&CLUSTER_PD>; 329 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 330 }; 331 332 CPU_PD1: power-domain-cpu1 { 333 #power-domain-cells = <0>; 334 power-domains = <&CLUSTER_PD>; 335 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 336 }; 337 338 CPU_PD2: power-domain-cpu2 { 339 #power-domain-cells = <0>; 340 power-domains = <&CLUSTER_PD>; 341 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 342 }; 343 344 CPU_PD3: power-domain-cpu3 { 345 #power-domain-cells = <0>; 346 power-domains = <&CLUSTER_PD>; 347 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 348 }; 349 350 CPU_PD4: power-domain-cpu4 { 351 #power-domain-cells = <0>; 352 power-domains = <&CLUSTER_PD>; 353 domain-idle-states = <&BIG_CPU_SLEEP_0>; 354 }; 355 356 CPU_PD5: power-domain-cpu5 { 357 #power-domain-cells = <0>; 358 power-domains = <&CLUSTER_PD>; 359 domain-idle-states = <&BIG_CPU_SLEEP_0>; 360 }; 361 362 CPU_PD6: power-domain-cpu6 { 363 #power-domain-cells = <0>; 364 power-domains = <&CLUSTER_PD>; 365 domain-idle-states = <&BIG_CPU_SLEEP_0>; 366 }; 367 368 CPU_PD7: power-domain-cpu7 { 369 #power-domain-cells = <0>; 370 power-domains = <&CLUSTER_PD>; 371 domain-idle-states = <&BIG_CPU_SLEEP_0>; 372 }; 373 374 CLUSTER_PD: power-domain-cpu-cluster0 { 375 #power-domain-cells = <0>; 376 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 377 }; 378 }; 379 380 qup_opp_table_100mhz: opp-table-qup { 381 compatible = "operating-points-v2"; 382 383 opp-50000000 { 384 opp-hz = /bits/ 64 <50000000>; 385 required-opps = <&rpmhpd_opp_min_svs>; 386 }; 387 388 opp-75000000 { 389 opp-hz = /bits/ 64 <75000000>; 390 required-opps = <&rpmhpd_opp_low_svs>; 391 }; 392 393 opp-100000000 { 394 opp-hz = /bits/ 64 <100000000>; 395 required-opps = <&rpmhpd_opp_svs>; 396 }; 397 }; 398 399 reserved_memory: reserved-memory { 400 #address-cells = <2>; 401 #size-cells = <2>; 402 ranges; 403 404 hyp_mem: memory@80000000 { 405 reg = <0x0 0x80000000 0x0 0x600000>; 406 no-map; 407 }; 408 409 xbl_dt_log_mem: memory@80600000 { 410 reg = <0x0 0x80600000 0x0 0x40000>; 411 no-map; 412 }; 413 414 xbl_ramdump_mem: memory@80640000 { 415 reg = <0x0 0x80640000 0x0 0x180000>; 416 no-map; 417 }; 418 419 xbl_sc_mem: memory@807c0000 { 420 reg = <0x0 0x807c0000 0x0 0x40000>; 421 no-map; 422 }; 423 424 aop_image_mem: memory@80800000 { 425 reg = <0x0 0x80800000 0x0 0x60000>; 426 no-map; 427 }; 428 429 aop_cmd_db_mem: memory@80860000 { 430 compatible = "qcom,cmd-db"; 431 reg = <0x0 0x80860000 0x0 0x20000>; 432 no-map; 433 }; 434 435 aop_config_mem: memory@80880000 { 436 reg = <0x0 0x80880000 0x0 0x20000>; 437 no-map; 438 }; 439 440 tme_crash_dump_mem: memory@808a0000 { 441 reg = <0x0 0x808a0000 0x0 0x40000>; 442 no-map; 443 }; 444 445 tme_log_mem: memory@808e0000 { 446 reg = <0x0 0x808e0000 0x0 0x4000>; 447 no-map; 448 }; 449 450 uefi_log_mem: memory@808e4000 { 451 reg = <0x0 0x808e4000 0x0 0x10000>; 452 no-map; 453 }; 454 455 /* secdata region can be reused by apps */ 456 smem: memory@80900000 { 457 compatible = "qcom,smem"; 458 reg = <0x0 0x80900000 0x0 0x200000>; 459 hwlocks = <&tcsr_mutex 3>; 460 no-map; 461 }; 462 463 cpucp_fw_mem: memory@80b00000 { 464 reg = <0x0 0x80b00000 0x0 0x100000>; 465 no-map; 466 }; 467 468 cdsp_secure_heap: memory@80c00000 { 469 reg = <0x0 0x80c00000 0x0 0x4600000>; 470 no-map; 471 }; 472 473 video_mem: memory@85700000 { 474 reg = <0x0 0x85700000 0x0 0x700000>; 475 no-map; 476 }; 477 478 adsp_mem: memory@85e00000 { 479 reg = <0x0 0x85e00000 0x0 0x2100000>; 480 no-map; 481 }; 482 483 slpi_mem: memory@88000000 { 484 reg = <0x0 0x88000000 0x0 0x1900000>; 485 no-map; 486 }; 487 488 cdsp_mem: memory@89900000 { 489 reg = <0x0 0x89900000 0x0 0x2000000>; 490 no-map; 491 }; 492 493 ipa_fw_mem: memory@8b900000 { 494 reg = <0x0 0x8b900000 0x0 0x10000>; 495 no-map; 496 }; 497 498 ipa_gsi_mem: memory@8b910000 { 499 reg = <0x0 0x8b910000 0x0 0xa000>; 500 no-map; 501 }; 502 503 gpu_micro_code_mem: memory@8b91a000 { 504 reg = <0x0 0x8b91a000 0x0 0x2000>; 505 no-map; 506 }; 507 508 spss_region_mem: memory@8ba00000 { 509 reg = <0x0 0x8ba00000 0x0 0x180000>; 510 no-map; 511 }; 512 513 /* First part of the "SPU secure shared memory" region */ 514 spu_tz_shared_mem: memory@8bb80000 { 515 reg = <0x0 0x8bb80000 0x0 0x60000>; 516 no-map; 517 }; 518 519 /* Second part of the "SPU secure shared memory" region */ 520 spu_modem_shared_mem: memory@8bbe0000 { 521 reg = <0x0 0x8bbe0000 0x0 0x20000>; 522 no-map; 523 }; 524 525 mpss_mem: memory@8bc00000 { 526 reg = <0x0 0x8bc00000 0x0 0x13200000>; 527 no-map; 528 }; 529 530 cvp_mem: memory@9ee00000 { 531 reg = <0x0 0x9ee00000 0x0 0x700000>; 532 no-map; 533 }; 534 535 camera_mem: memory@9f500000 { 536 reg = <0x0 0x9f500000 0x0 0x800000>; 537 no-map; 538 }; 539 540 rmtfs_mem: memory@9fd00000 { 541 compatible = "qcom,rmtfs-mem"; 542 reg = <0x0 0x9fd00000 0x0 0x280000>; 543 no-map; 544 545 qcom,client-id = <1>; 546 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 547 }; 548 549 xbl_sc_mem2: memory@a6e00000 { 550 reg = <0x0 0xa6e00000 0x0 0x40000>; 551 no-map; 552 }; 553 554 global_sync_mem: memory@a6f00000 { 555 reg = <0x0 0xa6f00000 0x0 0x100000>; 556 no-map; 557 }; 558 559 /* uefi region can be reused by APPS */ 560 561 /* Linux kernel image is loaded at 0xa0000000 */ 562 563 oem_vm_mem: memory@bb000000 { 564 reg = <0x0 0xbb000000 0x0 0x5000000>; 565 no-map; 566 }; 567 568 mte_mem: memory@c0000000 { 569 reg = <0x0 0xc0000000 0x0 0x20000000>; 570 no-map; 571 }; 572 573 qheebsp_reserved_mem: memory@e0000000 { 574 reg = <0x0 0xe0000000 0x0 0x600000>; 575 no-map; 576 }; 577 578 cpusys_vm_mem: memory@e0600000 { 579 reg = <0x0 0xe0600000 0x0 0x400000>; 580 no-map; 581 }; 582 583 hyp_reserved_mem: memory@e0a00000 { 584 reg = <0x0 0xe0a00000 0x0 0x100000>; 585 no-map; 586 }; 587 588 trust_ui_vm_mem: memory@e0b00000 { 589 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 590 no-map; 591 }; 592 593 trust_ui_vm_qrtr: memory@e55f3000 { 594 reg = <0x0 0xe55f3000 0x0 0x9000>; 595 no-map; 596 }; 597 598 trust_ui_vm_vblk0_ring: memory@e55fc000 { 599 reg = <0x0 0xe55fc000 0x0 0x4000>; 600 no-map; 601 }; 602 603 trust_ui_vm_swiotlb: memory@e5600000 { 604 reg = <0x0 0xe5600000 0x0 0x100000>; 605 no-map; 606 }; 607 608 tz_stat_mem: memory@e8800000 { 609 reg = <0x0 0xe8800000 0x0 0x100000>; 610 no-map; 611 }; 612 613 tags_mem: memory@e8900000 { 614 reg = <0x0 0xe8900000 0x0 0x1200000>; 615 no-map; 616 }; 617 618 qtee_mem: memory@e9b00000 { 619 reg = <0x0 0xe9b00000 0x0 0x500000>; 620 no-map; 621 }; 622 623 trusted_apps_mem: memory@ea000000 { 624 reg = <0x0 0xea000000 0x0 0x3900000>; 625 no-map; 626 }; 627 628 trusted_apps_ext_mem: memory@ed900000 { 629 reg = <0x0 0xed900000 0x0 0x3b00000>; 630 no-map; 631 }; 632 }; 633 634 smp2p-adsp { 635 compatible = "qcom,smp2p"; 636 qcom,smem = <443>, <429>; 637 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 638 IPCC_MPROC_SIGNAL_SMP2P 639 IRQ_TYPE_EDGE_RISING>; 640 mboxes = <&ipcc IPCC_CLIENT_LPASS 641 IPCC_MPROC_SIGNAL_SMP2P>; 642 643 qcom,local-pid = <0>; 644 qcom,remote-pid = <2>; 645 646 smp2p_adsp_out: master-kernel { 647 qcom,entry-name = "master-kernel"; 648 #qcom,smem-state-cells = <1>; 649 }; 650 651 smp2p_adsp_in: slave-kernel { 652 qcom,entry-name = "slave-kernel"; 653 interrupt-controller; 654 #interrupt-cells = <2>; 655 }; 656 }; 657 658 smp2p-cdsp { 659 compatible = "qcom,smp2p"; 660 qcom,smem = <94>, <432>; 661 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 662 IPCC_MPROC_SIGNAL_SMP2P 663 IRQ_TYPE_EDGE_RISING>; 664 mboxes = <&ipcc IPCC_CLIENT_CDSP 665 IPCC_MPROC_SIGNAL_SMP2P>; 666 667 qcom,local-pid = <0>; 668 qcom,remote-pid = <5>; 669 670 smp2p_cdsp_out: master-kernel { 671 qcom,entry-name = "master-kernel"; 672 #qcom,smem-state-cells = <1>; 673 }; 674 675 smp2p_cdsp_in: slave-kernel { 676 qcom,entry-name = "slave-kernel"; 677 interrupt-controller; 678 #interrupt-cells = <2>; 679 }; 680 }; 681 682 smp2p-modem { 683 compatible = "qcom,smp2p"; 684 qcom,smem = <435>, <428>; 685 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 686 IPCC_MPROC_SIGNAL_SMP2P 687 IRQ_TYPE_EDGE_RISING>; 688 mboxes = <&ipcc IPCC_CLIENT_MPSS 689 IPCC_MPROC_SIGNAL_SMP2P>; 690 691 qcom,local-pid = <0>; 692 qcom,remote-pid = <1>; 693 694 smp2p_modem_out: master-kernel { 695 qcom,entry-name = "master-kernel"; 696 #qcom,smem-state-cells = <1>; 697 }; 698 699 smp2p_modem_in: slave-kernel { 700 qcom,entry-name = "slave-kernel"; 701 interrupt-controller; 702 #interrupt-cells = <2>; 703 }; 704 705 ipa_smp2p_out: ipa-ap-to-modem { 706 qcom,entry-name = "ipa"; 707 #qcom,smem-state-cells = <1>; 708 }; 709 710 ipa_smp2p_in: ipa-modem-to-ap { 711 qcom,entry-name = "ipa"; 712 interrupt-controller; 713 #interrupt-cells = <2>; 714 }; 715 }; 716 717 smp2p-slpi { 718 compatible = "qcom,smp2p"; 719 qcom,smem = <481>, <430>; 720 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 721 IPCC_MPROC_SIGNAL_SMP2P 722 IRQ_TYPE_EDGE_RISING>; 723 mboxes = <&ipcc IPCC_CLIENT_SLPI 724 IPCC_MPROC_SIGNAL_SMP2P>; 725 726 qcom,local-pid = <0>; 727 qcom,remote-pid = <3>; 728 729 smp2p_slpi_out: master-kernel { 730 qcom,entry-name = "master-kernel"; 731 #qcom,smem-state-cells = <1>; 732 }; 733 734 smp2p_slpi_in: slave-kernel { 735 qcom,entry-name = "slave-kernel"; 736 interrupt-controller; 737 #interrupt-cells = <2>; 738 }; 739 }; 740 741 soc: soc@0 { 742 #address-cells = <2>; 743 #size-cells = <2>; 744 ranges = <0 0 0 0 0x10 0>; 745 dma-ranges = <0 0 0 0 0x10 0>; 746 compatible = "simple-bus"; 747 748 gcc: clock-controller@100000 { 749 compatible = "qcom,gcc-sm8450"; 750 reg = <0x0 0x00100000 0x0 0x1f4200>; 751 #clock-cells = <1>; 752 #reset-cells = <1>; 753 #power-domain-cells = <1>; 754 clocks = <&rpmhcc RPMH_CXO_CLK>, 755 <&sleep_clk>, 756 <&pcie0_phy>, 757 <&pcie1_phy>, 758 <0>, 759 <&ufs_mem_phy 0>, 760 <&ufs_mem_phy 1>, 761 <&ufs_mem_phy 2>, 762 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 763 clock-names = "bi_tcxo", 764 "sleep_clk", 765 "pcie_0_pipe_clk", 766 "pcie_1_pipe_clk", 767 "pcie_1_phy_aux_clk", 768 "ufs_phy_rx_symbol_0_clk", 769 "ufs_phy_rx_symbol_1_clk", 770 "ufs_phy_tx_symbol_0_clk", 771 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 772 }; 773 774 gpi_dma2: dma-controller@800000 { 775 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 776 #dma-cells = <3>; 777 reg = <0 0x00800000 0 0x60000>; 778 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 790 dma-channels = <12>; 791 dma-channel-mask = <0x7e>; 792 iommus = <&apps_smmu 0x496 0x0>; 793 status = "disabled"; 794 }; 795 796 qupv3_id_2: geniqup@8c0000 { 797 compatible = "qcom,geni-se-qup"; 798 reg = <0x0 0x008c0000 0x0 0x2000>; 799 clock-names = "m-ahb", "s-ahb"; 800 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 801 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 802 iommus = <&apps_smmu 0x483 0x0>; 803 #address-cells = <2>; 804 #size-cells = <2>; 805 ranges; 806 status = "disabled"; 807 808 i2c15: i2c@880000 { 809 compatible = "qcom,geni-i2c"; 810 reg = <0x0 0x00880000 0x0 0x4000>; 811 clock-names = "se"; 812 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&qup_i2c15_data_clk>; 815 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 819 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 820 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 821 interconnect-names = "qup-core", "qup-config", "qup-memory"; 822 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 823 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 824 dma-names = "tx", "rx"; 825 status = "disabled"; 826 }; 827 828 spi15: spi@880000 { 829 compatible = "qcom,geni-spi"; 830 reg = <0x0 0x00880000 0x0 0x4000>; 831 clock-names = "se"; 832 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 833 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 836 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 837 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 838 interconnect-names = "qup-core", "qup-config"; 839 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 840 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 841 dma-names = "tx", "rx"; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 status = "disabled"; 845 }; 846 847 i2c16: i2c@884000 { 848 compatible = "qcom,geni-i2c"; 849 reg = <0x0 0x00884000 0x0 0x4000>; 850 clock-names = "se"; 851 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 852 pinctrl-names = "default"; 853 pinctrl-0 = <&qup_i2c16_data_clk>; 854 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 858 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 859 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 860 interconnect-names = "qup-core", "qup-config", "qup-memory"; 861 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 862 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 863 dma-names = "tx", "rx"; 864 status = "disabled"; 865 }; 866 867 spi16: spi@884000 { 868 compatible = "qcom,geni-spi"; 869 reg = <0x0 0x00884000 0x0 0x4000>; 870 clock-names = "se"; 871 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 872 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 875 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 876 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 877 interconnect-names = "qup-core", "qup-config"; 878 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 879 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 880 dma-names = "tx", "rx"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 status = "disabled"; 884 }; 885 886 i2c17: i2c@888000 { 887 compatible = "qcom,geni-i2c"; 888 reg = <0x0 0x00888000 0x0 0x4000>; 889 clock-names = "se"; 890 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 891 pinctrl-names = "default"; 892 pinctrl-0 = <&qup_i2c17_data_clk>; 893 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 897 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 898 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 899 interconnect-names = "qup-core", "qup-config", "qup-memory"; 900 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 901 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 902 dma-names = "tx", "rx"; 903 status = "disabled"; 904 }; 905 906 spi17: spi@888000 { 907 compatible = "qcom,geni-spi"; 908 reg = <0x0 0x00888000 0x0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 911 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 914 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 915 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 916 interconnect-names = "qup-core", "qup-config"; 917 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 918 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 919 dma-names = "tx", "rx"; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 status = "disabled"; 923 }; 924 925 i2c18: i2c@88c000 { 926 compatible = "qcom,geni-i2c"; 927 reg = <0x0 0x0088c000 0x0 0x4000>; 928 clock-names = "se"; 929 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 930 pinctrl-names = "default"; 931 pinctrl-0 = <&qup_i2c18_data_clk>; 932 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 936 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 937 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 938 interconnect-names = "qup-core", "qup-config", "qup-memory"; 939 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 940 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 941 dma-names = "tx", "rx"; 942 status = "disabled"; 943 }; 944 945 spi18: spi@88c000 { 946 compatible = "qcom,geni-spi"; 947 reg = <0 0x0088c000 0 0x4000>; 948 clock-names = "se"; 949 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 950 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 953 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 954 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 955 interconnect-names = "qup-core", "qup-config"; 956 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 957 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 958 dma-names = "tx", "rx"; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 status = "disabled"; 962 }; 963 964 i2c19: i2c@890000 { 965 compatible = "qcom,geni-i2c"; 966 reg = <0x0 0x00890000 0x0 0x4000>; 967 clock-names = "se"; 968 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 969 pinctrl-names = "default"; 970 pinctrl-0 = <&qup_i2c19_data_clk>; 971 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 975 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 976 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 977 interconnect-names = "qup-core", "qup-config", "qup-memory"; 978 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 979 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 980 dma-names = "tx", "rx"; 981 status = "disabled"; 982 }; 983 984 spi19: spi@890000 { 985 compatible = "qcom,geni-spi"; 986 reg = <0 0x00890000 0 0x4000>; 987 clock-names = "se"; 988 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 989 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 990 pinctrl-names = "default"; 991 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 992 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 993 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 994 interconnect-names = "qup-core", "qup-config"; 995 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 996 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 997 dma-names = "tx", "rx"; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 i2c20: i2c@894000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0x0 0x00894000 0x0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&qup_i2c20_data_clk>; 1010 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1014 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1015 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1016 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1017 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1018 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1019 dma-names = "tx", "rx"; 1020 status = "disabled"; 1021 }; 1022 1023 uart20: serial@894000 { 1024 compatible = "qcom,geni-uart"; 1025 reg = <0 0x00894000 0 0x4000>; 1026 clock-names = "se"; 1027 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1028 pinctrl-names = "default"; 1029 pinctrl-0 = <&qup_uart20_default>; 1030 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1031 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1032 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1033 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1034 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1035 interconnect-names = "qup-core", 1036 "qup-config"; 1037 status = "disabled"; 1038 }; 1039 1040 spi20: spi@894000 { 1041 compatible = "qcom,geni-spi"; 1042 reg = <0 0x00894000 0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1045 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1046 pinctrl-names = "default"; 1047 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1048 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1049 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1050 interconnect-names = "qup-core", "qup-config"; 1051 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1052 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1053 dma-names = "tx", "rx"; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 status = "disabled"; 1057 }; 1058 1059 i2c21: i2c@898000 { 1060 compatible = "qcom,geni-i2c"; 1061 reg = <0x0 0x00898000 0x0 0x4000>; 1062 clock-names = "se"; 1063 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1064 pinctrl-names = "default"; 1065 pinctrl-0 = <&qup_i2c21_data_clk>; 1066 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1070 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1071 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1072 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1073 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1074 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1075 dma-names = "tx", "rx"; 1076 status = "disabled"; 1077 }; 1078 1079 spi21: spi@898000 { 1080 compatible = "qcom,geni-spi"; 1081 reg = <0 0x00898000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1084 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1085 pinctrl-names = "default"; 1086 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1087 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1088 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1089 interconnect-names = "qup-core", "qup-config"; 1090 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1091 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1092 dma-names = "tx", "rx"; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 status = "disabled"; 1096 }; 1097 }; 1098 1099 gpi_dma0: dma-controller@900000 { 1100 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1101 #dma-cells = <3>; 1102 reg = <0 0x00900000 0 0x60000>; 1103 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1115 dma-channels = <12>; 1116 dma-channel-mask = <0x7e>; 1117 iommus = <&apps_smmu 0x5b6 0x0>; 1118 status = "disabled"; 1119 }; 1120 1121 qupv3_id_0: geniqup@9c0000 { 1122 compatible = "qcom,geni-se-qup"; 1123 reg = <0x0 0x009c0000 0x0 0x2000>; 1124 clock-names = "m-ahb", "s-ahb"; 1125 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1126 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1127 iommus = <&apps_smmu 0x5a3 0x0>; 1128 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1129 interconnect-names = "qup-core"; 1130 #address-cells = <2>; 1131 #size-cells = <2>; 1132 ranges; 1133 status = "disabled"; 1134 1135 i2c0: i2c@980000 { 1136 compatible = "qcom,geni-i2c"; 1137 reg = <0x0 0x00980000 0x0 0x4000>; 1138 clock-names = "se"; 1139 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1140 pinctrl-names = "default"; 1141 pinctrl-0 = <&qup_i2c0_data_clk>; 1142 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1146 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1147 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1148 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1149 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1150 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1151 dma-names = "tx", "rx"; 1152 status = "disabled"; 1153 }; 1154 1155 spi0: spi@980000 { 1156 compatible = "qcom,geni-spi"; 1157 reg = <0x0 0x00980000 0x0 0x4000>; 1158 clock-names = "se"; 1159 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1160 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1163 power-domains = <&rpmhpd RPMHPD_CX>; 1164 operating-points-v2 = <&qup_opp_table_100mhz>; 1165 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1166 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1167 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1168 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1169 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1170 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1171 dma-names = "tx", "rx"; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 i2c1: i2c@984000 { 1178 compatible = "qcom,geni-i2c"; 1179 reg = <0x0 0x00984000 0x0 0x4000>; 1180 clock-names = "se"; 1181 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1182 pinctrl-names = "default"; 1183 pinctrl-0 = <&qup_i2c1_data_clk>; 1184 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1188 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1189 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1190 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1191 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1192 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1193 dma-names = "tx", "rx"; 1194 status = "disabled"; 1195 }; 1196 1197 spi1: spi@984000 { 1198 compatible = "qcom,geni-spi"; 1199 reg = <0x0 0x00984000 0x0 0x4000>; 1200 clock-names = "se"; 1201 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1202 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1203 pinctrl-names = "default"; 1204 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1205 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1206 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1207 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1208 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1209 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1210 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1211 dma-names = "tx", "rx"; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 status = "disabled"; 1215 }; 1216 1217 i2c2: i2c@988000 { 1218 compatible = "qcom,geni-i2c"; 1219 reg = <0x0 0x00988000 0x0 0x4000>; 1220 clock-names = "se"; 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&qup_i2c2_data_clk>; 1224 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1225 #address-cells = <1>; 1226 #size-cells = <0>; 1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1228 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1229 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1230 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1231 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1232 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1233 dma-names = "tx", "rx"; 1234 status = "disabled"; 1235 }; 1236 1237 spi2: spi@988000 { 1238 compatible = "qcom,geni-spi"; 1239 reg = <0x0 0x00988000 0x0 0x4000>; 1240 clock-names = "se"; 1241 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1242 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1245 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1246 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1247 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1248 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1249 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1250 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1251 dma-names = "tx", "rx"; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 status = "disabled"; 1255 }; 1256 1257 1258 i2c3: i2c@98c000 { 1259 compatible = "qcom,geni-i2c"; 1260 reg = <0x0 0x0098c000 0x0 0x4000>; 1261 clock-names = "se"; 1262 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1263 pinctrl-names = "default"; 1264 pinctrl-0 = <&qup_i2c3_data_clk>; 1265 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1266 #address-cells = <1>; 1267 #size-cells = <0>; 1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1269 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1270 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1271 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1272 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1273 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1274 dma-names = "tx", "rx"; 1275 status = "disabled"; 1276 }; 1277 1278 spi3: spi@98c000 { 1279 compatible = "qcom,geni-spi"; 1280 reg = <0x0 0x0098c000 0x0 0x4000>; 1281 clock-names = "se"; 1282 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1283 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1286 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1287 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1288 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1289 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1290 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1291 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1292 dma-names = "tx", "rx"; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 status = "disabled"; 1296 }; 1297 1298 i2c4: i2c@990000 { 1299 compatible = "qcom,geni-i2c"; 1300 reg = <0x0 0x00990000 0x0 0x4000>; 1301 clock-names = "se"; 1302 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&qup_i2c4_data_clk>; 1305 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1309 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1310 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1311 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1312 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1313 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1314 dma-names = "tx", "rx"; 1315 status = "disabled"; 1316 }; 1317 1318 spi4: spi@990000 { 1319 compatible = "qcom,geni-spi"; 1320 reg = <0x0 0x00990000 0x0 0x4000>; 1321 clock-names = "se"; 1322 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1323 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1324 pinctrl-names = "default"; 1325 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1326 power-domains = <&rpmhpd RPMHPD_CX>; 1327 operating-points-v2 = <&qup_opp_table_100mhz>; 1328 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1329 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1330 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1331 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1332 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1333 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1334 dma-names = "tx", "rx"; 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 status = "disabled"; 1338 }; 1339 1340 i2c5: i2c@994000 { 1341 compatible = "qcom,geni-i2c"; 1342 reg = <0x0 0x00994000 0x0 0x4000>; 1343 clock-names = "se"; 1344 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1345 pinctrl-names = "default"; 1346 pinctrl-0 = <&qup_i2c5_data_clk>; 1347 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1351 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1352 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1353 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1354 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1355 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1356 dma-names = "tx", "rx"; 1357 status = "disabled"; 1358 }; 1359 1360 spi5: spi@994000 { 1361 compatible = "qcom,geni-spi"; 1362 reg = <0x0 0x00994000 0x0 0x4000>; 1363 clock-names = "se"; 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1365 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1366 pinctrl-names = "default"; 1367 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1368 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1369 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1370 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1371 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1372 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1373 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1374 dma-names = "tx", "rx"; 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 status = "disabled"; 1378 }; 1379 1380 1381 i2c6: i2c@998000 { 1382 compatible = "qcom,geni-i2c"; 1383 reg = <0x0 0x00998000 0x0 0x4000>; 1384 clock-names = "se"; 1385 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1386 pinctrl-names = "default"; 1387 pinctrl-0 = <&qup_i2c6_data_clk>; 1388 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1392 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1393 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1394 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1395 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1396 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1397 dma-names = "tx", "rx"; 1398 status = "disabled"; 1399 }; 1400 1401 spi6: spi@998000 { 1402 compatible = "qcom,geni-spi"; 1403 reg = <0x0 0x00998000 0x0 0x4000>; 1404 clock-names = "se"; 1405 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1406 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1407 pinctrl-names = "default"; 1408 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1409 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1410 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1411 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1412 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1413 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1414 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1415 dma-names = "tx", "rx"; 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 status = "disabled"; 1419 }; 1420 1421 uart7: serial@99c000 { 1422 compatible = "qcom,geni-debug-uart"; 1423 reg = <0 0x0099c000 0 0x4000>; 1424 clock-names = "se"; 1425 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1426 pinctrl-names = "default"; 1427 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1428 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1429 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1430 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1431 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1432 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1433 interconnect-names = "qup-core", 1434 "qup-config"; 1435 status = "disabled"; 1436 }; 1437 }; 1438 1439 gpi_dma1: dma-controller@a00000 { 1440 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1441 #dma-cells = <3>; 1442 reg = <0 0x00a00000 0 0x60000>; 1443 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1455 dma-channels = <12>; 1456 dma-channel-mask = <0x7e>; 1457 iommus = <&apps_smmu 0x56 0x0>; 1458 status = "disabled"; 1459 }; 1460 1461 qupv3_id_1: geniqup@ac0000 { 1462 compatible = "qcom,geni-se-qup"; 1463 reg = <0x0 0x00ac0000 0x0 0x6000>; 1464 clock-names = "m-ahb", "s-ahb"; 1465 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1466 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1467 iommus = <&apps_smmu 0x43 0x0>; 1468 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1469 interconnect-names = "qup-core"; 1470 #address-cells = <2>; 1471 #size-cells = <2>; 1472 ranges; 1473 status = "disabled"; 1474 1475 i2c8: i2c@a80000 { 1476 compatible = "qcom,geni-i2c"; 1477 reg = <0x0 0x00a80000 0x0 0x4000>; 1478 clock-names = "se"; 1479 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_i2c8_data_clk>; 1482 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1486 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1487 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1488 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1489 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1490 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1491 dma-names = "tx", "rx"; 1492 status = "disabled"; 1493 }; 1494 1495 spi8: spi@a80000 { 1496 compatible = "qcom,geni-spi"; 1497 reg = <0x0 0x00a80000 0x0 0x4000>; 1498 clock-names = "se"; 1499 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1500 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1503 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1504 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1505 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1506 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1507 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1508 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1509 dma-names = "tx", "rx"; 1510 #address-cells = <1>; 1511 #size-cells = <0>; 1512 status = "disabled"; 1513 }; 1514 1515 i2c9: i2c@a84000 { 1516 compatible = "qcom,geni-i2c"; 1517 reg = <0x0 0x00a84000 0x0 0x4000>; 1518 clock-names = "se"; 1519 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1520 pinctrl-names = "default"; 1521 pinctrl-0 = <&qup_i2c9_data_clk>; 1522 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1523 #address-cells = <1>; 1524 #size-cells = <0>; 1525 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1526 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1527 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1528 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1529 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1530 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1531 dma-names = "tx", "rx"; 1532 status = "disabled"; 1533 }; 1534 1535 spi9: spi@a84000 { 1536 compatible = "qcom,geni-spi"; 1537 reg = <0x0 0x00a84000 0x0 0x4000>; 1538 clock-names = "se"; 1539 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1540 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1541 pinctrl-names = "default"; 1542 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1544 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1545 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1546 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1547 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1548 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1549 dma-names = "tx", "rx"; 1550 #address-cells = <1>; 1551 #size-cells = <0>; 1552 status = "disabled"; 1553 }; 1554 1555 i2c10: i2c@a88000 { 1556 compatible = "qcom,geni-i2c"; 1557 reg = <0x0 0x00a88000 0x0 0x4000>; 1558 clock-names = "se"; 1559 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1560 pinctrl-names = "default"; 1561 pinctrl-0 = <&qup_i2c10_data_clk>; 1562 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1566 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1567 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1568 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1569 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1570 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1571 dma-names = "tx", "rx"; 1572 status = "disabled"; 1573 }; 1574 1575 spi10: spi@a88000 { 1576 compatible = "qcom,geni-spi"; 1577 reg = <0x0 0x00a88000 0x0 0x4000>; 1578 clock-names = "se"; 1579 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1580 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1581 pinctrl-names = "default"; 1582 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1584 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1585 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1586 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1587 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1588 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1589 dma-names = "tx", "rx"; 1590 #address-cells = <1>; 1591 #size-cells = <0>; 1592 status = "disabled"; 1593 }; 1594 1595 i2c11: i2c@a8c000 { 1596 compatible = "qcom,geni-i2c"; 1597 reg = <0x0 0x00a8c000 0x0 0x4000>; 1598 clock-names = "se"; 1599 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1600 pinctrl-names = "default"; 1601 pinctrl-0 = <&qup_i2c11_data_clk>; 1602 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1606 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1607 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1608 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1609 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1610 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1611 dma-names = "tx", "rx"; 1612 status = "disabled"; 1613 }; 1614 1615 spi11: spi@a8c000 { 1616 compatible = "qcom,geni-spi"; 1617 reg = <0x0 0x00a8c000 0x0 0x4000>; 1618 clock-names = "se"; 1619 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1620 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1621 pinctrl-names = "default"; 1622 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1624 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1625 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1626 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1627 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1628 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1629 dma-names = "tx", "rx"; 1630 #address-cells = <1>; 1631 #size-cells = <0>; 1632 status = "disabled"; 1633 }; 1634 1635 i2c12: i2c@a90000 { 1636 compatible = "qcom,geni-i2c"; 1637 reg = <0x0 0x00a90000 0x0 0x4000>; 1638 clock-names = "se"; 1639 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1640 pinctrl-names = "default"; 1641 pinctrl-0 = <&qup_i2c12_data_clk>; 1642 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1646 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1647 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1648 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1649 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1650 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1651 dma-names = "tx", "rx"; 1652 status = "disabled"; 1653 }; 1654 1655 spi12: spi@a90000 { 1656 compatible = "qcom,geni-spi"; 1657 reg = <0x0 0x00a90000 0x0 0x4000>; 1658 clock-names = "se"; 1659 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1660 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1661 pinctrl-names = "default"; 1662 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1663 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1664 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1665 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1666 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1667 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1668 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1669 dma-names = "tx", "rx"; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 status = "disabled"; 1673 }; 1674 1675 i2c13: i2c@a94000 { 1676 compatible = "qcom,geni-i2c"; 1677 reg = <0 0x00a94000 0 0x4000>; 1678 clock-names = "se"; 1679 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1680 pinctrl-names = "default"; 1681 pinctrl-0 = <&qup_i2c13_data_clk>; 1682 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1684 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1685 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1686 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1687 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1688 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1689 dma-names = "tx", "rx"; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 status = "disabled"; 1693 }; 1694 1695 spi13: spi@a94000 { 1696 compatible = "qcom,geni-spi"; 1697 reg = <0x0 0x00a94000 0x0 0x4000>; 1698 clock-names = "se"; 1699 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1700 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1701 pinctrl-names = "default"; 1702 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1703 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1704 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1705 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1706 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1707 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1708 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1709 dma-names = "tx", "rx"; 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 status = "disabled"; 1713 }; 1714 1715 i2c14: i2c@a98000 { 1716 compatible = "qcom,geni-i2c"; 1717 reg = <0 0x00a98000 0 0x4000>; 1718 clock-names = "se"; 1719 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1720 pinctrl-names = "default"; 1721 pinctrl-0 = <&qup_i2c14_data_clk>; 1722 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1723 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1724 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1725 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1726 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1727 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1728 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1729 dma-names = "tx", "rx"; 1730 #address-cells = <1>; 1731 #size-cells = <0>; 1732 status = "disabled"; 1733 }; 1734 1735 spi14: spi@a98000 { 1736 compatible = "qcom,geni-spi"; 1737 reg = <0x0 0x00a98000 0x0 0x4000>; 1738 clock-names = "se"; 1739 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1740 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1741 pinctrl-names = "default"; 1742 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1743 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1744 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1745 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1746 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1747 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1748 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1749 dma-names = "tx", "rx"; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 status = "disabled"; 1753 }; 1754 }; 1755 1756 rng: rng@10c3000 { 1757 compatible = "qcom,sm8450-trng", "qcom,trng"; 1758 reg = <0 0x010c3000 0 0x1000>; 1759 }; 1760 1761 pcie0: pcie@1c00000 { 1762 compatible = "qcom,pcie-sm8450-pcie0"; 1763 reg = <0 0x01c00000 0 0x3000>, 1764 <0 0x60000000 0 0xf1d>, 1765 <0 0x60000f20 0 0xa8>, 1766 <0 0x60001000 0 0x1000>, 1767 <0 0x60100000 0 0x100000>; 1768 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1769 device_type = "pci"; 1770 linux,pci-domain = <0>; 1771 bus-range = <0x00 0xff>; 1772 num-lanes = <1>; 1773 1774 #address-cells = <3>; 1775 #size-cells = <2>; 1776 1777 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1778 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1779 1780 msi-map = <0x0 &gic_its 0x5980 0x1>, 1781 <0x100 &gic_its 0x5981 0x1>; 1782 msi-map-mask = <0xff00>; 1783 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1791 interrupt-names = "msi0", 1792 "msi1", 1793 "msi2", 1794 "msi3", 1795 "msi4", 1796 "msi5", 1797 "msi6", 1798 "msi7"; 1799 #interrupt-cells = <1>; 1800 interrupt-map-mask = <0 0 0 0x7>; 1801 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1802 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1803 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1804 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1805 1806 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1807 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1808 <&pcie0_phy>, 1809 <&rpmhcc RPMH_CXO_CLK>, 1810 <&gcc GCC_PCIE_0_AUX_CLK>, 1811 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1812 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1813 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1814 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1815 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1816 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1817 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1818 clock-names = "pipe", 1819 "pipe_mux", 1820 "phy_pipe", 1821 "ref", 1822 "aux", 1823 "cfg", 1824 "bus_master", 1825 "bus_slave", 1826 "slave_q2a", 1827 "ddrss_sf_tbu", 1828 "aggre0", 1829 "aggre1"; 1830 1831 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1832 <0x100 &apps_smmu 0x1c01 0x1>; 1833 1834 resets = <&gcc GCC_PCIE_0_BCR>; 1835 reset-names = "pci"; 1836 1837 power-domains = <&gcc PCIE_0_GDSC>; 1838 1839 phys = <&pcie0_phy>; 1840 phy-names = "pciephy"; 1841 1842 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1843 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1844 1845 pinctrl-names = "default"; 1846 pinctrl-0 = <&pcie0_default_state>; 1847 1848 status = "disabled"; 1849 }; 1850 1851 pcie0_phy: phy@1c06000 { 1852 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1853 reg = <0 0x01c06000 0 0x2000>; 1854 1855 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1856 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1857 <&gcc GCC_PCIE_0_CLKREF_EN>, 1858 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1859 <&gcc GCC_PCIE_0_PIPE_CLK>; 1860 clock-names = "aux", 1861 "cfg_ahb", 1862 "ref", 1863 "rchng", 1864 "pipe"; 1865 1866 clock-output-names = "pcie_0_pipe_clk"; 1867 #clock-cells = <0>; 1868 1869 #phy-cells = <0>; 1870 1871 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1872 reset-names = "phy"; 1873 1874 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1875 assigned-clock-rates = <100000000>; 1876 1877 status = "disabled"; 1878 }; 1879 1880 pcie1: pcie@1c08000 { 1881 compatible = "qcom,pcie-sm8450-pcie1"; 1882 reg = <0 0x01c08000 0 0x3000>, 1883 <0 0x40000000 0 0xf1d>, 1884 <0 0x40000f20 0 0xa8>, 1885 <0 0x40001000 0 0x1000>, 1886 <0 0x40100000 0 0x100000>; 1887 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1888 device_type = "pci"; 1889 linux,pci-domain = <1>; 1890 bus-range = <0x00 0xff>; 1891 num-lanes = <2>; 1892 1893 #address-cells = <3>; 1894 #size-cells = <2>; 1895 1896 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1897 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1898 1899 msi-map = <0x0 &gic_its 0x5a00 0x1>, 1900 <0x100 &gic_its 0x5a01 0x1>; 1901 msi-map-mask = <0xff00>; 1902 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1910 interrupt-names = "msi0", 1911 "msi1", 1912 "msi2", 1913 "msi3", 1914 "msi4", 1915 "msi5", 1916 "msi6", 1917 "msi7"; 1918 #interrupt-cells = <1>; 1919 interrupt-map-mask = <0 0 0 0x7>; 1920 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1921 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1922 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1923 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1924 1925 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1926 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1927 <&pcie1_phy>, 1928 <&rpmhcc RPMH_CXO_CLK>, 1929 <&gcc GCC_PCIE_1_AUX_CLK>, 1930 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1931 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1932 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1933 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1934 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1935 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1936 clock-names = "pipe", 1937 "pipe_mux", 1938 "phy_pipe", 1939 "ref", 1940 "aux", 1941 "cfg", 1942 "bus_master", 1943 "bus_slave", 1944 "slave_q2a", 1945 "ddrss_sf_tbu", 1946 "aggre1"; 1947 1948 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1949 <0x100 &apps_smmu 0x1c81 0x1>; 1950 1951 resets = <&gcc GCC_PCIE_1_BCR>; 1952 reset-names = "pci"; 1953 1954 power-domains = <&gcc PCIE_1_GDSC>; 1955 1956 phys = <&pcie1_phy>; 1957 phy-names = "pciephy"; 1958 1959 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 1960 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1961 1962 pinctrl-names = "default"; 1963 pinctrl-0 = <&pcie1_default_state>; 1964 1965 status = "disabled"; 1966 }; 1967 1968 pcie1_phy: phy@1c0e000 { 1969 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 1970 reg = <0 0x01c0e000 0 0x2000>; 1971 1972 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1973 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1974 <&gcc GCC_PCIE_1_CLKREF_EN>, 1975 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1976 <&gcc GCC_PCIE_1_PIPE_CLK>; 1977 clock-names = "aux", 1978 "cfg_ahb", 1979 "ref", 1980 "rchng", 1981 "pipe"; 1982 1983 clock-output-names = "pcie_1_pipe_clk"; 1984 #clock-cells = <0>; 1985 1986 #phy-cells = <0>; 1987 1988 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1989 reset-names = "phy"; 1990 1991 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1992 assigned-clock-rates = <100000000>; 1993 1994 status = "disabled"; 1995 }; 1996 1997 config_noc: interconnect@1500000 { 1998 compatible = "qcom,sm8450-config-noc"; 1999 reg = <0 0x01500000 0 0x1c000>; 2000 #interconnect-cells = <2>; 2001 qcom,bcm-voters = <&apps_bcm_voter>; 2002 }; 2003 2004 system_noc: interconnect@1680000 { 2005 compatible = "qcom,sm8450-system-noc"; 2006 reg = <0 0x01680000 0 0x1e200>; 2007 #interconnect-cells = <2>; 2008 qcom,bcm-voters = <&apps_bcm_voter>; 2009 }; 2010 2011 pcie_noc: interconnect@16c0000 { 2012 compatible = "qcom,sm8450-pcie-anoc"; 2013 reg = <0 0x016c0000 0 0xe280>; 2014 #interconnect-cells = <2>; 2015 qcom,bcm-voters = <&apps_bcm_voter>; 2016 }; 2017 2018 aggre1_noc: interconnect@16e0000 { 2019 compatible = "qcom,sm8450-aggre1-noc"; 2020 reg = <0 0x016e0000 0 0x1c080>; 2021 #interconnect-cells = <2>; 2022 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2023 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2024 qcom,bcm-voters = <&apps_bcm_voter>; 2025 }; 2026 2027 aggre2_noc: interconnect@1700000 { 2028 compatible = "qcom,sm8450-aggre2-noc"; 2029 reg = <0 0x01700000 0 0x31080>; 2030 #interconnect-cells = <2>; 2031 qcom,bcm-voters = <&apps_bcm_voter>; 2032 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2033 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 2034 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2035 <&rpmhcc RPMH_IPA_CLK>; 2036 }; 2037 2038 mmss_noc: interconnect@1740000 { 2039 compatible = "qcom,sm8450-mmss-noc"; 2040 reg = <0 0x01740000 0 0x1f080>; 2041 #interconnect-cells = <2>; 2042 qcom,bcm-voters = <&apps_bcm_voter>; 2043 }; 2044 2045 tcsr_mutex: hwlock@1f40000 { 2046 compatible = "qcom,tcsr-mutex"; 2047 reg = <0x0 0x01f40000 0x0 0x40000>; 2048 #hwlock-cells = <1>; 2049 }; 2050 2051 tcsr: syscon@1fc0000 { 2052 compatible = "qcom,sm8450-tcsr", "syscon"; 2053 reg = <0x0 0x1fc0000 0x0 0x30000>; 2054 }; 2055 2056 gpu: gpu@3d00000 { 2057 compatible = "qcom,adreno-730.1", "qcom,adreno"; 2058 reg = <0x0 0x03d00000 0x0 0x40000>, 2059 <0x0 0x03d9e000 0x0 0x1000>, 2060 <0x0 0x03d61000 0x0 0x800>; 2061 reg-names = "kgsl_3d0_reg_memory", 2062 "cx_mem", 2063 "cx_dbgc"; 2064 2065 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2066 2067 iommus = <&adreno_smmu 0 0x400>, 2068 <&adreno_smmu 1 0x400>; 2069 2070 operating-points-v2 = <&gpu_opp_table>; 2071 2072 qcom,gmu = <&gmu>; 2073 #cooling-cells = <2>; 2074 2075 status = "disabled"; 2076 2077 zap-shader { 2078 memory-region = <&gpu_micro_code_mem>; 2079 }; 2080 2081 gpu_opp_table: opp-table { 2082 compatible = "operating-points-v2"; 2083 2084 opp-818000000 { 2085 opp-hz = /bits/ 64 <818000000>; 2086 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2087 }; 2088 2089 opp-791000000 { 2090 opp-hz = /bits/ 64 <791000000>; 2091 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2092 }; 2093 2094 opp-734000000 { 2095 opp-hz = /bits/ 64 <734000000>; 2096 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2097 }; 2098 2099 opp-640000000 { 2100 opp-hz = /bits/ 64 <640000000>; 2101 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2102 }; 2103 2104 opp-599000000 { 2105 opp-hz = /bits/ 64 <599000000>; 2106 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2107 }; 2108 2109 opp-545000000 { 2110 opp-hz = /bits/ 64 <545000000>; 2111 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2112 }; 2113 2114 opp-492000000 { 2115 opp-hz = /bits/ 64 <492000000>; 2116 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2117 }; 2118 2119 opp-421000000 { 2120 opp-hz = /bits/ 64 <421000000>; 2121 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2122 }; 2123 2124 opp-350000000 { 2125 opp-hz = /bits/ 64 <350000000>; 2126 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2127 }; 2128 2129 opp-317000000 { 2130 opp-hz = /bits/ 64 <317000000>; 2131 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2132 }; 2133 2134 opp-285000000 { 2135 opp-hz = /bits/ 64 <285000000>; 2136 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2137 }; 2138 2139 opp-220000000 { 2140 opp-hz = /bits/ 64 <220000000>; 2141 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2142 }; 2143 }; 2144 }; 2145 2146 gmu: gmu@3d6a000 { 2147 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu"; 2148 reg = <0x0 0x03d6a000 0x0 0x35000>, 2149 <0x0 0x03d50000 0x0 0x10000>, 2150 <0x0 0x0b290000 0x0 0x10000>; 2151 reg-names = "gmu", "rscc", "gmu_pdc"; 2152 2153 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2155 interrupt-names = "hfi", "gmu"; 2156 2157 clocks = <&gpucc GPU_CC_AHB_CLK>, 2158 <&gpucc GPU_CC_CX_GMU_CLK>, 2159 <&gpucc GPU_CC_CXO_CLK>, 2160 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2161 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2162 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2163 <&gpucc GPU_CC_DEMET_CLK>; 2164 clock-names = "ahb", 2165 "gmu", 2166 "cxo", 2167 "axi", 2168 "memnoc", 2169 "hub", 2170 "demet"; 2171 2172 power-domains = <&gpucc GPU_CX_GDSC>, 2173 <&gpucc GPU_GX_GDSC>; 2174 power-domain-names = "cx", 2175 "gx"; 2176 2177 iommus = <&adreno_smmu 5 0x400>; 2178 2179 qcom,qmp = <&aoss_qmp>; 2180 2181 operating-points-v2 = <&gmu_opp_table>; 2182 2183 gmu_opp_table: opp-table { 2184 compatible = "operating-points-v2"; 2185 2186 opp-500000000 { 2187 opp-hz = /bits/ 64 <500000000>; 2188 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2189 }; 2190 2191 opp-200000000 { 2192 opp-hz = /bits/ 64 <200000000>; 2193 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2194 }; 2195 }; 2196 }; 2197 2198 gpucc: clock-controller@3d90000 { 2199 compatible = "qcom,sm8450-gpucc"; 2200 reg = <0x0 0x03d90000 0x0 0xa000>; 2201 clocks = <&rpmhcc RPMH_CXO_CLK>, 2202 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2203 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2204 #clock-cells = <1>; 2205 #reset-cells = <1>; 2206 #power-domain-cells = <1>; 2207 }; 2208 2209 adreno_smmu: iommu@3da0000 { 2210 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu", 2211 "qcom,smmu-500", "arm,mmu-500"; 2212 reg = <0x0 0x03da0000 0x0 0x40000>; 2213 #iommu-cells = <2>; 2214 #global-interrupts = <1>; 2215 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2219 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2221 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2223 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2228 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2229 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2231 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2236 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2237 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2238 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2239 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, 2240 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 2241 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2242 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2243 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2244 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2245 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2246 <&gpucc GPU_CC_AHB_CLK>; 2247 clock-names = "gmu", 2248 "hub", 2249 "hlos", 2250 "bus", 2251 "iface", 2252 "ahb"; 2253 power-domains = <&gpucc GPU_CX_GDSC>; 2254 dma-coherent; 2255 }; 2256 2257 usb_1_hsphy: phy@88e3000 { 2258 compatible = "qcom,sm8450-usb-hs-phy", 2259 "qcom,usb-snps-hs-7nm-phy"; 2260 reg = <0 0x088e3000 0 0x400>; 2261 status = "disabled"; 2262 #phy-cells = <0>; 2263 2264 clocks = <&rpmhcc RPMH_CXO_CLK>; 2265 clock-names = "ref"; 2266 2267 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2268 }; 2269 2270 usb_1_qmpphy: phy@88e8000 { 2271 compatible = "qcom,sm8450-qmp-usb3-dp-phy"; 2272 reg = <0 0x088e8000 0 0x3000>; 2273 2274 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2275 <&rpmhcc RPMH_CXO_CLK>, 2276 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2277 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2278 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2279 2280 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2281 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2282 reset-names = "phy", "common"; 2283 2284 #clock-cells = <1>; 2285 #phy-cells = <1>; 2286 2287 status = "disabled"; 2288 2289 ports { 2290 #address-cells = <1>; 2291 #size-cells = <0>; 2292 2293 port@0 { 2294 reg = <0>; 2295 2296 usb_1_qmpphy_out: endpoint { 2297 }; 2298 }; 2299 2300 port@1 { 2301 reg = <1>; 2302 2303 usb_1_qmpphy_usb_ss_in: endpoint { 2304 }; 2305 }; 2306 2307 port@2 { 2308 reg = <2>; 2309 2310 usb_1_qmpphy_dp_in: endpoint { 2311 }; 2312 }; 2313 }; 2314 }; 2315 2316 remoteproc_slpi: remoteproc@2400000 { 2317 compatible = "qcom,sm8450-slpi-pas"; 2318 reg = <0 0x02400000 0 0x4000>; 2319 2320 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2321 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2322 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2323 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2324 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2325 interrupt-names = "wdog", "fatal", "ready", 2326 "handover", "stop-ack"; 2327 2328 clocks = <&rpmhcc RPMH_CXO_CLK>; 2329 clock-names = "xo"; 2330 2331 power-domains = <&rpmhpd RPMHPD_LCX>, 2332 <&rpmhpd RPMHPD_LMX>; 2333 power-domain-names = "lcx", "lmx"; 2334 2335 memory-region = <&slpi_mem>; 2336 2337 qcom,qmp = <&aoss_qmp>; 2338 2339 qcom,smem-states = <&smp2p_slpi_out 0>; 2340 qcom,smem-state-names = "stop"; 2341 2342 status = "disabled"; 2343 2344 glink-edge { 2345 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2346 IPCC_MPROC_SIGNAL_GLINK_QMP 2347 IRQ_TYPE_EDGE_RISING>; 2348 mboxes = <&ipcc IPCC_CLIENT_SLPI 2349 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2350 2351 label = "slpi"; 2352 qcom,remote-pid = <3>; 2353 2354 fastrpc { 2355 compatible = "qcom,fastrpc"; 2356 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2357 label = "sdsp"; 2358 #address-cells = <1>; 2359 #size-cells = <0>; 2360 2361 compute-cb@1 { 2362 compatible = "qcom,fastrpc-compute-cb"; 2363 reg = <1>; 2364 iommus = <&apps_smmu 0x0541 0x0>; 2365 }; 2366 2367 compute-cb@2 { 2368 compatible = "qcom,fastrpc-compute-cb"; 2369 reg = <2>; 2370 iommus = <&apps_smmu 0x0542 0x0>; 2371 }; 2372 2373 compute-cb@3 { 2374 compatible = "qcom,fastrpc-compute-cb"; 2375 reg = <3>; 2376 iommus = <&apps_smmu 0x0543 0x0>; 2377 /* note: shared-cb = <4> in downstream */ 2378 }; 2379 }; 2380 }; 2381 }; 2382 2383 wsa2macro: codec@31e0000 { 2384 compatible = "qcom,sm8450-lpass-wsa-macro"; 2385 reg = <0 0x031e0000 0 0x1000>; 2386 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2387 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2388 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2389 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2390 <&vamacro>; 2391 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2392 2393 #clock-cells = <0>; 2394 clock-output-names = "wsa2-mclk"; 2395 #sound-dai-cells = <1>; 2396 }; 2397 2398 swr4: soundwire@31f0000 { 2399 compatible = "qcom,soundwire-v1.7.0"; 2400 reg = <0 0x031f0000 0 0x2000>; 2401 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2402 clocks = <&wsa2macro>; 2403 clock-names = "iface"; 2404 label = "WSA2"; 2405 2406 pinctrl-0 = <&wsa2_swr_active>; 2407 pinctrl-names = "default"; 2408 2409 qcom,din-ports = <2>; 2410 qcom,dout-ports = <6>; 2411 2412 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2413 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2414 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2415 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2416 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2417 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2418 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2419 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2420 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2421 2422 #address-cells = <2>; 2423 #size-cells = <0>; 2424 #sound-dai-cells = <1>; 2425 status = "disabled"; 2426 }; 2427 2428 rxmacro: codec@3200000 { 2429 compatible = "qcom,sm8450-lpass-rx-macro"; 2430 reg = <0 0x03200000 0 0x1000>; 2431 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2432 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2433 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2434 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2435 <&vamacro>; 2436 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2437 2438 #clock-cells = <0>; 2439 clock-output-names = "mclk"; 2440 #sound-dai-cells = <1>; 2441 }; 2442 2443 swr1: soundwire@3210000 { 2444 compatible = "qcom,soundwire-v1.7.0"; 2445 reg = <0 0x03210000 0 0x2000>; 2446 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2447 clocks = <&rxmacro>; 2448 clock-names = "iface"; 2449 label = "RX"; 2450 qcom,din-ports = <0>; 2451 qcom,dout-ports = <5>; 2452 2453 pinctrl-0 = <&rx_swr_active>; 2454 pinctrl-names = "default"; 2455 2456 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2457 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2458 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2459 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2460 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2461 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2462 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2463 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2464 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2465 2466 #address-cells = <2>; 2467 #size-cells = <0>; 2468 #sound-dai-cells = <1>; 2469 status = "disabled"; 2470 }; 2471 2472 txmacro: codec@3220000 { 2473 compatible = "qcom,sm8450-lpass-tx-macro"; 2474 reg = <0 0x03220000 0 0x1000>; 2475 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2476 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2477 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2478 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2479 <&vamacro>; 2480 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2481 2482 #clock-cells = <0>; 2483 clock-output-names = "mclk"; 2484 #sound-dai-cells = <1>; 2485 }; 2486 2487 wsamacro: codec@3240000 { 2488 compatible = "qcom,sm8450-lpass-wsa-macro"; 2489 reg = <0 0x03240000 0 0x1000>; 2490 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2491 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2492 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2493 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2494 <&vamacro>; 2495 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2496 2497 #clock-cells = <0>; 2498 clock-output-names = "mclk"; 2499 #sound-dai-cells = <1>; 2500 }; 2501 2502 swr0: soundwire@3250000 { 2503 compatible = "qcom,soundwire-v1.7.0"; 2504 reg = <0 0x03250000 0 0x2000>; 2505 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2506 clocks = <&wsamacro>; 2507 clock-names = "iface"; 2508 label = "WSA"; 2509 2510 pinctrl-0 = <&wsa_swr_active>; 2511 pinctrl-names = "default"; 2512 2513 qcom,din-ports = <2>; 2514 qcom,dout-ports = <6>; 2515 2516 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2517 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2518 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2519 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2520 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2521 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2522 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2523 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2524 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2525 2526 #address-cells = <2>; 2527 #size-cells = <0>; 2528 #sound-dai-cells = <1>; 2529 status = "disabled"; 2530 }; 2531 2532 swr2: soundwire@33b0000 { 2533 compatible = "qcom,soundwire-v1.7.0"; 2534 reg = <0 0x033b0000 0 0x2000>; 2535 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2536 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2537 interrupt-names = "core", "wakeup"; 2538 2539 clocks = <&txmacro>; 2540 clock-names = "iface"; 2541 label = "TX"; 2542 2543 pinctrl-0 = <&tx_swr_active>; 2544 pinctrl-names = "default"; 2545 2546 qcom,din-ports = <4>; 2547 qcom,dout-ports = <0>; 2548 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2549 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2550 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2551 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2552 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2553 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2554 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2555 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2556 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2557 2558 #address-cells = <2>; 2559 #size-cells = <0>; 2560 #sound-dai-cells = <1>; 2561 status = "disabled"; 2562 }; 2563 2564 vamacro: codec@33f0000 { 2565 compatible = "qcom,sm8450-lpass-va-macro"; 2566 reg = <0 0x033f0000 0 0x1000>; 2567 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2568 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2569 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2570 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2571 clock-names = "mclk", "macro", "dcodec", "npl"; 2572 2573 #clock-cells = <0>; 2574 clock-output-names = "fsgen"; 2575 #sound-dai-cells = <1>; 2576 status = "disabled"; 2577 }; 2578 2579 remoteproc_adsp: remoteproc@30000000 { 2580 compatible = "qcom,sm8450-adsp-pas"; 2581 reg = <0 0x30000000 0 0x100>; 2582 2583 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2584 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2585 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2586 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2587 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2588 interrupt-names = "wdog", "fatal", "ready", 2589 "handover", "stop-ack"; 2590 2591 clocks = <&rpmhcc RPMH_CXO_CLK>; 2592 clock-names = "xo"; 2593 2594 power-domains = <&rpmhpd RPMHPD_LCX>, 2595 <&rpmhpd RPMHPD_LMX>; 2596 power-domain-names = "lcx", "lmx"; 2597 2598 memory-region = <&adsp_mem>; 2599 2600 qcom,qmp = <&aoss_qmp>; 2601 2602 qcom,smem-states = <&smp2p_adsp_out 0>; 2603 qcom,smem-state-names = "stop"; 2604 2605 status = "disabled"; 2606 2607 remoteproc_adsp_glink: glink-edge { 2608 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2609 IPCC_MPROC_SIGNAL_GLINK_QMP 2610 IRQ_TYPE_EDGE_RISING>; 2611 mboxes = <&ipcc IPCC_CLIENT_LPASS 2612 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2613 2614 label = "lpass"; 2615 qcom,remote-pid = <2>; 2616 2617 gpr { 2618 compatible = "qcom,gpr"; 2619 qcom,glink-channels = "adsp_apps"; 2620 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2621 qcom,intents = <512 20>; 2622 #address-cells = <1>; 2623 #size-cells = <0>; 2624 2625 q6apm: service@1 { 2626 compatible = "qcom,q6apm"; 2627 reg = <GPR_APM_MODULE_IID>; 2628 #sound-dai-cells = <0>; 2629 qcom,protection-domain = "avs/audio", 2630 "msm/adsp/audio_pd"; 2631 2632 q6apmdai: dais { 2633 compatible = "qcom,q6apm-dais"; 2634 iommus = <&apps_smmu 0x1801 0x0>; 2635 }; 2636 2637 q6apmbedai: bedais { 2638 compatible = "qcom,q6apm-lpass-dais"; 2639 #sound-dai-cells = <1>; 2640 }; 2641 }; 2642 2643 q6prm: service@2 { 2644 compatible = "qcom,q6prm"; 2645 reg = <GPR_PRM_MODULE_IID>; 2646 qcom,protection-domain = "avs/audio", 2647 "msm/adsp/audio_pd"; 2648 2649 q6prmcc: clock-controller { 2650 compatible = "qcom,q6prm-lpass-clocks"; 2651 #clock-cells = <2>; 2652 }; 2653 }; 2654 }; 2655 2656 fastrpc { 2657 compatible = "qcom,fastrpc"; 2658 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2659 label = "adsp"; 2660 #address-cells = <1>; 2661 #size-cells = <0>; 2662 2663 compute-cb@3 { 2664 compatible = "qcom,fastrpc-compute-cb"; 2665 reg = <3>; 2666 iommus = <&apps_smmu 0x1803 0x0>; 2667 }; 2668 2669 compute-cb@4 { 2670 compatible = "qcom,fastrpc-compute-cb"; 2671 reg = <4>; 2672 iommus = <&apps_smmu 0x1804 0x0>; 2673 }; 2674 2675 compute-cb@5 { 2676 compatible = "qcom,fastrpc-compute-cb"; 2677 reg = <5>; 2678 iommus = <&apps_smmu 0x1805 0x0>; 2679 }; 2680 }; 2681 }; 2682 }; 2683 2684 remoteproc_cdsp: remoteproc@32300000 { 2685 compatible = "qcom,sm8450-cdsp-pas"; 2686 reg = <0 0x32300000 0 0x1400000>; 2687 2688 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2689 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2690 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2691 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2692 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2693 interrupt-names = "wdog", "fatal", "ready", 2694 "handover", "stop-ack"; 2695 2696 clocks = <&rpmhcc RPMH_CXO_CLK>; 2697 clock-names = "xo"; 2698 2699 power-domains = <&rpmhpd RPMHPD_CX>, 2700 <&rpmhpd RPMHPD_MXC>; 2701 power-domain-names = "cx", "mxc"; 2702 2703 memory-region = <&cdsp_mem>; 2704 2705 qcom,qmp = <&aoss_qmp>; 2706 2707 qcom,smem-states = <&smp2p_cdsp_out 0>; 2708 qcom,smem-state-names = "stop"; 2709 2710 status = "disabled"; 2711 2712 glink-edge { 2713 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2714 IPCC_MPROC_SIGNAL_GLINK_QMP 2715 IRQ_TYPE_EDGE_RISING>; 2716 mboxes = <&ipcc IPCC_CLIENT_CDSP 2717 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2718 2719 label = "cdsp"; 2720 qcom,remote-pid = <5>; 2721 2722 fastrpc { 2723 compatible = "qcom,fastrpc"; 2724 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2725 label = "cdsp"; 2726 #address-cells = <1>; 2727 #size-cells = <0>; 2728 2729 compute-cb@1 { 2730 compatible = "qcom,fastrpc-compute-cb"; 2731 reg = <1>; 2732 iommus = <&apps_smmu 0x2161 0x0400>, 2733 <&apps_smmu 0x1021 0x1420>; 2734 }; 2735 2736 compute-cb@2 { 2737 compatible = "qcom,fastrpc-compute-cb"; 2738 reg = <2>; 2739 iommus = <&apps_smmu 0x2162 0x0400>, 2740 <&apps_smmu 0x1022 0x1420>; 2741 }; 2742 2743 compute-cb@3 { 2744 compatible = "qcom,fastrpc-compute-cb"; 2745 reg = <3>; 2746 iommus = <&apps_smmu 0x2163 0x0400>, 2747 <&apps_smmu 0x1023 0x1420>; 2748 }; 2749 2750 compute-cb@4 { 2751 compatible = "qcom,fastrpc-compute-cb"; 2752 reg = <4>; 2753 iommus = <&apps_smmu 0x2164 0x0400>, 2754 <&apps_smmu 0x1024 0x1420>; 2755 }; 2756 2757 compute-cb@5 { 2758 compatible = "qcom,fastrpc-compute-cb"; 2759 reg = <5>; 2760 iommus = <&apps_smmu 0x2165 0x0400>, 2761 <&apps_smmu 0x1025 0x1420>; 2762 }; 2763 2764 compute-cb@6 { 2765 compatible = "qcom,fastrpc-compute-cb"; 2766 reg = <6>; 2767 iommus = <&apps_smmu 0x2166 0x0400>, 2768 <&apps_smmu 0x1026 0x1420>; 2769 }; 2770 2771 compute-cb@7 { 2772 compatible = "qcom,fastrpc-compute-cb"; 2773 reg = <7>; 2774 iommus = <&apps_smmu 0x2167 0x0400>, 2775 <&apps_smmu 0x1027 0x1420>; 2776 }; 2777 2778 compute-cb@8 { 2779 compatible = "qcom,fastrpc-compute-cb"; 2780 reg = <8>; 2781 iommus = <&apps_smmu 0x2168 0x0400>, 2782 <&apps_smmu 0x1028 0x1420>; 2783 }; 2784 2785 /* note: secure cb9 in downstream */ 2786 }; 2787 }; 2788 }; 2789 2790 remoteproc_mpss: remoteproc@4080000 { 2791 compatible = "qcom,sm8450-mpss-pas"; 2792 reg = <0x0 0x04080000 0x0 0x4040>; 2793 2794 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2795 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2796 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2797 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2798 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2799 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2800 interrupt-names = "wdog", "fatal", "ready", "handover", 2801 "stop-ack", "shutdown-ack"; 2802 2803 clocks = <&rpmhcc RPMH_CXO_CLK>; 2804 clock-names = "xo"; 2805 2806 power-domains = <&rpmhpd RPMHPD_CX>, 2807 <&rpmhpd RPMHPD_MSS>; 2808 power-domain-names = "cx", "mss"; 2809 2810 memory-region = <&mpss_mem>; 2811 2812 qcom,qmp = <&aoss_qmp>; 2813 2814 qcom,smem-states = <&smp2p_modem_out 0>; 2815 qcom,smem-state-names = "stop"; 2816 2817 status = "disabled"; 2818 2819 glink-edge { 2820 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2821 IPCC_MPROC_SIGNAL_GLINK_QMP 2822 IRQ_TYPE_EDGE_RISING>; 2823 mboxes = <&ipcc IPCC_CLIENT_MPSS 2824 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2825 label = "modem"; 2826 qcom,remote-pid = <1>; 2827 }; 2828 }; 2829 2830 videocc: clock-controller@aaf0000 { 2831 compatible = "qcom,sm8450-videocc"; 2832 reg = <0 0x0aaf0000 0 0x10000>; 2833 clocks = <&rpmhcc RPMH_CXO_CLK>, 2834 <&gcc GCC_VIDEO_AHB_CLK>; 2835 power-domains = <&rpmhpd RPMHPD_MMCX>; 2836 required-opps = <&rpmhpd_opp_low_svs>; 2837 #clock-cells = <1>; 2838 #reset-cells = <1>; 2839 #power-domain-cells = <1>; 2840 }; 2841 2842 cci0: cci@ac15000 { 2843 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2844 reg = <0 0x0ac15000 0 0x1000>; 2845 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 2846 power-domains = <&camcc TITAN_TOP_GDSC>; 2847 2848 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2849 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2850 <&camcc CAM_CC_CPAS_AHB_CLK>, 2851 <&camcc CAM_CC_CCI_0_CLK>, 2852 <&camcc CAM_CC_CCI_0_CLK_SRC>; 2853 clock-names = "camnoc_axi", 2854 "slow_ahb_src", 2855 "cpas_ahb", 2856 "cci", 2857 "cci_src"; 2858 pinctrl-0 = <&cci0_default &cci1_default>; 2859 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2860 pinctrl-names = "default", "sleep"; 2861 2862 status = "disabled"; 2863 #address-cells = <1>; 2864 #size-cells = <0>; 2865 2866 cci0_i2c0: i2c-bus@0 { 2867 reg = <0>; 2868 clock-frequency = <1000000>; 2869 #address-cells = <1>; 2870 #size-cells = <0>; 2871 }; 2872 2873 cci0_i2c1: i2c-bus@1 { 2874 reg = <1>; 2875 clock-frequency = <1000000>; 2876 #address-cells = <1>; 2877 #size-cells = <0>; 2878 }; 2879 }; 2880 2881 cci1: cci@ac16000 { 2882 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2883 reg = <0 0x0ac16000 0 0x1000>; 2884 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 2885 power-domains = <&camcc TITAN_TOP_GDSC>; 2886 2887 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2888 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2889 <&camcc CAM_CC_CPAS_AHB_CLK>, 2890 <&camcc CAM_CC_CCI_1_CLK>, 2891 <&camcc CAM_CC_CCI_1_CLK_SRC>; 2892 clock-names = "camnoc_axi", 2893 "slow_ahb_src", 2894 "cpas_ahb", 2895 "cci", 2896 "cci_src"; 2897 pinctrl-0 = <&cci2_default &cci3_default>; 2898 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 2899 pinctrl-names = "default", "sleep"; 2900 2901 status = "disabled"; 2902 #address-cells = <1>; 2903 #size-cells = <0>; 2904 2905 cci1_i2c0: i2c-bus@0 { 2906 reg = <0>; 2907 clock-frequency = <1000000>; 2908 #address-cells = <1>; 2909 #size-cells = <0>; 2910 }; 2911 2912 cci1_i2c1: i2c-bus@1 { 2913 reg = <1>; 2914 clock-frequency = <1000000>; 2915 #address-cells = <1>; 2916 #size-cells = <0>; 2917 }; 2918 }; 2919 2920 camcc: clock-controller@ade0000 { 2921 compatible = "qcom,sm8450-camcc"; 2922 reg = <0 0x0ade0000 0 0x20000>; 2923 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2924 <&rpmhcc RPMH_CXO_CLK>, 2925 <&rpmhcc RPMH_CXO_CLK_A>, 2926 <&sleep_clk>; 2927 power-domains = <&rpmhpd RPMHPD_MMCX>; 2928 required-opps = <&rpmhpd_opp_low_svs>; 2929 #clock-cells = <1>; 2930 #reset-cells = <1>; 2931 #power-domain-cells = <1>; 2932 status = "disabled"; 2933 }; 2934 2935 mdss: display-subsystem@ae00000 { 2936 compatible = "qcom,sm8450-mdss"; 2937 reg = <0 0x0ae00000 0 0x1000>; 2938 reg-names = "mdss"; 2939 2940 /* same path used twice */ 2941 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2942 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2943 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2944 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2945 interconnect-names = "mdp0-mem", 2946 "mdp1-mem", 2947 "cpu-cfg"; 2948 2949 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2950 2951 power-domains = <&dispcc MDSS_GDSC>; 2952 2953 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2954 <&gcc GCC_DISP_HF_AXI_CLK>, 2955 <&gcc GCC_DISP_SF_AXI_CLK>, 2956 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2957 2958 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2959 interrupt-controller; 2960 #interrupt-cells = <1>; 2961 2962 iommus = <&apps_smmu 0x2800 0x402>; 2963 2964 #address-cells = <2>; 2965 #size-cells = <2>; 2966 ranges; 2967 2968 status = "disabled"; 2969 2970 mdss_mdp: display-controller@ae01000 { 2971 compatible = "qcom,sm8450-dpu"; 2972 reg = <0 0x0ae01000 0 0x8f000>, 2973 <0 0x0aeb0000 0 0x2008>; 2974 reg-names = "mdp", "vbif"; 2975 2976 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2977 <&gcc GCC_DISP_SF_AXI_CLK>, 2978 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2979 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2980 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2981 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2982 clock-names = "bus", 2983 "nrt_bus", 2984 "iface", 2985 "lut", 2986 "core", 2987 "vsync"; 2988 2989 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2990 assigned-clock-rates = <19200000>; 2991 2992 operating-points-v2 = <&mdp_opp_table>; 2993 power-domains = <&rpmhpd RPMHPD_MMCX>; 2994 2995 interrupt-parent = <&mdss>; 2996 interrupts = <0>; 2997 2998 ports { 2999 #address-cells = <1>; 3000 #size-cells = <0>; 3001 3002 port@0 { 3003 reg = <0>; 3004 dpu_intf1_out: endpoint { 3005 remote-endpoint = <&mdss_dsi0_in>; 3006 }; 3007 }; 3008 3009 port@1 { 3010 reg = <1>; 3011 dpu_intf2_out: endpoint { 3012 remote-endpoint = <&mdss_dsi1_in>; 3013 }; 3014 }; 3015 3016 port@2 { 3017 reg = <2>; 3018 dpu_intf0_out: endpoint { 3019 remote-endpoint = <&mdss_dp0_in>; 3020 }; 3021 }; 3022 }; 3023 3024 mdp_opp_table: opp-table { 3025 compatible = "operating-points-v2"; 3026 3027 opp-172000000 { 3028 opp-hz = /bits/ 64 <172000000>; 3029 required-opps = <&rpmhpd_opp_low_svs_d1>; 3030 }; 3031 3032 opp-200000000 { 3033 opp-hz = /bits/ 64 <200000000>; 3034 required-opps = <&rpmhpd_opp_low_svs>; 3035 }; 3036 3037 opp-325000000 { 3038 opp-hz = /bits/ 64 <325000000>; 3039 required-opps = <&rpmhpd_opp_svs>; 3040 }; 3041 3042 opp-375000000 { 3043 opp-hz = /bits/ 64 <375000000>; 3044 required-opps = <&rpmhpd_opp_svs_l1>; 3045 }; 3046 3047 opp-500000000 { 3048 opp-hz = /bits/ 64 <500000000>; 3049 required-opps = <&rpmhpd_opp_nom>; 3050 }; 3051 }; 3052 }; 3053 3054 mdss_dp0: displayport-controller@ae90000 { 3055 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; 3056 reg = <0 0xae90000 0 0x200>, 3057 <0 0xae90200 0 0x200>, 3058 <0 0xae90400 0 0xc00>, 3059 <0 0xae91000 0 0x400>, 3060 <0 0xae91400 0 0x400>; 3061 interrupt-parent = <&mdss>; 3062 interrupts = <12>; 3063 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3064 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3065 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3066 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3067 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3068 clock-names = "core_iface", 3069 "core_aux", 3070 "ctrl_link", 3071 "ctrl_link_iface", 3072 "stream_pixel"; 3073 3074 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3075 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3076 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3077 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3078 3079 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3080 phy-names = "dp"; 3081 3082 #sound-dai-cells = <0>; 3083 3084 operating-points-v2 = <&dp_opp_table>; 3085 power-domains = <&rpmhpd RPMHPD_MMCX>; 3086 3087 status = "disabled"; 3088 3089 ports { 3090 #address-cells = <1>; 3091 #size-cells = <0>; 3092 3093 port@0 { 3094 reg = <0>; 3095 mdss_dp0_in: endpoint { 3096 remote-endpoint = <&dpu_intf0_out>; 3097 }; 3098 }; 3099 }; 3100 3101 dp_opp_table: opp-table { 3102 compatible = "operating-points-v2"; 3103 3104 opp-160000000 { 3105 opp-hz = /bits/ 64 <160000000>; 3106 required-opps = <&rpmhpd_opp_low_svs>; 3107 }; 3108 3109 opp-270000000 { 3110 opp-hz = /bits/ 64 <270000000>; 3111 required-opps = <&rpmhpd_opp_svs>; 3112 }; 3113 3114 opp-540000000 { 3115 opp-hz = /bits/ 64 <540000000>; 3116 required-opps = <&rpmhpd_opp_svs_l1>; 3117 }; 3118 3119 opp-810000000 { 3120 opp-hz = /bits/ 64 <810000000>; 3121 required-opps = <&rpmhpd_opp_nom>; 3122 }; 3123 }; 3124 }; 3125 3126 mdss_dsi0: dsi@ae94000 { 3127 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3128 reg = <0 0x0ae94000 0 0x400>; 3129 reg-names = "dsi_ctrl"; 3130 3131 interrupt-parent = <&mdss>; 3132 interrupts = <4>; 3133 3134 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3135 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3136 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3137 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3138 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3139 <&gcc GCC_DISP_HF_AXI_CLK>; 3140 clock-names = "byte", 3141 "byte_intf", 3142 "pixel", 3143 "core", 3144 "iface", 3145 "bus"; 3146 3147 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3148 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 3149 3150 operating-points-v2 = <&mdss_dsi_opp_table>; 3151 power-domains = <&rpmhpd RPMHPD_MMCX>; 3152 3153 phys = <&mdss_dsi0_phy>; 3154 phy-names = "dsi"; 3155 3156 #address-cells = <1>; 3157 #size-cells = <0>; 3158 3159 status = "disabled"; 3160 3161 ports { 3162 #address-cells = <1>; 3163 #size-cells = <0>; 3164 3165 port@0 { 3166 reg = <0>; 3167 mdss_dsi0_in: endpoint { 3168 remote-endpoint = <&dpu_intf1_out>; 3169 }; 3170 }; 3171 3172 port@1 { 3173 reg = <1>; 3174 mdss_dsi0_out: endpoint { 3175 }; 3176 }; 3177 }; 3178 3179 mdss_dsi_opp_table: opp-table { 3180 compatible = "operating-points-v2"; 3181 3182 opp-187500000 { 3183 opp-hz = /bits/ 64 <187500000>; 3184 required-opps = <&rpmhpd_opp_low_svs>; 3185 }; 3186 3187 opp-300000000 { 3188 opp-hz = /bits/ 64 <300000000>; 3189 required-opps = <&rpmhpd_opp_svs>; 3190 }; 3191 3192 opp-358000000 { 3193 opp-hz = /bits/ 64 <358000000>; 3194 required-opps = <&rpmhpd_opp_svs_l1>; 3195 }; 3196 }; 3197 }; 3198 3199 mdss_dsi0_phy: phy@ae94400 { 3200 compatible = "qcom,sm8450-dsi-phy-5nm"; 3201 reg = <0 0x0ae94400 0 0x200>, 3202 <0 0x0ae94600 0 0x280>, 3203 <0 0x0ae94900 0 0x260>; 3204 reg-names = "dsi_phy", 3205 "dsi_phy_lane", 3206 "dsi_pll"; 3207 3208 #clock-cells = <1>; 3209 #phy-cells = <0>; 3210 3211 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3212 <&rpmhcc RPMH_CXO_CLK>; 3213 clock-names = "iface", "ref"; 3214 3215 status = "disabled"; 3216 }; 3217 3218 mdss_dsi1: dsi@ae96000 { 3219 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3220 reg = <0 0x0ae96000 0 0x400>; 3221 reg-names = "dsi_ctrl"; 3222 3223 interrupt-parent = <&mdss>; 3224 interrupts = <5>; 3225 3226 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3227 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3228 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3229 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3230 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3231 <&gcc GCC_DISP_HF_AXI_CLK>; 3232 clock-names = "byte", 3233 "byte_intf", 3234 "pixel", 3235 "core", 3236 "iface", 3237 "bus"; 3238 3239 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3240 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 3241 3242 operating-points-v2 = <&mdss_dsi_opp_table>; 3243 power-domains = <&rpmhpd RPMHPD_MMCX>; 3244 3245 phys = <&mdss_dsi1_phy>; 3246 phy-names = "dsi"; 3247 3248 #address-cells = <1>; 3249 #size-cells = <0>; 3250 3251 status = "disabled"; 3252 3253 ports { 3254 #address-cells = <1>; 3255 #size-cells = <0>; 3256 3257 port@0 { 3258 reg = <0>; 3259 mdss_dsi1_in: endpoint { 3260 remote-endpoint = <&dpu_intf2_out>; 3261 }; 3262 }; 3263 3264 port@1 { 3265 reg = <1>; 3266 mdss_dsi1_out: endpoint { 3267 }; 3268 }; 3269 }; 3270 }; 3271 3272 mdss_dsi1_phy: phy@ae96400 { 3273 compatible = "qcom,sm8450-dsi-phy-5nm"; 3274 reg = <0 0x0ae96400 0 0x200>, 3275 <0 0x0ae96600 0 0x280>, 3276 <0 0x0ae96900 0 0x260>; 3277 reg-names = "dsi_phy", 3278 "dsi_phy_lane", 3279 "dsi_pll"; 3280 3281 #clock-cells = <1>; 3282 #phy-cells = <0>; 3283 3284 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3285 <&rpmhcc RPMH_CXO_CLK>; 3286 clock-names = "iface", "ref"; 3287 3288 status = "disabled"; 3289 }; 3290 }; 3291 3292 dispcc: clock-controller@af00000 { 3293 compatible = "qcom,sm8450-dispcc"; 3294 reg = <0 0x0af00000 0 0x20000>; 3295 clocks = <&rpmhcc RPMH_CXO_CLK>, 3296 <&rpmhcc RPMH_CXO_CLK_A>, 3297 <&gcc GCC_DISP_AHB_CLK>, 3298 <&sleep_clk>, 3299 <&mdss_dsi0_phy 0>, 3300 <&mdss_dsi0_phy 1>, 3301 <&mdss_dsi1_phy 0>, 3302 <&mdss_dsi1_phy 1>, 3303 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3304 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3305 <0>, /* dp1 */ 3306 <0>, 3307 <0>, /* dp2 */ 3308 <0>, 3309 <0>, /* dp3 */ 3310 <0>; 3311 power-domains = <&rpmhpd RPMHPD_MMCX>; 3312 required-opps = <&rpmhpd_opp_low_svs>; 3313 #clock-cells = <1>; 3314 #reset-cells = <1>; 3315 #power-domain-cells = <1>; 3316 status = "disabled"; 3317 }; 3318 3319 pdc: interrupt-controller@b220000 { 3320 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 3321 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3322 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 3323 <94 609 31>, <125 63 1>, <126 716 12>; 3324 #interrupt-cells = <2>; 3325 interrupt-parent = <&intc>; 3326 interrupt-controller; 3327 }; 3328 3329 tsens0: thermal-sensor@c263000 { 3330 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3331 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3332 <0 0x0c222000 0 0x1000>; /* SROT */ 3333 #qcom,sensors = <16>; 3334 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3336 interrupt-names = "uplow", "critical"; 3337 #thermal-sensor-cells = <1>; 3338 }; 3339 3340 tsens1: thermal-sensor@c265000 { 3341 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3342 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3343 <0 0x0c223000 0 0x1000>; /* SROT */ 3344 #qcom,sensors = <16>; 3345 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3347 interrupt-names = "uplow", "critical"; 3348 #thermal-sensor-cells = <1>; 3349 }; 3350 3351 aoss_qmp: power-management@c300000 { 3352 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3353 reg = <0 0x0c300000 0 0x400>; 3354 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3355 IRQ_TYPE_EDGE_RISING>; 3356 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3357 3358 #clock-cells = <0>; 3359 }; 3360 3361 sram@c3f0000 { 3362 compatible = "qcom,rpmh-stats"; 3363 reg = <0 0x0c3f0000 0 0x400>; 3364 }; 3365 3366 spmi_bus: spmi@c400000 { 3367 compatible = "qcom,spmi-pmic-arb"; 3368 reg = <0 0x0c400000 0 0x00003000>, 3369 <0 0x0c500000 0 0x00400000>, 3370 <0 0x0c440000 0 0x00080000>, 3371 <0 0x0c4c0000 0 0x00010000>, 3372 <0 0x0c42d000 0 0x00010000>; 3373 reg-names = "core", 3374 "chnls", 3375 "obsrvr", 3376 "intr", 3377 "cnfg"; 3378 interrupt-names = "periph_irq"; 3379 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3380 qcom,ee = <0>; 3381 qcom,channel = <0>; 3382 interrupt-controller; 3383 #interrupt-cells = <4>; 3384 #address-cells = <2>; 3385 #size-cells = <0>; 3386 }; 3387 3388 ipcc: mailbox@ed18000 { 3389 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3390 reg = <0 0x0ed18000 0 0x1000>; 3391 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3392 interrupt-controller; 3393 #interrupt-cells = <3>; 3394 #mbox-cells = <2>; 3395 }; 3396 3397 tlmm: pinctrl@f100000 { 3398 compatible = "qcom,sm8450-tlmm"; 3399 reg = <0 0x0f100000 0 0x300000>; 3400 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3401 gpio-controller; 3402 #gpio-cells = <2>; 3403 interrupt-controller; 3404 #interrupt-cells = <2>; 3405 gpio-ranges = <&tlmm 0 0 211>; 3406 wakeup-parent = <&pdc>; 3407 3408 sdc2_default_state: sdc2-default-state { 3409 clk-pins { 3410 pins = "sdc2_clk"; 3411 drive-strength = <16>; 3412 bias-disable; 3413 }; 3414 3415 cmd-pins { 3416 pins = "sdc2_cmd"; 3417 drive-strength = <16>; 3418 bias-pull-up; 3419 }; 3420 3421 data-pins { 3422 pins = "sdc2_data"; 3423 drive-strength = <16>; 3424 bias-pull-up; 3425 }; 3426 }; 3427 3428 sdc2_sleep_state: sdc2-sleep-state { 3429 clk-pins { 3430 pins = "sdc2_clk"; 3431 drive-strength = <2>; 3432 bias-disable; 3433 }; 3434 3435 cmd-pins { 3436 pins = "sdc2_cmd"; 3437 drive-strength = <2>; 3438 bias-pull-up; 3439 }; 3440 3441 data-pins { 3442 pins = "sdc2_data"; 3443 drive-strength = <2>; 3444 bias-pull-up; 3445 }; 3446 }; 3447 3448 cci0_default: cci0-default-state { 3449 /* SDA, SCL */ 3450 pins = "gpio110", "gpio111"; 3451 function = "cci_i2c"; 3452 drive-strength = <2>; 3453 bias-pull-up; 3454 }; 3455 3456 cci0_sleep: cci0-sleep-state { 3457 /* SDA, SCL */ 3458 pins = "gpio110", "gpio111"; 3459 function = "cci_i2c"; 3460 drive-strength = <2>; 3461 bias-pull-down; 3462 }; 3463 3464 cci1_default: cci1-default-state { 3465 /* SDA, SCL */ 3466 pins = "gpio112", "gpio113"; 3467 function = "cci_i2c"; 3468 drive-strength = <2>; 3469 bias-pull-up; 3470 }; 3471 3472 cci1_sleep: cci1-sleep-state { 3473 /* SDA, SCL */ 3474 pins = "gpio112", "gpio113"; 3475 function = "cci_i2c"; 3476 drive-strength = <2>; 3477 bias-pull-down; 3478 }; 3479 3480 cci2_default: cci2-default-state { 3481 /* SDA, SCL */ 3482 pins = "gpio114", "gpio115"; 3483 function = "cci_i2c"; 3484 drive-strength = <2>; 3485 bias-pull-up; 3486 }; 3487 3488 cci2_sleep: cci2-sleep-state { 3489 /* SDA, SCL */ 3490 pins = "gpio114", "gpio115"; 3491 function = "cci_i2c"; 3492 drive-strength = <2>; 3493 bias-pull-down; 3494 }; 3495 3496 cci3_default: cci3-default-state { 3497 /* SDA, SCL */ 3498 pins = "gpio208", "gpio209"; 3499 function = "cci_i2c"; 3500 drive-strength = <2>; 3501 bias-pull-up; 3502 }; 3503 3504 cci3_sleep: cci3-sleep-state { 3505 /* SDA, SCL */ 3506 pins = "gpio208", "gpio209"; 3507 function = "cci_i2c"; 3508 drive-strength = <2>; 3509 bias-pull-down; 3510 }; 3511 3512 pcie0_default_state: pcie0-default-state { 3513 perst-pins { 3514 pins = "gpio94"; 3515 function = "gpio"; 3516 drive-strength = <2>; 3517 bias-pull-down; 3518 }; 3519 3520 clkreq-pins { 3521 pins = "gpio95"; 3522 function = "pcie0_clkreqn"; 3523 drive-strength = <2>; 3524 bias-pull-up; 3525 }; 3526 3527 wake-pins { 3528 pins = "gpio96"; 3529 function = "gpio"; 3530 drive-strength = <2>; 3531 bias-pull-up; 3532 }; 3533 }; 3534 3535 pcie1_default_state: pcie1-default-state { 3536 perst-pins { 3537 pins = "gpio97"; 3538 function = "gpio"; 3539 drive-strength = <2>; 3540 bias-pull-down; 3541 }; 3542 3543 clkreq-pins { 3544 pins = "gpio98"; 3545 function = "pcie1_clkreqn"; 3546 drive-strength = <2>; 3547 bias-pull-up; 3548 }; 3549 3550 wake-pins { 3551 pins = "gpio99"; 3552 function = "gpio"; 3553 drive-strength = <2>; 3554 bias-pull-up; 3555 }; 3556 }; 3557 3558 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3559 pins = "gpio0", "gpio1"; 3560 function = "qup0"; 3561 }; 3562 3563 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3564 pins = "gpio4", "gpio5"; 3565 function = "qup1"; 3566 }; 3567 3568 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3569 pins = "gpio8", "gpio9"; 3570 function = "qup2"; 3571 }; 3572 3573 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3574 pins = "gpio12", "gpio13"; 3575 function = "qup3"; 3576 }; 3577 3578 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3579 pins = "gpio16", "gpio17"; 3580 function = "qup4"; 3581 }; 3582 3583 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3584 pins = "gpio206", "gpio207"; 3585 function = "qup5"; 3586 }; 3587 3588 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3589 pins = "gpio20", "gpio21"; 3590 function = "qup6"; 3591 }; 3592 3593 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3594 pins = "gpio28", "gpio29"; 3595 function = "qup8"; 3596 }; 3597 3598 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3599 pins = "gpio32", "gpio33"; 3600 function = "qup9"; 3601 }; 3602 3603 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3604 pins = "gpio36", "gpio37"; 3605 function = "qup10"; 3606 }; 3607 3608 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3609 pins = "gpio40", "gpio41"; 3610 function = "qup11"; 3611 }; 3612 3613 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3614 pins = "gpio44", "gpio45"; 3615 function = "qup12"; 3616 }; 3617 3618 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3619 pins = "gpio48", "gpio49"; 3620 function = "qup13"; 3621 drive-strength = <2>; 3622 bias-pull-up; 3623 }; 3624 3625 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3626 pins = "gpio52", "gpio53"; 3627 function = "qup14"; 3628 drive-strength = <2>; 3629 bias-pull-up; 3630 }; 3631 3632 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3633 pins = "gpio56", "gpio57"; 3634 function = "qup15"; 3635 }; 3636 3637 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 3638 pins = "gpio60", "gpio61"; 3639 function = "qup16"; 3640 }; 3641 3642 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 3643 pins = "gpio64", "gpio65"; 3644 function = "qup17"; 3645 }; 3646 3647 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 3648 pins = "gpio68", "gpio69"; 3649 function = "qup18"; 3650 }; 3651 3652 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 3653 pins = "gpio72", "gpio73"; 3654 function = "qup19"; 3655 }; 3656 3657 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 3658 pins = "gpio76", "gpio77"; 3659 function = "qup20"; 3660 }; 3661 3662 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 3663 pins = "gpio80", "gpio81"; 3664 function = "qup21"; 3665 }; 3666 3667 qup_spi0_cs: qup-spi0-cs-state { 3668 pins = "gpio3"; 3669 function = "qup0"; 3670 }; 3671 3672 qup_spi0_data_clk: qup-spi0-data-clk-state { 3673 pins = "gpio0", "gpio1", "gpio2"; 3674 function = "qup0"; 3675 }; 3676 3677 qup_spi1_cs: qup-spi1-cs-state { 3678 pins = "gpio7"; 3679 function = "qup1"; 3680 }; 3681 3682 qup_spi1_data_clk: qup-spi1-data-clk-state { 3683 pins = "gpio4", "gpio5", "gpio6"; 3684 function = "qup1"; 3685 }; 3686 3687 qup_spi2_cs: qup-spi2-cs-state { 3688 pins = "gpio11"; 3689 function = "qup2"; 3690 }; 3691 3692 qup_spi2_data_clk: qup-spi2-data-clk-state { 3693 pins = "gpio8", "gpio9", "gpio10"; 3694 function = "qup2"; 3695 }; 3696 3697 qup_spi3_cs: qup-spi3-cs-state { 3698 pins = "gpio15"; 3699 function = "qup3"; 3700 }; 3701 3702 qup_spi3_data_clk: qup-spi3-data-clk-state { 3703 pins = "gpio12", "gpio13", "gpio14"; 3704 function = "qup3"; 3705 }; 3706 3707 qup_spi4_cs: qup-spi4-cs-state { 3708 pins = "gpio19"; 3709 function = "qup4"; 3710 drive-strength = <6>; 3711 bias-disable; 3712 }; 3713 3714 qup_spi4_data_clk: qup-spi4-data-clk-state { 3715 pins = "gpio16", "gpio17", "gpio18"; 3716 function = "qup4"; 3717 }; 3718 3719 qup_spi5_cs: qup-spi5-cs-state { 3720 pins = "gpio85"; 3721 function = "qup5"; 3722 }; 3723 3724 qup_spi5_data_clk: qup-spi5-data-clk-state { 3725 pins = "gpio206", "gpio207", "gpio84"; 3726 function = "qup5"; 3727 }; 3728 3729 qup_spi6_cs: qup-spi6-cs-state { 3730 pins = "gpio23"; 3731 function = "qup6"; 3732 }; 3733 3734 qup_spi6_data_clk: qup-spi6-data-clk-state { 3735 pins = "gpio20", "gpio21", "gpio22"; 3736 function = "qup6"; 3737 }; 3738 3739 qup_spi8_cs: qup-spi8-cs-state { 3740 pins = "gpio31"; 3741 function = "qup8"; 3742 }; 3743 3744 qup_spi8_data_clk: qup-spi8-data-clk-state { 3745 pins = "gpio28", "gpio29", "gpio30"; 3746 function = "qup8"; 3747 }; 3748 3749 qup_spi9_cs: qup-spi9-cs-state { 3750 pins = "gpio35"; 3751 function = "qup9"; 3752 }; 3753 3754 qup_spi9_data_clk: qup-spi9-data-clk-state { 3755 pins = "gpio32", "gpio33", "gpio34"; 3756 function = "qup9"; 3757 }; 3758 3759 qup_spi10_cs: qup-spi10-cs-state { 3760 pins = "gpio39"; 3761 function = "qup10"; 3762 }; 3763 3764 qup_spi10_data_clk: qup-spi10-data-clk-state { 3765 pins = "gpio36", "gpio37", "gpio38"; 3766 function = "qup10"; 3767 }; 3768 3769 qup_spi11_cs: qup-spi11-cs-state { 3770 pins = "gpio43"; 3771 function = "qup11"; 3772 }; 3773 3774 qup_spi11_data_clk: qup-spi11-data-clk-state { 3775 pins = "gpio40", "gpio41", "gpio42"; 3776 function = "qup11"; 3777 }; 3778 3779 qup_spi12_cs: qup-spi12-cs-state { 3780 pins = "gpio47"; 3781 function = "qup12"; 3782 }; 3783 3784 qup_spi12_data_clk: qup-spi12-data-clk-state { 3785 pins = "gpio44", "gpio45", "gpio46"; 3786 function = "qup12"; 3787 }; 3788 3789 qup_spi13_cs: qup-spi13-cs-state { 3790 pins = "gpio51"; 3791 function = "qup13"; 3792 }; 3793 3794 qup_spi13_data_clk: qup-spi13-data-clk-state { 3795 pins = "gpio48", "gpio49", "gpio50"; 3796 function = "qup13"; 3797 }; 3798 3799 qup_spi14_cs: qup-spi14-cs-state { 3800 pins = "gpio55"; 3801 function = "qup14"; 3802 }; 3803 3804 qup_spi14_data_clk: qup-spi14-data-clk-state { 3805 pins = "gpio52", "gpio53", "gpio54"; 3806 function = "qup14"; 3807 }; 3808 3809 qup_spi15_cs: qup-spi15-cs-state { 3810 pins = "gpio59"; 3811 function = "qup15"; 3812 }; 3813 3814 qup_spi15_data_clk: qup-spi15-data-clk-state { 3815 pins = "gpio56", "gpio57", "gpio58"; 3816 function = "qup15"; 3817 }; 3818 3819 qup_spi16_cs: qup-spi16-cs-state { 3820 pins = "gpio63"; 3821 function = "qup16"; 3822 }; 3823 3824 qup_spi16_data_clk: qup-spi16-data-clk-state { 3825 pins = "gpio60", "gpio61", "gpio62"; 3826 function = "qup16"; 3827 }; 3828 3829 qup_spi17_cs: qup-spi17-cs-state { 3830 pins = "gpio67"; 3831 function = "qup17"; 3832 }; 3833 3834 qup_spi17_data_clk: qup-spi17-data-clk-state { 3835 pins = "gpio64", "gpio65", "gpio66"; 3836 function = "qup17"; 3837 }; 3838 3839 qup_spi18_cs: qup-spi18-cs-state { 3840 pins = "gpio71"; 3841 function = "qup18"; 3842 drive-strength = <6>; 3843 bias-disable; 3844 }; 3845 3846 qup_spi18_data_clk: qup-spi18-data-clk-state { 3847 pins = "gpio68", "gpio69", "gpio70"; 3848 function = "qup18"; 3849 drive-strength = <6>; 3850 bias-disable; 3851 }; 3852 3853 qup_spi19_cs: qup-spi19-cs-state { 3854 pins = "gpio75"; 3855 function = "qup19"; 3856 drive-strength = <6>; 3857 bias-disable; 3858 }; 3859 3860 qup_spi19_data_clk: qup-spi19-data-clk-state { 3861 pins = "gpio72", "gpio73", "gpio74"; 3862 function = "qup19"; 3863 drive-strength = <6>; 3864 bias-disable; 3865 }; 3866 3867 qup_spi20_cs: qup-spi20-cs-state { 3868 pins = "gpio79"; 3869 function = "qup20"; 3870 }; 3871 3872 qup_spi20_data_clk: qup-spi20-data-clk-state { 3873 pins = "gpio76", "gpio77", "gpio78"; 3874 function = "qup20"; 3875 }; 3876 3877 qup_spi21_cs: qup-spi21-cs-state { 3878 pins = "gpio83"; 3879 function = "qup21"; 3880 }; 3881 3882 qup_spi21_data_clk: qup-spi21-data-clk-state { 3883 pins = "gpio80", "gpio81", "gpio82"; 3884 function = "qup21"; 3885 }; 3886 3887 qup_uart7_rx: qup-uart7-rx-state { 3888 pins = "gpio26"; 3889 function = "qup7"; 3890 drive-strength = <2>; 3891 bias-disable; 3892 }; 3893 3894 qup_uart7_tx: qup-uart7-tx-state { 3895 pins = "gpio27"; 3896 function = "qup7"; 3897 drive-strength = <2>; 3898 bias-disable; 3899 }; 3900 3901 qup_uart20_default: qup-uart20-default-state { 3902 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 3903 function = "qup20"; 3904 }; 3905 }; 3906 3907 lpass_tlmm: pinctrl@3440000 { 3908 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 3909 reg = <0 0x03440000 0x0 0x20000>, 3910 <0 0x034d0000 0x0 0x10000>; 3911 gpio-controller; 3912 #gpio-cells = <2>; 3913 gpio-ranges = <&lpass_tlmm 0 0 23>; 3914 3915 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3916 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3917 clock-names = "core", "audio"; 3918 3919 tx_swr_active: tx-swr-active-state { 3920 clk-pins { 3921 pins = "gpio0"; 3922 function = "swr_tx_clk"; 3923 drive-strength = <2>; 3924 slew-rate = <1>; 3925 bias-disable; 3926 }; 3927 3928 data-pins { 3929 pins = "gpio1", "gpio2", "gpio14"; 3930 function = "swr_tx_data"; 3931 drive-strength = <2>; 3932 slew-rate = <1>; 3933 bias-bus-hold; 3934 }; 3935 }; 3936 3937 rx_swr_active: rx-swr-active-state { 3938 clk-pins { 3939 pins = "gpio3"; 3940 function = "swr_rx_clk"; 3941 drive-strength = <2>; 3942 slew-rate = <1>; 3943 bias-disable; 3944 }; 3945 3946 data-pins { 3947 pins = "gpio4", "gpio5"; 3948 function = "swr_rx_data"; 3949 drive-strength = <2>; 3950 slew-rate = <1>; 3951 bias-bus-hold; 3952 }; 3953 }; 3954 3955 dmic01_default: dmic01-default-state { 3956 clk-pins { 3957 pins = "gpio6"; 3958 function = "dmic1_clk"; 3959 drive-strength = <8>; 3960 output-high; 3961 }; 3962 3963 data-pins { 3964 pins = "gpio7"; 3965 function = "dmic1_data"; 3966 drive-strength = <8>; 3967 }; 3968 }; 3969 3970 dmic23_default: dmic23-default-state { 3971 clk-pins { 3972 pins = "gpio8"; 3973 function = "dmic2_clk"; 3974 drive-strength = <8>; 3975 output-high; 3976 }; 3977 3978 data-pins { 3979 pins = "gpio9"; 3980 function = "dmic2_data"; 3981 drive-strength = <8>; 3982 }; 3983 }; 3984 3985 wsa_swr_active: wsa-swr-active-state { 3986 clk-pins { 3987 pins = "gpio10"; 3988 function = "wsa_swr_clk"; 3989 drive-strength = <2>; 3990 slew-rate = <1>; 3991 bias-disable; 3992 }; 3993 3994 data-pins { 3995 pins = "gpio11"; 3996 function = "wsa_swr_data"; 3997 drive-strength = <2>; 3998 slew-rate = <1>; 3999 bias-bus-hold; 4000 }; 4001 }; 4002 4003 wsa2_swr_active: wsa2-swr-active-state { 4004 clk-pins { 4005 pins = "gpio15"; 4006 function = "wsa2_swr_clk"; 4007 drive-strength = <2>; 4008 slew-rate = <1>; 4009 bias-disable; 4010 }; 4011 4012 data-pins { 4013 pins = "gpio16"; 4014 function = "wsa2_swr_data"; 4015 drive-strength = <2>; 4016 slew-rate = <1>; 4017 bias-bus-hold; 4018 }; 4019 }; 4020 }; 4021 4022 sram@146aa000 { 4023 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; 4024 reg = <0 0x146aa000 0 0x1000>; 4025 ranges = <0 0 0x146aa000 0x1000>; 4026 4027 #address-cells = <1>; 4028 #size-cells = <1>; 4029 4030 pil-reloc@94c { 4031 compatible = "qcom,pil-reloc-info"; 4032 reg = <0x94c 0xc8>; 4033 }; 4034 }; 4035 4036 apps_smmu: iommu@15000000 { 4037 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 4038 reg = <0 0x15000000 0 0x100000>; 4039 #iommu-cells = <2>; 4040 #global-interrupts = <1>; 4041 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4042 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4043 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4044 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4045 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4046 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4047 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4048 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4049 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4050 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4051 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4054 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4055 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4056 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4057 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4067 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4129 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4130 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 4138 }; 4139 4140 intc: interrupt-controller@17100000 { 4141 compatible = "arm,gic-v3"; 4142 #interrupt-cells = <3>; 4143 interrupt-controller; 4144 #redistributor-regions = <1>; 4145 redistributor-stride = <0x0 0x40000>; 4146 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 4147 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 4148 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4149 #address-cells = <2>; 4150 #size-cells = <2>; 4151 ranges; 4152 4153 gic_its: msi-controller@17140000 { 4154 compatible = "arm,gic-v3-its"; 4155 reg = <0x0 0x17140000 0x0 0x20000>; 4156 msi-controller; 4157 #msi-cells = <1>; 4158 }; 4159 }; 4160 4161 timer@17420000 { 4162 compatible = "arm,armv7-timer-mem"; 4163 #address-cells = <1>; 4164 #size-cells = <1>; 4165 ranges = <0 0 0 0x20000000>; 4166 reg = <0x0 0x17420000 0x0 0x1000>; 4167 clock-frequency = <19200000>; 4168 4169 frame@17421000 { 4170 frame-number = <0>; 4171 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4172 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4173 reg = <0x17421000 0x1000>, 4174 <0x17422000 0x1000>; 4175 }; 4176 4177 frame@17423000 { 4178 frame-number = <1>; 4179 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4180 reg = <0x17423000 0x1000>; 4181 status = "disabled"; 4182 }; 4183 4184 frame@17425000 { 4185 frame-number = <2>; 4186 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4187 reg = <0x17425000 0x1000>; 4188 status = "disabled"; 4189 }; 4190 4191 frame@17427000 { 4192 frame-number = <3>; 4193 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4194 reg = <0x17427000 0x1000>; 4195 status = "disabled"; 4196 }; 4197 4198 frame@17429000 { 4199 frame-number = <4>; 4200 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4201 reg = <0x17429000 0x1000>; 4202 status = "disabled"; 4203 }; 4204 4205 frame@1742b000 { 4206 frame-number = <5>; 4207 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4208 reg = <0x1742b000 0x1000>; 4209 status = "disabled"; 4210 }; 4211 4212 frame@1742d000 { 4213 frame-number = <6>; 4214 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4215 reg = <0x1742d000 0x1000>; 4216 status = "disabled"; 4217 }; 4218 }; 4219 4220 apps_rsc: rsc@17a00000 { 4221 label = "apps_rsc"; 4222 compatible = "qcom,rpmh-rsc"; 4223 reg = <0x0 0x17a00000 0x0 0x10000>, 4224 <0x0 0x17a10000 0x0 0x10000>, 4225 <0x0 0x17a20000 0x0 0x10000>, 4226 <0x0 0x17a30000 0x0 0x10000>; 4227 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 4228 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4229 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4230 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4231 qcom,tcs-offset = <0xd00>; 4232 qcom,drv-id = <2>; 4233 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4234 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4235 power-domains = <&CLUSTER_PD>; 4236 4237 apps_bcm_voter: bcm-voter { 4238 compatible = "qcom,bcm-voter"; 4239 }; 4240 4241 rpmhcc: clock-controller { 4242 compatible = "qcom,sm8450-rpmh-clk"; 4243 #clock-cells = <1>; 4244 clock-names = "xo"; 4245 clocks = <&xo_board>; 4246 }; 4247 4248 rpmhpd: power-controller { 4249 compatible = "qcom,sm8450-rpmhpd"; 4250 #power-domain-cells = <1>; 4251 operating-points-v2 = <&rpmhpd_opp_table>; 4252 4253 rpmhpd_opp_table: opp-table { 4254 compatible = "operating-points-v2"; 4255 4256 rpmhpd_opp_ret: opp1 { 4257 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4258 }; 4259 4260 rpmhpd_opp_min_svs: opp2 { 4261 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4262 }; 4263 4264 rpmhpd_opp_low_svs_d1: opp3 { 4265 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4266 }; 4267 4268 rpmhpd_opp_low_svs: opp4 { 4269 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4270 }; 4271 4272 rpmhpd_opp_low_svs_l1: opp5 { 4273 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4274 }; 4275 4276 rpmhpd_opp_svs: opp6 { 4277 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4278 }; 4279 4280 rpmhpd_opp_svs_l0: opp7 { 4281 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4282 }; 4283 4284 rpmhpd_opp_svs_l1: opp8 { 4285 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4286 }; 4287 4288 rpmhpd_opp_svs_l2: opp9 { 4289 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4290 }; 4291 4292 rpmhpd_opp_nom: opp10 { 4293 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4294 }; 4295 4296 rpmhpd_opp_nom_l1: opp11 { 4297 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4298 }; 4299 4300 rpmhpd_opp_nom_l2: opp12 { 4301 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4302 }; 4303 4304 rpmhpd_opp_turbo: opp13 { 4305 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4306 }; 4307 4308 rpmhpd_opp_turbo_l1: opp14 { 4309 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4310 }; 4311 }; 4312 }; 4313 }; 4314 4315 cpufreq_hw: cpufreq@17d91000 { 4316 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 4317 reg = <0 0x17d91000 0 0x1000>, 4318 <0 0x17d92000 0 0x1000>, 4319 <0 0x17d93000 0 0x1000>; 4320 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4321 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4322 clock-names = "xo", "alternate"; 4323 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4324 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4325 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4326 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4327 #freq-domain-cells = <1>; 4328 #clock-cells = <1>; 4329 }; 4330 4331 gem_noc: interconnect@19100000 { 4332 compatible = "qcom,sm8450-gem-noc"; 4333 reg = <0 0x19100000 0 0xbb800>; 4334 #interconnect-cells = <2>; 4335 qcom,bcm-voters = <&apps_bcm_voter>; 4336 }; 4337 4338 system-cache-controller@19200000 { 4339 compatible = "qcom,sm8450-llcc"; 4340 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, 4341 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, 4342 <0 0x19a00000 0 0x80000>; 4343 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4344 "llcc3_base", "llcc_broadcast_base"; 4345 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4346 }; 4347 4348 ufs_mem_hc: ufshc@1d84000 { 4349 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 4350 "jedec,ufs-2.0"; 4351 reg = <0 0x01d84000 0 0x3000>; 4352 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 4353 phys = <&ufs_mem_phy>; 4354 phy-names = "ufsphy"; 4355 lanes-per-direction = <2>; 4356 #reset-cells = <1>; 4357 resets = <&gcc GCC_UFS_PHY_BCR>; 4358 reset-names = "rst"; 4359 4360 power-domains = <&gcc UFS_PHY_GDSC>; 4361 4362 iommus = <&apps_smmu 0xe0 0x0>; 4363 dma-coherent; 4364 4365 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 4366 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 4367 interconnect-names = "ufs-ddr", "cpu-ufs"; 4368 clock-names = 4369 "core_clk", 4370 "bus_aggr_clk", 4371 "iface_clk", 4372 "core_clk_unipro", 4373 "ref_clk", 4374 "tx_lane0_sync_clk", 4375 "rx_lane0_sync_clk", 4376 "rx_lane1_sync_clk"; 4377 clocks = 4378 <&gcc GCC_UFS_PHY_AXI_CLK>, 4379 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 4380 <&gcc GCC_UFS_PHY_AHB_CLK>, 4381 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 4382 <&rpmhcc RPMH_CXO_CLK>, 4383 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 4384 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 4385 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 4386 freq-table-hz = 4387 <75000000 300000000>, 4388 <0 0>, 4389 <0 0>, 4390 <75000000 300000000>, 4391 <75000000 300000000>, 4392 <0 0>, 4393 <0 0>, 4394 <0 0>; 4395 qcom,ice = <&ice>; 4396 4397 status = "disabled"; 4398 }; 4399 4400 ufs_mem_phy: phy@1d87000 { 4401 compatible = "qcom,sm8450-qmp-ufs-phy"; 4402 reg = <0 0x01d87000 0 0x1000>; 4403 4404 clock-names = "ref", "ref_aux", "qref"; 4405 clocks = <&rpmhcc RPMH_CXO_CLK>, 4406 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 4407 <&gcc GCC_UFS_0_CLKREF_EN>; 4408 4409 resets = <&ufs_mem_hc 0>; 4410 reset-names = "ufsphy"; 4411 4412 #clock-cells = <1>; 4413 #phy-cells = <0>; 4414 4415 status = "disabled"; 4416 }; 4417 4418 ice: crypto@1d88000 { 4419 compatible = "qcom,sm8450-inline-crypto-engine", 4420 "qcom,inline-crypto-engine"; 4421 reg = <0 0x01d88000 0 0x8000>; 4422 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4423 }; 4424 4425 cryptobam: dma-controller@1dc4000 { 4426 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 4427 reg = <0 0x01dc4000 0 0x28000>; 4428 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 4429 #dma-cells = <1>; 4430 qcom,ee = <0>; 4431 qcom,controlled-remotely; 4432 iommus = <&apps_smmu 0x584 0x11>, 4433 <&apps_smmu 0x588 0x0>, 4434 <&apps_smmu 0x598 0x5>, 4435 <&apps_smmu 0x59a 0x0>, 4436 <&apps_smmu 0x59f 0x0>; 4437 }; 4438 4439 crypto: crypto@1dfa000 { 4440 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; 4441 reg = <0 0x01dfa000 0 0x6000>; 4442 dmas = <&cryptobam 4>, <&cryptobam 5>; 4443 dma-names = "rx", "tx"; 4444 iommus = <&apps_smmu 0x584 0x11>, 4445 <&apps_smmu 0x588 0x0>, 4446 <&apps_smmu 0x598 0x5>, 4447 <&apps_smmu 0x59a 0x0>, 4448 <&apps_smmu 0x59f 0x0>; 4449 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 4450 interconnect-names = "memory"; 4451 }; 4452 4453 sdhc_2: mmc@8804000 { 4454 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 4455 reg = <0 0x08804000 0 0x1000>; 4456 4457 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4458 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4459 interrupt-names = "hc_irq", "pwr_irq"; 4460 4461 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4462 <&gcc GCC_SDCC2_APPS_CLK>, 4463 <&rpmhcc RPMH_CXO_CLK>; 4464 clock-names = "iface", "core", "xo"; 4465 resets = <&gcc GCC_SDCC2_BCR>; 4466 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4467 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 4468 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4469 iommus = <&apps_smmu 0x4a0 0x0>; 4470 power-domains = <&rpmhpd RPMHPD_CX>; 4471 operating-points-v2 = <&sdhc2_opp_table>; 4472 bus-width = <4>; 4473 dma-coherent; 4474 4475 /* Forbid SDR104/SDR50 - broken hw! */ 4476 sdhci-caps-mask = <0x3 0x0>; 4477 4478 status = "disabled"; 4479 4480 sdhc2_opp_table: opp-table { 4481 compatible = "operating-points-v2"; 4482 4483 opp-100000000 { 4484 opp-hz = /bits/ 64 <100000000>; 4485 required-opps = <&rpmhpd_opp_low_svs>; 4486 }; 4487 4488 opp-202000000 { 4489 opp-hz = /bits/ 64 <202000000>; 4490 required-opps = <&rpmhpd_opp_svs_l1>; 4491 }; 4492 }; 4493 }; 4494 4495 usb_1: usb@a6f8800 { 4496 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 4497 reg = <0 0x0a6f8800 0 0x400>; 4498 status = "disabled"; 4499 #address-cells = <2>; 4500 #size-cells = <2>; 4501 ranges; 4502 4503 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4504 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4505 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4506 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4507 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4508 <&gcc GCC_USB3_0_CLKREF_EN>; 4509 clock-names = "cfg_noc", 4510 "core", 4511 "iface", 4512 "sleep", 4513 "mock_utmi", 4514 "xo"; 4515 4516 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4517 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4518 assigned-clock-rates = <19200000>, <200000000>; 4519 4520 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4521 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4522 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4523 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4524 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4525 interrupt-names = "pwr_event", 4526 "hs_phy_irq", 4527 "dp_hs_phy_irq", 4528 "dm_hs_phy_irq", 4529 "ss_phy_irq"; 4530 4531 power-domains = <&gcc USB30_PRIM_GDSC>; 4532 4533 resets = <&gcc GCC_USB30_PRIM_BCR>; 4534 4535 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4536 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4537 interconnect-names = "usb-ddr", "apps-usb"; 4538 4539 usb_1_dwc3: usb@a600000 { 4540 compatible = "snps,dwc3"; 4541 reg = <0 0x0a600000 0 0xcd00>; 4542 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4543 iommus = <&apps_smmu 0x0 0x0>; 4544 snps,dis_u2_susphy_quirk; 4545 snps,dis_enblslpm_quirk; 4546 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4547 phy-names = "usb2-phy", "usb3-phy"; 4548 4549 ports { 4550 #address-cells = <1>; 4551 #size-cells = <0>; 4552 4553 port@0 { 4554 reg = <0>; 4555 4556 usb_1_dwc3_hs: endpoint { 4557 }; 4558 }; 4559 4560 port@1 { 4561 reg = <1>; 4562 4563 usb_1_dwc3_ss: endpoint { 4564 }; 4565 }; 4566 }; 4567 }; 4568 }; 4569 4570 nsp_noc: interconnect@320c0000 { 4571 compatible = "qcom,sm8450-nsp-noc"; 4572 reg = <0 0x320c0000 0 0x10000>; 4573 #interconnect-cells = <2>; 4574 qcom,bcm-voters = <&apps_bcm_voter>; 4575 }; 4576 4577 lpass_ag_noc: interconnect@3c40000 { 4578 compatible = "qcom,sm8450-lpass-ag-noc"; 4579 reg = <0 0x03c40000 0 0x17200>; 4580 #interconnect-cells = <2>; 4581 qcom,bcm-voters = <&apps_bcm_voter>; 4582 }; 4583 }; 4584 4585 sound: sound { 4586 }; 4587 4588 thermal-zones { 4589 aoss0-thermal { 4590 polling-delay-passive = <0>; 4591 polling-delay = <0>; 4592 thermal-sensors = <&tsens0 0>; 4593 4594 trips { 4595 thermal-engine-config { 4596 temperature = <125000>; 4597 hysteresis = <1000>; 4598 type = "passive"; 4599 }; 4600 4601 reset-mon-cfg { 4602 temperature = <115000>; 4603 hysteresis = <5000>; 4604 type = "passive"; 4605 }; 4606 }; 4607 }; 4608 4609 cpuss0-thermal { 4610 polling-delay-passive = <0>; 4611 polling-delay = <0>; 4612 thermal-sensors = <&tsens0 1>; 4613 4614 trips { 4615 thermal-engine-config { 4616 temperature = <125000>; 4617 hysteresis = <1000>; 4618 type = "passive"; 4619 }; 4620 4621 reset-mon-cfg { 4622 temperature = <115000>; 4623 hysteresis = <5000>; 4624 type = "passive"; 4625 }; 4626 }; 4627 }; 4628 4629 cpuss1-thermal { 4630 polling-delay-passive = <0>; 4631 polling-delay = <0>; 4632 thermal-sensors = <&tsens0 2>; 4633 4634 trips { 4635 thermal-engine-config { 4636 temperature = <125000>; 4637 hysteresis = <1000>; 4638 type = "passive"; 4639 }; 4640 4641 reset-mon-cfg { 4642 temperature = <115000>; 4643 hysteresis = <5000>; 4644 type = "passive"; 4645 }; 4646 }; 4647 }; 4648 4649 cpuss3-thermal { 4650 polling-delay-passive = <0>; 4651 polling-delay = <0>; 4652 thermal-sensors = <&tsens0 3>; 4653 4654 trips { 4655 thermal-engine-config { 4656 temperature = <125000>; 4657 hysteresis = <1000>; 4658 type = "passive"; 4659 }; 4660 4661 reset-mon-cfg { 4662 temperature = <115000>; 4663 hysteresis = <5000>; 4664 type = "passive"; 4665 }; 4666 }; 4667 }; 4668 4669 cpuss4-thermal { 4670 polling-delay-passive = <0>; 4671 polling-delay = <0>; 4672 thermal-sensors = <&tsens0 4>; 4673 4674 trips { 4675 thermal-engine-config { 4676 temperature = <125000>; 4677 hysteresis = <1000>; 4678 type = "passive"; 4679 }; 4680 4681 reset-mon-cfg { 4682 temperature = <115000>; 4683 hysteresis = <5000>; 4684 type = "passive"; 4685 }; 4686 }; 4687 }; 4688 4689 cpu4-top-thermal { 4690 polling-delay-passive = <0>; 4691 polling-delay = <0>; 4692 thermal-sensors = <&tsens0 5>; 4693 4694 trips { 4695 cpu4_top_alert0: trip-point0 { 4696 temperature = <90000>; 4697 hysteresis = <2000>; 4698 type = "passive"; 4699 }; 4700 4701 cpu4_top_alert1: trip-point1 { 4702 temperature = <95000>; 4703 hysteresis = <2000>; 4704 type = "passive"; 4705 }; 4706 4707 cpu4_top_crit: cpu-crit { 4708 temperature = <110000>; 4709 hysteresis = <1000>; 4710 type = "critical"; 4711 }; 4712 }; 4713 }; 4714 4715 cpu4-bottom-thermal { 4716 polling-delay-passive = <0>; 4717 polling-delay = <0>; 4718 thermal-sensors = <&tsens0 6>; 4719 4720 trips { 4721 cpu4_bottom_alert0: trip-point0 { 4722 temperature = <90000>; 4723 hysteresis = <2000>; 4724 type = "passive"; 4725 }; 4726 4727 cpu4_bottom_alert1: trip-point1 { 4728 temperature = <95000>; 4729 hysteresis = <2000>; 4730 type = "passive"; 4731 }; 4732 4733 cpu4_bottom_crit: cpu-crit { 4734 temperature = <110000>; 4735 hysteresis = <1000>; 4736 type = "critical"; 4737 }; 4738 }; 4739 }; 4740 4741 cpu5-top-thermal { 4742 polling-delay-passive = <0>; 4743 polling-delay = <0>; 4744 thermal-sensors = <&tsens0 7>; 4745 4746 trips { 4747 cpu5_top_alert0: trip-point0 { 4748 temperature = <90000>; 4749 hysteresis = <2000>; 4750 type = "passive"; 4751 }; 4752 4753 cpu5_top_alert1: trip-point1 { 4754 temperature = <95000>; 4755 hysteresis = <2000>; 4756 type = "passive"; 4757 }; 4758 4759 cpu5_top_crit: cpu-crit { 4760 temperature = <110000>; 4761 hysteresis = <1000>; 4762 type = "critical"; 4763 }; 4764 }; 4765 }; 4766 4767 cpu5-bottom-thermal { 4768 polling-delay-passive = <0>; 4769 polling-delay = <0>; 4770 thermal-sensors = <&tsens0 8>; 4771 4772 trips { 4773 cpu5_bottom_alert0: trip-point0 { 4774 temperature = <90000>; 4775 hysteresis = <2000>; 4776 type = "passive"; 4777 }; 4778 4779 cpu5_bottom_alert1: trip-point1 { 4780 temperature = <95000>; 4781 hysteresis = <2000>; 4782 type = "passive"; 4783 }; 4784 4785 cpu5_bottom_crit: cpu-crit { 4786 temperature = <110000>; 4787 hysteresis = <1000>; 4788 type = "critical"; 4789 }; 4790 }; 4791 }; 4792 4793 cpu6-top-thermal { 4794 polling-delay-passive = <0>; 4795 polling-delay = <0>; 4796 thermal-sensors = <&tsens0 9>; 4797 4798 trips { 4799 cpu6_top_alert0: trip-point0 { 4800 temperature = <90000>; 4801 hysteresis = <2000>; 4802 type = "passive"; 4803 }; 4804 4805 cpu6_top_alert1: trip-point1 { 4806 temperature = <95000>; 4807 hysteresis = <2000>; 4808 type = "passive"; 4809 }; 4810 4811 cpu6_top_crit: cpu-crit { 4812 temperature = <110000>; 4813 hysteresis = <1000>; 4814 type = "critical"; 4815 }; 4816 }; 4817 }; 4818 4819 cpu6-bottom-thermal { 4820 polling-delay-passive = <0>; 4821 polling-delay = <0>; 4822 thermal-sensors = <&tsens0 10>; 4823 4824 trips { 4825 cpu6_bottom_alert0: trip-point0 { 4826 temperature = <90000>; 4827 hysteresis = <2000>; 4828 type = "passive"; 4829 }; 4830 4831 cpu6_bottom_alert1: trip-point1 { 4832 temperature = <95000>; 4833 hysteresis = <2000>; 4834 type = "passive"; 4835 }; 4836 4837 cpu6_bottom_crit: cpu-crit { 4838 temperature = <110000>; 4839 hysteresis = <1000>; 4840 type = "critical"; 4841 }; 4842 }; 4843 }; 4844 4845 cpu7-top-thermal { 4846 polling-delay-passive = <0>; 4847 polling-delay = <0>; 4848 thermal-sensors = <&tsens0 11>; 4849 4850 trips { 4851 cpu7_top_alert0: trip-point0 { 4852 temperature = <90000>; 4853 hysteresis = <2000>; 4854 type = "passive"; 4855 }; 4856 4857 cpu7_top_alert1: trip-point1 { 4858 temperature = <95000>; 4859 hysteresis = <2000>; 4860 type = "passive"; 4861 }; 4862 4863 cpu7_top_crit: cpu-crit { 4864 temperature = <110000>; 4865 hysteresis = <1000>; 4866 type = "critical"; 4867 }; 4868 }; 4869 }; 4870 4871 cpu7-middle-thermal { 4872 polling-delay-passive = <0>; 4873 polling-delay = <0>; 4874 thermal-sensors = <&tsens0 12>; 4875 4876 trips { 4877 cpu7_middle_alert0: trip-point0 { 4878 temperature = <90000>; 4879 hysteresis = <2000>; 4880 type = "passive"; 4881 }; 4882 4883 cpu7_middle_alert1: trip-point1 { 4884 temperature = <95000>; 4885 hysteresis = <2000>; 4886 type = "passive"; 4887 }; 4888 4889 cpu7_middle_crit: cpu-crit { 4890 temperature = <110000>; 4891 hysteresis = <1000>; 4892 type = "critical"; 4893 }; 4894 }; 4895 }; 4896 4897 cpu7-bottom-thermal { 4898 polling-delay-passive = <0>; 4899 polling-delay = <0>; 4900 thermal-sensors = <&tsens0 13>; 4901 4902 trips { 4903 cpu7_bottom_alert0: trip-point0 { 4904 temperature = <90000>; 4905 hysteresis = <2000>; 4906 type = "passive"; 4907 }; 4908 4909 cpu7_bottom_alert1: trip-point1 { 4910 temperature = <95000>; 4911 hysteresis = <2000>; 4912 type = "passive"; 4913 }; 4914 4915 cpu7_bottom_crit: cpu-crit { 4916 temperature = <110000>; 4917 hysteresis = <1000>; 4918 type = "critical"; 4919 }; 4920 }; 4921 }; 4922 4923 gpu-top-thermal { 4924 polling-delay-passive = <10>; 4925 polling-delay = <0>; 4926 thermal-sensors = <&tsens0 14>; 4927 4928 cooling-maps { 4929 map0 { 4930 trip = <&gpu_top_alert0>; 4931 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4932 }; 4933 }; 4934 4935 trips { 4936 thermal-engine-config { 4937 temperature = <125000>; 4938 hysteresis = <1000>; 4939 type = "passive"; 4940 }; 4941 4942 thermal-hal-config { 4943 temperature = <125000>; 4944 hysteresis = <1000>; 4945 type = "passive"; 4946 }; 4947 4948 reset-mon-cfg { 4949 temperature = <115000>; 4950 hysteresis = <5000>; 4951 type = "passive"; 4952 }; 4953 4954 gpu_top_alert0: trip-point0 { 4955 temperature = <95000>; 4956 hysteresis = <5000>; 4957 type = "passive"; 4958 }; 4959 }; 4960 }; 4961 4962 gpu-bottom-thermal { 4963 polling-delay-passive = <10>; 4964 polling-delay = <0>; 4965 thermal-sensors = <&tsens0 15>; 4966 4967 cooling-maps { 4968 map0 { 4969 trip = <&gpu_bottom_alert0>; 4970 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4971 }; 4972 }; 4973 4974 trips { 4975 thermal-engine-config { 4976 temperature = <125000>; 4977 hysteresis = <1000>; 4978 type = "passive"; 4979 }; 4980 4981 thermal-hal-config { 4982 temperature = <125000>; 4983 hysteresis = <1000>; 4984 type = "passive"; 4985 }; 4986 4987 reset-mon-cfg { 4988 temperature = <115000>; 4989 hysteresis = <5000>; 4990 type = "passive"; 4991 }; 4992 4993 gpu_bottom_alert0: trip-point0 { 4994 temperature = <95000>; 4995 hysteresis = <5000>; 4996 type = "passive"; 4997 }; 4998 }; 4999 }; 5000 5001 aoss1-thermal { 5002 polling-delay-passive = <0>; 5003 polling-delay = <0>; 5004 thermal-sensors = <&tsens1 0>; 5005 5006 trips { 5007 thermal-engine-config { 5008 temperature = <125000>; 5009 hysteresis = <1000>; 5010 type = "passive"; 5011 }; 5012 5013 reset-mon-cfg { 5014 temperature = <115000>; 5015 hysteresis = <5000>; 5016 type = "passive"; 5017 }; 5018 }; 5019 }; 5020 5021 cpu0-thermal { 5022 polling-delay-passive = <0>; 5023 polling-delay = <0>; 5024 thermal-sensors = <&tsens1 1>; 5025 5026 trips { 5027 cpu0_alert0: trip-point0 { 5028 temperature = <90000>; 5029 hysteresis = <2000>; 5030 type = "passive"; 5031 }; 5032 5033 cpu0_alert1: trip-point1 { 5034 temperature = <95000>; 5035 hysteresis = <2000>; 5036 type = "passive"; 5037 }; 5038 5039 cpu0_crit: cpu-crit { 5040 temperature = <110000>; 5041 hysteresis = <1000>; 5042 type = "critical"; 5043 }; 5044 }; 5045 }; 5046 5047 cpu1-thermal { 5048 polling-delay-passive = <0>; 5049 polling-delay = <0>; 5050 thermal-sensors = <&tsens1 2>; 5051 5052 trips { 5053 cpu1_alert0: trip-point0 { 5054 temperature = <90000>; 5055 hysteresis = <2000>; 5056 type = "passive"; 5057 }; 5058 5059 cpu1_alert1: trip-point1 { 5060 temperature = <95000>; 5061 hysteresis = <2000>; 5062 type = "passive"; 5063 }; 5064 5065 cpu1_crit: cpu-crit { 5066 temperature = <110000>; 5067 hysteresis = <1000>; 5068 type = "critical"; 5069 }; 5070 }; 5071 }; 5072 5073 cpu2-thermal { 5074 polling-delay-passive = <0>; 5075 polling-delay = <0>; 5076 thermal-sensors = <&tsens1 3>; 5077 5078 trips { 5079 cpu2_alert0: trip-point0 { 5080 temperature = <90000>; 5081 hysteresis = <2000>; 5082 type = "passive"; 5083 }; 5084 5085 cpu2_alert1: trip-point1 { 5086 temperature = <95000>; 5087 hysteresis = <2000>; 5088 type = "passive"; 5089 }; 5090 5091 cpu2_crit: cpu-crit { 5092 temperature = <110000>; 5093 hysteresis = <1000>; 5094 type = "critical"; 5095 }; 5096 }; 5097 }; 5098 5099 cpu3-thermal { 5100 polling-delay-passive = <0>; 5101 polling-delay = <0>; 5102 thermal-sensors = <&tsens1 4>; 5103 5104 trips { 5105 cpu3_alert0: trip-point0 { 5106 temperature = <90000>; 5107 hysteresis = <2000>; 5108 type = "passive"; 5109 }; 5110 5111 cpu3_alert1: trip-point1 { 5112 temperature = <95000>; 5113 hysteresis = <2000>; 5114 type = "passive"; 5115 }; 5116 5117 cpu3_crit: cpu-crit { 5118 temperature = <110000>; 5119 hysteresis = <1000>; 5120 type = "critical"; 5121 }; 5122 }; 5123 }; 5124 5125 cdsp0-thermal { 5126 polling-delay-passive = <10>; 5127 polling-delay = <0>; 5128 thermal-sensors = <&tsens1 5>; 5129 5130 trips { 5131 thermal-engine-config { 5132 temperature = <125000>; 5133 hysteresis = <1000>; 5134 type = "passive"; 5135 }; 5136 5137 thermal-hal-config { 5138 temperature = <125000>; 5139 hysteresis = <1000>; 5140 type = "passive"; 5141 }; 5142 5143 reset-mon-cfg { 5144 temperature = <115000>; 5145 hysteresis = <5000>; 5146 type = "passive"; 5147 }; 5148 5149 cdsp_0_config: junction-config { 5150 temperature = <95000>; 5151 hysteresis = <5000>; 5152 type = "passive"; 5153 }; 5154 }; 5155 }; 5156 5157 cdsp1-thermal { 5158 polling-delay-passive = <10>; 5159 polling-delay = <0>; 5160 thermal-sensors = <&tsens1 6>; 5161 5162 trips { 5163 thermal-engine-config { 5164 temperature = <125000>; 5165 hysteresis = <1000>; 5166 type = "passive"; 5167 }; 5168 5169 thermal-hal-config { 5170 temperature = <125000>; 5171 hysteresis = <1000>; 5172 type = "passive"; 5173 }; 5174 5175 reset-mon-cfg { 5176 temperature = <115000>; 5177 hysteresis = <5000>; 5178 type = "passive"; 5179 }; 5180 5181 cdsp_1_config: junction-config { 5182 temperature = <95000>; 5183 hysteresis = <5000>; 5184 type = "passive"; 5185 }; 5186 }; 5187 }; 5188 5189 cdsp2-thermal { 5190 polling-delay-passive = <10>; 5191 polling-delay = <0>; 5192 thermal-sensors = <&tsens1 7>; 5193 5194 trips { 5195 thermal-engine-config { 5196 temperature = <125000>; 5197 hysteresis = <1000>; 5198 type = "passive"; 5199 }; 5200 5201 thermal-hal-config { 5202 temperature = <125000>; 5203 hysteresis = <1000>; 5204 type = "passive"; 5205 }; 5206 5207 reset-mon-cfg { 5208 temperature = <115000>; 5209 hysteresis = <5000>; 5210 type = "passive"; 5211 }; 5212 5213 cdsp_2_config: junction-config { 5214 temperature = <95000>; 5215 hysteresis = <5000>; 5216 type = "passive"; 5217 }; 5218 }; 5219 }; 5220 5221 video-thermal { 5222 polling-delay-passive = <0>; 5223 polling-delay = <0>; 5224 thermal-sensors = <&tsens1 8>; 5225 5226 trips { 5227 thermal-engine-config { 5228 temperature = <125000>; 5229 hysteresis = <1000>; 5230 type = "passive"; 5231 }; 5232 5233 reset-mon-cfg { 5234 temperature = <115000>; 5235 hysteresis = <5000>; 5236 type = "passive"; 5237 }; 5238 }; 5239 }; 5240 5241 mem-thermal { 5242 polling-delay-passive = <10>; 5243 polling-delay = <0>; 5244 thermal-sensors = <&tsens1 9>; 5245 5246 trips { 5247 thermal-engine-config { 5248 temperature = <125000>; 5249 hysteresis = <1000>; 5250 type = "passive"; 5251 }; 5252 5253 ddr_config0: ddr0-config { 5254 temperature = <90000>; 5255 hysteresis = <5000>; 5256 type = "passive"; 5257 }; 5258 5259 reset-mon-cfg { 5260 temperature = <115000>; 5261 hysteresis = <5000>; 5262 type = "passive"; 5263 }; 5264 }; 5265 }; 5266 5267 modem0-thermal { 5268 polling-delay-passive = <0>; 5269 polling-delay = <0>; 5270 thermal-sensors = <&tsens1 10>; 5271 5272 trips { 5273 thermal-engine-config { 5274 temperature = <125000>; 5275 hysteresis = <1000>; 5276 type = "passive"; 5277 }; 5278 5279 mdmss0_config0: mdmss0-config0 { 5280 temperature = <102000>; 5281 hysteresis = <3000>; 5282 type = "passive"; 5283 }; 5284 5285 mdmss0_config1: mdmss0-config1 { 5286 temperature = <105000>; 5287 hysteresis = <3000>; 5288 type = "passive"; 5289 }; 5290 5291 reset-mon-cfg { 5292 temperature = <115000>; 5293 hysteresis = <5000>; 5294 type = "passive"; 5295 }; 5296 }; 5297 }; 5298 5299 modem1-thermal { 5300 polling-delay-passive = <0>; 5301 polling-delay = <0>; 5302 thermal-sensors = <&tsens1 11>; 5303 5304 trips { 5305 thermal-engine-config { 5306 temperature = <125000>; 5307 hysteresis = <1000>; 5308 type = "passive"; 5309 }; 5310 5311 mdmss1_config0: mdmss1-config0 { 5312 temperature = <102000>; 5313 hysteresis = <3000>; 5314 type = "passive"; 5315 }; 5316 5317 mdmss1_config1: mdmss1-config1 { 5318 temperature = <105000>; 5319 hysteresis = <3000>; 5320 type = "passive"; 5321 }; 5322 5323 reset-mon-cfg { 5324 temperature = <115000>; 5325 hysteresis = <5000>; 5326 type = "passive"; 5327 }; 5328 }; 5329 }; 5330 5331 modem2-thermal { 5332 polling-delay-passive = <0>; 5333 polling-delay = <0>; 5334 thermal-sensors = <&tsens1 12>; 5335 5336 trips { 5337 thermal-engine-config { 5338 temperature = <125000>; 5339 hysteresis = <1000>; 5340 type = "passive"; 5341 }; 5342 5343 mdmss2_config0: mdmss2-config0 { 5344 temperature = <102000>; 5345 hysteresis = <3000>; 5346 type = "passive"; 5347 }; 5348 5349 mdmss2_config1: mdmss2-config1 { 5350 temperature = <105000>; 5351 hysteresis = <3000>; 5352 type = "passive"; 5353 }; 5354 5355 reset-mon-cfg { 5356 temperature = <115000>; 5357 hysteresis = <5000>; 5358 type = "passive"; 5359 }; 5360 }; 5361 }; 5362 5363 modem3-thermal { 5364 polling-delay-passive = <0>; 5365 polling-delay = <0>; 5366 thermal-sensors = <&tsens1 13>; 5367 5368 trips { 5369 thermal-engine-config { 5370 temperature = <125000>; 5371 hysteresis = <1000>; 5372 type = "passive"; 5373 }; 5374 5375 mdmss3_config0: mdmss3-config0 { 5376 temperature = <102000>; 5377 hysteresis = <3000>; 5378 type = "passive"; 5379 }; 5380 5381 mdmss3_config1: mdmss3-config1 { 5382 temperature = <105000>; 5383 hysteresis = <3000>; 5384 type = "passive"; 5385 }; 5386 5387 reset-mon-cfg { 5388 temperature = <115000>; 5389 hysteresis = <5000>; 5390 type = "passive"; 5391 }; 5392 }; 5393 }; 5394 5395 camera0-thermal { 5396 polling-delay-passive = <0>; 5397 polling-delay = <0>; 5398 thermal-sensors = <&tsens1 14>; 5399 5400 trips { 5401 thermal-engine-config { 5402 temperature = <125000>; 5403 hysteresis = <1000>; 5404 type = "passive"; 5405 }; 5406 5407 reset-mon-cfg { 5408 temperature = <115000>; 5409 hysteresis = <5000>; 5410 type = "passive"; 5411 }; 5412 }; 5413 }; 5414 5415 camera1-thermal { 5416 polling-delay-passive = <0>; 5417 polling-delay = <0>; 5418 thermal-sensors = <&tsens1 15>; 5419 5420 trips { 5421 thermal-engine-config { 5422 temperature = <125000>; 5423 hysteresis = <1000>; 5424 type = "passive"; 5425 }; 5426 5427 reset-mon-cfg { 5428 temperature = <115000>; 5429 hysteresis = <5000>; 5430 type = "passive"; 5431 }; 5432 }; 5433 }; 5434 }; 5435 5436 timer { 5437 compatible = "arm,armv8-timer"; 5438 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5439 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5440 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5441 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5442 clock-frequency = <19200000>; 5443 }; 5444}; 5445